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mxc nand: remove dead code
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
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34f6e157
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h>
27#include <linux/interrupt.h>
28#include <linux/device.h>
29#include <linux/platform_device.h>
30#include <linux/clk.h>
31#include <linux/err.h>
32#include <linux/io.h>
33
34#include <asm/mach/flash.h>
35#include <mach/mxc_nand.h>
36
37#define DRIVER_NAME "mxc_nand"
38
39/* Addresses for NFC registers */
40#define NFC_BUF_SIZE 0xE00
41#define NFC_BUF_ADDR 0xE04
42#define NFC_FLASH_ADDR 0xE06
43#define NFC_FLASH_CMD 0xE08
44#define NFC_CONFIG 0xE0A
45#define NFC_ECC_STATUS_RESULT 0xE0C
46#define NFC_RSLTMAIN_AREA 0xE0E
47#define NFC_RSLTSPARE_AREA 0xE10
48#define NFC_WRPROT 0xE12
49#define NFC_UNLOCKSTART_BLKADDR 0xE14
50#define NFC_UNLOCKEND_BLKADDR 0xE16
51#define NFC_NF_WRPRST 0xE18
52#define NFC_CONFIG1 0xE1A
53#define NFC_CONFIG2 0xE1C
54
55/* Addresses for NFC RAM BUFFER Main area 0 */
56#define MAIN_AREA0 0x000
57#define MAIN_AREA1 0x200
58#define MAIN_AREA2 0x400
59#define MAIN_AREA3 0x600
60
61/* Addresses for NFC SPARE BUFFER Spare area 0 */
62#define SPARE_AREA0 0x800
63#define SPARE_AREA1 0x810
64#define SPARE_AREA2 0x820
65#define SPARE_AREA3 0x830
66
67/* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
68 * for Command operation */
69#define NFC_CMD 0x1
70
71/* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
72 * for Address operation */
73#define NFC_ADDR 0x2
74
75/* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
76 * for Input operation */
77#define NFC_INPUT 0x4
78
79/* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
80 * for Data Output operation */
81#define NFC_OUTPUT 0x8
82
83/* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
84 * for Read ID operation */
85#define NFC_ID 0x10
86
87/* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
88 * for Read Status operation */
89#define NFC_STATUS 0x20
90
91/* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
92 * Status operation */
93#define NFC_INT 0x8000
94
95#define NFC_SP_EN (1 << 2)
96#define NFC_ECC_EN (1 << 3)
97#define NFC_INT_MSK (1 << 4)
98#define NFC_BIG (1 << 5)
99#define NFC_RST (1 << 6)
100#define NFC_CE (1 << 7)
101#define NFC_ONE_CYCLE (1 << 8)
102
103struct mxc_nand_host {
104 struct mtd_info mtd;
105 struct nand_chip nand;
106 struct mtd_partition *parts;
107 struct device *dev;
108
109 void __iomem *regs;
110 int spare_only;
111 int status_request;
112 int pagesize_2k;
113 uint16_t col_addr;
114 struct clk *clk;
115 int clk_act;
116 int irq;
117
118 wait_queue_head_t irq_waitq;
119};
120
121/* Define delays in microsec for NAND device operations */
122#define TROP_US_DELAY 2000
123/* Macros to get byte and bit positions of ECC */
124#define COLPOS(x) ((x) >> 3)
125#define BITPOS(x) ((x) & 0xf)
126
127/* Define single bit Error positions in Main & Spare area */
128#define MAIN_SINGLEBIT_ERROR 0x4
129#define SPARE_SINGLEBIT_ERROR 0x1
130
131/* OOB placement block for use with hardware ecc generation */
8c1fd89a 132static struct nand_ecclayout nand_hw_eccoob_smallpage = {
34f6e157
SH		 133 .eccbytes = 5,
134 .eccpos = {6, 7, 8, 9, 10},
8c1fd89a 135 .oobfree = {{0, 5}, {12, 4}, }
34f6e157
SH		 136};
137
8c1fd89a 138static struct nand_ecclayout nand_hw_eccoob_largepage = {
bd3fd62e
VB		 139 .eccbytes = 20,
140 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
141 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
142 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
34f6e157
SH		 143};
144
145#ifdef CONFIG_MTD_PARTITIONS
146static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
147#endif
148
149static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
150{
151 struct mxc_nand_host *host = dev_id;
152
153 uint16_t tmp;
154
155 tmp = readw(host->regs + NFC_CONFIG1);
156 tmp |= NFC_INT_MSK; /* Disable interrupt */
157 writew(tmp, host->regs + NFC_CONFIG1);
158
159 wake_up(&host->irq_waitq);
160
161 return IRQ_HANDLED;
162}
163
164/* This function polls the NANDFC to wait for the basic operation to
165 * complete by checking the INT bit of config2 register.
166 */
167static void wait_op_done(struct mxc_nand_host *host, int max_retries,
62465491 168 int useirq)
34f6e157
SH		 169{
170 uint32_t tmp;
171
172 if (useirq) {
173 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
174
175 tmp = readw(host->regs + NFC_CONFIG1);
176 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
177 writew(tmp, host->regs + NFC_CONFIG1);
178
179 wait_event(host->irq_waitq,
180 readw(host->regs + NFC_CONFIG2) & NFC_INT);
181
182 tmp = readw(host->regs + NFC_CONFIG2);
183 tmp &= ~NFC_INT;
184 writew(tmp, host->regs + NFC_CONFIG2);
185 }
186 } else {
187 while (max_retries-- > 0) {
188 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
189 tmp = readw(host->regs + NFC_CONFIG2);
190 tmp &= ~NFC_INT;
191 writew(tmp, host->regs + NFC_CONFIG2);
192 break;
193 }
194 udelay(1);
195 }
43950a60 196 if (max_retries < 0)
62465491
SH		 197 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
198 __func__);
34f6e157
SH		 199 }
200}
201
202/* This function issues the specified command to the NAND device and
203 * waits for completion. */
204static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
205{
206 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
207
208 writew(cmd, host->regs + NFC_FLASH_CMD);
209 writew(NFC_CMD, host->regs + NFC_CONFIG2);
210
211 /* Wait for operation to complete */
62465491 212 wait_op_done(host, TROP_US_DELAY, useirq);
34f6e157
SH		 213}
214
215/* This function sends an address (or partial address) to the
216 * NAND device. The address is used to select the source/destination for
217 * a NAND command. */
218static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
219{
220 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
221
222 writew(addr, host->regs + NFC_FLASH_ADDR);
223 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
224
225 /* Wait for operation to complete */
62465491 226 wait_op_done(host, TROP_US_DELAY, islast);
34f6e157
SH		 227}
228
06ecb04a
SH		 229static void send_page(struct mxc_nand_host *host, uint8_t buf_id,
230 int spare_only, unsigned int ops)
34f6e157 231{
06ecb04a 232 DEBUG(MTD_DEBUG_LEVEL3, "send_page (%d)\n", spare_only);
34f6e157
SH		 233
234 /* NANDFC buffer 0 is used for page read/write */
235 writew(buf_id, host->regs + NFC_BUF_ADDR);
236
237 /* Configure spare or page+spare access */
238 if (!host->pagesize_2k) {
239 uint16_t config1 = readw(host->regs + NFC_CONFIG1);
240 if (spare_only)
241 config1 |= NFC_SP_EN;
242 else
243 config1 &= ~(NFC_SP_EN);
244 writew(config1, host->regs + NFC_CONFIG1);
245 }
246
06ecb04a 247 writew(ops, host->regs + NFC_CONFIG2);
34f6e157
SH		 248
249 /* Wait for operation to complete */
62465491 250 wait_op_done(host, TROP_US_DELAY, true);
34f6e157
SH		 251}
252
253/* Request the NANDFC to perform a read of the NAND device ID. */
254static void send_read_id(struct mxc_nand_host *host)
255{
256 struct nand_chip *this = &host->nand;
257 uint16_t tmp;
258
259 /* NANDFC buffer 0 is used for device ID output */
260 writew(0x0, host->regs + NFC_BUF_ADDR);
261
262 /* Read ID into main buffer */
263 tmp = readw(host->regs + NFC_CONFIG1);
264 tmp &= ~NFC_SP_EN;
265 writew(tmp, host->regs + NFC_CONFIG1);
266
267 writew(NFC_ID, host->regs + NFC_CONFIG2);
268
269 /* Wait for operation to complete */
62465491 270 wait_op_done(host, TROP_US_DELAY, true);
34f6e157
SH		 271
272 if (this->options & NAND_BUSWIDTH_16) {
273 void __iomem *main_buf = host->regs + MAIN_AREA0;
274 /* compress the ID info */
275 writeb(readb(main_buf + 2), main_buf + 1);
276 writeb(readb(main_buf + 4), main_buf + 2);
277 writeb(readb(main_buf + 6), main_buf + 3);
278 writeb(readb(main_buf + 8), main_buf + 4);
279 writeb(readb(main_buf + 10), main_buf + 5);
280 }
281}
282
283/* This function requests the NANDFC to perform a read of the
284 * NAND device status and returns the current status. */
285static uint16_t get_dev_status(struct mxc_nand_host *host)
286{
287 void __iomem *main_buf = host->regs + MAIN_AREA1;
288 uint32_t store;
289 uint16_t ret, tmp;
290 /* Issue status request to NAND device */
291
292 /* store the main area1 first word, later do recovery */
293 store = readl(main_buf);
294 /* NANDFC buffer 1 is used for device status to prevent
295 * corruption of read/write buffer on status requests. */
296 writew(1, host->regs + NFC_BUF_ADDR);
297
298 /* Read status into main buffer */
299 tmp = readw(host->regs + NFC_CONFIG1);
300 tmp &= ~NFC_SP_EN;
301 writew(tmp, host->regs + NFC_CONFIG1);
302
303 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
304
305 /* Wait for operation to complete */
62465491 306 wait_op_done(host, TROP_US_DELAY, true);
34f6e157
SH		 307
308 /* Status is placed in first word of main buffer */
309 /* get status, then recovery area 1 data */
310 ret = readw(main_buf);
311 writel(store, main_buf);
312
313 return ret;
314}
315
316/* This functions is used by upper layer to checks if device is ready */
317static int mxc_nand_dev_ready(struct mtd_info *mtd)
318{
319 /*
320 * NFC handles R/B internally. Therefore, this function
321 * always returns status as ready.
322 */
323 return 1;
324}
325
326static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
327{
328 /*
329 * If HW ECC is enabled, we turn it on during init. There is
330 * no need to enable again here.
331 */
332}
333
334static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
335 u_char *read_ecc, u_char *calc_ecc)
336{
337 struct nand_chip *nand_chip = mtd->priv;
338 struct mxc_nand_host *host = nand_chip->priv;
339
340 /*
341 * 1-Bit errors are automatically corrected in HW. No need for
342 * additional correction. 2-Bit errors cannot be corrected by
343 * HW ECC, so we need to return failure
344 */
345 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
346
347 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
348 DEBUG(MTD_DEBUG_LEVEL0,
349 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
350 return -1;
351 }
352
353 return 0;
354}
355
356static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
357 u_char *ecc_code)
358{
359 return 0;
360}
361
362static u_char mxc_nand_read_byte(struct mtd_info *mtd)
363{
364 struct nand_chip *nand_chip = mtd->priv;
365 struct mxc_nand_host *host = nand_chip->priv;
366 uint8_t ret = 0;
367 uint16_t col, rd_word;
368 uint16_t __iomem *main_buf = host->regs + MAIN_AREA0;
369 uint16_t __iomem *spare_buf = host->regs + SPARE_AREA0;
370
371 /* Check for status request */
372 if (host->status_request)
373 return get_dev_status(host) & 0xFF;
374
375 /* Get column for 16-bit access */
376 col = host->col_addr >> 1;
377
378 /* If we are accessing the spare region */
379 if (host->spare_only)
380 rd_word = readw(&spare_buf[col]);
381 else
382 rd_word = readw(&main_buf[col]);
383
384 /* Pick upper/lower byte of word from RAM buffer */
385 if (host->col_addr & 0x1)
386 ret = (rd_word >> 8) & 0xFF;
387 else
388 ret = rd_word & 0xFF;
389
390 /* Update saved column address */
391 host->col_addr++;
392
393 return ret;
394}
395
396static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
397{
398 struct nand_chip *nand_chip = mtd->priv;
399 struct mxc_nand_host *host = nand_chip->priv;
400 uint16_t col, rd_word, ret;
401 uint16_t __iomem *p;
402
403 DEBUG(MTD_DEBUG_LEVEL3,
404 "mxc_nand_read_word(col = %d)\n", host->col_addr);
405
406 col = host->col_addr;
407 /* Adjust saved column address */
408 if (col < mtd->writesize && host->spare_only)
409 col += mtd->writesize;
410
411 if (col < mtd->writesize)
412 p = (host->regs + MAIN_AREA0) + (col >> 1);
413 else
414 p = (host->regs + SPARE_AREA0) + ((col - mtd->writesize) >> 1);
415
416 if (col & 1) {
417 rd_word = readw(p);
418 ret = (rd_word >> 8) & 0xff;
419 rd_word = readw(&p[1]);
420 ret |= (rd_word << 8) & 0xff00;
421
422 } else
423 ret = readw(p);
424
425 /* Update saved column address */
426 host->col_addr = col + 2;
427
428 return ret;
429}
430
431/* Write data of length len to buffer buf. The data to be
432 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
433 * Operation by the NFC, the data is written to NAND Flash */
434static void mxc_nand_write_buf(struct mtd_info *mtd,
435 const u_char *buf, int len)
436{
437 struct nand_chip *nand_chip = mtd->priv;
438 struct mxc_nand_host *host = nand_chip->priv;
439 int n, col, i = 0;
440
441 DEBUG(MTD_DEBUG_LEVEL3,
442 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
443 len);
444
445 col = host->col_addr;
446
447 /* Adjust saved column address */
448 if (col < mtd->writesize && host->spare_only)
449 col += mtd->writesize;
450
451 n = mtd->writesize + mtd->oobsize - col;
452 n = min(len, n);
453
454 DEBUG(MTD_DEBUG_LEVEL3,
455 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
456
457 while (n) {
458 void __iomem *p;
459
460 if (col < mtd->writesize)
461 p = host->regs + MAIN_AREA0 + (col & ~3);
462 else
463 p = host->regs + SPARE_AREA0 -
464 mtd->writesize + (col & ~3);
465
466 DEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
467 __LINE__, p);
468
469 if (((col | (int)&buf[i]) & 3) || n < 16) {
470 uint32_t data = 0;
471
472 if (col & 3 || n < 4)
473 data = readl(p);
474
475 switch (col & 3) {
476 case 0:
477 if (n) {
478 data = (data & 0xffffff00) |
479 (buf[i++] << 0);
480 n--;
481 col++;
482 }
483 case 1:
484 if (n) {
485 data = (data & 0xffff00ff) |
486 (buf[i++] << 8);
487 n--;
488 col++;
489 }
490 case 2:
491 if (n) {
492 data = (data & 0xff00ffff) |
493 (buf[i++] << 16);
494 n--;
495 col++;
496 }
497 case 3:
498 if (n) {
499 data = (data & 0x00ffffff) |
500 (buf[i++] << 24);
501 n--;
502 col++;
503 }
504 }
505
506 writel(data, p);
507 } else {
508 int m = mtd->writesize - col;
509
510 if (col >= mtd->writesize)
511 m += mtd->oobsize;
512
513 m = min(n, m) & ~3;
514
515 DEBUG(MTD_DEBUG_LEVEL3,
516 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
517 __func__, __LINE__, n, m, i, col);
518
519 memcpy(p, &buf[i], m);
520 col += m;
521 i += m;
522 n -= m;
523 }
524 }
525 /* Update saved column address */
526 host->col_addr = col;
527}
528
529/* Read the data buffer from the NAND Flash. To read the data from NAND
530 * Flash first the data output cycle is initiated by the NFC, which copies
531 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
532 */
533static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
534{
535 struct nand_chip *nand_chip = mtd->priv;
536 struct mxc_nand_host *host = nand_chip->priv;
537 int n, col, i = 0;
538
539 DEBUG(MTD_DEBUG_LEVEL3,
540 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
541
542 col = host->col_addr;
543
544 /* Adjust saved column address */
545 if (col < mtd->writesize && host->spare_only)
546 col += mtd->writesize;
547
548 n = mtd->writesize + mtd->oobsize - col;
549 n = min(len, n);
550
551 while (n) {
552 void __iomem *p;
553
554 if (col < mtd->writesize)
555 p = host->regs + MAIN_AREA0 + (col & ~3);
556 else
557 p = host->regs + SPARE_AREA0 -
558 mtd->writesize + (col & ~3);
559
560 if (((col | (int)&buf[i]) & 3) || n < 16) {
561 uint32_t data;
562
563 data = readl(p);
564 switch (col & 3) {
565 case 0:
566 if (n) {
567 buf[i++] = (uint8_t) (data);
568 n--;
569 col++;
570 }
571 case 1:
572 if (n) {
573 buf[i++] = (uint8_t) (data >> 8);
574 n--;
575 col++;
576 }
577 case 2:
578 if (n) {
579 buf[i++] = (uint8_t) (data >> 16);
580 n--;
581 col++;
582 }
583 case 3:
584 if (n) {
585 buf[i++] = (uint8_t) (data >> 24);
586 n--;
587 col++;
588 }
589 }
590 } else {
591 int m = mtd->writesize - col;
592
593 if (col >= mtd->writesize)
594 m += mtd->oobsize;
595
596 m = min(n, m) & ~3;
597 memcpy(&buf[i], p, m);
598 col += m;
599 i += m;
600 n -= m;
601 }
602 }
603 /* Update saved column address */
604 host->col_addr = col;
605
606}
607
608/* Used by the upper layer to verify the data in NAND Flash
609 * with the data in the buf. */
610static int mxc_nand_verify_buf(struct mtd_info *mtd,
611 const u_char *buf, int len)
612{
613 return -EFAULT;
614}
615
616/* This function is used by upper layer for select and
617 * deselect of the NAND chip */
618static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
619{
620 struct nand_chip *nand_chip = mtd->priv;
621 struct mxc_nand_host *host = nand_chip->priv;
622
34f6e157
SH		 623 switch (chip) {
624 case -1:
625 /* Disable the NFC clock */
626 if (host->clk_act) {
627 clk_disable(host->clk);
628 host->clk_act = 0;
629 }
630 break;
631 case 0:
632 /* Enable the NFC clock */
633 if (!host->clk_act) {
634 clk_enable(host->clk);
635 host->clk_act = 1;
636 }
637 break;
638
639 default:
640 break;
641 }
642}
643
a3e65b64
SH		 644static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
645{
646 struct nand_chip *nand_chip = mtd->priv;
647 struct mxc_nand_host *host = nand_chip->priv;
648
649 /* Write out column address, if necessary */
650 if (column != -1) {
651 /*
652 * MXC NANDFC can only perform full page+spare or
653 * spare-only read/write. When the upper layers
654 * layers perform a read/write buf operation,
655 * we will used the saved column adress to index into
656 * the full page.
657 */
658 send_addr(host, 0, page_addr == -1);
659 if (host->pagesize_2k)
660 /* another col addr cycle for 2k page */
661 send_addr(host, 0, false);
662 }
663
664 /* Write out page address, if necessary */
665 if (page_addr != -1) {
666 /* paddr_0 - p_addr_7 */
667 send_addr(host, (page_addr & 0xff), false);
668
669 if (host->pagesize_2k) {
670 if (mtd->size >= 0x10000000) {
671 /* paddr_8 - paddr_15 */
672 send_addr(host, (page_addr >> 8) & 0xff, false);
673 send_addr(host, (page_addr >> 16) & 0xff, true);
674 } else
675 /* paddr_8 - paddr_15 */
676 send_addr(host, (page_addr >> 8) & 0xff, true);
677 } else {
678 /* One more address cycle for higher density devices */
679 if (mtd->size >= 0x4000000) {
680 /* paddr_8 - paddr_15 */
681 send_addr(host, (page_addr >> 8) & 0xff, false);
682 send_addr(host, (page_addr >> 16) & 0xff, true);
683 } else
684 /* paddr_8 - paddr_15 */
685 send_addr(host, (page_addr >> 8) & 0xff, true);
686 }
687 }
688}
689
34f6e157
SH		 690/* Used by the upper layer to write command to NAND Flash for
691 * different operations to be carried out on NAND Flash */
692static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
693 int column, int page_addr)
694{
695 struct nand_chip *nand_chip = mtd->priv;
696 struct mxc_nand_host *host = nand_chip->priv;
697 int useirq = true;
698
699 DEBUG(MTD_DEBUG_LEVEL3,
700 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
701 command, column, page_addr);
702
703 /* Reset command state information */
704 host->status_request = false;
705
706 /* Command pre-processing step */
707 switch (command) {
708
709 case NAND_CMD_STATUS:
710 host->col_addr = 0;
711 host->status_request = true;
712 break;
713
714 case NAND_CMD_READ0:
715 host->col_addr = column;
716 host->spare_only = false;
717 useirq = false;
718 break;
719
720 case NAND_CMD_READOOB:
721 host->col_addr = column;
722 host->spare_only = true;
723 useirq = false;
724 if (host->pagesize_2k)
725 command = NAND_CMD_READ0; /* only READ0 is valid */
726 break;
727
728 case NAND_CMD_SEQIN:
729 if (column >= mtd->writesize) {
730 /*
731 * FIXME: before send SEQIN command for write OOB,
732 * We must read one page out.
733 * For K9F1GXX has no READ1 command to set current HW
734 * pointer to spare area, we must write the whole page
735 * including OOB together.
736 */
737 if (host->pagesize_2k)
738 /* call ourself to read a page */
739 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
740 page_addr);
741
742 host->col_addr = column - mtd->writesize;
743 host->spare_only = true;
744
745 /* Set program pointer to spare region */
746 if (!host->pagesize_2k)
747 send_cmd(host, NAND_CMD_READOOB, false);
748 } else {
749 host->spare_only = false;
750 host->col_addr = column;
751
752 /* Set program pointer to page start */
753 if (!host->pagesize_2k)
754 send_cmd(host, NAND_CMD_READ0, false);
755 }
756 useirq = false;
757 break;
758
759 case NAND_CMD_PAGEPROG:
06ecb04a 760 send_page(host, 0, host->spare_only, NFC_INPUT);
34f6e157
SH		 761
762 if (host->pagesize_2k) {
763 /* data in 4 areas datas */
06ecb04a
SH		 764 send_page(host, 1, host->spare_only, NFC_INPUT);
765 send_page(host, 2, host->spare_only, NFC_INPUT);
766 send_page(host, 3, host->spare_only, NFC_INPUT);
34f6e157
SH		 767 }
768
769 break;
770
771 case NAND_CMD_ERASE1:
772 useirq = false;
773 break;
774 }
775
776 /* Write out the command to the device. */
777 send_cmd(host, command, useirq);
a3e65b64 778 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 779
780 /* Command post-processing step */
781 switch (command) {
782
783 case NAND_CMD_RESET:
784 break;
785
786 case NAND_CMD_READOOB:
787 case NAND_CMD_READ0:
788 if (host->pagesize_2k) {
789 /* send read confirm command */
790 send_cmd(host, NAND_CMD_READSTART, true);
791 /* read for each AREA */
06ecb04a
SH		 792 send_page(host, 0, host->spare_only, NFC_OUTPUT);
793 send_page(host, 1, host->spare_only, NFC_OUTPUT);
794 send_page(host, 2, host->spare_only, NFC_OUTPUT);
795 send_page(host, 3, host->spare_only, NFC_OUTPUT);
34f6e157 796 } else
06ecb04a 797 send_page(host, 0, host->spare_only, NFC_OUTPUT);
34f6e157
SH		 798 break;
799
800 case NAND_CMD_READID:
8541c118 801 host->col_addr = 0;
34f6e157
SH		 802 send_read_id(host);
803 break;
804
805 case NAND_CMD_PAGEPROG:
806 break;
807
808 case NAND_CMD_STATUS:
809 break;
810
811 case NAND_CMD_ERASE2:
812 break;
813 }
814}
815
816static int __init mxcnd_probe(struct platform_device *pdev)
817{
818 struct nand_chip *this;
819 struct mtd_info *mtd;
820 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
821 struct mxc_nand_host *host;
822 struct resource *res;
823 uint16_t tmp;
824 int err = 0, nr_parts = 0;
825
826 /* Allocate memory for MTD device structure and private data */
827 host = kzalloc(sizeof(struct mxc_nand_host), GFP_KERNEL);
828 if (!host)
829 return -ENOMEM;
830
831 host->dev = &pdev->dev;
832 /* structures must be linked */
833 this = &host->nand;
834 mtd = &host->mtd;
835 mtd->priv = this;
836 mtd->owner = THIS_MODULE;
87f39f04 837 mtd->dev.parent = &pdev->dev;
8541c118 838 mtd->name = "mxc_nand";
34f6e157
SH		 839
840 /* 50 us command delay time */
841 this->chip_delay = 5;
842
843 this->priv = host;
844 this->dev_ready = mxc_nand_dev_ready;
845 this->cmdfunc = mxc_nand_command;
846 this->select_chip = mxc_nand_select_chip;
847 this->read_byte = mxc_nand_read_byte;
848 this->read_word = mxc_nand_read_word;
849 this->write_buf = mxc_nand_write_buf;
850 this->read_buf = mxc_nand_read_buf;
851 this->verify_buf = mxc_nand_verify_buf;
852
e65fb009 853 host->clk = clk_get(&pdev->dev, "nfc");
8541c118
VB		 854 if (IS_ERR(host->clk)) {
855 err = PTR_ERR(host->clk);
34f6e157 856 goto eclk;
8541c118 857 }
34f6e157
SH		 858
859 clk_enable(host->clk);
860 host->clk_act = 1;
861
862 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
863 if (!res) {
864 err = -ENODEV;
865 goto eres;
866 }
867
868 host->regs = ioremap(res->start, res->end - res->start + 1);
869 if (!host->regs) {
8541c118 870 err = -ENOMEM;
34f6e157
SH		 871 goto eres;
872 }
873
874 tmp = readw(host->regs + NFC_CONFIG1);
875 tmp |= NFC_INT_MSK;
876 writew(tmp, host->regs + NFC_CONFIG1);
877
878 init_waitqueue_head(&host->irq_waitq);
879
880 host->irq = platform_get_irq(pdev, 0);
881
882 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
883 if (err)
884 goto eirq;
885
13e1add1
SH		 886 /* Reset NAND */
887 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
888
889 /* preset operation */
890 /* Unlock the internal RAM Buffer */
891 writew(0x2, host->regs + NFC_CONFIG);
892
893 /* Blocks to be unlocked */
894 writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
895 writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
896
897 /* Unlock Block Command for given address range */
898 writew(0x4, host->regs + NFC_WRPROT);
899
900 this->ecc.size = 512;
901 this->ecc.bytes = 3;
902 this->ecc.layout = &nand_hw_eccoob_smallpage;
903
34f6e157
SH		 904 if (pdata->hw_ecc) {
905 this->ecc.calculate = mxc_nand_calculate_ecc;
906 this->ecc.hwctl = mxc_nand_enable_hwecc;
907 this->ecc.correct = mxc_nand_correct_data;
908 this->ecc.mode = NAND_ECC_HW;
34f6e157
SH		 909 tmp = readw(host->regs + NFC_CONFIG1);
910 tmp |= NFC_ECC_EN;
911 writew(tmp, host->regs + NFC_CONFIG1);
912 } else {
34f6e157
SH		 913 this->ecc.mode = NAND_ECC_SOFT;
914 tmp = readw(host->regs + NFC_CONFIG1);
915 tmp &= ~NFC_ECC_EN;
916 writew(tmp, host->regs + NFC_CONFIG1);
917 }
918
34f6e157 919 /* NAND bus width determines access funtions used by upper layer */
13e1add1 920 if (pdata->width == 2)
34f6e157 921 this->options |= NAND_BUSWIDTH_16;
34f6e157 922
bd3fd62e
VB		 923 /* first scan to find the device and get the page size */
924 if (nand_scan_ident(mtd, 1)) {
925 err = -ENXIO;
926 goto escan;
927 }
34f6e157 928
13e1add1
SH		 929 if (mtd->writesize == 2048) {
930 host->pagesize_2k = 1;
931 this->ecc.layout = &nand_hw_eccoob_largepage;
bd3fd62e
VB		 932 }
933
934 /* second phase scan */
935 if (nand_scan_tail(mtd)) {
34f6e157
SH		 936 err = -ENXIO;
937 goto escan;
938 }
939
940 /* Register the partitions */
941#ifdef CONFIG_MTD_PARTITIONS
942 nr_parts =
943 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
944 if (nr_parts > 0)
945 add_mtd_partitions(mtd, host->parts, nr_parts);
946 else
947#endif
948 {
949 pr_info("Registering %s as whole device\n", mtd->name);
950 add_mtd_device(mtd);
951 }
952
953 platform_set_drvdata(pdev, host);
954
955 return 0;
956
957escan:
b258fd8d 958 free_irq(host->irq, host);
34f6e157
SH		 959eirq:
960 iounmap(host->regs);
961eres:
962 clk_put(host->clk);
963eclk:
964 kfree(host);
965
966 return err;
967}
968
82613b0d 969static int __exit mxcnd_remove(struct platform_device *pdev)
34f6e157
SH		 970{
971 struct mxc_nand_host *host = platform_get_drvdata(pdev);
972
973 clk_put(host->clk);
974
975 platform_set_drvdata(pdev, NULL);
976
977 nand_release(&host->mtd);
b258fd8d 978 free_irq(host->irq, host);
34f6e157
SH		 979 iounmap(host->regs);
980 kfree(host);
981
982 return 0;
983}
984
985#ifdef CONFIG_PM
986static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
987{
8541c118
VB		 988 struct mtd_info *mtd = platform_get_drvdata(pdev);
989 struct nand_chip *nand_chip = mtd->priv;
990 struct mxc_nand_host *host = nand_chip->priv;
34f6e157
SH		 991 int ret = 0;
992
993 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
8541c118
VB		 994 if (mtd) {
995 ret = mtd->suspend(mtd);
996 /* Disable the NFC clock */
997 clk_disable(host->clk);
998 }
34f6e157
SH		 999
1000 return ret;
1001}
1002
1003static int mxcnd_resume(struct platform_device *pdev)
1004{
8541c118
VB		 1005 struct mtd_info *mtd = platform_get_drvdata(pdev);
1006 struct nand_chip *nand_chip = mtd->priv;
1007 struct mxc_nand_host *host = nand_chip->priv;
34f6e157
SH		 1008 int ret = 0;
1009
1010 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
34f6e157 1011
8541c118
VB		 1012 if (mtd) {
1013 /* Enable the NFC clock */
1014 clk_enable(host->clk);
1015 mtd->resume(mtd);
1016 }
34f6e157 1017
34f6e157
SH		 1018 return ret;
1019}
1020
1021#else
1022# define mxcnd_suspend NULL
1023# define mxcnd_resume NULL
1024#endif /* CONFIG_PM */
1025
1026static struct platform_driver mxcnd_driver = {
1027 .driver = {
1028 .name = DRIVER_NAME,
1029 },
1030 .remove = __exit_p(mxcnd_remove),
1031 .suspend = mxcnd_suspend,
1032 .resume = mxcnd_resume,
1033};
1034
1035static int __init mxc_nd_init(void)
1036{
8541c118 1037 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
34f6e157
SH		 1038}
1039
1040static void __exit mxc_nd_cleanup(void)
1041{
1042 /* Unregister the device structure */
1043 platform_driver_unregister(&mxcnd_driver);
1044}
1045
1046module_init(mxc_nd_init);
1047module_exit(mxc_nd_cleanup);
1048
1049MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1050MODULE_DESCRIPTION("MXC NAND MTD driver");
1051MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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