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34f6e157 SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/nand.h> | |
26 | #include <linux/mtd/partitions.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/io.h> | |
33 | ||
34 | #include <asm/mach/flash.h> | |
35 | #include <mach/mxc_nand.h> | |
36 | ||
37 | #define DRIVER_NAME "mxc_nand" | |
38 | ||
39 | /* Addresses for NFC registers */ | |
40 | #define NFC_BUF_SIZE 0xE00 | |
41 | #define NFC_BUF_ADDR 0xE04 | |
42 | #define NFC_FLASH_ADDR 0xE06 | |
43 | #define NFC_FLASH_CMD 0xE08 | |
44 | #define NFC_CONFIG 0xE0A | |
45 | #define NFC_ECC_STATUS_RESULT 0xE0C | |
46 | #define NFC_RSLTMAIN_AREA 0xE0E | |
47 | #define NFC_RSLTSPARE_AREA 0xE10 | |
48 | #define NFC_WRPROT 0xE12 | |
49 | #define NFC_UNLOCKSTART_BLKADDR 0xE14 | |
50 | #define NFC_UNLOCKEND_BLKADDR 0xE16 | |
51 | #define NFC_NF_WRPRST 0xE18 | |
52 | #define NFC_CONFIG1 0xE1A | |
53 | #define NFC_CONFIG2 0xE1C | |
54 | ||
34f6e157 SH |
55 | /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register |
56 | * for Command operation */ | |
57 | #define NFC_CMD 0x1 | |
58 | ||
59 | /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register | |
60 | * for Address operation */ | |
61 | #define NFC_ADDR 0x2 | |
62 | ||
63 | /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register | |
64 | * for Input operation */ | |
65 | #define NFC_INPUT 0x4 | |
66 | ||
67 | /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register | |
68 | * for Data Output operation */ | |
69 | #define NFC_OUTPUT 0x8 | |
70 | ||
71 | /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register | |
72 | * for Read ID operation */ | |
73 | #define NFC_ID 0x10 | |
74 | ||
75 | /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register | |
76 | * for Read Status operation */ | |
77 | #define NFC_STATUS 0x20 | |
78 | ||
79 | /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read | |
80 | * Status operation */ | |
81 | #define NFC_INT 0x8000 | |
82 | ||
83 | #define NFC_SP_EN (1 << 2) | |
84 | #define NFC_ECC_EN (1 << 3) | |
85 | #define NFC_INT_MSK (1 << 4) | |
86 | #define NFC_BIG (1 << 5) | |
87 | #define NFC_RST (1 << 6) | |
88 | #define NFC_CE (1 << 7) | |
89 | #define NFC_ONE_CYCLE (1 << 8) | |
90 | ||
91 | struct mxc_nand_host { | |
92 | struct mtd_info mtd; | |
93 | struct nand_chip nand; | |
94 | struct mtd_partition *parts; | |
95 | struct device *dev; | |
96 | ||
c6de7e1b SH |
97 | void *spare0; |
98 | void *main_area0; | |
99 | void *main_area1; | |
100 | ||
101 | void __iomem *base; | |
34f6e157 | 102 | void __iomem *regs; |
34f6e157 SH |
103 | int status_request; |
104 | int pagesize_2k; | |
34f6e157 SH |
105 | struct clk *clk; |
106 | int clk_act; | |
107 | int irq; | |
108 | ||
109 | wait_queue_head_t irq_waitq; | |
f8f9608d SH |
110 | |
111 | uint8_t *data_buf; | |
112 | unsigned int buf_start; | |
113 | int spare_len; | |
34f6e157 SH |
114 | }; |
115 | ||
116 | /* Define delays in microsec for NAND device operations */ | |
117 | #define TROP_US_DELAY 2000 | |
34f6e157 SH |
118 | |
119 | /* OOB placement block for use with hardware ecc generation */ | |
8c1fd89a | 120 | static struct nand_ecclayout nand_hw_eccoob_smallpage = { |
34f6e157 SH |
121 | .eccbytes = 5, |
122 | .eccpos = {6, 7, 8, 9, 10}, | |
8c1fd89a | 123 | .oobfree = {{0, 5}, {12, 4}, } |
34f6e157 SH |
124 | }; |
125 | ||
8c1fd89a | 126 | static struct nand_ecclayout nand_hw_eccoob_largepage = { |
bd3fd62e VB |
127 | .eccbytes = 20, |
128 | .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, | |
129 | 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, | |
130 | .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } | |
34f6e157 SH |
131 | }; |
132 | ||
133 | #ifdef CONFIG_MTD_PARTITIONS | |
134 | static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; | |
135 | #endif | |
136 | ||
137 | static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) | |
138 | { | |
139 | struct mxc_nand_host *host = dev_id; | |
140 | ||
141 | uint16_t tmp; | |
142 | ||
143 | tmp = readw(host->regs + NFC_CONFIG1); | |
144 | tmp |= NFC_INT_MSK; /* Disable interrupt */ | |
145 | writew(tmp, host->regs + NFC_CONFIG1); | |
146 | ||
147 | wake_up(&host->irq_waitq); | |
148 | ||
149 | return IRQ_HANDLED; | |
150 | } | |
151 | ||
152 | /* This function polls the NANDFC to wait for the basic operation to | |
153 | * complete by checking the INT bit of config2 register. | |
154 | */ | |
155 | static void wait_op_done(struct mxc_nand_host *host, int max_retries, | |
62465491 | 156 | int useirq) |
34f6e157 SH |
157 | { |
158 | uint32_t tmp; | |
159 | ||
160 | if (useirq) { | |
161 | if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) { | |
162 | ||
163 | tmp = readw(host->regs + NFC_CONFIG1); | |
164 | tmp &= ~NFC_INT_MSK; /* Enable interrupt */ | |
165 | writew(tmp, host->regs + NFC_CONFIG1); | |
166 | ||
167 | wait_event(host->irq_waitq, | |
168 | readw(host->regs + NFC_CONFIG2) & NFC_INT); | |
169 | ||
170 | tmp = readw(host->regs + NFC_CONFIG2); | |
171 | tmp &= ~NFC_INT; | |
172 | writew(tmp, host->regs + NFC_CONFIG2); | |
173 | } | |
174 | } else { | |
175 | while (max_retries-- > 0) { | |
176 | if (readw(host->regs + NFC_CONFIG2) & NFC_INT) { | |
177 | tmp = readw(host->regs + NFC_CONFIG2); | |
178 | tmp &= ~NFC_INT; | |
179 | writew(tmp, host->regs + NFC_CONFIG2); | |
180 | break; | |
181 | } | |
182 | udelay(1); | |
183 | } | |
43950a60 | 184 | if (max_retries < 0) |
62465491 SH |
185 | DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n", |
186 | __func__); | |
34f6e157 SH |
187 | } |
188 | } | |
189 | ||
190 | /* This function issues the specified command to the NAND device and | |
191 | * waits for completion. */ | |
192 | static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq) | |
193 | { | |
194 | DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq); | |
195 | ||
196 | writew(cmd, host->regs + NFC_FLASH_CMD); | |
197 | writew(NFC_CMD, host->regs + NFC_CONFIG2); | |
198 | ||
199 | /* Wait for operation to complete */ | |
62465491 | 200 | wait_op_done(host, TROP_US_DELAY, useirq); |
34f6e157 SH |
201 | } |
202 | ||
203 | /* This function sends an address (or partial address) to the | |
204 | * NAND device. The address is used to select the source/destination for | |
205 | * a NAND command. */ | |
206 | static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast) | |
207 | { | |
208 | DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast); | |
209 | ||
210 | writew(addr, host->regs + NFC_FLASH_ADDR); | |
211 | writew(NFC_ADDR, host->regs + NFC_CONFIG2); | |
212 | ||
213 | /* Wait for operation to complete */ | |
62465491 | 214 | wait_op_done(host, TROP_US_DELAY, islast); |
34f6e157 SH |
215 | } |
216 | ||
c5d23f1b | 217 | static void send_page(struct mxc_nand_host *host, unsigned int ops) |
34f6e157 | 218 | { |
c5d23f1b | 219 | int bufs, i; |
34f6e157 | 220 | |
c5d23f1b SH |
221 | if (host->pagesize_2k) |
222 | bufs = 4; | |
223 | else | |
224 | bufs = 1; | |
34f6e157 | 225 | |
c5d23f1b SH |
226 | for (i = 0; i < bufs; i++) { |
227 | ||
228 | /* NANDFC buffer 0 is used for page read/write */ | |
229 | writew(i, host->regs + NFC_BUF_ADDR); | |
230 | ||
231 | writew(ops, host->regs + NFC_CONFIG2); | |
232 | ||
233 | /* Wait for operation to complete */ | |
234 | wait_op_done(host, TROP_US_DELAY, true); | |
235 | } | |
34f6e157 SH |
236 | } |
237 | ||
238 | /* Request the NANDFC to perform a read of the NAND device ID. */ | |
239 | static void send_read_id(struct mxc_nand_host *host) | |
240 | { | |
241 | struct nand_chip *this = &host->nand; | |
242 | uint16_t tmp; | |
243 | ||
244 | /* NANDFC buffer 0 is used for device ID output */ | |
245 | writew(0x0, host->regs + NFC_BUF_ADDR); | |
246 | ||
247 | /* Read ID into main buffer */ | |
248 | tmp = readw(host->regs + NFC_CONFIG1); | |
249 | tmp &= ~NFC_SP_EN; | |
250 | writew(tmp, host->regs + NFC_CONFIG1); | |
251 | ||
252 | writew(NFC_ID, host->regs + NFC_CONFIG2); | |
253 | ||
254 | /* Wait for operation to complete */ | |
62465491 | 255 | wait_op_done(host, TROP_US_DELAY, true); |
34f6e157 SH |
256 | |
257 | if (this->options & NAND_BUSWIDTH_16) { | |
c6de7e1b | 258 | void __iomem *main_buf = host->main_area0; |
34f6e157 SH |
259 | /* compress the ID info */ |
260 | writeb(readb(main_buf + 2), main_buf + 1); | |
261 | writeb(readb(main_buf + 4), main_buf + 2); | |
262 | writeb(readb(main_buf + 6), main_buf + 3); | |
263 | writeb(readb(main_buf + 8), main_buf + 4); | |
264 | writeb(readb(main_buf + 10), main_buf + 5); | |
265 | } | |
c6de7e1b | 266 | memcpy(host->data_buf, host->main_area0, 16); |
34f6e157 SH |
267 | } |
268 | ||
269 | /* This function requests the NANDFC to perform a read of the | |
270 | * NAND device status and returns the current status. */ | |
271 | static uint16_t get_dev_status(struct mxc_nand_host *host) | |
272 | { | |
c6de7e1b | 273 | void __iomem *main_buf = host->main_area1; |
34f6e157 SH |
274 | uint32_t store; |
275 | uint16_t ret, tmp; | |
276 | /* Issue status request to NAND device */ | |
277 | ||
278 | /* store the main area1 first word, later do recovery */ | |
279 | store = readl(main_buf); | |
280 | /* NANDFC buffer 1 is used for device status to prevent | |
281 | * corruption of read/write buffer on status requests. */ | |
282 | writew(1, host->regs + NFC_BUF_ADDR); | |
283 | ||
284 | /* Read status into main buffer */ | |
285 | tmp = readw(host->regs + NFC_CONFIG1); | |
286 | tmp &= ~NFC_SP_EN; | |
287 | writew(tmp, host->regs + NFC_CONFIG1); | |
288 | ||
289 | writew(NFC_STATUS, host->regs + NFC_CONFIG2); | |
290 | ||
291 | /* Wait for operation to complete */ | |
62465491 | 292 | wait_op_done(host, TROP_US_DELAY, true); |
34f6e157 SH |
293 | |
294 | /* Status is placed in first word of main buffer */ | |
295 | /* get status, then recovery area 1 data */ | |
296 | ret = readw(main_buf); | |
297 | writel(store, main_buf); | |
298 | ||
299 | return ret; | |
300 | } | |
301 | ||
302 | /* This functions is used by upper layer to checks if device is ready */ | |
303 | static int mxc_nand_dev_ready(struct mtd_info *mtd) | |
304 | { | |
305 | /* | |
306 | * NFC handles R/B internally. Therefore, this function | |
307 | * always returns status as ready. | |
308 | */ | |
309 | return 1; | |
310 | } | |
311 | ||
312 | static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
313 | { | |
314 | /* | |
315 | * If HW ECC is enabled, we turn it on during init. There is | |
316 | * no need to enable again here. | |
317 | */ | |
318 | } | |
319 | ||
320 | static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, | |
321 | u_char *read_ecc, u_char *calc_ecc) | |
322 | { | |
323 | struct nand_chip *nand_chip = mtd->priv; | |
324 | struct mxc_nand_host *host = nand_chip->priv; | |
325 | ||
326 | /* | |
327 | * 1-Bit errors are automatically corrected in HW. No need for | |
328 | * additional correction. 2-Bit errors cannot be corrected by | |
329 | * HW ECC, so we need to return failure | |
330 | */ | |
331 | uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT); | |
332 | ||
333 | if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { | |
334 | DEBUG(MTD_DEBUG_LEVEL0, | |
335 | "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); | |
336 | return -1; | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
343 | u_char *ecc_code) | |
344 | { | |
345 | return 0; | |
346 | } | |
347 | ||
348 | static u_char mxc_nand_read_byte(struct mtd_info *mtd) | |
349 | { | |
350 | struct nand_chip *nand_chip = mtd->priv; | |
351 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 352 | uint8_t ret; |
34f6e157 SH |
353 | |
354 | /* Check for status request */ | |
355 | if (host->status_request) | |
356 | return get_dev_status(host) & 0xFF; | |
357 | ||
f8f9608d SH |
358 | ret = *(uint8_t *)(host->data_buf + host->buf_start); |
359 | host->buf_start++; | |
34f6e157 SH |
360 | |
361 | return ret; | |
362 | } | |
363 | ||
364 | static uint16_t mxc_nand_read_word(struct mtd_info *mtd) | |
365 | { | |
366 | struct nand_chip *nand_chip = mtd->priv; | |
367 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 368 | uint16_t ret; |
34f6e157 | 369 | |
f8f9608d SH |
370 | ret = *(uint16_t *)(host->data_buf + host->buf_start); |
371 | host->buf_start += 2; | |
34f6e157 SH |
372 | |
373 | return ret; | |
374 | } | |
375 | ||
376 | /* Write data of length len to buffer buf. The data to be | |
377 | * written on NAND Flash is first copied to RAMbuffer. After the Data Input | |
378 | * Operation by the NFC, the data is written to NAND Flash */ | |
379 | static void mxc_nand_write_buf(struct mtd_info *mtd, | |
380 | const u_char *buf, int len) | |
381 | { | |
382 | struct nand_chip *nand_chip = mtd->priv; | |
383 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
384 | u16 col = host->buf_start; |
385 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 386 | |
f8f9608d | 387 | n = min(n, len); |
34f6e157 | 388 | |
f8f9608d | 389 | memcpy(host->data_buf + col, buf, n); |
34f6e157 | 390 | |
f8f9608d | 391 | host->buf_start += n; |
34f6e157 SH |
392 | } |
393 | ||
394 | /* Read the data buffer from the NAND Flash. To read the data from NAND | |
395 | * Flash first the data output cycle is initiated by the NFC, which copies | |
396 | * the data to RAMbuffer. This data of length len is then copied to buffer buf. | |
397 | */ | |
398 | static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
399 | { | |
400 | struct nand_chip *nand_chip = mtd->priv; | |
401 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
402 | u16 col = host->buf_start; |
403 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 404 | |
f8f9608d | 405 | n = min(n, len); |
34f6e157 | 406 | |
f8f9608d | 407 | memcpy(buf, host->data_buf + col, len); |
34f6e157 | 408 | |
f8f9608d | 409 | host->buf_start += len; |
34f6e157 SH |
410 | } |
411 | ||
412 | /* Used by the upper layer to verify the data in NAND Flash | |
413 | * with the data in the buf. */ | |
414 | static int mxc_nand_verify_buf(struct mtd_info *mtd, | |
415 | const u_char *buf, int len) | |
416 | { | |
417 | return -EFAULT; | |
418 | } | |
419 | ||
420 | /* This function is used by upper layer for select and | |
421 | * deselect of the NAND chip */ | |
422 | static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) | |
423 | { | |
424 | struct nand_chip *nand_chip = mtd->priv; | |
425 | struct mxc_nand_host *host = nand_chip->priv; | |
426 | ||
34f6e157 SH |
427 | switch (chip) { |
428 | case -1: | |
429 | /* Disable the NFC clock */ | |
430 | if (host->clk_act) { | |
431 | clk_disable(host->clk); | |
432 | host->clk_act = 0; | |
433 | } | |
434 | break; | |
435 | case 0: | |
436 | /* Enable the NFC clock */ | |
437 | if (!host->clk_act) { | |
438 | clk_enable(host->clk); | |
439 | host->clk_act = 1; | |
440 | } | |
441 | break; | |
442 | ||
443 | default: | |
444 | break; | |
445 | } | |
446 | } | |
447 | ||
f8f9608d SH |
448 | /* |
449 | * Function to transfer data to/from spare area. | |
450 | */ | |
451 | static void copy_spare(struct mtd_info *mtd, bool bfrom) | |
452 | { | |
453 | struct nand_chip *this = mtd->priv; | |
454 | struct mxc_nand_host *host = this->priv; | |
455 | u16 i, j; | |
456 | u16 n = mtd->writesize >> 9; | |
457 | u8 *d = host->data_buf + mtd->writesize; | |
c6de7e1b | 458 | u8 *s = host->spare0; |
f8f9608d SH |
459 | u16 t = host->spare_len; |
460 | ||
461 | j = (mtd->oobsize / n >> 1) << 1; | |
462 | ||
463 | if (bfrom) { | |
464 | for (i = 0; i < n - 1; i++) | |
465 | memcpy(d + i * j, s + i * t, j); | |
466 | ||
467 | /* the last section */ | |
468 | memcpy(d + i * j, s + i * t, mtd->oobsize - i * j); | |
469 | } else { | |
470 | for (i = 0; i < n - 1; i++) | |
471 | memcpy(&s[i * t], &d[i * j], j); | |
472 | ||
473 | /* the last section */ | |
474 | memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j); | |
475 | } | |
476 | } | |
477 | ||
a3e65b64 SH |
478 | static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) |
479 | { | |
480 | struct nand_chip *nand_chip = mtd->priv; | |
481 | struct mxc_nand_host *host = nand_chip->priv; | |
482 | ||
483 | /* Write out column address, if necessary */ | |
484 | if (column != -1) { | |
485 | /* | |
486 | * MXC NANDFC can only perform full page+spare or | |
487 | * spare-only read/write. When the upper layers | |
488 | * layers perform a read/write buf operation, | |
489 | * we will used the saved column adress to index into | |
490 | * the full page. | |
491 | */ | |
492 | send_addr(host, 0, page_addr == -1); | |
493 | if (host->pagesize_2k) | |
494 | /* another col addr cycle for 2k page */ | |
495 | send_addr(host, 0, false); | |
496 | } | |
497 | ||
498 | /* Write out page address, if necessary */ | |
499 | if (page_addr != -1) { | |
500 | /* paddr_0 - p_addr_7 */ | |
501 | send_addr(host, (page_addr & 0xff), false); | |
502 | ||
503 | if (host->pagesize_2k) { | |
504 | if (mtd->size >= 0x10000000) { | |
505 | /* paddr_8 - paddr_15 */ | |
506 | send_addr(host, (page_addr >> 8) & 0xff, false); | |
507 | send_addr(host, (page_addr >> 16) & 0xff, true); | |
508 | } else | |
509 | /* paddr_8 - paddr_15 */ | |
510 | send_addr(host, (page_addr >> 8) & 0xff, true); | |
511 | } else { | |
512 | /* One more address cycle for higher density devices */ | |
513 | if (mtd->size >= 0x4000000) { | |
514 | /* paddr_8 - paddr_15 */ | |
515 | send_addr(host, (page_addr >> 8) & 0xff, false); | |
516 | send_addr(host, (page_addr >> 16) & 0xff, true); | |
517 | } else | |
518 | /* paddr_8 - paddr_15 */ | |
519 | send_addr(host, (page_addr >> 8) & 0xff, true); | |
520 | } | |
521 | } | |
522 | } | |
523 | ||
34f6e157 SH |
524 | /* Used by the upper layer to write command to NAND Flash for |
525 | * different operations to be carried out on NAND Flash */ | |
526 | static void mxc_nand_command(struct mtd_info *mtd, unsigned command, | |
527 | int column, int page_addr) | |
528 | { | |
529 | struct nand_chip *nand_chip = mtd->priv; | |
530 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 SH |
531 | |
532 | DEBUG(MTD_DEBUG_LEVEL3, | |
533 | "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", | |
534 | command, column, page_addr); | |
535 | ||
536 | /* Reset command state information */ | |
537 | host->status_request = false; | |
538 | ||
539 | /* Command pre-processing step */ | |
540 | switch (command) { | |
541 | ||
542 | case NAND_CMD_STATUS: | |
f8f9608d | 543 | host->buf_start = 0; |
34f6e157 | 544 | host->status_request = true; |
34f6e157 | 545 | |
89121a6b SH |
546 | send_cmd(host, command, true); |
547 | mxc_do_addr_cycle(mtd, column, page_addr); | |
34f6e157 SH |
548 | break; |
549 | ||
89121a6b | 550 | case NAND_CMD_READ0: |
34f6e157 | 551 | case NAND_CMD_READOOB: |
89121a6b SH |
552 | if (command == NAND_CMD_READ0) |
553 | host->buf_start = column; | |
554 | else | |
555 | host->buf_start = column + mtd->writesize; | |
f8f9608d | 556 | |
34f6e157 SH |
557 | if (host->pagesize_2k) |
558 | command = NAND_CMD_READ0; /* only READ0 is valid */ | |
89121a6b SH |
559 | |
560 | send_cmd(host, command, false); | |
561 | mxc_do_addr_cycle(mtd, column, page_addr); | |
562 | ||
c5d23f1b | 563 | if (host->pagesize_2k) |
89121a6b | 564 | send_cmd(host, NAND_CMD_READSTART, true); |
c5d23f1b SH |
565 | |
566 | send_page(host, NFC_OUTPUT); | |
89121a6b | 567 | |
c6de7e1b | 568 | memcpy(host->data_buf, host->main_area0, mtd->writesize); |
89121a6b | 569 | copy_spare(mtd, true); |
34f6e157 SH |
570 | break; |
571 | ||
572 | case NAND_CMD_SEQIN: | |
573 | if (column >= mtd->writesize) { | |
574 | /* | |
575 | * FIXME: before send SEQIN command for write OOB, | |
576 | * We must read one page out. | |
577 | * For K9F1GXX has no READ1 command to set current HW | |
578 | * pointer to spare area, we must write the whole page | |
579 | * including OOB together. | |
580 | */ | |
581 | if (host->pagesize_2k) | |
582 | /* call ourself to read a page */ | |
583 | mxc_nand_command(mtd, NAND_CMD_READ0, 0, | |
584 | page_addr); | |
585 | ||
f8f9608d | 586 | host->buf_start = column; |
34f6e157 SH |
587 | |
588 | /* Set program pointer to spare region */ | |
589 | if (!host->pagesize_2k) | |
590 | send_cmd(host, NAND_CMD_READOOB, false); | |
591 | } else { | |
f8f9608d | 592 | host->buf_start = column; |
34f6e157 SH |
593 | |
594 | /* Set program pointer to page start */ | |
595 | if (!host->pagesize_2k) | |
596 | send_cmd(host, NAND_CMD_READ0, false); | |
597 | } | |
89121a6b SH |
598 | |
599 | send_cmd(host, command, false); | |
600 | mxc_do_addr_cycle(mtd, column, page_addr); | |
34f6e157 SH |
601 | break; |
602 | ||
603 | case NAND_CMD_PAGEPROG: | |
c6de7e1b | 604 | memcpy(host->main_area0, host->data_buf, mtd->writesize); |
f8f9608d | 605 | copy_spare(mtd, false); |
c5d23f1b | 606 | send_page(host, NFC_INPUT); |
89121a6b SH |
607 | send_cmd(host, command, true); |
608 | mxc_do_addr_cycle(mtd, column, page_addr); | |
34f6e157 SH |
609 | break; |
610 | ||
611 | case NAND_CMD_READID: | |
89121a6b SH |
612 | send_cmd(host, command, true); |
613 | mxc_do_addr_cycle(mtd, column, page_addr); | |
34f6e157 SH |
614 | send_read_id(host); |
615 | break; | |
616 | ||
89121a6b | 617 | case NAND_CMD_ERASE1: |
34f6e157 | 618 | case NAND_CMD_ERASE2: |
89121a6b SH |
619 | send_cmd(host, command, false); |
620 | mxc_do_addr_cycle(mtd, column, page_addr); | |
621 | ||
34f6e157 SH |
622 | break; |
623 | } | |
624 | } | |
625 | ||
626 | static int __init mxcnd_probe(struct platform_device *pdev) | |
627 | { | |
628 | struct nand_chip *this; | |
629 | struct mtd_info *mtd; | |
630 | struct mxc_nand_platform_data *pdata = pdev->dev.platform_data; | |
631 | struct mxc_nand_host *host; | |
632 | struct resource *res; | |
633 | uint16_t tmp; | |
634 | int err = 0, nr_parts = 0; | |
635 | ||
636 | /* Allocate memory for MTD device structure and private data */ | |
f8f9608d SH |
637 | host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE + |
638 | NAND_MAX_OOBSIZE, GFP_KERNEL); | |
34f6e157 SH |
639 | if (!host) |
640 | return -ENOMEM; | |
641 | ||
f8f9608d SH |
642 | host->data_buf = (uint8_t *)(host + 1); |
643 | host->spare_len = 16; | |
644 | ||
34f6e157 SH |
645 | host->dev = &pdev->dev; |
646 | /* structures must be linked */ | |
647 | this = &host->nand; | |
648 | mtd = &host->mtd; | |
649 | mtd->priv = this; | |
650 | mtd->owner = THIS_MODULE; | |
87f39f04 | 651 | mtd->dev.parent = &pdev->dev; |
8541c118 | 652 | mtd->name = "mxc_nand"; |
34f6e157 SH |
653 | |
654 | /* 50 us command delay time */ | |
655 | this->chip_delay = 5; | |
656 | ||
657 | this->priv = host; | |
658 | this->dev_ready = mxc_nand_dev_ready; | |
659 | this->cmdfunc = mxc_nand_command; | |
660 | this->select_chip = mxc_nand_select_chip; | |
661 | this->read_byte = mxc_nand_read_byte; | |
662 | this->read_word = mxc_nand_read_word; | |
663 | this->write_buf = mxc_nand_write_buf; | |
664 | this->read_buf = mxc_nand_read_buf; | |
665 | this->verify_buf = mxc_nand_verify_buf; | |
666 | ||
e65fb009 | 667 | host->clk = clk_get(&pdev->dev, "nfc"); |
8541c118 VB |
668 | if (IS_ERR(host->clk)) { |
669 | err = PTR_ERR(host->clk); | |
34f6e157 | 670 | goto eclk; |
8541c118 | 671 | } |
34f6e157 SH |
672 | |
673 | clk_enable(host->clk); | |
674 | host->clk_act = 1; | |
675 | ||
676 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
677 | if (!res) { | |
678 | err = -ENODEV; | |
679 | goto eres; | |
680 | } | |
681 | ||
c6de7e1b SH |
682 | host->base = ioremap(res->start, resource_size(res)); |
683 | if (!host->base) { | |
8541c118 | 684 | err = -ENOMEM; |
34f6e157 SH |
685 | goto eres; |
686 | } | |
687 | ||
c6de7e1b SH |
688 | host->regs = host->base; |
689 | host->main_area0 = host->base; | |
690 | host->main_area1 = host->base + 0x200; | |
691 | host->spare0 = host->base + 0x800; | |
692 | ||
34f6e157 SH |
693 | tmp = readw(host->regs + NFC_CONFIG1); |
694 | tmp |= NFC_INT_MSK; | |
695 | writew(tmp, host->regs + NFC_CONFIG1); | |
696 | ||
697 | init_waitqueue_head(&host->irq_waitq); | |
698 | ||
699 | host->irq = platform_get_irq(pdev, 0); | |
700 | ||
701 | err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host); | |
702 | if (err) | |
703 | goto eirq; | |
704 | ||
13e1add1 SH |
705 | /* Reset NAND */ |
706 | this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
707 | ||
708 | /* preset operation */ | |
709 | /* Unlock the internal RAM Buffer */ | |
710 | writew(0x2, host->regs + NFC_CONFIG); | |
711 | ||
712 | /* Blocks to be unlocked */ | |
713 | writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR); | |
714 | writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR); | |
715 | ||
716 | /* Unlock Block Command for given address range */ | |
717 | writew(0x4, host->regs + NFC_WRPROT); | |
718 | ||
719 | this->ecc.size = 512; | |
720 | this->ecc.bytes = 3; | |
721 | this->ecc.layout = &nand_hw_eccoob_smallpage; | |
722 | ||
34f6e157 SH |
723 | if (pdata->hw_ecc) { |
724 | this->ecc.calculate = mxc_nand_calculate_ecc; | |
725 | this->ecc.hwctl = mxc_nand_enable_hwecc; | |
726 | this->ecc.correct = mxc_nand_correct_data; | |
727 | this->ecc.mode = NAND_ECC_HW; | |
34f6e157 SH |
728 | tmp = readw(host->regs + NFC_CONFIG1); |
729 | tmp |= NFC_ECC_EN; | |
730 | writew(tmp, host->regs + NFC_CONFIG1); | |
731 | } else { | |
34f6e157 SH |
732 | this->ecc.mode = NAND_ECC_SOFT; |
733 | tmp = readw(host->regs + NFC_CONFIG1); | |
734 | tmp &= ~NFC_ECC_EN; | |
735 | writew(tmp, host->regs + NFC_CONFIG1); | |
736 | } | |
737 | ||
34f6e157 | 738 | /* NAND bus width determines access funtions used by upper layer */ |
13e1add1 | 739 | if (pdata->width == 2) |
34f6e157 | 740 | this->options |= NAND_BUSWIDTH_16; |
34f6e157 | 741 | |
bd3fd62e VB |
742 | /* first scan to find the device and get the page size */ |
743 | if (nand_scan_ident(mtd, 1)) { | |
744 | err = -ENXIO; | |
745 | goto escan; | |
746 | } | |
34f6e157 | 747 | |
13e1add1 SH |
748 | if (mtd->writesize == 2048) { |
749 | host->pagesize_2k = 1; | |
750 | this->ecc.layout = &nand_hw_eccoob_largepage; | |
bd3fd62e VB |
751 | } |
752 | ||
753 | /* second phase scan */ | |
754 | if (nand_scan_tail(mtd)) { | |
34f6e157 SH |
755 | err = -ENXIO; |
756 | goto escan; | |
757 | } | |
758 | ||
759 | /* Register the partitions */ | |
760 | #ifdef CONFIG_MTD_PARTITIONS | |
761 | nr_parts = | |
762 | parse_mtd_partitions(mtd, part_probes, &host->parts, 0); | |
763 | if (nr_parts > 0) | |
764 | add_mtd_partitions(mtd, host->parts, nr_parts); | |
765 | else | |
766 | #endif | |
767 | { | |
768 | pr_info("Registering %s as whole device\n", mtd->name); | |
769 | add_mtd_device(mtd); | |
770 | } | |
771 | ||
772 | platform_set_drvdata(pdev, host); | |
773 | ||
774 | return 0; | |
775 | ||
776 | escan: | |
b258fd8d | 777 | free_irq(host->irq, host); |
34f6e157 | 778 | eirq: |
c6de7e1b | 779 | iounmap(host->base); |
34f6e157 SH |
780 | eres: |
781 | clk_put(host->clk); | |
782 | eclk: | |
783 | kfree(host); | |
784 | ||
785 | return err; | |
786 | } | |
787 | ||
82613b0d | 788 | static int __exit mxcnd_remove(struct platform_device *pdev) |
34f6e157 SH |
789 | { |
790 | struct mxc_nand_host *host = platform_get_drvdata(pdev); | |
791 | ||
792 | clk_put(host->clk); | |
793 | ||
794 | platform_set_drvdata(pdev, NULL); | |
795 | ||
796 | nand_release(&host->mtd); | |
b258fd8d | 797 | free_irq(host->irq, host); |
c6de7e1b | 798 | iounmap(host->base); |
34f6e157 SH |
799 | kfree(host); |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
804 | #ifdef CONFIG_PM | |
805 | static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state) | |
806 | { | |
8541c118 VB |
807 | struct mtd_info *mtd = platform_get_drvdata(pdev); |
808 | struct nand_chip *nand_chip = mtd->priv; | |
809 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 SH |
810 | int ret = 0; |
811 | ||
812 | DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n"); | |
8541c118 VB |
813 | if (mtd) { |
814 | ret = mtd->suspend(mtd); | |
815 | /* Disable the NFC clock */ | |
816 | clk_disable(host->clk); | |
817 | } | |
34f6e157 SH |
818 | |
819 | return ret; | |
820 | } | |
821 | ||
822 | static int mxcnd_resume(struct platform_device *pdev) | |
823 | { | |
8541c118 VB |
824 | struct mtd_info *mtd = platform_get_drvdata(pdev); |
825 | struct nand_chip *nand_chip = mtd->priv; | |
826 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 SH |
827 | int ret = 0; |
828 | ||
829 | DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n"); | |
34f6e157 | 830 | |
8541c118 VB |
831 | if (mtd) { |
832 | /* Enable the NFC clock */ | |
833 | clk_enable(host->clk); | |
834 | mtd->resume(mtd); | |
835 | } | |
34f6e157 | 836 | |
34f6e157 SH |
837 | return ret; |
838 | } | |
839 | ||
840 | #else | |
841 | # define mxcnd_suspend NULL | |
842 | # define mxcnd_resume NULL | |
843 | #endif /* CONFIG_PM */ | |
844 | ||
845 | static struct platform_driver mxcnd_driver = { | |
846 | .driver = { | |
847 | .name = DRIVER_NAME, | |
848 | }, | |
849 | .remove = __exit_p(mxcnd_remove), | |
850 | .suspend = mxcnd_suspend, | |
851 | .resume = mxcnd_resume, | |
852 | }; | |
853 | ||
854 | static int __init mxc_nd_init(void) | |
855 | { | |
8541c118 | 856 | return platform_driver_probe(&mxcnd_driver, mxcnd_probe); |
34f6e157 SH |
857 | } |
858 | ||
859 | static void __exit mxc_nd_cleanup(void) | |
860 | { | |
861 | /* Unregister the device structure */ | |
862 | platform_driver_unregister(&mxcnd_driver); | |
863 | } | |
864 | ||
865 | module_init(mxc_nd_init); | |
866 | module_exit(mxc_nd_cleanup); | |
867 | ||
868 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
869 | MODULE_DESCRIPTION("MXC NAND MTD driver"); | |
870 | MODULE_LICENSE("GPL"); |