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mtd: mxc-nand: Add a timeout when waiting for interrupt
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
CommitLineData
34f6e157
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h>
27#include <linux/interrupt.h>
28#include <linux/device.h>
29#include <linux/platform_device.h>
30#include <linux/clk.h>
31#include <linux/err.h>
32#include <linux/io.h>
63f1474c
SH		 33#include <linux/irq.h>
34#include <linux/completion.h>
d367e37e 35#include <linux/of.h>
6436356b
UKK		 36#include <linux/of_device.h>
37#include <linux/of_mtd.h>
34f6e157
SH		 38
39#include <asm/mach/flash.h>
82906b13 40#include <linux/platform_data/mtd-mxc_nand.h>
34f6e157
SH		 41
42#define DRIVER_NAME "mxc_nand"
43
44/* Addresses for NFC registers */
1bc99180
SH		 45#define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
46#define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
47#define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
48#define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
49#define NFC_V1_V2_CONFIG (host->regs + 0x0a)
50#define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
51#define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
52#define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
53#define NFC_V1_V2_WRPROT (host->regs + 0x12)
54#define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
55#define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
d178e3e8
BS		 56#define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
57#define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
58#define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
59#define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
60#define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
61#define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
62#define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
63#define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
1bc99180
SH		 64#define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
65#define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
66#define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
67
6e85dfdc 68#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
1bc99180
SH		 69#define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
70#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
71#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
72#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
73#define NFC_V1_V2_CONFIG1_RST (1 << 6)
74#define NFC_V1_V2_CONFIG1_CE (1 << 7)
b8db2f51
SH		 75#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
76#define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
77#define NFC_V2_CONFIG1_FP_INT (1 << 11)
1bc99180
SH		 78
79#define NFC_V1_V2_CONFIG2_INT (1 << 15)
80
81/*
82 * Operation modes for the NFC. Valid for v1, v2 and v3
83 * type controllers.
84 */
85#define NFC_CMD (1 << 0)
86#define NFC_ADDR (1 << 1)
87#define NFC_INPUT (1 << 2)
88#define NFC_OUTPUT (1 << 3)
89#define NFC_ID (1 << 4)
90#define NFC_STATUS (1 << 5)
34f6e157 91
71ec5155
SH		 92#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
93#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
94
95#define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
96#define NFC_V3_CONFIG1_SP_EN (1 << 0)
97#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
98
99#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
100
101#define NFC_V3_LAUNCH (host->regs_axi + 0x40)
102
103#define NFC_V3_WRPROT (host->regs_ip + 0x0)
104#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
105#define NFC_V3_WRPROT_LOCK (1 << 1)
106#define NFC_V3_WRPROT_UNLOCK (1 << 2)
107#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
108
109#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
110
111#define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
112#define NFC_V3_CONFIG2_PS_512 (0 << 0)
113#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
114#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
115#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
116#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
117#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
118#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
119#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
71718a8e 120#define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
71ec5155
SH		 121#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
122#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
123#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
124#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
125
126#define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
127#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
128#define NFC_V3_CONFIG3_FW8 (1 << 3)
129#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
130#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
131#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
132#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
133
134#define NFC_V3_IPC (host->regs_ip + 0x2C)
135#define NFC_V3_IPC_CREQ (1 << 0)
136#define NFC_V3_IPC_INT (1 << 31)
137
138#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
34f6e157 139
e4303b25
UKK		 140struct mxc_nand_host;
141
142struct mxc_nand_devtype_data {
143 void (*preset)(struct mtd_info *);
144 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
145 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
146 void (*send_page)(struct mtd_info *, unsigned int);
147 void (*send_read_id)(struct mxc_nand_host *);
148 uint16_t (*get_dev_status)(struct mxc_nand_host *);
149 int (*check_int)(struct mxc_nand_host *);
150 void (*irq_control)(struct mxc_nand_host *, int);
6d38af25 151 u32 (*get_ecc_status)(struct mxc_nand_host *);
6dcdf99d 152 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
5e05a2d6 153 void (*select_chip)(struct mtd_info *mtd, int chip);
69d023be
UKK		 154 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
155 u_char *read_ecc, u_char *calc_ecc);
f48d0f9a
UKK		 156
157 /*
158 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
159 * (CONFIG1:INT_MSK is set). To handle this the driver uses
160 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
161 */
162 int irqpending_quirk;
163 int needs_ip;
164
165 size_t regs_offset;
166 size_t spare0_offset;
167 size_t axi_offset;
168
169 int spare_len;
170 int eccbytes;
171 int eccsize;
71718a8e 172 int ppb_shift;
e4303b25
UKK		 173};
174
34f6e157
SH		 175struct mxc_nand_host {
176 struct mtd_info mtd;
177 struct nand_chip nand;
34f6e157
SH		 178 struct device *dev;
179
4b6f05e1
UKK		 180 void __iomem *spare0;
181 void __iomem *main_area0;
c6de7e1b
SH		 182
183 void __iomem *base;
34f6e157 184 void __iomem *regs;
71ec5155
SH		 185 void __iomem *regs_axi;
186 void __iomem *regs_ip;
34f6e157 187 int status_request;
34f6e157
SH		 188 struct clk *clk;
189 int clk_act;
190 int irq;
94f77e50 191 int eccsize;
d178e3e8 192 int active_cs;
34f6e157 193
63f1474c 194 struct completion op_completion;
34f6e157 195
f8f9608d
SH		 196 uint8_t *data_buf;
197 unsigned int buf_start;
5f97304e 198
e4303b25 199 const struct mxc_nand_devtype_data *devtype_data;
6436356b 200 struct mxc_nand_platform_data pdata;
34f6e157
SH		 201};
202
34f6e157 203/* OOB placement block for use with hardware ecc generation */
9467114e 204static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
34f6e157
SH		 205 .eccbytes = 5,
206 .eccpos = {6, 7, 8, 9, 10},
8c1fd89a 207 .oobfree = {{0, 5}, {12, 4}, }
bd3fd62e
VB		 208};
209
9467114e 210static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
bd3fd62e
VB		 211 .eccbytes = 20,
212 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
213 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
214 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
34f6e157
SH		 215};
216
9467114e
SH		 217/* OOB description for 512 byte pages with 16 byte OOB */
218static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
219 .eccbytes = 1 * 9,
220 .eccpos = {
221 7, 8, 9, 10, 11, 12, 13, 14, 15
222 },
223 .oobfree = {
224 {.offset = 0, .length = 5}
225 }
226};
227
228/* OOB description for 2048 byte pages with 64 byte OOB */
229static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
230 .eccbytes = 4 * 9,
231 .eccpos = {
232 7, 8, 9, 10, 11, 12, 13, 14, 15,
233 23, 24, 25, 26, 27, 28, 29, 30, 31,
234 39, 40, 41, 42, 43, 44, 45, 46, 47,
235 55, 56, 57, 58, 59, 60, 61, 62, 63
236 },
237 .oobfree = {
238 {.offset = 2, .length = 4},
239 {.offset = 16, .length = 7},
240 {.offset = 32, .length = 7},
241 {.offset = 48, .length = 7}
242 }
243};
244
2c1c5f19
BS		 245/* OOB description for 4096 byte pages with 128 byte OOB */
246static struct nand_ecclayout nandv2_hw_eccoob_4k = {
247 .eccbytes = 8 * 9,
248 .eccpos = {
249 7, 8, 9, 10, 11, 12, 13, 14, 15,
250 23, 24, 25, 26, 27, 28, 29, 30, 31,
251 39, 40, 41, 42, 43, 44, 45, 46, 47,
252 55, 56, 57, 58, 59, 60, 61, 62, 63,
253 71, 72, 73, 74, 75, 76, 77, 78, 79,
254 87, 88, 89, 90, 91, 92, 93, 94, 95,
255 103, 104, 105, 106, 107, 108, 109, 110, 111,
256 119, 120, 121, 122, 123, 124, 125, 126, 127,
257 },
258 .oobfree = {
259 {.offset = 2, .length = 4},
260 {.offset = 16, .length = 7},
261 {.offset = 32, .length = 7},
262 {.offset = 48, .length = 7},
263 {.offset = 64, .length = 7},
264 {.offset = 80, .length = 7},
265 {.offset = 96, .length = 7},
266 {.offset = 112, .length = 7},
267 }
268};
269
b2ac0376 270static const char * const part_probes[] = {
740bb0c4 271 "cmdlinepart", "RedBoot", "ofpart", NULL };
34f6e157 272
096bcc23
SH		 273static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
274{
275 int i;
276 u32 *t = trg;
277 const __iomem u32 *s = src;
278
279 for (i = 0; i < (size >> 2); i++)
280 *t++ = __raw_readl(s++);
281}
282
33a87a15 283static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
096bcc23 284{
33a87a15
KV		 285 /* __iowrite32_copy use 32bit size values so divide by 4 */
286 __iowrite32_copy(trg, src, size / 4);
096bcc23
SH		 287}
288
71ec5155
SH		 289static int check_int_v3(struct mxc_nand_host *host)
290{
291 uint32_t tmp;
292
293 tmp = readl(NFC_V3_IPC);
294 if (!(tmp & NFC_V3_IPC_INT))
295 return 0;
296
297 tmp &= ~NFC_V3_IPC_INT;
298 writel(tmp, NFC_V3_IPC);
299
300 return 1;
301}
302
7aaf28ac
SH		 303static int check_int_v1_v2(struct mxc_nand_host *host)
304{
305 uint32_t tmp;
306
1bc99180
SH		 307 tmp = readw(NFC_V1_V2_CONFIG2);
308 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
7aaf28ac
SH		 309 return 0;
310
f48d0f9a 311 if (!host->devtype_data->irqpending_quirk)
63f1474c 312 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
7aaf28ac
SH		 313
314 return 1;
315}
316
63f1474c
SH		 317static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
318{
319 uint16_t tmp;
320
321 tmp = readw(NFC_V1_V2_CONFIG1);
322
323 if (activate)
324 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
325 else
326 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
327
328 writew(tmp, NFC_V1_V2_CONFIG1);
329}
330
331static void irq_control_v3(struct mxc_nand_host *host, int activate)
332{
333 uint32_t tmp;
334
335 tmp = readl(NFC_V3_CONFIG2);
336
337 if (activate)
338 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
339 else
340 tmp |= NFC_V3_CONFIG2_INT_MSK;
341
342 writel(tmp, NFC_V3_CONFIG2);
343}
344
8556958a
UKK		 345static void irq_control(struct mxc_nand_host *host, int activate)
346{
f48d0f9a 347 if (host->devtype_data->irqpending_quirk) {
8556958a
UKK		 348 if (activate)
349 enable_irq(host->irq);
350 else
351 disable_irq_nosync(host->irq);
352 } else {
e4303b25 353 host->devtype_data->irq_control(host, activate);
8556958a
UKK		 354 }
355}
356
6d38af25
UKK		 357static u32 get_ecc_status_v1(struct mxc_nand_host *host)
358{
359 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
360}
361
362static u32 get_ecc_status_v2(struct mxc_nand_host *host)
363{
364 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
365}
366
367static u32 get_ecc_status_v3(struct mxc_nand_host *host)
368{
369 return readl(NFC_V3_ECC_STATUS_RESULT);
370}
371
8556958a
UKK		 372static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
373{
374 struct mxc_nand_host *host = dev_id;
375
e4303b25 376 if (!host->devtype_data->check_int(host))
8556958a
UKK		 377 return IRQ_NONE;
378
379 irq_control(host, 0);
380
381 complete(&host->op_completion);
382
383 return IRQ_HANDLED;
384}
385
34f6e157
SH		 386/* This function polls the NANDFC to wait for the basic operation to
387 * complete by checking the INT bit of config2 register.
388 */
e35d1d8a 389static int wait_op_done(struct mxc_nand_host *host, int useirq)
34f6e157 390{
e35d1d8a
UKK		 391 int ret = 0;
392
393 /*
394 * If operation is already complete, don't bother to setup an irq or a
395 * loop.
396 */
397 if (host->devtype_data->check_int(host))
398 return 0;
34f6e157
SH		 399
400 if (useirq) {
e35d1d8a
UKK		 401 unsigned long timeout;
402
403 reinit_completion(&host->op_completion);
404
405 irq_control(host, 1);
406
407 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
408 if (!timeout && !host->devtype_data->check_int(host)) {
409 dev_dbg(host->dev, "timeout waiting for irq\n");
410 ret = -ETIMEDOUT;
34f6e157
SH		 411 }
412 } else {
e35d1d8a
UKK		 413 int max_retries = 8000;
414 int done;
7aaf28ac 415
e35d1d8a 416 do {
34f6e157 417 udelay(1);
e35d1d8a
UKK		 418
419 done = host->devtype_data->check_int(host);
420 if (done)
421 break;
422
423 } while (--max_retries);
424
425 if (!done) {
426 dev_dbg(host->dev, "timeout polling for completion\n");
427 ret = -ETIMEDOUT;
34f6e157 428 }
34f6e157 429 }
e35d1d8a
UKK		 430
431 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
432
433 return ret;
34f6e157
SH		 434}
435
71ec5155
SH		 436static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
437{
438 /* fill command */
439 writel(cmd, NFC_V3_FLASH_CMD);
440
441 /* send out command */
442 writel(NFC_CMD, NFC_V3_LAUNCH);
443
444 /* Wait for operation to complete */
445 wait_op_done(host, useirq);
446}
447
34f6e157
SH		 448/* This function issues the specified command to the NAND device and
449 * waits for completion. */
5f97304e 450static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
34f6e157 451{
289c0522 452 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
34f6e157 453
1bc99180
SH		 454 writew(cmd, NFC_V1_V2_FLASH_CMD);
455 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
34f6e157 456
f48d0f9a 457 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
a47bfd2e
IC		 458 int max_retries = 100;
459 /* Reset completion is indicated by NFC_CONFIG2 */
460 /* being set to 0 */
461 while (max_retries-- > 0) {
1bc99180 462 if (readw(NFC_V1_V2_CONFIG2) == 0) {
a47bfd2e
IC		 463 break;
464 }
465 udelay(1);
466 }
467 if (max_retries < 0)
0a32a102 468 pr_debug("%s: RESET failed\n", __func__);
a47bfd2e
IC		 469 } else {
470 /* Wait for operation to complete */
471 wait_op_done(host, useirq);
472 }
34f6e157
SH		 473}
474
71ec5155
SH		 475static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
476{
477 /* fill address */
478 writel(addr, NFC_V3_FLASH_ADDR0);
479
480 /* send out address */
481 writel(NFC_ADDR, NFC_V3_LAUNCH);
482
483 wait_op_done(host, 0);
484}
485
34f6e157
SH		 486/* This function sends an address (or partial address) to the
487 * NAND device. The address is used to select the source/destination for
488 * a NAND command. */
5f97304e 489static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
34f6e157 490{
289c0522 491 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
34f6e157 492
1bc99180
SH		 493 writew(addr, NFC_V1_V2_FLASH_ADDR);
494 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
34f6e157
SH		 495
496 /* Wait for operation to complete */
c110eaf4 497 wait_op_done(host, islast);
34f6e157
SH		 498}
499
71ec5155
SH		 500static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
501{
502 struct nand_chip *nand_chip = mtd->priv;
503 struct mxc_nand_host *host = nand_chip->priv;
504 uint32_t tmp;
505
506 tmp = readl(NFC_V3_CONFIG1);
507 tmp &= ~(7 << 4);
508 writel(tmp, NFC_V3_CONFIG1);
509
510 /* transfer data from NFC ram to nand */
511 writel(ops, NFC_V3_LAUNCH);
512
513 wait_op_done(host, false);
514}
515
6d38af25
UKK		 516static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
517{
518 struct nand_chip *nand_chip = mtd->priv;
519 struct mxc_nand_host *host = nand_chip->priv;
520
521 /* NANDFC buffer 0 is used for page read/write */
522 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
523
524 writew(ops, NFC_V1_V2_CONFIG2);
525
526 /* Wait for operation to complete */
527 wait_op_done(host, true);
528}
529
530static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
34f6e157 531{
2d69c7fa
SH		 532 struct nand_chip *nand_chip = mtd->priv;
533 struct mxc_nand_host *host = nand_chip->priv;
c5d23f1b 534 int bufs, i;
34f6e157 535
6d38af25 536 if (mtd->writesize > 512)
c5d23f1b
SH		 537 bufs = 4;
538 else
539 bufs = 1;
34f6e157 540
c5d23f1b 541 for (i = 0; i < bufs; i++) {
34f6e157 542
c5d23f1b 543 /* NANDFC buffer 0 is used for page read/write */
d178e3e8 544 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
34f6e157 545
1bc99180 546 writew(ops, NFC_V1_V2_CONFIG2);
34f6e157 547
c5d23f1b 548 /* Wait for operation to complete */
c110eaf4 549 wait_op_done(host, true);
34f6e157 550 }
34f6e157
SH		 551}
552
71ec5155
SH		 553static void send_read_id_v3(struct mxc_nand_host *host)
554{
a8459f21
RS		 555 struct nand_chip *this = &host->nand;
556
71ec5155
SH		 557 /* Read ID into main buffer */
558 writel(NFC_ID, NFC_V3_LAUNCH);
559
560 wait_op_done(host, true);
561
096bcc23 562 memcpy32_fromio(host->data_buf, host->main_area0, 16);
a8459f21
RS		 563
564 if (this->options & NAND_BUSWIDTH_16) {
565 /* compress the ID info */
566 host->data_buf[1] = host->data_buf[2];
567 host->data_buf[2] = host->data_buf[4];
568 host->data_buf[3] = host->data_buf[6];
569 host->data_buf[4] = host->data_buf[8];
570 host->data_buf[5] = host->data_buf[10];
571 }
71ec5155
SH		 572}
573
34f6e157 574/* Request the NANDFC to perform a read of the NAND device ID. */
5f97304e 575static void send_read_id_v1_v2(struct mxc_nand_host *host)
34f6e157
SH		 576{
577 struct nand_chip *this = &host->nand;
34f6e157
SH		 578
579 /* NANDFC buffer 0 is used for device ID output */
d178e3e8 580 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
34f6e157 581
1bc99180 582 writew(NFC_ID, NFC_V1_V2_CONFIG2);
34f6e157
SH		 583
584 /* Wait for operation to complete */
c110eaf4 585 wait_op_done(host, true);
34f6e157 586
096bcc23 587 memcpy32_fromio(host->data_buf, host->main_area0, 16);
f7b66e5e 588
34f6e157 589 if (this->options & NAND_BUSWIDTH_16) {
34f6e157 590 /* compress the ID info */
f7b66e5e
JO		 591 host->data_buf[1] = host->data_buf[2];
592 host->data_buf[2] = host->data_buf[4];
593 host->data_buf[3] = host->data_buf[6];
594 host->data_buf[4] = host->data_buf[8];
595 host->data_buf[5] = host->data_buf[10];
34f6e157
SH		 596 }
597}
598
71ec5155
SH		 599static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
600{
601 writew(NFC_STATUS, NFC_V3_LAUNCH);
602 wait_op_done(host, true);
603
604 return readl(NFC_V3_CONFIG1) >> 16;
605}
606
34f6e157
SH		 607/* This function requests the NANDFC to perform a read of the
608 * NAND device status and returns the current status. */
5f97304e 609static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
34f6e157 610{
c29c607a 611 void __iomem *main_buf = host->main_area0;
34f6e157 612 uint32_t store;
f06368f7 613 uint16_t ret;
34f6e157 614
d178e3e8 615 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
34f6e157 616
c29c607a
SH		 617 /*
618 * The device status is stored in main_area0. To
619 * prevent corruption of the buffer save the value
620 * and restore it afterwards.
621 */
34f6e157 622 store = readl(main_buf);
34f6e157 623
1bc99180 624 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
c110eaf4 625 wait_op_done(host, true);
34f6e157 626
34f6e157 627 ret = readw(main_buf);
c29c607a 628
34f6e157
SH		 629 writel(store, main_buf);
630
631 return ret;
632}
633
634/* This functions is used by upper layer to checks if device is ready */
635static int mxc_nand_dev_ready(struct mtd_info *mtd)
636{
637 /*
638 * NFC handles R/B internally. Therefore, this function
639 * always returns status as ready.
640 */
641 return 1;
642}
643
644static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
645{
646 /*
647 * If HW ECC is enabled, we turn it on during init. There is
648 * no need to enable again here.
649 */
650}
651
94f77e50 652static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
34f6e157
SH		 653 u_char *read_ecc, u_char *calc_ecc)
654{
655 struct nand_chip *nand_chip = mtd->priv;
656 struct mxc_nand_host *host = nand_chip->priv;
657
658 /*
659 * 1-Bit errors are automatically corrected in HW. No need for
660 * additional correction. 2-Bit errors cannot be corrected by
661 * HW ECC, so we need to return failure
662 */
6d38af25 663 uint16_t ecc_status = get_ecc_status_v1(host);
34f6e157
SH		 664
665 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
289c0522 666 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
34f6e157
SH		 667 return -1;
668 }
669
670 return 0;
671}
672
94f77e50
SH		 673static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
674 u_char *read_ecc, u_char *calc_ecc)
675{
676 struct nand_chip *nand_chip = mtd->priv;
677 struct mxc_nand_host *host = nand_chip->priv;
678 u32 ecc_stat, err;
679 int no_subpages = 1;
680 int ret = 0;
681 u8 ecc_bit_mask, err_limit;
682
683 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
684 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
685
686 no_subpages = mtd->writesize >> 9;
687
6d38af25 688 ecc_stat = host->devtype_data->get_ecc_status(host);
94f77e50
SH		 689
690 do {
691 err = ecc_stat & ecc_bit_mask;
692 if (err > err_limit) {
693 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
694 return -1;
695 } else {
696 ret += err;
697 }
698 ecc_stat >>= 4;
699 } while (--no_subpages);
700
94f77e50
SH		 701 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
702
703 return ret;
704}
705
34f6e157
SH		 706static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
707 u_char *ecc_code)
708{
709 return 0;
710}
711
712static u_char mxc_nand_read_byte(struct mtd_info *mtd)
713{
714 struct nand_chip *nand_chip = mtd->priv;
715 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d 716 uint8_t ret;
34f6e157
SH		 717
718 /* Check for status request */
719 if (host->status_request)
e4303b25 720 return host->devtype_data->get_dev_status(host) & 0xFF;
34f6e157 721
f8f9608d
SH		 722 ret = *(uint8_t *)(host->data_buf + host->buf_start);
723 host->buf_start++;
34f6e157
SH		 724
725 return ret;
726}
727
728static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
729{
730 struct nand_chip *nand_chip = mtd->priv;
731 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d 732 uint16_t ret;
34f6e157 733
f8f9608d
SH		 734 ret = *(uint16_t *)(host->data_buf + host->buf_start);
735 host->buf_start += 2;
34f6e157
SH		 736
737 return ret;
738}
739
740/* Write data of length len to buffer buf. The data to be
741 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
742 * Operation by the NFC, the data is written to NAND Flash */
743static void mxc_nand_write_buf(struct mtd_info *mtd,
744 const u_char *buf, int len)
745{
746 struct nand_chip *nand_chip = mtd->priv;
747 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d
SH		 748 u16 col = host->buf_start;
749 int n = mtd->oobsize + mtd->writesize - col;
34f6e157 750
f8f9608d 751 n = min(n, len);
34f6e157 752
f8f9608d 753 memcpy(host->data_buf + col, buf, n);
34f6e157 754
f8f9608d 755 host->buf_start += n;
34f6e157
SH		 756}
757
758/* Read the data buffer from the NAND Flash. To read the data from NAND
759 * Flash first the data output cycle is initiated by the NFC, which copies
760 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
761 */
762static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
763{
764 struct nand_chip *nand_chip = mtd->priv;
765 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d
SH		 766 u16 col = host->buf_start;
767 int n = mtd->oobsize + mtd->writesize - col;
34f6e157 768
f8f9608d 769 n = min(n, len);
34f6e157 770
5d9d9936 771 memcpy(buf, host->data_buf + col, n);
34f6e157 772
5d9d9936 773 host->buf_start += n;
34f6e157
SH		 774}
775
34f6e157
SH		 776/* This function is used by upper layer for select and
777 * deselect of the NAND chip */
5e05a2d6 778static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
34f6e157
SH		 779{
780 struct nand_chip *nand_chip = mtd->priv;
781 struct mxc_nand_host *host = nand_chip->priv;
782
d178e3e8 783 if (chip == -1) {
34f6e157
SH		 784 /* Disable the NFC clock */
785 if (host->clk_act) {
97c3213f 786 clk_disable_unprepare(host->clk);
34f6e157
SH		 787 host->clk_act = 0;
788 }
d178e3e8
BS		 789 return;
790 }
791
792 if (!host->clk_act) {
34f6e157 793 /* Enable the NFC clock */
97c3213f 794 clk_prepare_enable(host->clk);
d178e3e8
BS		 795 host->clk_act = 1;
796 }
5e05a2d6 797}
34f6e157 798
5e05a2d6
UKK		 799static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
800{
801 struct nand_chip *nand_chip = mtd->priv;
802 struct mxc_nand_host *host = nand_chip->priv;
803
804 if (chip == -1) {
805 /* Disable the NFC clock */
806 if (host->clk_act) {
3d059693 807 clk_disable_unprepare(host->clk);
5e05a2d6
UKK		 808 host->clk_act = 0;
809 }
810 return;
811 }
34f6e157 812
5e05a2d6
UKK		 813 if (!host->clk_act) {
814 /* Enable the NFC clock */
3d059693 815 clk_prepare_enable(host->clk);
5e05a2d6 816 host->clk_act = 1;
34f6e157 817 }
5e05a2d6
UKK		 818
819 host->active_cs = chip;
820 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
34f6e157
SH		 821}
822
f8f9608d
SH		 823/*
824 * Function to transfer data to/from spare area.
825 */
826static void copy_spare(struct mtd_info *mtd, bool bfrom)
34f6e157 827{
f8f9608d
SH		 828 struct nand_chip *this = mtd->priv;
829 struct mxc_nand_host *host = this->priv;
830 u16 i, j;
831 u16 n = mtd->writesize >> 9;
832 u8 *d = host->data_buf + mtd->writesize;
4b6f05e1 833 u8 __iomem *s = host->spare0;
f48d0f9a 834 u16 t = host->devtype_data->spare_len;
f8f9608d
SH		 835
836 j = (mtd->oobsize / n >> 1) << 1;
837
838 if (bfrom) {
839 for (i = 0; i < n - 1; i++)
096bcc23 840 memcpy32_fromio(d + i * j, s + i * t, j);
f8f9608d
SH		 841
842 /* the last section */
096bcc23 843 memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
f8f9608d
SH		 844 } else {
845 for (i = 0; i < n - 1; i++)
096bcc23 846 memcpy32_toio(&s[i * t], &d[i * j], j);
34f6e157 847
f8f9608d 848 /* the last section */
096bcc23 849 memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
34f6e157 850 }
f8f9608d 851}
34f6e157 852
a3e65b64
SH		 853static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
854{
855 struct nand_chip *nand_chip = mtd->priv;
856 struct mxc_nand_host *host = nand_chip->priv;
34f6e157
SH		 857
858 /* Write out column address, if necessary */
859 if (column != -1) {
860 /*
861 * MXC NANDFC can only perform full page+spare or
862 * spare-only read/write. When the upper layers
177b241d
GE		 863 * perform a read/write buf operation, the saved column
864 * address is used to index into the full page.
34f6e157 865 */
e4303b25 866 host->devtype_data->send_addr(host, 0, page_addr == -1);
2d69c7fa 867 if (mtd->writesize > 512)
34f6e157 868 /* another col addr cycle for 2k page */
e4303b25 869 host->devtype_data->send_addr(host, 0, false);
34f6e157
SH		 870 }
871
872 /* Write out page address, if necessary */
873 if (page_addr != -1) {
874 /* paddr_0 - p_addr_7 */
e4303b25 875 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
34f6e157 876
2d69c7fa 877 if (mtd->writesize > 512) {
bd3fd62e
VB		 878 if (mtd->size >= 0x10000000) {
879 /* paddr_8 - paddr_15 */
e4303b25
UKK		 880 host->devtype_data->send_addr(host,
881 (page_addr >> 8) & 0xff,
882 false);
883 host->devtype_data->send_addr(host,
884 (page_addr >> 16) & 0xff,
885 true);
bd3fd62e
VB		 886 } else
887 /* paddr_8 - paddr_15 */
e4303b25
UKK		 888 host->devtype_data->send_addr(host,
889 (page_addr >> 8) & 0xff, true);
34f6e157
SH		 890 } else {
891 /* One more address cycle for higher density devices */
892 if (mtd->size >= 0x4000000) {
893 /* paddr_8 - paddr_15 */
e4303b25
UKK		 894 host->devtype_data->send_addr(host,
895 (page_addr >> 8) & 0xff,
896 false);
897 host->devtype_data->send_addr(host,
898 (page_addr >> 16) & 0xff,
899 true);
34f6e157
SH		 900 } else
901 /* paddr_8 - paddr_15 */
e4303b25
UKK		 902 host->devtype_data->send_addr(host,
903 (page_addr >> 8) & 0xff, true);
34f6e157
SH		 904 }
905 }
a3e65b64
SH		 906}
907
6e85dfdc
SH		 908/*
909 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
910 * on how much oob the nand chip has. For 8bit ecc we need at least
911 * 26 bytes of oob data per 512 byte block.
912 */
913static int get_eccsize(struct mtd_info *mtd)
914{
915 int oobbytes_per_512 = 0;
916
917 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
918
919 if (oobbytes_per_512 < 26)
920 return 4;
921 else
922 return 8;
923}
924
6d38af25 925static void preset_v1(struct mtd_info *mtd)
d4840180
IC		 926{
927 struct nand_chip *nand_chip = mtd->priv;
928 struct mxc_nand_host *host = nand_chip->priv;
b8db2f51
SH		 929 uint16_t config1 = 0;
930
931 if (nand_chip->ecc.mode == NAND_ECC_HW)
932 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
933
f48d0f9a 934 if (!host->devtype_data->irqpending_quirk)
6d38af25
UKK		 935 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
936
937 host->eccsize = 1;
938
939 writew(config1, NFC_V1_V2_CONFIG1);
940 /* preset operation */
941
942 /* Unlock the internal RAM Buffer */
943 writew(0x2, NFC_V1_V2_CONFIG);
944
945 /* Blocks to be unlocked */
946 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
947 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
948
949 /* Unlock Block Command for given address range */
950 writew(0x4, NFC_V1_V2_WRPROT);
951}
952
953static void preset_v2(struct mtd_info *mtd)
d4840180
IC		 954{
955 struct nand_chip *nand_chip = mtd->priv;
956 struct mxc_nand_host *host = nand_chip->priv;
b8db2f51
SH		 957 uint16_t config1 = 0;
958
959 if (nand_chip->ecc.mode == NAND_ECC_HW)
960 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
961
6d38af25 962 config1 |= NFC_V2_CONFIG1_FP_INT;
b8db2f51 963
f48d0f9a 964 if (!host->devtype_data->irqpending_quirk)
b8db2f51 965 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
6e85dfdc 966
6d38af25 967 if (mtd->writesize) {
b8db2f51
SH		 968 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
969
6e85dfdc
SH		 970 host->eccsize = get_eccsize(mtd);
971 if (host->eccsize == 4)
b8db2f51
SH		 972 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
973
974 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
d4840180 975 } else {
6e85dfdc 976 host->eccsize = 1;
d4840180 977 }
6e85dfdc 978
b8db2f51 979 writew(config1, NFC_V1_V2_CONFIG1);
d4840180
IC		 980 /* preset operation */
981
982 /* Unlock the internal RAM Buffer */
1bc99180 983 writew(0x2, NFC_V1_V2_CONFIG);
d4840180
IC		 984
985 /* Blocks to be unlocked */
6d38af25
UKK		 986 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
987 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
988 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
989 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
990 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
991 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
992 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
993 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
d4840180
IC		 994
995 /* Unlock Block Command for given address range */
1bc99180 996 writew(0x4, NFC_V1_V2_WRPROT);
d4840180
IC		 997}
998
71ec5155
SH		 999static void preset_v3(struct mtd_info *mtd)
1000{
1001 struct nand_chip *chip = mtd->priv;
1002 struct mxc_nand_host *host = chip->priv;
1003 uint32_t config2, config3;
1004 int i, addr_phases;
1005
1006 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1007 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1008
1009 /* Unlock the internal RAM Buffer */
1010 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1011 NFC_V3_WRPROT);
1012
1013 /* Blocks to be unlocked */
1014 for (i = 0; i < NAND_MAX_CHIPS; i++)
1015 writel(0x0 | (0xffff << 16),
1016 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1017
1018 writel(0, NFC_V3_IPC);
1019
1020 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1021 NFC_V3_CONFIG2_2CMD_PHASES |
1022 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1023 NFC_V3_CONFIG2_ST_CMD(0x70) |
63f1474c 1024 NFC_V3_CONFIG2_INT_MSK |
71ec5155
SH		 1025 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1026
1027 if (chip->ecc.mode == NAND_ECC_HW)
1028 config2 |= NFC_V3_CONFIG2_ECC_EN;
1029
1030 addr_phases = fls(chip->pagemask) >> 3;
1031
1032 if (mtd->writesize == 2048) {
1033 config2 |= NFC_V3_CONFIG2_PS_2048;
1034 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1035 } else if (mtd->writesize == 4096) {
1036 config2 |= NFC_V3_CONFIG2_PS_4096;
1037 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1038 } else {
1039 config2 |= NFC_V3_CONFIG2_PS_512;
1040 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1041 }
1042
1043 if (mtd->writesize) {
71718a8e
SH		 1044 config2 |= NFC_V3_CONFIG2_PPB(
1045 ffs(mtd->erasesize / mtd->writesize) - 6,
1046 host->devtype_data->ppb_shift);
71ec5155
SH		 1047 host->eccsize = get_eccsize(mtd);
1048 if (host->eccsize == 8)
1049 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1050 }
1051
1052 writel(config2, NFC_V3_CONFIG2);
1053
1054 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1055 NFC_V3_CONFIG3_NO_SDMA |
1056 NFC_V3_CONFIG3_RBB_MODE |
1057 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1058 NFC_V3_CONFIG3_ADD_OP(0);
1059
1060 if (!(chip->options & NAND_BUSWIDTH_16))
1061 config3 |= NFC_V3_CONFIG3_FW8;
1062
1063 writel(config3, NFC_V3_CONFIG3);
1064
1065 writel(0, NFC_V3_DELAY_LINE);
d4840180
IC		 1066}
1067
34f6e157
SH		 1068/* Used by the upper layer to write command to NAND Flash for
1069 * different operations to be carried out on NAND Flash */
1070static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1071 int column, int page_addr)
1072{
1073 struct nand_chip *nand_chip = mtd->priv;
1074 struct mxc_nand_host *host = nand_chip->priv;
34f6e157 1075
289c0522 1076 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
34f6e157
SH		 1077 command, column, page_addr);
1078
1079 /* Reset command state information */
1080 host->status_request = false;
34f6e157 1081
34f6e157 1082 /* Command pre-processing step */
34f6e157 1083 switch (command) {
d4840180 1084 case NAND_CMD_RESET:
e4303b25
UKK		 1085 host->devtype_data->preset(mtd);
1086 host->devtype_data->send_cmd(host, command, false);
d4840180 1087 break;
34f6e157 1088
34f6e157 1089 case NAND_CMD_STATUS:
f8f9608d 1090 host->buf_start = 0;
34f6e157 1091 host->status_request = true;
34f6e157 1092
e4303b25 1093 host->devtype_data->send_cmd(host, command, true);
89121a6b 1094 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 1095 break;
1096
34f6e157 1097 case NAND_CMD_READ0:
34f6e157 1098 case NAND_CMD_READOOB:
89121a6b
SH		 1099 if (command == NAND_CMD_READ0)
1100 host->buf_start = column;
1101 else
1102 host->buf_start = column + mtd->writesize;
f8f9608d 1103
5ea32021 1104 command = NAND_CMD_READ0; /* only READ0 is valid */
89121a6b 1105
e4303b25 1106 host->devtype_data->send_cmd(host, command, false);
89121a6b
SH		 1107 mxc_do_addr_cycle(mtd, column, page_addr);
1108
2d69c7fa 1109 if (mtd->writesize > 512)
e4303b25
UKK		 1110 host->devtype_data->send_cmd(host,
1111 NAND_CMD_READSTART, true);
c5d23f1b 1112
e4303b25 1113 host->devtype_data->send_page(mtd, NFC_OUTPUT);
89121a6b 1114
096bcc23
SH		 1115 memcpy32_fromio(host->data_buf, host->main_area0,
1116 mtd->writesize);
89121a6b 1117 copy_spare(mtd, true);
34f6e157
SH		 1118 break;
1119
34f6e157 1120 case NAND_CMD_SEQIN:
5ea32021
SH		 1121 if (column >= mtd->writesize)
1122 /* call ourself to read a page */
1123 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
34f6e157 1124
5ea32021 1125 host->buf_start = column;
89121a6b 1126
e4303b25 1127 host->devtype_data->send_cmd(host, command, false);
89121a6b 1128 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 1129 break;
1130
1131 case NAND_CMD_PAGEPROG:
096bcc23 1132 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
f8f9608d 1133 copy_spare(mtd, false);
e4303b25
UKK		 1134 host->devtype_data->send_page(mtd, NFC_INPUT);
1135 host->devtype_data->send_cmd(host, command, true);
89121a6b 1136 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 1137 break;
1138
34f6e157 1139 case NAND_CMD_READID:
e4303b25 1140 host->devtype_data->send_cmd(host, command, true);
89121a6b 1141 mxc_do_addr_cycle(mtd, column, page_addr);
e4303b25 1142 host->devtype_data->send_read_id(host);
9467114e 1143 host->buf_start = column;
34f6e157
SH		 1144 break;
1145
89121a6b 1146 case NAND_CMD_ERASE1:
34f6e157 1147 case NAND_CMD_ERASE2:
e4303b25 1148 host->devtype_data->send_cmd(host, command, false);
89121a6b
SH		 1149 mxc_do_addr_cycle(mtd, column, page_addr);
1150
34f6e157
SH		 1151 break;
1152 }
1153}
1154
f1372055
SH		 1155/*
1156 * The generic flash bbt decriptors overlap with our ecc
1157 * hardware, so define some i.MX specific ones.
1158 */
1159static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1160static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1161
1162static struct nand_bbt_descr bbt_main_descr = {
1163 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1164 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1165 .offs = 0,
1166 .len = 4,
1167 .veroffs = 4,
1168 .maxblocks = 4,
1169 .pattern = bbt_pattern,
1170};
1171
1172static struct nand_bbt_descr bbt_mirror_descr = {
1173 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1174 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1175 .offs = 0,
1176 .len = 4,
1177 .veroffs = 4,
1178 .maxblocks = 4,
1179 .pattern = mirror_pattern,
1180};
1181
f48d0f9a 1182/* v1 + irqpending_quirk: i.MX21 */
e4303b25 1183static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
6d38af25 1184 .preset = preset_v1,
e4303b25
UKK		 1185 .send_cmd = send_cmd_v1_v2,
1186 .send_addr = send_addr_v1_v2,
6d38af25 1187 .send_page = send_page_v1,
e4303b25
UKK		 1188 .send_read_id = send_read_id_v1_v2,
1189 .get_dev_status = get_dev_status_v1_v2,
1190 .check_int = check_int_v1_v2,
1191 .irq_control = irq_control_v1_v2,
6d38af25 1192 .get_ecc_status = get_ecc_status_v1,
6dcdf99d
UKK		 1193 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1194 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1195 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
5e05a2d6 1196 .select_chip = mxc_nand_select_chip_v1_v3,
69d023be 1197 .correct_data = mxc_nand_correct_data_v1,
f48d0f9a
UKK		 1198 .irqpending_quirk = 1,
1199 .needs_ip = 0,
1200 .regs_offset = 0xe00,
1201 .spare0_offset = 0x800,
1202 .spare_len = 16,
1203 .eccbytes = 3,
1204 .eccsize = 1,
1205};
1206
1207/* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1208static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1209 .preset = preset_v1,
1210 .send_cmd = send_cmd_v1_v2,
1211 .send_addr = send_addr_v1_v2,
1212 .send_page = send_page_v1,
1213 .send_read_id = send_read_id_v1_v2,
1214 .get_dev_status = get_dev_status_v1_v2,
1215 .check_int = check_int_v1_v2,
1216 .irq_control = irq_control_v1_v2,
1217 .get_ecc_status = get_ecc_status_v1,
1218 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1219 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1220 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1221 .select_chip = mxc_nand_select_chip_v1_v3,
1222 .correct_data = mxc_nand_correct_data_v1,
1223 .irqpending_quirk = 0,
1224 .needs_ip = 0,
1225 .regs_offset = 0xe00,
1226 .spare0_offset = 0x800,
1227 .axi_offset = 0,
1228 .spare_len = 16,
1229 .eccbytes = 3,
1230 .eccsize = 1,
e4303b25
UKK		 1231};
1232
1233/* v21: i.MX25, i.MX35 */
1234static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
6d38af25 1235 .preset = preset_v2,
e4303b25
UKK		 1236 .send_cmd = send_cmd_v1_v2,
1237 .send_addr = send_addr_v1_v2,
6d38af25 1238 .send_page = send_page_v2,
e4303b25
UKK		 1239 .send_read_id = send_read_id_v1_v2,
1240 .get_dev_status = get_dev_status_v1_v2,
1241 .check_int = check_int_v1_v2,
1242 .irq_control = irq_control_v1_v2,
6d38af25 1243 .get_ecc_status = get_ecc_status_v2,
6dcdf99d
UKK		 1244 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1245 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1246 .ecclayout_4k = &nandv2_hw_eccoob_4k,
5e05a2d6 1247 .select_chip = mxc_nand_select_chip_v2,
69d023be 1248 .correct_data = mxc_nand_correct_data_v2_v3,
f48d0f9a
UKK		 1249 .irqpending_quirk = 0,
1250 .needs_ip = 0,
1251 .regs_offset = 0x1e00,
1252 .spare0_offset = 0x1000,
1253 .axi_offset = 0,
1254 .spare_len = 64,
1255 .eccbytes = 9,
1256 .eccsize = 0,
e4303b25
UKK		 1257};
1258
71718a8e 1259/* v3.2a: i.MX51 */
e4303b25
UKK		 1260static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1261 .preset = preset_v3,
1262 .send_cmd = send_cmd_v3,
1263 .send_addr = send_addr_v3,
1264 .send_page = send_page_v3,
1265 .send_read_id = send_read_id_v3,
1266 .get_dev_status = get_dev_status_v3,
1267 .check_int = check_int_v3,
1268 .irq_control = irq_control_v3,
6d38af25 1269 .get_ecc_status = get_ecc_status_v3,
6dcdf99d
UKK		 1270 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1271 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1272 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
5e05a2d6 1273 .select_chip = mxc_nand_select_chip_v1_v3,
69d023be 1274 .correct_data = mxc_nand_correct_data_v2_v3,
f48d0f9a
UKK		 1275 .irqpending_quirk = 0,
1276 .needs_ip = 1,
1277 .regs_offset = 0,
1278 .spare0_offset = 0x1000,
1279 .axi_offset = 0x1e00,
1280 .spare_len = 64,
1281 .eccbytes = 0,
1282 .eccsize = 0,
71718a8e
SH		 1283 .ppb_shift = 7,
1284};
1285
1286/* v3.2b: i.MX53 */
1287static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1288 .preset = preset_v3,
1289 .send_cmd = send_cmd_v3,
1290 .send_addr = send_addr_v3,
1291 .send_page = send_page_v3,
1292 .send_read_id = send_read_id_v3,
1293 .get_dev_status = get_dev_status_v3,
1294 .check_int = check_int_v3,
1295 .irq_control = irq_control_v3,
1296 .get_ecc_status = get_ecc_status_v3,
1297 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1298 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1299 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1300 .select_chip = mxc_nand_select_chip_v1_v3,
1301 .correct_data = mxc_nand_correct_data_v2_v3,
1302 .irqpending_quirk = 0,
1303 .needs_ip = 1,
1304 .regs_offset = 0,
1305 .spare0_offset = 0x1000,
1306 .axi_offset = 0x1e00,
1307 .spare_len = 64,
1308 .eccbytes = 0,
1309 .eccsize = 0,
1310 .ppb_shift = 8,
e4303b25
UKK		 1311};
1312
4d62435f
SG		 1313static inline int is_imx21_nfc(struct mxc_nand_host *host)
1314{
1315 return host->devtype_data == &imx21_nand_devtype_data;
1316}
1317
1318static inline int is_imx27_nfc(struct mxc_nand_host *host)
1319{
1320 return host->devtype_data == &imx27_nand_devtype_data;
1321}
1322
1323static inline int is_imx25_nfc(struct mxc_nand_host *host)
1324{
1325 return host->devtype_data == &imx25_nand_devtype_data;
1326}
1327
1328static inline int is_imx51_nfc(struct mxc_nand_host *host)
1329{
1330 return host->devtype_data == &imx51_nand_devtype_data;
1331}
1332
1333static inline int is_imx53_nfc(struct mxc_nand_host *host)
1334{
1335 return host->devtype_data == &imx53_nand_devtype_data;
1336}
1337
1338static struct platform_device_id mxcnd_devtype[] = {
1339 {
1340 .name = "imx21-nand",
1341 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1342 }, {
1343 .name = "imx27-nand",
1344 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1345 }, {
1346 .name = "imx25-nand",
1347 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1348 }, {
1349 .name = "imx51-nand",
1350 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1351 }, {
1352 .name = "imx53-nand",
1353 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1354 }, {
1355 /* sentinel */
1356 }
1357};
1358MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1359
6436356b
UKK		 1360#ifdef CONFIG_OF_MTD
1361static const struct of_device_id mxcnd_dt_ids[] = {
1362 {
1363 .compatible = "fsl,imx21-nand",
1364 .data = &imx21_nand_devtype_data,
1365 }, {
1366 .compatible = "fsl,imx27-nand",
1367 .data = &imx27_nand_devtype_data,
1368 }, {
1369 .compatible = "fsl,imx25-nand",
1370 .data = &imx25_nand_devtype_data,
1371 }, {
1372 .compatible = "fsl,imx51-nand",
1373 .data = &imx51_nand_devtype_data,
71718a8e
SH		 1374 }, {
1375 .compatible = "fsl,imx53-nand",
1376 .data = &imx53_nand_devtype_data,
6436356b
UKK		 1377 },
1378 { /* sentinel */ }
1379};
1380
1381static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1382{
1383 struct device_node *np = host->dev->of_node;
1384 struct mxc_nand_platform_data *pdata = &host->pdata;
1385 const struct of_device_id *of_id =
1386 of_match_device(mxcnd_dt_ids, host->dev);
1387 int buswidth;
1388
1389 if (!np)
1390 return 1;
1391
1392 if (of_get_nand_ecc_mode(np) >= 0)
1393 pdata->hw_ecc = 1;
1394
1395 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1396
1397 buswidth = of_get_nand_bus_width(np);
1398 if (buswidth < 0)
1399 return buswidth;
1400
1401 pdata->width = buswidth / 8;
1402
1403 host->devtype_data = of_id->data;
1404
1405 return 0;
1406}
1407#else
1408static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1409{
1410 return 1;
1411}
1412#endif
1413
06f25510 1414static int mxcnd_probe(struct platform_device *pdev)
34f6e157
SH		 1415{
1416 struct nand_chip *this;
1417 struct mtd_info *mtd;
34f6e157
SH		 1418 struct mxc_nand_host *host;
1419 struct resource *res;
d4ed8f12 1420 int err = 0;
34f6e157
SH		 1421
1422 /* Allocate memory for MTD device structure and private data */
a5900554
HS		 1423 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1424 GFP_KERNEL);
34f6e157
SH		 1425 if (!host)
1426 return -ENOMEM;
1427
a5900554
HS		 1428 /* allocate a temporary buffer for the nand_scan_ident() */
1429 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1430 if (!host->data_buf)
1431 return -ENOMEM;
f8f9608d 1432
34f6e157
SH		 1433 host->dev = &pdev->dev;
1434 /* structures must be linked */
1435 this = &host->nand;
1436 mtd = &host->mtd;
1437 mtd->priv = this;
1438 mtd->owner = THIS_MODULE;
87f39f04 1439 mtd->dev.parent = &pdev->dev;
1fbff0a6 1440 mtd->name = DRIVER_NAME;
34f6e157
SH		 1441
1442 /* 50 us command delay time */
1443 this->chip_delay = 5;
1444
1445 this->priv = host;
1446 this->dev_ready = mxc_nand_dev_ready;
1447 this->cmdfunc = mxc_nand_command;
34f6e157
SH		 1448 this->read_byte = mxc_nand_read_byte;
1449 this->read_word = mxc_nand_read_word;
1450 this->write_buf = mxc_nand_write_buf;
1451 this->read_buf = mxc_nand_read_buf;
34f6e157 1452
24b82d3c 1453 host->clk = devm_clk_get(&pdev->dev, NULL);
e4a09cbf
SH		 1454 if (IS_ERR(host->clk))
1455 return PTR_ERR(host->clk);
34f6e157 1456
71885b65 1457 err = mxcnd_probe_dt(host);
4d62435f 1458 if (err > 0) {
453810b7
JH		 1459 struct mxc_nand_platform_data *pdata =
1460 dev_get_platdata(&pdev->dev);
4d62435f
SG		 1461 if (pdata) {
1462 host->pdata = *pdata;
1463 host->devtype_data = (struct mxc_nand_devtype_data *)
1464 pdev->id_entry->driver_data;
1465 } else {
1466 err = -ENODEV;
1467 }
1468 }
71885b65
SH		 1469 if (err < 0)
1470 return err;
1471
1472 if (host->devtype_data->needs_ip) {
1473 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b0de774c
TR		 1474 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1475 if (IS_ERR(host->regs_ip))
1476 return PTR_ERR(host->regs_ip);
71885b65
SH		 1477
1478 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1479 } else {
1480 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1481 }
1482
b0de774c
TR		 1483 host->base = devm_ioremap_resource(&pdev->dev, res);
1484 if (IS_ERR(host->base))
1485 return PTR_ERR(host->base);
34f6e157 1486
c6de7e1b 1487 host->main_area0 = host->base;
9467114e 1488
f48d0f9a
UKK		 1489 if (host->devtype_data->regs_offset)
1490 host->regs = host->base + host->devtype_data->regs_offset;
1491 host->spare0 = host->base + host->devtype_data->spare0_offset;
1492 if (host->devtype_data->axi_offset)
1493 host->regs_axi = host->base + host->devtype_data->axi_offset;
1494
1495 this->ecc.bytes = host->devtype_data->eccbytes;
1496 host->eccsize = host->devtype_data->eccsize;
1497
1498 this->select_chip = host->devtype_data->select_chip;
1499 this->ecc.size = 512;
1500 this->ecc.layout = host->devtype_data->ecclayout_512;
1501
6436356b 1502 if (host->pdata.hw_ecc) {
34f6e157
SH		 1503 this->ecc.calculate = mxc_nand_calculate_ecc;
1504 this->ecc.hwctl = mxc_nand_enable_hwecc;
69d023be 1505 this->ecc.correct = host->devtype_data->correct_data;
34f6e157 1506 this->ecc.mode = NAND_ECC_HW;
34f6e157 1507 } else {
34f6e157 1508 this->ecc.mode = NAND_ECC_SOFT;
34f6e157
SH		 1509 }
1510
6436356b
UKK		 1511 /* NAND bus width determines access functions used by upper layer */
1512 if (host->pdata.width == 2)
34f6e157 1513 this->options |= NAND_BUSWIDTH_16;
34f6e157 1514
6436356b 1515 if (host->pdata.flash_bbt) {
f1372055
SH		 1516 this->bbt_td = &bbt_main_descr;
1517 this->bbt_md = &bbt_mirror_descr;
1518 /* update flash based bbt */
bb9ebd4e 1519 this->bbt_options |= NAND_BBT_USE_FLASH;
34f6e157
SH		 1520 }
1521
63f1474c 1522 init_completion(&host->op_completion);
d4840180
IC		 1523
1524 host->irq = platform_get_irq(pdev, 0);
26fbf48b
FE		 1525 if (host->irq < 0)
1526 return host->irq;
d4840180 1527
63f1474c 1528 /*
e4303b25
UKK		 1529 * Use host->devtype_data->irq_control() here instead of irq_control()
1530 * because we must not disable_irq_nosync without having requested the
1531 * irq.
63f1474c 1532 */
e4303b25 1533 host->devtype_data->irq_control(host, 0);
63f1474c 1534
e4a09cbf 1535 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
b1eb234f 1536 0, DRIVER_NAME, host);
d4840180 1537 if (err)
e4a09cbf
SH		 1538 return err;
1539
dcedf628
FE		 1540 err = clk_prepare_enable(host->clk);
1541 if (err)
1542 return err;
e4a09cbf 1543 host->clk_act = 1;
d4840180 1544
63f1474c 1545 /*
8556958a
UKK		 1546 * Now that we "own" the interrupt make sure the interrupt mask bit is
1547 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1548 * on this machine.
63f1474c 1549 */
f48d0f9a 1550 if (host->devtype_data->irqpending_quirk) {
8556958a 1551 disable_irq_nosync(host->irq);
e4303b25 1552 host->devtype_data->irq_control(host, 1);
8556958a 1553 }
63f1474c 1554
bd3fd62e 1555 /* first scan to find the device and get the page size */
4d62435f 1556 if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
bd3fd62e
VB		 1557 err = -ENXIO;
1558 goto escan;
1559 }
34f6e157 1560
a5900554
HS		 1561 /* allocate the right size buffer now */
1562 devm_kfree(&pdev->dev, (void *)host->data_buf);
1563 host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1564 GFP_KERNEL);
1565 if (!host->data_buf) {
1566 err = -ENOMEM;
1567 goto escan;
1568 }
1569
6e85dfdc 1570 /* Call preset again, with correct writesize this time */
e4303b25 1571 host->devtype_data->preset(mtd);
6e85dfdc 1572
2d69c7fa 1573 if (mtd->writesize == 2048)
6dcdf99d
UKK		 1574 this->ecc.layout = host->devtype_data->ecclayout_2k;
1575 else if (mtd->writesize == 4096)
1576 this->ecc.layout = host->devtype_data->ecclayout_4k;
34f6e157 1577
6a918bad 1578 if (this->ecc.mode == NAND_ECC_HW) {
4d62435f 1579 if (is_imx21_nfc(host) || is_imx27_nfc(host))
6a918bad
MD		 1580 this->ecc.strength = 1;
1581 else
1582 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1583 }
1584
4a43faf5
SH		 1585 /* second phase scan */
1586 if (nand_scan_tail(mtd)) {
1587 err = -ENXIO;
1588 goto escan;
1589 }
1590
34f6e157 1591 /* Register the partitions */
6436356b
UKK		 1592 mtd_device_parse_register(mtd, part_probes,
1593 &(struct mtd_part_parser_data){
1594 .of_node = pdev->dev.of_node,
1595 },
1596 host->pdata.parts,
1597 host->pdata.nr_parts);
34f6e157
SH		 1598
1599 platform_set_drvdata(pdev, host);
1600
1601 return 0;
1602
1603escan:
c10d8ee3
LW		 1604 if (host->clk_act)
1605 clk_disable_unprepare(host->clk);
34f6e157
SH		 1606
1607 return err;
1608}
1609
810b7e06 1610static int mxcnd_remove(struct platform_device *pdev)
34f6e157
SH		 1611{
1612 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1613
34f6e157 1614 nand_release(&host->mtd);
8bfd4f7f
WY		 1615 if (host->clk_act)
1616 clk_disable_unprepare(host->clk);
34f6e157
SH		 1617
1618 return 0;
1619}
1620
34f6e157
SH		 1621static struct platform_driver mxcnd_driver = {
1622 .driver = {
1623 .name = DRIVER_NAME,
6436356b 1624 .of_match_table = of_match_ptr(mxcnd_dt_ids),
04dd0d3a 1625 },
4d62435f 1626 .id_table = mxcnd_devtype,
ddf16d62 1627 .probe = mxcnd_probe,
5153b88c 1628 .remove = mxcnd_remove,
34f6e157 1629};
ddf16d62 1630module_platform_driver(mxcnd_driver);
34f6e157
SH		 1631
1632MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1633MODULE_DESCRIPTION("MXC NAND MTD driver");
1634MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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