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34f6e157 SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/nand.h> | |
26 | #include <linux/mtd/partitions.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/io.h> | |
63f1474c SH |
33 | #include <linux/irq.h> |
34 | #include <linux/completion.h> | |
34f6e157 SH |
35 | |
36 | #include <asm/mach/flash.h> | |
37 | #include <mach/mxc_nand.h> | |
9467114e | 38 | #include <mach/hardware.h> |
34f6e157 SH |
39 | |
40 | #define DRIVER_NAME "mxc_nand" | |
41 | ||
9467114e | 42 | #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35()) |
a47bfd2e | 43 | #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21()) |
c97926dd | 44 | #define nfc_is_v3_2() (cpu_is_mx51() || cpu_is_mx53()) |
71ec5155 | 45 | #define nfc_is_v3() nfc_is_v3_2() |
9467114e | 46 | |
34f6e157 | 47 | /* Addresses for NFC registers */ |
1bc99180 SH |
48 | #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) |
49 | #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) | |
50 | #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) | |
51 | #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) | |
52 | #define NFC_V1_V2_CONFIG (host->regs + 0x0a) | |
53 | #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) | |
54 | #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) | |
55 | #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10) | |
56 | #define NFC_V1_V2_WRPROT (host->regs + 0x12) | |
57 | #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) | |
58 | #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) | |
d178e3e8 BS |
59 | #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20) |
60 | #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24) | |
61 | #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28) | |
62 | #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c) | |
63 | #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22) | |
64 | #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26) | |
65 | #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a) | |
66 | #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e) | |
1bc99180 SH |
67 | #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) |
68 | #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) | |
69 | #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) | |
70 | ||
6e85dfdc | 71 | #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) |
1bc99180 SH |
72 | #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) |
73 | #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) | |
74 | #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) | |
75 | #define NFC_V1_V2_CONFIG1_BIG (1 << 5) | |
76 | #define NFC_V1_V2_CONFIG1_RST (1 << 6) | |
77 | #define NFC_V1_V2_CONFIG1_CE (1 << 7) | |
b8db2f51 SH |
78 | #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) |
79 | #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) | |
80 | #define NFC_V2_CONFIG1_FP_INT (1 << 11) | |
1bc99180 SH |
81 | |
82 | #define NFC_V1_V2_CONFIG2_INT (1 << 15) | |
83 | ||
84 | /* | |
85 | * Operation modes for the NFC. Valid for v1, v2 and v3 | |
86 | * type controllers. | |
87 | */ | |
88 | #define NFC_CMD (1 << 0) | |
89 | #define NFC_ADDR (1 << 1) | |
90 | #define NFC_INPUT (1 << 2) | |
91 | #define NFC_OUTPUT (1 << 3) | |
92 | #define NFC_ID (1 << 4) | |
93 | #define NFC_STATUS (1 << 5) | |
34f6e157 | 94 | |
71ec5155 SH |
95 | #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) |
96 | #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) | |
97 | ||
98 | #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) | |
99 | #define NFC_V3_CONFIG1_SP_EN (1 << 0) | |
100 | #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) | |
101 | ||
102 | #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) | |
103 | ||
104 | #define NFC_V3_LAUNCH (host->regs_axi + 0x40) | |
105 | ||
106 | #define NFC_V3_WRPROT (host->regs_ip + 0x0) | |
107 | #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) | |
108 | #define NFC_V3_WRPROT_LOCK (1 << 1) | |
109 | #define NFC_V3_WRPROT_UNLOCK (1 << 2) | |
110 | #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) | |
111 | ||
112 | #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) | |
113 | ||
114 | #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) | |
115 | #define NFC_V3_CONFIG2_PS_512 (0 << 0) | |
116 | #define NFC_V3_CONFIG2_PS_2048 (1 << 0) | |
117 | #define NFC_V3_CONFIG2_PS_4096 (2 << 0) | |
118 | #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) | |
119 | #define NFC_V3_CONFIG2_ECC_EN (1 << 3) | |
120 | #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) | |
121 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) | |
122 | #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) | |
123 | #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) | |
124 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) | |
125 | #define NFC_V3_CONFIG2_INT_MSK (1 << 15) | |
126 | #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) | |
127 | #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) | |
128 | ||
129 | #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) | |
130 | #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) | |
131 | #define NFC_V3_CONFIG3_FW8 (1 << 3) | |
132 | #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) | |
133 | #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) | |
134 | #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) | |
135 | #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) | |
136 | ||
137 | #define NFC_V3_IPC (host->regs_ip + 0x2C) | |
138 | #define NFC_V3_IPC_CREQ (1 << 0) | |
139 | #define NFC_V3_IPC_INT (1 << 31) | |
140 | ||
141 | #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) | |
34f6e157 | 142 | |
e4303b25 UKK |
143 | struct mxc_nand_host; |
144 | ||
145 | struct mxc_nand_devtype_data { | |
146 | void (*preset)(struct mtd_info *); | |
147 | void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); | |
148 | void (*send_addr)(struct mxc_nand_host *, uint16_t, int); | |
149 | void (*send_page)(struct mtd_info *, unsigned int); | |
150 | void (*send_read_id)(struct mxc_nand_host *); | |
151 | uint16_t (*get_dev_status)(struct mxc_nand_host *); | |
152 | int (*check_int)(struct mxc_nand_host *); | |
153 | void (*irq_control)(struct mxc_nand_host *, int); | |
6d38af25 | 154 | u32 (*get_ecc_status)(struct mxc_nand_host *); |
6dcdf99d | 155 | struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k; |
5e05a2d6 | 156 | void (*select_chip)(struct mtd_info *mtd, int chip); |
69d023be UKK |
157 | int (*correct_data)(struct mtd_info *mtd, u_char *dat, |
158 | u_char *read_ecc, u_char *calc_ecc); | |
f48d0f9a UKK |
159 | |
160 | /* | |
161 | * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked | |
162 | * (CONFIG1:INT_MSK is set). To handle this the driver uses | |
163 | * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK | |
164 | */ | |
165 | int irqpending_quirk; | |
166 | int needs_ip; | |
167 | ||
168 | size_t regs_offset; | |
169 | size_t spare0_offset; | |
170 | size_t axi_offset; | |
171 | ||
172 | int spare_len; | |
173 | int eccbytes; | |
174 | int eccsize; | |
e4303b25 UKK |
175 | }; |
176 | ||
34f6e157 SH |
177 | struct mxc_nand_host { |
178 | struct mtd_info mtd; | |
179 | struct nand_chip nand; | |
34f6e157 SH |
180 | struct device *dev; |
181 | ||
c6de7e1b SH |
182 | void *spare0; |
183 | void *main_area0; | |
c6de7e1b SH |
184 | |
185 | void __iomem *base; | |
34f6e157 | 186 | void __iomem *regs; |
71ec5155 SH |
187 | void __iomem *regs_axi; |
188 | void __iomem *regs_ip; | |
34f6e157 | 189 | int status_request; |
34f6e157 SH |
190 | struct clk *clk; |
191 | int clk_act; | |
192 | int irq; | |
94f77e50 | 193 | int eccsize; |
d178e3e8 | 194 | int active_cs; |
34f6e157 | 195 | |
63f1474c | 196 | struct completion op_completion; |
34f6e157 | 197 | |
f8f9608d SH |
198 | uint8_t *data_buf; |
199 | unsigned int buf_start; | |
5f97304e | 200 | |
e4303b25 | 201 | const struct mxc_nand_devtype_data *devtype_data; |
34f6e157 SH |
202 | }; |
203 | ||
34f6e157 | 204 | /* OOB placement block for use with hardware ecc generation */ |
9467114e | 205 | static struct nand_ecclayout nandv1_hw_eccoob_smallpage = { |
34f6e157 SH |
206 | .eccbytes = 5, |
207 | .eccpos = {6, 7, 8, 9, 10}, | |
8c1fd89a | 208 | .oobfree = {{0, 5}, {12, 4}, } |
bd3fd62e VB |
209 | }; |
210 | ||
9467114e | 211 | static struct nand_ecclayout nandv1_hw_eccoob_largepage = { |
bd3fd62e VB |
212 | .eccbytes = 20, |
213 | .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, | |
214 | 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, | |
215 | .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } | |
34f6e157 SH |
216 | }; |
217 | ||
9467114e SH |
218 | /* OOB description for 512 byte pages with 16 byte OOB */ |
219 | static struct nand_ecclayout nandv2_hw_eccoob_smallpage = { | |
220 | .eccbytes = 1 * 9, | |
221 | .eccpos = { | |
222 | 7, 8, 9, 10, 11, 12, 13, 14, 15 | |
223 | }, | |
224 | .oobfree = { | |
225 | {.offset = 0, .length = 5} | |
226 | } | |
227 | }; | |
228 | ||
229 | /* OOB description for 2048 byte pages with 64 byte OOB */ | |
230 | static struct nand_ecclayout nandv2_hw_eccoob_largepage = { | |
231 | .eccbytes = 4 * 9, | |
232 | .eccpos = { | |
233 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
234 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
235 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
236 | 55, 56, 57, 58, 59, 60, 61, 62, 63 | |
237 | }, | |
238 | .oobfree = { | |
239 | {.offset = 2, .length = 4}, | |
240 | {.offset = 16, .length = 7}, | |
241 | {.offset = 32, .length = 7}, | |
242 | {.offset = 48, .length = 7} | |
243 | } | |
244 | }; | |
245 | ||
2c1c5f19 BS |
246 | /* OOB description for 4096 byte pages with 128 byte OOB */ |
247 | static struct nand_ecclayout nandv2_hw_eccoob_4k = { | |
248 | .eccbytes = 8 * 9, | |
249 | .eccpos = { | |
250 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
251 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
252 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
253 | 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
254 | 71, 72, 73, 74, 75, 76, 77, 78, 79, | |
255 | 87, 88, 89, 90, 91, 92, 93, 94, 95, | |
256 | 103, 104, 105, 106, 107, 108, 109, 110, 111, | |
257 | 119, 120, 121, 122, 123, 124, 125, 126, 127, | |
258 | }, | |
259 | .oobfree = { | |
260 | {.offset = 2, .length = 4}, | |
261 | {.offset = 16, .length = 7}, | |
262 | {.offset = 32, .length = 7}, | |
263 | {.offset = 48, .length = 7}, | |
264 | {.offset = 64, .length = 7}, | |
265 | {.offset = 80, .length = 7}, | |
266 | {.offset = 96, .length = 7}, | |
267 | {.offset = 112, .length = 7}, | |
268 | } | |
269 | }; | |
270 | ||
34f6e157 | 271 | static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; |
34f6e157 | 272 | |
71ec5155 SH |
273 | static int check_int_v3(struct mxc_nand_host *host) |
274 | { | |
275 | uint32_t tmp; | |
276 | ||
277 | tmp = readl(NFC_V3_IPC); | |
278 | if (!(tmp & NFC_V3_IPC_INT)) | |
279 | return 0; | |
280 | ||
281 | tmp &= ~NFC_V3_IPC_INT; | |
282 | writel(tmp, NFC_V3_IPC); | |
283 | ||
284 | return 1; | |
285 | } | |
286 | ||
7aaf28ac SH |
287 | static int check_int_v1_v2(struct mxc_nand_host *host) |
288 | { | |
289 | uint32_t tmp; | |
290 | ||
1bc99180 SH |
291 | tmp = readw(NFC_V1_V2_CONFIG2); |
292 | if (!(tmp & NFC_V1_V2_CONFIG2_INT)) | |
7aaf28ac SH |
293 | return 0; |
294 | ||
f48d0f9a | 295 | if (!host->devtype_data->irqpending_quirk) |
63f1474c | 296 | writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2); |
7aaf28ac SH |
297 | |
298 | return 1; | |
299 | } | |
300 | ||
63f1474c SH |
301 | static void irq_control_v1_v2(struct mxc_nand_host *host, int activate) |
302 | { | |
303 | uint16_t tmp; | |
304 | ||
305 | tmp = readw(NFC_V1_V2_CONFIG1); | |
306 | ||
307 | if (activate) | |
308 | tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK; | |
309 | else | |
310 | tmp |= NFC_V1_V2_CONFIG1_INT_MSK; | |
311 | ||
312 | writew(tmp, NFC_V1_V2_CONFIG1); | |
313 | } | |
314 | ||
315 | static void irq_control_v3(struct mxc_nand_host *host, int activate) | |
316 | { | |
317 | uint32_t tmp; | |
318 | ||
319 | tmp = readl(NFC_V3_CONFIG2); | |
320 | ||
321 | if (activate) | |
322 | tmp &= ~NFC_V3_CONFIG2_INT_MSK; | |
323 | else | |
324 | tmp |= NFC_V3_CONFIG2_INT_MSK; | |
325 | ||
326 | writel(tmp, NFC_V3_CONFIG2); | |
327 | } | |
328 | ||
8556958a UKK |
329 | static void irq_control(struct mxc_nand_host *host, int activate) |
330 | { | |
f48d0f9a | 331 | if (host->devtype_data->irqpending_quirk) { |
8556958a UKK |
332 | if (activate) |
333 | enable_irq(host->irq); | |
334 | else | |
335 | disable_irq_nosync(host->irq); | |
336 | } else { | |
e4303b25 | 337 | host->devtype_data->irq_control(host, activate); |
8556958a UKK |
338 | } |
339 | } | |
340 | ||
6d38af25 UKK |
341 | static u32 get_ecc_status_v1(struct mxc_nand_host *host) |
342 | { | |
343 | return readw(NFC_V1_V2_ECC_STATUS_RESULT); | |
344 | } | |
345 | ||
346 | static u32 get_ecc_status_v2(struct mxc_nand_host *host) | |
347 | { | |
348 | return readl(NFC_V1_V2_ECC_STATUS_RESULT); | |
349 | } | |
350 | ||
351 | static u32 get_ecc_status_v3(struct mxc_nand_host *host) | |
352 | { | |
353 | return readl(NFC_V3_ECC_STATUS_RESULT); | |
354 | } | |
355 | ||
8556958a UKK |
356 | static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) |
357 | { | |
358 | struct mxc_nand_host *host = dev_id; | |
359 | ||
e4303b25 | 360 | if (!host->devtype_data->check_int(host)) |
8556958a UKK |
361 | return IRQ_NONE; |
362 | ||
363 | irq_control(host, 0); | |
364 | ||
365 | complete(&host->op_completion); | |
366 | ||
367 | return IRQ_HANDLED; | |
368 | } | |
369 | ||
34f6e157 SH |
370 | /* This function polls the NANDFC to wait for the basic operation to |
371 | * complete by checking the INT bit of config2 register. | |
372 | */ | |
c110eaf4 | 373 | static void wait_op_done(struct mxc_nand_host *host, int useirq) |
34f6e157 | 374 | { |
a47bfd2e | 375 | int max_retries = 8000; |
34f6e157 SH |
376 | |
377 | if (useirq) { | |
e4303b25 | 378 | if (!host->devtype_data->check_int(host)) { |
63f1474c | 379 | INIT_COMPLETION(host->op_completion); |
8556958a | 380 | irq_control(host, 1); |
63f1474c | 381 | wait_for_completion(&host->op_completion); |
34f6e157 SH |
382 | } |
383 | } else { | |
384 | while (max_retries-- > 0) { | |
e4303b25 | 385 | if (host->devtype_data->check_int(host)) |
34f6e157 | 386 | break; |
7aaf28ac | 387 | |
34f6e157 SH |
388 | udelay(1); |
389 | } | |
43950a60 | 390 | if (max_retries < 0) |
0a32a102 | 391 | pr_debug("%s: INT not set\n", __func__); |
34f6e157 SH |
392 | } |
393 | } | |
394 | ||
71ec5155 SH |
395 | static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
396 | { | |
397 | /* fill command */ | |
398 | writel(cmd, NFC_V3_FLASH_CMD); | |
399 | ||
400 | /* send out command */ | |
401 | writel(NFC_CMD, NFC_V3_LAUNCH); | |
402 | ||
403 | /* Wait for operation to complete */ | |
404 | wait_op_done(host, useirq); | |
405 | } | |
406 | ||
34f6e157 SH |
407 | /* This function issues the specified command to the NAND device and |
408 | * waits for completion. */ | |
5f97304e | 409 | static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
34f6e157 | 410 | { |
289c0522 | 411 | pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq); |
34f6e157 | 412 | |
1bc99180 SH |
413 | writew(cmd, NFC_V1_V2_FLASH_CMD); |
414 | writew(NFC_CMD, NFC_V1_V2_CONFIG2); | |
34f6e157 | 415 | |
f48d0f9a | 416 | if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) { |
a47bfd2e IC |
417 | int max_retries = 100; |
418 | /* Reset completion is indicated by NFC_CONFIG2 */ | |
419 | /* being set to 0 */ | |
420 | while (max_retries-- > 0) { | |
1bc99180 | 421 | if (readw(NFC_V1_V2_CONFIG2) == 0) { |
a47bfd2e IC |
422 | break; |
423 | } | |
424 | udelay(1); | |
425 | } | |
426 | if (max_retries < 0) | |
0a32a102 | 427 | pr_debug("%s: RESET failed\n", __func__); |
a47bfd2e IC |
428 | } else { |
429 | /* Wait for operation to complete */ | |
430 | wait_op_done(host, useirq); | |
431 | } | |
34f6e157 SH |
432 | } |
433 | ||
71ec5155 SH |
434 | static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast) |
435 | { | |
436 | /* fill address */ | |
437 | writel(addr, NFC_V3_FLASH_ADDR0); | |
438 | ||
439 | /* send out address */ | |
440 | writel(NFC_ADDR, NFC_V3_LAUNCH); | |
441 | ||
442 | wait_op_done(host, 0); | |
443 | } | |
444 | ||
34f6e157 SH |
445 | /* This function sends an address (or partial address) to the |
446 | * NAND device. The address is used to select the source/destination for | |
447 | * a NAND command. */ | |
5f97304e | 448 | static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast) |
34f6e157 | 449 | { |
289c0522 | 450 | pr_debug("send_addr(host, 0x%x %d)\n", addr, islast); |
34f6e157 | 451 | |
1bc99180 SH |
452 | writew(addr, NFC_V1_V2_FLASH_ADDR); |
453 | writew(NFC_ADDR, NFC_V1_V2_CONFIG2); | |
34f6e157 SH |
454 | |
455 | /* Wait for operation to complete */ | |
c110eaf4 | 456 | wait_op_done(host, islast); |
34f6e157 SH |
457 | } |
458 | ||
71ec5155 SH |
459 | static void send_page_v3(struct mtd_info *mtd, unsigned int ops) |
460 | { | |
461 | struct nand_chip *nand_chip = mtd->priv; | |
462 | struct mxc_nand_host *host = nand_chip->priv; | |
463 | uint32_t tmp; | |
464 | ||
465 | tmp = readl(NFC_V3_CONFIG1); | |
466 | tmp &= ~(7 << 4); | |
467 | writel(tmp, NFC_V3_CONFIG1); | |
468 | ||
469 | /* transfer data from NFC ram to nand */ | |
470 | writel(ops, NFC_V3_LAUNCH); | |
471 | ||
472 | wait_op_done(host, false); | |
473 | } | |
474 | ||
6d38af25 UKK |
475 | static void send_page_v2(struct mtd_info *mtd, unsigned int ops) |
476 | { | |
477 | struct nand_chip *nand_chip = mtd->priv; | |
478 | struct mxc_nand_host *host = nand_chip->priv; | |
479 | ||
480 | /* NANDFC buffer 0 is used for page read/write */ | |
481 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
482 | ||
483 | writew(ops, NFC_V1_V2_CONFIG2); | |
484 | ||
485 | /* Wait for operation to complete */ | |
486 | wait_op_done(host, true); | |
487 | } | |
488 | ||
489 | static void send_page_v1(struct mtd_info *mtd, unsigned int ops) | |
34f6e157 | 490 | { |
2d69c7fa SH |
491 | struct nand_chip *nand_chip = mtd->priv; |
492 | struct mxc_nand_host *host = nand_chip->priv; | |
c5d23f1b | 493 | int bufs, i; |
34f6e157 | 494 | |
6d38af25 | 495 | if (mtd->writesize > 512) |
c5d23f1b SH |
496 | bufs = 4; |
497 | else | |
498 | bufs = 1; | |
34f6e157 | 499 | |
c5d23f1b | 500 | for (i = 0; i < bufs; i++) { |
34f6e157 | 501 | |
c5d23f1b | 502 | /* NANDFC buffer 0 is used for page read/write */ |
d178e3e8 | 503 | writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 504 | |
1bc99180 | 505 | writew(ops, NFC_V1_V2_CONFIG2); |
34f6e157 | 506 | |
c5d23f1b | 507 | /* Wait for operation to complete */ |
c110eaf4 | 508 | wait_op_done(host, true); |
34f6e157 | 509 | } |
34f6e157 SH |
510 | } |
511 | ||
71ec5155 SH |
512 | static void send_read_id_v3(struct mxc_nand_host *host) |
513 | { | |
514 | /* Read ID into main buffer */ | |
515 | writel(NFC_ID, NFC_V3_LAUNCH); | |
516 | ||
517 | wait_op_done(host, true); | |
518 | ||
519 | memcpy(host->data_buf, host->main_area0, 16); | |
520 | } | |
521 | ||
34f6e157 | 522 | /* Request the NANDFC to perform a read of the NAND device ID. */ |
5f97304e | 523 | static void send_read_id_v1_v2(struct mxc_nand_host *host) |
34f6e157 SH |
524 | { |
525 | struct nand_chip *this = &host->nand; | |
34f6e157 SH |
526 | |
527 | /* NANDFC buffer 0 is used for device ID output */ | |
d178e3e8 | 528 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 529 | |
1bc99180 | 530 | writew(NFC_ID, NFC_V1_V2_CONFIG2); |
34f6e157 SH |
531 | |
532 | /* Wait for operation to complete */ | |
c110eaf4 | 533 | wait_op_done(host, true); |
34f6e157 | 534 | |
f7b66e5e JO |
535 | memcpy(host->data_buf, host->main_area0, 16); |
536 | ||
34f6e157 | 537 | if (this->options & NAND_BUSWIDTH_16) { |
34f6e157 | 538 | /* compress the ID info */ |
f7b66e5e JO |
539 | host->data_buf[1] = host->data_buf[2]; |
540 | host->data_buf[2] = host->data_buf[4]; | |
541 | host->data_buf[3] = host->data_buf[6]; | |
542 | host->data_buf[4] = host->data_buf[8]; | |
543 | host->data_buf[5] = host->data_buf[10]; | |
34f6e157 SH |
544 | } |
545 | } | |
546 | ||
71ec5155 SH |
547 | static uint16_t get_dev_status_v3(struct mxc_nand_host *host) |
548 | { | |
549 | writew(NFC_STATUS, NFC_V3_LAUNCH); | |
550 | wait_op_done(host, true); | |
551 | ||
552 | return readl(NFC_V3_CONFIG1) >> 16; | |
553 | } | |
554 | ||
34f6e157 SH |
555 | /* This function requests the NANDFC to perform a read of the |
556 | * NAND device status and returns the current status. */ | |
5f97304e | 557 | static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host) |
34f6e157 | 558 | { |
c29c607a | 559 | void __iomem *main_buf = host->main_area0; |
34f6e157 | 560 | uint32_t store; |
f06368f7 | 561 | uint16_t ret; |
34f6e157 | 562 | |
d178e3e8 | 563 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 564 | |
c29c607a SH |
565 | /* |
566 | * The device status is stored in main_area0. To | |
567 | * prevent corruption of the buffer save the value | |
568 | * and restore it afterwards. | |
569 | */ | |
34f6e157 | 570 | store = readl(main_buf); |
34f6e157 | 571 | |
1bc99180 | 572 | writew(NFC_STATUS, NFC_V1_V2_CONFIG2); |
c110eaf4 | 573 | wait_op_done(host, true); |
34f6e157 | 574 | |
34f6e157 | 575 | ret = readw(main_buf); |
c29c607a | 576 | |
34f6e157 SH |
577 | writel(store, main_buf); |
578 | ||
579 | return ret; | |
580 | } | |
581 | ||
582 | /* This functions is used by upper layer to checks if device is ready */ | |
583 | static int mxc_nand_dev_ready(struct mtd_info *mtd) | |
584 | { | |
585 | /* | |
586 | * NFC handles R/B internally. Therefore, this function | |
587 | * always returns status as ready. | |
588 | */ | |
589 | return 1; | |
590 | } | |
591 | ||
592 | static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
593 | { | |
594 | /* | |
595 | * If HW ECC is enabled, we turn it on during init. There is | |
596 | * no need to enable again here. | |
597 | */ | |
598 | } | |
599 | ||
94f77e50 | 600 | static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat, |
34f6e157 SH |
601 | u_char *read_ecc, u_char *calc_ecc) |
602 | { | |
603 | struct nand_chip *nand_chip = mtd->priv; | |
604 | struct mxc_nand_host *host = nand_chip->priv; | |
605 | ||
606 | /* | |
607 | * 1-Bit errors are automatically corrected in HW. No need for | |
608 | * additional correction. 2-Bit errors cannot be corrected by | |
609 | * HW ECC, so we need to return failure | |
610 | */ | |
6d38af25 | 611 | uint16_t ecc_status = get_ecc_status_v1(host); |
34f6e157 SH |
612 | |
613 | if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { | |
289c0522 | 614 | pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); |
34f6e157 SH |
615 | return -1; |
616 | } | |
617 | ||
618 | return 0; | |
619 | } | |
620 | ||
94f77e50 SH |
621 | static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat, |
622 | u_char *read_ecc, u_char *calc_ecc) | |
623 | { | |
624 | struct nand_chip *nand_chip = mtd->priv; | |
625 | struct mxc_nand_host *host = nand_chip->priv; | |
626 | u32 ecc_stat, err; | |
627 | int no_subpages = 1; | |
628 | int ret = 0; | |
629 | u8 ecc_bit_mask, err_limit; | |
630 | ||
631 | ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; | |
632 | err_limit = (host->eccsize == 4) ? 0x4 : 0x8; | |
633 | ||
634 | no_subpages = mtd->writesize >> 9; | |
635 | ||
6d38af25 | 636 | ecc_stat = host->devtype_data->get_ecc_status(host); |
94f77e50 SH |
637 | |
638 | do { | |
639 | err = ecc_stat & ecc_bit_mask; | |
640 | if (err > err_limit) { | |
641 | printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); | |
642 | return -1; | |
643 | } else { | |
644 | ret += err; | |
645 | } | |
646 | ecc_stat >>= 4; | |
647 | } while (--no_subpages); | |
648 | ||
649 | mtd->ecc_stats.corrected += ret; | |
650 | pr_debug("%d Symbol Correctable RS-ECC Error\n", ret); | |
651 | ||
652 | return ret; | |
653 | } | |
654 | ||
34f6e157 SH |
655 | static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
656 | u_char *ecc_code) | |
657 | { | |
658 | return 0; | |
659 | } | |
660 | ||
661 | static u_char mxc_nand_read_byte(struct mtd_info *mtd) | |
662 | { | |
663 | struct nand_chip *nand_chip = mtd->priv; | |
664 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 665 | uint8_t ret; |
34f6e157 SH |
666 | |
667 | /* Check for status request */ | |
668 | if (host->status_request) | |
e4303b25 | 669 | return host->devtype_data->get_dev_status(host) & 0xFF; |
34f6e157 | 670 | |
f8f9608d SH |
671 | ret = *(uint8_t *)(host->data_buf + host->buf_start); |
672 | host->buf_start++; | |
34f6e157 SH |
673 | |
674 | return ret; | |
675 | } | |
676 | ||
677 | static uint16_t mxc_nand_read_word(struct mtd_info *mtd) | |
678 | { | |
679 | struct nand_chip *nand_chip = mtd->priv; | |
680 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 681 | uint16_t ret; |
34f6e157 | 682 | |
f8f9608d SH |
683 | ret = *(uint16_t *)(host->data_buf + host->buf_start); |
684 | host->buf_start += 2; | |
34f6e157 SH |
685 | |
686 | return ret; | |
687 | } | |
688 | ||
689 | /* Write data of length len to buffer buf. The data to be | |
690 | * written on NAND Flash is first copied to RAMbuffer. After the Data Input | |
691 | * Operation by the NFC, the data is written to NAND Flash */ | |
692 | static void mxc_nand_write_buf(struct mtd_info *mtd, | |
693 | const u_char *buf, int len) | |
694 | { | |
695 | struct nand_chip *nand_chip = mtd->priv; | |
696 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
697 | u16 col = host->buf_start; |
698 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 699 | |
f8f9608d | 700 | n = min(n, len); |
34f6e157 | 701 | |
f8f9608d | 702 | memcpy(host->data_buf + col, buf, n); |
34f6e157 | 703 | |
f8f9608d | 704 | host->buf_start += n; |
34f6e157 SH |
705 | } |
706 | ||
707 | /* Read the data buffer from the NAND Flash. To read the data from NAND | |
708 | * Flash first the data output cycle is initiated by the NFC, which copies | |
709 | * the data to RAMbuffer. This data of length len is then copied to buffer buf. | |
710 | */ | |
711 | static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
712 | { | |
713 | struct nand_chip *nand_chip = mtd->priv; | |
714 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
715 | u16 col = host->buf_start; |
716 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 717 | |
f8f9608d | 718 | n = min(n, len); |
34f6e157 | 719 | |
5d9d9936 | 720 | memcpy(buf, host->data_buf + col, n); |
34f6e157 | 721 | |
5d9d9936 | 722 | host->buf_start += n; |
34f6e157 SH |
723 | } |
724 | ||
725 | /* Used by the upper layer to verify the data in NAND Flash | |
726 | * with the data in the buf. */ | |
727 | static int mxc_nand_verify_buf(struct mtd_info *mtd, | |
728 | const u_char *buf, int len) | |
729 | { | |
730 | return -EFAULT; | |
731 | } | |
732 | ||
733 | /* This function is used by upper layer for select and | |
734 | * deselect of the NAND chip */ | |
5e05a2d6 | 735 | static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip) |
34f6e157 SH |
736 | { |
737 | struct nand_chip *nand_chip = mtd->priv; | |
738 | struct mxc_nand_host *host = nand_chip->priv; | |
739 | ||
d178e3e8 | 740 | if (chip == -1) { |
34f6e157 SH |
741 | /* Disable the NFC clock */ |
742 | if (host->clk_act) { | |
743 | clk_disable(host->clk); | |
744 | host->clk_act = 0; | |
745 | } | |
d178e3e8 BS |
746 | return; |
747 | } | |
748 | ||
749 | if (!host->clk_act) { | |
34f6e157 | 750 | /* Enable the NFC clock */ |
d178e3e8 BS |
751 | clk_enable(host->clk); |
752 | host->clk_act = 1; | |
753 | } | |
5e05a2d6 UKK |
754 | } |
755 | ||
756 | static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip) | |
757 | { | |
758 | struct nand_chip *nand_chip = mtd->priv; | |
759 | struct mxc_nand_host *host = nand_chip->priv; | |
760 | ||
761 | if (chip == -1) { | |
762 | /* Disable the NFC clock */ | |
763 | if (host->clk_act) { | |
764 | clk_disable(host->clk); | |
765 | host->clk_act = 0; | |
766 | } | |
767 | return; | |
768 | } | |
34f6e157 | 769 | |
5e05a2d6 UKK |
770 | if (!host->clk_act) { |
771 | /* Enable the NFC clock */ | |
772 | clk_enable(host->clk); | |
773 | host->clk_act = 1; | |
34f6e157 | 774 | } |
5e05a2d6 UKK |
775 | |
776 | host->active_cs = chip; | |
777 | writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR); | |
34f6e157 SH |
778 | } |
779 | ||
f8f9608d SH |
780 | /* |
781 | * Function to transfer data to/from spare area. | |
782 | */ | |
783 | static void copy_spare(struct mtd_info *mtd, bool bfrom) | |
34f6e157 | 784 | { |
f8f9608d SH |
785 | struct nand_chip *this = mtd->priv; |
786 | struct mxc_nand_host *host = this->priv; | |
787 | u16 i, j; | |
788 | u16 n = mtd->writesize >> 9; | |
789 | u8 *d = host->data_buf + mtd->writesize; | |
c6de7e1b | 790 | u8 *s = host->spare0; |
f48d0f9a | 791 | u16 t = host->devtype_data->spare_len; |
f8f9608d SH |
792 | |
793 | j = (mtd->oobsize / n >> 1) << 1; | |
794 | ||
795 | if (bfrom) { | |
796 | for (i = 0; i < n - 1; i++) | |
797 | memcpy(d + i * j, s + i * t, j); | |
798 | ||
799 | /* the last section */ | |
800 | memcpy(d + i * j, s + i * t, mtd->oobsize - i * j); | |
801 | } else { | |
802 | for (i = 0; i < n - 1; i++) | |
803 | memcpy(&s[i * t], &d[i * j], j); | |
34f6e157 | 804 | |
f8f9608d SH |
805 | /* the last section */ |
806 | memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j); | |
34f6e157 | 807 | } |
f8f9608d | 808 | } |
34f6e157 | 809 | |
a3e65b64 SH |
810 | static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) |
811 | { | |
812 | struct nand_chip *nand_chip = mtd->priv; | |
813 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 SH |
814 | |
815 | /* Write out column address, if necessary */ | |
816 | if (column != -1) { | |
817 | /* | |
818 | * MXC NANDFC can only perform full page+spare or | |
819 | * spare-only read/write. When the upper layers | |
177b241d GE |
820 | * perform a read/write buf operation, the saved column |
821 | * address is used to index into the full page. | |
34f6e157 | 822 | */ |
e4303b25 | 823 | host->devtype_data->send_addr(host, 0, page_addr == -1); |
2d69c7fa | 824 | if (mtd->writesize > 512) |
34f6e157 | 825 | /* another col addr cycle for 2k page */ |
e4303b25 | 826 | host->devtype_data->send_addr(host, 0, false); |
34f6e157 SH |
827 | } |
828 | ||
829 | /* Write out page address, if necessary */ | |
830 | if (page_addr != -1) { | |
831 | /* paddr_0 - p_addr_7 */ | |
e4303b25 | 832 | host->devtype_data->send_addr(host, (page_addr & 0xff), false); |
34f6e157 | 833 | |
2d69c7fa | 834 | if (mtd->writesize > 512) { |
bd3fd62e VB |
835 | if (mtd->size >= 0x10000000) { |
836 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
837 | host->devtype_data->send_addr(host, |
838 | (page_addr >> 8) & 0xff, | |
839 | false); | |
840 | host->devtype_data->send_addr(host, | |
841 | (page_addr >> 16) & 0xff, | |
842 | true); | |
bd3fd62e VB |
843 | } else |
844 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
845 | host->devtype_data->send_addr(host, |
846 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
847 | } else { |
848 | /* One more address cycle for higher density devices */ | |
849 | if (mtd->size >= 0x4000000) { | |
850 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
851 | host->devtype_data->send_addr(host, |
852 | (page_addr >> 8) & 0xff, | |
853 | false); | |
854 | host->devtype_data->send_addr(host, | |
855 | (page_addr >> 16) & 0xff, | |
856 | true); | |
34f6e157 SH |
857 | } else |
858 | /* paddr_8 - paddr_15 */ | |
e4303b25 UKK |
859 | host->devtype_data->send_addr(host, |
860 | (page_addr >> 8) & 0xff, true); | |
34f6e157 SH |
861 | } |
862 | } | |
a3e65b64 SH |
863 | } |
864 | ||
6e85dfdc SH |
865 | /* |
866 | * v2 and v3 type controllers can do 4bit or 8bit ecc depending | |
867 | * on how much oob the nand chip has. For 8bit ecc we need at least | |
868 | * 26 bytes of oob data per 512 byte block. | |
869 | */ | |
870 | static int get_eccsize(struct mtd_info *mtd) | |
871 | { | |
872 | int oobbytes_per_512 = 0; | |
873 | ||
874 | oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; | |
875 | ||
876 | if (oobbytes_per_512 < 26) | |
877 | return 4; | |
878 | else | |
879 | return 8; | |
880 | } | |
881 | ||
6d38af25 | 882 | static void preset_v1(struct mtd_info *mtd) |
d4840180 IC |
883 | { |
884 | struct nand_chip *nand_chip = mtd->priv; | |
885 | struct mxc_nand_host *host = nand_chip->priv; | |
b8db2f51 SH |
886 | uint16_t config1 = 0; |
887 | ||
888 | if (nand_chip->ecc.mode == NAND_ECC_HW) | |
889 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
890 | ||
f48d0f9a | 891 | if (!host->devtype_data->irqpending_quirk) |
6d38af25 UKK |
892 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
893 | ||
894 | host->eccsize = 1; | |
895 | ||
896 | writew(config1, NFC_V1_V2_CONFIG1); | |
897 | /* preset operation */ | |
898 | ||
899 | /* Unlock the internal RAM Buffer */ | |
900 | writew(0x2, NFC_V1_V2_CONFIG); | |
901 | ||
902 | /* Blocks to be unlocked */ | |
903 | writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR); | |
904 | writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR); | |
905 | ||
906 | /* Unlock Block Command for given address range */ | |
907 | writew(0x4, NFC_V1_V2_WRPROT); | |
908 | } | |
909 | ||
910 | static void preset_v2(struct mtd_info *mtd) | |
911 | { | |
912 | struct nand_chip *nand_chip = mtd->priv; | |
913 | struct mxc_nand_host *host = nand_chip->priv; | |
914 | uint16_t config1 = 0; | |
915 | ||
916 | if (nand_chip->ecc.mode == NAND_ECC_HW) | |
917 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
918 | ||
919 | config1 |= NFC_V2_CONFIG1_FP_INT; | |
b8db2f51 | 920 | |
f48d0f9a | 921 | if (!host->devtype_data->irqpending_quirk) |
b8db2f51 | 922 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; |
6e85dfdc | 923 | |
6d38af25 | 924 | if (mtd->writesize) { |
b8db2f51 SH |
925 | uint16_t pages_per_block = mtd->erasesize / mtd->writesize; |
926 | ||
6e85dfdc SH |
927 | host->eccsize = get_eccsize(mtd); |
928 | if (host->eccsize == 4) | |
b8db2f51 SH |
929 | config1 |= NFC_V2_CONFIG1_ECC_MODE_4; |
930 | ||
931 | config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); | |
d4840180 | 932 | } else { |
6e85dfdc | 933 | host->eccsize = 1; |
d4840180 | 934 | } |
6e85dfdc | 935 | |
b8db2f51 | 936 | writew(config1, NFC_V1_V2_CONFIG1); |
d4840180 IC |
937 | /* preset operation */ |
938 | ||
939 | /* Unlock the internal RAM Buffer */ | |
1bc99180 | 940 | writew(0x2, NFC_V1_V2_CONFIG); |
d4840180 IC |
941 | |
942 | /* Blocks to be unlocked */ | |
6d38af25 UKK |
943 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0); |
944 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1); | |
945 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2); | |
946 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3); | |
947 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0); | |
948 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1); | |
949 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2); | |
950 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3); | |
d4840180 IC |
951 | |
952 | /* Unlock Block Command for given address range */ | |
1bc99180 | 953 | writew(0x4, NFC_V1_V2_WRPROT); |
d4840180 IC |
954 | } |
955 | ||
71ec5155 SH |
956 | static void preset_v3(struct mtd_info *mtd) |
957 | { | |
958 | struct nand_chip *chip = mtd->priv; | |
959 | struct mxc_nand_host *host = chip->priv; | |
960 | uint32_t config2, config3; | |
961 | int i, addr_phases; | |
962 | ||
963 | writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); | |
964 | writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); | |
965 | ||
966 | /* Unlock the internal RAM Buffer */ | |
967 | writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, | |
968 | NFC_V3_WRPROT); | |
969 | ||
970 | /* Blocks to be unlocked */ | |
971 | for (i = 0; i < NAND_MAX_CHIPS; i++) | |
972 | writel(0x0 | (0xffff << 16), | |
973 | NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); | |
974 | ||
975 | writel(0, NFC_V3_IPC); | |
976 | ||
977 | config2 = NFC_V3_CONFIG2_ONE_CYCLE | | |
978 | NFC_V3_CONFIG2_2CMD_PHASES | | |
979 | NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | | |
980 | NFC_V3_CONFIG2_ST_CMD(0x70) | | |
63f1474c | 981 | NFC_V3_CONFIG2_INT_MSK | |
71ec5155 SH |
982 | NFC_V3_CONFIG2_NUM_ADDR_PHASE0; |
983 | ||
984 | if (chip->ecc.mode == NAND_ECC_HW) | |
985 | config2 |= NFC_V3_CONFIG2_ECC_EN; | |
986 | ||
987 | addr_phases = fls(chip->pagemask) >> 3; | |
988 | ||
989 | if (mtd->writesize == 2048) { | |
990 | config2 |= NFC_V3_CONFIG2_PS_2048; | |
991 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
992 | } else if (mtd->writesize == 4096) { | |
993 | config2 |= NFC_V3_CONFIG2_PS_4096; | |
994 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
995 | } else { | |
996 | config2 |= NFC_V3_CONFIG2_PS_512; | |
997 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); | |
998 | } | |
999 | ||
1000 | if (mtd->writesize) { | |
1001 | config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6); | |
1002 | host->eccsize = get_eccsize(mtd); | |
1003 | if (host->eccsize == 8) | |
1004 | config2 |= NFC_V3_CONFIG2_ECC_MODE_8; | |
1005 | } | |
1006 | ||
1007 | writel(config2, NFC_V3_CONFIG2); | |
1008 | ||
1009 | config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | | |
1010 | NFC_V3_CONFIG3_NO_SDMA | | |
1011 | NFC_V3_CONFIG3_RBB_MODE | | |
1012 | NFC_V3_CONFIG3_SBB(6) | /* Reset default */ | |
1013 | NFC_V3_CONFIG3_ADD_OP(0); | |
1014 | ||
1015 | if (!(chip->options & NAND_BUSWIDTH_16)) | |
1016 | config3 |= NFC_V3_CONFIG3_FW8; | |
1017 | ||
1018 | writel(config3, NFC_V3_CONFIG3); | |
1019 | ||
1020 | writel(0, NFC_V3_DELAY_LINE); | |
d4840180 IC |
1021 | } |
1022 | ||
34f6e157 SH |
1023 | /* Used by the upper layer to write command to NAND Flash for |
1024 | * different operations to be carried out on NAND Flash */ | |
1025 | static void mxc_nand_command(struct mtd_info *mtd, unsigned command, | |
1026 | int column, int page_addr) | |
1027 | { | |
1028 | struct nand_chip *nand_chip = mtd->priv; | |
1029 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 | 1030 | |
289c0522 | 1031 | pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", |
34f6e157 SH |
1032 | command, column, page_addr); |
1033 | ||
1034 | /* Reset command state information */ | |
1035 | host->status_request = false; | |
34f6e157 | 1036 | |
34f6e157 | 1037 | /* Command pre-processing step */ |
34f6e157 | 1038 | switch (command) { |
d4840180 | 1039 | case NAND_CMD_RESET: |
e4303b25 UKK |
1040 | host->devtype_data->preset(mtd); |
1041 | host->devtype_data->send_cmd(host, command, false); | |
d4840180 | 1042 | break; |
34f6e157 | 1043 | |
34f6e157 | 1044 | case NAND_CMD_STATUS: |
f8f9608d | 1045 | host->buf_start = 0; |
34f6e157 | 1046 | host->status_request = true; |
34f6e157 | 1047 | |
e4303b25 | 1048 | host->devtype_data->send_cmd(host, command, true); |
89121a6b | 1049 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1050 | break; |
1051 | ||
34f6e157 | 1052 | case NAND_CMD_READ0: |
34f6e157 | 1053 | case NAND_CMD_READOOB: |
89121a6b SH |
1054 | if (command == NAND_CMD_READ0) |
1055 | host->buf_start = column; | |
1056 | else | |
1057 | host->buf_start = column + mtd->writesize; | |
f8f9608d | 1058 | |
5ea32021 | 1059 | command = NAND_CMD_READ0; /* only READ0 is valid */ |
89121a6b | 1060 | |
e4303b25 | 1061 | host->devtype_data->send_cmd(host, command, false); |
89121a6b SH |
1062 | mxc_do_addr_cycle(mtd, column, page_addr); |
1063 | ||
2d69c7fa | 1064 | if (mtd->writesize > 512) |
e4303b25 UKK |
1065 | host->devtype_data->send_cmd(host, |
1066 | NAND_CMD_READSTART, true); | |
c5d23f1b | 1067 | |
e4303b25 | 1068 | host->devtype_data->send_page(mtd, NFC_OUTPUT); |
89121a6b | 1069 | |
c6de7e1b | 1070 | memcpy(host->data_buf, host->main_area0, mtd->writesize); |
89121a6b | 1071 | copy_spare(mtd, true); |
34f6e157 SH |
1072 | break; |
1073 | ||
34f6e157 | 1074 | case NAND_CMD_SEQIN: |
5ea32021 SH |
1075 | if (column >= mtd->writesize) |
1076 | /* call ourself to read a page */ | |
1077 | mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); | |
34f6e157 | 1078 | |
5ea32021 | 1079 | host->buf_start = column; |
89121a6b | 1080 | |
e4303b25 | 1081 | host->devtype_data->send_cmd(host, command, false); |
89121a6b | 1082 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1083 | break; |
1084 | ||
1085 | case NAND_CMD_PAGEPROG: | |
c6de7e1b | 1086 | memcpy(host->main_area0, host->data_buf, mtd->writesize); |
f8f9608d | 1087 | copy_spare(mtd, false); |
e4303b25 UKK |
1088 | host->devtype_data->send_page(mtd, NFC_INPUT); |
1089 | host->devtype_data->send_cmd(host, command, true); | |
89121a6b | 1090 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
1091 | break; |
1092 | ||
34f6e157 | 1093 | case NAND_CMD_READID: |
e4303b25 | 1094 | host->devtype_data->send_cmd(host, command, true); |
89121a6b | 1095 | mxc_do_addr_cycle(mtd, column, page_addr); |
e4303b25 | 1096 | host->devtype_data->send_read_id(host); |
9467114e | 1097 | host->buf_start = column; |
34f6e157 SH |
1098 | break; |
1099 | ||
89121a6b | 1100 | case NAND_CMD_ERASE1: |
34f6e157 | 1101 | case NAND_CMD_ERASE2: |
e4303b25 | 1102 | host->devtype_data->send_cmd(host, command, false); |
89121a6b SH |
1103 | mxc_do_addr_cycle(mtd, column, page_addr); |
1104 | ||
34f6e157 SH |
1105 | break; |
1106 | } | |
1107 | } | |
1108 | ||
f1372055 SH |
1109 | /* |
1110 | * The generic flash bbt decriptors overlap with our ecc | |
1111 | * hardware, so define some i.MX specific ones. | |
1112 | */ | |
1113 | static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; | |
1114 | static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; | |
1115 | ||
1116 | static struct nand_bbt_descr bbt_main_descr = { | |
1117 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1118 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1119 | .offs = 0, | |
1120 | .len = 4, | |
1121 | .veroffs = 4, | |
1122 | .maxblocks = 4, | |
1123 | .pattern = bbt_pattern, | |
1124 | }; | |
1125 | ||
1126 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1127 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1128 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1129 | .offs = 0, | |
1130 | .len = 4, | |
1131 | .veroffs = 4, | |
1132 | .maxblocks = 4, | |
1133 | .pattern = mirror_pattern, | |
1134 | }; | |
1135 | ||
f48d0f9a | 1136 | /* v1 + irqpending_quirk: i.MX21 */ |
e4303b25 | 1137 | static const struct mxc_nand_devtype_data imx21_nand_devtype_data = { |
6d38af25 | 1138 | .preset = preset_v1, |
e4303b25 UKK |
1139 | .send_cmd = send_cmd_v1_v2, |
1140 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1141 | .send_page = send_page_v1, |
e4303b25 UKK |
1142 | .send_read_id = send_read_id_v1_v2, |
1143 | .get_dev_status = get_dev_status_v1_v2, | |
1144 | .check_int = check_int_v1_v2, | |
1145 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1146 | .get_ecc_status = get_ecc_status_v1, |
6dcdf99d UKK |
1147 | .ecclayout_512 = &nandv1_hw_eccoob_smallpage, |
1148 | .ecclayout_2k = &nandv1_hw_eccoob_largepage, | |
1149 | .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */ | |
5e05a2d6 | 1150 | .select_chip = mxc_nand_select_chip_v1_v3, |
69d023be | 1151 | .correct_data = mxc_nand_correct_data_v1, |
f48d0f9a UKK |
1152 | .irqpending_quirk = 1, |
1153 | .needs_ip = 0, | |
1154 | .regs_offset = 0xe00, | |
1155 | .spare0_offset = 0x800, | |
1156 | .spare_len = 16, | |
1157 | .eccbytes = 3, | |
1158 | .eccsize = 1, | |
1159 | }; | |
1160 | ||
1161 | /* v1 + !irqpending_quirk: i.MX27, i.MX31 */ | |
1162 | static const struct mxc_nand_devtype_data imx27_nand_devtype_data = { | |
1163 | .preset = preset_v1, | |
1164 | .send_cmd = send_cmd_v1_v2, | |
1165 | .send_addr = send_addr_v1_v2, | |
1166 | .send_page = send_page_v1, | |
1167 | .send_read_id = send_read_id_v1_v2, | |
1168 | .get_dev_status = get_dev_status_v1_v2, | |
1169 | .check_int = check_int_v1_v2, | |
1170 | .irq_control = irq_control_v1_v2, | |
1171 | .get_ecc_status = get_ecc_status_v1, | |
1172 | .ecclayout_512 = &nandv1_hw_eccoob_smallpage, | |
1173 | .ecclayout_2k = &nandv1_hw_eccoob_largepage, | |
1174 | .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */ | |
1175 | .select_chip = mxc_nand_select_chip_v1_v3, | |
1176 | .correct_data = mxc_nand_correct_data_v1, | |
1177 | .irqpending_quirk = 0, | |
1178 | .needs_ip = 0, | |
1179 | .regs_offset = 0xe00, | |
1180 | .spare0_offset = 0x800, | |
1181 | .axi_offset = 0, | |
1182 | .spare_len = 16, | |
1183 | .eccbytes = 3, | |
1184 | .eccsize = 1, | |
e4303b25 UKK |
1185 | }; |
1186 | ||
1187 | /* v21: i.MX25, i.MX35 */ | |
1188 | static const struct mxc_nand_devtype_data imx25_nand_devtype_data = { | |
6d38af25 | 1189 | .preset = preset_v2, |
e4303b25 UKK |
1190 | .send_cmd = send_cmd_v1_v2, |
1191 | .send_addr = send_addr_v1_v2, | |
6d38af25 | 1192 | .send_page = send_page_v2, |
e4303b25 UKK |
1193 | .send_read_id = send_read_id_v1_v2, |
1194 | .get_dev_status = get_dev_status_v1_v2, | |
1195 | .check_int = check_int_v1_v2, | |
1196 | .irq_control = irq_control_v1_v2, | |
6d38af25 | 1197 | .get_ecc_status = get_ecc_status_v2, |
6dcdf99d UKK |
1198 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, |
1199 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1200 | .ecclayout_4k = &nandv2_hw_eccoob_4k, | |
5e05a2d6 | 1201 | .select_chip = mxc_nand_select_chip_v2, |
69d023be | 1202 | .correct_data = mxc_nand_correct_data_v2_v3, |
f48d0f9a UKK |
1203 | .irqpending_quirk = 0, |
1204 | .needs_ip = 0, | |
1205 | .regs_offset = 0x1e00, | |
1206 | .spare0_offset = 0x1000, | |
1207 | .axi_offset = 0, | |
1208 | .spare_len = 64, | |
1209 | .eccbytes = 9, | |
1210 | .eccsize = 0, | |
e4303b25 UKK |
1211 | }; |
1212 | ||
1213 | /* v3: i.MX51, i.MX53 */ | |
1214 | static const struct mxc_nand_devtype_data imx51_nand_devtype_data = { | |
1215 | .preset = preset_v3, | |
1216 | .send_cmd = send_cmd_v3, | |
1217 | .send_addr = send_addr_v3, | |
1218 | .send_page = send_page_v3, | |
1219 | .send_read_id = send_read_id_v3, | |
1220 | .get_dev_status = get_dev_status_v3, | |
1221 | .check_int = check_int_v3, | |
1222 | .irq_control = irq_control_v3, | |
6d38af25 | 1223 | .get_ecc_status = get_ecc_status_v3, |
6dcdf99d UKK |
1224 | .ecclayout_512 = &nandv2_hw_eccoob_smallpage, |
1225 | .ecclayout_2k = &nandv2_hw_eccoob_largepage, | |
1226 | .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */ | |
5e05a2d6 | 1227 | .select_chip = mxc_nand_select_chip_v1_v3, |
69d023be | 1228 | .correct_data = mxc_nand_correct_data_v2_v3, |
f48d0f9a UKK |
1229 | .irqpending_quirk = 0, |
1230 | .needs_ip = 1, | |
1231 | .regs_offset = 0, | |
1232 | .spare0_offset = 0x1000, | |
1233 | .axi_offset = 0x1e00, | |
1234 | .spare_len = 64, | |
1235 | .eccbytes = 0, | |
1236 | .eccsize = 0, | |
e4303b25 UKK |
1237 | }; |
1238 | ||
34f6e157 SH |
1239 | static int __init mxcnd_probe(struct platform_device *pdev) |
1240 | { | |
1241 | struct nand_chip *this; | |
1242 | struct mtd_info *mtd; | |
1243 | struct mxc_nand_platform_data *pdata = pdev->dev.platform_data; | |
1244 | struct mxc_nand_host *host; | |
1245 | struct resource *res; | |
d4ed8f12 | 1246 | int err = 0; |
34f6e157 SH |
1247 | |
1248 | /* Allocate memory for MTD device structure and private data */ | |
f8f9608d SH |
1249 | host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE + |
1250 | NAND_MAX_OOBSIZE, GFP_KERNEL); | |
34f6e157 SH |
1251 | if (!host) |
1252 | return -ENOMEM; | |
1253 | ||
f8f9608d | 1254 | host->data_buf = (uint8_t *)(host + 1); |
f8f9608d | 1255 | |
34f6e157 SH |
1256 | host->dev = &pdev->dev; |
1257 | /* structures must be linked */ | |
1258 | this = &host->nand; | |
1259 | mtd = &host->mtd; | |
1260 | mtd->priv = this; | |
1261 | mtd->owner = THIS_MODULE; | |
87f39f04 | 1262 | mtd->dev.parent = &pdev->dev; |
1fbff0a6 | 1263 | mtd->name = DRIVER_NAME; |
34f6e157 SH |
1264 | |
1265 | /* 50 us command delay time */ | |
1266 | this->chip_delay = 5; | |
1267 | ||
1268 | this->priv = host; | |
1269 | this->dev_ready = mxc_nand_dev_ready; | |
1270 | this->cmdfunc = mxc_nand_command; | |
34f6e157 SH |
1271 | this->read_byte = mxc_nand_read_byte; |
1272 | this->read_word = mxc_nand_read_word; | |
1273 | this->write_buf = mxc_nand_write_buf; | |
1274 | this->read_buf = mxc_nand_read_buf; | |
1275 | this->verify_buf = mxc_nand_verify_buf; | |
1276 | ||
e65fb009 | 1277 | host->clk = clk_get(&pdev->dev, "nfc"); |
8541c118 VB |
1278 | if (IS_ERR(host->clk)) { |
1279 | err = PTR_ERR(host->clk); | |
34f6e157 | 1280 | goto eclk; |
8541c118 | 1281 | } |
34f6e157 SH |
1282 | |
1283 | clk_enable(host->clk); | |
1284 | host->clk_act = 1; | |
1285 | ||
1286 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1287 | if (!res) { | |
1288 | err = -ENODEV; | |
1289 | goto eres; | |
1290 | } | |
1291 | ||
c6de7e1b SH |
1292 | host->base = ioremap(res->start, resource_size(res)); |
1293 | if (!host->base) { | |
8541c118 | 1294 | err = -ENOMEM; |
34f6e157 SH |
1295 | goto eres; |
1296 | } | |
1297 | ||
c6de7e1b | 1298 | host->main_area0 = host->base; |
9467114e | 1299 | |
e4303b25 | 1300 | if (nfc_is_v1()) { |
63f1474c | 1301 | if (cpu_is_mx21()) |
f48d0f9a UKK |
1302 | host->devtype_data = &imx21_nand_devtype_data; |
1303 | else | |
1304 | host->devtype_data = &imx27_nand_devtype_data; | |
e4303b25 UKK |
1305 | } else if (nfc_is_v21()) { |
1306 | host->devtype_data = &imx25_nand_devtype_data; | |
71ec5155 | 1307 | } else if (nfc_is_v3_2()) { |
e4303b25 | 1308 | host->devtype_data = &imx51_nand_devtype_data; |
f48d0f9a UKK |
1309 | } else |
1310 | BUG(); | |
1311 | ||
1312 | if (host->devtype_data->regs_offset) | |
1313 | host->regs = host->base + host->devtype_data->regs_offset; | |
1314 | host->spare0 = host->base + host->devtype_data->spare0_offset; | |
1315 | if (host->devtype_data->axi_offset) | |
1316 | host->regs_axi = host->base + host->devtype_data->axi_offset; | |
1317 | ||
1318 | this->ecc.bytes = host->devtype_data->eccbytes; | |
1319 | host->eccsize = host->devtype_data->eccsize; | |
1320 | ||
1321 | this->select_chip = host->devtype_data->select_chip; | |
1322 | this->ecc.size = 512; | |
1323 | this->ecc.layout = host->devtype_data->ecclayout_512; | |
1324 | ||
1325 | if (host->devtype_data->needs_ip) { | |
71ec5155 SH |
1326 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1327 | if (!res) { | |
1328 | err = -ENODEV; | |
1329 | goto eirq; | |
1330 | } | |
1331 | host->regs_ip = ioremap(res->start, resource_size(res)); | |
1332 | if (!host->regs_ip) { | |
1333 | err = -ENOMEM; | |
1334 | goto eirq; | |
1335 | } | |
f48d0f9a | 1336 | } |
13e1add1 | 1337 | |
34f6e157 SH |
1338 | if (pdata->hw_ecc) { |
1339 | this->ecc.calculate = mxc_nand_calculate_ecc; | |
1340 | this->ecc.hwctl = mxc_nand_enable_hwecc; | |
69d023be | 1341 | this->ecc.correct = host->devtype_data->correct_data; |
34f6e157 | 1342 | this->ecc.mode = NAND_ECC_HW; |
34f6e157 | 1343 | } else { |
34f6e157 | 1344 | this->ecc.mode = NAND_ECC_SOFT; |
34f6e157 SH |
1345 | } |
1346 | ||
34f6e157 | 1347 | /* NAND bus width determines access funtions used by upper layer */ |
13e1add1 | 1348 | if (pdata->width == 2) |
34f6e157 | 1349 | this->options |= NAND_BUSWIDTH_16; |
34f6e157 | 1350 | |
f1372055 SH |
1351 | if (pdata->flash_bbt) { |
1352 | this->bbt_td = &bbt_main_descr; | |
1353 | this->bbt_md = &bbt_mirror_descr; | |
1354 | /* update flash based bbt */ | |
bb9ebd4e | 1355 | this->bbt_options |= NAND_BBT_USE_FLASH; |
34f6e157 SH |
1356 | } |
1357 | ||
63f1474c | 1358 | init_completion(&host->op_completion); |
d4840180 IC |
1359 | |
1360 | host->irq = platform_get_irq(pdev, 0); | |
1361 | ||
63f1474c | 1362 | /* |
e4303b25 UKK |
1363 | * Use host->devtype_data->irq_control() here instead of irq_control() |
1364 | * because we must not disable_irq_nosync without having requested the | |
1365 | * irq. | |
63f1474c | 1366 | */ |
e4303b25 | 1367 | host->devtype_data->irq_control(host, 0); |
63f1474c | 1368 | |
a47bfd2e | 1369 | err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host); |
d4840180 IC |
1370 | if (err) |
1371 | goto eirq; | |
1372 | ||
63f1474c | 1373 | /* |
8556958a UKK |
1374 | * Now that we "own" the interrupt make sure the interrupt mask bit is |
1375 | * cleared on i.MX21. Otherwise we can't read the interrupt status bit | |
1376 | * on this machine. | |
63f1474c | 1377 | */ |
f48d0f9a | 1378 | if (host->devtype_data->irqpending_quirk) { |
8556958a | 1379 | disable_irq_nosync(host->irq); |
e4303b25 | 1380 | host->devtype_data->irq_control(host, 1); |
8556958a | 1381 | } |
63f1474c | 1382 | |
bd3fd62e | 1383 | /* first scan to find the device and get the page size */ |
d178e3e8 | 1384 | if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) { |
bd3fd62e VB |
1385 | err = -ENXIO; |
1386 | goto escan; | |
1387 | } | |
34f6e157 | 1388 | |
6e85dfdc | 1389 | /* Call preset again, with correct writesize this time */ |
e4303b25 | 1390 | host->devtype_data->preset(mtd); |
6e85dfdc | 1391 | |
2d69c7fa | 1392 | if (mtd->writesize == 2048) |
6dcdf99d UKK |
1393 | this->ecc.layout = host->devtype_data->ecclayout_2k; |
1394 | else if (mtd->writesize == 4096) | |
1395 | this->ecc.layout = host->devtype_data->ecclayout_4k; | |
bd3fd62e VB |
1396 | |
1397 | /* second phase scan */ | |
1398 | if (nand_scan_tail(mtd)) { | |
34f6e157 SH |
1399 | err = -ENXIO; |
1400 | goto escan; | |
1401 | } | |
1402 | ||
6a918bad MD |
1403 | if (this->ecc.mode == NAND_ECC_HW) { |
1404 | if (nfc_is_v1()) | |
1405 | this->ecc.strength = 1; | |
1406 | else | |
1407 | this->ecc.strength = (host->eccsize == 4) ? 4 : 8; | |
1408 | } | |
1409 | ||
34f6e157 | 1410 | /* Register the partitions */ |
42d7fbe2 AB |
1411 | mtd_device_parse_register(mtd, part_probes, NULL, pdata->parts, |
1412 | pdata->nr_parts); | |
34f6e157 SH |
1413 | |
1414 | platform_set_drvdata(pdev, host); | |
1415 | ||
1416 | return 0; | |
1417 | ||
1418 | escan: | |
b258fd8d | 1419 | free_irq(host->irq, host); |
34f6e157 | 1420 | eirq: |
71ec5155 SH |
1421 | if (host->regs_ip) |
1422 | iounmap(host->regs_ip); | |
c6de7e1b | 1423 | iounmap(host->base); |
34f6e157 SH |
1424 | eres: |
1425 | clk_put(host->clk); | |
1426 | eclk: | |
1427 | kfree(host); | |
1428 | ||
1429 | return err; | |
1430 | } | |
1431 | ||
51eeb878 | 1432 | static int __devexit mxcnd_remove(struct platform_device *pdev) |
34f6e157 SH |
1433 | { |
1434 | struct mxc_nand_host *host = platform_get_drvdata(pdev); | |
1435 | ||
1436 | clk_put(host->clk); | |
1437 | ||
1438 | platform_set_drvdata(pdev, NULL); | |
1439 | ||
1440 | nand_release(&host->mtd); | |
b258fd8d | 1441 | free_irq(host->irq, host); |
71ec5155 SH |
1442 | if (host->regs_ip) |
1443 | iounmap(host->regs_ip); | |
c6de7e1b | 1444 | iounmap(host->base); |
34f6e157 SH |
1445 | kfree(host); |
1446 | ||
1447 | return 0; | |
1448 | } | |
1449 | ||
34f6e157 SH |
1450 | static struct platform_driver mxcnd_driver = { |
1451 | .driver = { | |
1452 | .name = DRIVER_NAME, | |
8d1fd16d | 1453 | .owner = THIS_MODULE, |
04dd0d3a | 1454 | }, |
daa0f15a | 1455 | .remove = __devexit_p(mxcnd_remove), |
34f6e157 SH |
1456 | }; |
1457 | ||
1458 | static int __init mxc_nd_init(void) | |
1459 | { | |
8541c118 | 1460 | return platform_driver_probe(&mxcnd_driver, mxcnd_probe); |
34f6e157 SH |
1461 | } |
1462 | ||
1463 | static void __exit mxc_nd_cleanup(void) | |
1464 | { | |
1465 | /* Unregister the device structure */ | |
1466 | platform_driver_unregister(&mxcnd_driver); | |
1467 | } | |
1468 | ||
1469 | module_init(mxc_nd_init); | |
1470 | module_exit(mxc_nd_cleanup); | |
1471 | ||
1472 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
1473 | MODULE_DESCRIPTION("MXC NAND MTD driver"); | |
1474 | MODULE_LICENSE("GPL"); |