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mxc nand: use buffers
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
CommitLineData
34f6e157
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h>
27#include <linux/interrupt.h>
28#include <linux/device.h>
29#include <linux/platform_device.h>
30#include <linux/clk.h>
31#include <linux/err.h>
32#include <linux/io.h>
33
34#include <asm/mach/flash.h>
35#include <mach/mxc_nand.h>
36
37#define DRIVER_NAME "mxc_nand"
38
39/* Addresses for NFC registers */
40#define NFC_BUF_SIZE 0xE00
41#define NFC_BUF_ADDR 0xE04
42#define NFC_FLASH_ADDR 0xE06
43#define NFC_FLASH_CMD 0xE08
44#define NFC_CONFIG 0xE0A
45#define NFC_ECC_STATUS_RESULT 0xE0C
46#define NFC_RSLTMAIN_AREA 0xE0E
47#define NFC_RSLTSPARE_AREA 0xE10
48#define NFC_WRPROT 0xE12
49#define NFC_UNLOCKSTART_BLKADDR 0xE14
50#define NFC_UNLOCKEND_BLKADDR 0xE16
51#define NFC_NF_WRPRST 0xE18
52#define NFC_CONFIG1 0xE1A
53#define NFC_CONFIG2 0xE1C
54
55/* Addresses for NFC RAM BUFFER Main area 0 */
56#define MAIN_AREA0 0x000
57#define MAIN_AREA1 0x200
58#define MAIN_AREA2 0x400
59#define MAIN_AREA3 0x600
60
61/* Addresses for NFC SPARE BUFFER Spare area 0 */
62#define SPARE_AREA0 0x800
63#define SPARE_AREA1 0x810
64#define SPARE_AREA2 0x820
65#define SPARE_AREA3 0x830
66
67/* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
68 * for Command operation */
69#define NFC_CMD 0x1
70
71/* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
72 * for Address operation */
73#define NFC_ADDR 0x2
74
75/* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
76 * for Input operation */
77#define NFC_INPUT 0x4
78
79/* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
80 * for Data Output operation */
81#define NFC_OUTPUT 0x8
82
83/* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
84 * for Read ID operation */
85#define NFC_ID 0x10
86
87/* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
88 * for Read Status operation */
89#define NFC_STATUS 0x20
90
91/* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
92 * Status operation */
93#define NFC_INT 0x8000
94
95#define NFC_SP_EN (1 << 2)
96#define NFC_ECC_EN (1 << 3)
97#define NFC_INT_MSK (1 << 4)
98#define NFC_BIG (1 << 5)
99#define NFC_RST (1 << 6)
100#define NFC_CE (1 << 7)
101#define NFC_ONE_CYCLE (1 << 8)
102
103struct mxc_nand_host {
104 struct mtd_info mtd;
105 struct nand_chip nand;
106 struct mtd_partition *parts;
107 struct device *dev;
108
109 void __iomem *regs;
34f6e157
SH		 110 int status_request;
111 int pagesize_2k;
34f6e157
SH		 112 struct clk *clk;
113 int clk_act;
114 int irq;
115
116 wait_queue_head_t irq_waitq;
f8f9608d
SH		 117
118 uint8_t *data_buf;
119 unsigned int buf_start;
120 int spare_len;
34f6e157
SH		 121};
122
123/* Define delays in microsec for NAND device operations */
124#define TROP_US_DELAY 2000
125/* Macros to get byte and bit positions of ECC */
126#define COLPOS(x) ((x) >> 3)
127#define BITPOS(x) ((x) & 0xf)
128
129/* Define single bit Error positions in Main & Spare area */
130#define MAIN_SINGLEBIT_ERROR 0x4
131#define SPARE_SINGLEBIT_ERROR 0x1
132
133/* OOB placement block for use with hardware ecc generation */
8c1fd89a 134static struct nand_ecclayout nand_hw_eccoob_smallpage = {
34f6e157
SH		 135 .eccbytes = 5,
136 .eccpos = {6, 7, 8, 9, 10},
8c1fd89a 137 .oobfree = {{0, 5}, {12, 4}, }
34f6e157
SH		 138};
139
8c1fd89a 140static struct nand_ecclayout nand_hw_eccoob_largepage = {
bd3fd62e
VB		 141 .eccbytes = 20,
142 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
143 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
144 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
34f6e157
SH		 145};
146
147#ifdef CONFIG_MTD_PARTITIONS
148static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
149#endif
150
151static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
152{
153 struct mxc_nand_host *host = dev_id;
154
155 uint16_t tmp;
156
157 tmp = readw(host->regs + NFC_CONFIG1);
158 tmp |= NFC_INT_MSK; /* Disable interrupt */
159 writew(tmp, host->regs + NFC_CONFIG1);
160
161 wake_up(&host->irq_waitq);
162
163 return IRQ_HANDLED;
164}
165
166/* This function polls the NANDFC to wait for the basic operation to
167 * complete by checking the INT bit of config2 register.
168 */
169static void wait_op_done(struct mxc_nand_host *host, int max_retries,
62465491 170 int useirq)
34f6e157
SH		 171{
172 uint32_t tmp;
173
174 if (useirq) {
175 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
176
177 tmp = readw(host->regs + NFC_CONFIG1);
178 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
179 writew(tmp, host->regs + NFC_CONFIG1);
180
181 wait_event(host->irq_waitq,
182 readw(host->regs + NFC_CONFIG2) & NFC_INT);
183
184 tmp = readw(host->regs + NFC_CONFIG2);
185 tmp &= ~NFC_INT;
186 writew(tmp, host->regs + NFC_CONFIG2);
187 }
188 } else {
189 while (max_retries-- > 0) {
190 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
191 tmp = readw(host->regs + NFC_CONFIG2);
192 tmp &= ~NFC_INT;
193 writew(tmp, host->regs + NFC_CONFIG2);
194 break;
195 }
196 udelay(1);
197 }
43950a60 198 if (max_retries < 0)
62465491
SH		 199 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
200 __func__);
34f6e157
SH		 201 }
202}
203
204/* This function issues the specified command to the NAND device and
205 * waits for completion. */
206static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
207{
208 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
209
210 writew(cmd, host->regs + NFC_FLASH_CMD);
211 writew(NFC_CMD, host->regs + NFC_CONFIG2);
212
213 /* Wait for operation to complete */
62465491 214 wait_op_done(host, TROP_US_DELAY, useirq);
34f6e157
SH		 215}
216
217/* This function sends an address (or partial address) to the
218 * NAND device. The address is used to select the source/destination for
219 * a NAND command. */
220static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
221{
222 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
223
224 writew(addr, host->regs + NFC_FLASH_ADDR);
225 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
226
227 /* Wait for operation to complete */
62465491 228 wait_op_done(host, TROP_US_DELAY, islast);
34f6e157
SH		 229}
230
06ecb04a 231static void send_page(struct mxc_nand_host *host, uint8_t buf_id,
f8f9608d 232 unsigned int ops)
34f6e157 233{
34f6e157
SH		 234 /* NANDFC buffer 0 is used for page read/write */
235 writew(buf_id, host->regs + NFC_BUF_ADDR);
236
06ecb04a 237 writew(ops, host->regs + NFC_CONFIG2);
34f6e157
SH		 238
239 /* Wait for operation to complete */
62465491 240 wait_op_done(host, TROP_US_DELAY, true);
34f6e157
SH		 241}
242
243/* Request the NANDFC to perform a read of the NAND device ID. */
244static void send_read_id(struct mxc_nand_host *host)
245{
246 struct nand_chip *this = &host->nand;
247 uint16_t tmp;
248
249 /* NANDFC buffer 0 is used for device ID output */
250 writew(0x0, host->regs + NFC_BUF_ADDR);
251
252 /* Read ID into main buffer */
253 tmp = readw(host->regs + NFC_CONFIG1);
254 tmp &= ~NFC_SP_EN;
255 writew(tmp, host->regs + NFC_CONFIG1);
256
257 writew(NFC_ID, host->regs + NFC_CONFIG2);
258
259 /* Wait for operation to complete */
62465491 260 wait_op_done(host, TROP_US_DELAY, true);
34f6e157
SH		 261
262 if (this->options & NAND_BUSWIDTH_16) {
263 void __iomem *main_buf = host->regs + MAIN_AREA0;
264 /* compress the ID info */
265 writeb(readb(main_buf + 2), main_buf + 1);
266 writeb(readb(main_buf + 4), main_buf + 2);
267 writeb(readb(main_buf + 6), main_buf + 3);
268 writeb(readb(main_buf + 8), main_buf + 4);
269 writeb(readb(main_buf + 10), main_buf + 5);
270 }
f8f9608d 271 memcpy(host->data_buf, host->regs + MAIN_AREA0, 16);
34f6e157
SH		 272}
273
274/* This function requests the NANDFC to perform a read of the
275 * NAND device status and returns the current status. */
276static uint16_t get_dev_status(struct mxc_nand_host *host)
277{
278 void __iomem *main_buf = host->regs + MAIN_AREA1;
279 uint32_t store;
280 uint16_t ret, tmp;
281 /* Issue status request to NAND device */
282
283 /* store the main area1 first word, later do recovery */
284 store = readl(main_buf);
285 /* NANDFC buffer 1 is used for device status to prevent
286 * corruption of read/write buffer on status requests. */
287 writew(1, host->regs + NFC_BUF_ADDR);
288
289 /* Read status into main buffer */
290 tmp = readw(host->regs + NFC_CONFIG1);
291 tmp &= ~NFC_SP_EN;
292 writew(tmp, host->regs + NFC_CONFIG1);
293
294 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
295
296 /* Wait for operation to complete */
62465491 297 wait_op_done(host, TROP_US_DELAY, true);
34f6e157
SH		 298
299 /* Status is placed in first word of main buffer */
300 /* get status, then recovery area 1 data */
301 ret = readw(main_buf);
302 writel(store, main_buf);
303
304 return ret;
305}
306
307/* This functions is used by upper layer to checks if device is ready */
308static int mxc_nand_dev_ready(struct mtd_info *mtd)
309{
310 /*
311 * NFC handles R/B internally. Therefore, this function
312 * always returns status as ready.
313 */
314 return 1;
315}
316
317static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
318{
319 /*
320 * If HW ECC is enabled, we turn it on during init. There is
321 * no need to enable again here.
322 */
323}
324
325static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
326 u_char *read_ecc, u_char *calc_ecc)
327{
328 struct nand_chip *nand_chip = mtd->priv;
329 struct mxc_nand_host *host = nand_chip->priv;
330
331 /*
332 * 1-Bit errors are automatically corrected in HW. No need for
333 * additional correction. 2-Bit errors cannot be corrected by
334 * HW ECC, so we need to return failure
335 */
336 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
337
338 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
339 DEBUG(MTD_DEBUG_LEVEL0,
340 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
341 return -1;
342 }
343
344 return 0;
345}
346
347static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
348 u_char *ecc_code)
349{
350 return 0;
351}
352
353static u_char mxc_nand_read_byte(struct mtd_info *mtd)
354{
355 struct nand_chip *nand_chip = mtd->priv;
356 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d 357 uint8_t ret;
34f6e157
SH		 358
359 /* Check for status request */
360 if (host->status_request)
361 return get_dev_status(host) & 0xFF;
362
f8f9608d
SH		 363 ret = *(uint8_t *)(host->data_buf + host->buf_start);
364 host->buf_start++;
34f6e157
SH		 365
366 return ret;
367}
368
369static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
370{
371 struct nand_chip *nand_chip = mtd->priv;
372 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d 373 uint16_t ret;
34f6e157 374
f8f9608d
SH		 375 ret = *(uint16_t *)(host->data_buf + host->buf_start);
376 host->buf_start += 2;
34f6e157
SH		 377
378 return ret;
379}
380
381/* Write data of length len to buffer buf. The data to be
382 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
383 * Operation by the NFC, the data is written to NAND Flash */
384static void mxc_nand_write_buf(struct mtd_info *mtd,
385 const u_char *buf, int len)
386{
387 struct nand_chip *nand_chip = mtd->priv;
388 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d
SH		 389 u16 col = host->buf_start;
390 int n = mtd->oobsize + mtd->writesize - col;
34f6e157 391
f8f9608d 392 n = min(n, len);
34f6e157 393
f8f9608d 394 memcpy(host->data_buf + col, buf, n);
34f6e157 395
f8f9608d 396 host->buf_start += n;
34f6e157
SH		 397}
398
399/* Read the data buffer from the NAND Flash. To read the data from NAND
400 * Flash first the data output cycle is initiated by the NFC, which copies
401 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
402 */
403static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
404{
405 struct nand_chip *nand_chip = mtd->priv;
406 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d
SH		 407 u16 col = host->buf_start;
408 int n = mtd->oobsize + mtd->writesize - col;
34f6e157 409
f8f9608d 410 n = min(n, len);
34f6e157 411
f8f9608d 412 memcpy(buf, host->data_buf + col, len);
34f6e157 413
f8f9608d 414 host->buf_start += len;
34f6e157
SH		 415}
416
417/* Used by the upper layer to verify the data in NAND Flash
418 * with the data in the buf. */
419static int mxc_nand_verify_buf(struct mtd_info *mtd,
420 const u_char *buf, int len)
421{
422 return -EFAULT;
423}
424
425/* This function is used by upper layer for select and
426 * deselect of the NAND chip */
427static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
428{
429 struct nand_chip *nand_chip = mtd->priv;
430 struct mxc_nand_host *host = nand_chip->priv;
431
34f6e157
SH		 432 switch (chip) {
433 case -1:
434 /* Disable the NFC clock */
435 if (host->clk_act) {
436 clk_disable(host->clk);
437 host->clk_act = 0;
438 }
439 break;
440 case 0:
441 /* Enable the NFC clock */
442 if (!host->clk_act) {
443 clk_enable(host->clk);
444 host->clk_act = 1;
445 }
446 break;
447
448 default:
449 break;
450 }
451}
452
f8f9608d
SH		 453/*
454 * Function to transfer data to/from spare area.
455 */
456static void copy_spare(struct mtd_info *mtd, bool bfrom)
457{
458 struct nand_chip *this = mtd->priv;
459 struct mxc_nand_host *host = this->priv;
460 u16 i, j;
461 u16 n = mtd->writesize >> 9;
462 u8 *d = host->data_buf + mtd->writesize;
463 u8 *s = host->regs + SPARE_AREA0;
464 u16 t = host->spare_len;
465
466 j = (mtd->oobsize / n >> 1) << 1;
467
468 if (bfrom) {
469 for (i = 0; i < n - 1; i++)
470 memcpy(d + i * j, s + i * t, j);
471
472 /* the last section */
473 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
474 } else {
475 for (i = 0; i < n - 1; i++)
476 memcpy(&s[i * t], &d[i * j], j);
477
478 /* the last section */
479 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
480 }
481}
482
a3e65b64
SH		 483static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
484{
485 struct nand_chip *nand_chip = mtd->priv;
486 struct mxc_nand_host *host = nand_chip->priv;
487
488 /* Write out column address, if necessary */
489 if (column != -1) {
490 /*
491 * MXC NANDFC can only perform full page+spare or
492 * spare-only read/write. When the upper layers
493 * layers perform a read/write buf operation,
494 * we will used the saved column adress to index into
495 * the full page.
496 */
497 send_addr(host, 0, page_addr == -1);
498 if (host->pagesize_2k)
499 /* another col addr cycle for 2k page */
500 send_addr(host, 0, false);
501 }
502
503 /* Write out page address, if necessary */
504 if (page_addr != -1) {
505 /* paddr_0 - p_addr_7 */
506 send_addr(host, (page_addr & 0xff), false);
507
508 if (host->pagesize_2k) {
509 if (mtd->size >= 0x10000000) {
510 /* paddr_8 - paddr_15 */
511 send_addr(host, (page_addr >> 8) & 0xff, false);
512 send_addr(host, (page_addr >> 16) & 0xff, true);
513 } else
514 /* paddr_8 - paddr_15 */
515 send_addr(host, (page_addr >> 8) & 0xff, true);
516 } else {
517 /* One more address cycle for higher density devices */
518 if (mtd->size >= 0x4000000) {
519 /* paddr_8 - paddr_15 */
520 send_addr(host, (page_addr >> 8) & 0xff, false);
521 send_addr(host, (page_addr >> 16) & 0xff, true);
522 } else
523 /* paddr_8 - paddr_15 */
524 send_addr(host, (page_addr >> 8) & 0xff, true);
525 }
526 }
527}
528
34f6e157
SH		 529/* Used by the upper layer to write command to NAND Flash for
530 * different operations to be carried out on NAND Flash */
531static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
532 int column, int page_addr)
533{
534 struct nand_chip *nand_chip = mtd->priv;
535 struct mxc_nand_host *host = nand_chip->priv;
536 int useirq = true;
537
538 DEBUG(MTD_DEBUG_LEVEL3,
539 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
540 command, column, page_addr);
541
542 /* Reset command state information */
543 host->status_request = false;
544
545 /* Command pre-processing step */
546 switch (command) {
547
548 case NAND_CMD_STATUS:
f8f9608d 549 host->buf_start = 0;
34f6e157
SH		 550 host->status_request = true;
551 break;
552
553 case NAND_CMD_READ0:
f8f9608d 554 host->buf_start = column;
34f6e157
SH		 555 useirq = false;
556 break;
557
558 case NAND_CMD_READOOB:
f8f9608d
SH		 559 host->buf_start = column + mtd->writesize;
560
34f6e157
SH		 561 useirq = false;
562 if (host->pagesize_2k)
563 command = NAND_CMD_READ0; /* only READ0 is valid */
564 break;
565
566 case NAND_CMD_SEQIN:
567 if (column >= mtd->writesize) {
568 /*
569 * FIXME: before send SEQIN command for write OOB,
570 * We must read one page out.
571 * For K9F1GXX has no READ1 command to set current HW
572 * pointer to spare area, we must write the whole page
573 * including OOB together.
574 */
575 if (host->pagesize_2k)
576 /* call ourself to read a page */
577 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
578 page_addr);
579
f8f9608d 580 host->buf_start = column;
34f6e157
SH		 581
582 /* Set program pointer to spare region */
583 if (!host->pagesize_2k)
584 send_cmd(host, NAND_CMD_READOOB, false);
585 } else {
f8f9608d 586 host->buf_start = column;
34f6e157
SH		 587
588 /* Set program pointer to page start */
589 if (!host->pagesize_2k)
590 send_cmd(host, NAND_CMD_READ0, false);
591 }
592 useirq = false;
593 break;
594
595 case NAND_CMD_PAGEPROG:
f8f9608d
SH		 596 memcpy(host->regs + MAIN_AREA0, host->data_buf, mtd->writesize);
597 copy_spare(mtd, false);
598 send_page(host, 0, NFC_INPUT);
34f6e157
SH		 599
600 if (host->pagesize_2k) {
601 /* data in 4 areas datas */
f8f9608d
SH		 602 send_page(host, 1, NFC_INPUT);
603 send_page(host, 2, NFC_INPUT);
604 send_page(host, 3, NFC_INPUT);
34f6e157
SH		 605 }
606
607 break;
608
609 case NAND_CMD_ERASE1:
610 useirq = false;
611 break;
612 }
613
614 /* Write out the command to the device. */
615 send_cmd(host, command, useirq);
a3e65b64 616 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 617
618 /* Command post-processing step */
619 switch (command) {
620
621 case NAND_CMD_RESET:
622 break;
623
624 case NAND_CMD_READOOB:
625 case NAND_CMD_READ0:
626 if (host->pagesize_2k) {
627 /* send read confirm command */
628 send_cmd(host, NAND_CMD_READSTART, true);
629 /* read for each AREA */
f8f9608d
SH		 630 send_page(host, 0, NFC_OUTPUT);
631 send_page(host, 1, NFC_OUTPUT);
632 send_page(host, 2, NFC_OUTPUT);
633 send_page(host, 3, NFC_OUTPUT);
34f6e157 634 } else
f8f9608d
SH		 635 send_page(host, 0, NFC_OUTPUT);
636
637 memcpy(host->data_buf, host->regs + MAIN_AREA0, mtd->writesize);
638 copy_spare(mtd, true);
34f6e157
SH		 639 break;
640
641 case NAND_CMD_READID:
642 send_read_id(host);
643 break;
644
645 case NAND_CMD_PAGEPROG:
646 break;
647
648 case NAND_CMD_STATUS:
649 break;
650
651 case NAND_CMD_ERASE2:
652 break;
653 }
654}
655
656static int __init mxcnd_probe(struct platform_device *pdev)
657{
658 struct nand_chip *this;
659 struct mtd_info *mtd;
660 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
661 struct mxc_nand_host *host;
662 struct resource *res;
663 uint16_t tmp;
664 int err = 0, nr_parts = 0;
665
666 /* Allocate memory for MTD device structure and private data */
f8f9608d
SH		 667 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
668 NAND_MAX_OOBSIZE, GFP_KERNEL);
34f6e157
SH		 669 if (!host)
670 return -ENOMEM;
671
f8f9608d
SH		 672 host->data_buf = (uint8_t *)(host + 1);
673 host->spare_len = 16;
674
34f6e157
SH		 675 host->dev = &pdev->dev;
676 /* structures must be linked */
677 this = &host->nand;
678 mtd = &host->mtd;
679 mtd->priv = this;
680 mtd->owner = THIS_MODULE;
87f39f04 681 mtd->dev.parent = &pdev->dev;
8541c118 682 mtd->name = "mxc_nand";
34f6e157
SH		 683
684 /* 50 us command delay time */
685 this->chip_delay = 5;
686
687 this->priv = host;
688 this->dev_ready = mxc_nand_dev_ready;
689 this->cmdfunc = mxc_nand_command;
690 this->select_chip = mxc_nand_select_chip;
691 this->read_byte = mxc_nand_read_byte;
692 this->read_word = mxc_nand_read_word;
693 this->write_buf = mxc_nand_write_buf;
694 this->read_buf = mxc_nand_read_buf;
695 this->verify_buf = mxc_nand_verify_buf;
696
e65fb009 697 host->clk = clk_get(&pdev->dev, "nfc");
8541c118
VB		 698 if (IS_ERR(host->clk)) {
699 err = PTR_ERR(host->clk);
34f6e157 700 goto eclk;
8541c118 701 }
34f6e157
SH		 702
703 clk_enable(host->clk);
704 host->clk_act = 1;
705
706 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
707 if (!res) {
708 err = -ENODEV;
709 goto eres;
710 }
711
d970a073 712 host->regs = ioremap(res->start, resource_size(res));
34f6e157 713 if (!host->regs) {
8541c118 714 err = -ENOMEM;
34f6e157
SH		 715 goto eres;
716 }
717
718 tmp = readw(host->regs + NFC_CONFIG1);
719 tmp |= NFC_INT_MSK;
720 writew(tmp, host->regs + NFC_CONFIG1);
721
722 init_waitqueue_head(&host->irq_waitq);
723
724 host->irq = platform_get_irq(pdev, 0);
725
726 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
727 if (err)
728 goto eirq;
729
13e1add1
SH		 730 /* Reset NAND */
731 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
732
733 /* preset operation */
734 /* Unlock the internal RAM Buffer */
735 writew(0x2, host->regs + NFC_CONFIG);
736
737 /* Blocks to be unlocked */
738 writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
739 writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
740
741 /* Unlock Block Command for given address range */
742 writew(0x4, host->regs + NFC_WRPROT);
743
744 this->ecc.size = 512;
745 this->ecc.bytes = 3;
746 this->ecc.layout = &nand_hw_eccoob_smallpage;
747
34f6e157
SH		 748 if (pdata->hw_ecc) {
749 this->ecc.calculate = mxc_nand_calculate_ecc;
750 this->ecc.hwctl = mxc_nand_enable_hwecc;
751 this->ecc.correct = mxc_nand_correct_data;
752 this->ecc.mode = NAND_ECC_HW;
34f6e157
SH		 753 tmp = readw(host->regs + NFC_CONFIG1);
754 tmp |= NFC_ECC_EN;
755 writew(tmp, host->regs + NFC_CONFIG1);
756 } else {
34f6e157
SH		 757 this->ecc.mode = NAND_ECC_SOFT;
758 tmp = readw(host->regs + NFC_CONFIG1);
759 tmp &= ~NFC_ECC_EN;
760 writew(tmp, host->regs + NFC_CONFIG1);
761 }
762
34f6e157 763 /* NAND bus width determines access funtions used by upper layer */
13e1add1 764 if (pdata->width == 2)
34f6e157 765 this->options |= NAND_BUSWIDTH_16;
34f6e157 766
bd3fd62e
VB		 767 /* first scan to find the device and get the page size */
768 if (nand_scan_ident(mtd, 1)) {
769 err = -ENXIO;
770 goto escan;
771 }
34f6e157 772
13e1add1
SH		 773 if (mtd->writesize == 2048) {
774 host->pagesize_2k = 1;
775 this->ecc.layout = &nand_hw_eccoob_largepage;
bd3fd62e
VB		 776 }
777
778 /* second phase scan */
779 if (nand_scan_tail(mtd)) {
34f6e157
SH		 780 err = -ENXIO;
781 goto escan;
782 }
783
784 /* Register the partitions */
785#ifdef CONFIG_MTD_PARTITIONS
786 nr_parts =
787 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
788 if (nr_parts > 0)
789 add_mtd_partitions(mtd, host->parts, nr_parts);
790 else
791#endif
792 {
793 pr_info("Registering %s as whole device\n", mtd->name);
794 add_mtd_device(mtd);
795 }
796
797 platform_set_drvdata(pdev, host);
798
799 return 0;
800
801escan:
b258fd8d 802 free_irq(host->irq, host);
34f6e157
SH		 803eirq:
804 iounmap(host->regs);
805eres:
806 clk_put(host->clk);
807eclk:
808 kfree(host);
809
810 return err;
811}
812
82613b0d 813static int __exit mxcnd_remove(struct platform_device *pdev)
34f6e157
SH		 814{
815 struct mxc_nand_host *host = platform_get_drvdata(pdev);
816
817 clk_put(host->clk);
818
819 platform_set_drvdata(pdev, NULL);
820
821 nand_release(&host->mtd);
b258fd8d 822 free_irq(host->irq, host);
34f6e157
SH		 823 iounmap(host->regs);
824 kfree(host);
825
826 return 0;
827}
828
829#ifdef CONFIG_PM
830static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
831{
8541c118
VB		 832 struct mtd_info *mtd = platform_get_drvdata(pdev);
833 struct nand_chip *nand_chip = mtd->priv;
834 struct mxc_nand_host *host = nand_chip->priv;
34f6e157
SH		 835 int ret = 0;
836
837 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
8541c118
VB		 838 if (mtd) {
839 ret = mtd->suspend(mtd);
840 /* Disable the NFC clock */
841 clk_disable(host->clk);
842 }
34f6e157
SH		 843
844 return ret;
845}
846
847static int mxcnd_resume(struct platform_device *pdev)
848{
8541c118
VB		 849 struct mtd_info *mtd = platform_get_drvdata(pdev);
850 struct nand_chip *nand_chip = mtd->priv;
851 struct mxc_nand_host *host = nand_chip->priv;
34f6e157
SH		 852 int ret = 0;
853
854 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
34f6e157 855
8541c118
VB		 856 if (mtd) {
857 /* Enable the NFC clock */
858 clk_enable(host->clk);
859 mtd->resume(mtd);
860 }
34f6e157 861
34f6e157
SH		 862 return ret;
863}
864
865#else
866# define mxcnd_suspend NULL
867# define mxcnd_resume NULL
868#endif /* CONFIG_PM */
869
870static struct platform_driver mxcnd_driver = {
871 .driver = {
872 .name = DRIVER_NAME,
873 },
874 .remove = __exit_p(mxcnd_remove),
875 .suspend = mxcnd_suspend,
876 .resume = mxcnd_resume,
877};
878
879static int __init mxc_nd_init(void)
880{
8541c118 881 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
34f6e157
SH		 882}
883
884static void __exit mxc_nd_cleanup(void)
885{
886 /* Unregister the device structure */
887 platform_driver_unregister(&mxcnd_driver);
888}
889
890module_init(mxc_nd_init);
891module_exit(mxc_nd_cleanup);
892
893MODULE_AUTHOR("Freescale Semiconductor, Inc.");
894MODULE_DESCRIPTION("MXC NAND MTD driver");
895MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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