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mtd: nand: Fix integer overflow in ONFI detection of chips >= 4GiB
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
1da177e4
LT		 45#include <linux/interrupt.h>
46#include <linux/bitops.h>
8fe833c1 47#include <linux/leds.h>
7351d3a5 48#include <linux/io.h>
1da177e4
LT		 49
50#ifdef CONFIG_MTD_PARTITIONS
51#include <linux/mtd/partitions.h>
52#endif
53
54/* Define default oob placement schemes for large and small page devices */
5bd34c09 55static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 56 .eccbytes = 3,
57 .eccpos = {0, 1, 2},
5bd34c09
TG		 58 .oobfree = {
59 {.offset = 3,
60 .length = 2},
61 {.offset = 6,
f8ac0414 62 .length = 2} }
1da177e4
LT		 63};
64
5bd34c09 65static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 66 .eccbytes = 6,
67 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 68 .oobfree = {
69 {.offset = 8,
f8ac0414 70 . length = 8} }
1da177e4
LT		 71};
72
5bd34c09 73static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 74 .eccbytes = 24,
75 .eccpos = {
e0c7d767
DW		 76 40, 41, 42, 43, 44, 45, 46, 47,
77 48, 49, 50, 51, 52, 53, 54, 55,
78 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 79 .oobfree = {
80 {.offset = 2,
f8ac0414 81 .length = 38} }
1da177e4
LT		 82};
83
81ec5364
TG		 84static struct nand_ecclayout nand_oob_128 = {
85 .eccbytes = 48,
86 .eccpos = {
87 80, 81, 82, 83, 84, 85, 86, 87,
88 88, 89, 90, 91, 92, 93, 94, 95,
89 96, 97, 98, 99, 100, 101, 102, 103,
90 104, 105, 106, 107, 108, 109, 110, 111,
91 112, 113, 114, 115, 116, 117, 118, 119,
92 120, 121, 122, 123, 124, 125, 126, 127},
93 .oobfree = {
94 {.offset = 2,
f8ac0414 95 .length = 78} }
81ec5364
TG		 96};
97
ace4dfee 98static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 99 int new_state);
1da177e4 100
8593fbc6
TG		 101static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
102 struct mtd_oob_ops *ops);
103
d470a97c 104/*
8e87d782 105 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 106 * compiled away when LED support is disabled.
107 */
108DEFINE_LED_TRIGGER(nand_led_trigger);
109
6fe5a6ac
VS		 110static int check_offs_len(struct mtd_info *mtd,
111 loff_t ofs, uint64_t len)
112{
113 struct nand_chip *chip = mtd->priv;
114 int ret = 0;
115
116 /* Start address must align on block boundary */
117 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
118 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
119 ret = -EINVAL;
120 }
121
122 /* Length must align on block boundary */
123 if (len & ((1 << chip->phys_erase_shift) - 1)) {
124 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
125 __func__);
126 ret = -EINVAL;
127 }
128
129 /* Do not allow past end of device */
130 if (ofs + len > mtd->size) {
131 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
132 __func__);
133 ret = -EINVAL;
134 }
135
136 return ret;
137}
138
1da177e4
LT		 139/**
140 * nand_release_device - [GENERIC] release chip
141 * @mtd: MTD device structure
61b03bd7
TG		 142 *
143 * Deselect, release chip lock and wake up anyone waiting on the device
1da177e4 144 */
e0c7d767 145static void nand_release_device(struct mtd_info *mtd)
1da177e4 146{
ace4dfee 147 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 148
149 /* De-select the NAND device */
ace4dfee 150 chip->select_chip(mtd, -1);
0dfc6246 151
a36ed299 152 /* Release the controller and the chip */
ace4dfee
TG		 153 spin_lock(&chip->controller->lock);
154 chip->controller->active = NULL;
155 chip->state = FL_READY;
156 wake_up(&chip->controller->wq);
157 spin_unlock(&chip->controller->lock);
1da177e4
LT		 158}
159
160/**
161 * nand_read_byte - [DEFAULT] read one byte from the chip
162 * @mtd: MTD device structure
163 *
164 * Default read function for 8bit buswith
165 */
58dd8f2b 166static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 167{
ace4dfee
TG		 168 struct nand_chip *chip = mtd->priv;
169 return readb(chip->IO_ADDR_R);
1da177e4
LT		 170}
171
1da177e4
LT		 172/**
173 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
174 * @mtd: MTD device structure
175 *
61b03bd7 176 * Default read function for 16bit buswith with
1da177e4
LT		 177 * endianess conversion
178 */
58dd8f2b 179static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 180{
ace4dfee
TG		 181 struct nand_chip *chip = mtd->priv;
182 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 183}
184
1da177e4
LT		 185/**
186 * nand_read_word - [DEFAULT] read one word from the chip
187 * @mtd: MTD device structure
188 *
61b03bd7 189 * Default read function for 16bit buswith without
1da177e4
LT		 190 * endianess conversion
191 */
192static u16 nand_read_word(struct mtd_info *mtd)
193{
ace4dfee
TG		 194 struct nand_chip *chip = mtd->priv;
195 return readw(chip->IO_ADDR_R);
1da177e4
LT		 196}
197
1da177e4
LT		 198/**
199 * nand_select_chip - [DEFAULT] control CE line
200 * @mtd: MTD device structure
844d3b42 201 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 202 *
203 * Default select function for 1 chip devices.
204 */
ace4dfee 205static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 206{
ace4dfee
TG		 207 struct nand_chip *chip = mtd->priv;
208
209 switch (chipnr) {
1da177e4 210 case -1:
ace4dfee 211 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 212 break;
213 case 0:
1da177e4
LT		 214 break;
215
216 default:
217 BUG();
218 }
219}
220
221/**
222 * nand_write_buf - [DEFAULT] write buffer to chip
223 * @mtd: MTD device structure
224 * @buf: data buffer
225 * @len: number of bytes to write
226 *
227 * Default write function for 8bit buswith
228 */
58dd8f2b 229static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 230{
231 int i;
ace4dfee 232 struct nand_chip *chip = mtd->priv;
1da177e4 233
e0c7d767 234 for (i = 0; i < len; i++)
ace4dfee 235 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 236}
237
238/**
61b03bd7 239 * nand_read_buf - [DEFAULT] read chip data into buffer
1da177e4
LT		 240 * @mtd: MTD device structure
241 * @buf: buffer to store date
242 * @len: number of bytes to read
243 *
244 * Default read function for 8bit buswith
245 */
58dd8f2b 246static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 247{
248 int i;
ace4dfee 249 struct nand_chip *chip = mtd->priv;
1da177e4 250
e0c7d767 251 for (i = 0; i < len; i++)
ace4dfee 252 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 253}
254
255/**
61b03bd7 256 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 257 * @mtd: MTD device structure
258 * @buf: buffer containing the data to compare
259 * @len: number of bytes to compare
260 *
261 * Default verify function for 8bit buswith
262 */
58dd8f2b 263static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 264{
265 int i;
ace4dfee 266 struct nand_chip *chip = mtd->priv;
1da177e4 267
e0c7d767 268 for (i = 0; i < len; i++)
ace4dfee 269 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 270 return -EFAULT;
1da177e4
LT		 271 return 0;
272}
273
274/**
275 * nand_write_buf16 - [DEFAULT] write buffer to chip
276 * @mtd: MTD device structure
277 * @buf: data buffer
278 * @len: number of bytes to write
279 *
280 * Default write function for 16bit buswith
281 */
58dd8f2b 282static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 283{
284 int i;
ace4dfee 285 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 286 u16 *p = (u16 *) buf;
287 len >>= 1;
61b03bd7 288
e0c7d767 289 for (i = 0; i < len; i++)
ace4dfee 290 writew(p[i], chip->IO_ADDR_W);
61b03bd7 291
1da177e4
LT		 292}
293
294/**
61b03bd7 295 * nand_read_buf16 - [DEFAULT] read chip data into buffer
1da177e4
LT		 296 * @mtd: MTD device structure
297 * @buf: buffer to store date
298 * @len: number of bytes to read
299 *
300 * Default read function for 16bit buswith
301 */
58dd8f2b 302static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 303{
304 int i;
ace4dfee 305 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 306 u16 *p = (u16 *) buf;
307 len >>= 1;
308
e0c7d767 309 for (i = 0; i < len; i++)
ace4dfee 310 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 311}
312
313/**
61b03bd7 314 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 315 * @mtd: MTD device structure
316 * @buf: buffer containing the data to compare
317 * @len: number of bytes to compare
318 *
319 * Default verify function for 16bit buswith
320 */
58dd8f2b 321static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 322{
323 int i;
ace4dfee 324 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 325 u16 *p = (u16 *) buf;
326 len >>= 1;
327
e0c7d767 328 for (i = 0; i < len; i++)
ace4dfee 329 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 330 return -EFAULT;
331
332 return 0;
333}
334
335/**
336 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
337 * @mtd: MTD device structure
338 * @ofs: offset from device start
339 * @getchip: 0, if the chip is already selected
340 *
61b03bd7 341 * Check, if the block is bad.
1da177e4
LT		 342 */
343static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
344{
345 int page, chipnr, res = 0;
ace4dfee 346 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 347 u16 bad;
348
30fe8115 349 if (chip->options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 350 ofs += mtd->erasesize - mtd->writesize;
351
1a12f46a
TK		 352 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
353
1da177e4 354 if (getchip) {
ace4dfee 355 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 356
ace4dfee 357 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 358
359 /* Select the NAND device */
ace4dfee 360 chip->select_chip(mtd, chipnr);
1a12f46a 361 }
1da177e4 362
ace4dfee
TG		 363 if (chip->options & NAND_BUSWIDTH_16) {
364 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 365 page);
ace4dfee
TG		 366 bad = cpu_to_le16(chip->read_word(mtd));
367 if (chip->badblockpos & 0x1)
49196f33 368 bad >>= 8;
e0b58d0a
ML		 369 else
370 bad &= 0xFF;
1da177e4 371 } else {
1a12f46a 372 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
e0b58d0a 373 bad = chip->read_byte(mtd);
1da177e4 374 }
61b03bd7 375
e0b58d0a
ML		 376 if (likely(chip->badblockbits == 8))
377 res = bad != 0xFF;
378 else
379 res = hweight8(bad) < chip->badblockbits;
380
ace4dfee 381 if (getchip)
1da177e4 382 nand_release_device(mtd);
61b03bd7 383
1da177e4
LT		 384 return res;
385}
386
387/**
388 * nand_default_block_markbad - [DEFAULT] mark a block bad
389 * @mtd: MTD device structure
390 * @ofs: offset from device start
391 *
392 * This is the default implementation, which can be overridden by
393 * a hardware specific driver.
394*/
395static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
396{
ace4dfee 397 struct nand_chip *chip = mtd->priv;
58dd8f2b 398 uint8_t buf[2] = { 0, 0 };
02ed70bb 399 int block, ret, i = 0;
61b03bd7 400
30fe8115 401 if (chip->options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 402 ofs += mtd->erasesize - mtd->writesize;
403
1da177e4 404 /* Get block number */
4226b510 405 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 406 if (chip->bbt)
407 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4
LT		 408
409 /* Do we have a flash based bad block table ? */
ace4dfee 410 if (chip->options & NAND_USE_FLASH_BBT)
f1a28c02
TG		 411 ret = nand_update_bbt(mtd, ofs);
412 else {
c0b8ba7b 413 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 414
02ed70bb
BN		 415 /* Write to first two pages and to byte 1 and 6 if necessary.
416 * If we write to more than one location, the first error
417 * encountered quits the procedure. We write two bytes per
418 * location, so we dont have to mess with 16 bit access.
419 */
420 do {
421 chip->ops.len = chip->ops.ooblen = 2;
422 chip->ops.datbuf = NULL;
423 chip->ops.oobbuf = buf;
424 chip->ops.ooboffs = chip->badblockpos & ~0x01;
425
426 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
427
428 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
429 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
430 & ~0x01;
431 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
432 }
433 i++;
434 ofs += mtd->writesize;
435 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
436 i < 2);
437
c0b8ba7b 438 nand_release_device(mtd);
f1a28c02
TG		 439 }
440 if (!ret)
441 mtd->ecc_stats.badblocks++;
c0b8ba7b 442
f1a28c02 443 return ret;
1da177e4
LT		 444}
445
61b03bd7 446/**
1da177e4
LT		 447 * nand_check_wp - [GENERIC] check if the chip is write protected
448 * @mtd: MTD device structure
61b03bd7 449 * Check, if the device is write protected
1da177e4 450 *
61b03bd7 451 * The function expects, that the device is already selected
1da177e4 452 */
e0c7d767 453static int nand_check_wp(struct mtd_info *mtd)
1da177e4 454{
ace4dfee 455 struct nand_chip *chip = mtd->priv;
93edbad6
ML		 456
457 /* broken xD cards report WP despite being writable */
458 if (chip->options & NAND_BROKEN_XD)
459 return 0;
460
1da177e4 461 /* Check the WP bit */
ace4dfee
TG		 462 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
463 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 464}
465
466/**
467 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
468 * @mtd: MTD device structure
469 * @ofs: offset from device start
470 * @getchip: 0, if the chip is already selected
471 * @allowbbt: 1, if its allowed to access the bbt area
472 *
473 * Check, if the block is bad. Either by reading the bad block table or
474 * calling of the scan function.
475 */
2c0a2bed
TG		 476static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
477 int allowbbt)
1da177e4 478{
ace4dfee 479 struct nand_chip *chip = mtd->priv;
61b03bd7 480
ace4dfee
TG		 481 if (!chip->bbt)
482 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 483
1da177e4 484 /* Return info from the table */
e0c7d767 485 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 486}
487
2af7c653
SK		 488/**
489 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
490 * @mtd: MTD device structure
491 * @timeo: Timeout
492 *
493 * Helper function for nand_wait_ready used when needing to wait in interrupt
494 * context.
495 */
496static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
497{
498 struct nand_chip *chip = mtd->priv;
499 int i;
500
501 /* Wait for the device to get ready */
502 for (i = 0; i < timeo; i++) {
503 if (chip->dev_ready(mtd))
504 break;
505 touch_softlockup_watchdog();
506 mdelay(1);
507 }
508}
509
61b03bd7 510/*
3b88775c
TG		 511 * Wait for the ready pin, after a command
512 * The timeout is catched later.
513 */
4b648b02 514void nand_wait_ready(struct mtd_info *mtd)
3b88775c 515{
ace4dfee 516 struct nand_chip *chip = mtd->priv;
e0c7d767 517 unsigned long timeo = jiffies + 2;
3b88775c 518
2af7c653
SK		 519 /* 400ms timeout */
520 if (in_interrupt() || oops_in_progress)
521 return panic_nand_wait_ready(mtd, 400);
522
8fe833c1 523 led_trigger_event(nand_led_trigger, LED_FULL);
3b88775c
TG		 524 /* wait until command is processed or timeout occures */
525 do {
ace4dfee 526 if (chip->dev_ready(mtd))
8fe833c1 527 break;
8446f1d3 528 touch_softlockup_watchdog();
61b03bd7 529 } while (time_before(jiffies, timeo));
8fe833c1 530 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 531}
4b648b02 532EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 533
1da177e4
LT		 534/**
535 * nand_command - [DEFAULT] Send command to NAND device
536 * @mtd: MTD device structure
537 * @command: the command to be sent
538 * @column: the column address for this command, -1 if none
539 * @page_addr: the page address for this command, -1 if none
540 *
541 * Send command to NAND device. This function is used for small page
542 * devices (256/512 Bytes per page)
543 */
7abd3ef9
TG		 544static void nand_command(struct mtd_info *mtd, unsigned int command,
545 int column, int page_addr)
1da177e4 546{
ace4dfee 547 register struct nand_chip *chip = mtd->priv;
7abd3ef9 548 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 549
1da177e4
LT		 550 /*
551 * Write out the command to the device.
552 */
553 if (command == NAND_CMD_SEQIN) {
554 int readcmd;
555
28318776 556 if (column >= mtd->writesize) {
1da177e4 557 /* OOB area */
28318776 558 column -= mtd->writesize;
1da177e4
LT		 559 readcmd = NAND_CMD_READOOB;
560 } else if (column < 256) {
561 /* First 256 bytes --> READ0 */
562 readcmd = NAND_CMD_READ0;
563 } else {
564 column -= 256;
565 readcmd = NAND_CMD_READ1;
566 }
ace4dfee 567 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 568 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 569 }
ace4dfee 570 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 571
7abd3ef9
TG		 572 /*
573 * Address cycle, when necessary
574 */
575 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
576 /* Serially input address */
577 if (column != -1) {
578 /* Adjust columns for 16 bit buswidth */
ace4dfee 579 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 580 column >>= 1;
ace4dfee 581 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 582 ctrl &= ~NAND_CTRL_CHANGE;
583 }
584 if (page_addr != -1) {
ace4dfee 585 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 586 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 587 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 588 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 589 if (chip->chipsize > (32 << 20))
590 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 591 }
ace4dfee 592 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 593
594 /*
595 * program and erase have their own busy handlers
1da177e4 596 * status and sequential in needs no delay
e0c7d767 597 */
1da177e4 598 switch (command) {
61b03bd7 599
1da177e4
LT		 600 case NAND_CMD_PAGEPROG:
601 case NAND_CMD_ERASE1:
602 case NAND_CMD_ERASE2:
603 case NAND_CMD_SEQIN:
604 case NAND_CMD_STATUS:
605 return;
606
607 case NAND_CMD_RESET:
ace4dfee 608 if (chip->dev_ready)
1da177e4 609 break;
ace4dfee
TG		 610 udelay(chip->chip_delay);
611 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 612 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 613 chip->cmd_ctrl(mtd,
614 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 615 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
616 ;
1da177e4
LT		 617 return;
618
e0c7d767 619 /* This applies to read commands */
1da177e4 620 default:
61b03bd7 621 /*
1da177e4
LT		 622 * If we don't have access to the busy pin, we apply the given
623 * command delay
e0c7d767 624 */
ace4dfee
TG		 625 if (!chip->dev_ready) {
626 udelay(chip->chip_delay);
1da177e4 627 return;
61b03bd7 628 }
1da177e4 629 }
1da177e4
LT		 630 /* Apply this short delay always to ensure that we do wait tWB in
631 * any case on any machine. */
e0c7d767 632 ndelay(100);
3b88775c
TG		 633
634 nand_wait_ready(mtd);
1da177e4
LT		 635}
636
637/**
638 * nand_command_lp - [DEFAULT] Send command to NAND large page device
639 * @mtd: MTD device structure
640 * @command: the command to be sent
641 * @column: the column address for this command, -1 if none
642 * @page_addr: the page address for this command, -1 if none
643 *
7abd3ef9
TG		 644 * Send command to NAND device. This is the version for the new large page
645 * devices We dont have the separate regions as we have in the small page
646 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 647 */
7abd3ef9
TG		 648static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
649 int column, int page_addr)
1da177e4 650{
ace4dfee 651 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 652
653 /* Emulate NAND_CMD_READOOB */
654 if (command == NAND_CMD_READOOB) {
28318776 655 column += mtd->writesize;
1da177e4
LT		 656 command = NAND_CMD_READ0;
657 }
61b03bd7 658
7abd3ef9 659 /* Command latch cycle */
ace4dfee 660 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 661 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 662
663 if (column != -1 || page_addr != -1) {
7abd3ef9 664 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 665
666 /* Serially input address */
667 if (column != -1) {
668 /* Adjust columns for 16 bit buswidth */
ace4dfee 669 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 670 column >>= 1;
ace4dfee 671 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 672 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 673 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 674 }
1da177e4 675 if (page_addr != -1) {
ace4dfee
TG		 676 chip->cmd_ctrl(mtd, page_addr, ctrl);
677 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 678 NAND_NCE | NAND_ALE);
1da177e4 679 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 680 if (chip->chipsize > (128 << 20))
681 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 682 NAND_NCE | NAND_ALE);
1da177e4 683 }
1da177e4 684 }
ace4dfee 685 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 686
687 /*
688 * program and erase have their own busy handlers
30f464b7
DM		 689 * status, sequential in, and deplete1 need no delay
690 */
1da177e4 691 switch (command) {
61b03bd7 692
1da177e4
LT		 693 case NAND_CMD_CACHEDPROG:
694 case NAND_CMD_PAGEPROG:
695 case NAND_CMD_ERASE1:
696 case NAND_CMD_ERASE2:
697 case NAND_CMD_SEQIN:
7bc3312b 698 case NAND_CMD_RNDIN:
1da177e4 699 case NAND_CMD_STATUS:
30f464b7 700 case NAND_CMD_DEPLETE1:
1da177e4
LT		 701 return;
702
e0c7d767
DW		 703 /*
704 * read error status commands require only a short delay
705 */
30f464b7
DM		 706 case NAND_CMD_STATUS_ERROR:
707 case NAND_CMD_STATUS_ERROR0:
708 case NAND_CMD_STATUS_ERROR1:
709 case NAND_CMD_STATUS_ERROR2:
710 case NAND_CMD_STATUS_ERROR3:
ace4dfee 711 udelay(chip->chip_delay);
30f464b7 712 return;
1da177e4
LT		 713
714 case NAND_CMD_RESET:
ace4dfee 715 if (chip->dev_ready)
1da177e4 716 break;
ace4dfee 717 udelay(chip->chip_delay);
12efdde3
TG		 718 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
719 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
720 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
721 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 722 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
723 ;
1da177e4
LT		 724 return;
725
7bc3312b
TG		 726 case NAND_CMD_RNDOUT:
727 /* No ready / busy check necessary */
728 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
729 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
730 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
731 NAND_NCE | NAND_CTRL_CHANGE);
732 return;
733
1da177e4 734 case NAND_CMD_READ0:
12efdde3
TG		 735 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
736 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
737 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
738 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 739
e0c7d767 740 /* This applies to read commands */
1da177e4 741 default:
61b03bd7 742 /*
1da177e4
LT		 743 * If we don't have access to the busy pin, we apply the given
744 * command delay
e0c7d767 745 */
ace4dfee
TG		 746 if (!chip->dev_ready) {
747 udelay(chip->chip_delay);
1da177e4 748 return;
61b03bd7 749 }
1da177e4 750 }
3b88775c 751
1da177e4
LT		 752 /* Apply this short delay always to ensure that we do wait tWB in
753 * any case on any machine. */
e0c7d767 754 ndelay(100);
3b88775c
TG		 755
756 nand_wait_ready(mtd);
1da177e4
LT		 757}
758
2af7c653
SK		 759/**
760 * panic_nand_get_device - [GENERIC] Get chip for selected access
761 * @chip: the nand chip descriptor
762 * @mtd: MTD device structure
763 * @new_state: the state which is requested
764 *
765 * Used when in panic, no locks are taken.
766 */
767static void panic_nand_get_device(struct nand_chip *chip,
768 struct mtd_info *mtd, int new_state)
769{
770 /* Hardware controller shared among independend devices */
771 chip->controller->active = chip;
772 chip->state = new_state;
773}
774
1da177e4
LT		 775/**
776 * nand_get_device - [GENERIC] Get chip for selected access
844d3b42 777 * @chip: the nand chip descriptor
1da177e4 778 * @mtd: MTD device structure
61b03bd7 779 * @new_state: the state which is requested
1da177e4
LT		 780 *
781 * Get the device and lock it for exclusive access
782 */
2c0a2bed 783static int
ace4dfee 784nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 785{
ace4dfee
TG		 786 spinlock_t *lock = &chip->controller->lock;
787 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 788 DECLARE_WAITQUEUE(wait, current);
7351d3a5 789retry:
0dfc6246
TG		 790 spin_lock(lock);
791
b8b3ee9a 792 /* Hardware controller shared among independent devices */
ace4dfee
TG		 793 if (!chip->controller->active)
794 chip->controller->active = chip;
a36ed299 795
ace4dfee
TG		 796 if (chip->controller->active == chip && chip->state == FL_READY) {
797 chip->state = new_state;
0dfc6246 798 spin_unlock(lock);
962034f4
VW		 799 return 0;
800 }
801 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 802 if (chip->controller->active->state == FL_PM_SUSPENDED) {
803 chip->state = FL_PM_SUSPENDED;
804 spin_unlock(lock);
805 return 0;
6b0d9a84 806 }
0dfc6246
TG		 807 }
808 set_current_state(TASK_UNINTERRUPTIBLE);
809 add_wait_queue(wq, &wait);
810 spin_unlock(lock);
811 schedule();
812 remove_wait_queue(wq, &wait);
1da177e4
LT		 813 goto retry;
814}
815
2af7c653
SK		 816/**
817 * panic_nand_wait - [GENERIC] wait until the command is done
818 * @mtd: MTD device structure
819 * @chip: NAND chip structure
820 * @timeo: Timeout
821 *
822 * Wait for command done. This is a helper function for nand_wait used when
823 * we are in interrupt context. May happen when in panic and trying to write
824 * an oops trough mtdoops.
825 */
826static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
827 unsigned long timeo)
828{
829 int i;
830 for (i = 0; i < timeo; i++) {
831 if (chip->dev_ready) {
832 if (chip->dev_ready(mtd))
833 break;
834 } else {
835 if (chip->read_byte(mtd) & NAND_STATUS_READY)
836 break;
837 }
838 mdelay(1);
f8ac0414 839 }
2af7c653
SK		 840}
841
1da177e4
LT		 842/**
843 * nand_wait - [DEFAULT] wait until the command is done
844 * @mtd: MTD device structure
844d3b42 845 * @chip: NAND chip structure
1da177e4
LT		 846 *
847 * Wait for command done. This applies to erase and program only
61b03bd7 848 * Erase can take up to 400ms and program up to 20ms according to
1da177e4 849 * general NAND and SmartMedia specs
844d3b42 850 */
7bc3312b 851static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 852{
853
e0c7d767 854 unsigned long timeo = jiffies;
7bc3312b 855 int status, state = chip->state;
61b03bd7 856
1da177e4 857 if (state == FL_ERASING)
e0c7d767 858 timeo += (HZ * 400) / 1000;
1da177e4 859 else
e0c7d767 860 timeo += (HZ * 20) / 1000;
1da177e4 861
8fe833c1
RP		 862 led_trigger_event(nand_led_trigger, LED_FULL);
863
1da177e4
LT		 864 /* Apply this short delay always to ensure that we do wait tWB in
865 * any case on any machine. */
e0c7d767 866 ndelay(100);
1da177e4 867
ace4dfee
TG		 868 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
869 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 870 else
ace4dfee 871 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 872
2af7c653
SK		 873 if (in_interrupt() || oops_in_progress)
874 panic_nand_wait(mtd, chip, timeo);
875 else {
876 while (time_before(jiffies, timeo)) {
877 if (chip->dev_ready) {
878 if (chip->dev_ready(mtd))
879 break;
880 } else {
881 if (chip->read_byte(mtd) & NAND_STATUS_READY)
882 break;
883 }
884 cond_resched();
1da177e4 885 }
1da177e4 886 }
8fe833c1
RP		 887 led_trigger_event(nand_led_trigger, LED_OFF);
888
ace4dfee 889 status = (int)chip->read_byte(mtd);
1da177e4
LT		 890 return status;
891}
892
7d70f334 893/**
b6d676db 894 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
7d70f334 895 *
b6d676db
RD		 896 * @mtd: mtd info
897 * @ofs: offset to start unlock from
898 * @len: length to unlock
899 * @invert: when = 0, unlock the range of blocks within the lower and
7d70f334 900 * upper boundary address
b6d676db 901 * when = 1, unlock the range of blocks outside the boundaries
7d70f334
VS		 902 * of the lower and upper boundary address
903 *
b6d676db 904 * return - unlock status
7d70f334
VS		 905 */
906static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
907 uint64_t len, int invert)
908{
909 int ret = 0;
910 int status, page;
911 struct nand_chip *chip = mtd->priv;
912
913 /* Submit address of first page to unlock */
914 page = ofs >> chip->page_shift;
915 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
916
917 /* Submit address of last page to unlock */
918 page = (ofs + len) >> chip->page_shift;
919 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
920 (page | invert) & chip->pagemask);
921
922 /* Call wait ready function */
923 status = chip->waitfunc(mtd, chip);
924 udelay(1000);
925 /* See if device thinks it succeeded */
926 if (status & 0x01) {
927 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
928 __func__, status);
929 ret = -EIO;
930 }
931
932 return ret;
933}
934
935/**
b6d676db 936 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
7d70f334 937 *
b6d676db
RD		 938 * @mtd: mtd info
939 * @ofs: offset to start unlock from
940 * @len: length to unlock
7d70f334 941 *
b6d676db 942 * return - unlock status
7d70f334
VS		 943 */
944int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
945{
946 int ret = 0;
947 int chipnr;
948 struct nand_chip *chip = mtd->priv;
949
950 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
951 __func__, (unsigned long long)ofs, len);
952
953 if (check_offs_len(mtd, ofs, len))
954 ret = -EINVAL;
955
956 /* Align to last block address if size addresses end of the device */
957 if (ofs + len == mtd->size)
958 len -= mtd->erasesize;
959
960 nand_get_device(chip, mtd, FL_UNLOCKING);
961
962 /* Shift to get chip number */
963 chipnr = ofs >> chip->chip_shift;
964
965 chip->select_chip(mtd, chipnr);
966
967 /* Check, if it is write protected */
968 if (nand_check_wp(mtd)) {
969 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
970 __func__);
971 ret = -EIO;
972 goto out;
973 }
974
975 ret = __nand_unlock(mtd, ofs, len, 0);
976
977out:
978 /* de-select the NAND device */
979 chip->select_chip(mtd, -1);
980
981 nand_release_device(mtd);
982
983 return ret;
984}
7351d3a5 985EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 986
987/**
b6d676db 988 * nand_lock - [REPLACEABLE] locks all blocks present in the device
7d70f334 989 *
b6d676db
RD		 990 * @mtd: mtd info
991 * @ofs: offset to start unlock from
992 * @len: length to unlock
7d70f334 993 *
b6d676db 994 * return - lock status
7d70f334 995 *
b6d676db
RD		 996 * This feature is not supported in many NAND parts. 'Micron' NAND parts
997 * do have this feature, but it allows only to lock all blocks, not for
7d70f334
VS		 998 * specified range for block.
999 *
1000 * Implementing 'lock' feature by making use of 'unlock', for now.
1001 */
1002int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1003{
1004 int ret = 0;
1005 int chipnr, status, page;
1006 struct nand_chip *chip = mtd->priv;
1007
1008 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
1009 __func__, (unsigned long long)ofs, len);
1010
1011 if (check_offs_len(mtd, ofs, len))
1012 ret = -EINVAL;
1013
1014 nand_get_device(chip, mtd, FL_LOCKING);
1015
1016 /* Shift to get chip number */
1017 chipnr = ofs >> chip->chip_shift;
1018
1019 chip->select_chip(mtd, chipnr);
1020
1021 /* Check, if it is write protected */
1022 if (nand_check_wp(mtd)) {
1023 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1024 __func__);
1025 status = MTD_ERASE_FAILED;
1026 ret = -EIO;
1027 goto out;
1028 }
1029
1030 /* Submit address of first page to lock */
1031 page = ofs >> chip->page_shift;
1032 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1033
1034 /* Call wait ready function */
1035 status = chip->waitfunc(mtd, chip);
1036 udelay(1000);
1037 /* See if device thinks it succeeded */
1038 if (status & 0x01) {
1039 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1040 __func__, status);
1041 ret = -EIO;
1042 goto out;
1043 }
1044
1045 ret = __nand_unlock(mtd, ofs, len, 0x1);
1046
1047out:
1048 /* de-select the NAND device */
1049 chip->select_chip(mtd, -1);
1050
1051 nand_release_device(mtd);
1052
1053 return ret;
1054}
7351d3a5 1055EXPORT_SYMBOL(nand_lock);
7d70f334 1056
8593fbc6
TG		 1057/**
1058 * nand_read_page_raw - [Intern] read raw page data without ecc
1059 * @mtd: mtd info structure
1060 * @chip: nand chip info structure
1061 * @buf: buffer to store read data
58475fb9 1062 * @page: page number to read
52ff49df
DB		 1063 *
1064 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1065 */
1066static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1067 uint8_t *buf, int page)
8593fbc6
TG		 1068{
1069 chip->read_buf(mtd, buf, mtd->writesize);
1070 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1071 return 0;
1072}
1073
52ff49df
DB		 1074/**
1075 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1076 * @mtd: mtd info structure
1077 * @chip: nand chip info structure
1078 * @buf: buffer to store read data
58475fb9 1079 * @page: page number to read
52ff49df
DB		 1080 *
1081 * We need a special oob layout and handling even when OOB isn't used.
1082 */
7351d3a5
FF		 1083static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1084 struct nand_chip *chip,
1085 uint8_t *buf, int page)
52ff49df
DB		 1086{
1087 int eccsize = chip->ecc.size;
1088 int eccbytes = chip->ecc.bytes;
1089 uint8_t *oob = chip->oob_poi;
1090 int steps, size;
1091
1092 for (steps = chip->ecc.steps; steps > 0; steps--) {
1093 chip->read_buf(mtd, buf, eccsize);
1094 buf += eccsize;
1095
1096 if (chip->ecc.prepad) {
1097 chip->read_buf(mtd, oob, chip->ecc.prepad);
1098 oob += chip->ecc.prepad;
1099 }
1100
1101 chip->read_buf(mtd, oob, eccbytes);
1102 oob += eccbytes;
1103
1104 if (chip->ecc.postpad) {
1105 chip->read_buf(mtd, oob, chip->ecc.postpad);
1106 oob += chip->ecc.postpad;
1107 }
1108 }
1109
1110 size = mtd->oobsize - (oob - chip->oob_poi);
1111 if (size)
1112 chip->read_buf(mtd, oob, size);
1113
1114 return 0;
1115}
1116
1da177e4 1117/**
d29ebdbe 1118 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
f5bbdacc
TG		 1119 * @mtd: mtd info structure
1120 * @chip: nand chip info structure
1121 * @buf: buffer to store read data
58475fb9 1122 * @page: page number to read
068e3c0a 1123 */
f5bbdacc 1124static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1125 uint8_t *buf, int page)
1da177e4 1126{
f5bbdacc
TG		 1127 int i, eccsize = chip->ecc.size;
1128 int eccbytes = chip->ecc.bytes;
1129 int eccsteps = chip->ecc.steps;
1130 uint8_t *p = buf;
4bf63fcb
DW		 1131 uint8_t *ecc_calc = chip->buffers->ecccalc;
1132 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1133 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 1134
46a8cf2d 1135 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 1136
1137 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1138 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1139
1140 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1141 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1142
1143 eccsteps = chip->ecc.steps;
1144 p = buf;
1145
1146 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1147 int stat;
1148
1149 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1150 if (stat < 0)
f5bbdacc
TG		 1151 mtd->ecc_stats.failed++;
1152 else
1153 mtd->ecc_stats.corrected += stat;
1154 }
1155 return 0;
22c60f5f 1156}
1da177e4 1157
3d459559
AK		 1158/**
1159 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1160 * @mtd: mtd info structure
1161 * @chip: nand chip info structure
17c1d2be
AK		 1162 * @data_offs: offset of requested data within the page
1163 * @readlen: data length
1164 * @bufpoi: buffer to store read data
3d459559 1165 */
7351d3a5
FF		 1166static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1167 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1168{
1169 int start_step, end_step, num_steps;
1170 uint32_t *eccpos = chip->ecc.layout->eccpos;
1171 uint8_t *p;
1172 int data_col_addr, i, gaps = 0;
1173 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1174 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1175 int index = 0;
3d459559
AK		 1176
1177 /* Column address wihin the page aligned to ECC size (256bytes). */
1178 start_step = data_offs / chip->ecc.size;
1179 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1180 num_steps = end_step - start_step + 1;
1181
1182 /* Data size aligned to ECC ecc.size*/
1183 datafrag_len = num_steps * chip->ecc.size;
1184 eccfrag_len = num_steps * chip->ecc.bytes;
1185
1186 data_col_addr = start_step * chip->ecc.size;
1187 /* If we read not a page aligned data */
1188 if (data_col_addr != 0)
1189 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1190
1191 p = bufpoi + data_col_addr;
1192 chip->read_buf(mtd, p, datafrag_len);
1193
1194 /* Calculate ECC */
1195 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1196 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1197
1198 /* The performance is faster if to position offsets
1199 according to ecc.pos. Let make sure here that
1200 there are no gaps in ecc positions */
1201 for (i = 0; i < eccfrag_len - 1; i++) {
1202 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1203 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1204 gaps = 1;
1205 break;
1206 }
1207 }
1208 if (gaps) {
1209 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1210 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1211 } else {
1212 /* send the command to read the particular ecc bytes */
1213 /* take care about buswidth alignment in read_buf */
7351d3a5
FF		 1214 index = start_step * chip->ecc.bytes;
1215
1216 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1217 aligned_len = eccfrag_len;
7351d3a5 1218 if (eccpos[index] & (busw - 1))
3d459559 1219 aligned_len++;
7351d3a5 1220 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1221 aligned_len++;
1222
7351d3a5
FF		 1223 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1224 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1225 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1226 }
1227
1228 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1229 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1230
1231 p = bufpoi + data_col_addr;
1232 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1233 int stat;
1234
7351d3a5
FF		 1235 stat = chip->ecc.correct(mtd, p,
1236 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
12c8eb98 1237 if (stat < 0)
3d459559
AK		 1238 mtd->ecc_stats.failed++;
1239 else
1240 mtd->ecc_stats.corrected += stat;
1241 }
1242 return 0;
1243}
1244
068e3c0a 1245/**
d29ebdbe 1246 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
f5bbdacc
TG		 1247 * @mtd: mtd info structure
1248 * @chip: nand chip info structure
1249 * @buf: buffer to store read data
58475fb9 1250 * @page: page number to read
068e3c0a 1251 *
f5bbdacc 1252 * Not for syndrome calculating ecc controllers which need a special oob layout
068e3c0a 1253 */
f5bbdacc 1254static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1255 uint8_t *buf, int page)
1da177e4 1256{
f5bbdacc
TG		 1257 int i, eccsize = chip->ecc.size;
1258 int eccbytes = chip->ecc.bytes;
1259 int eccsteps = chip->ecc.steps;
1260 uint8_t *p = buf;
4bf63fcb
DW		 1261 uint8_t *ecc_calc = chip->buffers->ecccalc;
1262 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1263 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1264
1265 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1266 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1267 chip->read_buf(mtd, p, eccsize);
1268 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1269 }
f75e5097 1270 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1271
f5bbdacc 1272 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1273 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1274
f5bbdacc
TG		 1275 eccsteps = chip->ecc.steps;
1276 p = buf;
61b03bd7 1277
f5bbdacc
TG		 1278 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1279 int stat;
1da177e4 1280
f5bbdacc 1281 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1282 if (stat < 0)
f5bbdacc
TG		 1283 mtd->ecc_stats.failed++;
1284 else
1285 mtd->ecc_stats.corrected += stat;
1286 }
1287 return 0;
1288}
1da177e4 1289
6e0cb135
SN		 1290/**
1291 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1292 * @mtd: mtd info structure
1293 * @chip: nand chip info structure
1294 * @buf: buffer to store read data
58475fb9 1295 * @page: page number to read
6e0cb135
SN		 1296 *
1297 * Hardware ECC for large page chips, require OOB to be read first.
1298 * For this ECC mode, the write_page method is re-used from ECC_HW.
1299 * These methods read/write ECC from the OOB area, unlike the
1300 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1301 * "infix ECC" scheme and reads/writes ECC from the data area, by
1302 * overwriting the NAND manufacturer bad block markings.
1303 */
1304static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1305 struct nand_chip *chip, uint8_t *buf, int page)
1306{
1307 int i, eccsize = chip->ecc.size;
1308 int eccbytes = chip->ecc.bytes;
1309 int eccsteps = chip->ecc.steps;
1310 uint8_t *p = buf;
1311 uint8_t *ecc_code = chip->buffers->ecccode;
1312 uint32_t *eccpos = chip->ecc.layout->eccpos;
1313 uint8_t *ecc_calc = chip->buffers->ecccalc;
1314
1315 /* Read the OOB area first */
1316 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1317 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1318 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1319
1320 for (i = 0; i < chip->ecc.total; i++)
1321 ecc_code[i] = chip->oob_poi[eccpos[i]];
1322
1323 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1324 int stat;
1325
1326 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1327 chip->read_buf(mtd, p, eccsize);
1328 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1329
1330 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1331 if (stat < 0)
1332 mtd->ecc_stats.failed++;
1333 else
1334 mtd->ecc_stats.corrected += stat;
1335 }
1336 return 0;
1337}
1338
f5bbdacc 1339/**
d29ebdbe 1340 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
f5bbdacc
TG		 1341 * @mtd: mtd info structure
1342 * @chip: nand chip info structure
1343 * @buf: buffer to store read data
58475fb9 1344 * @page: page number to read
f5bbdacc
TG		 1345 *
1346 * The hw generator calculates the error syndrome automatically. Therefor
f75e5097 1347 * we need a special oob layout and handling.
f5bbdacc
TG		 1348 */
1349static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1350 uint8_t *buf, int page)
f5bbdacc
TG		 1351{
1352 int i, eccsize = chip->ecc.size;
1353 int eccbytes = chip->ecc.bytes;
1354 int eccsteps = chip->ecc.steps;
1355 uint8_t *p = buf;
f75e5097 1356 uint8_t *oob = chip->oob_poi;
1da177e4 1357
f5bbdacc
TG		 1358 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1359 int stat;
61b03bd7 1360
f5bbdacc
TG		 1361 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1362 chip->read_buf(mtd, p, eccsize);
1da177e4 1363
f5bbdacc
TG		 1364 if (chip->ecc.prepad) {
1365 chip->read_buf(mtd, oob, chip->ecc.prepad);
1366 oob += chip->ecc.prepad;
1367 }
1da177e4 1368
f5bbdacc
TG		 1369 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1370 chip->read_buf(mtd, oob, eccbytes);
1371 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1372
c32b8dcc 1373 if (stat < 0)
f5bbdacc 1374 mtd->ecc_stats.failed++;
61b03bd7 1375 else
f5bbdacc 1376 mtd->ecc_stats.corrected += stat;
61b03bd7 1377
f5bbdacc 1378 oob += eccbytes;
1da177e4 1379
f5bbdacc
TG		 1380 if (chip->ecc.postpad) {
1381 chip->read_buf(mtd, oob, chip->ecc.postpad);
1382 oob += chip->ecc.postpad;
61b03bd7 1383 }
f5bbdacc 1384 }
1da177e4 1385
f5bbdacc 1386 /* Calculate remaining oob bytes */
7e4178f9 1387 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1388 if (i)
1389 chip->read_buf(mtd, oob, i);
61b03bd7 1390
f5bbdacc
TG		 1391 return 0;
1392}
1da177e4 1393
f5bbdacc 1394/**
8593fbc6
TG		 1395 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1396 * @chip: nand chip structure
844d3b42 1397 * @oob: oob destination address
8593fbc6 1398 * @ops: oob ops structure
7014568b 1399 * @len: size of oob to transfer
8593fbc6
TG		 1400 */
1401static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1402 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1403{
f8ac0414 1404 switch (ops->mode) {
8593fbc6
TG		 1405
1406 case MTD_OOB_PLACE:
1407 case MTD_OOB_RAW:
1408 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1409 return oob + len;
1410
1411 case MTD_OOB_AUTO: {
1412 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1413 uint32_t boffs = 0, roffs = ops->ooboffs;
1414 size_t bytes = 0;
8593fbc6 1415
f8ac0414 1416 for (; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1417 /* Read request not from offset 0 ? */
1418 if (unlikely(roffs)) {
1419 if (roffs >= free->length) {
1420 roffs -= free->length;
1421 continue;
1422 }
1423 boffs = free->offset + roffs;
1424 bytes = min_t(size_t, len,
1425 (free->length - roffs));
1426 roffs = 0;
1427 } else {
1428 bytes = min_t(size_t, len, free->length);
1429 boffs = free->offset;
1430 }
1431 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1432 oob += bytes;
1433 }
1434 return oob;
1435 }
1436 default:
1437 BUG();
1438 }
1439 return NULL;
1440}
1441
1442/**
1443 * nand_do_read_ops - [Internal] Read data with ECC
f5bbdacc
TG		 1444 *
1445 * @mtd: MTD device structure
1446 * @from: offset to read from
844d3b42 1447 * @ops: oob ops structure
f5bbdacc
TG		 1448 *
1449 * Internal function. Called with chip held.
1450 */
8593fbc6
TG		 1451static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1452 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1453{
1454 int chipnr, page, realpage, col, bytes, aligned;
1455 struct nand_chip *chip = mtd->priv;
1456 struct mtd_ecc_stats stats;
1457 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1458 int sndcmd = 1;
1459 int ret = 0;
8593fbc6 1460 uint32_t readlen = ops->len;
7014568b 1461 uint32_t oobreadlen = ops->ooblen;
9aca334e
ML		 1462 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1463 mtd->oobavail : mtd->oobsize;
1464
8593fbc6 1465 uint8_t *bufpoi, *oob, *buf;
1da177e4 1466
f5bbdacc 1467 stats = mtd->ecc_stats;
1da177e4 1468
f5bbdacc
TG		 1469 chipnr = (int)(from >> chip->chip_shift);
1470 chip->select_chip(mtd, chipnr);
61b03bd7 1471
f5bbdacc
TG		 1472 realpage = (int)(from >> chip->page_shift);
1473 page = realpage & chip->pagemask;
1da177e4 1474
f5bbdacc 1475 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1476
8593fbc6
TG		 1477 buf = ops->datbuf;
1478 oob = ops->oobbuf;
1479
f8ac0414 1480 while (1) {
f5bbdacc
TG		 1481 bytes = min(mtd->writesize - col, readlen);
1482 aligned = (bytes == mtd->writesize);
61b03bd7 1483
f5bbdacc 1484 /* Is the current page in the buffer ? */
8593fbc6 1485 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1486 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1487
f5bbdacc
TG		 1488 if (likely(sndcmd)) {
1489 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1490 sndcmd = 0;
1da177e4 1491 }
1da177e4 1492
f5bbdacc 1493 /* Now read the page into the buffer */
956e944c 1494 if (unlikely(ops->mode == MTD_OOB_RAW))
46a8cf2d
SN		 1495 ret = chip->ecc.read_page_raw(mtd, chip,
1496 bufpoi, page);
3d459559 1497 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1498 ret = chip->ecc.read_subpage(mtd, chip,
1499 col, bytes, bufpoi);
956e944c 1500 else
46a8cf2d
SN		 1501 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1502 page);
f5bbdacc 1503 if (ret < 0)
1da177e4 1504 break;
f5bbdacc
TG		 1505
1506 /* Transfer not aligned data */
1507 if (!aligned) {
c1194c79
AB		 1508 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1509 !(mtd->ecc_stats.failed - stats.failed))
3d459559 1510 chip->pagebuf = realpage;
4bf63fcb 1511 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1512 }
1513
8593fbc6
TG		 1514 buf += bytes;
1515
1516 if (unlikely(oob)) {
9aca334e 1517
b64d39d8
ML		 1518 int toread = min(oobreadlen, max_oobsize);
1519
1520 if (toread) {
1521 oob = nand_transfer_oob(chip,
1522 oob, ops, toread);
1523 oobreadlen -= toread;
1524 }
8593fbc6
TG		 1525 }
1526
f5bbdacc
TG		 1527 if (!(chip->options & NAND_NO_READRDY)) {
1528 /*
1529 * Apply delay or wait for ready/busy pin. Do
1530 * this before the AUTOINCR check, so no
1531 * problems arise if a chip which does auto
1532 * increment is marked as NOAUTOINCR by the
1533 * board driver.
1534 */
1535 if (!chip->dev_ready)
1536 udelay(chip->chip_delay);
1537 else
1538 nand_wait_ready(mtd);
1da177e4 1539 }
8593fbc6 1540 } else {
4bf63fcb 1541 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1542 buf += bytes;
1543 }
1da177e4 1544
f5bbdacc 1545 readlen -= bytes;
61b03bd7 1546
f5bbdacc 1547 if (!readlen)
61b03bd7 1548 break;
1da177e4
LT		 1549
1550 /* For subsequent reads align to page boundary. */
1551 col = 0;
1552 /* Increment page address */
1553 realpage++;
1554
ace4dfee 1555 page = realpage & chip->pagemask;
1da177e4
LT		 1556 /* Check, if we cross a chip boundary */
1557 if (!page) {
1558 chipnr++;
ace4dfee
TG		 1559 chip->select_chip(mtd, -1);
1560 chip->select_chip(mtd, chipnr);
1da177e4 1561 }
f5bbdacc 1562
61b03bd7
TG		 1563 /* Check, if the chip supports auto page increment
1564 * or if we have hit a block boundary.
e0c7d767 1565 */
f5bbdacc 1566 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1567 sndcmd = 1;
1da177e4
LT		 1568 }
1569
8593fbc6 1570 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1571 if (oob)
1572 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1573
f5bbdacc
TG		 1574 if (ret)
1575 return ret;
1576
9a1fcdfd
TG		 1577 if (mtd->ecc_stats.failed - stats.failed)
1578 return -EBADMSG;
1579
1580 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1581}
1582
1583/**
1584 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1585 * @mtd: MTD device structure
1586 * @from: offset to read from
1587 * @len: number of bytes to read
1588 * @retlen: pointer to variable to store the number of read bytes
1589 * @buf: the databuffer to put data
1590 *
1591 * Get hold of the chip and call nand_do_read
1592 */
1593static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1594 size_t *retlen, uint8_t *buf)
1595{
8593fbc6 1596 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1597 int ret;
1598
f5bbdacc
TG		 1599 /* Do not allow reads past end of device */
1600 if ((from + len) > mtd->size)
1601 return -EINVAL;
1602 if (!len)
1603 return 0;
1604
8593fbc6 1605 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1606
8593fbc6
TG		 1607 chip->ops.len = len;
1608 chip->ops.datbuf = buf;
1609 chip->ops.oobbuf = NULL;
1610
1611 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1612
7fd5aecc
RP		 1613 *retlen = chip->ops.retlen;
1614
f5bbdacc
TG		 1615 nand_release_device(mtd);
1616
1617 return ret;
1da177e4
LT		 1618}
1619
7bc3312b
TG		 1620/**
1621 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1622 * @mtd: mtd info structure
1623 * @chip: nand chip info structure
1624 * @page: page number to read
1625 * @sndcmd: flag whether to issue read command or not
1626 */
1627static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1628 int page, int sndcmd)
1629{
1630 if (sndcmd) {
1631 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1632 sndcmd = 0;
1633 }
1634 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1635 return sndcmd;
1636}
1637
1638/**
1639 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1640 * with syndromes
1641 * @mtd: mtd info structure
1642 * @chip: nand chip info structure
1643 * @page: page number to read
1644 * @sndcmd: flag whether to issue read command or not
1645 */
1646static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1647 int page, int sndcmd)
1648{
1649 uint8_t *buf = chip->oob_poi;
1650 int length = mtd->oobsize;
1651 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1652 int eccsize = chip->ecc.size;
1653 uint8_t *bufpoi = buf;
1654 int i, toread, sndrnd = 0, pos;
1655
1656 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1657 for (i = 0; i < chip->ecc.steps; i++) {
1658 if (sndrnd) {
1659 pos = eccsize + i * (eccsize + chunk);
1660 if (mtd->writesize > 512)
1661 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1662 else
1663 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1664 } else
1665 sndrnd = 1;
1666 toread = min_t(int, length, chunk);
1667 chip->read_buf(mtd, bufpoi, toread);
1668 bufpoi += toread;
1669 length -= toread;
1670 }
1671 if (length > 0)
1672 chip->read_buf(mtd, bufpoi, length);
1673
1674 return 1;
1675}
1676
1677/**
1678 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1679 * @mtd: mtd info structure
1680 * @chip: nand chip info structure
1681 * @page: page number to write
1682 */
1683static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1684 int page)
1685{
1686 int status = 0;
1687 const uint8_t *buf = chip->oob_poi;
1688 int length = mtd->oobsize;
1689
1690 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1691 chip->write_buf(mtd, buf, length);
1692 /* Send command to program the OOB data */
1693 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1694
1695 status = chip->waitfunc(mtd, chip);
1696
0d420f9d 1697 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1698}
1699
1700/**
1701 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1702 * with syndrome - only for large page flash !
1703 * @mtd: mtd info structure
1704 * @chip: nand chip info structure
1705 * @page: page number to write
1706 */
1707static int nand_write_oob_syndrome(struct mtd_info *mtd,
1708 struct nand_chip *chip, int page)
1709{
1710 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1711 int eccsize = chip->ecc.size, length = mtd->oobsize;
1712 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1713 const uint8_t *bufpoi = chip->oob_poi;
1714
1715 /*
1716 * data-ecc-data-ecc ... ecc-oob
1717 * or
1718 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1719 */
1720 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1721 pos = steps * (eccsize + chunk);
1722 steps = 0;
1723 } else
8b0036ee 1724 pos = eccsize;
7bc3312b
TG		 1725
1726 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1727 for (i = 0; i < steps; i++) {
1728 if (sndcmd) {
1729 if (mtd->writesize <= 512) {
1730 uint32_t fill = 0xFFFFFFFF;
1731
1732 len = eccsize;
1733 while (len > 0) {
1734 int num = min_t(int, len, 4);
1735 chip->write_buf(mtd, (uint8_t *)&fill,
1736 num);
1737 len -= num;
1738 }
1739 } else {
1740 pos = eccsize + i * (eccsize + chunk);
1741 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1742 }
1743 } else
1744 sndcmd = 1;
1745 len = min_t(int, length, chunk);
1746 chip->write_buf(mtd, bufpoi, len);
1747 bufpoi += len;
1748 length -= len;
1749 }
1750 if (length > 0)
1751 chip->write_buf(mtd, bufpoi, length);
1752
1753 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1754 status = chip->waitfunc(mtd, chip);
1755
1756 return status & NAND_STATUS_FAIL ? -EIO : 0;
1757}
1758
1da177e4 1759/**
8593fbc6 1760 * nand_do_read_oob - [Intern] NAND read out-of-band
1da177e4
LT		 1761 * @mtd: MTD device structure
1762 * @from: offset to read from
8593fbc6 1763 * @ops: oob operations description structure
1da177e4
LT		 1764 *
1765 * NAND read out-of-band data from the spare area
1766 */
8593fbc6
TG		 1767static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1768 struct mtd_oob_ops *ops)
1da177e4 1769{
7bc3312b 1770 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1771 struct nand_chip *chip = mtd->priv;
7314e9e7 1772 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1773 int readlen = ops->ooblen;
1774 int len;
7bc3312b 1775 uint8_t *buf = ops->oobbuf;
61b03bd7 1776
20d8e248 1777 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1778 __func__, (unsigned long long)from, readlen);
1da177e4 1779
03736155 1780 if (ops->mode == MTD_OOB_AUTO)
7014568b 1781 len = chip->ecc.layout->oobavail;
03736155
AH		 1782 else
1783 len = mtd->oobsize;
1784
e14feafb
JL		 1785 /* Do not allow read past end of page */
1786 if ((ops->ooboffs + readlen) > len) {
1787 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to read "
1788 "past end of page\n", __func__);
1789 return -EINVAL;
1790 }
1791
03736155 1792 if (unlikely(ops->ooboffs >= len)) {
20d8e248 1793 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1794 "outside oob\n", __func__);
03736155
AH		 1795 return -EINVAL;
1796 }
1797
1798 /* Do not allow reads past end of device */
1799 if (unlikely(from >= mtd->size ||
1800 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1801 (from >> chip->page_shift)) * len)) {
20d8e248 1802 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1803 "of device\n", __func__);
03736155
AH		 1804 return -EINVAL;
1805 }
7014568b 1806
7314e9e7 1807 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1808 chip->select_chip(mtd, chipnr);
1da177e4 1809
7314e9e7
TG		 1810 /* Shift to get page */
1811 realpage = (int)(from >> chip->page_shift);
1812 page = realpage & chip->pagemask;
1da177e4 1813
f8ac0414 1814 while (1) {
7bc3312b 1815 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1816
1817 len = min(len, readlen);
1818 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1819
7314e9e7
TG		 1820 if (!(chip->options & NAND_NO_READRDY)) {
1821 /*
1822 * Apply delay or wait for ready/busy pin. Do this
1823 * before the AUTOINCR check, so no problems arise if a
1824 * chip which does auto increment is marked as
1825 * NOAUTOINCR by the board driver.
19870da7 1826 */
ace4dfee
TG		 1827 if (!chip->dev_ready)
1828 udelay(chip->chip_delay);
19870da7
TG		 1829 else
1830 nand_wait_ready(mtd);
7314e9e7 1831 }
19870da7 1832
7014568b 1833 readlen -= len;
0d420f9d
SZ		 1834 if (!readlen)
1835 break;
1836
7314e9e7
TG		 1837 /* Increment page address */
1838 realpage++;
1839
1840 page = realpage & chip->pagemask;
1841 /* Check, if we cross a chip boundary */
1842 if (!page) {
1843 chipnr++;
1844 chip->select_chip(mtd, -1);
1845 chip->select_chip(mtd, chipnr);
1da177e4 1846 }
7314e9e7
TG		 1847
1848 /* Check, if the chip supports auto page increment
1849 * or if we have hit a block boundary.
1850 */
1851 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1852 sndcmd = 1;
1da177e4
LT		 1853 }
1854
7014568b 1855 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1856 return 0;
1857}
1858
1859/**
8593fbc6 1860 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1da177e4 1861 * @mtd: MTD device structure
1da177e4 1862 * @from: offset to read from
8593fbc6 1863 * @ops: oob operation description structure
1da177e4 1864 *
8593fbc6 1865 * NAND read data and/or out-of-band data
1da177e4 1866 */
8593fbc6
TG		 1867static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1868 struct mtd_oob_ops *ops)
1da177e4 1869{
ace4dfee 1870 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1871 int ret = -ENOTSUPP;
1872
1873 ops->retlen = 0;
1da177e4
LT		 1874
1875 /* Do not allow reads past end of device */
7014568b 1876 if (ops->datbuf && (from + ops->len) > mtd->size) {
20d8e248 1877 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1878 "beyond end of device\n", __func__);
1da177e4
LT		 1879 return -EINVAL;
1880 }
1881
ace4dfee 1882 nand_get_device(chip, mtd, FL_READING);
1da177e4 1883
f8ac0414 1884 switch (ops->mode) {
8593fbc6
TG		 1885 case MTD_OOB_PLACE:
1886 case MTD_OOB_AUTO:
8593fbc6 1887 case MTD_OOB_RAW:
8593fbc6 1888 break;
1da177e4 1889
8593fbc6
TG		 1890 default:
1891 goto out;
1892 }
1da177e4 1893
8593fbc6
TG		 1894 if (!ops->datbuf)
1895 ret = nand_do_read_oob(mtd, from, ops);
1896 else
1897 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1898
7351d3a5 1899out:
8593fbc6
TG		 1900 nand_release_device(mtd);
1901 return ret;
1902}
61b03bd7 1903
1da177e4 1904
8593fbc6
TG		 1905/**
1906 * nand_write_page_raw - [Intern] raw page write function
1907 * @mtd: mtd info structure
1908 * @chip: nand chip info structure
1909 * @buf: data buffer
52ff49df
DB		 1910 *
1911 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1912 */
1913static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1914 const uint8_t *buf)
1915{
1916 chip->write_buf(mtd, buf, mtd->writesize);
1917 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1918}
1919
52ff49df
DB		 1920/**
1921 * nand_write_page_raw_syndrome - [Intern] raw page write function
1922 * @mtd: mtd info structure
1923 * @chip: nand chip info structure
1924 * @buf: data buffer
1925 *
1926 * We need a special oob layout and handling even when ECC isn't checked.
1927 */
7351d3a5
FF		 1928static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1929 struct nand_chip *chip,
1930 const uint8_t *buf)
52ff49df
DB		 1931{
1932 int eccsize = chip->ecc.size;
1933 int eccbytes = chip->ecc.bytes;
1934 uint8_t *oob = chip->oob_poi;
1935 int steps, size;
1936
1937 for (steps = chip->ecc.steps; steps > 0; steps--) {
1938 chip->write_buf(mtd, buf, eccsize);
1939 buf += eccsize;
1940
1941 if (chip->ecc.prepad) {
1942 chip->write_buf(mtd, oob, chip->ecc.prepad);
1943 oob += chip->ecc.prepad;
1944 }
1945
1946 chip->read_buf(mtd, oob, eccbytes);
1947 oob += eccbytes;
1948
1949 if (chip->ecc.postpad) {
1950 chip->write_buf(mtd, oob, chip->ecc.postpad);
1951 oob += chip->ecc.postpad;
1952 }
1953 }
1954
1955 size = mtd->oobsize - (oob - chip->oob_poi);
1956 if (size)
1957 chip->write_buf(mtd, oob, size);
1958}
9223a456 1959/**
d29ebdbe 1960 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
f75e5097
TG		 1961 * @mtd: mtd info structure
1962 * @chip: nand chip info structure
1963 * @buf: data buffer
9223a456 1964 */
f75e5097
TG		 1965static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1966 const uint8_t *buf)
9223a456 1967{
f75e5097
TG		 1968 int i, eccsize = chip->ecc.size;
1969 int eccbytes = chip->ecc.bytes;
1970 int eccsteps = chip->ecc.steps;
4bf63fcb 1971 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1972 const uint8_t *p = buf;
8b099a39 1973 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1974
8593fbc6
TG		 1975 /* Software ecc calculation */
1976 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1977 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1978
8593fbc6
TG		 1979 for (i = 0; i < chip->ecc.total; i++)
1980 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1981
90424de8 1982 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1983}
9223a456 1984
f75e5097 1985/**
d29ebdbe 1986 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
f75e5097
TG		 1987 * @mtd: mtd info structure
1988 * @chip: nand chip info structure
1989 * @buf: data buffer
1990 */
1991static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1992 const uint8_t *buf)
1993{
1994 int i, eccsize = chip->ecc.size;
1995 int eccbytes = chip->ecc.bytes;
1996 int eccsteps = chip->ecc.steps;
4bf63fcb 1997 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1998 const uint8_t *p = buf;
8b099a39 1999 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2000
f75e5097
TG		 2001 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2002 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2003 chip->write_buf(mtd, p, eccsize);
f75e5097 2004 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2005 }
2006
f75e5097
TG		 2007 for (i = 0; i < chip->ecc.total; i++)
2008 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2009
2010 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 2011}
2012
61b03bd7 2013/**
d29ebdbe 2014 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
f75e5097
TG		 2015 * @mtd: mtd info structure
2016 * @chip: nand chip info structure
2017 * @buf: data buffer
1da177e4 2018 *
f75e5097
TG		 2019 * The hw generator calculates the error syndrome automatically. Therefor
2020 * we need a special oob layout and handling.
2021 */
2022static void nand_write_page_syndrome(struct mtd_info *mtd,
2023 struct nand_chip *chip, const uint8_t *buf)
1da177e4 2024{
f75e5097
TG		 2025 int i, eccsize = chip->ecc.size;
2026 int eccbytes = chip->ecc.bytes;
2027 int eccsteps = chip->ecc.steps;
2028 const uint8_t *p = buf;
2029 uint8_t *oob = chip->oob_poi;
1da177e4 2030
f75e5097 2031 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2032
f75e5097
TG		 2033 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2034 chip->write_buf(mtd, p, eccsize);
61b03bd7 2035
f75e5097
TG		 2036 if (chip->ecc.prepad) {
2037 chip->write_buf(mtd, oob, chip->ecc.prepad);
2038 oob += chip->ecc.prepad;
2039 }
2040
2041 chip->ecc.calculate(mtd, p, oob);
2042 chip->write_buf(mtd, oob, eccbytes);
2043 oob += eccbytes;
2044
2045 if (chip->ecc.postpad) {
2046 chip->write_buf(mtd, oob, chip->ecc.postpad);
2047 oob += chip->ecc.postpad;
1da177e4 2048 }
1da177e4 2049 }
f75e5097
TG		 2050
2051 /* Calculate remaining oob bytes */
7e4178f9 2052 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2053 if (i)
2054 chip->write_buf(mtd, oob, i);
2055}
2056
2057/**
956e944c 2058 * nand_write_page - [REPLACEABLE] write one page
f75e5097
TG		 2059 * @mtd: MTD device structure
2060 * @chip: NAND chip descriptor
2061 * @buf: the data to write
2062 * @page: page number to write
2063 * @cached: cached programming
efbfe96c 2064 * @raw: use _raw version of write_page
f75e5097
TG		 2065 */
2066static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 2067 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 2068{
2069 int status;
2070
2071 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2072
956e944c
DW		 2073 if (unlikely(raw))
2074 chip->ecc.write_page_raw(mtd, chip, buf);
2075 else
2076 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 2077
2078 /*
2079 * Cached progamming disabled for now, Not sure if its worth the
2080 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2081 */
2082 cached = 0;
2083
2084 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2085
2086 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2087 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2088 /*
2089 * See if operation failed and additional status checks are
2090 * available
2091 */
2092 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2093 status = chip->errstat(mtd, chip, FL_WRITING, status,
2094 page);
2095
2096 if (status & NAND_STATUS_FAIL)
2097 return -EIO;
2098 } else {
2099 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2100 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2101 }
2102
2103#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2104 /* Send command to read back the data */
2105 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2106
2107 if (chip->verify_buf(mtd, buf, mtd->writesize))
2108 return -EIO;
2109#endif
2110 return 0;
1da177e4
LT		 2111}
2112
8593fbc6
TG		 2113/**
2114 * nand_fill_oob - [Internal] Transfer client buffer to oob
2115 * @chip: nand chip structure
2116 * @oob: oob data buffer
b6d676db 2117 * @len: oob data write length
8593fbc6
TG		 2118 * @ops: oob ops structure
2119 */
782ce79a
ML		 2120static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2121 struct mtd_oob_ops *ops)
8593fbc6 2122{
f8ac0414 2123 switch (ops->mode) {
8593fbc6
TG		 2124
2125 case MTD_OOB_PLACE:
2126 case MTD_OOB_RAW:
2127 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2128 return oob + len;
2129
2130 case MTD_OOB_AUTO: {
2131 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2132 uint32_t boffs = 0, woffs = ops->ooboffs;
2133 size_t bytes = 0;
8593fbc6 2134
f8ac0414 2135 for (; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 2136 /* Write request not from offset 0 ? */
2137 if (unlikely(woffs)) {
2138 if (woffs >= free->length) {
2139 woffs -= free->length;
2140 continue;
2141 }
2142 boffs = free->offset + woffs;
2143 bytes = min_t(size_t, len,
2144 (free->length - woffs));
2145 woffs = 0;
2146 } else {
2147 bytes = min_t(size_t, len, free->length);
2148 boffs = free->offset;
2149 }
8b0036ee 2150 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2151 oob += bytes;
2152 }
2153 return oob;
2154 }
2155 default:
2156 BUG();
2157 }
2158 return NULL;
2159}
2160
f8ac0414 2161#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2162
2163/**
8593fbc6 2164 * nand_do_write_ops - [Internal] NAND write with ECC
1da177e4
LT		 2165 * @mtd: MTD device structure
2166 * @to: offset to write to
8593fbc6 2167 * @ops: oob operations description structure
1da177e4
LT		 2168 *
2169 * NAND write with ECC
2170 */
8593fbc6
TG		 2171static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2172 struct mtd_oob_ops *ops)
1da177e4 2173{
29072b96 2174 int chipnr, realpage, page, blockmask, column;
ace4dfee 2175 struct nand_chip *chip = mtd->priv;
8593fbc6 2176 uint32_t writelen = ops->len;
782ce79a
ML		 2177
2178 uint32_t oobwritelen = ops->ooblen;
2179 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2180 mtd->oobavail : mtd->oobsize;
2181
8593fbc6
TG		 2182 uint8_t *oob = ops->oobbuf;
2183 uint8_t *buf = ops->datbuf;
29072b96 2184 int ret, subpage;
1da177e4 2185
8593fbc6 2186 ops->retlen = 0;
29072b96
TG		 2187 if (!writelen)
2188 return 0;
1da177e4 2189
61b03bd7 2190 /* reject writes, which are not page aligned */
8593fbc6 2191 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
20d8e248 2192 printk(KERN_NOTICE "%s: Attempt to write not "
2193 "page aligned data\n", __func__);
1da177e4
LT		 2194 return -EINVAL;
2195 }
2196
29072b96
TG		 2197 column = to & (mtd->writesize - 1);
2198 subpage = column || (writelen & (mtd->writesize - 1));
2199
2200 if (subpage && oob)
2201 return -EINVAL;
1da177e4 2202
6a930961
TG		 2203 chipnr = (int)(to >> chip->chip_shift);
2204 chip->select_chip(mtd, chipnr);
2205
1da177e4
LT		 2206 /* Check, if it is write protected */
2207 if (nand_check_wp(mtd))
8593fbc6 2208 return -EIO;
1da177e4 2209
f75e5097
TG		 2210 realpage = (int)(to >> chip->page_shift);
2211 page = realpage & chip->pagemask;
2212 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2213
2214 /* Invalidate the page cache, when we write to the cached page */
2215 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2216 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2217 chip->pagebuf = -1;
61b03bd7 2218
7dcdcbef
DW		 2219 /* If we're not given explicit OOB data, let it be 0xFF */
2220 if (likely(!oob))
2221 memset(chip->oob_poi, 0xff, mtd->oobsize);
61b03bd7 2222
782ce79a 2223 /* Don't allow multipage oob writes with offset */
cdcf12b2 2224 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2225 return -EINVAL;
2226
f8ac0414 2227 while (1) {
29072b96 2228 int bytes = mtd->writesize;
f75e5097 2229 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2230 uint8_t *wbuf = buf;
2231
2232 /* Partial page write ? */
2233 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2234 cached = 0;
2235 bytes = min_t(int, bytes - column, (int) writelen);
2236 chip->pagebuf = -1;
2237 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2238 memcpy(&chip->buffers->databuf[column], buf, bytes);
2239 wbuf = chip->buffers->databuf;
2240 }
1da177e4 2241
782ce79a
ML		 2242 if (unlikely(oob)) {
2243 size_t len = min(oobwritelen, oobmaxlen);
2244 oob = nand_fill_oob(chip, oob, len, ops);
2245 oobwritelen -= len;
2246 }
8593fbc6 2247
29072b96 2248 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 2249 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 2250 if (ret)
2251 break;
2252
2253 writelen -= bytes;
2254 if (!writelen)
2255 break;
2256
29072b96 2257 column = 0;
f75e5097
TG		 2258 buf += bytes;
2259 realpage++;
2260
2261 page = realpage & chip->pagemask;
2262 /* Check, if we cross a chip boundary */
2263 if (!page) {
2264 chipnr++;
2265 chip->select_chip(mtd, -1);
2266 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2267 }
2268 }
8593fbc6 2269
8593fbc6 2270 ops->retlen = ops->len - writelen;
7014568b
VW		 2271 if (unlikely(oob))
2272 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2273 return ret;
2274}
2275
2af7c653
SK		 2276/**
2277 * panic_nand_write - [MTD Interface] NAND write with ECC
2278 * @mtd: MTD device structure
2279 * @to: offset to write to
2280 * @len: number of bytes to write
2281 * @retlen: pointer to variable to store the number of written bytes
2282 * @buf: the data to write
2283 *
2284 * NAND write with ECC. Used when performing writes in interrupt context, this
2285 * may for example be called by mtdoops when writing an oops while in panic.
2286 */
2287static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2288 size_t *retlen, const uint8_t *buf)
2289{
2290 struct nand_chip *chip = mtd->priv;
2291 int ret;
2292
2293 /* Do not allow reads past end of device */
2294 if ((to + len) > mtd->size)
2295 return -EINVAL;
2296 if (!len)
2297 return 0;
2298
2299 /* Wait for the device to get ready. */
2300 panic_nand_wait(mtd, chip, 400);
2301
2302 /* Grab the device. */
2303 panic_nand_get_device(chip, mtd, FL_WRITING);
2304
2305 chip->ops.len = len;
2306 chip->ops.datbuf = (uint8_t *)buf;
2307 chip->ops.oobbuf = NULL;
2308
2309 ret = nand_do_write_ops(mtd, to, &chip->ops);
2310
2311 *retlen = chip->ops.retlen;
2312 return ret;
2313}
2314
f75e5097 2315/**
8593fbc6 2316 * nand_write - [MTD Interface] NAND write with ECC
f75e5097 2317 * @mtd: MTD device structure
f75e5097
TG		 2318 * @to: offset to write to
2319 * @len: number of bytes to write
8593fbc6
TG		 2320 * @retlen: pointer to variable to store the number of written bytes
2321 * @buf: the data to write
f75e5097 2322 *
8593fbc6 2323 * NAND write with ECC
f75e5097 2324 */
8593fbc6
TG		 2325static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2326 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2327{
2328 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 2329 int ret;
2330
8593fbc6
TG		 2331 /* Do not allow reads past end of device */
2332 if ((to + len) > mtd->size)
f75e5097 2333 return -EINVAL;
8593fbc6
TG		 2334 if (!len)
2335 return 0;
f75e5097 2336
7bc3312b 2337 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 2338
8593fbc6
TG		 2339 chip->ops.len = len;
2340 chip->ops.datbuf = (uint8_t *)buf;
2341 chip->ops.oobbuf = NULL;
f75e5097 2342
8593fbc6 2343 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 2344
7fd5aecc
RP		 2345 *retlen = chip->ops.retlen;
2346
f75e5097 2347 nand_release_device(mtd);
8593fbc6 2348
8593fbc6 2349 return ret;
f75e5097 2350}
7314e9e7 2351
1da177e4 2352/**
8593fbc6 2353 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1da177e4
LT		 2354 * @mtd: MTD device structure
2355 * @to: offset to write to
8593fbc6 2356 * @ops: oob operation description structure
1da177e4
LT		 2357 *
2358 * NAND write out-of-band
2359 */
8593fbc6
TG		 2360static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2361 struct mtd_oob_ops *ops)
1da177e4 2362{
03736155 2363 int chipnr, page, status, len;
ace4dfee 2364 struct nand_chip *chip = mtd->priv;
1da177e4 2365
20d8e248 2366 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2367 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2368
03736155
AH		 2369 if (ops->mode == MTD_OOB_AUTO)
2370 len = chip->ecc.layout->oobavail;
2371 else
2372 len = mtd->oobsize;
2373
1da177e4 2374 /* Do not allow write past end of page */
03736155 2375 if ((ops->ooboffs + ops->ooblen) > len) {
20d8e248 2376 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2377 "past end of page\n", __func__);
1da177e4
LT		 2378 return -EINVAL;
2379 }
2380
03736155 2381 if (unlikely(ops->ooboffs >= len)) {
20d8e248 2382 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2383 "write outside oob\n", __func__);
03736155
AH		 2384 return -EINVAL;
2385 }
2386
e14feafb 2387 /* Do not allow write past end of device */
03736155
AH		 2388 if (unlikely(to >= mtd->size ||
2389 ops->ooboffs + ops->ooblen >
2390 ((mtd->size >> chip->page_shift) -
2391 (to >> chip->page_shift)) * len)) {
20d8e248 2392 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2393 "end of device\n", __func__);
03736155
AH		 2394 return -EINVAL;
2395 }
2396
7314e9e7 2397 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2398 chip->select_chip(mtd, chipnr);
1da177e4 2399
7314e9e7
TG		 2400 /* Shift to get page */
2401 page = (int)(to >> chip->page_shift);
2402
2403 /*
2404 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2405 * of my DiskOnChip 2000 test units) will clear the whole data page too
2406 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2407 * it in the doc2000 driver in August 1999. dwmw2.
2408 */
ace4dfee 2409 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2410
2411 /* Check, if it is write protected */
2412 if (nand_check_wp(mtd))
8593fbc6 2413 return -EROFS;
61b03bd7 2414
1da177e4 2415 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2416 if (page == chip->pagebuf)
2417 chip->pagebuf = -1;
1da177e4 2418
7bc3312b 2419 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2420 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
7bc3312b
TG		 2421 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2422 memset(chip->oob_poi, 0xff, mtd->oobsize);
1da177e4 2423
7bc3312b
TG		 2424 if (status)
2425 return status;
1da177e4 2426
7014568b 2427 ops->oobretlen = ops->ooblen;
1da177e4 2428
7bc3312b 2429 return 0;
8593fbc6
TG		 2430}
2431
2432/**
2433 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2434 * @mtd: MTD device structure
844d3b42 2435 * @to: offset to write to
8593fbc6
TG		 2436 * @ops: oob operation description structure
2437 */
2438static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2439 struct mtd_oob_ops *ops)
2440{
8593fbc6
TG		 2441 struct nand_chip *chip = mtd->priv;
2442 int ret = -ENOTSUPP;
2443
2444 ops->retlen = 0;
2445
2446 /* Do not allow writes past end of device */
7014568b 2447 if (ops->datbuf && (to + ops->len) > mtd->size) {
20d8e248 2448 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2449 "end of device\n", __func__);
8593fbc6
TG		 2450 return -EINVAL;
2451 }
2452
7bc3312b 2453 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2454
f8ac0414 2455 switch (ops->mode) {
8593fbc6
TG		 2456 case MTD_OOB_PLACE:
2457 case MTD_OOB_AUTO:
8593fbc6 2458 case MTD_OOB_RAW:
8593fbc6
TG		 2459 break;
2460
2461 default:
2462 goto out;
2463 }
2464
2465 if (!ops->datbuf)
2466 ret = nand_do_write_oob(mtd, to, ops);
2467 else
2468 ret = nand_do_write_ops(mtd, to, ops);
2469
7351d3a5 2470out:
1da177e4 2471 nand_release_device(mtd);
1da177e4
LT		 2472 return ret;
2473}
2474
1da177e4
LT		 2475/**
2476 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2477 * @mtd: MTD device structure
2478 * @page: the page address of the block which will be erased
2479 *
2480 * Standard erase command for NAND chips
2481 */
e0c7d767 2482static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2483{
ace4dfee 2484 struct nand_chip *chip = mtd->priv;
1da177e4 2485 /* Send commands to erase a block */
ace4dfee
TG		 2486 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2487 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2488}
2489
2490/**
2491 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2492 * @mtd: MTD device structure
2493 * @page: the page address of the block which will be erased
2494 *
2495 * AND multi block erase command function
2496 * Erase 4 consecutive blocks
2497 */
e0c7d767 2498static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2499{
ace4dfee 2500 struct nand_chip *chip = mtd->priv;
1da177e4 2501 /* Send commands to erase a block */
ace4dfee
TG		 2502 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2503 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2504 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2505 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2506 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2507}
2508
2509/**
2510 * nand_erase - [MTD Interface] erase block(s)
2511 * @mtd: MTD device structure
2512 * @instr: erase instruction
2513 *
2514 * Erase one ore more blocks
2515 */
e0c7d767 2516static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2517{
e0c7d767 2518 return nand_erase_nand(mtd, instr, 0);
1da177e4 2519}
61b03bd7 2520
30f464b7 2521#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2522/**
ace4dfee 2523 * nand_erase_nand - [Internal] erase block(s)
1da177e4
LT		 2524 * @mtd: MTD device structure
2525 * @instr: erase instruction
2526 * @allowbbt: allow erasing the bbt area
2527 *
2528 * Erase one ore more blocks
2529 */
ace4dfee
TG		 2530int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2531 int allowbbt)
1da177e4 2532{
69423d99 2533 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2534 struct nand_chip *chip = mtd->priv;
f8ac0414 2535 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2536 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2537 loff_t len;
1da177e4 2538
20d8e248 2539 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2540 __func__, (unsigned long long)instr->addr,
2541 (unsigned long long)instr->len);
1da177e4 2542
6fe5a6ac 2543 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2544 return -EINVAL;
1da177e4 2545
bb0eb217 2546 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2547
2548 /* Grab the lock and see if the device is available */
ace4dfee 2549 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2550
2551 /* Shift to get first page */
ace4dfee
TG		 2552 page = (int)(instr->addr >> chip->page_shift);
2553 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2554
2555 /* Calculate pages in each block */
ace4dfee 2556 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2557
2558 /* Select the NAND device */
ace4dfee 2559 chip->select_chip(mtd, chipnr);
1da177e4 2560
1da177e4
LT		 2561 /* Check, if it is write protected */
2562 if (nand_check_wp(mtd)) {
20d8e248 2563 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2564 __func__);
1da177e4
LT		 2565 instr->state = MTD_ERASE_FAILED;
2566 goto erase_exit;
2567 }
2568
ace4dfee
TG		 2569 /*
2570 * If BBT requires refresh, set the BBT page mask to see if the BBT
2571 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2572 * can not be matched. This is also done when the bbt is actually
2573 * erased to avoid recusrsive updates
2574 */
2575 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2576 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2577
1da177e4
LT		 2578 /* Loop through the pages */
2579 len = instr->len;
2580
2581 instr->state = MTD_ERASING;
2582
2583 while (len) {
ace4dfee
TG		 2584 /*
2585 * heck if we have a bad block, we do not erase bad blocks !
2586 */
2587 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2588 chip->page_shift, 0, allowbbt)) {
20d8e248 2589 printk(KERN_WARNING "%s: attempt to erase a bad block "
2590 "at page 0x%08x\n", __func__, page);
1da177e4
LT		 2591 instr->state = MTD_ERASE_FAILED;
2592 goto erase_exit;
2593 }
61b03bd7 2594
ace4dfee
TG		 2595 /*
2596 * Invalidate the page cache, if we erase the block which
2597 * contains the current cached page
2598 */
2599 if (page <= chip->pagebuf && chip->pagebuf <
2600 (page + pages_per_block))
2601 chip->pagebuf = -1;
1da177e4 2602
ace4dfee 2603 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2604
7bc3312b 2605 status = chip->waitfunc(mtd, chip);
1da177e4 2606
ace4dfee
TG		 2607 /*
2608 * See if operation failed and additional status checks are
2609 * available
2610 */
2611 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2612 status = chip->errstat(mtd, chip, FL_ERASING,
2613 status, page);
068e3c0a 2614
1da177e4 2615 /* See if block erase succeeded */
a4ab4c5d 2616 if (status & NAND_STATUS_FAIL) {
20d8e248 2617 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2618 "page 0x%08x\n", __func__, page);
1da177e4 2619 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2620 instr->fail_addr =
2621 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2622 goto erase_exit;
2623 }
30f464b7 2624
ace4dfee
TG		 2625 /*
2626 * If BBT requires refresh, set the BBT rewrite flag to the
2627 * page being erased
2628 */
2629 if (bbt_masked_page != 0xffffffff &&
2630 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2631 rewrite_bbt[chipnr] =
2632 ((loff_t)page << chip->page_shift);
61b03bd7 2633
1da177e4 2634 /* Increment page address and decrement length */
ace4dfee 2635 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2636 page += pages_per_block;
2637
2638 /* Check, if we cross a chip boundary */
ace4dfee 2639 if (len && !(page & chip->pagemask)) {
1da177e4 2640 chipnr++;
ace4dfee
TG		 2641 chip->select_chip(mtd, -1);
2642 chip->select_chip(mtd, chipnr);
30f464b7 2643
ace4dfee
TG		 2644 /*
2645 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2646 * page mask to see if this BBT should be rewritten
2647 */
2648 if (bbt_masked_page != 0xffffffff &&
2649 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2650 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2651 BBT_PAGE_MASK;
1da177e4
LT		 2652 }
2653 }
2654 instr->state = MTD_ERASE_DONE;
2655
7351d3a5 2656erase_exit:
1da177e4
LT		 2657
2658 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2659
2660 /* Deselect and wake up anyone waiting on the device */
2661 nand_release_device(mtd);
2662
49defc01
DW		 2663 /* Do call back function */
2664 if (!ret)
2665 mtd_erase_callback(instr);
2666
ace4dfee
TG		 2667 /*
2668 * If BBT requires refresh and erase was successful, rewrite any
2669 * selected bad block tables
2670 */
2671 if (bbt_masked_page == 0xffffffff || ret)
2672 return ret;
2673
2674 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2675 if (!rewrite_bbt[chipnr])
2676 continue;
2677 /* update the BBT for chip */
20d8e248 2678 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2679 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2680 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
ace4dfee 2681 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2682 }
2683
1da177e4
LT		 2684 /* Return more or less happy */
2685 return ret;
2686}
2687
2688/**
2689 * nand_sync - [MTD Interface] sync
2690 * @mtd: MTD device structure
2691 *
2692 * Sync is actually a wait for chip ready function
2693 */
e0c7d767 2694static void nand_sync(struct mtd_info *mtd)
1da177e4 2695{
ace4dfee 2696 struct nand_chip *chip = mtd->priv;
1da177e4 2697
20d8e248 2698 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
1da177e4
LT		 2699
2700 /* Grab the lock and see if the device is available */
ace4dfee 2701 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2702 /* Release it and go back */
e0c7d767 2703 nand_release_device(mtd);
1da177e4
LT		 2704}
2705
1da177e4 2706/**
ace4dfee 2707 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1da177e4 2708 * @mtd: MTD device structure
844d3b42 2709 * @offs: offset relative to mtd start
1da177e4 2710 */
ace4dfee 2711static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2712{
2713 /* Check for invalid offset */
ace4dfee 2714 if (offs > mtd->size)
1da177e4 2715 return -EINVAL;
61b03bd7 2716
ace4dfee 2717 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2718}
2719
2720/**
ace4dfee 2721 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1da177e4
LT		 2722 * @mtd: MTD device structure
2723 * @ofs: offset relative to mtd start
2724 */
e0c7d767 2725static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2726{
ace4dfee 2727 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2728 int ret;
2729
f8ac0414
FF		 2730 ret = nand_block_isbad(mtd, ofs);
2731 if (ret) {
e0c7d767 2732 /* If it was bad already, return success and do nothing. */
1da177e4
LT		 2733 if (ret > 0)
2734 return 0;
e0c7d767
DW		 2735 return ret;
2736 }
1da177e4 2737
ace4dfee 2738 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2739}
2740
962034f4
VW		 2741/**
2742 * nand_suspend - [MTD Interface] Suspend the NAND flash
2743 * @mtd: MTD device structure
2744 */
2745static int nand_suspend(struct mtd_info *mtd)
2746{
ace4dfee 2747 struct nand_chip *chip = mtd->priv;
962034f4 2748
ace4dfee 2749 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2750}
2751
2752/**
2753 * nand_resume - [MTD Interface] Resume the NAND flash
2754 * @mtd: MTD device structure
2755 */
2756static void nand_resume(struct mtd_info *mtd)
2757{
ace4dfee 2758 struct nand_chip *chip = mtd->priv;
962034f4 2759
ace4dfee 2760 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2761 nand_release_device(mtd);
2762 else
20d8e248 2763 printk(KERN_ERR "%s called for a chip which is not "
2764 "in suspended state\n", __func__);
962034f4
VW		 2765}
2766
7aa65bfd
TG		 2767/*
2768 * Set default functions
2769 */
ace4dfee 2770static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2771{
1da177e4 2772 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2773 if (!chip->chip_delay)
2774 chip->chip_delay = 20;
1da177e4
LT		 2775
2776 /* check, if a user supplied command function given */
ace4dfee
TG		 2777 if (chip->cmdfunc == NULL)
2778 chip->cmdfunc = nand_command;
1da177e4
LT		 2779
2780 /* check, if a user supplied wait function given */
ace4dfee
TG		 2781 if (chip->waitfunc == NULL)
2782 chip->waitfunc = nand_wait;
2783
2784 if (!chip->select_chip)
2785 chip->select_chip = nand_select_chip;
2786 if (!chip->read_byte)
2787 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2788 if (!chip->read_word)
2789 chip->read_word = nand_read_word;
2790 if (!chip->block_bad)
2791 chip->block_bad = nand_block_bad;
2792 if (!chip->block_markbad)
2793 chip->block_markbad = nand_default_block_markbad;
2794 if (!chip->write_buf)
2795 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2796 if (!chip->read_buf)
2797 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2798 if (!chip->verify_buf)
2799 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2800 if (!chip->scan_bbt)
2801 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2802
2803 if (!chip->controller) {
2804 chip->controller = &chip->hwcontrol;
2805 spin_lock_init(&chip->controller->lock);
2806 init_waitqueue_head(&chip->controller->wq);
2807 }
2808
7aa65bfd
TG		 2809}
2810
d1e1f4e4
FF		 2811/*
2812 * sanitize ONFI strings so we can safely print them
2813 */
2814static void sanitize_string(uint8_t *s, size_t len)
2815{
2816 ssize_t i;
2817
2818 /* null terminate */
2819 s[len - 1] = 0;
2820
2821 /* remove non printable chars */
2822 for (i = 0; i < len - 1; i++) {
2823 if (s[i] < ' ' || s[i] > 127)
2824 s[i] = '?';
2825 }
2826
2827 /* remove trailing spaces */
2828 strim(s);
2829}
2830
2831static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2832{
2833 int i;
2834 while (len--) {
2835 crc ^= *p++ << 8;
2836 for (i = 0; i < 8; i++)
2837 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2838 }
2839
2840 return crc;
2841}
2842
6fb277ba
FF		 2843/*
2844 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2845 */
2846static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2847 int busw)
2848{
2849 struct nand_onfi_params *p = &chip->onfi_params;
2850 int i;
2851 int val;
2852
2853 /* try ONFI for unknow chip or LP */
2854 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2855 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2856 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2857 return 0;
2858
2859 printk(KERN_INFO "ONFI flash detected\n");
2860 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2861 for (i = 0; i < 3; i++) {
2862 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2863 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2864 le16_to_cpu(p->crc)) {
2865 printk(KERN_INFO "ONFI param page %d valid\n", i);
2866 break;
2867 }
2868 }
2869
2870 if (i == 3)
2871 return 0;
2872
2873 /* check version */
2874 val = le16_to_cpu(p->revision);
2875 if (val == 1 || val > (1 << 4)) {
2876 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2877 __func__, val);
2878 return 0;
2879 }
2880
2881 if (val & (1 << 4))
2882 chip->onfi_version = 22;
2883 else if (val & (1 << 3))
2884 chip->onfi_version = 21;
2885 else if (val & (1 << 2))
2886 chip->onfi_version = 20;
2887 else
2888 chip->onfi_version = 10;
2889
2890 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2891 sanitize_string(p->model, sizeof(p->model));
2892 if (!mtd->name)
2893 mtd->name = p->model;
2894 mtd->writesize = le32_to_cpu(p->byte_per_page);
2895 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2896 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4ccb3b44 2897 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
6fb277ba
FF		 2898 busw = 0;
2899 if (le16_to_cpu(p->features) & 1)
2900 busw = NAND_BUSWIDTH_16;
2901
2902 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2903 chip->options |= (NAND_NO_READRDY |
2904 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2905
2906 return 1;
2907}
2908
7aa65bfd 2909/*
ace4dfee 2910 * Get the flash and manufacturer id and lookup if the type is supported
7aa65bfd
TG		 2911 */
2912static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2913 struct nand_chip *chip,
7351d3a5
FF		 2914 int busw,
2915 int *maf_id, int *dev_id,
5e81e88a 2916 struct nand_flash_dev *type)
7aa65bfd 2917{
d1e1f4e4 2918 int i, maf_idx;
426c457a 2919 u8 id_data[8];
6fb277ba 2920 int ret;
1da177e4
LT		 2921
2922 /* Select the device */
ace4dfee 2923 chip->select_chip(mtd, 0);
1da177e4 2924
ef89a880
KB		 2925 /*
2926 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2927 * after power-up
2928 */
2929 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2930
1da177e4 2931 /* Send the command for reading device ID */
ace4dfee 2932 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2933
2934 /* Read manufacturer and device IDs */
ace4dfee 2935 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2936 *dev_id = chip->read_byte(mtd);
1da177e4 2937
ed8165c7
BD		 2938 /* Try again to make sure, as some systems the bus-hold or other
2939 * interface concerns can cause random data which looks like a
2940 * possibly credible NAND flash to appear. If the two results do
2941 * not match, ignore the device completely.
2942 */
2943
2944 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2945
d1e1f4e4 2946 for (i = 0; i < 2; i++)
426c457a 2947 id_data[i] = chip->read_byte(mtd);
ed8165c7 2948
d1e1f4e4 2949 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
ed8165c7
BD		 2950 printk(KERN_INFO "%s: second ID read did not match "
2951 "%02x,%02x against %02x,%02x\n", __func__,
d1e1f4e4 2952 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2953 return ERR_PTR(-ENODEV);
2954 }
2955
7aa65bfd 2956 if (!type)
5e81e88a
DW		 2957 type = nand_flash_ids;
2958
2959 for (; type->name != NULL; type++)
d1e1f4e4 2960 if (*dev_id == type->id)
f8ac0414 2961 break;
5e81e88a 2962
d1e1f4e4
FF		 2963 chip->onfi_version = 0;
2964 if (!type->name || !type->pagesize) {
6fb277ba
FF		 2965 /* Check is chip is ONFI compliant */
2966 ret = nand_flash_detect_onfi(mtd, chip, busw);
2967 if (ret)
2968 goto ident_done;
d1e1f4e4
FF		 2969 }
2970
2971 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2972
2973 /* Read entire ID string */
2974
2975 for (i = 0; i < 8; i++)
2976 id_data[i] = chip->read_byte(mtd);
2977
5e81e88a 2978 if (!type->name)
7aa65bfd
TG		 2979 return ERR_PTR(-ENODEV);
2980
ba0251fe
TG		 2981 if (!mtd->name)
2982 mtd->name = type->name;
2983
69423d99 2984 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 2985
12a40a57
HS		 2986 if (!type->pagesize && chip->init_size) {
2987 /* set the pagesize, oobsize, erasesize by the driver*/
2988 busw = chip->init_size(mtd, chip, id_data);
2989 } else if (!type->pagesize) {
7aa65bfd 2990 int extid;
29072b96 2991 /* The 3rd id byte holds MLC / multichip data */
426c457a 2992 chip->cellinfo = id_data[2];
7aa65bfd 2993 /* The 4th id byte is the important one */
426c457a 2994 extid = id_data[3];
61b03bd7 2995
426c457a
KC		 2996 /*
2997 * Field definitions are in the following datasheets:
2998 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 2999 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 3000 *
3001 * Check for wraparound + Samsung ID + nonzero 6th byte
3002 * to decide what to do.
3003 */
3004 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3005 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 3006 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 3007 id_data[5] != 0x00) {
3008 /* Calc pagesize */
3009 mtd->writesize = 2048 << (extid & 0x03);
3010 extid >>= 2;
3011 /* Calc oobsize */
34c5bf6c
BN		 3012 switch (extid & 0x03) {
3013 case 1:
3014 mtd->oobsize = 128;
3015 break;
3016 case 2:
3017 mtd->oobsize = 218;
3018 break;
3019 case 3:
3020 mtd->oobsize = 400;
3021 break;
3022 default:
3023 mtd->oobsize = 436;
3024 break;
3025 }
426c457a
KC		 3026 extid >>= 2;
3027 /* Calc blocksize */
3028 mtd->erasesize = (128 * 1024) <<
3029 (((extid >> 1) & 0x04) | (extid & 0x03));
3030 busw = 0;
3031 } else {
3032 /* Calc pagesize */
3033 mtd->writesize = 1024 << (extid & 0x03);
3034 extid >>= 2;
3035 /* Calc oobsize */
3036 mtd->oobsize = (8 << (extid & 0x01)) *
3037 (mtd->writesize >> 9);
3038 extid >>= 2;
3039 /* Calc blocksize. Blocksize is multiples of 64KiB */
3040 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3041 extid >>= 2;
3042 /* Get buswidth information */
3043 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3044 }
7aa65bfd
TG		 3045 } else {
3046 /*
ace4dfee 3047 * Old devices have chip data hardcoded in the device id table
7aa65bfd 3048 */
ba0251fe
TG		 3049 mtd->erasesize = type->erasesize;
3050 mtd->writesize = type->pagesize;
4cbb9b80 3051 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3052 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3053
3054 /*
3055 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3056 * some Spansion chips have erasesize that conflicts with size
3057 * listed in nand_ids table
3058 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3059 */
3060 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3061 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3062 id_data[7] == 0x00 && mtd->writesize == 512) {
3063 mtd->erasesize = 128 * 1024;
3064 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3065 }
7aa65bfd 3066 }
d1e1f4e4
FF		 3067 /* Get chip options, preserve non chip based options */
3068 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3069 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3070
3071 /* Check if chip is a not a samsung device. Do not clear the
3072 * options for chips which are not having an extended id.
3073 */
3074 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3075 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3076ident_done:
3077
3078 /*
3079 * Set chip as a default. Board drivers can override it, if necessary
3080 */
3081 chip->options |= NAND_NO_AUTOINCR;
1da177e4 3082
7aa65bfd 3083 /* Try to identify manufacturer */
9a909867 3084 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3085 if (nand_manuf_ids[maf_idx].id == *maf_id)
3086 break;
3087 }
0ea4a755 3088
7aa65bfd
TG		 3089 /*
3090 * Check, if buswidth is correct. Hardware drivers should set
ace4dfee 3091 * chip correct !
7aa65bfd 3092 */
ace4dfee 3093 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
7aa65bfd
TG		 3094 printk(KERN_INFO "NAND device: Manufacturer ID:"
3095 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
d1e1f4e4 3096 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
7aa65bfd 3097 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
ace4dfee 3098 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
7aa65bfd
TG		 3099 busw ? 16 : 8);
3100 return ERR_PTR(-EINVAL);
3101 }
61b03bd7 3102
7aa65bfd 3103 /* Calculate the address shift from the page size */
ace4dfee 3104 chip->page_shift = ffs(mtd->writesize) - 1;
7aa65bfd 3105 /* Convert chipsize to number of pages per chip -1. */
ace4dfee 3106 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3107
ace4dfee 3108 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3109 ffs(mtd->erasesize) - 1;
69423d99
AH		 3110 if (chip->chipsize & 0xffffffff)
3111 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3112 else {
3113 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3114 chip->chip_shift += 32 - 1;
3115 }
1da177e4 3116
7aa65bfd 3117 /* Set the bad block position */
065a1ed8 3118 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3119 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3120 else
3121 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3122
b60b08b0
KC		 3123 /*
3124 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3125 * on Samsung and Hynix MLC devices; stored in first two pages
3126 * of each block on Micron devices with 2KiB pages and on
13ed7aed
BN		 3127 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3128 * only the first page.
b60b08b0
KC		 3129 */
3130 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3131 (*maf_id == NAND_MFR_SAMSUNG ||
3132 *maf_id == NAND_MFR_HYNIX))
30fe8115 3133 chip->options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3134 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3135 (*maf_id == NAND_MFR_SAMSUNG ||
3136 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3137 *maf_id == NAND_MFR_TOSHIBA ||
c7b28e25
BN		 3138 *maf_id == NAND_MFR_AMD)) ||
3139 (mtd->writesize == 2048 &&
3140 *maf_id == NAND_MFR_MICRON))
3141 chip->options |= NAND_BBT_SCAN2NDPAGE;
3142
58373ff0
BN		 3143 /*
3144 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
3145 */
3146 if (!(busw & NAND_BUSWIDTH_16) &&
3147 *maf_id == NAND_MFR_STMICRO &&
3148 mtd->writesize == 2048) {
3149 chip->options |= NAND_BBT_SCANBYTE1AND6;
3150 chip->badblockpos = 0;
3151 }
b60b08b0 3152
7aa65bfd 3153 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3154 if (chip->options & NAND_4PAGE_ARRAY)
3155 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3156 else
ace4dfee 3157 chip->erase_cmd = single_erase_cmd;
7aa65bfd
TG		 3158
3159 /* Do not replace user supplied command function ! */
ace4dfee
TG		 3160 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3161 chip->cmdfunc = nand_command_lp;
7aa65bfd 3162
d1e1f4e4 3163 /* TODO onfi flash name */
7aa65bfd 3164 printk(KERN_INFO "NAND device: Manufacturer ID:"
d1e1f4e4
FF		 3165 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3166 nand_manuf_ids[maf_idx].name,
f8ac0414 3167 chip->onfi_version ? type->name : chip->onfi_params.model);
7aa65bfd
TG		 3168
3169 return type;
3170}
3171
7aa65bfd 3172/**
3b85c321
DW		 3173 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3174 * @mtd: MTD device structure
3175 * @maxchips: Number of chips to scan for
5e81e88a 3176 * @table: Alternative NAND ID table
7aa65bfd 3177 *
3b85c321
DW		 3178 * This is the first phase of the normal nand_scan() function. It
3179 * reads the flash ID and sets up MTD fields accordingly.
7aa65bfd 3180 *
3b85c321 3181 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3182 */
5e81e88a
DW		 3183int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3184 struct nand_flash_dev *table)
7aa65bfd 3185{
d1e1f4e4 3186 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3187 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3188 struct nand_flash_dev *type;
3189
7aa65bfd 3190 /* Get buswidth to select the correct functions */
ace4dfee 3191 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3192 /* Set the default functions */
ace4dfee 3193 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3194
3195 /* Read the flash type */
7351d3a5
FF		 3196 type = nand_get_flash_type(mtd, chip, busw,
3197 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3198
3199 if (IS_ERR(type)) {
b1c6e6db
BD		 3200 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3201 printk(KERN_WARNING "No NAND device found.\n");
ace4dfee 3202 chip->select_chip(mtd, -1);
7aa65bfd 3203 return PTR_ERR(type);
1da177e4
LT		 3204 }
3205
7aa65bfd 3206 /* Check for a chip array */
e0c7d767 3207 for (i = 1; i < maxchips; i++) {
ace4dfee 3208 chip->select_chip(mtd, i);
ef89a880
KB		 3209 /* See comment in nand_get_flash_type for reset */
3210 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3211 /* Send the command for reading device ID */
ace4dfee 3212 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3213 /* Read manufacturer and device IDs */
ace4dfee 3214 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3215 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3216 break;
3217 }
3218 if (i > 1)
3219 printk(KERN_INFO "%d NAND chips detected\n", i);
61b03bd7 3220
1da177e4 3221 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3222 chip->numchips = i;
3223 mtd->size = i * chip->chipsize;
7aa65bfd 3224
3b85c321
DW		 3225 return 0;
3226}
7351d3a5 3227EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3228
3229
3230/**
3231 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3232 * @mtd: MTD device structure
3b85c321
DW		 3233 *
3234 * This is the second phase of the normal nand_scan() function. It
3235 * fills out all the uninitialized function pointers with the defaults
3236 * and scans for a bad block table if appropriate.
3237 */
3238int nand_scan_tail(struct mtd_info *mtd)
3239{
3240 int i;
3241 struct nand_chip *chip = mtd->priv;
3242
4bf63fcb
DW		 3243 if (!(chip->options & NAND_OWN_BUFFERS))
3244 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3245 if (!chip->buffers)
3246 return -ENOMEM;
3247
7dcdcbef 3248 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3249 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3250
7aa65bfd
TG		 3251 /*
3252 * If no default placement scheme is given, select an appropriate one
3253 */
5bd34c09 3254 if (!chip->ecc.layout) {
61b03bd7 3255 switch (mtd->oobsize) {
1da177e4 3256 case 8:
5bd34c09 3257 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3258 break;
3259 case 16:
5bd34c09 3260 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3261 break;
3262 case 64:
5bd34c09 3263 chip->ecc.layout = &nand_oob_64;
1da177e4 3264 break;
81ec5364
TG		 3265 case 128:
3266 chip->ecc.layout = &nand_oob_128;
3267 break;
1da177e4 3268 default:
7aa65bfd
TG		 3269 printk(KERN_WARNING "No oob scheme defined for "
3270 "oobsize %d\n", mtd->oobsize);
1da177e4
LT		 3271 BUG();
3272 }
3273 }
61b03bd7 3274
956e944c
DW		 3275 if (!chip->write_page)
3276 chip->write_page = nand_write_page;
3277
61b03bd7 3278 /*
7aa65bfd
TG		 3279 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3280 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3281 */
956e944c 3282
ace4dfee 3283 switch (chip->ecc.mode) {
6e0cb135
SN		 3284 case NAND_ECC_HW_OOB_FIRST:
3285 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3286 if (!chip->ecc.calculate || !chip->ecc.correct ||
3287 !chip->ecc.hwctl) {
3288 printk(KERN_WARNING "No ECC functions supplied; "
3289 "Hardware ECC not possible\n");
3290 BUG();
3291 }
3292 if (!chip->ecc.read_page)
3293 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3294
6dfc6d25 3295 case NAND_ECC_HW:
f5bbdacc
TG		 3296 /* Use standard hwecc read page function ? */
3297 if (!chip->ecc.read_page)
3298 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3299 if (!chip->ecc.write_page)
3300 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3301 if (!chip->ecc.read_page_raw)
3302 chip->ecc.read_page_raw = nand_read_page_raw;
3303 if (!chip->ecc.write_page_raw)
3304 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3305 if (!chip->ecc.read_oob)
3306 chip->ecc.read_oob = nand_read_oob_std;
3307 if (!chip->ecc.write_oob)
3308 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3309
6dfc6d25 3310 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3311 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3312 !chip->ecc.hwctl) &&
3313 (!chip->ecc.read_page ||
1c45f604 3314 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3315 !chip->ecc.write_page ||
1c45f604 3316 chip->ecc.write_page == nand_write_page_hwecc)) {
6e0cb135 3317 printk(KERN_WARNING "No ECC functions supplied; "
6dfc6d25
TG		 3318 "Hardware ECC not possible\n");
3319 BUG();
3320 }
f75e5097 3321 /* Use standard syndrome read/write page function ? */
f5bbdacc
TG		 3322 if (!chip->ecc.read_page)
3323 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3324 if (!chip->ecc.write_page)
3325 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3326 if (!chip->ecc.read_page_raw)
3327 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3328 if (!chip->ecc.write_page_raw)
3329 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3330 if (!chip->ecc.read_oob)
3331 chip->ecc.read_oob = nand_read_oob_syndrome;
3332 if (!chip->ecc.write_oob)
3333 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3334
ace4dfee 3335 if (mtd->writesize >= chip->ecc.size)
6dfc6d25
TG		 3336 break;
3337 printk(KERN_WARNING "%d byte HW ECC not possible on "
3338 "%d byte page size, fallback to SW ECC\n",
ace4dfee
TG		 3339 chip->ecc.size, mtd->writesize);
3340 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3341
6dfc6d25 3342 case NAND_ECC_SOFT:
ace4dfee
TG		 3343 chip->ecc.calculate = nand_calculate_ecc;
3344 chip->ecc.correct = nand_correct_data;
f5bbdacc 3345 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3346 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3347 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3348 chip->ecc.read_page_raw = nand_read_page_raw;
3349 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3350 chip->ecc.read_oob = nand_read_oob_std;
3351 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3352 if (!chip->ecc.size)
3353 chip->ecc.size = 256;
ace4dfee 3354 chip->ecc.bytes = 3;
1da177e4 3355 break;
61b03bd7
TG		 3356
3357 case NAND_ECC_NONE:
7aa65bfd
TG		 3358 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3359 "This is not recommended !!\n");
8593fbc6
TG		 3360 chip->ecc.read_page = nand_read_page_raw;
3361 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3362 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3363 chip->ecc.read_page_raw = nand_read_page_raw;
3364 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3365 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3366 chip->ecc.size = mtd->writesize;
3367 chip->ecc.bytes = 0;
1da177e4 3368 break;
956e944c 3369
1da177e4 3370 default:
7aa65bfd 3371 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
ace4dfee 3372 chip->ecc.mode);
61b03bd7 3373 BUG();
1da177e4 3374 }
61b03bd7 3375
5bd34c09
TG		 3376 /*
3377 * The number of bytes available for a client to place data into
3378 * the out of band area
3379 */
3380 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3381 for (i = 0; chip->ecc.layout->oobfree[i].length
3382 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3383 chip->ecc.layout->oobavail +=
3384 chip->ecc.layout->oobfree[i].length;
1f92267c 3385 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3386
7aa65bfd
TG		 3387 /*
3388 * Set the number of read / write steps for one page depending on ECC
3389 * mode
3390 */
ace4dfee 3391 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3392 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
6dfc6d25
TG		 3393 printk(KERN_WARNING "Invalid ecc parameters\n");
3394 BUG();
1da177e4 3395 }
f5bbdacc 3396 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3397
29072b96
TG		 3398 /*
3399 * Allow subpage writes up to ecc.steps. Not possible for MLC
3400 * FLASH.
3401 */
3402 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3403 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3404 switch (chip->ecc.steps) {
29072b96
TG		 3405 case 2:
3406 mtd->subpage_sft = 1;
3407 break;
3408 case 4:
3409 case 8:
81ec5364 3410 case 16:
29072b96
TG		 3411 mtd->subpage_sft = 2;
3412 break;
3413 }
3414 }
3415 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3416
04bbd0ea 3417 /* Initialize state */
ace4dfee 3418 chip->state = FL_READY;
1da177e4
LT		 3419
3420 /* De-select the device */
ace4dfee 3421 chip->select_chip(mtd, -1);
1da177e4
LT		 3422
3423 /* Invalidate the pagebuffer reference */
ace4dfee 3424 chip->pagebuf = -1;
1da177e4
LT		 3425
3426 /* Fill in remaining MTD driver data */
3427 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3428 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3429 MTD_CAP_NANDFLASH;
1da177e4
LT		 3430 mtd->erase = nand_erase;
3431 mtd->point = NULL;
3432 mtd->unpoint = NULL;
3433 mtd->read = nand_read;
3434 mtd->write = nand_write;
2af7c653 3435 mtd->panic_write = panic_nand_write;
1da177e4
LT		 3436 mtd->read_oob = nand_read_oob;
3437 mtd->write_oob = nand_write_oob;
1da177e4
LT		 3438 mtd->sync = nand_sync;
3439 mtd->lock = NULL;
3440 mtd->unlock = NULL;
962034f4
VW		 3441 mtd->suspend = nand_suspend;
3442 mtd->resume = nand_resume;
1da177e4
LT		 3443 mtd->block_isbad = nand_block_isbad;
3444 mtd->block_markbad = nand_block_markbad;
3445
5bd34c09
TG		 3446 /* propagate ecc.layout to mtd_info */
3447 mtd->ecclayout = chip->ecc.layout;
1da177e4 3448
0040bf38 3449 /* Check, if we should skip the bad block table scan */
ace4dfee 3450 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3451 return 0;
1da177e4
LT		 3452
3453 /* Build bad block table */
ace4dfee 3454 return chip->scan_bbt(mtd);
1da177e4 3455}
7351d3a5 3456EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3457
a6e6abd5 3458/* is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5
FF		 3459 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3460 * to call us from in-kernel code if the core NAND support is modular. */
3b85c321
DW		 3461#ifdef MODULE
3462#define caller_is_module() (1)
3463#else
3464#define caller_is_module() \
a6e6abd5 3465 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3466#endif
3467
3468/**
3469 * nand_scan - [NAND Interface] Scan for the NAND device
3470 * @mtd: MTD device structure
3471 * @maxchips: Number of chips to scan for
3472 *
3473 * This fills out all the uninitialized function pointers
3474 * with the defaults.
3475 * The flash ID is read and the mtd/chip structures are
3476 * filled with the appropriate values.
3477 * The mtd->owner field must be set to the module of the caller
3478 *
3479 */
3480int nand_scan(struct mtd_info *mtd, int maxchips)
3481{
3482 int ret;
3483
3484 /* Many callers got this wrong, so check for it for a while... */
3485 if (!mtd->owner && caller_is_module()) {
20d8e248 3486 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3487 __func__);
3b85c321
DW		 3488 BUG();
3489 }
3490
5e81e88a 3491 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3492 if (!ret)
3493 ret = nand_scan_tail(mtd);
3494 return ret;
3495}
7351d3a5 3496EXPORT_SYMBOL(nand_scan);
3b85c321 3497
1da177e4 3498/**
61b03bd7 3499 * nand_release - [NAND Interface] Free resources held by the NAND device
1da177e4
LT		 3500 * @mtd: MTD device structure
3501*/
e0c7d767 3502void nand_release(struct mtd_info *mtd)
1da177e4 3503{
ace4dfee 3504 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 3505
3506#ifdef CONFIG_MTD_PARTITIONS
3507 /* Deregister partitions */
e0c7d767 3508 del_mtd_partitions(mtd);
1da177e4
LT		 3509#endif
3510 /* Deregister the device */
e0c7d767 3511 del_mtd_device(mtd);
1da177e4 3512
fa671646 3513 /* Free bad block table memory */
ace4dfee 3514 kfree(chip->bbt);
4bf63fcb
DW		 3515 if (!(chip->options & NAND_OWN_BUFFERS))
3516 kfree(chip->buffers);
58373ff0
BN		 3517
3518 /* Free bad block descriptor memory */
3519 if (chip->badblock_pattern && chip->badblock_pattern->options
3520 & NAND_BBT_DYNAMICSTRUCT)
3521 kfree(chip->badblock_pattern);
1da177e4 3522}
e0c7d767 3523EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3524
3525static int __init nand_base_init(void)
3526{
3527 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3528 return 0;
3529}
3530
3531static void __exit nand_base_exit(void)
3532{
3533 led_trigger_unregister_simple(nand_led_trigger);
3534}
3535
3536module_init(nand_base_init);
3537module_exit(nand_base_exit);
3538
e0c7d767 3539MODULE_LICENSE("GPL");
7351d3a5
FF		 3540MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3541MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3542MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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