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Revert "drm/i915: Use crtc_state->active in primary check_plane func"
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Overview:
3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
61b03bd7 5 *
1da177e4 6 * Additional technical information is available on
8b2b403c 7 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 8 *
1da177e4 9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 11 *
ace4dfee 12 * Credits:
61b03bd7
TG		 13 * David Woodhouse for adding multichip support
14 *
1da177e4
LT		 15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
17 *
ace4dfee 18 * TODO:
1da177e4
LT		 19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 21 * if we have HW ECC support.
c0b8ba7b 22 * BBT table is not serialized, has to be fixed
1da177e4 23 *
1da177e4
LT		 24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
20171642
EG		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
552d9205 32#include <linux/module.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/errno.h>
7aa65bfd 35#include <linux/err.h>
1da177e4
LT		 36#include <linux/sched.h>
37#include <linux/slab.h>
66507c7b 38#include <linux/mm.h>
1da177e4
LT		 39#include <linux/types.h>
40#include <linux/mtd/mtd.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/nand_ecc.h>
193bd400 43#include <linux/mtd/nand_bch.h>
1da177e4
LT		 44#include <linux/interrupt.h>
45#include <linux/bitops.h>
8fe833c1 46#include <linux/leds.h>
7351d3a5 47#include <linux/io.h>
1da177e4 48#include <linux/mtd/partitions.h>
5844feea 49#include <linux/of_mtd.h>
1da177e4
LT		 50
51/* Define default oob placement schemes for large and small page devices */
5bd34c09 52static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 53 .eccbytes = 3,
54 .eccpos = {0, 1, 2},
5bd34c09
TG		 55 .oobfree = {
56 {.offset = 3,
57 .length = 2},
58 {.offset = 6,
f8ac0414 59 .length = 2} }
1da177e4
LT		 60};
61
5bd34c09 62static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 63 .eccbytes = 6,
64 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 65 .oobfree = {
66 {.offset = 8,
f8ac0414 67 . length = 8} }
1da177e4
LT		 68};
69
5bd34c09 70static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 71 .eccbytes = 24,
72 .eccpos = {
e0c7d767
DW		 73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 76 .oobfree = {
77 {.offset = 2,
f8ac0414 78 .length = 38} }
1da177e4
LT		 79};
80
81ec5364
TG		 81static struct nand_ecclayout nand_oob_128 = {
82 .eccbytes = 48,
83 .eccpos = {
84 80, 81, 82, 83, 84, 85, 86, 87,
85 88, 89, 90, 91, 92, 93, 94, 95,
86 96, 97, 98, 99, 100, 101, 102, 103,
87 104, 105, 106, 107, 108, 109, 110, 111,
88 112, 113, 114, 115, 116, 117, 118, 119,
89 120, 121, 122, 123, 124, 125, 126, 127},
90 .oobfree = {
91 {.offset = 2,
f8ac0414 92 .length = 78} }
81ec5364
TG		 93};
94
6a8214aa 95static int nand_get_device(struct mtd_info *mtd, int new_state);
1da177e4 96
8593fbc6
TG		 97static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
98 struct mtd_oob_ops *ops);
99
d470a97c 100/*
8e87d782 101 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 102 * compiled away when LED support is disabled.
103 */
104DEFINE_LED_TRIGGER(nand_led_trigger);
105
6fe5a6ac
VS		 106static int check_offs_len(struct mtd_info *mtd,
107 loff_t ofs, uint64_t len)
108{
109 struct nand_chip *chip = mtd->priv;
110 int ret = 0;
111
112 /* Start address must align on block boundary */
daae74ca 113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 114 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 115 ret = -EINVAL;
116 }
117
118 /* Length must align on block boundary */
daae74ca 119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 120 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 121 ret = -EINVAL;
122 }
123
6fe5a6ac
VS		 124 return ret;
125}
126
1da177e4
LT		 127/**
128 * nand_release_device - [GENERIC] release chip
8b6e50c9 129 * @mtd: MTD device structure
61b03bd7 130 *
b0bb6903 131 * Release chip lock and wake up anyone waiting on the device.
1da177e4 132 */
e0c7d767 133static void nand_release_device(struct mtd_info *mtd)
1da177e4 134{
ace4dfee 135 struct nand_chip *chip = mtd->priv;
1da177e4 136
a36ed299 137 /* Release the controller and the chip */
ace4dfee
TG		 138 spin_lock(&chip->controller->lock);
139 chip->controller->active = NULL;
140 chip->state = FL_READY;
141 wake_up(&chip->controller->wq);
142 spin_unlock(&chip->controller->lock);
1da177e4
LT		 143}
144
145/**
146 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 147 * @mtd: MTD device structure
1da177e4 148 *
7854d3f7 149 * Default read function for 8bit buswidth
1da177e4 150 */
58dd8f2b 151static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 152{
ace4dfee
TG		 153 struct nand_chip *chip = mtd->priv;
154 return readb(chip->IO_ADDR_R);
1da177e4
LT		 155}
156
1da177e4 157/**
7854d3f7 158 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 159 * @mtd: MTD device structure
1da177e4 160 *
7854d3f7
BN		 161 * Default read function for 16bit buswidth with endianness conversion.
162 *
1da177e4 163 */
58dd8f2b 164static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 165{
ace4dfee
TG		 166 struct nand_chip *chip = mtd->priv;
167 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 168}
169
1da177e4
LT		 170/**
171 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 172 * @mtd: MTD device structure
1da177e4 173 *
7854d3f7 174 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 175 */
176static u16 nand_read_word(struct mtd_info *mtd)
177{
ace4dfee
TG		 178 struct nand_chip *chip = mtd->priv;
179 return readw(chip->IO_ADDR_R);
1da177e4
LT		 180}
181
1da177e4
LT		 182/**
183 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 184 * @mtd: MTD device structure
185 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 186 *
187 * Default select function for 1 chip devices.
188 */
ace4dfee 189static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 190{
ace4dfee
TG		 191 struct nand_chip *chip = mtd->priv;
192
193 switch (chipnr) {
1da177e4 194 case -1:
ace4dfee 195 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 196 break;
197 case 0:
1da177e4
LT		 198 break;
199
200 default:
201 BUG();
202 }
203}
204
05f78359
UKK		 205/**
206 * nand_write_byte - [DEFAULT] write single byte to chip
207 * @mtd: MTD device structure
208 * @byte: value to write
209 *
210 * Default function to write a byte to I/O[7:0]
211 */
212static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
213{
214 struct nand_chip *chip = mtd->priv;
215
216 chip->write_buf(mtd, &byte, 1);
217}
218
219/**
220 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
221 * @mtd: MTD device structure
222 * @byte: value to write
223 *
224 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
225 */
226static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
227{
228 struct nand_chip *chip = mtd->priv;
229 uint16_t word = byte;
230
231 /*
232 * It's not entirely clear what should happen to I/O[15:8] when writing
233 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
234 *
235 * When the host supports a 16-bit bus width, only data is
236 * transferred at the 16-bit width. All address and command line
237 * transfers shall use only the lower 8-bits of the data bus. During
238 * command transfers, the host may place any value on the upper
239 * 8-bits of the data bus. During address transfers, the host shall
240 * set the upper 8-bits of the data bus to 00h.
241 *
242 * One user of the write_byte callback is nand_onfi_set_features. The
243 * four parameters are specified to be written to I/O[7:0], but this is
244 * neither an address nor a command transfer. Let's assume a 0 on the
245 * upper I/O lines is OK.
246 */
247 chip->write_buf(mtd, (uint8_t *)&word, 2);
248}
249
1da177e4
LT		 250/**
251 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 252 * @mtd: MTD device structure
253 * @buf: data buffer
254 * @len: number of bytes to write
1da177e4 255 *
7854d3f7 256 * Default write function for 8bit buswidth.
1da177e4 257 */
58dd8f2b 258static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 259{
ace4dfee 260 struct nand_chip *chip = mtd->priv;
1da177e4 261
76413839 262 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 263}
264
265/**
61b03bd7 266 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 267 * @mtd: MTD device structure
268 * @buf: buffer to store date
269 * @len: number of bytes to read
1da177e4 270 *
7854d3f7 271 * Default read function for 8bit buswidth.
1da177e4 272 */
58dd8f2b 273static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 274{
ace4dfee 275 struct nand_chip *chip = mtd->priv;
1da177e4 276
76413839 277 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 278}
279
1da177e4
LT		 280/**
281 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 282 * @mtd: MTD device structure
283 * @buf: data buffer
284 * @len: number of bytes to write
1da177e4 285 *
7854d3f7 286 * Default write function for 16bit buswidth.
1da177e4 287 */
58dd8f2b 288static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 289{
ace4dfee 290 struct nand_chip *chip = mtd->priv;
1da177e4 291 u16 *p = (u16 *) buf;
61b03bd7 292
76413839 293 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 294}
295
296/**
61b03bd7 297 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 298 * @mtd: MTD device structure
299 * @buf: buffer to store date
300 * @len: number of bytes to read
1da177e4 301 *
7854d3f7 302 * Default read function for 16bit buswidth.
1da177e4 303 */
58dd8f2b 304static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 305{
ace4dfee 306 struct nand_chip *chip = mtd->priv;
1da177e4 307 u16 *p = (u16 *) buf;
1da177e4 308
76413839 309 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 310}
311
1da177e4
LT		 312/**
313 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 314 * @mtd: MTD device structure
315 * @ofs: offset from device start
316 * @getchip: 0, if the chip is already selected
1da177e4 317 *
61b03bd7 318 * Check, if the block is bad.
1da177e4
LT		 319 */
320static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
321{
cdbec050 322 int page, chipnr, res = 0, i = 0;
ace4dfee 323 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 324 u16 bad;
325
5fb1549d 326 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 327 ofs += mtd->erasesize - mtd->writesize;
328
1a12f46a
TK		 329 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
330
1da177e4 331 if (getchip) {
ace4dfee 332 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 333
6a8214aa 334 nand_get_device(mtd, FL_READING);
1da177e4
LT		 335
336 /* Select the NAND device */
ace4dfee 337 chip->select_chip(mtd, chipnr);
1a12f46a 338 }
1da177e4 339
cdbec050
BN		 340 do {
341 if (chip->options & NAND_BUSWIDTH_16) {
342 chip->cmdfunc(mtd, NAND_CMD_READOOB,
343 chip->badblockpos & 0xFE, page);
344 bad = cpu_to_le16(chip->read_word(mtd));
345 if (chip->badblockpos & 0x1)
346 bad >>= 8;
347 else
348 bad &= 0xFF;
349 } else {
350 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
351 page);
352 bad = chip->read_byte(mtd);
353 }
354
355 if (likely(chip->badblockbits == 8))
356 res = bad != 0xFF;
e0b58d0a 357 else
cdbec050
BN		 358 res = hweight8(bad) < chip->badblockbits;
359 ofs += mtd->writesize;
360 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
361 i++;
362 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 363
b0bb6903
HS		 364 if (getchip) {
365 chip->select_chip(mtd, -1);
1da177e4 366 nand_release_device(mtd);
b0bb6903 367 }
61b03bd7 368
1da177e4
LT		 369 return res;
370}
371
372/**
5a0edb25 373 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
8b6e50c9
BN		 374 * @mtd: MTD device structure
375 * @ofs: offset from device start
1da177e4 376 *
8b6e50c9 377 * This is the default implementation, which can be overridden by a hardware
5a0edb25
BN		 378 * specific driver. It provides the details for writing a bad block marker to a
379 * block.
380 */
381static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
382{
383 struct nand_chip *chip = mtd->priv;
384 struct mtd_oob_ops ops;
385 uint8_t buf[2] = { 0, 0 };
386 int ret = 0, res, i = 0;
387
0ec56dc4 388 memset(&ops, 0, sizeof(ops));
5a0edb25
BN		 389 ops.oobbuf = buf;
390 ops.ooboffs = chip->badblockpos;
391 if (chip->options & NAND_BUSWIDTH_16) {
392 ops.ooboffs &= ~0x01;
393 ops.len = ops.ooblen = 2;
394 } else {
395 ops.len = ops.ooblen = 1;
396 }
397 ops.mode = MTD_OPS_PLACE_OOB;
398
399 /* Write to first/last page(s) if necessary */
400 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
401 ofs += mtd->erasesize - mtd->writesize;
402 do {
403 res = nand_do_write_oob(mtd, ofs, &ops);
404 if (!ret)
405 ret = res;
406
407 i++;
408 ofs += mtd->writesize;
409 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
410
411 return ret;
412}
413
414/**
415 * nand_block_markbad_lowlevel - mark a block bad
416 * @mtd: MTD device structure
417 * @ofs: offset from device start
418 *
419 * This function performs the generic NAND bad block marking steps (i.e., bad
420 * block table(s) and/or marker(s)). We only allow the hardware driver to
421 * specify how to write bad block markers to OOB (chip->block_markbad).
422 *
b32843b7 423 * We try operations in the following order:
e2414f4c 424 * (1) erase the affected block, to allow OOB marker to be written cleanly
b32843b7
BN		 425 * (2) write bad block marker to OOB area of affected block (unless flag
426 * NAND_BBT_NO_OOB_BBM is present)
427 * (3) update the BBT
428 * Note that we retain the first error encountered in (2) or (3), finish the
e2414f4c 429 * procedures, and dump the error in the end.
1da177e4 430*/
5a0edb25 431static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
1da177e4 432{
ace4dfee 433 struct nand_chip *chip = mtd->priv;
b32843b7 434 int res, ret = 0;
61b03bd7 435
b32843b7 436 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
00918429
BN		 437 struct erase_info einfo;
438
439 /* Attempt erase before marking OOB */
440 memset(&einfo, 0, sizeof(einfo));
441 einfo.mtd = mtd;
442 einfo.addr = ofs;
daae74ca 443 einfo.len = 1ULL << chip->phys_erase_shift;
00918429 444 nand_erase_nand(mtd, &einfo, 0);
1da177e4 445
b32843b7 446 /* Write bad block marker to OOB */
6a8214aa 447 nand_get_device(mtd, FL_WRITING);
5a0edb25 448 ret = chip->block_markbad(mtd, ofs);
c0b8ba7b 449 nand_release_device(mtd);
f1a28c02 450 }
e2414f4c 451
b32843b7
BN		 452 /* Mark block bad in BBT */
453 if (chip->bbt) {
454 res = nand_markbad_bbt(mtd, ofs);
e2414f4c
BN		 455 if (!ret)
456 ret = res;
457 }
458
f1a28c02
TG		 459 if (!ret)
460 mtd->ecc_stats.badblocks++;
c0b8ba7b 461
f1a28c02 462 return ret;
1da177e4
LT		 463}
464
61b03bd7 465/**
1da177e4 466 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 467 * @mtd: MTD device structure
1da177e4 468 *
8b6e50c9
BN		 469 * Check, if the device is write protected. The function expects, that the
470 * device is already selected.
1da177e4 471 */
e0c7d767 472static int nand_check_wp(struct mtd_info *mtd)
1da177e4 473{
ace4dfee 474 struct nand_chip *chip = mtd->priv;
93edbad6 475
8b6e50c9 476 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 477 if (chip->options & NAND_BROKEN_XD)
478 return 0;
479
1da177e4 480 /* Check the WP bit */
ace4dfee
TG		 481 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
482 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 483}
484
8471bb73 485/**
c30e1f79 486 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
8471bb73
EG		 487 * @mtd: MTD device structure
488 * @ofs: offset from device start
489 *
c30e1f79 490 * Check if the block is marked as reserved.
8471bb73
EG		 491 */
492static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
493{
494 struct nand_chip *chip = mtd->priv;
495
496 if (!chip->bbt)
497 return 0;
498 /* Return info from the table */
499 return nand_isreserved_bbt(mtd, ofs);
500}
501
1da177e4
LT		 502/**
503 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 504 * @mtd: MTD device structure
505 * @ofs: offset from device start
506 * @getchip: 0, if the chip is already selected
507 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 508 *
509 * Check, if the block is bad. Either by reading the bad block table or
510 * calling of the scan function.
511 */
2c0a2bed
TG		 512static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
513 int allowbbt)
1da177e4 514{
ace4dfee 515 struct nand_chip *chip = mtd->priv;
61b03bd7 516
ace4dfee
TG		 517 if (!chip->bbt)
518 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 519
1da177e4 520 /* Return info from the table */
e0c7d767 521 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 522}
523
2af7c653
SK		 524/**
525 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 526 * @mtd: MTD device structure
527 * @timeo: Timeout
2af7c653
SK		 528 *
529 * Helper function for nand_wait_ready used when needing to wait in interrupt
530 * context.
531 */
532static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
533{
534 struct nand_chip *chip = mtd->priv;
535 int i;
536
537 /* Wait for the device to get ready */
538 for (i = 0; i < timeo; i++) {
539 if (chip->dev_ready(mtd))
540 break;
541 touch_softlockup_watchdog();
542 mdelay(1);
543 }
544}
545
7854d3f7 546/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 547void nand_wait_ready(struct mtd_info *mtd)
3b88775c 548{
ace4dfee 549 struct nand_chip *chip = mtd->priv;
ca6a2489 550 unsigned long timeo = jiffies + msecs_to_jiffies(20);
3b88775c 551
2af7c653
SK		 552 /* 400ms timeout */
553 if (in_interrupt() || oops_in_progress)
554 return panic_nand_wait_ready(mtd, 400);
555
8fe833c1 556 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 557 /* Wait until command is processed or timeout occurs */
3b88775c 558 do {
ace4dfee 559 if (chip->dev_ready(mtd))
8fe833c1 560 break;
8446f1d3 561 touch_softlockup_watchdog();
61b03bd7 562 } while (time_before(jiffies, timeo));
8fe833c1 563 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 564}
4b648b02 565EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 566
60c70d66
RQ		 567/**
568 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
569 * @mtd: MTD device structure
570 * @timeo: Timeout in ms
571 *
572 * Wait for status ready (i.e. command done) or timeout.
573 */
574static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
575{
576 register struct nand_chip *chip = mtd->priv;
577
578 timeo = jiffies + msecs_to_jiffies(timeo);
579 do {
580 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
581 break;
582 touch_softlockup_watchdog();
583 } while (time_before(jiffies, timeo));
584};
585
1da177e4
LT		 586/**
587 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 588 * @mtd: MTD device structure
589 * @command: the command to be sent
590 * @column: the column address for this command, -1 if none
591 * @page_addr: the page address for this command, -1 if none
1da177e4 592 *
8b6e50c9 593 * Send command to NAND device. This function is used for small page devices
51148f1f 594 * (512 Bytes per page).
1da177e4 595 */
7abd3ef9
TG		 596static void nand_command(struct mtd_info *mtd, unsigned int command,
597 int column, int page_addr)
1da177e4 598{
ace4dfee 599 register struct nand_chip *chip = mtd->priv;
7abd3ef9 600 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 601
8b6e50c9 602 /* Write out the command to the device */
1da177e4
LT		 603 if (command == NAND_CMD_SEQIN) {
604 int readcmd;
605
28318776 606 if (column >= mtd->writesize) {
1da177e4 607 /* OOB area */
28318776 608 column -= mtd->writesize;
1da177e4
LT		 609 readcmd = NAND_CMD_READOOB;
610 } else if (column < 256) {
611 /* First 256 bytes --> READ0 */
612 readcmd = NAND_CMD_READ0;
613 } else {
614 column -= 256;
615 readcmd = NAND_CMD_READ1;
616 }
ace4dfee 617 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 618 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 619 }
ace4dfee 620 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 621
8b6e50c9 622 /* Address cycle, when necessary */
7abd3ef9
TG		 623 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
624 /* Serially input address */
625 if (column != -1) {
626 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 627 if (chip->options & NAND_BUSWIDTH_16 &&
628 !nand_opcode_8bits(command))
7abd3ef9 629 column >>= 1;
ace4dfee 630 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 631 ctrl &= ~NAND_CTRL_CHANGE;
632 }
633 if (page_addr != -1) {
ace4dfee 634 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 635 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 636 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 637 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 638 if (chip->chipsize > (32 << 20))
639 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 640 }
ace4dfee 641 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 642
643 /*
8b6e50c9
BN		 644 * Program and erase have their own busy handlers status and sequential
645 * in needs no delay
e0c7d767 646 */
1da177e4 647 switch (command) {
61b03bd7 648
1da177e4
LT		 649 case NAND_CMD_PAGEPROG:
650 case NAND_CMD_ERASE1:
651 case NAND_CMD_ERASE2:
652 case NAND_CMD_SEQIN:
653 case NAND_CMD_STATUS:
654 return;
655
656 case NAND_CMD_RESET:
ace4dfee 657 if (chip->dev_ready)
1da177e4 658 break;
ace4dfee
TG		 659 udelay(chip->chip_delay);
660 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 661 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 662 chip->cmd_ctrl(mtd,
663 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 664 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
665 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 666 return;
667
e0c7d767 668 /* This applies to read commands */
1da177e4 669 default:
61b03bd7 670 /*
1da177e4
LT		 671 * If we don't have access to the busy pin, we apply the given
672 * command delay
e0c7d767 673 */
ace4dfee
TG		 674 if (!chip->dev_ready) {
675 udelay(chip->chip_delay);
1da177e4 676 return;
61b03bd7 677 }
1da177e4 678 }
8b6e50c9
BN		 679 /*
680 * Apply this short delay always to ensure that we do wait tWB in
681 * any case on any machine.
682 */
e0c7d767 683 ndelay(100);
3b88775c
TG		 684
685 nand_wait_ready(mtd);
1da177e4
LT		 686}
687
688/**
689 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 690 * @mtd: MTD device structure
691 * @command: the command to be sent
692 * @column: the column address for this command, -1 if none
693 * @page_addr: the page address for this command, -1 if none
1da177e4 694 *
7abd3ef9 695 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 696 * devices. We don't have the separate regions as we have in the small page
697 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 698 */
7abd3ef9
TG		 699static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
700 int column, int page_addr)
1da177e4 701{
ace4dfee 702 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 703
704 /* Emulate NAND_CMD_READOOB */
705 if (command == NAND_CMD_READOOB) {
28318776 706 column += mtd->writesize;
1da177e4
LT		 707 command = NAND_CMD_READ0;
708 }
61b03bd7 709
7abd3ef9 710 /* Command latch cycle */
fb066ada 711 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 712
713 if (column != -1 || page_addr != -1) {
7abd3ef9 714 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 715
716 /* Serially input address */
717 if (column != -1) {
718 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 719 if (chip->options & NAND_BUSWIDTH_16 &&
720 !nand_opcode_8bits(command))
1da177e4 721 column >>= 1;
ace4dfee 722 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 723 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 724 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 725 }
1da177e4 726 if (page_addr != -1) {
ace4dfee
TG		 727 chip->cmd_ctrl(mtd, page_addr, ctrl);
728 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 729 NAND_NCE | NAND_ALE);
1da177e4 730 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 731 if (chip->chipsize > (128 << 20))
732 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 733 NAND_NCE | NAND_ALE);
1da177e4 734 }
1da177e4 735 }
ace4dfee 736 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 737
738 /*
8b6e50c9 739 * Program and erase have their own busy handlers status, sequential
7a442f17 740 * in and status need no delay.
30f464b7 741 */
1da177e4 742 switch (command) {
61b03bd7 743
1da177e4
LT		 744 case NAND_CMD_CACHEDPROG:
745 case NAND_CMD_PAGEPROG:
746 case NAND_CMD_ERASE1:
747 case NAND_CMD_ERASE2:
748 case NAND_CMD_SEQIN:
7bc3312b 749 case NAND_CMD_RNDIN:
1da177e4 750 case NAND_CMD_STATUS:
30f464b7 751 return;
1da177e4
LT		 752
753 case NAND_CMD_RESET:
ace4dfee 754 if (chip->dev_ready)
1da177e4 755 break;
ace4dfee 756 udelay(chip->chip_delay);
12efdde3
TG		 757 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
758 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
759 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
760 NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 761 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
762 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 763 return;
764
7bc3312b
TG		 765 case NAND_CMD_RNDOUT:
766 /* No ready / busy check necessary */
767 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
768 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
769 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
770 NAND_NCE | NAND_CTRL_CHANGE);
771 return;
772
1da177e4 773 case NAND_CMD_READ0:
12efdde3
TG		 774 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
775 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
776 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
777 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 778
e0c7d767 779 /* This applies to read commands */
1da177e4 780 default:
61b03bd7 781 /*
1da177e4 782 * If we don't have access to the busy pin, we apply the given
8b6e50c9 783 * command delay.
e0c7d767 784 */
ace4dfee
TG		 785 if (!chip->dev_ready) {
786 udelay(chip->chip_delay);
1da177e4 787 return;
61b03bd7 788 }
1da177e4 789 }
3b88775c 790
8b6e50c9
BN		 791 /*
792 * Apply this short delay always to ensure that we do wait tWB in
793 * any case on any machine.
794 */
e0c7d767 795 ndelay(100);
3b88775c
TG		 796
797 nand_wait_ready(mtd);
1da177e4
LT		 798}
799
2af7c653
SK		 800/**
801 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 802 * @chip: the nand chip descriptor
803 * @mtd: MTD device structure
804 * @new_state: the state which is requested
2af7c653
SK		 805 *
806 * Used when in panic, no locks are taken.
807 */
808static void panic_nand_get_device(struct nand_chip *chip,
809 struct mtd_info *mtd, int new_state)
810{
7854d3f7 811 /* Hardware controller shared among independent devices */
2af7c653
SK		 812 chip->controller->active = chip;
813 chip->state = new_state;
814}
815
1da177e4
LT		 816/**
817 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 818 * @mtd: MTD device structure
819 * @new_state: the state which is requested
1da177e4
LT		 820 *
821 * Get the device and lock it for exclusive access
822 */
2c0a2bed 823static int
6a8214aa 824nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 825{
6a8214aa 826 struct nand_chip *chip = mtd->priv;
ace4dfee
TG		 827 spinlock_t *lock = &chip->controller->lock;
828 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 829 DECLARE_WAITQUEUE(wait, current);
7351d3a5 830retry:
0dfc6246
TG		 831 spin_lock(lock);
832
b8b3ee9a 833 /* Hardware controller shared among independent devices */
ace4dfee
TG		 834 if (!chip->controller->active)
835 chip->controller->active = chip;
a36ed299 836
ace4dfee
TG		 837 if (chip->controller->active == chip && chip->state == FL_READY) {
838 chip->state = new_state;
0dfc6246 839 spin_unlock(lock);
962034f4
VW		 840 return 0;
841 }
842 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 843 if (chip->controller->active->state == FL_PM_SUSPENDED) {
844 chip->state = FL_PM_SUSPENDED;
845 spin_unlock(lock);
846 return 0;
6b0d9a84 847 }
0dfc6246
TG		 848 }
849 set_current_state(TASK_UNINTERRUPTIBLE);
850 add_wait_queue(wq, &wait);
851 spin_unlock(lock);
852 schedule();
853 remove_wait_queue(wq, &wait);
1da177e4
LT		 854 goto retry;
855}
856
2af7c653 857/**
8b6e50c9
BN		 858 * panic_nand_wait - [GENERIC] wait until the command is done
859 * @mtd: MTD device structure
860 * @chip: NAND chip structure
861 * @timeo: timeout
2af7c653
SK		 862 *
863 * Wait for command done. This is a helper function for nand_wait used when
864 * we are in interrupt context. May happen when in panic and trying to write
b595076a 865 * an oops through mtdoops.
2af7c653
SK		 866 */
867static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
868 unsigned long timeo)
869{
870 int i;
871 for (i = 0; i < timeo; i++) {
872 if (chip->dev_ready) {
873 if (chip->dev_ready(mtd))
874 break;
875 } else {
876 if (chip->read_byte(mtd) & NAND_STATUS_READY)
877 break;
878 }
879 mdelay(1);
f8ac0414 880 }
2af7c653
SK		 881}
882
1da177e4 883/**
8b6e50c9
BN		 884 * nand_wait - [DEFAULT] wait until the command is done
885 * @mtd: MTD device structure
886 * @chip: NAND chip structure
1da177e4 887 *
8b6e50c9
BN		 888 * Wait for command done. This applies to erase and program only. Erase can
889 * take up to 400ms and program up to 20ms according to general NAND and
890 * SmartMedia specs.
844d3b42 891 */
7bc3312b 892static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 893{
894
7bc3312b 895 int status, state = chip->state;
6d2559f8 896 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1da177e4 897
8fe833c1
RP		 898 led_trigger_event(nand_led_trigger, LED_FULL);
899
8b6e50c9
BN		 900 /*
901 * Apply this short delay always to ensure that we do wait tWB in any
902 * case on any machine.
903 */
e0c7d767 904 ndelay(100);
1da177e4 905
14c65786 906 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 907
2af7c653
SK		 908 if (in_interrupt() || oops_in_progress)
909 panic_nand_wait(mtd, chip, timeo);
910 else {
6d2559f8 911 timeo = jiffies + msecs_to_jiffies(timeo);
2af7c653
SK		 912 while (time_before(jiffies, timeo)) {
913 if (chip->dev_ready) {
914 if (chip->dev_ready(mtd))
915 break;
916 } else {
917 if (chip->read_byte(mtd) & NAND_STATUS_READY)
918 break;
919 }
920 cond_resched();
1da177e4 921 }
1da177e4 922 }
8fe833c1
RP		 923 led_trigger_event(nand_led_trigger, LED_OFF);
924
ace4dfee 925 status = (int)chip->read_byte(mtd);
f251b8df
MC		 926 /* This can happen if in case of timeout or buggy dev_ready */
927 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 928 return status;
929}
930
7d70f334 931/**
b6d676db 932 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 933 * @mtd: mtd info
934 * @ofs: offset to start unlock from
935 * @len: length to unlock
8b6e50c9
BN		 936 * @invert: when = 0, unlock the range of blocks within the lower and
937 * upper boundary address
938 * when = 1, unlock the range of blocks outside the boundaries
939 * of the lower and upper boundary address
7d70f334 940 *
8b6e50c9 941 * Returs unlock status.
7d70f334
VS		 942 */
943static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
944 uint64_t len, int invert)
945{
946 int ret = 0;
947 int status, page;
948 struct nand_chip *chip = mtd->priv;
949
950 /* Submit address of first page to unlock */
951 page = ofs >> chip->page_shift;
952 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
953
954 /* Submit address of last page to unlock */
955 page = (ofs + len) >> chip->page_shift;
956 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
957 (page | invert) & chip->pagemask);
958
959 /* Call wait ready function */
960 status = chip->waitfunc(mtd, chip);
7d70f334 961 /* See if device thinks it succeeded */
74830966 962 if (status & NAND_STATUS_FAIL) {
289c0522 963 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 964 __func__, status);
965 ret = -EIO;
966 }
967
968 return ret;
969}
970
971/**
b6d676db 972 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 973 * @mtd: mtd info
974 * @ofs: offset to start unlock from
975 * @len: length to unlock
7d70f334 976 *
8b6e50c9 977 * Returns unlock status.
7d70f334
VS		 978 */
979int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
980{
981 int ret = 0;
982 int chipnr;
983 struct nand_chip *chip = mtd->priv;
984
289c0522 985 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 986 __func__, (unsigned long long)ofs, len);
987
988 if (check_offs_len(mtd, ofs, len))
b1a2348a 989 return -EINVAL;
7d70f334
VS		 990
991 /* Align to last block address if size addresses end of the device */
992 if (ofs + len == mtd->size)
993 len -= mtd->erasesize;
994
6a8214aa 995 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 996
997 /* Shift to get chip number */
998 chipnr = ofs >> chip->chip_shift;
999
1000 chip->select_chip(mtd, chipnr);
1001
57d3a9a8
WD		 1002 /*
1003 * Reset the chip.
1004 * If we want to check the WP through READ STATUS and check the bit 7
1005 * we must reset the chip
1006 * some operation can also clear the bit 7 of status register
1007 * eg. erase/program a locked block
1008 */
1009 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1010
7d70f334
VS		 1011 /* Check, if it is write protected */
1012 if (nand_check_wp(mtd)) {
289c0522 1013 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1014 __func__);
1015 ret = -EIO;
1016 goto out;
1017 }
1018
1019 ret = __nand_unlock(mtd, ofs, len, 0);
1020
1021out:
b0bb6903 1022 chip->select_chip(mtd, -1);
7d70f334
VS		 1023 nand_release_device(mtd);
1024
1025 return ret;
1026}
7351d3a5 1027EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 1028
1029/**
b6d676db 1030 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 1031 * @mtd: mtd info
1032 * @ofs: offset to start unlock from
1033 * @len: length to unlock
7d70f334 1034 *
8b6e50c9
BN		 1035 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1036 * have this feature, but it allows only to lock all blocks, not for specified
1037 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1038 * now.
7d70f334 1039 *
8b6e50c9 1040 * Returns lock status.
7d70f334
VS		 1041 */
1042int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1043{
1044 int ret = 0;
1045 int chipnr, status, page;
1046 struct nand_chip *chip = mtd->priv;
1047
289c0522 1048 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1049 __func__, (unsigned long long)ofs, len);
1050
1051 if (check_offs_len(mtd, ofs, len))
b1a2348a 1052 return -EINVAL;
7d70f334 1053
6a8214aa 1054 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 1055
1056 /* Shift to get chip number */
1057 chipnr = ofs >> chip->chip_shift;
1058
1059 chip->select_chip(mtd, chipnr);
1060
57d3a9a8
WD		 1061 /*
1062 * Reset the chip.
1063 * If we want to check the WP through READ STATUS and check the bit 7
1064 * we must reset the chip
1065 * some operation can also clear the bit 7 of status register
1066 * eg. erase/program a locked block
1067 */
1068 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1069
7d70f334
VS		 1070 /* Check, if it is write protected */
1071 if (nand_check_wp(mtd)) {
289c0522 1072 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1073 __func__);
1074 status = MTD_ERASE_FAILED;
1075 ret = -EIO;
1076 goto out;
1077 }
1078
1079 /* Submit address of first page to lock */
1080 page = ofs >> chip->page_shift;
1081 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1082
1083 /* Call wait ready function */
1084 status = chip->waitfunc(mtd, chip);
7d70f334 1085 /* See if device thinks it succeeded */
74830966 1086 if (status & NAND_STATUS_FAIL) {
289c0522 1087 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1088 __func__, status);
1089 ret = -EIO;
1090 goto out;
1091 }
1092
1093 ret = __nand_unlock(mtd, ofs, len, 0x1);
1094
1095out:
b0bb6903 1096 chip->select_chip(mtd, -1);
7d70f334
VS		 1097 nand_release_device(mtd);
1098
1099 return ret;
1100}
7351d3a5 1101EXPORT_SYMBOL(nand_lock);
7d70f334 1102
8593fbc6 1103/**
7854d3f7 1104 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1105 * @mtd: mtd info structure
1106 * @chip: nand chip info structure
1107 * @buf: buffer to store read data
1fbb938d 1108 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1109 * @page: page number to read
52ff49df 1110 *
7854d3f7 1111 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1112 */
1113static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1114 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1115{
1116 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1117 if (oob_required)
1118 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1119 return 0;
1120}
1121
52ff49df 1122/**
7854d3f7 1123 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1124 * @mtd: mtd info structure
1125 * @chip: nand chip info structure
1126 * @buf: buffer to store read data
1fbb938d 1127 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1128 * @page: page number to read
52ff49df
DB		 1129 *
1130 * We need a special oob layout and handling even when OOB isn't used.
1131 */
7351d3a5 1132static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1133 struct nand_chip *chip, uint8_t *buf,
1134 int oob_required, int page)
52ff49df
DB		 1135{
1136 int eccsize = chip->ecc.size;
1137 int eccbytes = chip->ecc.bytes;
1138 uint8_t *oob = chip->oob_poi;
1139 int steps, size;
1140
1141 for (steps = chip->ecc.steps; steps > 0; steps--) {
1142 chip->read_buf(mtd, buf, eccsize);
1143 buf += eccsize;
1144
1145 if (chip->ecc.prepad) {
1146 chip->read_buf(mtd, oob, chip->ecc.prepad);
1147 oob += chip->ecc.prepad;
1148 }
1149
1150 chip->read_buf(mtd, oob, eccbytes);
1151 oob += eccbytes;
1152
1153 if (chip->ecc.postpad) {
1154 chip->read_buf(mtd, oob, chip->ecc.postpad);
1155 oob += chip->ecc.postpad;
1156 }
1157 }
1158
1159 size = mtd->oobsize - (oob - chip->oob_poi);
1160 if (size)
1161 chip->read_buf(mtd, oob, size);
1162
1163 return 0;
1164}
1165
1da177e4 1166/**
7854d3f7 1167 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1168 * @mtd: mtd info structure
1169 * @chip: nand chip info structure
1170 * @buf: buffer to store read data
1fbb938d 1171 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1172 * @page: page number to read
068e3c0a 1173 */
f5bbdacc 1174static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1175 uint8_t *buf, int oob_required, int page)
1da177e4 1176{
f5bbdacc
TG		 1177 int i, eccsize = chip->ecc.size;
1178 int eccbytes = chip->ecc.bytes;
1179 int eccsteps = chip->ecc.steps;
1180 uint8_t *p = buf;
4bf63fcb
DW		 1181 uint8_t *ecc_calc = chip->buffers->ecccalc;
1182 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1183 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1184 unsigned int max_bitflips = 0;
f5bbdacc 1185
1fbb938d 1186 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1187
1188 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1189 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1190
1191 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1192 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1193
1194 eccsteps = chip->ecc.steps;
1195 p = buf;
1196
1197 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1198 int stat;
1199
1200 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1201 if (stat < 0) {
f5bbdacc 1202 mtd->ecc_stats.failed++;
3f91e94f 1203 } else {
f5bbdacc 1204 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1205 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1206 }
f5bbdacc 1207 }
3f91e94f 1208 return max_bitflips;
22c60f5f 1209}
1da177e4 1210
3d459559 1211/**
837a6ba4 1212 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1213 * @mtd: mtd info structure
1214 * @chip: nand chip info structure
1215 * @data_offs: offset of requested data within the page
1216 * @readlen: data length
1217 * @bufpoi: buffer to store read data
e004debd 1218 * @page: page number to read
3d459559 1219 */
7351d3a5 1220static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
e004debd
HS		 1221 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1222 int page)
3d459559
AK		 1223{
1224 int start_step, end_step, num_steps;
1225 uint32_t *eccpos = chip->ecc.layout->eccpos;
1226 uint8_t *p;
1227 int data_col_addr, i, gaps = 0;
1228 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1229 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
4a4163ca 1230 int index;
3f91e94f 1231 unsigned int max_bitflips = 0;
3d459559 1232
7854d3f7 1233 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1234 start_step = data_offs / chip->ecc.size;
1235 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1236 num_steps = end_step - start_step + 1;
4a4163ca 1237 index = start_step * chip->ecc.bytes;
3d459559 1238
8b6e50c9 1239 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1240 datafrag_len = num_steps * chip->ecc.size;
1241 eccfrag_len = num_steps * chip->ecc.bytes;
1242
1243 data_col_addr = start_step * chip->ecc.size;
1244 /* If we read not a page aligned data */
1245 if (data_col_addr != 0)
1246 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1247
1248 p = bufpoi + data_col_addr;
1249 chip->read_buf(mtd, p, datafrag_len);
1250
8b6e50c9 1251 /* Calculate ECC */
3d459559
AK		 1252 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1253 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1254
8b6e50c9
BN		 1255 /*
1256 * The performance is faster if we position offsets according to
7854d3f7 1257 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1258 */
3d459559 1259 for (i = 0; i < eccfrag_len - 1; i++) {
47570bb1 1260 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
3d459559
AK		 1261 gaps = 1;
1262 break;
1263 }
1264 }
1265 if (gaps) {
1266 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1267 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1268 } else {
8b6e50c9 1269 /*
7854d3f7 1270 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1271 * about buswidth alignment in read_buf.
1272 */
7351d3a5 1273 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1274 aligned_len = eccfrag_len;
7351d3a5 1275 if (eccpos[index] & (busw - 1))
3d459559 1276 aligned_len++;
7351d3a5 1277 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1278 aligned_len++;
1279
7351d3a5
FF		 1280 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1281 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1282 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1283 }
1284
1285 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1286 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1287
1288 p = bufpoi + data_col_addr;
1289 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1290 int stat;
1291
7351d3a5
FF		 1292 stat = chip->ecc.correct(mtd, p,
1293 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1294 if (stat < 0) {
3d459559 1295 mtd->ecc_stats.failed++;
3f91e94f 1296 } else {
3d459559 1297 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1298 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1299 }
3d459559 1300 }
3f91e94f 1301 return max_bitflips;
3d459559
AK		 1302}
1303
068e3c0a 1304/**
7854d3f7 1305 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1306 * @mtd: mtd info structure
1307 * @chip: nand chip info structure
1308 * @buf: buffer to store read data
1fbb938d 1309 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1310 * @page: page number to read
068e3c0a 1311 *
7854d3f7 1312 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1313 */
f5bbdacc 1314static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1315 uint8_t *buf, int oob_required, int page)
1da177e4 1316{
f5bbdacc
TG		 1317 int i, eccsize = chip->ecc.size;
1318 int eccbytes = chip->ecc.bytes;
1319 int eccsteps = chip->ecc.steps;
1320 uint8_t *p = buf;
4bf63fcb
DW		 1321 uint8_t *ecc_calc = chip->buffers->ecccalc;
1322 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1323 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1324 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1325
1326 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1327 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1328 chip->read_buf(mtd, p, eccsize);
1329 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1330 }
f75e5097 1331 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1332
f5bbdacc 1333 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1334 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1335
f5bbdacc
TG		 1336 eccsteps = chip->ecc.steps;
1337 p = buf;
61b03bd7 1338
f5bbdacc
TG		 1339 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1340 int stat;
1da177e4 1341
f5bbdacc 1342 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1343 if (stat < 0) {
f5bbdacc 1344 mtd->ecc_stats.failed++;
3f91e94f 1345 } else {
f5bbdacc 1346 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1347 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1348 }
f5bbdacc 1349 }
3f91e94f 1350 return max_bitflips;
f5bbdacc 1351}
1da177e4 1352
6e0cb135 1353/**
7854d3f7 1354 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1355 * @mtd: mtd info structure
1356 * @chip: nand chip info structure
1357 * @buf: buffer to store read data
1fbb938d 1358 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1359 * @page: page number to read
6e0cb135 1360 *
8b6e50c9
BN		 1361 * Hardware ECC for large page chips, require OOB to be read first. For this
1362 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1363 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1364 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1365 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1366 */
1367static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1368 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1369{
1370 int i, eccsize = chip->ecc.size;
1371 int eccbytes = chip->ecc.bytes;
1372 int eccsteps = chip->ecc.steps;
1373 uint8_t *p = buf;
1374 uint8_t *ecc_code = chip->buffers->ecccode;
1375 uint32_t *eccpos = chip->ecc.layout->eccpos;
1376 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1377 unsigned int max_bitflips = 0;
6e0cb135
SN		 1378
1379 /* Read the OOB area first */
1380 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1381 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1382 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1383
1384 for (i = 0; i < chip->ecc.total; i++)
1385 ecc_code[i] = chip->oob_poi[eccpos[i]];
1386
1387 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1388 int stat;
1389
1390 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1391 chip->read_buf(mtd, p, eccsize);
1392 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1393
1394 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1395 if (stat < 0) {
6e0cb135 1396 mtd->ecc_stats.failed++;
3f91e94f 1397 } else {
6e0cb135 1398 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1399 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1400 }
6e0cb135 1401 }
3f91e94f 1402 return max_bitflips;
6e0cb135
SN		 1403}
1404
f5bbdacc 1405/**
7854d3f7 1406 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1407 * @mtd: mtd info structure
1408 * @chip: nand chip info structure
1409 * @buf: buffer to store read data
1fbb938d 1410 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1411 * @page: page number to read
f5bbdacc 1412 *
8b6e50c9
BN		 1413 * The hw generator calculates the error syndrome automatically. Therefore we
1414 * need a special oob layout and handling.
f5bbdacc
TG		 1415 */
1416static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1417 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1418{
1419 int i, eccsize = chip->ecc.size;
1420 int eccbytes = chip->ecc.bytes;
1421 int eccsteps = chip->ecc.steps;
1422 uint8_t *p = buf;
f75e5097 1423 uint8_t *oob = chip->oob_poi;
3f91e94f 1424 unsigned int max_bitflips = 0;
1da177e4 1425
f5bbdacc
TG		 1426 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1427 int stat;
61b03bd7 1428
f5bbdacc
TG		 1429 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1430 chip->read_buf(mtd, p, eccsize);
1da177e4 1431
f5bbdacc
TG		 1432 if (chip->ecc.prepad) {
1433 chip->read_buf(mtd, oob, chip->ecc.prepad);
1434 oob += chip->ecc.prepad;
1435 }
1da177e4 1436
f5bbdacc
TG		 1437 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1438 chip->read_buf(mtd, oob, eccbytes);
1439 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1440
3f91e94f 1441 if (stat < 0) {
f5bbdacc 1442 mtd->ecc_stats.failed++;
3f91e94f 1443 } else {
f5bbdacc 1444 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1445 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1446 }
61b03bd7 1447
f5bbdacc 1448 oob += eccbytes;
1da177e4 1449
f5bbdacc
TG		 1450 if (chip->ecc.postpad) {
1451 chip->read_buf(mtd, oob, chip->ecc.postpad);
1452 oob += chip->ecc.postpad;
61b03bd7 1453 }
f5bbdacc 1454 }
1da177e4 1455
f5bbdacc 1456 /* Calculate remaining oob bytes */
7e4178f9 1457 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1458 if (i)
1459 chip->read_buf(mtd, oob, i);
61b03bd7 1460
3f91e94f 1461 return max_bitflips;
f5bbdacc 1462}
1da177e4 1463
f5bbdacc 1464/**
7854d3f7 1465 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1466 * @chip: nand chip structure
1467 * @oob: oob destination address
1468 * @ops: oob ops structure
1469 * @len: size of oob to transfer
8593fbc6
TG		 1470 */
1471static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1472 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1473{
f8ac0414 1474 switch (ops->mode) {
8593fbc6 1475
0612b9dd
BN		 1476 case MTD_OPS_PLACE_OOB:
1477 case MTD_OPS_RAW:
8593fbc6
TG		 1478 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1479 return oob + len;
1480
0612b9dd 1481 case MTD_OPS_AUTO_OOB: {
8593fbc6 1482 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1483 uint32_t boffs = 0, roffs = ops->ooboffs;
1484 size_t bytes = 0;
8593fbc6 1485
f8ac0414 1486 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1487 /* Read request not from offset 0? */
7bc3312b
TG		 1488 if (unlikely(roffs)) {
1489 if (roffs >= free->length) {
1490 roffs -= free->length;
1491 continue;
1492 }
1493 boffs = free->offset + roffs;
1494 bytes = min_t(size_t, len,
1495 (free->length - roffs));
1496 roffs = 0;
1497 } else {
1498 bytes = min_t(size_t, len, free->length);
1499 boffs = free->offset;
1500 }
1501 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1502 oob += bytes;
1503 }
1504 return oob;
1505 }
1506 default:
1507 BUG();
1508 }
1509 return NULL;
1510}
1511
ba84fb59
BN		 1512/**
1513 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1514 * @mtd: MTD device structure
1515 * @retry_mode: the retry mode to use
1516 *
1517 * Some vendors supply a special command to shift the Vt threshold, to be used
1518 * when there are too many bitflips in a page (i.e., ECC error). After setting
1519 * a new threshold, the host should retry reading the page.
1520 */
1521static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1522{
1523 struct nand_chip *chip = mtd->priv;
1524
1525 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1526
1527 if (retry_mode >= chip->read_retries)
1528 return -EINVAL;
1529
1530 if (!chip->setup_read_retry)
1531 return -EOPNOTSUPP;
1532
1533 return chip->setup_read_retry(mtd, retry_mode);
1534}
1535
8593fbc6 1536/**
7854d3f7 1537 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1538 * @mtd: MTD device structure
1539 * @from: offset to read from
1540 * @ops: oob ops structure
f5bbdacc
TG		 1541 *
1542 * Internal function. Called with chip held.
1543 */
8593fbc6
TG		 1544static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1545 struct mtd_oob_ops *ops)
f5bbdacc 1546{
e47f3db4 1547 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc 1548 struct nand_chip *chip = mtd->priv;
f5bbdacc 1549 int ret = 0;
8593fbc6 1550 uint32_t readlen = ops->len;
7014568b 1551 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1552 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1553 mtd->oobavail : mtd->oobsize;
1554
8593fbc6 1555 uint8_t *bufpoi, *oob, *buf;
66507c7b 1556 int use_bufpoi;
edbc4540 1557 unsigned int max_bitflips = 0;
ba84fb59 1558 int retry_mode = 0;
b72f3dfb 1559 bool ecc_fail = false;
1da177e4 1560
f5bbdacc
TG		 1561 chipnr = (int)(from >> chip->chip_shift);
1562 chip->select_chip(mtd, chipnr);
61b03bd7 1563
f5bbdacc
TG		 1564 realpage = (int)(from >> chip->page_shift);
1565 page = realpage & chip->pagemask;
1da177e4 1566
f5bbdacc 1567 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1568
8593fbc6
TG		 1569 buf = ops->datbuf;
1570 oob = ops->oobbuf;
e47f3db4 1571 oob_required = oob ? 1 : 0;
8593fbc6 1572
f8ac0414 1573 while (1) {
b72f3dfb
BN		 1574 unsigned int ecc_failures = mtd->ecc_stats.failed;
1575
f5bbdacc
TG		 1576 bytes = min(mtd->writesize - col, readlen);
1577 aligned = (bytes == mtd->writesize);
61b03bd7 1578
66507c7b
KD		 1579 if (!aligned)
1580 use_bufpoi = 1;
1581 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1582 use_bufpoi = !virt_addr_valid(buf);
1583 else
1584 use_bufpoi = 0;
1585
8b6e50c9 1586 /* Is the current page in the buffer? */
8593fbc6 1587 if (realpage != chip->pagebuf || oob) {
66507c7b
KD		 1588 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1589
1590 if (use_bufpoi && aligned)
1591 pr_debug("%s: using read bounce buffer for buf@%p\n",
1592 __func__, buf);
61b03bd7 1593
ba84fb59 1594read_retry:
c00a0991 1595 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1596
edbc4540
MD		 1597 /*
1598 * Now read the page into the buffer. Absent an error,
1599 * the read methods return max bitflips per ecc step.
1600 */
0612b9dd 1601 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1602 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1603 oob_required,
1604 page);
a5ff4f10
JW		 1605 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1606 !oob)
7351d3a5 1607 ret = chip->ecc.read_subpage(mtd, chip,
e004debd
HS		 1608 col, bytes, bufpoi,
1609 page);
956e944c 1610 else
46a8cf2d 1611 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1612 oob_required, page);
6d77b9d0 1613 if (ret < 0) {
66507c7b 1614 if (use_bufpoi)
6d77b9d0
BN		 1615 /* Invalidate page cache */
1616 chip->pagebuf = -1;
1da177e4 1617 break;
6d77b9d0 1618 }
f5bbdacc 1619
edbc4540
MD		 1620 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1621
f5bbdacc 1622 /* Transfer not aligned data */
66507c7b 1623 if (use_bufpoi) {
a5ff4f10 1624 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
b72f3dfb 1625 !(mtd->ecc_stats.failed - ecc_failures) &&
edbc4540 1626 (ops->mode != MTD_OPS_RAW)) {
3d459559 1627 chip->pagebuf = realpage;
edbc4540
MD		 1628 chip->pagebuf_bitflips = ret;
1629 } else {
6d77b9d0
BN		 1630 /* Invalidate page cache */
1631 chip->pagebuf = -1;
edbc4540 1632 }
4bf63fcb 1633 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1634 }
1635
8593fbc6 1636 if (unlikely(oob)) {
b64d39d8
ML		 1637 int toread = min(oobreadlen, max_oobsize);
1638
1639 if (toread) {
1640 oob = nand_transfer_oob(chip,
1641 oob, ops, toread);
1642 oobreadlen -= toread;
1643 }
8593fbc6 1644 }
5bc7c33c
BN		 1645
1646 if (chip->options & NAND_NEED_READRDY) {
1647 /* Apply delay or wait for ready/busy pin */
1648 if (!chip->dev_ready)
1649 udelay(chip->chip_delay);
1650 else
1651 nand_wait_ready(mtd);
1652 }
b72f3dfb 1653
ba84fb59 1654 if (mtd->ecc_stats.failed - ecc_failures) {
28fa65e6 1655 if (retry_mode + 1 < chip->read_retries) {
ba84fb59
BN		 1656 retry_mode++;
1657 ret = nand_setup_read_retry(mtd,
1658 retry_mode);
1659 if (ret < 0)
1660 break;
1661
1662 /* Reset failures; retry */
1663 mtd->ecc_stats.failed = ecc_failures;
1664 goto read_retry;
1665 } else {
1666 /* No more retry modes; real failure */
1667 ecc_fail = true;
1668 }
1669 }
1670
1671 buf += bytes;
8593fbc6 1672 } else {
4bf63fcb 1673 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1674 buf += bytes;
edbc4540
MD		 1675 max_bitflips = max_t(unsigned int, max_bitflips,
1676 chip->pagebuf_bitflips);
8593fbc6 1677 }
1da177e4 1678
f5bbdacc 1679 readlen -= bytes;
61b03bd7 1680
ba84fb59
BN		 1681 /* Reset to retry mode 0 */
1682 if (retry_mode) {
1683 ret = nand_setup_read_retry(mtd, 0);
1684 if (ret < 0)
1685 break;
1686 retry_mode = 0;
1687 }
1688
f5bbdacc 1689 if (!readlen)
61b03bd7 1690 break;
1da177e4 1691
8b6e50c9 1692 /* For subsequent reads align to page boundary */
1da177e4
LT		 1693 col = 0;
1694 /* Increment page address */
1695 realpage++;
1696
ace4dfee 1697 page = realpage & chip->pagemask;
1da177e4
LT		 1698 /* Check, if we cross a chip boundary */
1699 if (!page) {
1700 chipnr++;
ace4dfee
TG		 1701 chip->select_chip(mtd, -1);
1702 chip->select_chip(mtd, chipnr);
1da177e4 1703 }
1da177e4 1704 }
b0bb6903 1705 chip->select_chip(mtd, -1);
1da177e4 1706
8593fbc6 1707 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1708 if (oob)
1709 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1710
3f91e94f 1711 if (ret < 0)
f5bbdacc
TG		 1712 return ret;
1713
b72f3dfb 1714 if (ecc_fail)
9a1fcdfd
TG		 1715 return -EBADMSG;
1716
edbc4540 1717 return max_bitflips;
f5bbdacc
TG		 1718}
1719
1720/**
25985edc 1721 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1722 * @mtd: MTD device structure
1723 * @from: offset to read from
1724 * @len: number of bytes to read
1725 * @retlen: pointer to variable to store the number of read bytes
1726 * @buf: the databuffer to put data
f5bbdacc 1727 *
8b6e50c9 1728 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1729 */
1730static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1731 size_t *retlen, uint8_t *buf)
1732{
4a89ff88 1733 struct mtd_oob_ops ops;
f5bbdacc
TG		 1734 int ret;
1735
6a8214aa 1736 nand_get_device(mtd, FL_READING);
0ec56dc4 1737 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 1738 ops.len = len;
1739 ops.datbuf = buf;
11041ae6 1740 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1741 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1742 *retlen = ops.retlen;
f5bbdacc 1743 nand_release_device(mtd);
f5bbdacc 1744 return ret;
1da177e4
LT		 1745}
1746
7bc3312b 1747/**
7854d3f7 1748 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1749 * @mtd: mtd info structure
1750 * @chip: nand chip info structure
1751 * @page: page number to read
7bc3312b
TG		 1752 */
1753static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1754 int page)
7bc3312b 1755{
5c2ffb11 1756 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1757 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1758 return 0;
7bc3312b
TG		 1759}
1760
1761/**
7854d3f7 1762 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1763 * with syndromes
8b6e50c9
BN		 1764 * @mtd: mtd info structure
1765 * @chip: nand chip info structure
1766 * @page: page number to read
7bc3312b
TG		 1767 */
1768static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1769 int page)
7bc3312b 1770{
7bc3312b
TG		 1771 int length = mtd->oobsize;
1772 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1773 int eccsize = chip->ecc.size;
2ea69d21 1774 uint8_t *bufpoi = chip->oob_poi;
7bc3312b
TG		 1775 int i, toread, sndrnd = 0, pos;
1776
1777 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1778 for (i = 0; i < chip->ecc.steps; i++) {
1779 if (sndrnd) {
1780 pos = eccsize + i * (eccsize + chunk);
1781 if (mtd->writesize > 512)
1782 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1783 else
1784 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1785 } else
1786 sndrnd = 1;
1787 toread = min_t(int, length, chunk);
1788 chip->read_buf(mtd, bufpoi, toread);
1789 bufpoi += toread;
1790 length -= toread;
1791 }
1792 if (length > 0)
1793 chip->read_buf(mtd, bufpoi, length);
1794
5c2ffb11 1795 return 0;
7bc3312b
TG		 1796}
1797
1798/**
7854d3f7 1799 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1800 * @mtd: mtd info structure
1801 * @chip: nand chip info structure
1802 * @page: page number to write
7bc3312b
TG		 1803 */
1804static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1805 int page)
1806{
1807 int status = 0;
1808 const uint8_t *buf = chip->oob_poi;
1809 int length = mtd->oobsize;
1810
1811 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1812 chip->write_buf(mtd, buf, length);
1813 /* Send command to program the OOB data */
1814 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1815
1816 status = chip->waitfunc(mtd, chip);
1817
0d420f9d 1818 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1819}
1820
1821/**
7854d3f7 1822 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1823 * with syndrome - only for large page flash
1824 * @mtd: mtd info structure
1825 * @chip: nand chip info structure
1826 * @page: page number to write
7bc3312b
TG		 1827 */
1828static int nand_write_oob_syndrome(struct mtd_info *mtd,
1829 struct nand_chip *chip, int page)
1830{
1831 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1832 int eccsize = chip->ecc.size, length = mtd->oobsize;
1833 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1834 const uint8_t *bufpoi = chip->oob_poi;
1835
1836 /*
1837 * data-ecc-data-ecc ... ecc-oob
1838 * or
1839 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1840 */
1841 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1842 pos = steps * (eccsize + chunk);
1843 steps = 0;
1844 } else
8b0036ee 1845 pos = eccsize;
7bc3312b
TG		 1846
1847 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1848 for (i = 0; i < steps; i++) {
1849 if (sndcmd) {
1850 if (mtd->writesize <= 512) {
1851 uint32_t fill = 0xFFFFFFFF;
1852
1853 len = eccsize;
1854 while (len > 0) {
1855 int num = min_t(int, len, 4);
1856 chip->write_buf(mtd, (uint8_t *)&fill,
1857 num);
1858 len -= num;
1859 }
1860 } else {
1861 pos = eccsize + i * (eccsize + chunk);
1862 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1863 }
1864 } else
1865 sndcmd = 1;
1866 len = min_t(int, length, chunk);
1867 chip->write_buf(mtd, bufpoi, len);
1868 bufpoi += len;
1869 length -= len;
1870 }
1871 if (length > 0)
1872 chip->write_buf(mtd, bufpoi, length);
1873
1874 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1875 status = chip->waitfunc(mtd, chip);
1876
1877 return status & NAND_STATUS_FAIL ? -EIO : 0;
1878}
1879
1da177e4 1880/**
7854d3f7 1881 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1882 * @mtd: MTD device structure
1883 * @from: offset to read from
1884 * @ops: oob operations description structure
1da177e4 1885 *
8b6e50c9 1886 * NAND read out-of-band data from the spare area.
1da177e4 1887 */
8593fbc6
TG		 1888static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1889 struct mtd_oob_ops *ops)
1da177e4 1890{
c00a0991 1891 int page, realpage, chipnr;
ace4dfee 1892 struct nand_chip *chip = mtd->priv;
041e4575 1893 struct mtd_ecc_stats stats;
7014568b
VW		 1894 int readlen = ops->ooblen;
1895 int len;
7bc3312b 1896 uint8_t *buf = ops->oobbuf;
1951f2f7 1897 int ret = 0;
61b03bd7 1898
289c0522 1899 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1900 __func__, (unsigned long long)from, readlen);
1da177e4 1901
041e4575
BN		 1902 stats = mtd->ecc_stats;
1903
0612b9dd 1904 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1905 len = chip->ecc.layout->oobavail;
03736155
AH		 1906 else
1907 len = mtd->oobsize;
1908
1909 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1910 pr_debug("%s: attempt to start read outside oob\n",
1911 __func__);
03736155
AH		 1912 return -EINVAL;
1913 }
1914
1915 /* Do not allow reads past end of device */
1916 if (unlikely(from >= mtd->size ||
1917 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1918 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1919 pr_debug("%s: attempt to read beyond end of device\n",
1920 __func__);
03736155
AH		 1921 return -EINVAL;
1922 }
7014568b 1923
7314e9e7 1924 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1925 chip->select_chip(mtd, chipnr);
1da177e4 1926
7314e9e7
TG		 1927 /* Shift to get page */
1928 realpage = (int)(from >> chip->page_shift);
1929 page = realpage & chip->pagemask;
1da177e4 1930
f8ac0414 1931 while (1) {
0612b9dd 1932 if (ops->mode == MTD_OPS_RAW)
1951f2f7 1933 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 1934 else
1951f2f7
SL		 1935 ret = chip->ecc.read_oob(mtd, chip, page);
1936
1937 if (ret < 0)
1938 break;
7014568b
VW		 1939
1940 len = min(len, readlen);
1941 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1942
5bc7c33c
BN		 1943 if (chip->options & NAND_NEED_READRDY) {
1944 /* Apply delay or wait for ready/busy pin */
1945 if (!chip->dev_ready)
1946 udelay(chip->chip_delay);
1947 else
1948 nand_wait_ready(mtd);
1949 }
1950
7014568b 1951 readlen -= len;
0d420f9d
SZ		 1952 if (!readlen)
1953 break;
1954
7314e9e7
TG		 1955 /* Increment page address */
1956 realpage++;
1957
1958 page = realpage & chip->pagemask;
1959 /* Check, if we cross a chip boundary */
1960 if (!page) {
1961 chipnr++;
1962 chip->select_chip(mtd, -1);
1963 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1964 }
1965 }
b0bb6903 1966 chip->select_chip(mtd, -1);
1da177e4 1967
1951f2f7
SL		 1968 ops->oobretlen = ops->ooblen - readlen;
1969
1970 if (ret < 0)
1971 return ret;
041e4575
BN		 1972
1973 if (mtd->ecc_stats.failed - stats.failed)
1974 return -EBADMSG;
1975
1976 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1977}
1978
1979/**
8593fbc6 1980 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1981 * @mtd: MTD device structure
1982 * @from: offset to read from
1983 * @ops: oob operation description structure
1da177e4 1984 *
8b6e50c9 1985 * NAND read data and/or out-of-band data.
1da177e4 1986 */
8593fbc6
TG		 1987static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1988 struct mtd_oob_ops *ops)
1da177e4 1989{
8593fbc6
TG		 1990 int ret = -ENOTSUPP;
1991
1992 ops->retlen = 0;
1da177e4
LT		 1993
1994 /* Do not allow reads past end of device */
7014568b 1995 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1996 pr_debug("%s: attempt to read beyond end of device\n",
1997 __func__);
1da177e4
LT		 1998 return -EINVAL;
1999 }
2000
6a8214aa 2001 nand_get_device(mtd, FL_READING);
1da177e4 2002
f8ac0414 2003 switch (ops->mode) {
0612b9dd
BN		 2004 case MTD_OPS_PLACE_OOB:
2005 case MTD_OPS_AUTO_OOB:
2006 case MTD_OPS_RAW:
8593fbc6 2007 break;
1da177e4 2008
8593fbc6
TG		 2009 default:
2010 goto out;
2011 }
1da177e4 2012
8593fbc6
TG		 2013 if (!ops->datbuf)
2014 ret = nand_do_read_oob(mtd, from, ops);
2015 else
2016 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 2017
7351d3a5 2018out:
8593fbc6
TG		 2019 nand_release_device(mtd);
2020 return ret;
2021}
61b03bd7 2022
1da177e4 2023
8593fbc6 2024/**
7854d3f7 2025 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 2026 * @mtd: mtd info structure
2027 * @chip: nand chip info structure
2028 * @buf: data buffer
1fbb938d 2029 * @oob_required: must write chip->oob_poi to OOB
52ff49df 2030 *
7854d3f7 2031 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 2032 */
fdbad98d 2033static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2034 const uint8_t *buf, int oob_required)
8593fbc6
TG		 2035{
2036 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 2037 if (oob_required)
2038 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2039
2040 return 0;
1da177e4
LT		 2041}
2042
52ff49df 2043/**
7854d3f7 2044 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 2045 * @mtd: mtd info structure
2046 * @chip: nand chip info structure
2047 * @buf: data buffer
1fbb938d 2048 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 2049 *
2050 * We need a special oob layout and handling even when ECC isn't checked.
2051 */
fdbad98d 2052static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 2053 struct nand_chip *chip,
1fbb938d 2054 const uint8_t *buf, int oob_required)
52ff49df
DB		 2055{
2056 int eccsize = chip->ecc.size;
2057 int eccbytes = chip->ecc.bytes;
2058 uint8_t *oob = chip->oob_poi;
2059 int steps, size;
2060
2061 for (steps = chip->ecc.steps; steps > 0; steps--) {
2062 chip->write_buf(mtd, buf, eccsize);
2063 buf += eccsize;
2064
2065 if (chip->ecc.prepad) {
2066 chip->write_buf(mtd, oob, chip->ecc.prepad);
2067 oob += chip->ecc.prepad;
2068 }
2069
60c3bc1f 2070 chip->write_buf(mtd, oob, eccbytes);
52ff49df
DB		 2071 oob += eccbytes;
2072
2073 if (chip->ecc.postpad) {
2074 chip->write_buf(mtd, oob, chip->ecc.postpad);
2075 oob += chip->ecc.postpad;
2076 }
2077 }
2078
2079 size = mtd->oobsize - (oob - chip->oob_poi);
2080 if (size)
2081 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 2082
2083 return 0;
52ff49df 2084}
9223a456 2085/**
7854d3f7 2086 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 2087 * @mtd: mtd info structure
2088 * @chip: nand chip info structure
2089 * @buf: data buffer
1fbb938d 2090 * @oob_required: must write chip->oob_poi to OOB
9223a456 2091 */
fdbad98d 2092static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2093 const uint8_t *buf, int oob_required)
9223a456 2094{
f75e5097
TG		 2095 int i, eccsize = chip->ecc.size;
2096 int eccbytes = chip->ecc.bytes;
2097 int eccsteps = chip->ecc.steps;
4bf63fcb 2098 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2099 const uint8_t *p = buf;
8b099a39 2100 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2101
7854d3f7 2102 /* Software ECC calculation */
8593fbc6
TG		 2103 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2104 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 2105
8593fbc6
TG		 2106 for (i = 0; i < chip->ecc.total; i++)
2107 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 2108
fdbad98d 2109 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 2110}
9223a456 2111
f75e5097 2112/**
7854d3f7 2113 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2114 * @mtd: mtd info structure
2115 * @chip: nand chip info structure
2116 * @buf: data buffer
1fbb938d 2117 * @oob_required: must write chip->oob_poi to OOB
f75e5097 2118 */
fdbad98d 2119static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2120 const uint8_t *buf, int oob_required)
f75e5097
TG		 2121{
2122 int i, eccsize = chip->ecc.size;
2123 int eccbytes = chip->ecc.bytes;
2124 int eccsteps = chip->ecc.steps;
4bf63fcb 2125 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2126 const uint8_t *p = buf;
8b099a39 2127 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2128
f75e5097
TG		 2129 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2130 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2131 chip->write_buf(mtd, p, eccsize);
f75e5097 2132 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2133 }
2134
f75e5097
TG		 2135 for (i = 0; i < chip->ecc.total; i++)
2136 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2137
2138 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2139
2140 return 0;
9223a456
TG		 2141}
2142
837a6ba4
GP		 2143
2144/**
73c8aaf4 2145 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
837a6ba4
GP		 2146 * @mtd: mtd info structure
2147 * @chip: nand chip info structure
d6a95080 2148 * @offset: column address of subpage within the page
837a6ba4 2149 * @data_len: data length
d6a95080 2150 * @buf: data buffer
837a6ba4
GP		 2151 * @oob_required: must write chip->oob_poi to OOB
2152 */
2153static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2154 struct nand_chip *chip, uint32_t offset,
d6a95080 2155 uint32_t data_len, const uint8_t *buf,
837a6ba4
GP		 2156 int oob_required)
2157{
2158 uint8_t *oob_buf = chip->oob_poi;
2159 uint8_t *ecc_calc = chip->buffers->ecccalc;
2160 int ecc_size = chip->ecc.size;
2161 int ecc_bytes = chip->ecc.bytes;
2162 int ecc_steps = chip->ecc.steps;
2163 uint32_t *eccpos = chip->ecc.layout->eccpos;
2164 uint32_t start_step = offset / ecc_size;
2165 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2166 int oob_bytes = mtd->oobsize / ecc_steps;
2167 int step, i;
2168
2169 for (step = 0; step < ecc_steps; step++) {
2170 /* configure controller for WRITE access */
2171 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2172
2173 /* write data (untouched subpages already masked by 0xFF) */
d6a95080 2174 chip->write_buf(mtd, buf, ecc_size);
837a6ba4
GP		 2175
2176 /* mask ECC of un-touched subpages by padding 0xFF */
2177 if ((step < start_step) || (step > end_step))
2178 memset(ecc_calc, 0xff, ecc_bytes);
2179 else
d6a95080 2180 chip->ecc.calculate(mtd, buf, ecc_calc);
837a6ba4
GP		 2181
2182 /* mask OOB of un-touched subpages by padding 0xFF */
2183 /* if oob_required, preserve OOB metadata of written subpage */
2184 if (!oob_required || (step < start_step) || (step > end_step))
2185 memset(oob_buf, 0xff, oob_bytes);
2186
d6a95080 2187 buf += ecc_size;
837a6ba4
GP		 2188 ecc_calc += ecc_bytes;
2189 oob_buf += oob_bytes;
2190 }
2191
2192 /* copy calculated ECC for whole page to chip->buffer->oob */
2193 /* this include masked-value(0xFF) for unwritten subpages */
2194 ecc_calc = chip->buffers->ecccalc;
2195 for (i = 0; i < chip->ecc.total; i++)
2196 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2197
2198 /* write OOB buffer to NAND device */
2199 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2200
2201 return 0;
2202}
2203
2204
61b03bd7 2205/**
7854d3f7 2206 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2207 * @mtd: mtd info structure
2208 * @chip: nand chip info structure
2209 * @buf: data buffer
1fbb938d 2210 * @oob_required: must write chip->oob_poi to OOB
1da177e4 2211 *
8b6e50c9
BN		 2212 * The hw generator calculates the error syndrome automatically. Therefore we
2213 * need a special oob layout and handling.
f75e5097 2214 */
fdbad98d 2215static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 2216 struct nand_chip *chip,
2217 const uint8_t *buf, int oob_required)
1da177e4 2218{
f75e5097
TG		 2219 int i, eccsize = chip->ecc.size;
2220 int eccbytes = chip->ecc.bytes;
2221 int eccsteps = chip->ecc.steps;
2222 const uint8_t *p = buf;
2223 uint8_t *oob = chip->oob_poi;
1da177e4 2224
f75e5097 2225 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2226
f75e5097
TG		 2227 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2228 chip->write_buf(mtd, p, eccsize);
61b03bd7 2229
f75e5097
TG		 2230 if (chip->ecc.prepad) {
2231 chip->write_buf(mtd, oob, chip->ecc.prepad);
2232 oob += chip->ecc.prepad;
2233 }
2234
2235 chip->ecc.calculate(mtd, p, oob);
2236 chip->write_buf(mtd, oob, eccbytes);
2237 oob += eccbytes;
2238
2239 if (chip->ecc.postpad) {
2240 chip->write_buf(mtd, oob, chip->ecc.postpad);
2241 oob += chip->ecc.postpad;
1da177e4 2242 }
1da177e4 2243 }
f75e5097
TG		 2244
2245 /* Calculate remaining oob bytes */
7e4178f9 2246 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2247 if (i)
2248 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2249
2250 return 0;
f75e5097
TG		 2251}
2252
2253/**
956e944c 2254 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2255 * @mtd: MTD device structure
2256 * @chip: NAND chip descriptor
837a6ba4
GP		 2257 * @offset: address offset within the page
2258 * @data_len: length of actual data to be written
8b6e50c9 2259 * @buf: the data to write
1fbb938d 2260 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2261 * @page: page number to write
2262 * @cached: cached programming
2263 * @raw: use _raw version of write_page
f75e5097
TG		 2264 */
2265static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4
GP		 2266 uint32_t offset, int data_len, const uint8_t *buf,
2267 int oob_required, int page, int cached, int raw)
f75e5097 2268{
837a6ba4
GP		 2269 int status, subpage;
2270
2271 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2272 chip->ecc.write_subpage)
2273 subpage = offset || (data_len < mtd->writesize);
2274 else
2275 subpage = 0;
f75e5097
TG		 2276
2277 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2278
956e944c 2279 if (unlikely(raw))
837a6ba4
GP		 2280 status = chip->ecc.write_page_raw(mtd, chip, buf,
2281 oob_required);
2282 else if (subpage)
2283 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2284 buf, oob_required);
956e944c 2285 else
fdbad98d
JW		 2286 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2287
2288 if (status < 0)
2289 return status;
f75e5097
TG		 2290
2291 /*
7854d3f7 2292 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2293 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2294 */
2295 cached = 0;
2296
3239a6cd 2297 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2298
2299 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2300 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2301 /*
2302 * See if operation failed and additional status checks are
8b6e50c9 2303 * available.
f75e5097
TG		 2304 */
2305 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2306 status = chip->errstat(mtd, chip, FL_WRITING, status,
2307 page);
2308
2309 if (status & NAND_STATUS_FAIL)
2310 return -EIO;
2311 } else {
2312 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2313 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2314 }
2315
f75e5097 2316 return 0;
1da177e4
LT		 2317}
2318
8593fbc6 2319/**
7854d3f7 2320 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2321 * @mtd: MTD device structure
8b6e50c9
BN		 2322 * @oob: oob data buffer
2323 * @len: oob data write length
2324 * @ops: oob ops structure
8593fbc6 2325 */
f722013e
TAA		 2326static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2327 struct mtd_oob_ops *ops)
8593fbc6 2328{
f722013e
TAA		 2329 struct nand_chip *chip = mtd->priv;
2330
2331 /*
2332 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2333 * data from a previous OOB read.
2334 */
2335 memset(chip->oob_poi, 0xff, mtd->oobsize);
2336
f8ac0414 2337 switch (ops->mode) {
8593fbc6 2338
0612b9dd
BN		 2339 case MTD_OPS_PLACE_OOB:
2340 case MTD_OPS_RAW:
8593fbc6
TG		 2341 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2342 return oob + len;
2343
0612b9dd 2344 case MTD_OPS_AUTO_OOB: {
8593fbc6 2345 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2346 uint32_t boffs = 0, woffs = ops->ooboffs;
2347 size_t bytes = 0;
8593fbc6 2348
f8ac0414 2349 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2350 /* Write request not from offset 0? */
7bc3312b
TG		 2351 if (unlikely(woffs)) {
2352 if (woffs >= free->length) {
2353 woffs -= free->length;
2354 continue;
2355 }
2356 boffs = free->offset + woffs;
2357 bytes = min_t(size_t, len,
2358 (free->length - woffs));
2359 woffs = 0;
2360 } else {
2361 bytes = min_t(size_t, len, free->length);
2362 boffs = free->offset;
2363 }
8b0036ee 2364 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2365 oob += bytes;
2366 }
2367 return oob;
2368 }
2369 default:
2370 BUG();
2371 }
2372 return NULL;
2373}
2374
f8ac0414 2375#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2376
2377/**
7854d3f7 2378 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2379 * @mtd: MTD device structure
2380 * @to: offset to write to
2381 * @ops: oob operations description structure
1da177e4 2382 *
8b6e50c9 2383 * NAND write with ECC.
1da177e4 2384 */
8593fbc6
TG		 2385static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2386 struct mtd_oob_ops *ops)
1da177e4 2387{
29072b96 2388 int chipnr, realpage, page, blockmask, column;
ace4dfee 2389 struct nand_chip *chip = mtd->priv;
8593fbc6 2390 uint32_t writelen = ops->len;
782ce79a
ML		 2391
2392 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2393 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2394 mtd->oobavail : mtd->oobsize;
2395
8593fbc6
TG		 2396 uint8_t *oob = ops->oobbuf;
2397 uint8_t *buf = ops->datbuf;
837a6ba4 2398 int ret;
e47f3db4 2399 int oob_required = oob ? 1 : 0;
1da177e4 2400
8593fbc6 2401 ops->retlen = 0;
29072b96
TG		 2402 if (!writelen)
2403 return 0;
1da177e4 2404
8b6e50c9 2405 /* Reject writes, which are not page aligned */
8593fbc6 2406 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2407 pr_notice("%s: attempt to write non page aligned data\n",
2408 __func__);
1da177e4
LT		 2409 return -EINVAL;
2410 }
2411
29072b96 2412 column = to & (mtd->writesize - 1);
1da177e4 2413
6a930961
TG		 2414 chipnr = (int)(to >> chip->chip_shift);
2415 chip->select_chip(mtd, chipnr);
2416
1da177e4 2417 /* Check, if it is write protected */
b0bb6903
HS		 2418 if (nand_check_wp(mtd)) {
2419 ret = -EIO;
2420 goto err_out;
2421 }
1da177e4 2422
f75e5097
TG		 2423 realpage = (int)(to >> chip->page_shift);
2424 page = realpage & chip->pagemask;
2425 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2426
2427 /* Invalidate the page cache, when we write to the cached page */
537ab1bd
BN		 2428 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2429 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2430 chip->pagebuf = -1;
61b03bd7 2431
782ce79a 2432 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2433 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2434 ret = -EINVAL;
2435 goto err_out;
2436 }
782ce79a 2437
f8ac0414 2438 while (1) {
29072b96 2439 int bytes = mtd->writesize;
f75e5097 2440 int cached = writelen > bytes && page != blockmask;
29072b96 2441 uint8_t *wbuf = buf;
66507c7b
KD		 2442 int use_bufpoi;
2443 int part_pagewr = (column || writelen < (mtd->writesize - 1));
2444
2445 if (part_pagewr)
2446 use_bufpoi = 1;
2447 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2448 use_bufpoi = !virt_addr_valid(buf);
2449 else
2450 use_bufpoi = 0;
29072b96 2451
66507c7b
KD		 2452 /* Partial page write?, or need to use bounce buffer */
2453 if (use_bufpoi) {
2454 pr_debug("%s: using write bounce buffer for buf@%p\n",
2455 __func__, buf);
29072b96 2456 cached = 0;
66507c7b
KD		 2457 if (part_pagewr)
2458 bytes = min_t(int, bytes - column, writelen);
29072b96
TG		 2459 chip->pagebuf = -1;
2460 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2461 memcpy(&chip->buffers->databuf[column], buf, bytes);
2462 wbuf = chip->buffers->databuf;
2463 }
1da177e4 2464
782ce79a
ML		 2465 if (unlikely(oob)) {
2466 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2467 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2468 oobwritelen -= len;
f722013e
TAA		 2469 } else {
2470 /* We still need to erase leftover OOB data */
2471 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2472 }
837a6ba4
GP		 2473 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2474 oob_required, page, cached,
2475 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2476 if (ret)
2477 break;
2478
2479 writelen -= bytes;
2480 if (!writelen)
2481 break;
2482
29072b96 2483 column = 0;
f75e5097
TG		 2484 buf += bytes;
2485 realpage++;
2486
2487 page = realpage & chip->pagemask;
2488 /* Check, if we cross a chip boundary */
2489 if (!page) {
2490 chipnr++;
2491 chip->select_chip(mtd, -1);
2492 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2493 }
2494 }
8593fbc6 2495
8593fbc6 2496 ops->retlen = ops->len - writelen;
7014568b
VW		 2497 if (unlikely(oob))
2498 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2499
2500err_out:
2501 chip->select_chip(mtd, -1);
1da177e4
LT		 2502 return ret;
2503}
2504
2af7c653
SK		 2505/**
2506 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2507 * @mtd: MTD device structure
2508 * @to: offset to write to
2509 * @len: number of bytes to write
2510 * @retlen: pointer to variable to store the number of written bytes
2511 * @buf: the data to write
2af7c653
SK		 2512 *
2513 * NAND write with ECC. Used when performing writes in interrupt context, this
2514 * may for example be called by mtdoops when writing an oops while in panic.
2515 */
2516static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2517 size_t *retlen, const uint8_t *buf)
2518{
2519 struct nand_chip *chip = mtd->priv;
4a89ff88 2520 struct mtd_oob_ops ops;
2af7c653
SK		 2521 int ret;
2522
8b6e50c9 2523 /* Wait for the device to get ready */
2af7c653
SK		 2524 panic_nand_wait(mtd, chip, 400);
2525
8b6e50c9 2526 /* Grab the device */
2af7c653
SK		 2527 panic_nand_get_device(chip, mtd, FL_WRITING);
2528
0ec56dc4 2529 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2530 ops.len = len;
2531 ops.datbuf = (uint8_t *)buf;
11041ae6 2532 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2533
4a89ff88 2534 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2535
4a89ff88 2536 *retlen = ops.retlen;
2af7c653
SK		 2537 return ret;
2538}
2539
f75e5097 2540/**
8593fbc6 2541 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2542 * @mtd: MTD device structure
2543 * @to: offset to write to
2544 * @len: number of bytes to write
2545 * @retlen: pointer to variable to store the number of written bytes
2546 * @buf: the data to write
f75e5097 2547 *
8b6e50c9 2548 * NAND write with ECC.
f75e5097 2549 */
8593fbc6
TG		 2550static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2551 size_t *retlen, const uint8_t *buf)
f75e5097 2552{
4a89ff88 2553 struct mtd_oob_ops ops;
f75e5097
TG		 2554 int ret;
2555
6a8214aa 2556 nand_get_device(mtd, FL_WRITING);
0ec56dc4 2557 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2558 ops.len = len;
2559 ops.datbuf = (uint8_t *)buf;
11041ae6 2560 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2561 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2562 *retlen = ops.retlen;
f75e5097 2563 nand_release_device(mtd);
8593fbc6 2564 return ret;
f75e5097 2565}
7314e9e7 2566
1da177e4 2567/**
8593fbc6 2568 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2569 * @mtd: MTD device structure
2570 * @to: offset to write to
2571 * @ops: oob operation description structure
1da177e4 2572 *
8b6e50c9 2573 * NAND write out-of-band.
1da177e4 2574 */
8593fbc6
TG		 2575static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2576 struct mtd_oob_ops *ops)
1da177e4 2577{
03736155 2578 int chipnr, page, status, len;
ace4dfee 2579 struct nand_chip *chip = mtd->priv;
1da177e4 2580
289c0522 2581 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2582 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2583
0612b9dd 2584 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2585 len = chip->ecc.layout->oobavail;
2586 else
2587 len = mtd->oobsize;
2588
1da177e4 2589 /* Do not allow write past end of page */
03736155 2590 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2591 pr_debug("%s: attempt to write past end of page\n",
2592 __func__);
1da177e4
LT		 2593 return -EINVAL;
2594 }
2595
03736155 2596 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2597 pr_debug("%s: attempt to start write outside oob\n",
2598 __func__);
03736155
AH		 2599 return -EINVAL;
2600 }
2601
775adc3d 2602 /* Do not allow write past end of device */
03736155
AH		 2603 if (unlikely(to >= mtd->size ||
2604 ops->ooboffs + ops->ooblen >
2605 ((mtd->size >> chip->page_shift) -
2606 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2607 pr_debug("%s: attempt to write beyond end of device\n",
2608 __func__);
03736155
AH		 2609 return -EINVAL;
2610 }
2611
7314e9e7 2612 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2613 chip->select_chip(mtd, chipnr);
1da177e4 2614
7314e9e7
TG		 2615 /* Shift to get page */
2616 page = (int)(to >> chip->page_shift);
2617
2618 /*
2619 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2620 * of my DiskOnChip 2000 test units) will clear the whole data page too
2621 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2622 * it in the doc2000 driver in August 1999. dwmw2.
2623 */
ace4dfee 2624 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2625
2626 /* Check, if it is write protected */
b0bb6903
HS		 2627 if (nand_check_wp(mtd)) {
2628 chip->select_chip(mtd, -1);
8593fbc6 2629 return -EROFS;
b0bb6903 2630 }
61b03bd7 2631
1da177e4 2632 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2633 if (page == chip->pagebuf)
2634 chip->pagebuf = -1;
1da177e4 2635
f722013e 2636 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2637
0612b9dd 2638 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2639 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2640 else
2641 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2642
b0bb6903
HS		 2643 chip->select_chip(mtd, -1);
2644
7bc3312b
TG		 2645 if (status)
2646 return status;
1da177e4 2647
7014568b 2648 ops->oobretlen = ops->ooblen;
1da177e4 2649
7bc3312b 2650 return 0;
8593fbc6
TG		 2651}
2652
2653/**
2654 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2655 * @mtd: MTD device structure
2656 * @to: offset to write to
2657 * @ops: oob operation description structure
8593fbc6
TG		 2658 */
2659static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2660 struct mtd_oob_ops *ops)
2661{
8593fbc6
TG		 2662 int ret = -ENOTSUPP;
2663
2664 ops->retlen = 0;
2665
2666 /* Do not allow writes past end of device */
7014568b 2667 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2668 pr_debug("%s: attempt to write beyond end of device\n",
2669 __func__);
8593fbc6
TG		 2670 return -EINVAL;
2671 }
2672
6a8214aa 2673 nand_get_device(mtd, FL_WRITING);
8593fbc6 2674
f8ac0414 2675 switch (ops->mode) {
0612b9dd
BN		 2676 case MTD_OPS_PLACE_OOB:
2677 case MTD_OPS_AUTO_OOB:
2678 case MTD_OPS_RAW:
8593fbc6
TG		 2679 break;
2680
2681 default:
2682 goto out;
2683 }
2684
2685 if (!ops->datbuf)
2686 ret = nand_do_write_oob(mtd, to, ops);
2687 else
2688 ret = nand_do_write_ops(mtd, to, ops);
2689
7351d3a5 2690out:
1da177e4 2691 nand_release_device(mtd);
1da177e4
LT		 2692 return ret;
2693}
2694
1da177e4 2695/**
49c50b97 2696 * single_erase - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2697 * @mtd: MTD device structure
2698 * @page: the page address of the block which will be erased
1da177e4 2699 *
49c50b97 2700 * Standard erase command for NAND chips. Returns NAND status.
1da177e4 2701 */
49c50b97 2702static int single_erase(struct mtd_info *mtd, int page)
1da177e4 2703{
ace4dfee 2704 struct nand_chip *chip = mtd->priv;
1da177e4 2705 /* Send commands to erase a block */
ace4dfee
TG		 2706 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2707 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
49c50b97
BN		 2708
2709 return chip->waitfunc(mtd, chip);
1da177e4
LT		 2710}
2711
1da177e4
LT		 2712/**
2713 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2714 * @mtd: MTD device structure
2715 * @instr: erase instruction
1da177e4 2716 *
8b6e50c9 2717 * Erase one ore more blocks.
1da177e4 2718 */
e0c7d767 2719static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2720{
e0c7d767 2721 return nand_erase_nand(mtd, instr, 0);
1da177e4 2722}
61b03bd7 2723
1da177e4 2724/**
7854d3f7 2725 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2726 * @mtd: MTD device structure
2727 * @instr: erase instruction
2728 * @allowbbt: allow erasing the bbt area
1da177e4 2729 *
8b6e50c9 2730 * Erase one ore more blocks.
1da177e4 2731 */
ace4dfee
TG		 2732int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2733 int allowbbt)
1da177e4 2734{
69423d99 2735 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2736 struct nand_chip *chip = mtd->priv;
69423d99 2737 loff_t len;
1da177e4 2738
289c0522
BN		 2739 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2740 __func__, (unsigned long long)instr->addr,
2741 (unsigned long long)instr->len);
1da177e4 2742
6fe5a6ac 2743 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2744 return -EINVAL;
1da177e4 2745
1da177e4 2746 /* Grab the lock and see if the device is available */
6a8214aa 2747 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 2748
2749 /* Shift to get first page */
ace4dfee
TG		 2750 page = (int)(instr->addr >> chip->page_shift);
2751 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2752
2753 /* Calculate pages in each block */
ace4dfee 2754 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2755
2756 /* Select the NAND device */
ace4dfee 2757 chip->select_chip(mtd, chipnr);
1da177e4 2758
1da177e4
LT		 2759 /* Check, if it is write protected */
2760 if (nand_check_wp(mtd)) {
289c0522
BN		 2761 pr_debug("%s: device is write protected!\n",
2762 __func__);
1da177e4
LT		 2763 instr->state = MTD_ERASE_FAILED;
2764 goto erase_exit;
2765 }
2766
2767 /* Loop through the pages */
2768 len = instr->len;
2769
2770 instr->state = MTD_ERASING;
2771
2772 while (len) {
12183a20 2773 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2774 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2775 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2776 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2777 __func__, page);
1da177e4
LT		 2778 instr->state = MTD_ERASE_FAILED;
2779 goto erase_exit;
2780 }
61b03bd7 2781
ace4dfee
TG		 2782 /*
2783 * Invalidate the page cache, if we erase the block which
8b6e50c9 2784 * contains the current cached page.
ace4dfee
TG		 2785 */
2786 if (page <= chip->pagebuf && chip->pagebuf <
2787 (page + pages_per_block))
2788 chip->pagebuf = -1;
1da177e4 2789
49c50b97 2790 status = chip->erase(mtd, page & chip->pagemask);
1da177e4 2791
ace4dfee
TG		 2792 /*
2793 * See if operation failed and additional status checks are
2794 * available
2795 */
2796 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2797 status = chip->errstat(mtd, chip, FL_ERASING,
2798 status, page);
068e3c0a 2799
1da177e4 2800 /* See if block erase succeeded */
a4ab4c5d 2801 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2802 pr_debug("%s: failed erase, page 0x%08x\n",
2803 __func__, page);
1da177e4 2804 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2805 instr->fail_addr =
2806 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2807 goto erase_exit;
2808 }
30f464b7 2809
1da177e4 2810 /* Increment page address and decrement length */
daae74ca 2811 len -= (1ULL << chip->phys_erase_shift);
1da177e4
LT		 2812 page += pages_per_block;
2813
2814 /* Check, if we cross a chip boundary */
ace4dfee 2815 if (len && !(page & chip->pagemask)) {
1da177e4 2816 chipnr++;
ace4dfee
TG		 2817 chip->select_chip(mtd, -1);
2818 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2819 }
2820 }
2821 instr->state = MTD_ERASE_DONE;
2822
7351d3a5 2823erase_exit:
1da177e4
LT		 2824
2825 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2826
2827 /* Deselect and wake up anyone waiting on the device */
b0bb6903 2828 chip->select_chip(mtd, -1);
1da177e4
LT		 2829 nand_release_device(mtd);
2830
49defc01
DW		 2831 /* Do call back function */
2832 if (!ret)
2833 mtd_erase_callback(instr);
2834
1da177e4
LT		 2835 /* Return more or less happy */
2836 return ret;
2837}
2838
2839/**
2840 * nand_sync - [MTD Interface] sync
8b6e50c9 2841 * @mtd: MTD device structure
1da177e4 2842 *
8b6e50c9 2843 * Sync is actually a wait for chip ready function.
1da177e4 2844 */
e0c7d767 2845static void nand_sync(struct mtd_info *mtd)
1da177e4 2846{
289c0522 2847 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2848
2849 /* Grab the lock and see if the device is available */
6a8214aa 2850 nand_get_device(mtd, FL_SYNCING);
1da177e4 2851 /* Release it and go back */
e0c7d767 2852 nand_release_device(mtd);
1da177e4
LT		 2853}
2854
1da177e4 2855/**
ace4dfee 2856 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2857 * @mtd: MTD device structure
2858 * @offs: offset relative to mtd start
1da177e4 2859 */
ace4dfee 2860static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2861{
ace4dfee 2862 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2863}
2864
2865/**
ace4dfee 2866 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2867 * @mtd: MTD device structure
2868 * @ofs: offset relative to mtd start
1da177e4 2869 */
e0c7d767 2870static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2871{
1da177e4
LT		 2872 int ret;
2873
f8ac0414
FF		 2874 ret = nand_block_isbad(mtd, ofs);
2875 if (ret) {
8b6e50c9 2876 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2877 if (ret > 0)
2878 return 0;
e0c7d767
DW		 2879 return ret;
2880 }
1da177e4 2881
5a0edb25 2882 return nand_block_markbad_lowlevel(mtd, ofs);
1da177e4
LT		 2883}
2884
7db03ecc
HS		 2885/**
2886 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2887 * @mtd: MTD device structure
2888 * @chip: nand chip info structure
2889 * @addr: feature address.
2890 * @subfeature_param: the subfeature parameters, a four bytes array.
2891 */
2892static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2893 int addr, uint8_t *subfeature_param)
2894{
2895 int status;
05f78359 2896 int i;
7db03ecc 2897
d914c932
DM		 2898 if (!chip->onfi_version ||
2899 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2900 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 2901 return -EINVAL;
2902
2903 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
05f78359
UKK		 2904 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2905 chip->write_byte(mtd, subfeature_param[i]);
2906
7db03ecc
HS		 2907 status = chip->waitfunc(mtd, chip);
2908 if (status & NAND_STATUS_FAIL)
2909 return -EIO;
2910 return 0;
2911}
2912
2913/**
2914 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2915 * @mtd: MTD device structure
2916 * @chip: nand chip info structure
2917 * @addr: feature address.
2918 * @subfeature_param: the subfeature parameters, a four bytes array.
2919 */
2920static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2921 int addr, uint8_t *subfeature_param)
2922{
05f78359
UKK		 2923 int i;
2924
d914c932
DM		 2925 if (!chip->onfi_version ||
2926 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2927 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 2928 return -EINVAL;
2929
7db03ecc 2930 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
05f78359
UKK		 2931 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2932 *subfeature_param++ = chip->read_byte(mtd);
7db03ecc
HS		 2933 return 0;
2934}
2935
962034f4
VW		 2936/**
2937 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2938 * @mtd: MTD device structure
962034f4
VW		 2939 */
2940static int nand_suspend(struct mtd_info *mtd)
2941{
6a8214aa 2942 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 2943}
2944
2945/**
2946 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2947 * @mtd: MTD device structure
962034f4
VW		 2948 */
2949static void nand_resume(struct mtd_info *mtd)
2950{
ace4dfee 2951 struct nand_chip *chip = mtd->priv;
962034f4 2952
ace4dfee 2953 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2954 nand_release_device(mtd);
2955 else
d0370219
BN		 2956 pr_err("%s called for a chip which is not in suspended state\n",
2957 __func__);
962034f4
VW		 2958}
2959
72ea4036
SB		 2960/**
2961 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
2962 * prevent further operations
2963 * @mtd: MTD device structure
2964 */
2965static void nand_shutdown(struct mtd_info *mtd)
2966{
2967 nand_get_device(mtd, FL_SHUTDOWN);
2968}
2969
8b6e50c9 2970/* Set default functions */
ace4dfee 2971static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2972{
1da177e4 2973 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2974 if (!chip->chip_delay)
2975 chip->chip_delay = 20;
1da177e4
LT		 2976
2977 /* check, if a user supplied command function given */
ace4dfee
TG		 2978 if (chip->cmdfunc == NULL)
2979 chip->cmdfunc = nand_command;
1da177e4
LT		 2980
2981 /* check, if a user supplied wait function given */
ace4dfee
TG		 2982 if (chip->waitfunc == NULL)
2983 chip->waitfunc = nand_wait;
2984
2985 if (!chip->select_chip)
2986 chip->select_chip = nand_select_chip;
68e80780 2987
4204cccd
HS		 2988 /* set for ONFI nand */
2989 if (!chip->onfi_set_features)
2990 chip->onfi_set_features = nand_onfi_set_features;
2991 if (!chip->onfi_get_features)
2992 chip->onfi_get_features = nand_onfi_get_features;
2993
68e80780
BN		 2994 /* If called twice, pointers that depend on busw may need to be reset */
2995 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 2996 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2997 if (!chip->read_word)
2998 chip->read_word = nand_read_word;
2999 if (!chip->block_bad)
3000 chip->block_bad = nand_block_bad;
3001 if (!chip->block_markbad)
3002 chip->block_markbad = nand_default_block_markbad;
68e80780 3003 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 3004 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
05f78359
UKK		 3005 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3006 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
68e80780 3007 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 3008 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 3009 if (!chip->scan_bbt)
3010 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 3011
3012 if (!chip->controller) {
3013 chip->controller = &chip->hwcontrol;
3014 spin_lock_init(&chip->controller->lock);
3015 init_waitqueue_head(&chip->controller->wq);
3016 }
3017
7aa65bfd
TG		 3018}
3019
8b6e50c9 3020/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 3021static void sanitize_string(uint8_t *s, size_t len)
3022{
3023 ssize_t i;
3024
8b6e50c9 3025 /* Null terminate */
d1e1f4e4
FF		 3026 s[len - 1] = 0;
3027
8b6e50c9 3028 /* Remove non printable chars */
d1e1f4e4
FF		 3029 for (i = 0; i < len - 1; i++) {
3030 if (s[i] < ' ' || s[i] > 127)
3031 s[i] = '?';
3032 }
3033
8b6e50c9 3034 /* Remove trailing spaces */
d1e1f4e4
FF		 3035 strim(s);
3036}
3037
3038static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3039{
3040 int i;
3041 while (len--) {
3042 crc ^= *p++ << 8;
3043 for (i = 0; i < 8; i++)
3044 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3045 }
3046
3047 return crc;
3048}
3049
6dcbe0cd
HS		 3050/* Parse the Extended Parameter Page. */
3051static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3052 struct nand_chip *chip, struct nand_onfi_params *p)
3053{
3054 struct onfi_ext_param_page *ep;
3055 struct onfi_ext_section *s;
3056 struct onfi_ext_ecc_info *ecc;
3057 uint8_t *cursor;
3058 int ret = -EINVAL;
3059 int len;
3060 int i;
3061
3062 len = le16_to_cpu(p->ext_param_page_length) * 16;
3063 ep = kmalloc(len, GFP_KERNEL);
5cb13271
BN		 3064 if (!ep)
3065 return -ENOMEM;
6dcbe0cd
HS		 3066
3067 /* Send our own NAND_CMD_PARAM. */
3068 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3069
3070 /* Use the Change Read Column command to skip the ONFI param pages. */
3071 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3072 sizeof(*p) * p->num_of_param_pages , -1);
3073
3074 /* Read out the Extended Parameter Page. */
3075 chip->read_buf(mtd, (uint8_t *)ep, len);
3076 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3077 != le16_to_cpu(ep->crc))) {
3078 pr_debug("fail in the CRC.\n");
3079 goto ext_out;
3080 }
3081
3082 /*
3083 * Check the signature.
3084 * Do not strictly follow the ONFI spec, maybe changed in future.
3085 */
3086 if (strncmp(ep->sig, "EPPS", 4)) {
3087 pr_debug("The signature is invalid.\n");
3088 goto ext_out;
3089 }
3090
3091 /* find the ECC section. */
3092 cursor = (uint8_t *)(ep + 1);
3093 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3094 s = ep->sections + i;
3095 if (s->type == ONFI_SECTION_TYPE_2)
3096 break;
3097 cursor += s->length * 16;
3098 }
3099 if (i == ONFI_EXT_SECTION_MAX) {
3100 pr_debug("We can not find the ECC section.\n");
3101 goto ext_out;
3102 }
3103
3104 /* get the info we want. */
3105 ecc = (struct onfi_ext_ecc_info *)cursor;
3106
4ae7d228
BN		 3107 if (!ecc->codeword_size) {
3108 pr_debug("Invalid codeword size\n");
3109 goto ext_out;
6dcbe0cd
HS		 3110 }
3111
4ae7d228
BN		 3112 chip->ecc_strength_ds = ecc->ecc_bits;
3113 chip->ecc_step_ds = 1 << ecc->codeword_size;
5cb13271 3114 ret = 0;
6dcbe0cd
HS		 3115
3116ext_out:
3117 kfree(ep);
3118 return ret;
3119}
3120
8429bb39
BN		 3121static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3122{
3123 struct nand_chip *chip = mtd->priv;
3124 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3125
3126 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3127 feature);
3128}
3129
3130/*
3131 * Configure chip properties from Micron vendor-specific ONFI table
3132 */
3133static void nand_onfi_detect_micron(struct nand_chip *chip,
3134 struct nand_onfi_params *p)
3135{
3136 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3137
3138 if (le16_to_cpu(p->vendor_revision) < 1)
3139 return;
3140
3141 chip->read_retries = micron->read_retry_options;
3142 chip->setup_read_retry = nand_setup_read_retry_micron;
3143}
3144
6fb277ba 3145/*
8b6e50c9 3146 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 3147 */
3148static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 3149 int *busw)
6fb277ba
FF		 3150{
3151 struct nand_onfi_params *p = &chip->onfi_params;
bd9c6e99 3152 int i, j;
6fb277ba
FF		 3153 int val;
3154
7854d3f7 3155 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 3156 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3157 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3158 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3159 return 0;
3160
6fb277ba
FF		 3161 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3162 for (i = 0; i < 3; i++) {
bd9c6e99
BN		 3163 for (j = 0; j < sizeof(*p); j++)
3164 ((uint8_t *)p)[j] = chip->read_byte(mtd);
6fb277ba
FF		 3165 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3166 le16_to_cpu(p->crc)) {
6fb277ba
FF		 3167 break;
3168 }
3169 }
3170
c7f23a70
BN		 3171 if (i == 3) {
3172 pr_err("Could not find valid ONFI parameter page; aborting\n");
6fb277ba 3173 return 0;
c7f23a70 3174 }
6fb277ba 3175
8b6e50c9 3176 /* Check version */
6fb277ba 3177 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 3178 if (val & (1 << 5))
3179 chip->onfi_version = 23;
3180 else if (val & (1 << 4))
6fb277ba
FF		 3181 chip->onfi_version = 22;
3182 else if (val & (1 << 3))
3183 chip->onfi_version = 21;
3184 else if (val & (1 << 2))
3185 chip->onfi_version = 20;
b7b1a29d 3186 else if (val & (1 << 1))
6fb277ba 3187 chip->onfi_version = 10;
b7b1a29d
BN		 3188
3189 if (!chip->onfi_version) {
20171642 3190 pr_info("unsupported ONFI version: %d\n", val);
b7b1a29d
BN		 3191 return 0;
3192 }
6fb277ba
FF		 3193
3194 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3195 sanitize_string(p->model, sizeof(p->model));
3196 if (!mtd->name)
3197 mtd->name = p->model;
4355b70c 3198
6fb277ba 3199 mtd->writesize = le32_to_cpu(p->byte_per_page);
4355b70c
BN		 3200
3201 /*
3202 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3203 * (don't ask me who thought of this...). MTD assumes that these
3204 * dimensions will be power-of-2, so just truncate the remaining area.
3205 */
3206 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3207 mtd->erasesize *= mtd->writesize;
3208
6fb277ba 3209 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4355b70c
BN		 3210
3211 /* See erasesize comment */
3212 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3213 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
13fbd179 3214 chip->bits_per_cell = p->bits_per_cell;
e2985fc1
HS		 3215
3216 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
08c248fb 3217 *busw = NAND_BUSWIDTH_16;
e2985fc1
HS		 3218 else
3219 *busw = 0;
6fb277ba 3220
10c86bab
HS		 3221 if (p->ecc_bits != 0xff) {
3222 chip->ecc_strength_ds = p->ecc_bits;
3223 chip->ecc_step_ds = 512;
6dcbe0cd
HS		 3224 } else if (chip->onfi_version >= 21 &&
3225 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3226
3227 /*
3228 * The nand_flash_detect_ext_param_page() uses the
3229 * Change Read Column command which maybe not supported
3230 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3231 * now. We do not replace user supplied command function.
3232 */
3233 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3234 chip->cmdfunc = nand_command_lp;
3235
3236 /* The Extended Parameter Page is supported since ONFI 2.1. */
3237 if (nand_flash_detect_ext_param_page(mtd, chip, p))
c7f23a70
BN		 3238 pr_warn("Failed to detect ONFI extended param page\n");
3239 } else {
3240 pr_warn("Could not retrieve ONFI ECC requirements\n");
10c86bab
HS		 3241 }
3242
8429bb39
BN		 3243 if (p->jedec_id == NAND_MFR_MICRON)
3244 nand_onfi_detect_micron(chip, p);
3245
6fb277ba
FF		 3246 return 1;
3247}
3248
91361818
HS		 3249/*
3250 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3251 */
3252static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3253 int *busw)
3254{
3255 struct nand_jedec_params *p = &chip->jedec_params;
3256 struct jedec_ecc_info *ecc;
3257 int val;
3258 int i, j;
3259
3260 /* Try JEDEC for unknown chip or LP */
3261 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3262 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3263 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3264 chip->read_byte(mtd) != 'C')
3265 return 0;
3266
3267 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3268 for (i = 0; i < 3; i++) {
3269 for (j = 0; j < sizeof(*p); j++)
3270 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3271
3272 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3273 le16_to_cpu(p->crc))
3274 break;
3275 }
3276
3277 if (i == 3) {
3278 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3279 return 0;
3280 }
3281
3282 /* Check version */
3283 val = le16_to_cpu(p->revision);
3284 if (val & (1 << 2))
3285 chip->jedec_version = 10;
3286 else if (val & (1 << 1))
3287 chip->jedec_version = 1; /* vendor specific version */
3288
3289 if (!chip->jedec_version) {
3290 pr_info("unsupported JEDEC version: %d\n", val);
3291 return 0;
3292 }
3293
3294 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3295 sanitize_string(p->model, sizeof(p->model));
3296 if (!mtd->name)
3297 mtd->name = p->model;
3298
3299 mtd->writesize = le32_to_cpu(p->byte_per_page);
3300
3301 /* Please reference to the comment for nand_flash_detect_onfi. */
3302 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3303 mtd->erasesize *= mtd->writesize;
3304
3305 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3306
3307 /* Please reference to the comment for nand_flash_detect_onfi. */
3308 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3309 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3310 chip->bits_per_cell = p->bits_per_cell;
3311
3312 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3313 *busw = NAND_BUSWIDTH_16;
3314 else
3315 *busw = 0;
3316
3317 /* ECC info */
3318 ecc = &p->ecc_info[0];
3319
3320 if (ecc->codeword_size >= 9) {
3321 chip->ecc_strength_ds = ecc->ecc_bits;
3322 chip->ecc_step_ds = 1 << ecc->codeword_size;
3323 } else {
3324 pr_warn("Invalid codeword size\n");
3325 }
3326
3327 return 1;
3328}
3329
e3b88bd6
BN		 3330/*
3331 * nand_id_has_period - Check if an ID string has a given wraparound period
3332 * @id_data: the ID string
3333 * @arrlen: the length of the @id_data array
3334 * @period: the period of repitition
3335 *
3336 * Check if an ID string is repeated within a given sequence of bytes at
3337 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3338 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3339 * if the repetition has a period of @period; otherwise, returns zero.
3340 */
3341static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3342{
3343 int i, j;
3344 for (i = 0; i < period; i++)
3345 for (j = i + period; j < arrlen; j += period)
3346 if (id_data[i] != id_data[j])
3347 return 0;
3348 return 1;
3349}
3350
3351/*
3352 * nand_id_len - Get the length of an ID string returned by CMD_READID
3353 * @id_data: the ID string
3354 * @arrlen: the length of the @id_data array
3355
3356 * Returns the length of the ID string, according to known wraparound/trailing
3357 * zero patterns. If no pattern exists, returns the length of the array.
3358 */
3359static int nand_id_len(u8 *id_data, int arrlen)
3360{
3361 int last_nonzero, period;
3362
3363 /* Find last non-zero byte */
3364 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3365 if (id_data[last_nonzero])
3366 break;
3367
3368 /* All zeros */
3369 if (last_nonzero < 0)
3370 return 0;
3371
3372 /* Calculate wraparound period */
3373 for (period = 1; period < arrlen; period++)
3374 if (nand_id_has_period(id_data, arrlen, period))
3375 break;
3376
3377 /* There's a repeated pattern */
3378 if (period < arrlen)
3379 return period;
3380
3381 /* There are trailing zeros */
3382 if (last_nonzero < arrlen - 1)
3383 return last_nonzero + 1;
3384
3385 /* No pattern detected */
3386 return arrlen;
3387}
3388
7db906b7
HS		 3389/* Extract the bits of per cell from the 3rd byte of the extended ID */
3390static int nand_get_bits_per_cell(u8 cellinfo)
3391{
3392 int bits;
3393
3394 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3395 bits >>= NAND_CI_CELLTYPE_SHIFT;
3396 return bits + 1;
3397}
3398
fc09bbc0
BN		 3399/*
3400 * Many new NAND share similar device ID codes, which represent the size of the
3401 * chip. The rest of the parameters must be decoded according to generic or
3402 * manufacturer-specific "extended ID" decoding patterns.
3403 */
3404static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3405 u8 id_data[8], int *busw)
3406{
e3b88bd6 3407 int extid, id_len;
fc09bbc0 3408 /* The 3rd id byte holds MLC / multichip data */
7db906b7 3409 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
fc09bbc0
BN		 3410 /* The 4th id byte is the important one */
3411 extid = id_data[3];
3412
e3b88bd6
BN		 3413 id_len = nand_id_len(id_data, 8);
3414
fc09bbc0
BN		 3415 /*
3416 * Field definitions are in the following datasheets:
3417 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 3418 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 3419 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 3420 *
af451af4
BN		 3421 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3422 * ID to decide what to do.
fc09bbc0 3423 */
af451af4 3424 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
1d0ed69d 3425 !nand_is_slc(chip) && id_data[5] != 0x00) {
fc09bbc0
BN		 3426 /* Calc pagesize */
3427 mtd->writesize = 2048 << (extid & 0x03);
3428 extid >>= 2;
3429 /* Calc oobsize */
e2d3a35e 3430 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 3431 case 1:
3432 mtd->oobsize = 128;
3433 break;
3434 case 2:
3435 mtd->oobsize = 218;
3436 break;
3437 case 3:
3438 mtd->oobsize = 400;
3439 break;
e2d3a35e 3440 case 4:
fc09bbc0
BN		 3441 mtd->oobsize = 436;
3442 break;
e2d3a35e
BN		 3443 case 5:
3444 mtd->oobsize = 512;
3445 break;
3446 case 6:
e2d3a35e
BN		 3447 mtd->oobsize = 640;
3448 break;
94d04e82
HS		 3449 case 7:
3450 default: /* Other cases are "reserved" (unknown) */
3451 mtd->oobsize = 1024;
3452 break;
fc09bbc0
BN		 3453 }
3454 extid >>= 2;
3455 /* Calc blocksize */
3456 mtd->erasesize = (128 * 1024) <<
3457 (((extid >> 1) & 0x04) | (extid & 0x03));
3458 *busw = 0;
73ca392f 3459 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
1d0ed69d 3460 !nand_is_slc(chip)) {
73ca392f
BN		 3461 unsigned int tmp;
3462
3463 /* Calc pagesize */
3464 mtd->writesize = 2048 << (extid & 0x03);
3465 extid >>= 2;
3466 /* Calc oobsize */
3467 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3468 case 0:
3469 mtd->oobsize = 128;
3470 break;
3471 case 1:
3472 mtd->oobsize = 224;
3473 break;
3474 case 2:
3475 mtd->oobsize = 448;
3476 break;
3477 case 3:
3478 mtd->oobsize = 64;
3479 break;
3480 case 4:
3481 mtd->oobsize = 32;
3482 break;
3483 case 5:
3484 mtd->oobsize = 16;
3485 break;
3486 default:
3487 mtd->oobsize = 640;
3488 break;
3489 }
3490 extid >>= 2;
3491 /* Calc blocksize */
3492 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3493 if (tmp < 0x03)
3494 mtd->erasesize = (128 * 1024) << tmp;
3495 else if (tmp == 0x03)
3496 mtd->erasesize = 768 * 1024;
3497 else
3498 mtd->erasesize = (64 * 1024) << tmp;
3499 *busw = 0;
fc09bbc0
BN		 3500 } else {
3501 /* Calc pagesize */
3502 mtd->writesize = 1024 << (extid & 0x03);
3503 extid >>= 2;
3504 /* Calc oobsize */
3505 mtd->oobsize = (8 << (extid & 0x01)) *
3506 (mtd->writesize >> 9);
3507 extid >>= 2;
3508 /* Calc blocksize. Blocksize is multiples of 64KiB */
3509 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3510 extid >>= 2;
3511 /* Get buswidth information */
3512 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
60c67382
BN		 3513
3514 /*
3515 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3516 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3517 * follows:
3518 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3519 * 110b -> 24nm
3520 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3521 */
3522 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
1d0ed69d 3523 nand_is_slc(chip) &&
60c67382
BN		 3524 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3525 !(id_data[4] & 0x80) /* !BENAND */) {
3526 mtd->oobsize = 32 * mtd->writesize >> 9;
3527 }
3528
fc09bbc0
BN		 3529 }
3530}
3531
f23a481c
BN		 3532/*
3533 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3534 * decodes a matching ID table entry and assigns the MTD size parameters for
3535 * the chip.
3536 */
3537static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3538 struct nand_flash_dev *type, u8 id_data[8],
3539 int *busw)
3540{
3541 int maf_id = id_data[0];
3542
3543 mtd->erasesize = type->erasesize;
3544 mtd->writesize = type->pagesize;
3545 mtd->oobsize = mtd->writesize / 32;
3546 *busw = type->options & NAND_BUSWIDTH_16;
3547
1c195e90
HS		 3548 /* All legacy ID NAND are small-page, SLC */
3549 chip->bits_per_cell = 1;
3550
f23a481c
BN		 3551 /*
3552 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3553 * some Spansion chips have erasesize that conflicts with size
3554 * listed in nand_ids table.
3555 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3556 */
3557 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3558 && id_data[6] == 0x00 && id_data[7] == 0x00
3559 && mtd->writesize == 512) {
3560 mtd->erasesize = 128 * 1024;
3561 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3562 }
3563}
3564
7e74c2d7
BN		 3565/*
3566 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3567 * heuristic patterns using various detected parameters (e.g., manufacturer,
3568 * page size, cell-type information).
3569 */
3570static void nand_decode_bbm_options(struct mtd_info *mtd,
3571 struct nand_chip *chip, u8 id_data[8])
3572{
3573 int maf_id = id_data[0];
3574
3575 /* Set the bad block position */
3576 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3577 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3578 else
3579 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3580
3581 /*
3582 * Bad block marker is stored in the last page of each block on Samsung
3583 * and Hynix MLC devices; stored in first two pages of each block on
3584 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3585 * AMD/Spansion, and Macronix. All others scan only the first page.
3586 */
1d0ed69d 3587 if (!nand_is_slc(chip) &&
7e74c2d7
BN		 3588 (maf_id == NAND_MFR_SAMSUNG ||
3589 maf_id == NAND_MFR_HYNIX))
3590 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
1d0ed69d 3591 else if ((nand_is_slc(chip) &&
7e74c2d7
BN		 3592 (maf_id == NAND_MFR_SAMSUNG ||
3593 maf_id == NAND_MFR_HYNIX ||
3594 maf_id == NAND_MFR_TOSHIBA ||
3595 maf_id == NAND_MFR_AMD ||
3596 maf_id == NAND_MFR_MACRONIX)) ||
3597 (mtd->writesize == 2048 &&
3598 maf_id == NAND_MFR_MICRON))
3599 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3600}
3601
ec6e87e3
HS		 3602static inline bool is_full_id_nand(struct nand_flash_dev *type)
3603{
3604 return type->id_len;
3605}
3606
3607static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3608 struct nand_flash_dev *type, u8 *id_data, int *busw)
3609{
3610 if (!strncmp(type->id, id_data, type->id_len)) {
3611 mtd->writesize = type->pagesize;
3612 mtd->erasesize = type->erasesize;
3613 mtd->oobsize = type->oobsize;
3614
7db906b7 3615 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
ec6e87e3
HS		 3616 chip->chipsize = (uint64_t)type->chipsize << 20;
3617 chip->options |= type->options;
57219342
HS		 3618 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3619 chip->ecc_step_ds = NAND_ECC_STEP(type);
57a94e24
BB		 3620 chip->onfi_timing_mode_default =
3621 type->onfi_timing_mode_default;
ec6e87e3
HS		 3622
3623 *busw = type->options & NAND_BUSWIDTH_16;
3624
092b6a1d
CZ		 3625 if (!mtd->name)
3626 mtd->name = type->name;
3627
ec6e87e3
HS		 3628 return true;
3629 }
3630 return false;
3631}
3632
7aa65bfd 3633/*
8b6e50c9 3634 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3635 */
3636static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3637 struct nand_chip *chip,
7351d3a5 3638 int *maf_id, int *dev_id,
5e81e88a 3639 struct nand_flash_dev *type)
7aa65bfd 3640{
bb77082f 3641 int busw;
d1e1f4e4 3642 int i, maf_idx;
426c457a 3643 u8 id_data[8];
1da177e4
LT		 3644
3645 /* Select the device */
ace4dfee 3646 chip->select_chip(mtd, 0);
1da177e4 3647
ef89a880
KB		 3648 /*
3649 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3650 * after power-up.
ef89a880
KB		 3651 */
3652 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3653
1da177e4 3654 /* Send the command for reading device ID */
ace4dfee 3655 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3656
3657 /* Read manufacturer and device IDs */
ace4dfee 3658 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3659 *dev_id = chip->read_byte(mtd);
1da177e4 3660
8b6e50c9
BN		 3661 /*
3662 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3663 * interface concerns can cause random data which looks like a
3664 * possibly credible NAND flash to appear. If the two results do
3665 * not match, ignore the device completely.
3666 */
3667
3668 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3669
4aef9b78
BN		 3670 /* Read entire ID string */
3671 for (i = 0; i < 8; i++)
426c457a 3672 id_data[i] = chip->read_byte(mtd);
ed8165c7 3673
d1e1f4e4 3674 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
20171642 3675 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
d0370219 3676 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3677 return ERR_PTR(-ENODEV);
3678 }
3679
7aa65bfd 3680 if (!type)
5e81e88a
DW		 3681 type = nand_flash_ids;
3682
ec6e87e3
HS		 3683 for (; type->name != NULL; type++) {
3684 if (is_full_id_nand(type)) {
3685 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3686 goto ident_done;
3687 } else if (*dev_id == type->dev_id) {
db5b09f6 3688 break;
ec6e87e3
HS		 3689 }
3690 }
5e81e88a 3691
d1e1f4e4
FF		 3692 chip->onfi_version = 0;
3693 if (!type->name || !type->pagesize) {
35fc5195 3694 /* Check if the chip is ONFI compliant */
47450b35 3695 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3696 goto ident_done;
91361818
HS		 3697
3698 /* Check if the chip is JEDEC compliant */
3699 if (nand_flash_detect_jedec(mtd, chip, &busw))
3700 goto ident_done;
d1e1f4e4
FF		 3701 }
3702
5e81e88a 3703 if (!type->name)
7aa65bfd
TG		 3704 return ERR_PTR(-ENODEV);
3705
ba0251fe
TG		 3706 if (!mtd->name)
3707 mtd->name = type->name;
3708
69423d99 3709 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3710
12a40a57 3711 if (!type->pagesize && chip->init_size) {
8b6e50c9 3712 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3713 busw = chip->init_size(mtd, chip, id_data);
3714 } else if (!type->pagesize) {
fc09bbc0
BN		 3715 /* Decode parameters from extended ID */
3716 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3717 } else {
f23a481c 3718 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3719 }
bf7a01bf
BN		 3720 /* Get chip options */
3721 chip->options |= type->options;
d1e1f4e4 3722
8b6e50c9
BN		 3723 /*
3724 * Check if chip is not a Samsung device. Do not clear the
3725 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3726 */
3727 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3728 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3729ident_done:
3730
7aa65bfd 3731 /* Try to identify manufacturer */
9a909867 3732 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3733 if (nand_manuf_ids[maf_idx].id == *maf_id)
3734 break;
3735 }
0ea4a755 3736
64b37b2a
MC		 3737 if (chip->options & NAND_BUSWIDTH_AUTO) {
3738 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3739 chip->options |= busw;
3740 nand_set_defaults(chip, busw);
3741 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3742 /*
3743 * Check, if buswidth is correct. Hardware drivers should set
3744 * chip correct!
3745 */
20171642
EG		 3746 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3747 *maf_id, *dev_id);
3748 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3749 pr_warn("bus width %d instead %d bit\n",
d0370219
BN		 3750 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3751 busw ? 16 : 8);
7aa65bfd
TG		 3752 return ERR_PTR(-EINVAL);
3753 }
61b03bd7 3754
7e74c2d7
BN		 3755 nand_decode_bbm_options(mtd, chip, id_data);
3756
7aa65bfd 3757 /* Calculate the address shift from the page size */
ace4dfee 3758 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3759 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3760 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3761
ace4dfee 3762 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3763 ffs(mtd->erasesize) - 1;
69423d99
AH		 3764 if (chip->chipsize & 0xffffffff)
3765 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3766 else {
3767 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3768 chip->chip_shift += 32 - 1;
3769 }
1da177e4 3770
26d9be11 3771 chip->badblockbits = 8;
49c50b97 3772 chip->erase = single_erase;
7aa65bfd 3773
8b6e50c9 3774 /* Do not replace user supplied command function! */
ace4dfee
TG		 3775 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3776 chip->cmdfunc = nand_command_lp;
7aa65bfd 3777
20171642
EG		 3778 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3779 *maf_id, *dev_id);
ffdac6cd
HS		 3780
3781 if (chip->onfi_version)
3782 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3783 chip->onfi_params.model);
3784 else if (chip->jedec_version)
3785 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3786 chip->jedec_params.model);
3787 else
3788 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3789 type->name);
3790
3755a991 3791 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3723e93c 3792 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3755a991 3793 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3794 return type;
3795}
3796
5844feea
BN		 3797static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip,
3798 struct device_node *dn)
3799{
3800 int ecc_mode, ecc_strength, ecc_step;
3801
3802 if (of_get_nand_bus_width(dn) == 16)
3803 chip->options |= NAND_BUSWIDTH_16;
3804
3805 if (of_get_nand_on_flash_bbt(dn))
3806 chip->bbt_options |= NAND_BBT_USE_FLASH;
3807
3808 ecc_mode = of_get_nand_ecc_mode(dn);
3809 ecc_strength = of_get_nand_ecc_strength(dn);
3810 ecc_step = of_get_nand_ecc_step_size(dn);
3811
3812 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
3813 (!(ecc_step >= 0) && ecc_strength >= 0)) {
3814 pr_err("must set both strength and step size in DT\n");
3815 return -EINVAL;
3816 }
3817
3818 if (ecc_mode >= 0)
3819 chip->ecc.mode = ecc_mode;
3820
3821 if (ecc_strength >= 0)
3822 chip->ecc.strength = ecc_strength;
3823
3824 if (ecc_step > 0)
3825 chip->ecc.size = ecc_step;
3826
3827 return 0;
3828}
3829
7aa65bfd 3830/**
3b85c321 3831 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3832 * @mtd: MTD device structure
3833 * @maxchips: number of chips to scan for
3834 * @table: alternative NAND ID table
7aa65bfd 3835 *
8b6e50c9
BN		 3836 * This is the first phase of the normal nand_scan() function. It reads the
3837 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3838 *
3b85c321 3839 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3840 */
5e81e88a
DW		 3841int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3842 struct nand_flash_dev *table)
7aa65bfd 3843{
bb77082f 3844 int i, nand_maf_id, nand_dev_id;
ace4dfee 3845 struct nand_chip *chip = mtd->priv;
7aa65bfd 3846 struct nand_flash_dev *type;
5844feea
BN		 3847 int ret;
3848
3849 if (chip->dn) {
3850 ret = nand_dt_init(mtd, chip, chip->dn);
3851 if (ret)
3852 return ret;
3853 }
7aa65bfd 3854
7aa65bfd 3855 /* Set the default functions */
bb77082f 3856 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
7aa65bfd
TG		 3857
3858 /* Read the flash type */
bb77082f
CZ		 3859 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3860 &nand_dev_id, table);
7aa65bfd
TG		 3861
3862 if (IS_ERR(type)) {
b1c6e6db 3863 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3864 pr_warn("No NAND device found\n");
ace4dfee 3865 chip->select_chip(mtd, -1);
7aa65bfd 3866 return PTR_ERR(type);
1da177e4
LT		 3867 }
3868
07300164
HS		 3869 chip->select_chip(mtd, -1);
3870
7aa65bfd 3871 /* Check for a chip array */
e0c7d767 3872 for (i = 1; i < maxchips; i++) {
ace4dfee 3873 chip->select_chip(mtd, i);
ef89a880
KB		 3874 /* See comment in nand_get_flash_type for reset */
3875 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3876 /* Send the command for reading device ID */
ace4dfee 3877 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3878 /* Read manufacturer and device IDs */
ace4dfee 3879 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 3880 nand_dev_id != chip->read_byte(mtd)) {
3881 chip->select_chip(mtd, -1);
1da177e4 3882 break;
07300164
HS		 3883 }
3884 chip->select_chip(mtd, -1);
1da177e4
LT		 3885 }
3886 if (i > 1)
20171642 3887 pr_info("%d chips detected\n", i);
61b03bd7 3888
1da177e4 3889 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3890 chip->numchips = i;
3891 mtd->size = i * chip->chipsize;
7aa65bfd 3892
3b85c321
DW		 3893 return 0;
3894}
7351d3a5 3895EXPORT_SYMBOL(nand_scan_ident);
3b85c321 3896
67a9ad9b
EG		 3897/*
3898 * Check if the chip configuration meet the datasheet requirements.
3899
3900 * If our configuration corrects A bits per B bytes and the minimum
3901 * required correction level is X bits per Y bytes, then we must ensure
3902 * both of the following are true:
3903 *
3904 * (1) A / B >= X / Y
3905 * (2) A >= X
3906 *
3907 * Requirement (1) ensures we can correct for the required bitflip density.
3908 * Requirement (2) ensures we can correct even when all bitflips are clumped
3909 * in the same sector.
3910 */
3911static bool nand_ecc_strength_good(struct mtd_info *mtd)
3912{
3913 struct nand_chip *chip = mtd->priv;
3914 struct nand_ecc_ctrl *ecc = &chip->ecc;
3915 int corr, ds_corr;
3916
3917 if (ecc->size == 0 || chip->ecc_step_ds == 0)
3918 /* Not enough information */
3919 return true;
3920
3921 /*
3922 * We get the number of corrected bits per page to compare
3923 * the correction density.
3924 */
3925 corr = (mtd->writesize * ecc->strength) / ecc->size;
3926 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
3927
3928 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
3929}
3b85c321
DW		 3930
3931/**
3932 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3933 * @mtd: MTD device structure
3b85c321 3934 *
8b6e50c9
BN		 3935 * This is the second phase of the normal nand_scan() function. It fills out
3936 * all the uninitialized function pointers with the defaults and scans for a
3937 * bad block table if appropriate.
3b85c321
DW		 3938 */
3939int nand_scan_tail(struct mtd_info *mtd)
3940{
3941 int i;
3942 struct nand_chip *chip = mtd->priv;
97de79e0 3943 struct nand_ecc_ctrl *ecc = &chip->ecc;
f02ea4e6 3944 struct nand_buffers *nbuf;
3b85c321 3945
e2414f4c
BN		 3946 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3947 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3948 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3949
f02ea4e6
HS		 3950 if (!(chip->options & NAND_OWN_BUFFERS)) {
3951 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
3952 + mtd->oobsize * 3, GFP_KERNEL);
3953 if (!nbuf)
3954 return -ENOMEM;
3955 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
3956 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
3957 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
3958
3959 chip->buffers = nbuf;
3960 } else {
3961 if (!chip->buffers)
3962 return -ENOMEM;
3963 }
4bf63fcb 3964
7dcdcbef 3965 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3966 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3967
7aa65bfd 3968 /*
8b6e50c9 3969 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3970 */
97de79e0 3971 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3972 switch (mtd->oobsize) {
1da177e4 3973 case 8:
97de79e0 3974 ecc->layout = &nand_oob_8;
1da177e4
LT		 3975 break;
3976 case 16:
97de79e0 3977 ecc->layout = &nand_oob_16;
1da177e4
LT		 3978 break;
3979 case 64:
97de79e0 3980 ecc->layout = &nand_oob_64;
1da177e4 3981 break;
81ec5364 3982 case 128:
97de79e0 3983 ecc->layout = &nand_oob_128;
81ec5364 3984 break;
1da177e4 3985 default:
d0370219
BN		 3986 pr_warn("No oob scheme defined for oobsize %d\n",
3987 mtd->oobsize);
1da177e4
LT		 3988 BUG();
3989 }
3990 }
61b03bd7 3991
956e944c
DW		 3992 if (!chip->write_page)
3993 chip->write_page = nand_write_page;
3994
61b03bd7 3995 /*
8b6e50c9 3996 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3997 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3998 */
956e944c 3999
97de79e0 4000 switch (ecc->mode) {
6e0cb135
SN		 4001 case NAND_ECC_HW_OOB_FIRST:
4002 /* Similar to NAND_ECC_HW, but a separate read_page handle */
97de79e0 4003 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
2ac63d90 4004 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
6e0cb135
SN		 4005 BUG();
4006 }
97de79e0
HS		 4007 if (!ecc->read_page)
4008 ecc->read_page = nand_read_page_hwecc_oob_first;
6e0cb135 4009
6dfc6d25 4010 case NAND_ECC_HW:
8b6e50c9 4011 /* Use standard hwecc read page function? */
97de79e0
HS		 4012 if (!ecc->read_page)
4013 ecc->read_page = nand_read_page_hwecc;
4014 if (!ecc->write_page)
4015 ecc->write_page = nand_write_page_hwecc;
4016 if (!ecc->read_page_raw)
4017 ecc->read_page_raw = nand_read_page_raw;
4018 if (!ecc->write_page_raw)
4019 ecc->write_page_raw = nand_write_page_raw;
4020 if (!ecc->read_oob)
4021 ecc->read_oob = nand_read_oob_std;
4022 if (!ecc->write_oob)
4023 ecc->write_oob = nand_write_oob_std;
4024 if (!ecc->read_subpage)
4025 ecc->read_subpage = nand_read_subpage;
4026 if (!ecc->write_subpage)
4027 ecc->write_subpage = nand_write_subpage_hwecc;
f5bbdacc 4028
6dfc6d25 4029 case NAND_ECC_HW_SYNDROME:
97de79e0
HS		 4030 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4031 (!ecc->read_page ||
4032 ecc->read_page == nand_read_page_hwecc ||
4033 !ecc->write_page ||
4034 ecc->write_page == nand_write_page_hwecc)) {
2ac63d90 4035 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
6dfc6d25
TG		 4036 BUG();
4037 }
8b6e50c9 4038 /* Use standard syndrome read/write page function? */
97de79e0
HS		 4039 if (!ecc->read_page)
4040 ecc->read_page = nand_read_page_syndrome;
4041 if (!ecc->write_page)
4042 ecc->write_page = nand_write_page_syndrome;
4043 if (!ecc->read_page_raw)
4044 ecc->read_page_raw = nand_read_page_raw_syndrome;
4045 if (!ecc->write_page_raw)
4046 ecc->write_page_raw = nand_write_page_raw_syndrome;
4047 if (!ecc->read_oob)
4048 ecc->read_oob = nand_read_oob_syndrome;
4049 if (!ecc->write_oob)
4050 ecc->write_oob = nand_write_oob_syndrome;
4051
4052 if (mtd->writesize >= ecc->size) {
4053 if (!ecc->strength) {
e2788c98
MD		 4054 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4055 BUG();
4056 }
6dfc6d25 4057 break;
e2788c98 4058 }
2ac63d90
RM		 4059 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4060 ecc->size, mtd->writesize);
97de79e0 4061 ecc->mode = NAND_ECC_SOFT;
61b03bd7 4062
6dfc6d25 4063 case NAND_ECC_SOFT:
97de79e0
HS		 4064 ecc->calculate = nand_calculate_ecc;
4065 ecc->correct = nand_correct_data;
4066 ecc->read_page = nand_read_page_swecc;
4067 ecc->read_subpage = nand_read_subpage;
4068 ecc->write_page = nand_write_page_swecc;
4069 ecc->read_page_raw = nand_read_page_raw;
4070 ecc->write_page_raw = nand_write_page_raw;
4071 ecc->read_oob = nand_read_oob_std;
4072 ecc->write_oob = nand_write_oob_std;
4073 if (!ecc->size)
4074 ecc->size = 256;
4075 ecc->bytes = 3;
4076 ecc->strength = 1;
1da177e4 4077 break;
61b03bd7 4078
193bd400
ID		 4079 case NAND_ECC_SOFT_BCH:
4080 if (!mtd_nand_has_bch()) {
148256fa 4081 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
193bd400
ID		 4082 BUG();
4083 }
97de79e0
HS		 4084 ecc->calculate = nand_bch_calculate_ecc;
4085 ecc->correct = nand_bch_correct_data;
4086 ecc->read_page = nand_read_page_swecc;
4087 ecc->read_subpage = nand_read_subpage;
4088 ecc->write_page = nand_write_page_swecc;
4089 ecc->read_page_raw = nand_read_page_raw;
4090 ecc->write_page_raw = nand_write_page_raw;
4091 ecc->read_oob = nand_read_oob_std;
4092 ecc->write_oob = nand_write_oob_std;
193bd400 4093 /*
e0377cde
AS		 4094 * Board driver should supply ecc.size and ecc.strength values
4095 * to select how many bits are correctable. Otherwise, default
4096 * to 4 bits for large page devices.
193bd400 4097 */
97de79e0
HS		 4098 if (!ecc->size && (mtd->oobsize >= 64)) {
4099 ecc->size = 512;
e0377cde 4100 ecc->strength = 4;
193bd400 4101 }
e0377cde
AS		 4102
4103 /* See nand_bch_init() for details. */
4104 ecc->bytes = DIV_ROUND_UP(
4105 ecc->strength * fls(8 * ecc->size), 8);
97de79e0
HS		 4106 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4107 &ecc->layout);
4108 if (!ecc->priv) {
9a4d4d69 4109 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 4110 BUG();
4111 }
4112 break;
4113
61b03bd7 4114 case NAND_ECC_NONE:
2ac63d90 4115 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
97de79e0
HS		 4116 ecc->read_page = nand_read_page_raw;
4117 ecc->write_page = nand_write_page_raw;
4118 ecc->read_oob = nand_read_oob_std;
4119 ecc->read_page_raw = nand_read_page_raw;
4120 ecc->write_page_raw = nand_write_page_raw;
4121 ecc->write_oob = nand_write_oob_std;
4122 ecc->size = mtd->writesize;
4123 ecc->bytes = 0;
4124 ecc->strength = 0;
1da177e4 4125 break;
956e944c 4126
1da177e4 4127 default:
97de79e0 4128 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
61b03bd7 4129 BUG();
1da177e4 4130 }
61b03bd7 4131
9ce244b3 4132 /* For many systems, the standard OOB write also works for raw */
97de79e0
HS		 4133 if (!ecc->read_oob_raw)
4134 ecc->read_oob_raw = ecc->read_oob;
4135 if (!ecc->write_oob_raw)
4136 ecc->write_oob_raw = ecc->write_oob;
9ce244b3 4137
5bd34c09
TG		 4138 /*
4139 * The number of bytes available for a client to place data into
8b6e50c9 4140 * the out of band area.
5bd34c09 4141 */
97de79e0
HS		 4142 ecc->layout->oobavail = 0;
4143 for (i = 0; ecc->layout->oobfree[i].length
4144 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4145 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4146 mtd->oobavail = ecc->layout->oobavail;
5bd34c09 4147
54c39e9b
TP		 4148 /* ECC sanity check: warn if it's too weak */
4149 if (!nand_ecc_strength_good(mtd))
4150 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4151 mtd->name);
67a9ad9b 4152
7aa65bfd
TG		 4153 /*
4154 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 4155 * mode.
7aa65bfd 4156 */
97de79e0
HS		 4157 ecc->steps = mtd->writesize / ecc->size;
4158 if (ecc->steps * ecc->size != mtd->writesize) {
9a4d4d69 4159 pr_warn("Invalid ECC parameters\n");
6dfc6d25 4160 BUG();
1da177e4 4161 }
97de79e0 4162 ecc->total = ecc->steps * ecc->bytes;
61b03bd7 4163
8b6e50c9 4164 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
1d0ed69d 4165 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
97de79e0 4166 switch (ecc->steps) {
29072b96
TG		 4167 case 2:
4168 mtd->subpage_sft = 1;
4169 break;
4170 case 4:
4171 case 8:
81ec5364 4172 case 16:
29072b96
TG		 4173 mtd->subpage_sft = 2;
4174 break;
4175 }
4176 }
4177 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4178
04bbd0ea 4179 /* Initialize state */
ace4dfee 4180 chip->state = FL_READY;
1da177e4 4181
1da177e4 4182 /* Invalidate the pagebuffer reference */
ace4dfee 4183 chip->pagebuf = -1;
1da177e4 4184
a5ff4f10 4185 /* Large page NAND with SOFT_ECC should support subpage reads */
4007e2d1
RL		 4186 switch (ecc->mode) {
4187 case NAND_ECC_SOFT:
4188 case NAND_ECC_SOFT_BCH:
4189 if (chip->page_shift > 9)
4190 chip->options |= NAND_SUBPAGE_READ;
4191 break;
4192
4193 default:
4194 break;
4195 }
a5ff4f10 4196
1da177e4 4197 /* Fill in remaining MTD driver data */
963d1c28 4198 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
93edbad6
ML		 4199 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4200 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 4201 mtd->_erase = nand_erase;
4202 mtd->_point = NULL;
4203 mtd->_unpoint = NULL;
4204 mtd->_read = nand_read;
4205 mtd->_write = nand_write;
4206 mtd->_panic_write = panic_nand_write;
4207 mtd->_read_oob = nand_read_oob;
4208 mtd->_write_oob = nand_write_oob;
4209 mtd->_sync = nand_sync;
4210 mtd->_lock = NULL;
4211 mtd->_unlock = NULL;
4212 mtd->_suspend = nand_suspend;
4213 mtd->_resume = nand_resume;
72ea4036 4214 mtd->_reboot = nand_shutdown;
8471bb73 4215 mtd->_block_isreserved = nand_block_isreserved;
3c3c10bb
AB		 4216 mtd->_block_isbad = nand_block_isbad;
4217 mtd->_block_markbad = nand_block_markbad;
cbcab65a 4218 mtd->writebufsize = mtd->writesize;
1da177e4 4219
6a918bad 4220 /* propagate ecc info to mtd_info */
97de79e0
HS		 4221 mtd->ecclayout = ecc->layout;
4222 mtd->ecc_strength = ecc->strength;
4223 mtd->ecc_step_size = ecc->size;
ea3b2ea2
SL		 4224 /*
4225 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4226 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4227 * properly set.
4228 */
4229 if (!mtd->bitflip_threshold)
240181fd 4230 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
1da177e4 4231
0040bf38 4232 /* Check, if we should skip the bad block table scan */
ace4dfee 4233 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 4234 return 0;
1da177e4
LT		 4235
4236 /* Build bad block table */
ace4dfee 4237 return chip->scan_bbt(mtd);
1da177e4 4238}
7351d3a5 4239EXPORT_SYMBOL(nand_scan_tail);
1da177e4 4240
8b6e50c9
BN		 4241/*
4242 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 4243 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 4244 * to call us from in-kernel code if the core NAND support is modular.
4245 */
3b85c321
DW		 4246#ifdef MODULE
4247#define caller_is_module() (1)
4248#else
4249#define caller_is_module() \
a6e6abd5 4250 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 4251#endif
4252
4253/**
4254 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4255 * @mtd: MTD device structure
4256 * @maxchips: number of chips to scan for
3b85c321 4257 *
8b6e50c9
BN		 4258 * This fills out all the uninitialized function pointers with the defaults.
4259 * The flash ID is read and the mtd/chip structures are filled with the
4260 * appropriate values. The mtd->owner field must be set to the module of the
4261 * caller.
3b85c321
DW		 4262 */
4263int nand_scan(struct mtd_info *mtd, int maxchips)
4264{
4265 int ret;
4266
4267 /* Many callers got this wrong, so check for it for a while... */
4268 if (!mtd->owner && caller_is_module()) {
d0370219 4269 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 4270 BUG();
4271 }
4272
5e81e88a 4273 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 4274 if (!ret)
4275 ret = nand_scan_tail(mtd);
4276 return ret;
4277}
7351d3a5 4278EXPORT_SYMBOL(nand_scan);
3b85c321 4279
1da177e4 4280/**
61b03bd7 4281 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 4282 * @mtd: MTD device structure
4283 */
e0c7d767 4284void nand_release(struct mtd_info *mtd)
1da177e4 4285{
ace4dfee 4286 struct nand_chip *chip = mtd->priv;
1da177e4 4287
193bd400
ID		 4288 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4289 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4290
5ffcaf3d 4291 mtd_device_unregister(mtd);
1da177e4 4292
fa671646 4293 /* Free bad block table memory */
ace4dfee 4294 kfree(chip->bbt);
4bf63fcb
DW		 4295 if (!(chip->options & NAND_OWN_BUFFERS))
4296 kfree(chip->buffers);
58373ff0
BN		 4297
4298 /* Free bad block descriptor memory */
4299 if (chip->badblock_pattern && chip->badblock_pattern->options
4300 & NAND_BBT_DYNAMICSTRUCT)
4301 kfree(chip->badblock_pattern);
1da177e4 4302}
e0c7d767 4303EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 4304
4305static int __init nand_base_init(void)
4306{
4307 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4308 return 0;
4309}
4310
4311static void __exit nand_base_exit(void)
4312{
4313 led_trigger_unregister_simple(nand_led_trigger);
4314}
4315
4316module_init(nand_base_init);
4317module_exit(nand_base_exit);
4318
e0c7d767 4319MODULE_LICENSE("GPL");
7351d3a5
FF		 4320MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4321MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 4322MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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