Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Additional technical information is available on |
8b2b403c | 10 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 24 | * if we have HW ECC support. |
1da177e4 LT |
25 | * The AG-AND chips have nice features for speed improvement, |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
c0b8ba7b | 27 | * BBT table is not serialized, has to be fixed |
1da177e4 | 28 | * |
1da177e4 LT |
29 | * This program is free software; you can redistribute it and/or modify |
30 | * it under the terms of the GNU General Public License version 2 as | |
31 | * published by the Free Software Foundation. | |
32 | * | |
33 | */ | |
34 | ||
552d9205 | 35 | #include <linux/module.h> |
1da177e4 LT |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
7aa65bfd | 38 | #include <linux/err.h> |
1da177e4 LT |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 45 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
46 | #include <linux/interrupt.h> |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
7351d3a5 | 49 | #include <linux/io.h> |
1da177e4 | 50 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
51 | |
52 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 53 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
54 | .eccbytes = 3, |
55 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
56 | .oobfree = { |
57 | {.offset = 3, | |
58 | .length = 2}, | |
59 | {.offset = 6, | |
f8ac0414 | 60 | .length = 2} } |
1da177e4 LT |
61 | }; |
62 | ||
5bd34c09 | 63 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
64 | .eccbytes = 6, |
65 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
66 | .oobfree = { |
67 | {.offset = 8, | |
f8ac0414 | 68 | . length = 8} } |
1da177e4 LT |
69 | }; |
70 | ||
5bd34c09 | 71 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
72 | .eccbytes = 24, |
73 | .eccpos = { | |
e0c7d767 DW |
74 | 40, 41, 42, 43, 44, 45, 46, 47, |
75 | 48, 49, 50, 51, 52, 53, 54, 55, | |
76 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
77 | .oobfree = { |
78 | {.offset = 2, | |
f8ac0414 | 79 | .length = 38} } |
1da177e4 LT |
80 | }; |
81 | ||
81ec5364 TG |
82 | static struct nand_ecclayout nand_oob_128 = { |
83 | .eccbytes = 48, | |
84 | .eccpos = { | |
85 | 80, 81, 82, 83, 84, 85, 86, 87, | |
86 | 88, 89, 90, 91, 92, 93, 94, 95, | |
87 | 96, 97, 98, 99, 100, 101, 102, 103, | |
88 | 104, 105, 106, 107, 108, 109, 110, 111, | |
89 | 112, 113, 114, 115, 116, 117, 118, 119, | |
90 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
91 | .oobfree = { | |
92 | {.offset = 2, | |
f8ac0414 | 93 | .length = 78} } |
81ec5364 TG |
94 | }; |
95 | ||
ace4dfee | 96 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 97 | int new_state); |
1da177e4 | 98 | |
8593fbc6 TG |
99 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
100 | struct mtd_oob_ops *ops); | |
101 | ||
d470a97c | 102 | /* |
8e87d782 | 103 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
104 | * compiled away when LED support is disabled. |
105 | */ | |
106 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
107 | ||
6fe5a6ac VS |
108 | static int check_offs_len(struct mtd_info *mtd, |
109 | loff_t ofs, uint64_t len) | |
110 | { | |
111 | struct nand_chip *chip = mtd->priv; | |
112 | int ret = 0; | |
113 | ||
114 | /* Start address must align on block boundary */ | |
115 | if (ofs & ((1 << chip->phys_erase_shift) - 1)) { | |
289c0522 | 116 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
117 | ret = -EINVAL; |
118 | } | |
119 | ||
120 | /* Length must align on block boundary */ | |
121 | if (len & ((1 << chip->phys_erase_shift) - 1)) { | |
289c0522 | 122 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
123 | ret = -EINVAL; |
124 | } | |
125 | ||
126 | /* Do not allow past end of device */ | |
127 | if (ofs + len > mtd->size) { | |
289c0522 | 128 | pr_debug("%s: past end of device\n", __func__); |
6fe5a6ac VS |
129 | ret = -EINVAL; |
130 | } | |
131 | ||
132 | return ret; | |
133 | } | |
134 | ||
1da177e4 LT |
135 | /** |
136 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 137 | * @mtd: MTD device structure |
61b03bd7 | 138 | * |
8b6e50c9 | 139 | * Deselect, release chip lock and wake up anyone waiting on the device. |
1da177e4 | 140 | */ |
e0c7d767 | 141 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 142 | { |
ace4dfee | 143 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
144 | |
145 | /* De-select the NAND device */ | |
ace4dfee | 146 | chip->select_chip(mtd, -1); |
0dfc6246 | 147 | |
a36ed299 | 148 | /* Release the controller and the chip */ |
ace4dfee TG |
149 | spin_lock(&chip->controller->lock); |
150 | chip->controller->active = NULL; | |
151 | chip->state = FL_READY; | |
152 | wake_up(&chip->controller->wq); | |
153 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
154 | } |
155 | ||
156 | /** | |
157 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 158 | * @mtd: MTD device structure |
1da177e4 | 159 | * |
7854d3f7 | 160 | * Default read function for 8bit buswidth |
1da177e4 | 161 | */ |
58dd8f2b | 162 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 163 | { |
ace4dfee TG |
164 | struct nand_chip *chip = mtd->priv; |
165 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
166 | } |
167 | ||
1da177e4 LT |
168 | /** |
169 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip | |
7854d3f7 | 170 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 171 | * @mtd: MTD device structure |
1da177e4 | 172 | * |
7854d3f7 BN |
173 | * Default read function for 16bit buswidth with endianness conversion. |
174 | * | |
1da177e4 | 175 | */ |
58dd8f2b | 176 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 177 | { |
ace4dfee TG |
178 | struct nand_chip *chip = mtd->priv; |
179 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
180 | } |
181 | ||
1da177e4 LT |
182 | /** |
183 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 184 | * @mtd: MTD device structure |
1da177e4 | 185 | * |
7854d3f7 | 186 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
187 | */ |
188 | static u16 nand_read_word(struct mtd_info *mtd) | |
189 | { | |
ace4dfee TG |
190 | struct nand_chip *chip = mtd->priv; |
191 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
192 | } |
193 | ||
1da177e4 LT |
194 | /** |
195 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
196 | * @mtd: MTD device structure |
197 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
198 | * |
199 | * Default select function for 1 chip devices. | |
200 | */ | |
ace4dfee | 201 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 202 | { |
ace4dfee TG |
203 | struct nand_chip *chip = mtd->priv; |
204 | ||
205 | switch (chipnr) { | |
1da177e4 | 206 | case -1: |
ace4dfee | 207 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
208 | break; |
209 | case 0: | |
1da177e4 LT |
210 | break; |
211 | ||
212 | default: | |
213 | BUG(); | |
214 | } | |
215 | } | |
216 | ||
217 | /** | |
218 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
219 | * @mtd: MTD device structure |
220 | * @buf: data buffer | |
221 | * @len: number of bytes to write | |
1da177e4 | 222 | * |
7854d3f7 | 223 | * Default write function for 8bit buswidth. |
1da177e4 | 224 | */ |
58dd8f2b | 225 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
226 | { |
227 | int i; | |
ace4dfee | 228 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 229 | |
e0c7d767 | 230 | for (i = 0; i < len; i++) |
ace4dfee | 231 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
232 | } |
233 | ||
234 | /** | |
61b03bd7 | 235 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
236 | * @mtd: MTD device structure |
237 | * @buf: buffer to store date | |
238 | * @len: number of bytes to read | |
1da177e4 | 239 | * |
7854d3f7 | 240 | * Default read function for 8bit buswidth. |
1da177e4 | 241 | */ |
58dd8f2b | 242 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
243 | { |
244 | int i; | |
ace4dfee | 245 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 246 | |
e0c7d767 | 247 | for (i = 0; i < len; i++) |
ace4dfee | 248 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
249 | } |
250 | ||
251 | /** | |
61b03bd7 | 252 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
8b6e50c9 BN |
253 | * @mtd: MTD device structure |
254 | * @buf: buffer containing the data to compare | |
255 | * @len: number of bytes to compare | |
1da177e4 | 256 | * |
7854d3f7 | 257 | * Default verify function for 8bit buswidth. |
1da177e4 | 258 | */ |
58dd8f2b | 259 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
260 | { |
261 | int i; | |
ace4dfee | 262 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 263 | |
e0c7d767 | 264 | for (i = 0; i < len; i++) |
ace4dfee | 265 | if (buf[i] != readb(chip->IO_ADDR_R)) |
1da177e4 | 266 | return -EFAULT; |
1da177e4 LT |
267 | return 0; |
268 | } | |
269 | ||
270 | /** | |
271 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
272 | * @mtd: MTD device structure |
273 | * @buf: data buffer | |
274 | * @len: number of bytes to write | |
1da177e4 | 275 | * |
7854d3f7 | 276 | * Default write function for 16bit buswidth. |
1da177e4 | 277 | */ |
58dd8f2b | 278 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
279 | { |
280 | int i; | |
ace4dfee | 281 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
282 | u16 *p = (u16 *) buf; |
283 | len >>= 1; | |
61b03bd7 | 284 | |
e0c7d767 | 285 | for (i = 0; i < len; i++) |
ace4dfee | 286 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 287 | |
1da177e4 LT |
288 | } |
289 | ||
290 | /** | |
61b03bd7 | 291 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
292 | * @mtd: MTD device structure |
293 | * @buf: buffer to store date | |
294 | * @len: number of bytes to read | |
1da177e4 | 295 | * |
7854d3f7 | 296 | * Default read function for 16bit buswidth. |
1da177e4 | 297 | */ |
58dd8f2b | 298 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
299 | { |
300 | int i; | |
ace4dfee | 301 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
302 | u16 *p = (u16 *) buf; |
303 | len >>= 1; | |
304 | ||
e0c7d767 | 305 | for (i = 0; i < len; i++) |
ace4dfee | 306 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
307 | } |
308 | ||
309 | /** | |
61b03bd7 | 310 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
8b6e50c9 BN |
311 | * @mtd: MTD device structure |
312 | * @buf: buffer containing the data to compare | |
313 | * @len: number of bytes to compare | |
1da177e4 | 314 | * |
7854d3f7 | 315 | * Default verify function for 16bit buswidth. |
1da177e4 | 316 | */ |
58dd8f2b | 317 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
318 | { |
319 | int i; | |
ace4dfee | 320 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
321 | u16 *p = (u16 *) buf; |
322 | len >>= 1; | |
323 | ||
e0c7d767 | 324 | for (i = 0; i < len; i++) |
ace4dfee | 325 | if (p[i] != readw(chip->IO_ADDR_R)) |
1da177e4 LT |
326 | return -EFAULT; |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
331 | /** | |
332 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
333 | * @mtd: MTD device structure |
334 | * @ofs: offset from device start | |
335 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 336 | * |
61b03bd7 | 337 | * Check, if the block is bad. |
1da177e4 LT |
338 | */ |
339 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
340 | { | |
341 | int page, chipnr, res = 0; | |
ace4dfee | 342 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
343 | u16 bad; |
344 | ||
5fb1549d | 345 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
346 | ofs += mtd->erasesize - mtd->writesize; |
347 | ||
1a12f46a TK |
348 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
349 | ||
1da177e4 | 350 | if (getchip) { |
ace4dfee | 351 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 352 | |
ace4dfee | 353 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
354 | |
355 | /* Select the NAND device */ | |
ace4dfee | 356 | chip->select_chip(mtd, chipnr); |
1a12f46a | 357 | } |
1da177e4 | 358 | |
ace4dfee TG |
359 | if (chip->options & NAND_BUSWIDTH_16) { |
360 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, | |
1a12f46a | 361 | page); |
ace4dfee TG |
362 | bad = cpu_to_le16(chip->read_word(mtd)); |
363 | if (chip->badblockpos & 0x1) | |
49196f33 | 364 | bad >>= 8; |
e0b58d0a ML |
365 | else |
366 | bad &= 0xFF; | |
1da177e4 | 367 | } else { |
1a12f46a | 368 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); |
e0b58d0a | 369 | bad = chip->read_byte(mtd); |
1da177e4 | 370 | } |
61b03bd7 | 371 | |
e0b58d0a ML |
372 | if (likely(chip->badblockbits == 8)) |
373 | res = bad != 0xFF; | |
374 | else | |
375 | res = hweight8(bad) < chip->badblockbits; | |
376 | ||
ace4dfee | 377 | if (getchip) |
1da177e4 | 378 | nand_release_device(mtd); |
61b03bd7 | 379 | |
1da177e4 LT |
380 | return res; |
381 | } | |
382 | ||
383 | /** | |
384 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
8b6e50c9 BN |
385 | * @mtd: MTD device structure |
386 | * @ofs: offset from device start | |
1da177e4 | 387 | * |
8b6e50c9 BN |
388 | * This is the default implementation, which can be overridden by a hardware |
389 | * specific driver. | |
1da177e4 LT |
390 | */ |
391 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
392 | { | |
ace4dfee | 393 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 394 | uint8_t buf[2] = { 0, 0 }; |
02ed70bb | 395 | int block, ret, i = 0; |
61b03bd7 | 396 | |
00918429 BN |
397 | if (!(chip->bbt_options & NAND_BBT_USE_FLASH)) { |
398 | struct erase_info einfo; | |
399 | ||
400 | /* Attempt erase before marking OOB */ | |
401 | memset(&einfo, 0, sizeof(einfo)); | |
402 | einfo.mtd = mtd; | |
403 | einfo.addr = ofs; | |
404 | einfo.len = 1 << chip->phys_erase_shift; | |
405 | nand_erase_nand(mtd, &einfo, 0); | |
406 | } | |
407 | ||
5fb1549d | 408 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
409 | ofs += mtd->erasesize - mtd->writesize; |
410 | ||
1da177e4 | 411 | /* Get block number */ |
4226b510 | 412 | block = (int)(ofs >> chip->bbt_erase_shift); |
ace4dfee TG |
413 | if (chip->bbt) |
414 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 | 415 | |
8b6e50c9 | 416 | /* Do we have a flash based bad block table? */ |
bb9ebd4e | 417 | if (chip->bbt_options & NAND_BBT_USE_FLASH) |
f1a28c02 TG |
418 | ret = nand_update_bbt(mtd, ofs); |
419 | else { | |
4a89ff88 BN |
420 | struct mtd_oob_ops ops; |
421 | ||
c0b8ba7b | 422 | nand_get_device(chip, mtd, FL_WRITING); |
f1a28c02 | 423 | |
a0dc5529 BN |
424 | /* |
425 | * Write to first two pages if necessary. If we write to more | |
426 | * than one location, the first error encountered quits the | |
427 | * procedure. We write two bytes per location, so we dont have | |
428 | * to mess with 16 bit access. | |
02ed70bb | 429 | */ |
4a89ff88 BN |
430 | ops.len = ops.ooblen = 2; |
431 | ops.datbuf = NULL; | |
432 | ops.oobbuf = buf; | |
433 | ops.ooboffs = chip->badblockpos & ~0x01; | |
23b1a99b | 434 | ops.mode = MTD_OPS_PLACE_OOB; |
02ed70bb | 435 | do { |
4a89ff88 | 436 | ret = nand_do_write_oob(mtd, ofs, &ops); |
02ed70bb | 437 | |
02ed70bb BN |
438 | i++; |
439 | ofs += mtd->writesize; | |
5fb1549d | 440 | } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && |
02ed70bb BN |
441 | i < 2); |
442 | ||
c0b8ba7b | 443 | nand_release_device(mtd); |
f1a28c02 TG |
444 | } |
445 | if (!ret) | |
446 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 447 | |
f1a28c02 | 448 | return ret; |
1da177e4 LT |
449 | } |
450 | ||
61b03bd7 | 451 | /** |
1da177e4 | 452 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 453 | * @mtd: MTD device structure |
1da177e4 | 454 | * |
8b6e50c9 BN |
455 | * Check, if the device is write protected. The function expects, that the |
456 | * device is already selected. | |
1da177e4 | 457 | */ |
e0c7d767 | 458 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 459 | { |
ace4dfee | 460 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 461 | |
8b6e50c9 | 462 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
463 | if (chip->options & NAND_BROKEN_XD) |
464 | return 0; | |
465 | ||
1da177e4 | 466 | /* Check the WP bit */ |
ace4dfee TG |
467 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
468 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
469 | } |
470 | ||
471 | /** | |
472 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
473 | * @mtd: MTD device structure |
474 | * @ofs: offset from device start | |
475 | * @getchip: 0, if the chip is already selected | |
476 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
477 | * |
478 | * Check, if the block is bad. Either by reading the bad block table or | |
479 | * calling of the scan function. | |
480 | */ | |
2c0a2bed TG |
481 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
482 | int allowbbt) | |
1da177e4 | 483 | { |
ace4dfee | 484 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 485 | |
ace4dfee TG |
486 | if (!chip->bbt) |
487 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 488 | |
1da177e4 | 489 | /* Return info from the table */ |
e0c7d767 | 490 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
491 | } |
492 | ||
2af7c653 SK |
493 | /** |
494 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
495 | * @mtd: MTD device structure |
496 | * @timeo: Timeout | |
2af7c653 SK |
497 | * |
498 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
499 | * context. | |
500 | */ | |
501 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
502 | { | |
503 | struct nand_chip *chip = mtd->priv; | |
504 | int i; | |
505 | ||
506 | /* Wait for the device to get ready */ | |
507 | for (i = 0; i < timeo; i++) { | |
508 | if (chip->dev_ready(mtd)) | |
509 | break; | |
510 | touch_softlockup_watchdog(); | |
511 | mdelay(1); | |
512 | } | |
513 | } | |
514 | ||
7854d3f7 | 515 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 516 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 517 | { |
ace4dfee | 518 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 519 | unsigned long timeo = jiffies + 2; |
3b88775c | 520 | |
2af7c653 SK |
521 | /* 400ms timeout */ |
522 | if (in_interrupt() || oops_in_progress) | |
523 | return panic_nand_wait_ready(mtd, 400); | |
524 | ||
8fe833c1 | 525 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 526 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 527 | do { |
ace4dfee | 528 | if (chip->dev_ready(mtd)) |
8fe833c1 | 529 | break; |
8446f1d3 | 530 | touch_softlockup_watchdog(); |
61b03bd7 | 531 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 532 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 533 | } |
4b648b02 | 534 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 535 | |
1da177e4 LT |
536 | /** |
537 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
538 | * @mtd: MTD device structure |
539 | * @command: the command to be sent | |
540 | * @column: the column address for this command, -1 if none | |
541 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 542 | * |
8b6e50c9 BN |
543 | * Send command to NAND device. This function is used for small page devices |
544 | * (256/512 Bytes per page). | |
1da177e4 | 545 | */ |
7abd3ef9 TG |
546 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
547 | int column, int page_addr) | |
1da177e4 | 548 | { |
ace4dfee | 549 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 550 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 551 | |
8b6e50c9 | 552 | /* Write out the command to the device */ |
1da177e4 LT |
553 | if (command == NAND_CMD_SEQIN) { |
554 | int readcmd; | |
555 | ||
28318776 | 556 | if (column >= mtd->writesize) { |
1da177e4 | 557 | /* OOB area */ |
28318776 | 558 | column -= mtd->writesize; |
1da177e4 LT |
559 | readcmd = NAND_CMD_READOOB; |
560 | } else if (column < 256) { | |
561 | /* First 256 bytes --> READ0 */ | |
562 | readcmd = NAND_CMD_READ0; | |
563 | } else { | |
564 | column -= 256; | |
565 | readcmd = NAND_CMD_READ1; | |
566 | } | |
ace4dfee | 567 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 568 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 569 | } |
ace4dfee | 570 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 571 | |
8b6e50c9 | 572 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
573 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
574 | /* Serially input address */ | |
575 | if (column != -1) { | |
576 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 577 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 578 | column >>= 1; |
ace4dfee | 579 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
580 | ctrl &= ~NAND_CTRL_CHANGE; |
581 | } | |
582 | if (page_addr != -1) { | |
ace4dfee | 583 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 584 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 585 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 586 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
587 | if (chip->chipsize > (32 << 20)) |
588 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 589 | } |
ace4dfee | 590 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
591 | |
592 | /* | |
8b6e50c9 BN |
593 | * Program and erase have their own busy handlers status and sequential |
594 | * in needs no delay | |
e0c7d767 | 595 | */ |
1da177e4 | 596 | switch (command) { |
61b03bd7 | 597 | |
1da177e4 LT |
598 | case NAND_CMD_PAGEPROG: |
599 | case NAND_CMD_ERASE1: | |
600 | case NAND_CMD_ERASE2: | |
601 | case NAND_CMD_SEQIN: | |
602 | case NAND_CMD_STATUS: | |
603 | return; | |
604 | ||
605 | case NAND_CMD_RESET: | |
ace4dfee | 606 | if (chip->dev_ready) |
1da177e4 | 607 | break; |
ace4dfee TG |
608 | udelay(chip->chip_delay); |
609 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 610 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
611 | chip->cmd_ctrl(mtd, |
612 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
613 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
614 | ; | |
1da177e4 LT |
615 | return; |
616 | ||
e0c7d767 | 617 | /* This applies to read commands */ |
1da177e4 | 618 | default: |
61b03bd7 | 619 | /* |
1da177e4 LT |
620 | * If we don't have access to the busy pin, we apply the given |
621 | * command delay | |
e0c7d767 | 622 | */ |
ace4dfee TG |
623 | if (!chip->dev_ready) { |
624 | udelay(chip->chip_delay); | |
1da177e4 | 625 | return; |
61b03bd7 | 626 | } |
1da177e4 | 627 | } |
8b6e50c9 BN |
628 | /* |
629 | * Apply this short delay always to ensure that we do wait tWB in | |
630 | * any case on any machine. | |
631 | */ | |
e0c7d767 | 632 | ndelay(100); |
3b88775c TG |
633 | |
634 | nand_wait_ready(mtd); | |
1da177e4 LT |
635 | } |
636 | ||
637 | /** | |
638 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
639 | * @mtd: MTD device structure |
640 | * @command: the command to be sent | |
641 | * @column: the column address for this command, -1 if none | |
642 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 643 | * |
7abd3ef9 | 644 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
645 | * devices. We don't have the separate regions as we have in the small page |
646 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 647 | */ |
7abd3ef9 TG |
648 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
649 | int column, int page_addr) | |
1da177e4 | 650 | { |
ace4dfee | 651 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
652 | |
653 | /* Emulate NAND_CMD_READOOB */ | |
654 | if (command == NAND_CMD_READOOB) { | |
28318776 | 655 | column += mtd->writesize; |
1da177e4 LT |
656 | command = NAND_CMD_READ0; |
657 | } | |
61b03bd7 | 658 | |
7abd3ef9 | 659 | /* Command latch cycle */ |
ace4dfee | 660 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 661 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
662 | |
663 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 664 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
665 | |
666 | /* Serially input address */ | |
667 | if (column != -1) { | |
668 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 669 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 670 | column >>= 1; |
ace4dfee | 671 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 672 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 673 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 674 | } |
1da177e4 | 675 | if (page_addr != -1) { |
ace4dfee TG |
676 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
677 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 678 | NAND_NCE | NAND_ALE); |
1da177e4 | 679 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
680 | if (chip->chipsize > (128 << 20)) |
681 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 682 | NAND_NCE | NAND_ALE); |
1da177e4 | 683 | } |
1da177e4 | 684 | } |
ace4dfee | 685 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
686 | |
687 | /* | |
8b6e50c9 BN |
688 | * Program and erase have their own busy handlers status, sequential |
689 | * in, and deplete1 need no delay. | |
30f464b7 | 690 | */ |
1da177e4 | 691 | switch (command) { |
61b03bd7 | 692 | |
1da177e4 LT |
693 | case NAND_CMD_CACHEDPROG: |
694 | case NAND_CMD_PAGEPROG: | |
695 | case NAND_CMD_ERASE1: | |
696 | case NAND_CMD_ERASE2: | |
697 | case NAND_CMD_SEQIN: | |
7bc3312b | 698 | case NAND_CMD_RNDIN: |
1da177e4 | 699 | case NAND_CMD_STATUS: |
30f464b7 | 700 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
701 | return; |
702 | ||
30f464b7 DM |
703 | case NAND_CMD_STATUS_ERROR: |
704 | case NAND_CMD_STATUS_ERROR0: | |
705 | case NAND_CMD_STATUS_ERROR1: | |
706 | case NAND_CMD_STATUS_ERROR2: | |
707 | case NAND_CMD_STATUS_ERROR3: | |
8b6e50c9 | 708 | /* Read error status commands require only a short delay */ |
ace4dfee | 709 | udelay(chip->chip_delay); |
30f464b7 | 710 | return; |
1da177e4 LT |
711 | |
712 | case NAND_CMD_RESET: | |
ace4dfee | 713 | if (chip->dev_ready) |
1da177e4 | 714 | break; |
ace4dfee | 715 | udelay(chip->chip_delay); |
12efdde3 TG |
716 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
717 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
718 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
719 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
720 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
721 | ; | |
1da177e4 LT |
722 | return; |
723 | ||
7bc3312b TG |
724 | case NAND_CMD_RNDOUT: |
725 | /* No ready / busy check necessary */ | |
726 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
727 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
728 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
729 | NAND_NCE | NAND_CTRL_CHANGE); | |
730 | return; | |
731 | ||
1da177e4 | 732 | case NAND_CMD_READ0: |
12efdde3 TG |
733 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
734 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
735 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
736 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 737 | |
e0c7d767 | 738 | /* This applies to read commands */ |
1da177e4 | 739 | default: |
61b03bd7 | 740 | /* |
1da177e4 | 741 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 742 | * command delay. |
e0c7d767 | 743 | */ |
ace4dfee TG |
744 | if (!chip->dev_ready) { |
745 | udelay(chip->chip_delay); | |
1da177e4 | 746 | return; |
61b03bd7 | 747 | } |
1da177e4 | 748 | } |
3b88775c | 749 | |
8b6e50c9 BN |
750 | /* |
751 | * Apply this short delay always to ensure that we do wait tWB in | |
752 | * any case on any machine. | |
753 | */ | |
e0c7d767 | 754 | ndelay(100); |
3b88775c TG |
755 | |
756 | nand_wait_ready(mtd); | |
1da177e4 LT |
757 | } |
758 | ||
2af7c653 SK |
759 | /** |
760 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
761 | * @chip: the nand chip descriptor |
762 | * @mtd: MTD device structure | |
763 | * @new_state: the state which is requested | |
2af7c653 SK |
764 | * |
765 | * Used when in panic, no locks are taken. | |
766 | */ | |
767 | static void panic_nand_get_device(struct nand_chip *chip, | |
768 | struct mtd_info *mtd, int new_state) | |
769 | { | |
7854d3f7 | 770 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
771 | chip->controller->active = chip; |
772 | chip->state = new_state; | |
773 | } | |
774 | ||
1da177e4 LT |
775 | /** |
776 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
777 | * @chip: the nand chip descriptor |
778 | * @mtd: MTD device structure | |
779 | * @new_state: the state which is requested | |
1da177e4 LT |
780 | * |
781 | * Get the device and lock it for exclusive access | |
782 | */ | |
2c0a2bed | 783 | static int |
ace4dfee | 784 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 785 | { |
ace4dfee TG |
786 | spinlock_t *lock = &chip->controller->lock; |
787 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 788 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 789 | retry: |
0dfc6246 TG |
790 | spin_lock(lock); |
791 | ||
b8b3ee9a | 792 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
793 | if (!chip->controller->active) |
794 | chip->controller->active = chip; | |
a36ed299 | 795 | |
ace4dfee TG |
796 | if (chip->controller->active == chip && chip->state == FL_READY) { |
797 | chip->state = new_state; | |
0dfc6246 | 798 | spin_unlock(lock); |
962034f4 VW |
799 | return 0; |
800 | } | |
801 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
802 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
803 | chip->state = FL_PM_SUSPENDED; | |
804 | spin_unlock(lock); | |
805 | return 0; | |
6b0d9a84 | 806 | } |
0dfc6246 TG |
807 | } |
808 | set_current_state(TASK_UNINTERRUPTIBLE); | |
809 | add_wait_queue(wq, &wait); | |
810 | spin_unlock(lock); | |
811 | schedule(); | |
812 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
813 | goto retry; |
814 | } | |
815 | ||
2af7c653 | 816 | /** |
8b6e50c9 BN |
817 | * panic_nand_wait - [GENERIC] wait until the command is done |
818 | * @mtd: MTD device structure | |
819 | * @chip: NAND chip structure | |
820 | * @timeo: timeout | |
2af7c653 SK |
821 | * |
822 | * Wait for command done. This is a helper function for nand_wait used when | |
823 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 824 | * an oops through mtdoops. |
2af7c653 SK |
825 | */ |
826 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
827 | unsigned long timeo) | |
828 | { | |
829 | int i; | |
830 | for (i = 0; i < timeo; i++) { | |
831 | if (chip->dev_ready) { | |
832 | if (chip->dev_ready(mtd)) | |
833 | break; | |
834 | } else { | |
835 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
836 | break; | |
837 | } | |
838 | mdelay(1); | |
f8ac0414 | 839 | } |
2af7c653 SK |
840 | } |
841 | ||
1da177e4 | 842 | /** |
8b6e50c9 BN |
843 | * nand_wait - [DEFAULT] wait until the command is done |
844 | * @mtd: MTD device structure | |
845 | * @chip: NAND chip structure | |
1da177e4 | 846 | * |
8b6e50c9 BN |
847 | * Wait for command done. This applies to erase and program only. Erase can |
848 | * take up to 400ms and program up to 20ms according to general NAND and | |
849 | * SmartMedia specs. | |
844d3b42 | 850 | */ |
7bc3312b | 851 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
852 | { |
853 | ||
e0c7d767 | 854 | unsigned long timeo = jiffies; |
7bc3312b | 855 | int status, state = chip->state; |
61b03bd7 | 856 | |
1da177e4 | 857 | if (state == FL_ERASING) |
e0c7d767 | 858 | timeo += (HZ * 400) / 1000; |
1da177e4 | 859 | else |
e0c7d767 | 860 | timeo += (HZ * 20) / 1000; |
1da177e4 | 861 | |
8fe833c1 RP |
862 | led_trigger_event(nand_led_trigger, LED_FULL); |
863 | ||
8b6e50c9 BN |
864 | /* |
865 | * Apply this short delay always to ensure that we do wait tWB in any | |
866 | * case on any machine. | |
867 | */ | |
e0c7d767 | 868 | ndelay(100); |
1da177e4 | 869 | |
ace4dfee TG |
870 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
871 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 872 | else |
ace4dfee | 873 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 874 | |
2af7c653 SK |
875 | if (in_interrupt() || oops_in_progress) |
876 | panic_nand_wait(mtd, chip, timeo); | |
877 | else { | |
878 | while (time_before(jiffies, timeo)) { | |
879 | if (chip->dev_ready) { | |
880 | if (chip->dev_ready(mtd)) | |
881 | break; | |
882 | } else { | |
883 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
884 | break; | |
885 | } | |
886 | cond_resched(); | |
1da177e4 | 887 | } |
1da177e4 | 888 | } |
8fe833c1 RP |
889 | led_trigger_event(nand_led_trigger, LED_OFF); |
890 | ||
ace4dfee | 891 | status = (int)chip->read_byte(mtd); |
1da177e4 LT |
892 | return status; |
893 | } | |
894 | ||
7d70f334 | 895 | /** |
b6d676db | 896 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
897 | * @mtd: mtd info |
898 | * @ofs: offset to start unlock from | |
899 | * @len: length to unlock | |
8b6e50c9 BN |
900 | * @invert: when = 0, unlock the range of blocks within the lower and |
901 | * upper boundary address | |
902 | * when = 1, unlock the range of blocks outside the boundaries | |
903 | * of the lower and upper boundary address | |
7d70f334 | 904 | * |
8b6e50c9 | 905 | * Returs unlock status. |
7d70f334 VS |
906 | */ |
907 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
908 | uint64_t len, int invert) | |
909 | { | |
910 | int ret = 0; | |
911 | int status, page; | |
912 | struct nand_chip *chip = mtd->priv; | |
913 | ||
914 | /* Submit address of first page to unlock */ | |
915 | page = ofs >> chip->page_shift; | |
916 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
917 | ||
918 | /* Submit address of last page to unlock */ | |
919 | page = (ofs + len) >> chip->page_shift; | |
920 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
921 | (page | invert) & chip->pagemask); | |
922 | ||
923 | /* Call wait ready function */ | |
924 | status = chip->waitfunc(mtd, chip); | |
7d70f334 VS |
925 | /* See if device thinks it succeeded */ |
926 | if (status & 0x01) { | |
289c0522 | 927 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
928 | __func__, status); |
929 | ret = -EIO; | |
930 | } | |
931 | ||
932 | return ret; | |
933 | } | |
934 | ||
935 | /** | |
b6d676db | 936 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
937 | * @mtd: mtd info |
938 | * @ofs: offset to start unlock from | |
939 | * @len: length to unlock | |
7d70f334 | 940 | * |
8b6e50c9 | 941 | * Returns unlock status. |
7d70f334 VS |
942 | */ |
943 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
944 | { | |
945 | int ret = 0; | |
946 | int chipnr; | |
947 | struct nand_chip *chip = mtd->priv; | |
948 | ||
289c0522 | 949 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
950 | __func__, (unsigned long long)ofs, len); |
951 | ||
952 | if (check_offs_len(mtd, ofs, len)) | |
953 | ret = -EINVAL; | |
954 | ||
955 | /* Align to last block address if size addresses end of the device */ | |
956 | if (ofs + len == mtd->size) | |
957 | len -= mtd->erasesize; | |
958 | ||
959 | nand_get_device(chip, mtd, FL_UNLOCKING); | |
960 | ||
961 | /* Shift to get chip number */ | |
962 | chipnr = ofs >> chip->chip_shift; | |
963 | ||
964 | chip->select_chip(mtd, chipnr); | |
965 | ||
966 | /* Check, if it is write protected */ | |
967 | if (nand_check_wp(mtd)) { | |
289c0522 | 968 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
969 | __func__); |
970 | ret = -EIO; | |
971 | goto out; | |
972 | } | |
973 | ||
974 | ret = __nand_unlock(mtd, ofs, len, 0); | |
975 | ||
976 | out: | |
7d70f334 VS |
977 | nand_release_device(mtd); |
978 | ||
979 | return ret; | |
980 | } | |
7351d3a5 | 981 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
982 | |
983 | /** | |
b6d676db | 984 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
985 | * @mtd: mtd info |
986 | * @ofs: offset to start unlock from | |
987 | * @len: length to unlock | |
7d70f334 | 988 | * |
8b6e50c9 BN |
989 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
990 | * have this feature, but it allows only to lock all blocks, not for specified | |
991 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
992 | * now. | |
7d70f334 | 993 | * |
8b6e50c9 | 994 | * Returns lock status. |
7d70f334 VS |
995 | */ |
996 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
997 | { | |
998 | int ret = 0; | |
999 | int chipnr, status, page; | |
1000 | struct nand_chip *chip = mtd->priv; | |
1001 | ||
289c0522 | 1002 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1003 | __func__, (unsigned long long)ofs, len); |
1004 | ||
1005 | if (check_offs_len(mtd, ofs, len)) | |
1006 | ret = -EINVAL; | |
1007 | ||
1008 | nand_get_device(chip, mtd, FL_LOCKING); | |
1009 | ||
1010 | /* Shift to get chip number */ | |
1011 | chipnr = ofs >> chip->chip_shift; | |
1012 | ||
1013 | chip->select_chip(mtd, chipnr); | |
1014 | ||
1015 | /* Check, if it is write protected */ | |
1016 | if (nand_check_wp(mtd)) { | |
289c0522 | 1017 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1018 | __func__); |
1019 | status = MTD_ERASE_FAILED; | |
1020 | ret = -EIO; | |
1021 | goto out; | |
1022 | } | |
1023 | ||
1024 | /* Submit address of first page to lock */ | |
1025 | page = ofs >> chip->page_shift; | |
1026 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1027 | ||
1028 | /* Call wait ready function */ | |
1029 | status = chip->waitfunc(mtd, chip); | |
7d70f334 VS |
1030 | /* See if device thinks it succeeded */ |
1031 | if (status & 0x01) { | |
289c0522 | 1032 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1033 | __func__, status); |
1034 | ret = -EIO; | |
1035 | goto out; | |
1036 | } | |
1037 | ||
1038 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1039 | ||
1040 | out: | |
7d70f334 VS |
1041 | nand_release_device(mtd); |
1042 | ||
1043 | return ret; | |
1044 | } | |
7351d3a5 | 1045 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1046 | |
8593fbc6 | 1047 | /** |
7854d3f7 | 1048 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1049 | * @mtd: mtd info structure |
1050 | * @chip: nand chip info structure | |
1051 | * @buf: buffer to store read data | |
1052 | * @page: page number to read | |
52ff49df | 1053 | * |
7854d3f7 | 1054 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1055 | */ |
1056 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1057 | uint8_t *buf, int page) |
8593fbc6 TG |
1058 | { |
1059 | chip->read_buf(mtd, buf, mtd->writesize); | |
1060 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1061 | return 0; | |
1062 | } | |
1063 | ||
52ff49df | 1064 | /** |
7854d3f7 | 1065 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1066 | * @mtd: mtd info structure |
1067 | * @chip: nand chip info structure | |
1068 | * @buf: buffer to store read data | |
1069 | * @page: page number to read | |
52ff49df DB |
1070 | * |
1071 | * We need a special oob layout and handling even when OOB isn't used. | |
1072 | */ | |
7351d3a5 FF |
1073 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1074 | struct nand_chip *chip, | |
1075 | uint8_t *buf, int page) | |
52ff49df DB |
1076 | { |
1077 | int eccsize = chip->ecc.size; | |
1078 | int eccbytes = chip->ecc.bytes; | |
1079 | uint8_t *oob = chip->oob_poi; | |
1080 | int steps, size; | |
1081 | ||
1082 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1083 | chip->read_buf(mtd, buf, eccsize); | |
1084 | buf += eccsize; | |
1085 | ||
1086 | if (chip->ecc.prepad) { | |
1087 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1088 | oob += chip->ecc.prepad; | |
1089 | } | |
1090 | ||
1091 | chip->read_buf(mtd, oob, eccbytes); | |
1092 | oob += eccbytes; | |
1093 | ||
1094 | if (chip->ecc.postpad) { | |
1095 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1096 | oob += chip->ecc.postpad; | |
1097 | } | |
1098 | } | |
1099 | ||
1100 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1101 | if (size) | |
1102 | chip->read_buf(mtd, oob, size); | |
1103 | ||
1104 | return 0; | |
1105 | } | |
1106 | ||
1da177e4 | 1107 | /** |
7854d3f7 | 1108 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1109 | * @mtd: mtd info structure |
1110 | * @chip: nand chip info structure | |
1111 | * @buf: buffer to store read data | |
1112 | * @page: page number to read | |
068e3c0a | 1113 | */ |
f5bbdacc | 1114 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1115 | uint8_t *buf, int page) |
1da177e4 | 1116 | { |
f5bbdacc TG |
1117 | int i, eccsize = chip->ecc.size; |
1118 | int eccbytes = chip->ecc.bytes; | |
1119 | int eccsteps = chip->ecc.steps; | |
1120 | uint8_t *p = buf; | |
4bf63fcb DW |
1121 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1122 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1123 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc | 1124 | |
46a8cf2d | 1125 | chip->ecc.read_page_raw(mtd, chip, buf, page); |
f5bbdacc TG |
1126 | |
1127 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1128 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1129 | ||
1130 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1131 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1132 | |
1133 | eccsteps = chip->ecc.steps; | |
1134 | p = buf; | |
1135 | ||
1136 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1137 | int stat; | |
1138 | ||
1139 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
c32b8dcc | 1140 | if (stat < 0) |
f5bbdacc TG |
1141 | mtd->ecc_stats.failed++; |
1142 | else | |
1143 | mtd->ecc_stats.corrected += stat; | |
1144 | } | |
1145 | return 0; | |
22c60f5f | 1146 | } |
1da177e4 | 1147 | |
3d459559 | 1148 | /** |
7854d3f7 | 1149 | * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function |
8b6e50c9 BN |
1150 | * @mtd: mtd info structure |
1151 | * @chip: nand chip info structure | |
1152 | * @data_offs: offset of requested data within the page | |
1153 | * @readlen: data length | |
1154 | * @bufpoi: buffer to store read data | |
3d459559 | 1155 | */ |
7351d3a5 FF |
1156 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
1157 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) | |
3d459559 AK |
1158 | { |
1159 | int start_step, end_step, num_steps; | |
1160 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1161 | uint8_t *p; | |
1162 | int data_col_addr, i, gaps = 0; | |
1163 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1164 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
7351d3a5 | 1165 | int index = 0; |
3d459559 | 1166 | |
7854d3f7 | 1167 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1168 | start_step = data_offs / chip->ecc.size; |
1169 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1170 | num_steps = end_step - start_step + 1; | |
1171 | ||
8b6e50c9 | 1172 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1173 | datafrag_len = num_steps * chip->ecc.size; |
1174 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1175 | ||
1176 | data_col_addr = start_step * chip->ecc.size; | |
1177 | /* If we read not a page aligned data */ | |
1178 | if (data_col_addr != 0) | |
1179 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1180 | ||
1181 | p = bufpoi + data_col_addr; | |
1182 | chip->read_buf(mtd, p, datafrag_len); | |
1183 | ||
8b6e50c9 | 1184 | /* Calculate ECC */ |
3d459559 AK |
1185 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1186 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1187 | ||
8b6e50c9 BN |
1188 | /* |
1189 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1190 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1191 | */ |
3d459559 AK |
1192 | for (i = 0; i < eccfrag_len - 1; i++) { |
1193 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1194 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1195 | gaps = 1; | |
1196 | break; | |
1197 | } | |
1198 | } | |
1199 | if (gaps) { | |
1200 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1201 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1202 | } else { | |
8b6e50c9 | 1203 | /* |
7854d3f7 | 1204 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1205 | * about buswidth alignment in read_buf. |
1206 | */ | |
7351d3a5 FF |
1207 | index = start_step * chip->ecc.bytes; |
1208 | ||
1209 | aligned_pos = eccpos[index] & ~(busw - 1); | |
3d459559 | 1210 | aligned_len = eccfrag_len; |
7351d3a5 | 1211 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1212 | aligned_len++; |
7351d3a5 | 1213 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1214 | aligned_len++; |
1215 | ||
7351d3a5 FF |
1216 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1217 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1218 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1219 | } | |
1220 | ||
1221 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1222 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1223 | |
1224 | p = bufpoi + data_col_addr; | |
1225 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1226 | int stat; | |
1227 | ||
7351d3a5 FF |
1228 | stat = chip->ecc.correct(mtd, p, |
1229 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
12c8eb98 | 1230 | if (stat < 0) |
3d459559 AK |
1231 | mtd->ecc_stats.failed++; |
1232 | else | |
1233 | mtd->ecc_stats.corrected += stat; | |
1234 | } | |
1235 | return 0; | |
1236 | } | |
1237 | ||
068e3c0a | 1238 | /** |
7854d3f7 | 1239 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1240 | * @mtd: mtd info structure |
1241 | * @chip: nand chip info structure | |
1242 | * @buf: buffer to store read data | |
1243 | * @page: page number to read | |
068e3c0a | 1244 | * |
7854d3f7 | 1245 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1246 | */ |
f5bbdacc | 1247 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1248 | uint8_t *buf, int page) |
1da177e4 | 1249 | { |
f5bbdacc TG |
1250 | int i, eccsize = chip->ecc.size; |
1251 | int eccbytes = chip->ecc.bytes; | |
1252 | int eccsteps = chip->ecc.steps; | |
1253 | uint8_t *p = buf; | |
4bf63fcb DW |
1254 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1255 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1256 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc TG |
1257 | |
1258 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1259 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1260 | chip->read_buf(mtd, p, eccsize); | |
1261 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1262 | } |
f75e5097 | 1263 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1264 | |
f5bbdacc | 1265 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1266 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1267 | |
f5bbdacc TG |
1268 | eccsteps = chip->ecc.steps; |
1269 | p = buf; | |
61b03bd7 | 1270 | |
f5bbdacc TG |
1271 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1272 | int stat; | |
1da177e4 | 1273 | |
f5bbdacc | 1274 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
c32b8dcc | 1275 | if (stat < 0) |
f5bbdacc TG |
1276 | mtd->ecc_stats.failed++; |
1277 | else | |
1278 | mtd->ecc_stats.corrected += stat; | |
1279 | } | |
1280 | return 0; | |
1281 | } | |
1da177e4 | 1282 | |
6e0cb135 | 1283 | /** |
7854d3f7 | 1284 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1285 | * @mtd: mtd info structure |
1286 | * @chip: nand chip info structure | |
1287 | * @buf: buffer to store read data | |
1288 | * @page: page number to read | |
6e0cb135 | 1289 | * |
8b6e50c9 BN |
1290 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1291 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1292 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1293 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1294 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1295 | */ |
1296 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1297 | struct nand_chip *chip, uint8_t *buf, int page) | |
1298 | { | |
1299 | int i, eccsize = chip->ecc.size; | |
1300 | int eccbytes = chip->ecc.bytes; | |
1301 | int eccsteps = chip->ecc.steps; | |
1302 | uint8_t *p = buf; | |
1303 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1304 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1305 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1306 | ||
1307 | /* Read the OOB area first */ | |
1308 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1309 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1310 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1311 | ||
1312 | for (i = 0; i < chip->ecc.total; i++) | |
1313 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1314 | ||
1315 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1316 | int stat; | |
1317 | ||
1318 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1319 | chip->read_buf(mtd, p, eccsize); | |
1320 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1321 | ||
1322 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
1323 | if (stat < 0) | |
1324 | mtd->ecc_stats.failed++; | |
1325 | else | |
1326 | mtd->ecc_stats.corrected += stat; | |
1327 | } | |
1328 | return 0; | |
1329 | } | |
1330 | ||
f5bbdacc | 1331 | /** |
7854d3f7 | 1332 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1333 | * @mtd: mtd info structure |
1334 | * @chip: nand chip info structure | |
1335 | * @buf: buffer to store read data | |
1336 | * @page: page number to read | |
f5bbdacc | 1337 | * |
8b6e50c9 BN |
1338 | * The hw generator calculates the error syndrome automatically. Therefore we |
1339 | * need a special oob layout and handling. | |
f5bbdacc TG |
1340 | */ |
1341 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1342 | uint8_t *buf, int page) |
f5bbdacc TG |
1343 | { |
1344 | int i, eccsize = chip->ecc.size; | |
1345 | int eccbytes = chip->ecc.bytes; | |
1346 | int eccsteps = chip->ecc.steps; | |
1347 | uint8_t *p = buf; | |
f75e5097 | 1348 | uint8_t *oob = chip->oob_poi; |
1da177e4 | 1349 | |
f5bbdacc TG |
1350 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1351 | int stat; | |
61b03bd7 | 1352 | |
f5bbdacc TG |
1353 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1354 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1355 | |
f5bbdacc TG |
1356 | if (chip->ecc.prepad) { |
1357 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1358 | oob += chip->ecc.prepad; | |
1359 | } | |
1da177e4 | 1360 | |
f5bbdacc TG |
1361 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1362 | chip->read_buf(mtd, oob, eccbytes); | |
1363 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1364 | |
c32b8dcc | 1365 | if (stat < 0) |
f5bbdacc | 1366 | mtd->ecc_stats.failed++; |
61b03bd7 | 1367 | else |
f5bbdacc | 1368 | mtd->ecc_stats.corrected += stat; |
61b03bd7 | 1369 | |
f5bbdacc | 1370 | oob += eccbytes; |
1da177e4 | 1371 | |
f5bbdacc TG |
1372 | if (chip->ecc.postpad) { |
1373 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1374 | oob += chip->ecc.postpad; | |
61b03bd7 | 1375 | } |
f5bbdacc | 1376 | } |
1da177e4 | 1377 | |
f5bbdacc | 1378 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1379 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1380 | if (i) |
1381 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1382 | |
f5bbdacc TG |
1383 | return 0; |
1384 | } | |
1da177e4 | 1385 | |
f5bbdacc | 1386 | /** |
7854d3f7 | 1387 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1388 | * @chip: nand chip structure |
1389 | * @oob: oob destination address | |
1390 | * @ops: oob ops structure | |
1391 | * @len: size of oob to transfer | |
8593fbc6 TG |
1392 | */ |
1393 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1394 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1395 | { |
f8ac0414 | 1396 | switch (ops->mode) { |
8593fbc6 | 1397 | |
0612b9dd BN |
1398 | case MTD_OPS_PLACE_OOB: |
1399 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1400 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1401 | return oob + len; | |
1402 | ||
0612b9dd | 1403 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1404 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1405 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1406 | size_t bytes = 0; | |
8593fbc6 | 1407 | |
f8ac0414 | 1408 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1409 | /* Read request not from offset 0? */ |
7bc3312b TG |
1410 | if (unlikely(roffs)) { |
1411 | if (roffs >= free->length) { | |
1412 | roffs -= free->length; | |
1413 | continue; | |
1414 | } | |
1415 | boffs = free->offset + roffs; | |
1416 | bytes = min_t(size_t, len, | |
1417 | (free->length - roffs)); | |
1418 | roffs = 0; | |
1419 | } else { | |
1420 | bytes = min_t(size_t, len, free->length); | |
1421 | boffs = free->offset; | |
1422 | } | |
1423 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1424 | oob += bytes; |
1425 | } | |
1426 | return oob; | |
1427 | } | |
1428 | default: | |
1429 | BUG(); | |
1430 | } | |
1431 | return NULL; | |
1432 | } | |
1433 | ||
1434 | /** | |
7854d3f7 | 1435 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1436 | * @mtd: MTD device structure |
1437 | * @from: offset to read from | |
1438 | * @ops: oob ops structure | |
f5bbdacc TG |
1439 | * |
1440 | * Internal function. Called with chip held. | |
1441 | */ | |
8593fbc6 TG |
1442 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1443 | struct mtd_oob_ops *ops) | |
f5bbdacc TG |
1444 | { |
1445 | int chipnr, page, realpage, col, bytes, aligned; | |
1446 | struct nand_chip *chip = mtd->priv; | |
1447 | struct mtd_ecc_stats stats; | |
1448 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
1449 | int sndcmd = 1; | |
1450 | int ret = 0; | |
8593fbc6 | 1451 | uint32_t readlen = ops->len; |
7014568b | 1452 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1453 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1454 | mtd->oobavail : mtd->oobsize; |
1455 | ||
8593fbc6 | 1456 | uint8_t *bufpoi, *oob, *buf; |
1da177e4 | 1457 | |
f5bbdacc | 1458 | stats = mtd->ecc_stats; |
1da177e4 | 1459 | |
f5bbdacc TG |
1460 | chipnr = (int)(from >> chip->chip_shift); |
1461 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1462 | |
f5bbdacc TG |
1463 | realpage = (int)(from >> chip->page_shift); |
1464 | page = realpage & chip->pagemask; | |
1da177e4 | 1465 | |
f5bbdacc | 1466 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1467 | |
8593fbc6 TG |
1468 | buf = ops->datbuf; |
1469 | oob = ops->oobbuf; | |
1470 | ||
f8ac0414 | 1471 | while (1) { |
f5bbdacc TG |
1472 | bytes = min(mtd->writesize - col, readlen); |
1473 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1474 | |
8b6e50c9 | 1475 | /* Is the current page in the buffer? */ |
8593fbc6 | 1476 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1477 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1478 | |
f5bbdacc TG |
1479 | if (likely(sndcmd)) { |
1480 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
1481 | sndcmd = 0; | |
1da177e4 | 1482 | } |
1da177e4 | 1483 | |
f5bbdacc | 1484 | /* Now read the page into the buffer */ |
0612b9dd | 1485 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
46a8cf2d SN |
1486 | ret = chip->ecc.read_page_raw(mtd, chip, |
1487 | bufpoi, page); | |
3d459559 | 1488 | else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) |
7351d3a5 FF |
1489 | ret = chip->ecc.read_subpage(mtd, chip, |
1490 | col, bytes, bufpoi); | |
956e944c | 1491 | else |
46a8cf2d SN |
1492 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
1493 | page); | |
6d77b9d0 BN |
1494 | if (ret < 0) { |
1495 | if (!aligned) | |
1496 | /* Invalidate page cache */ | |
1497 | chip->pagebuf = -1; | |
1da177e4 | 1498 | break; |
6d77b9d0 | 1499 | } |
f5bbdacc TG |
1500 | |
1501 | /* Transfer not aligned data */ | |
1502 | if (!aligned) { | |
c1194c79 | 1503 | if (!NAND_SUBPAGE_READ(chip) && !oob && |
6d77b9d0 BN |
1504 | !(mtd->ecc_stats.failed - stats.failed) && |
1505 | (ops->mode != MTD_OPS_RAW)) | |
3d459559 | 1506 | chip->pagebuf = realpage; |
6d77b9d0 BN |
1507 | else |
1508 | /* Invalidate page cache */ | |
1509 | chip->pagebuf = -1; | |
4bf63fcb | 1510 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1511 | } |
1512 | ||
8593fbc6 TG |
1513 | buf += bytes; |
1514 | ||
1515 | if (unlikely(oob)) { | |
9aca334e | 1516 | |
b64d39d8 ML |
1517 | int toread = min(oobreadlen, max_oobsize); |
1518 | ||
1519 | if (toread) { | |
1520 | oob = nand_transfer_oob(chip, | |
1521 | oob, ops, toread); | |
1522 | oobreadlen -= toread; | |
1523 | } | |
8593fbc6 TG |
1524 | } |
1525 | ||
f5bbdacc TG |
1526 | if (!(chip->options & NAND_NO_READRDY)) { |
1527 | /* | |
1528 | * Apply delay or wait for ready/busy pin. Do | |
1529 | * this before the AUTOINCR check, so no | |
1530 | * problems arise if a chip which does auto | |
1531 | * increment is marked as NOAUTOINCR by the | |
1532 | * board driver. | |
1533 | */ | |
1534 | if (!chip->dev_ready) | |
1535 | udelay(chip->chip_delay); | |
1536 | else | |
1537 | nand_wait_ready(mtd); | |
1da177e4 | 1538 | } |
8593fbc6 | 1539 | } else { |
4bf63fcb | 1540 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 TG |
1541 | buf += bytes; |
1542 | } | |
1da177e4 | 1543 | |
f5bbdacc | 1544 | readlen -= bytes; |
61b03bd7 | 1545 | |
f5bbdacc | 1546 | if (!readlen) |
61b03bd7 | 1547 | break; |
1da177e4 | 1548 | |
8b6e50c9 | 1549 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1550 | col = 0; |
1551 | /* Increment page address */ | |
1552 | realpage++; | |
1553 | ||
ace4dfee | 1554 | page = realpage & chip->pagemask; |
1da177e4 LT |
1555 | /* Check, if we cross a chip boundary */ |
1556 | if (!page) { | |
1557 | chipnr++; | |
ace4dfee TG |
1558 | chip->select_chip(mtd, -1); |
1559 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1560 | } |
f5bbdacc | 1561 | |
8b6e50c9 BN |
1562 | /* |
1563 | * Check, if the chip supports auto page increment or if we | |
1564 | * have hit a block boundary. | |
e0c7d767 | 1565 | */ |
f5bbdacc | 1566 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
61b03bd7 | 1567 | sndcmd = 1; |
1da177e4 LT |
1568 | } |
1569 | ||
8593fbc6 | 1570 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1571 | if (oob) |
1572 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1573 | |
f5bbdacc TG |
1574 | if (ret) |
1575 | return ret; | |
1576 | ||
9a1fcdfd TG |
1577 | if (mtd->ecc_stats.failed - stats.failed) |
1578 | return -EBADMSG; | |
1579 | ||
1580 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
f5bbdacc TG |
1581 | } |
1582 | ||
1583 | /** | |
25985edc | 1584 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1585 | * @mtd: MTD device structure |
1586 | * @from: offset to read from | |
1587 | * @len: number of bytes to read | |
1588 | * @retlen: pointer to variable to store the number of read bytes | |
1589 | * @buf: the databuffer to put data | |
f5bbdacc | 1590 | * |
8b6e50c9 | 1591 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1592 | */ |
1593 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1594 | size_t *retlen, uint8_t *buf) | |
1595 | { | |
8593fbc6 | 1596 | struct nand_chip *chip = mtd->priv; |
4a89ff88 | 1597 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1598 | int ret; |
1599 | ||
f5bbdacc TG |
1600 | /* Do not allow reads past end of device */ |
1601 | if ((from + len) > mtd->size) | |
1602 | return -EINVAL; | |
1603 | if (!len) | |
1604 | return 0; | |
1605 | ||
8593fbc6 | 1606 | nand_get_device(chip, mtd, FL_READING); |
f5bbdacc | 1607 | |
4a89ff88 BN |
1608 | ops.len = len; |
1609 | ops.datbuf = buf; | |
1610 | ops.oobbuf = NULL; | |
23b1a99b | 1611 | ops.mode = 0; |
8593fbc6 | 1612 | |
4a89ff88 | 1613 | ret = nand_do_read_ops(mtd, from, &ops); |
f5bbdacc | 1614 | |
4a89ff88 | 1615 | *retlen = ops.retlen; |
7fd5aecc | 1616 | |
f5bbdacc TG |
1617 | nand_release_device(mtd); |
1618 | ||
1619 | return ret; | |
1da177e4 LT |
1620 | } |
1621 | ||
7bc3312b | 1622 | /** |
7854d3f7 | 1623 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1624 | * @mtd: mtd info structure |
1625 | * @chip: nand chip info structure | |
1626 | * @page: page number to read | |
1627 | * @sndcmd: flag whether to issue read command or not | |
7bc3312b TG |
1628 | */ |
1629 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1630 | int page, int sndcmd) | |
1631 | { | |
1632 | if (sndcmd) { | |
1633 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1634 | sndcmd = 0; | |
1635 | } | |
1636 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1637 | return sndcmd; | |
1638 | } | |
1639 | ||
1640 | /** | |
7854d3f7 | 1641 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1642 | * with syndromes |
8b6e50c9 BN |
1643 | * @mtd: mtd info structure |
1644 | * @chip: nand chip info structure | |
1645 | * @page: page number to read | |
1646 | * @sndcmd: flag whether to issue read command or not | |
7bc3312b TG |
1647 | */ |
1648 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1649 | int page, int sndcmd) | |
1650 | { | |
1651 | uint8_t *buf = chip->oob_poi; | |
1652 | int length = mtd->oobsize; | |
1653 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1654 | int eccsize = chip->ecc.size; | |
1655 | uint8_t *bufpoi = buf; | |
1656 | int i, toread, sndrnd = 0, pos; | |
1657 | ||
1658 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1659 | for (i = 0; i < chip->ecc.steps; i++) { | |
1660 | if (sndrnd) { | |
1661 | pos = eccsize + i * (eccsize + chunk); | |
1662 | if (mtd->writesize > 512) | |
1663 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1664 | else | |
1665 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1666 | } else | |
1667 | sndrnd = 1; | |
1668 | toread = min_t(int, length, chunk); | |
1669 | chip->read_buf(mtd, bufpoi, toread); | |
1670 | bufpoi += toread; | |
1671 | length -= toread; | |
1672 | } | |
1673 | if (length > 0) | |
1674 | chip->read_buf(mtd, bufpoi, length); | |
1675 | ||
1676 | return 1; | |
1677 | } | |
1678 | ||
1679 | /** | |
7854d3f7 | 1680 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1681 | * @mtd: mtd info structure |
1682 | * @chip: nand chip info structure | |
1683 | * @page: page number to write | |
7bc3312b TG |
1684 | */ |
1685 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1686 | int page) | |
1687 | { | |
1688 | int status = 0; | |
1689 | const uint8_t *buf = chip->oob_poi; | |
1690 | int length = mtd->oobsize; | |
1691 | ||
1692 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1693 | chip->write_buf(mtd, buf, length); | |
1694 | /* Send command to program the OOB data */ | |
1695 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1696 | ||
1697 | status = chip->waitfunc(mtd, chip); | |
1698 | ||
0d420f9d | 1699 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1700 | } |
1701 | ||
1702 | /** | |
7854d3f7 | 1703 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1704 | * with syndrome - only for large page flash |
1705 | * @mtd: mtd info structure | |
1706 | * @chip: nand chip info structure | |
1707 | * @page: page number to write | |
7bc3312b TG |
1708 | */ |
1709 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1710 | struct nand_chip *chip, int page) | |
1711 | { | |
1712 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1713 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1714 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1715 | const uint8_t *bufpoi = chip->oob_poi; | |
1716 | ||
1717 | /* | |
1718 | * data-ecc-data-ecc ... ecc-oob | |
1719 | * or | |
1720 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1721 | */ | |
1722 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1723 | pos = steps * (eccsize + chunk); | |
1724 | steps = 0; | |
1725 | } else | |
8b0036ee | 1726 | pos = eccsize; |
7bc3312b TG |
1727 | |
1728 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1729 | for (i = 0; i < steps; i++) { | |
1730 | if (sndcmd) { | |
1731 | if (mtd->writesize <= 512) { | |
1732 | uint32_t fill = 0xFFFFFFFF; | |
1733 | ||
1734 | len = eccsize; | |
1735 | while (len > 0) { | |
1736 | int num = min_t(int, len, 4); | |
1737 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1738 | num); | |
1739 | len -= num; | |
1740 | } | |
1741 | } else { | |
1742 | pos = eccsize + i * (eccsize + chunk); | |
1743 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1744 | } | |
1745 | } else | |
1746 | sndcmd = 1; | |
1747 | len = min_t(int, length, chunk); | |
1748 | chip->write_buf(mtd, bufpoi, len); | |
1749 | bufpoi += len; | |
1750 | length -= len; | |
1751 | } | |
1752 | if (length > 0) | |
1753 | chip->write_buf(mtd, bufpoi, length); | |
1754 | ||
1755 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1756 | status = chip->waitfunc(mtd, chip); | |
1757 | ||
1758 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1759 | } | |
1760 | ||
1da177e4 | 1761 | /** |
7854d3f7 | 1762 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
1763 | * @mtd: MTD device structure |
1764 | * @from: offset to read from | |
1765 | * @ops: oob operations description structure | |
1da177e4 | 1766 | * |
8b6e50c9 | 1767 | * NAND read out-of-band data from the spare area. |
1da177e4 | 1768 | */ |
8593fbc6 TG |
1769 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1770 | struct mtd_oob_ops *ops) | |
1da177e4 | 1771 | { |
7bc3312b | 1772 | int page, realpage, chipnr, sndcmd = 1; |
ace4dfee | 1773 | struct nand_chip *chip = mtd->priv; |
041e4575 | 1774 | struct mtd_ecc_stats stats; |
7314e9e7 | 1775 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
7014568b VW |
1776 | int readlen = ops->ooblen; |
1777 | int len; | |
7bc3312b | 1778 | uint8_t *buf = ops->oobbuf; |
61b03bd7 | 1779 | |
289c0522 | 1780 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 1781 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 1782 | |
041e4575 BN |
1783 | stats = mtd->ecc_stats; |
1784 | ||
0612b9dd | 1785 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 1786 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1787 | else |
1788 | len = mtd->oobsize; | |
1789 | ||
1790 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
1791 | pr_debug("%s: attempt to start read outside oob\n", |
1792 | __func__); | |
03736155 AH |
1793 | return -EINVAL; |
1794 | } | |
1795 | ||
1796 | /* Do not allow reads past end of device */ | |
1797 | if (unlikely(from >= mtd->size || | |
1798 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1799 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
1800 | pr_debug("%s: attempt to read beyond end of device\n", |
1801 | __func__); | |
03736155 AH |
1802 | return -EINVAL; |
1803 | } | |
7014568b | 1804 | |
7314e9e7 | 1805 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1806 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1807 | |
7314e9e7 TG |
1808 | /* Shift to get page */ |
1809 | realpage = (int)(from >> chip->page_shift); | |
1810 | page = realpage & chip->pagemask; | |
1da177e4 | 1811 | |
f8ac0414 | 1812 | while (1) { |
0612b9dd | 1813 | if (ops->mode == MTD_OPS_RAW) |
c46f6483 BN |
1814 | sndcmd = chip->ecc.read_oob_raw(mtd, chip, page, sndcmd); |
1815 | else | |
1816 | sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); | |
7014568b VW |
1817 | |
1818 | len = min(len, readlen); | |
1819 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1820 | |
7314e9e7 TG |
1821 | if (!(chip->options & NAND_NO_READRDY)) { |
1822 | /* | |
1823 | * Apply delay or wait for ready/busy pin. Do this | |
1824 | * before the AUTOINCR check, so no problems arise if a | |
1825 | * chip which does auto increment is marked as | |
1826 | * NOAUTOINCR by the board driver. | |
19870da7 | 1827 | */ |
ace4dfee TG |
1828 | if (!chip->dev_ready) |
1829 | udelay(chip->chip_delay); | |
19870da7 TG |
1830 | else |
1831 | nand_wait_ready(mtd); | |
7314e9e7 | 1832 | } |
19870da7 | 1833 | |
7014568b | 1834 | readlen -= len; |
0d420f9d SZ |
1835 | if (!readlen) |
1836 | break; | |
1837 | ||
7314e9e7 TG |
1838 | /* Increment page address */ |
1839 | realpage++; | |
1840 | ||
1841 | page = realpage & chip->pagemask; | |
1842 | /* Check, if we cross a chip boundary */ | |
1843 | if (!page) { | |
1844 | chipnr++; | |
1845 | chip->select_chip(mtd, -1); | |
1846 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1847 | } |
7314e9e7 | 1848 | |
8b6e50c9 BN |
1849 | /* |
1850 | * Check, if the chip supports auto page increment or if we | |
1851 | * have hit a block boundary. | |
7314e9e7 TG |
1852 | */ |
1853 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) | |
1854 | sndcmd = 1; | |
1da177e4 LT |
1855 | } |
1856 | ||
7014568b | 1857 | ops->oobretlen = ops->ooblen; |
041e4575 BN |
1858 | |
1859 | if (mtd->ecc_stats.failed - stats.failed) | |
1860 | return -EBADMSG; | |
1861 | ||
1862 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
1863 | } |
1864 | ||
1865 | /** | |
8593fbc6 | 1866 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
1867 | * @mtd: MTD device structure |
1868 | * @from: offset to read from | |
1869 | * @ops: oob operation description structure | |
1da177e4 | 1870 | * |
8b6e50c9 | 1871 | * NAND read data and/or out-of-band data. |
1da177e4 | 1872 | */ |
8593fbc6 TG |
1873 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1874 | struct mtd_oob_ops *ops) | |
1da177e4 | 1875 | { |
ace4dfee | 1876 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1877 | int ret = -ENOTSUPP; |
1878 | ||
1879 | ops->retlen = 0; | |
1da177e4 LT |
1880 | |
1881 | /* Do not allow reads past end of device */ | |
7014568b | 1882 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
1883 | pr_debug("%s: attempt to read beyond end of device\n", |
1884 | __func__); | |
1da177e4 LT |
1885 | return -EINVAL; |
1886 | } | |
1887 | ||
ace4dfee | 1888 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1889 | |
f8ac0414 | 1890 | switch (ops->mode) { |
0612b9dd BN |
1891 | case MTD_OPS_PLACE_OOB: |
1892 | case MTD_OPS_AUTO_OOB: | |
1893 | case MTD_OPS_RAW: | |
8593fbc6 | 1894 | break; |
1da177e4 | 1895 | |
8593fbc6 TG |
1896 | default: |
1897 | goto out; | |
1898 | } | |
1da177e4 | 1899 | |
8593fbc6 TG |
1900 | if (!ops->datbuf) |
1901 | ret = nand_do_read_oob(mtd, from, ops); | |
1902 | else | |
1903 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1904 | |
7351d3a5 | 1905 | out: |
8593fbc6 TG |
1906 | nand_release_device(mtd); |
1907 | return ret; | |
1908 | } | |
61b03bd7 | 1909 | |
1da177e4 | 1910 | |
8593fbc6 | 1911 | /** |
7854d3f7 | 1912 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
1913 | * @mtd: mtd info structure |
1914 | * @chip: nand chip info structure | |
1915 | * @buf: data buffer | |
52ff49df | 1916 | * |
7854d3f7 | 1917 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1918 | */ |
1919 | static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1920 | const uint8_t *buf) | |
1921 | { | |
1922 | chip->write_buf(mtd, buf, mtd->writesize); | |
1923 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1da177e4 LT |
1924 | } |
1925 | ||
52ff49df | 1926 | /** |
7854d3f7 | 1927 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
1928 | * @mtd: mtd info structure |
1929 | * @chip: nand chip info structure | |
1930 | * @buf: data buffer | |
52ff49df DB |
1931 | * |
1932 | * We need a special oob layout and handling even when ECC isn't checked. | |
1933 | */ | |
7351d3a5 FF |
1934 | static void nand_write_page_raw_syndrome(struct mtd_info *mtd, |
1935 | struct nand_chip *chip, | |
1936 | const uint8_t *buf) | |
52ff49df DB |
1937 | { |
1938 | int eccsize = chip->ecc.size; | |
1939 | int eccbytes = chip->ecc.bytes; | |
1940 | uint8_t *oob = chip->oob_poi; | |
1941 | int steps, size; | |
1942 | ||
1943 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1944 | chip->write_buf(mtd, buf, eccsize); | |
1945 | buf += eccsize; | |
1946 | ||
1947 | if (chip->ecc.prepad) { | |
1948 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1949 | oob += chip->ecc.prepad; | |
1950 | } | |
1951 | ||
1952 | chip->read_buf(mtd, oob, eccbytes); | |
1953 | oob += eccbytes; | |
1954 | ||
1955 | if (chip->ecc.postpad) { | |
1956 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1957 | oob += chip->ecc.postpad; | |
1958 | } | |
1959 | } | |
1960 | ||
1961 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1962 | if (size) | |
1963 | chip->write_buf(mtd, oob, size); | |
1964 | } | |
9223a456 | 1965 | /** |
7854d3f7 | 1966 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
1967 | * @mtd: mtd info structure |
1968 | * @chip: nand chip info structure | |
1969 | * @buf: data buffer | |
9223a456 | 1970 | */ |
f75e5097 TG |
1971 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1972 | const uint8_t *buf) | |
9223a456 | 1973 | { |
f75e5097 TG |
1974 | int i, eccsize = chip->ecc.size; |
1975 | int eccbytes = chip->ecc.bytes; | |
1976 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1977 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1978 | const uint8_t *p = buf; |
8b099a39 | 1979 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1980 | |
7854d3f7 | 1981 | /* Software ECC calculation */ |
8593fbc6 TG |
1982 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
1983 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1984 | |
8593fbc6 TG |
1985 | for (i = 0; i < chip->ecc.total; i++) |
1986 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1987 | |
90424de8 | 1988 | chip->ecc.write_page_raw(mtd, chip, buf); |
f75e5097 | 1989 | } |
9223a456 | 1990 | |
f75e5097 | 1991 | /** |
7854d3f7 | 1992 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
1993 | * @mtd: mtd info structure |
1994 | * @chip: nand chip info structure | |
1995 | * @buf: data buffer | |
f75e5097 TG |
1996 | */ |
1997 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1998 | const uint8_t *buf) | |
1999 | { | |
2000 | int i, eccsize = chip->ecc.size; | |
2001 | int eccbytes = chip->ecc.bytes; | |
2002 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2003 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2004 | const uint8_t *p = buf; |
8b099a39 | 2005 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2006 | |
f75e5097 TG |
2007 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2008 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2009 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2010 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2011 | } |
2012 | ||
f75e5097 TG |
2013 | for (i = 0; i < chip->ecc.total; i++) |
2014 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2015 | ||
2016 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
9223a456 TG |
2017 | } |
2018 | ||
61b03bd7 | 2019 | /** |
7854d3f7 | 2020 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2021 | * @mtd: mtd info structure |
2022 | * @chip: nand chip info structure | |
2023 | * @buf: data buffer | |
1da177e4 | 2024 | * |
8b6e50c9 BN |
2025 | * The hw generator calculates the error syndrome automatically. Therefore we |
2026 | * need a special oob layout and handling. | |
f75e5097 TG |
2027 | */ |
2028 | static void nand_write_page_syndrome(struct mtd_info *mtd, | |
2029 | struct nand_chip *chip, const uint8_t *buf) | |
1da177e4 | 2030 | { |
f75e5097 TG |
2031 | int i, eccsize = chip->ecc.size; |
2032 | int eccbytes = chip->ecc.bytes; | |
2033 | int eccsteps = chip->ecc.steps; | |
2034 | const uint8_t *p = buf; | |
2035 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2036 | |
f75e5097 | 2037 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2038 | |
f75e5097 TG |
2039 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2040 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2041 | |
f75e5097 TG |
2042 | if (chip->ecc.prepad) { |
2043 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2044 | oob += chip->ecc.prepad; | |
2045 | } | |
2046 | ||
2047 | chip->ecc.calculate(mtd, p, oob); | |
2048 | chip->write_buf(mtd, oob, eccbytes); | |
2049 | oob += eccbytes; | |
2050 | ||
2051 | if (chip->ecc.postpad) { | |
2052 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2053 | oob += chip->ecc.postpad; | |
1da177e4 | 2054 | } |
1da177e4 | 2055 | } |
f75e5097 TG |
2056 | |
2057 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2058 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2059 | if (i) |
2060 | chip->write_buf(mtd, oob, i); | |
2061 | } | |
2062 | ||
2063 | /** | |
956e944c | 2064 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2065 | * @mtd: MTD device structure |
2066 | * @chip: NAND chip descriptor | |
2067 | * @buf: the data to write | |
2068 | * @page: page number to write | |
2069 | * @cached: cached programming | |
2070 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2071 | */ |
2072 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
956e944c | 2073 | const uint8_t *buf, int page, int cached, int raw) |
f75e5097 TG |
2074 | { |
2075 | int status; | |
2076 | ||
2077 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2078 | ||
956e944c DW |
2079 | if (unlikely(raw)) |
2080 | chip->ecc.write_page_raw(mtd, chip, buf); | |
2081 | else | |
2082 | chip->ecc.write_page(mtd, chip, buf); | |
f75e5097 TG |
2083 | |
2084 | /* | |
7854d3f7 | 2085 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2086 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2087 | */ |
2088 | cached = 0; | |
2089 | ||
2090 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
2091 | ||
2092 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2093 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2094 | /* |
2095 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2096 | * available. |
f75e5097 TG |
2097 | */ |
2098 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2099 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2100 | page); | |
2101 | ||
2102 | if (status & NAND_STATUS_FAIL) | |
2103 | return -EIO; | |
2104 | } else { | |
2105 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2106 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2107 | } |
2108 | ||
2109 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
2110 | /* Send command to read back the data */ | |
2111 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
2112 | ||
2113 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
2114 | return -EIO; | |
2115 | #endif | |
2116 | return 0; | |
1da177e4 LT |
2117 | } |
2118 | ||
8593fbc6 | 2119 | /** |
7854d3f7 | 2120 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2121 | * @mtd: MTD device structure |
8b6e50c9 BN |
2122 | * @oob: oob data buffer |
2123 | * @len: oob data write length | |
2124 | * @ops: oob ops structure | |
8593fbc6 | 2125 | */ |
f722013e TAA |
2126 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2127 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2128 | { |
f722013e TAA |
2129 | struct nand_chip *chip = mtd->priv; |
2130 | ||
2131 | /* | |
2132 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2133 | * data from a previous OOB read. | |
2134 | */ | |
2135 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2136 | ||
f8ac0414 | 2137 | switch (ops->mode) { |
8593fbc6 | 2138 | |
0612b9dd BN |
2139 | case MTD_OPS_PLACE_OOB: |
2140 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2141 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2142 | return oob + len; | |
2143 | ||
0612b9dd | 2144 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2145 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2146 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2147 | size_t bytes = 0; | |
8593fbc6 | 2148 | |
f8ac0414 | 2149 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2150 | /* Write request not from offset 0? */ |
7bc3312b TG |
2151 | if (unlikely(woffs)) { |
2152 | if (woffs >= free->length) { | |
2153 | woffs -= free->length; | |
2154 | continue; | |
2155 | } | |
2156 | boffs = free->offset + woffs; | |
2157 | bytes = min_t(size_t, len, | |
2158 | (free->length - woffs)); | |
2159 | woffs = 0; | |
2160 | } else { | |
2161 | bytes = min_t(size_t, len, free->length); | |
2162 | boffs = free->offset; | |
2163 | } | |
8b0036ee | 2164 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2165 | oob += bytes; |
2166 | } | |
2167 | return oob; | |
2168 | } | |
2169 | default: | |
2170 | BUG(); | |
2171 | } | |
2172 | return NULL; | |
2173 | } | |
2174 | ||
f8ac0414 | 2175 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2176 | |
2177 | /** | |
7854d3f7 | 2178 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2179 | * @mtd: MTD device structure |
2180 | * @to: offset to write to | |
2181 | * @ops: oob operations description structure | |
1da177e4 | 2182 | * |
8b6e50c9 | 2183 | * NAND write with ECC. |
1da177e4 | 2184 | */ |
8593fbc6 TG |
2185 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2186 | struct mtd_oob_ops *ops) | |
1da177e4 | 2187 | { |
29072b96 | 2188 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2189 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2190 | uint32_t writelen = ops->len; |
782ce79a ML |
2191 | |
2192 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2193 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2194 | mtd->oobavail : mtd->oobsize; |
2195 | ||
8593fbc6 TG |
2196 | uint8_t *oob = ops->oobbuf; |
2197 | uint8_t *buf = ops->datbuf; | |
29072b96 | 2198 | int ret, subpage; |
1da177e4 | 2199 | |
8593fbc6 | 2200 | ops->retlen = 0; |
29072b96 TG |
2201 | if (!writelen) |
2202 | return 0; | |
1da177e4 | 2203 | |
8b6e50c9 | 2204 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2205 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2206 | pr_notice("%s: attempt to write non page aligned data\n", |
2207 | __func__); | |
1da177e4 LT |
2208 | return -EINVAL; |
2209 | } | |
2210 | ||
29072b96 TG |
2211 | column = to & (mtd->writesize - 1); |
2212 | subpage = column || (writelen & (mtd->writesize - 1)); | |
2213 | ||
2214 | if (subpage && oob) | |
2215 | return -EINVAL; | |
1da177e4 | 2216 | |
6a930961 TG |
2217 | chipnr = (int)(to >> chip->chip_shift); |
2218 | chip->select_chip(mtd, chipnr); | |
2219 | ||
1da177e4 LT |
2220 | /* Check, if it is write protected */ |
2221 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2222 | return -EIO; |
1da177e4 | 2223 | |
f75e5097 TG |
2224 | realpage = (int)(to >> chip->page_shift); |
2225 | page = realpage & chip->pagemask; | |
2226 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2227 | ||
2228 | /* Invalidate the page cache, when we write to the cached page */ | |
2229 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2230 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2231 | chip->pagebuf = -1; |
61b03bd7 | 2232 | |
782ce79a | 2233 | /* Don't allow multipage oob writes with offset */ |
cdcf12b2 | 2234 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) |
782ce79a ML |
2235 | return -EINVAL; |
2236 | ||
f8ac0414 | 2237 | while (1) { |
29072b96 | 2238 | int bytes = mtd->writesize; |
f75e5097 | 2239 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2240 | uint8_t *wbuf = buf; |
2241 | ||
8b6e50c9 | 2242 | /* Partial page write? */ |
29072b96 TG |
2243 | if (unlikely(column || writelen < (mtd->writesize - 1))) { |
2244 | cached = 0; | |
2245 | bytes = min_t(int, bytes - column, (int) writelen); | |
2246 | chip->pagebuf = -1; | |
2247 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2248 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2249 | wbuf = chip->buffers->databuf; | |
2250 | } | |
1da177e4 | 2251 | |
782ce79a ML |
2252 | if (unlikely(oob)) { |
2253 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2254 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2255 | oobwritelen -= len; |
f722013e TAA |
2256 | } else { |
2257 | /* We still need to erase leftover OOB data */ | |
2258 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2259 | } |
8593fbc6 | 2260 | |
29072b96 | 2261 | ret = chip->write_page(mtd, chip, wbuf, page, cached, |
0612b9dd | 2262 | (ops->mode == MTD_OPS_RAW)); |
f75e5097 TG |
2263 | if (ret) |
2264 | break; | |
2265 | ||
2266 | writelen -= bytes; | |
2267 | if (!writelen) | |
2268 | break; | |
2269 | ||
29072b96 | 2270 | column = 0; |
f75e5097 TG |
2271 | buf += bytes; |
2272 | realpage++; | |
2273 | ||
2274 | page = realpage & chip->pagemask; | |
2275 | /* Check, if we cross a chip boundary */ | |
2276 | if (!page) { | |
2277 | chipnr++; | |
2278 | chip->select_chip(mtd, -1); | |
2279 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2280 | } |
2281 | } | |
8593fbc6 | 2282 | |
8593fbc6 | 2283 | ops->retlen = ops->len - writelen; |
7014568b VW |
2284 | if (unlikely(oob)) |
2285 | ops->oobretlen = ops->ooblen; | |
1da177e4 LT |
2286 | return ret; |
2287 | } | |
2288 | ||
2af7c653 SK |
2289 | /** |
2290 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2291 | * @mtd: MTD device structure |
2292 | * @to: offset to write to | |
2293 | * @len: number of bytes to write | |
2294 | * @retlen: pointer to variable to store the number of written bytes | |
2295 | * @buf: the data to write | |
2af7c653 SK |
2296 | * |
2297 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2298 | * may for example be called by mtdoops when writing an oops while in panic. | |
2299 | */ | |
2300 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2301 | size_t *retlen, const uint8_t *buf) | |
2302 | { | |
2303 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2304 | struct mtd_oob_ops ops; |
2af7c653 SK |
2305 | int ret; |
2306 | ||
2307 | /* Do not allow reads past end of device */ | |
2308 | if ((to + len) > mtd->size) | |
2309 | return -EINVAL; | |
2310 | if (!len) | |
2311 | return 0; | |
2312 | ||
8b6e50c9 | 2313 | /* Wait for the device to get ready */ |
2af7c653 SK |
2314 | panic_nand_wait(mtd, chip, 400); |
2315 | ||
8b6e50c9 | 2316 | /* Grab the device */ |
2af7c653 SK |
2317 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2318 | ||
4a89ff88 BN |
2319 | ops.len = len; |
2320 | ops.datbuf = (uint8_t *)buf; | |
2321 | ops.oobbuf = NULL; | |
23b1a99b | 2322 | ops.mode = 0; |
2af7c653 | 2323 | |
4a89ff88 | 2324 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2325 | |
4a89ff88 | 2326 | *retlen = ops.retlen; |
2af7c653 SK |
2327 | return ret; |
2328 | } | |
2329 | ||
f75e5097 | 2330 | /** |
8593fbc6 | 2331 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2332 | * @mtd: MTD device structure |
2333 | * @to: offset to write to | |
2334 | * @len: number of bytes to write | |
2335 | * @retlen: pointer to variable to store the number of written bytes | |
2336 | * @buf: the data to write | |
f75e5097 | 2337 | * |
8b6e50c9 | 2338 | * NAND write with ECC. |
f75e5097 | 2339 | */ |
8593fbc6 TG |
2340 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2341 | size_t *retlen, const uint8_t *buf) | |
f75e5097 TG |
2342 | { |
2343 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2344 | struct mtd_oob_ops ops; |
f75e5097 TG |
2345 | int ret; |
2346 | ||
8593fbc6 TG |
2347 | /* Do not allow reads past end of device */ |
2348 | if ((to + len) > mtd->size) | |
f75e5097 | 2349 | return -EINVAL; |
8593fbc6 TG |
2350 | if (!len) |
2351 | return 0; | |
f75e5097 | 2352 | |
7bc3312b | 2353 | nand_get_device(chip, mtd, FL_WRITING); |
f75e5097 | 2354 | |
4a89ff88 BN |
2355 | ops.len = len; |
2356 | ops.datbuf = (uint8_t *)buf; | |
2357 | ops.oobbuf = NULL; | |
23b1a99b | 2358 | ops.mode = 0; |
f75e5097 | 2359 | |
4a89ff88 | 2360 | ret = nand_do_write_ops(mtd, to, &ops); |
f75e5097 | 2361 | |
4a89ff88 | 2362 | *retlen = ops.retlen; |
7fd5aecc | 2363 | |
f75e5097 | 2364 | nand_release_device(mtd); |
8593fbc6 | 2365 | |
8593fbc6 | 2366 | return ret; |
f75e5097 | 2367 | } |
7314e9e7 | 2368 | |
1da177e4 | 2369 | /** |
8593fbc6 | 2370 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2371 | * @mtd: MTD device structure |
2372 | * @to: offset to write to | |
2373 | * @ops: oob operation description structure | |
1da177e4 | 2374 | * |
8b6e50c9 | 2375 | * NAND write out-of-band. |
1da177e4 | 2376 | */ |
8593fbc6 TG |
2377 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2378 | struct mtd_oob_ops *ops) | |
1da177e4 | 2379 | { |
03736155 | 2380 | int chipnr, page, status, len; |
ace4dfee | 2381 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2382 | |
289c0522 | 2383 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2384 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2385 | |
0612b9dd | 2386 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2387 | len = chip->ecc.layout->oobavail; |
2388 | else | |
2389 | len = mtd->oobsize; | |
2390 | ||
1da177e4 | 2391 | /* Do not allow write past end of page */ |
03736155 | 2392 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2393 | pr_debug("%s: attempt to write past end of page\n", |
2394 | __func__); | |
1da177e4 LT |
2395 | return -EINVAL; |
2396 | } | |
2397 | ||
03736155 | 2398 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2399 | pr_debug("%s: attempt to start write outside oob\n", |
2400 | __func__); | |
03736155 AH |
2401 | return -EINVAL; |
2402 | } | |
2403 | ||
775adc3d | 2404 | /* Do not allow write past end of device */ |
03736155 AH |
2405 | if (unlikely(to >= mtd->size || |
2406 | ops->ooboffs + ops->ooblen > | |
2407 | ((mtd->size >> chip->page_shift) - | |
2408 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2409 | pr_debug("%s: attempt to write beyond end of device\n", |
2410 | __func__); | |
03736155 AH |
2411 | return -EINVAL; |
2412 | } | |
2413 | ||
7314e9e7 | 2414 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2415 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2416 | |
7314e9e7 TG |
2417 | /* Shift to get page */ |
2418 | page = (int)(to >> chip->page_shift); | |
2419 | ||
2420 | /* | |
2421 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2422 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2423 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2424 | * it in the doc2000 driver in August 1999. dwmw2. | |
2425 | */ | |
ace4dfee | 2426 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2427 | |
2428 | /* Check, if it is write protected */ | |
2429 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2430 | return -EROFS; |
61b03bd7 | 2431 | |
1da177e4 | 2432 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2433 | if (page == chip->pagebuf) |
2434 | chip->pagebuf = -1; | |
1da177e4 | 2435 | |
f722013e | 2436 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2437 | |
0612b9dd | 2438 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2439 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2440 | else | |
2441 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2442 | |
7bc3312b TG |
2443 | if (status) |
2444 | return status; | |
1da177e4 | 2445 | |
7014568b | 2446 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2447 | |
7bc3312b | 2448 | return 0; |
8593fbc6 TG |
2449 | } |
2450 | ||
2451 | /** | |
2452 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2453 | * @mtd: MTD device structure |
2454 | * @to: offset to write to | |
2455 | * @ops: oob operation description structure | |
8593fbc6 TG |
2456 | */ |
2457 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2458 | struct mtd_oob_ops *ops) | |
2459 | { | |
8593fbc6 TG |
2460 | struct nand_chip *chip = mtd->priv; |
2461 | int ret = -ENOTSUPP; | |
2462 | ||
2463 | ops->retlen = 0; | |
2464 | ||
2465 | /* Do not allow writes past end of device */ | |
7014568b | 2466 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2467 | pr_debug("%s: attempt to write beyond end of device\n", |
2468 | __func__); | |
8593fbc6 TG |
2469 | return -EINVAL; |
2470 | } | |
2471 | ||
7bc3312b | 2472 | nand_get_device(chip, mtd, FL_WRITING); |
8593fbc6 | 2473 | |
f8ac0414 | 2474 | switch (ops->mode) { |
0612b9dd BN |
2475 | case MTD_OPS_PLACE_OOB: |
2476 | case MTD_OPS_AUTO_OOB: | |
2477 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2478 | break; |
2479 | ||
2480 | default: | |
2481 | goto out; | |
2482 | } | |
2483 | ||
2484 | if (!ops->datbuf) | |
2485 | ret = nand_do_write_oob(mtd, to, ops); | |
2486 | else | |
2487 | ret = nand_do_write_ops(mtd, to, ops); | |
2488 | ||
7351d3a5 | 2489 | out: |
1da177e4 | 2490 | nand_release_device(mtd); |
1da177e4 LT |
2491 | return ret; |
2492 | } | |
2493 | ||
1da177e4 | 2494 | /** |
7854d3f7 | 2495 | * single_erase_cmd - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2496 | * @mtd: MTD device structure |
2497 | * @page: the page address of the block which will be erased | |
1da177e4 | 2498 | * |
8b6e50c9 | 2499 | * Standard erase command for NAND chips. |
1da177e4 | 2500 | */ |
e0c7d767 | 2501 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2502 | { |
ace4dfee | 2503 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2504 | /* Send commands to erase a block */ |
ace4dfee TG |
2505 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2506 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2507 | } |
2508 | ||
2509 | /** | |
7854d3f7 | 2510 | * multi_erase_cmd - [GENERIC] AND specific block erase command function |
8b6e50c9 BN |
2511 | * @mtd: MTD device structure |
2512 | * @page: the page address of the block which will be erased | |
1da177e4 | 2513 | * |
8b6e50c9 | 2514 | * AND multi block erase command function. Erase 4 consecutive blocks. |
1da177e4 | 2515 | */ |
e0c7d767 | 2516 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2517 | { |
ace4dfee | 2518 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2519 | /* Send commands to erase a block */ |
ace4dfee TG |
2520 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2521 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2522 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2523 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
2524 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2525 | } |
2526 | ||
2527 | /** | |
2528 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2529 | * @mtd: MTD device structure |
2530 | * @instr: erase instruction | |
1da177e4 | 2531 | * |
8b6e50c9 | 2532 | * Erase one ore more blocks. |
1da177e4 | 2533 | */ |
e0c7d767 | 2534 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2535 | { |
e0c7d767 | 2536 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2537 | } |
61b03bd7 | 2538 | |
30f464b7 | 2539 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 2540 | /** |
7854d3f7 | 2541 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2542 | * @mtd: MTD device structure |
2543 | * @instr: erase instruction | |
2544 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2545 | * |
8b6e50c9 | 2546 | * Erase one ore more blocks. |
1da177e4 | 2547 | */ |
ace4dfee TG |
2548 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2549 | int allowbbt) | |
1da177e4 | 2550 | { |
69423d99 | 2551 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2552 | struct nand_chip *chip = mtd->priv; |
f8ac0414 | 2553 | loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0}; |
ace4dfee | 2554 | unsigned int bbt_masked_page = 0xffffffff; |
69423d99 | 2555 | loff_t len; |
1da177e4 | 2556 | |
289c0522 BN |
2557 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2558 | __func__, (unsigned long long)instr->addr, | |
2559 | (unsigned long long)instr->len); | |
1da177e4 | 2560 | |
6fe5a6ac | 2561 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2562 | return -EINVAL; |
1da177e4 | 2563 | |
bb0eb217 | 2564 | instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; |
1da177e4 LT |
2565 | |
2566 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2567 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
2568 | |
2569 | /* Shift to get first page */ | |
ace4dfee TG |
2570 | page = (int)(instr->addr >> chip->page_shift); |
2571 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2572 | |
2573 | /* Calculate pages in each block */ | |
ace4dfee | 2574 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2575 | |
2576 | /* Select the NAND device */ | |
ace4dfee | 2577 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2578 | |
1da177e4 LT |
2579 | /* Check, if it is write protected */ |
2580 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2581 | pr_debug("%s: device is write protected!\n", |
2582 | __func__); | |
1da177e4 LT |
2583 | instr->state = MTD_ERASE_FAILED; |
2584 | goto erase_exit; | |
2585 | } | |
2586 | ||
ace4dfee TG |
2587 | /* |
2588 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
2589 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
2590 | * can not be matched. This is also done when the bbt is actually | |
7854d3f7 | 2591 | * erased to avoid recursive updates. |
ace4dfee TG |
2592 | */ |
2593 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
2594 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 2595 | |
1da177e4 LT |
2596 | /* Loop through the pages */ |
2597 | len = instr->len; | |
2598 | ||
2599 | instr->state = MTD_ERASING; | |
2600 | ||
2601 | while (len) { | |
12183a20 | 2602 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2603 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2604 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2605 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2606 | __func__, page); | |
1da177e4 LT |
2607 | instr->state = MTD_ERASE_FAILED; |
2608 | goto erase_exit; | |
2609 | } | |
61b03bd7 | 2610 | |
ace4dfee TG |
2611 | /* |
2612 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2613 | * contains the current cached page. |
ace4dfee TG |
2614 | */ |
2615 | if (page <= chip->pagebuf && chip->pagebuf < | |
2616 | (page + pages_per_block)) | |
2617 | chip->pagebuf = -1; | |
1da177e4 | 2618 | |
ace4dfee | 2619 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2620 | |
7bc3312b | 2621 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2622 | |
ace4dfee TG |
2623 | /* |
2624 | * See if operation failed and additional status checks are | |
2625 | * available | |
2626 | */ | |
2627 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2628 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2629 | status, page); | |
068e3c0a | 2630 | |
1da177e4 | 2631 | /* See if block erase succeeded */ |
a4ab4c5d | 2632 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2633 | pr_debug("%s: failed erase, page 0x%08x\n", |
2634 | __func__, page); | |
1da177e4 | 2635 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2636 | instr->fail_addr = |
2637 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2638 | goto erase_exit; |
2639 | } | |
30f464b7 | 2640 | |
ace4dfee TG |
2641 | /* |
2642 | * If BBT requires refresh, set the BBT rewrite flag to the | |
8b6e50c9 | 2643 | * page being erased. |
ace4dfee TG |
2644 | */ |
2645 | if (bbt_masked_page != 0xffffffff && | |
2646 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
69423d99 AH |
2647 | rewrite_bbt[chipnr] = |
2648 | ((loff_t)page << chip->page_shift); | |
61b03bd7 | 2649 | |
1da177e4 | 2650 | /* Increment page address and decrement length */ |
ace4dfee | 2651 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
2652 | page += pages_per_block; |
2653 | ||
2654 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2655 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2656 | chipnr++; |
ace4dfee TG |
2657 | chip->select_chip(mtd, -1); |
2658 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 2659 | |
ace4dfee TG |
2660 | /* |
2661 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
8b6e50c9 | 2662 | * page mask to see if this BBT should be rewritten. |
ace4dfee TG |
2663 | */ |
2664 | if (bbt_masked_page != 0xffffffff && | |
2665 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
2666 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
2667 | BBT_PAGE_MASK; | |
1da177e4 LT |
2668 | } |
2669 | } | |
2670 | instr->state = MTD_ERASE_DONE; | |
2671 | ||
7351d3a5 | 2672 | erase_exit: |
1da177e4 LT |
2673 | |
2674 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2675 | |
2676 | /* Deselect and wake up anyone waiting on the device */ | |
2677 | nand_release_device(mtd); | |
2678 | ||
49defc01 DW |
2679 | /* Do call back function */ |
2680 | if (!ret) | |
2681 | mtd_erase_callback(instr); | |
2682 | ||
ace4dfee TG |
2683 | /* |
2684 | * If BBT requires refresh and erase was successful, rewrite any | |
8b6e50c9 | 2685 | * selected bad block tables. |
ace4dfee TG |
2686 | */ |
2687 | if (bbt_masked_page == 0xffffffff || ret) | |
2688 | return ret; | |
2689 | ||
2690 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2691 | if (!rewrite_bbt[chipnr]) | |
2692 | continue; | |
8b6e50c9 | 2693 | /* Update the BBT for chip */ |
289c0522 BN |
2694 | pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n", |
2695 | __func__, chipnr, rewrite_bbt[chipnr], | |
2696 | chip->bbt_td->pages[chipnr]); | |
ace4dfee | 2697 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); |
30f464b7 DM |
2698 | } |
2699 | ||
1da177e4 LT |
2700 | /* Return more or less happy */ |
2701 | return ret; | |
2702 | } | |
2703 | ||
2704 | /** | |
2705 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2706 | * @mtd: MTD device structure |
1da177e4 | 2707 | * |
8b6e50c9 | 2708 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2709 | */ |
e0c7d767 | 2710 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2711 | { |
ace4dfee | 2712 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2713 | |
289c0522 | 2714 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2715 | |
2716 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2717 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 2718 | /* Release it and go back */ |
e0c7d767 | 2719 | nand_release_device(mtd); |
1da177e4 LT |
2720 | } |
2721 | ||
1da177e4 | 2722 | /** |
ace4dfee | 2723 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2724 | * @mtd: MTD device structure |
2725 | * @offs: offset relative to mtd start | |
1da177e4 | 2726 | */ |
ace4dfee | 2727 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 LT |
2728 | { |
2729 | /* Check for invalid offset */ | |
ace4dfee | 2730 | if (offs > mtd->size) |
1da177e4 | 2731 | return -EINVAL; |
61b03bd7 | 2732 | |
ace4dfee | 2733 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2734 | } |
2735 | ||
2736 | /** | |
ace4dfee | 2737 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2738 | * @mtd: MTD device structure |
2739 | * @ofs: offset relative to mtd start | |
1da177e4 | 2740 | */ |
e0c7d767 | 2741 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2742 | { |
ace4dfee | 2743 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2744 | int ret; |
2745 | ||
f8ac0414 FF |
2746 | ret = nand_block_isbad(mtd, ofs); |
2747 | if (ret) { | |
8b6e50c9 | 2748 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
2749 | if (ret > 0) |
2750 | return 0; | |
e0c7d767 DW |
2751 | return ret; |
2752 | } | |
1da177e4 | 2753 | |
ace4dfee | 2754 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2755 | } |
2756 | ||
962034f4 VW |
2757 | /** |
2758 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 2759 | * @mtd: MTD device structure |
962034f4 VW |
2760 | */ |
2761 | static int nand_suspend(struct mtd_info *mtd) | |
2762 | { | |
ace4dfee | 2763 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2764 | |
ace4dfee | 2765 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2766 | } |
2767 | ||
2768 | /** | |
2769 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 2770 | * @mtd: MTD device structure |
962034f4 VW |
2771 | */ |
2772 | static void nand_resume(struct mtd_info *mtd) | |
2773 | { | |
ace4dfee | 2774 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2775 | |
ace4dfee | 2776 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2777 | nand_release_device(mtd); |
2778 | else | |
d0370219 BN |
2779 | pr_err("%s called for a chip which is not in suspended state\n", |
2780 | __func__); | |
962034f4 VW |
2781 | } |
2782 | ||
8b6e50c9 | 2783 | /* Set default functions */ |
ace4dfee | 2784 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2785 | { |
1da177e4 | 2786 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2787 | if (!chip->chip_delay) |
2788 | chip->chip_delay = 20; | |
1da177e4 LT |
2789 | |
2790 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2791 | if (chip->cmdfunc == NULL) |
2792 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2793 | |
2794 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2795 | if (chip->waitfunc == NULL) |
2796 | chip->waitfunc = nand_wait; | |
2797 | ||
2798 | if (!chip->select_chip) | |
2799 | chip->select_chip = nand_select_chip; | |
2800 | if (!chip->read_byte) | |
2801 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2802 | if (!chip->read_word) | |
2803 | chip->read_word = nand_read_word; | |
2804 | if (!chip->block_bad) | |
2805 | chip->block_bad = nand_block_bad; | |
2806 | if (!chip->block_markbad) | |
2807 | chip->block_markbad = nand_default_block_markbad; | |
2808 | if (!chip->write_buf) | |
2809 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2810 | if (!chip->read_buf) | |
2811 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
2812 | if (!chip->verify_buf) | |
2813 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; | |
2814 | if (!chip->scan_bbt) | |
2815 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2816 | |
2817 | if (!chip->controller) { | |
2818 | chip->controller = &chip->hwcontrol; | |
2819 | spin_lock_init(&chip->controller->lock); | |
2820 | init_waitqueue_head(&chip->controller->wq); | |
2821 | } | |
2822 | ||
7aa65bfd TG |
2823 | } |
2824 | ||
8b6e50c9 | 2825 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
2826 | static void sanitize_string(uint8_t *s, size_t len) |
2827 | { | |
2828 | ssize_t i; | |
2829 | ||
8b6e50c9 | 2830 | /* Null terminate */ |
d1e1f4e4 FF |
2831 | s[len - 1] = 0; |
2832 | ||
8b6e50c9 | 2833 | /* Remove non printable chars */ |
d1e1f4e4 FF |
2834 | for (i = 0; i < len - 1; i++) { |
2835 | if (s[i] < ' ' || s[i] > 127) | |
2836 | s[i] = '?'; | |
2837 | } | |
2838 | ||
8b6e50c9 | 2839 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
2840 | strim(s); |
2841 | } | |
2842 | ||
2843 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
2844 | { | |
2845 | int i; | |
2846 | while (len--) { | |
2847 | crc ^= *p++ << 8; | |
2848 | for (i = 0; i < 8; i++) | |
2849 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
2850 | } | |
2851 | ||
2852 | return crc; | |
2853 | } | |
2854 | ||
6fb277ba | 2855 | /* |
8b6e50c9 | 2856 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
2857 | */ |
2858 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 2859 | int *busw) |
6fb277ba FF |
2860 | { |
2861 | struct nand_onfi_params *p = &chip->onfi_params; | |
2862 | int i; | |
2863 | int val; | |
2864 | ||
7854d3f7 | 2865 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
2866 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
2867 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
2868 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
2869 | return 0; | |
2870 | ||
9a4d4d69 | 2871 | pr_info("ONFI flash detected\n"); |
6fb277ba FF |
2872 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
2873 | for (i = 0; i < 3; i++) { | |
2874 | chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); | |
2875 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == | |
2876 | le16_to_cpu(p->crc)) { | |
9a4d4d69 | 2877 | pr_info("ONFI param page %d valid\n", i); |
6fb277ba FF |
2878 | break; |
2879 | } | |
2880 | } | |
2881 | ||
2882 | if (i == 3) | |
2883 | return 0; | |
2884 | ||
8b6e50c9 | 2885 | /* Check version */ |
6fb277ba | 2886 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
2887 | if (val & (1 << 5)) |
2888 | chip->onfi_version = 23; | |
2889 | else if (val & (1 << 4)) | |
6fb277ba FF |
2890 | chip->onfi_version = 22; |
2891 | else if (val & (1 << 3)) | |
2892 | chip->onfi_version = 21; | |
2893 | else if (val & (1 << 2)) | |
2894 | chip->onfi_version = 20; | |
b7b1a29d | 2895 | else if (val & (1 << 1)) |
6fb277ba | 2896 | chip->onfi_version = 10; |
b7b1a29d BN |
2897 | else |
2898 | chip->onfi_version = 0; | |
2899 | ||
2900 | if (!chip->onfi_version) { | |
d0370219 | 2901 | pr_info("%s: unsupported ONFI version: %d\n", __func__, val); |
b7b1a29d BN |
2902 | return 0; |
2903 | } | |
6fb277ba FF |
2904 | |
2905 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
2906 | sanitize_string(p->model, sizeof(p->model)); | |
2907 | if (!mtd->name) | |
2908 | mtd->name = p->model; | |
2909 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
2910 | mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; | |
2911 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
4ccb3b44 | 2912 | chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize; |
08c248fb | 2913 | *busw = 0; |
6fb277ba | 2914 | if (le16_to_cpu(p->features) & 1) |
08c248fb | 2915 | *busw = NAND_BUSWIDTH_16; |
6fb277ba FF |
2916 | |
2917 | chip->options &= ~NAND_CHIPOPTIONS_MSK; | |
2918 | chip->options |= (NAND_NO_READRDY | | |
2919 | NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK; | |
2920 | ||
2921 | return 1; | |
2922 | } | |
2923 | ||
7aa65bfd | 2924 | /* |
8b6e50c9 | 2925 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
2926 | */ |
2927 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 2928 | struct nand_chip *chip, |
7351d3a5 FF |
2929 | int busw, |
2930 | int *maf_id, int *dev_id, | |
5e81e88a | 2931 | struct nand_flash_dev *type) |
7aa65bfd | 2932 | { |
d1e1f4e4 | 2933 | int i, maf_idx; |
426c457a | 2934 | u8 id_data[8]; |
6fb277ba | 2935 | int ret; |
1da177e4 LT |
2936 | |
2937 | /* Select the device */ | |
ace4dfee | 2938 | chip->select_chip(mtd, 0); |
1da177e4 | 2939 | |
ef89a880 KB |
2940 | /* |
2941 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 2942 | * after power-up. |
ef89a880 KB |
2943 | */ |
2944 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
2945 | ||
1da177e4 | 2946 | /* Send the command for reading device ID */ |
ace4dfee | 2947 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
2948 | |
2949 | /* Read manufacturer and device IDs */ | |
ace4dfee | 2950 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 2951 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 2952 | |
8b6e50c9 BN |
2953 | /* |
2954 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
2955 | * interface concerns can cause random data which looks like a |
2956 | * possibly credible NAND flash to appear. If the two results do | |
2957 | * not match, ignore the device completely. | |
2958 | */ | |
2959 | ||
2960 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
2961 | ||
d1e1f4e4 | 2962 | for (i = 0; i < 2; i++) |
426c457a | 2963 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 2964 | |
d1e1f4e4 | 2965 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
9a4d4d69 | 2966 | pr_info("%s: second ID read did not match " |
d0370219 BN |
2967 | "%02x,%02x against %02x,%02x\n", __func__, |
2968 | *maf_id, *dev_id, id_data[0], id_data[1]); | |
ed8165c7 BD |
2969 | return ERR_PTR(-ENODEV); |
2970 | } | |
2971 | ||
7aa65bfd | 2972 | if (!type) |
5e81e88a DW |
2973 | type = nand_flash_ids; |
2974 | ||
2975 | for (; type->name != NULL; type++) | |
d1e1f4e4 | 2976 | if (*dev_id == type->id) |
f8ac0414 | 2977 | break; |
5e81e88a | 2978 | |
d1e1f4e4 FF |
2979 | chip->onfi_version = 0; |
2980 | if (!type->name || !type->pagesize) { | |
6fb277ba | 2981 | /* Check is chip is ONFI compliant */ |
08c248fb | 2982 | ret = nand_flash_detect_onfi(mtd, chip, &busw); |
6fb277ba FF |
2983 | if (ret) |
2984 | goto ident_done; | |
d1e1f4e4 FF |
2985 | } |
2986 | ||
2987 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
2988 | ||
2989 | /* Read entire ID string */ | |
2990 | ||
2991 | for (i = 0; i < 8; i++) | |
2992 | id_data[i] = chip->read_byte(mtd); | |
2993 | ||
5e81e88a | 2994 | if (!type->name) |
7aa65bfd TG |
2995 | return ERR_PTR(-ENODEV); |
2996 | ||
ba0251fe TG |
2997 | if (!mtd->name) |
2998 | mtd->name = type->name; | |
2999 | ||
69423d99 | 3000 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3001 | |
12a40a57 | 3002 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 3003 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
3004 | busw = chip->init_size(mtd, chip, id_data); |
3005 | } else if (!type->pagesize) { | |
7aa65bfd | 3006 | int extid; |
29072b96 | 3007 | /* The 3rd id byte holds MLC / multichip data */ |
426c457a | 3008 | chip->cellinfo = id_data[2]; |
7aa65bfd | 3009 | /* The 4th id byte is the important one */ |
426c457a | 3010 | extid = id_data[3]; |
61b03bd7 | 3011 | |
426c457a KC |
3012 | /* |
3013 | * Field definitions are in the following datasheets: | |
3014 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
34c5bf6c | 3015 | * New style (6 byte ID): Samsung K9GBG08U0M (p.40) |
426c457a KC |
3016 | * |
3017 | * Check for wraparound + Samsung ID + nonzero 6th byte | |
3018 | * to decide what to do. | |
3019 | */ | |
3020 | if (id_data[0] == id_data[6] && id_data[1] == id_data[7] && | |
3021 | id_data[0] == NAND_MFR_SAMSUNG && | |
cfe3fdad | 3022 | (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && |
426c457a KC |
3023 | id_data[5] != 0x00) { |
3024 | /* Calc pagesize */ | |
3025 | mtd->writesize = 2048 << (extid & 0x03); | |
3026 | extid >>= 2; | |
3027 | /* Calc oobsize */ | |
34c5bf6c BN |
3028 | switch (extid & 0x03) { |
3029 | case 1: | |
3030 | mtd->oobsize = 128; | |
3031 | break; | |
3032 | case 2: | |
3033 | mtd->oobsize = 218; | |
3034 | break; | |
3035 | case 3: | |
3036 | mtd->oobsize = 400; | |
3037 | break; | |
3038 | default: | |
3039 | mtd->oobsize = 436; | |
3040 | break; | |
3041 | } | |
426c457a KC |
3042 | extid >>= 2; |
3043 | /* Calc blocksize */ | |
3044 | mtd->erasesize = (128 * 1024) << | |
3045 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3046 | busw = 0; | |
3047 | } else { | |
3048 | /* Calc pagesize */ | |
3049 | mtd->writesize = 1024 << (extid & 0x03); | |
3050 | extid >>= 2; | |
3051 | /* Calc oobsize */ | |
3052 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3053 | (mtd->writesize >> 9); | |
3054 | extid >>= 2; | |
3055 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3056 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3057 | extid >>= 2; | |
3058 | /* Get buswidth information */ | |
3059 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
3060 | } | |
7aa65bfd TG |
3061 | } else { |
3062 | /* | |
8b6e50c9 | 3063 | * Old devices have chip data hardcoded in the device id table. |
7aa65bfd | 3064 | */ |
ba0251fe TG |
3065 | mtd->erasesize = type->erasesize; |
3066 | mtd->writesize = type->pagesize; | |
4cbb9b80 | 3067 | mtd->oobsize = mtd->writesize / 32; |
ba0251fe | 3068 | busw = type->options & NAND_BUSWIDTH_16; |
2173bae8 BN |
3069 | |
3070 | /* | |
3071 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3072 | * some Spansion chips have erasesize that conflicts with size | |
8b6e50c9 | 3073 | * listed in nand_ids table. |
2173bae8 BN |
3074 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) |
3075 | */ | |
3076 | if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && | |
3077 | id_data[5] == 0x00 && id_data[6] == 0x00 && | |
3078 | id_data[7] == 0x00 && mtd->writesize == 512) { | |
3079 | mtd->erasesize = 128 * 1024; | |
3080 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3081 | } | |
7aa65bfd | 3082 | } |
d1e1f4e4 FF |
3083 | /* Get chip options, preserve non chip based options */ |
3084 | chip->options &= ~NAND_CHIPOPTIONS_MSK; | |
3085 | chip->options |= type->options & NAND_CHIPOPTIONS_MSK; | |
3086 | ||
8b6e50c9 BN |
3087 | /* |
3088 | * Check if chip is not a Samsung device. Do not clear the | |
3089 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3090 | */ |
3091 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3092 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3093 | ident_done: | |
3094 | ||
3095 | /* | |
8b6e50c9 | 3096 | * Set chip as a default. Board drivers can override it, if necessary. |
d1e1f4e4 FF |
3097 | */ |
3098 | chip->options |= NAND_NO_AUTOINCR; | |
1da177e4 | 3099 | |
7aa65bfd | 3100 | /* Try to identify manufacturer */ |
9a909867 | 3101 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3102 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3103 | break; | |
3104 | } | |
0ea4a755 | 3105 | |
7aa65bfd TG |
3106 | /* |
3107 | * Check, if buswidth is correct. Hardware drivers should set | |
8b6e50c9 | 3108 | * chip correct! |
7aa65bfd | 3109 | */ |
ace4dfee | 3110 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
9a4d4d69 | 3111 | pr_info("NAND device: Manufacturer ID:" |
d0370219 BN |
3112 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, |
3113 | *dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
9a4d4d69 | 3114 | pr_warn("NAND bus width %d instead %d bit\n", |
d0370219 BN |
3115 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3116 | busw ? 16 : 8); | |
7aa65bfd TG |
3117 | return ERR_PTR(-EINVAL); |
3118 | } | |
61b03bd7 | 3119 | |
7aa65bfd | 3120 | /* Calculate the address shift from the page size */ |
ace4dfee | 3121 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3122 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3123 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3124 | |
ace4dfee | 3125 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3126 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3127 | if (chip->chipsize & 0xffffffff) |
3128 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3129 | else { |
3130 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3131 | chip->chip_shift += 32 - 1; | |
3132 | } | |
1da177e4 | 3133 | |
26d9be11 AB |
3134 | chip->badblockbits = 8; |
3135 | ||
7aa65bfd | 3136 | /* Set the bad block position */ |
065a1ed8 | 3137 | if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16)) |
c7b28e25 | 3138 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; |
065a1ed8 BN |
3139 | else |
3140 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
61b03bd7 | 3141 | |
b60b08b0 KC |
3142 | /* |
3143 | * Bad block marker is stored in the last page of each block | |
c7b28e25 BN |
3144 | * on Samsung and Hynix MLC devices; stored in first two pages |
3145 | * of each block on Micron devices with 2KiB pages and on | |
8c342335 BN |
3146 | * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix. |
3147 | * All others scan only the first page. | |
b60b08b0 KC |
3148 | */ |
3149 | if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && | |
3150 | (*maf_id == NAND_MFR_SAMSUNG || | |
3151 | *maf_id == NAND_MFR_HYNIX)) | |
5fb1549d | 3152 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; |
c7b28e25 BN |
3153 | else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && |
3154 | (*maf_id == NAND_MFR_SAMSUNG || | |
3155 | *maf_id == NAND_MFR_HYNIX || | |
13ed7aed | 3156 | *maf_id == NAND_MFR_TOSHIBA || |
8c342335 BN |
3157 | *maf_id == NAND_MFR_AMD || |
3158 | *maf_id == NAND_MFR_MACRONIX)) || | |
c7b28e25 BN |
3159 | (mtd->writesize == 2048 && |
3160 | *maf_id == NAND_MFR_MICRON)) | |
5fb1549d | 3161 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; |
c7b28e25 | 3162 | |
7aa65bfd | 3163 | /* Check for AND chips with 4 page planes */ |
ace4dfee TG |
3164 | if (chip->options & NAND_4PAGE_ARRAY) |
3165 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 3166 | else |
ace4dfee | 3167 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd | 3168 | |
8b6e50c9 | 3169 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3170 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3171 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3172 | |
9a4d4d69 | 3173 | pr_info("NAND device: Manufacturer ID:" |
d1e1f4e4 FF |
3174 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id, |
3175 | nand_manuf_ids[maf_idx].name, | |
0b524fb9 | 3176 | chip->onfi_version ? chip->onfi_params.model : type->name); |
7aa65bfd TG |
3177 | |
3178 | return type; | |
3179 | } | |
3180 | ||
7aa65bfd | 3181 | /** |
3b85c321 | 3182 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3183 | * @mtd: MTD device structure |
3184 | * @maxchips: number of chips to scan for | |
3185 | * @table: alternative NAND ID table | |
7aa65bfd | 3186 | * |
8b6e50c9 BN |
3187 | * This is the first phase of the normal nand_scan() function. It reads the |
3188 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3189 | * |
3b85c321 | 3190 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3191 | */ |
5e81e88a DW |
3192 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3193 | struct nand_flash_dev *table) | |
7aa65bfd | 3194 | { |
d1e1f4e4 | 3195 | int i, busw, nand_maf_id, nand_dev_id; |
ace4dfee | 3196 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3197 | struct nand_flash_dev *type; |
3198 | ||
7aa65bfd | 3199 | /* Get buswidth to select the correct functions */ |
ace4dfee | 3200 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 3201 | /* Set the default functions */ |
ace4dfee | 3202 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
3203 | |
3204 | /* Read the flash type */ | |
7351d3a5 FF |
3205 | type = nand_get_flash_type(mtd, chip, busw, |
3206 | &nand_maf_id, &nand_dev_id, table); | |
7aa65bfd TG |
3207 | |
3208 | if (IS_ERR(type)) { | |
b1c6e6db | 3209 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3210 | pr_warn("No NAND device found\n"); |
ace4dfee | 3211 | chip->select_chip(mtd, -1); |
7aa65bfd | 3212 | return PTR_ERR(type); |
1da177e4 LT |
3213 | } |
3214 | ||
7aa65bfd | 3215 | /* Check for a chip array */ |
e0c7d767 | 3216 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3217 | chip->select_chip(mtd, i); |
ef89a880 KB |
3218 | /* See comment in nand_get_flash_type for reset */ |
3219 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3220 | /* Send the command for reading device ID */ |
ace4dfee | 3221 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3222 | /* Read manufacturer and device IDs */ |
ace4dfee | 3223 | if (nand_maf_id != chip->read_byte(mtd) || |
d1e1f4e4 | 3224 | nand_dev_id != chip->read_byte(mtd)) |
1da177e4 LT |
3225 | break; |
3226 | } | |
3227 | if (i > 1) | |
9a4d4d69 | 3228 | pr_info("%d NAND chips detected\n", i); |
61b03bd7 | 3229 | |
1da177e4 | 3230 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3231 | chip->numchips = i; |
3232 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3233 | |
3b85c321 DW |
3234 | return 0; |
3235 | } | |
7351d3a5 | 3236 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 DW |
3237 | |
3238 | ||
3239 | /** | |
3240 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 3241 | * @mtd: MTD device structure |
3b85c321 | 3242 | * |
8b6e50c9 BN |
3243 | * This is the second phase of the normal nand_scan() function. It fills out |
3244 | * all the uninitialized function pointers with the defaults and scans for a | |
3245 | * bad block table if appropriate. | |
3b85c321 DW |
3246 | */ |
3247 | int nand_scan_tail(struct mtd_info *mtd) | |
3248 | { | |
3249 | int i; | |
3250 | struct nand_chip *chip = mtd->priv; | |
3251 | ||
4bf63fcb DW |
3252 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3253 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
3254 | if (!chip->buffers) | |
3255 | return -ENOMEM; | |
3256 | ||
7dcdcbef | 3257 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3258 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3259 | |
7aa65bfd | 3260 | /* |
8b6e50c9 | 3261 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 3262 | */ |
193bd400 | 3263 | if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3264 | switch (mtd->oobsize) { |
1da177e4 | 3265 | case 8: |
5bd34c09 | 3266 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
3267 | break; |
3268 | case 16: | |
5bd34c09 | 3269 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
3270 | break; |
3271 | case 64: | |
5bd34c09 | 3272 | chip->ecc.layout = &nand_oob_64; |
1da177e4 | 3273 | break; |
81ec5364 TG |
3274 | case 128: |
3275 | chip->ecc.layout = &nand_oob_128; | |
3276 | break; | |
1da177e4 | 3277 | default: |
d0370219 BN |
3278 | pr_warn("No oob scheme defined for oobsize %d\n", |
3279 | mtd->oobsize); | |
1da177e4 LT |
3280 | BUG(); |
3281 | } | |
3282 | } | |
61b03bd7 | 3283 | |
956e944c DW |
3284 | if (!chip->write_page) |
3285 | chip->write_page = nand_write_page; | |
3286 | ||
61b03bd7 | 3287 | /* |
8b6e50c9 | 3288 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 3289 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 3290 | */ |
956e944c | 3291 | |
ace4dfee | 3292 | switch (chip->ecc.mode) { |
6e0cb135 SN |
3293 | case NAND_ECC_HW_OOB_FIRST: |
3294 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
3295 | if (!chip->ecc.calculate || !chip->ecc.correct || | |
3296 | !chip->ecc.hwctl) { | |
9a4d4d69 | 3297 | pr_warn("No ECC functions supplied; " |
d0370219 | 3298 | "hardware ECC not possible\n"); |
6e0cb135 SN |
3299 | BUG(); |
3300 | } | |
3301 | if (!chip->ecc.read_page) | |
3302 | chip->ecc.read_page = nand_read_page_hwecc_oob_first; | |
3303 | ||
6dfc6d25 | 3304 | case NAND_ECC_HW: |
8b6e50c9 | 3305 | /* Use standard hwecc read page function? */ |
f5bbdacc TG |
3306 | if (!chip->ecc.read_page) |
3307 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
3308 | if (!chip->ecc.write_page) |
3309 | chip->ecc.write_page = nand_write_page_hwecc; | |
52ff49df DB |
3310 | if (!chip->ecc.read_page_raw) |
3311 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3312 | if (!chip->ecc.write_page_raw) | |
3313 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3314 | if (!chip->ecc.read_oob) |
3315 | chip->ecc.read_oob = nand_read_oob_std; | |
3316 | if (!chip->ecc.write_oob) | |
3317 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 3318 | |
6dfc6d25 | 3319 | case NAND_ECC_HW_SYNDROME: |
78b65179 SW |
3320 | if ((!chip->ecc.calculate || !chip->ecc.correct || |
3321 | !chip->ecc.hwctl) && | |
3322 | (!chip->ecc.read_page || | |
1c45f604 | 3323 | chip->ecc.read_page == nand_read_page_hwecc || |
78b65179 | 3324 | !chip->ecc.write_page || |
1c45f604 | 3325 | chip->ecc.write_page == nand_write_page_hwecc)) { |
9a4d4d69 | 3326 | pr_warn("No ECC functions supplied; " |
d0370219 | 3327 | "hardware ECC not possible\n"); |
6dfc6d25 TG |
3328 | BUG(); |
3329 | } | |
8b6e50c9 | 3330 | /* Use standard syndrome read/write page function? */ |
f5bbdacc TG |
3331 | if (!chip->ecc.read_page) |
3332 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
3333 | if (!chip->ecc.write_page) |
3334 | chip->ecc.write_page = nand_write_page_syndrome; | |
52ff49df DB |
3335 | if (!chip->ecc.read_page_raw) |
3336 | chip->ecc.read_page_raw = nand_read_page_raw_syndrome; | |
3337 | if (!chip->ecc.write_page_raw) | |
3338 | chip->ecc.write_page_raw = nand_write_page_raw_syndrome; | |
7bc3312b TG |
3339 | if (!chip->ecc.read_oob) |
3340 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
3341 | if (!chip->ecc.write_oob) | |
3342 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 3343 | |
ace4dfee | 3344 | if (mtd->writesize >= chip->ecc.size) |
6dfc6d25 | 3345 | break; |
9a4d4d69 | 3346 | pr_warn("%d byte HW ECC not possible on " |
d0370219 BN |
3347 | "%d byte page size, fallback to SW ECC\n", |
3348 | chip->ecc.size, mtd->writesize); | |
ace4dfee | 3349 | chip->ecc.mode = NAND_ECC_SOFT; |
61b03bd7 | 3350 | |
6dfc6d25 | 3351 | case NAND_ECC_SOFT: |
ace4dfee TG |
3352 | chip->ecc.calculate = nand_calculate_ecc; |
3353 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 3354 | chip->ecc.read_page = nand_read_page_swecc; |
3d459559 | 3355 | chip->ecc.read_subpage = nand_read_subpage; |
f75e5097 | 3356 | chip->ecc.write_page = nand_write_page_swecc; |
52ff49df DB |
3357 | chip->ecc.read_page_raw = nand_read_page_raw; |
3358 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3359 | chip->ecc.read_oob = nand_read_oob_std; |
3360 | chip->ecc.write_oob = nand_write_oob_std; | |
9a73290d SV |
3361 | if (!chip->ecc.size) |
3362 | chip->ecc.size = 256; | |
ace4dfee | 3363 | chip->ecc.bytes = 3; |
1da177e4 | 3364 | break; |
61b03bd7 | 3365 | |
193bd400 ID |
3366 | case NAND_ECC_SOFT_BCH: |
3367 | if (!mtd_nand_has_bch()) { | |
9a4d4d69 | 3368 | pr_warn("CONFIG_MTD_ECC_BCH not enabled\n"); |
193bd400 ID |
3369 | BUG(); |
3370 | } | |
3371 | chip->ecc.calculate = nand_bch_calculate_ecc; | |
3372 | chip->ecc.correct = nand_bch_correct_data; | |
3373 | chip->ecc.read_page = nand_read_page_swecc; | |
3374 | chip->ecc.read_subpage = nand_read_subpage; | |
3375 | chip->ecc.write_page = nand_write_page_swecc; | |
3376 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3377 | chip->ecc.write_page_raw = nand_write_page_raw; | |
3378 | chip->ecc.read_oob = nand_read_oob_std; | |
3379 | chip->ecc.write_oob = nand_write_oob_std; | |
3380 | /* | |
3381 | * Board driver should supply ecc.size and ecc.bytes values to | |
3382 | * select how many bits are correctable; see nand_bch_init() | |
8b6e50c9 BN |
3383 | * for details. Otherwise, default to 4 bits for large page |
3384 | * devices. | |
193bd400 ID |
3385 | */ |
3386 | if (!chip->ecc.size && (mtd->oobsize >= 64)) { | |
3387 | chip->ecc.size = 512; | |
3388 | chip->ecc.bytes = 7; | |
3389 | } | |
3390 | chip->ecc.priv = nand_bch_init(mtd, | |
3391 | chip->ecc.size, | |
3392 | chip->ecc.bytes, | |
3393 | &chip->ecc.layout); | |
3394 | if (!chip->ecc.priv) { | |
9a4d4d69 | 3395 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
3396 | BUG(); |
3397 | } | |
3398 | break; | |
3399 | ||
61b03bd7 | 3400 | case NAND_ECC_NONE: |
9a4d4d69 | 3401 | pr_warn("NAND_ECC_NONE selected by board driver. " |
d0370219 | 3402 | "This is not recommended!\n"); |
8593fbc6 TG |
3403 | chip->ecc.read_page = nand_read_page_raw; |
3404 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b | 3405 | chip->ecc.read_oob = nand_read_oob_std; |
52ff49df DB |
3406 | chip->ecc.read_page_raw = nand_read_page_raw; |
3407 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b | 3408 | chip->ecc.write_oob = nand_write_oob_std; |
ace4dfee TG |
3409 | chip->ecc.size = mtd->writesize; |
3410 | chip->ecc.bytes = 0; | |
1da177e4 | 3411 | break; |
956e944c | 3412 | |
1da177e4 | 3413 | default: |
d0370219 | 3414 | pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode); |
61b03bd7 | 3415 | BUG(); |
1da177e4 | 3416 | } |
61b03bd7 | 3417 | |
9ce244b3 | 3418 | /* For many systems, the standard OOB write also works for raw */ |
c46f6483 BN |
3419 | if (!chip->ecc.read_oob_raw) |
3420 | chip->ecc.read_oob_raw = chip->ecc.read_oob; | |
9ce244b3 BN |
3421 | if (!chip->ecc.write_oob_raw) |
3422 | chip->ecc.write_oob_raw = chip->ecc.write_oob; | |
3423 | ||
5bd34c09 TG |
3424 | /* |
3425 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 3426 | * the out of band area. |
5bd34c09 TG |
3427 | */ |
3428 | chip->ecc.layout->oobavail = 0; | |
81d19b04 DB |
3429 | for (i = 0; chip->ecc.layout->oobfree[i].length |
3430 | && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) | |
5bd34c09 TG |
3431 | chip->ecc.layout->oobavail += |
3432 | chip->ecc.layout->oobfree[i].length; | |
1f92267c | 3433 | mtd->oobavail = chip->ecc.layout->oobavail; |
5bd34c09 | 3434 | |
7aa65bfd TG |
3435 | /* |
3436 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 3437 | * mode. |
7aa65bfd | 3438 | */ |
ace4dfee | 3439 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
f8ac0414 | 3440 | if (chip->ecc.steps * chip->ecc.size != mtd->writesize) { |
9a4d4d69 | 3441 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 3442 | BUG(); |
1da177e4 | 3443 | } |
f5bbdacc | 3444 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 3445 | |
8b6e50c9 | 3446 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
29072b96 TG |
3447 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && |
3448 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
f8ac0414 | 3449 | switch (chip->ecc.steps) { |
29072b96 TG |
3450 | case 2: |
3451 | mtd->subpage_sft = 1; | |
3452 | break; | |
3453 | case 4: | |
3454 | case 8: | |
81ec5364 | 3455 | case 16: |
29072b96 TG |
3456 | mtd->subpage_sft = 2; |
3457 | break; | |
3458 | } | |
3459 | } | |
3460 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
3461 | ||
04bbd0ea | 3462 | /* Initialize state */ |
ace4dfee | 3463 | chip->state = FL_READY; |
1da177e4 LT |
3464 | |
3465 | /* De-select the device */ | |
ace4dfee | 3466 | chip->select_chip(mtd, -1); |
1da177e4 LT |
3467 | |
3468 | /* Invalidate the pagebuffer reference */ | |
ace4dfee | 3469 | chip->pagebuf = -1; |
1da177e4 LT |
3470 | |
3471 | /* Fill in remaining MTD driver data */ | |
3472 | mtd->type = MTD_NANDFLASH; | |
93edbad6 ML |
3473 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
3474 | MTD_CAP_NANDFLASH; | |
1da177e4 LT |
3475 | mtd->erase = nand_erase; |
3476 | mtd->point = NULL; | |
3477 | mtd->unpoint = NULL; | |
3478 | mtd->read = nand_read; | |
3479 | mtd->write = nand_write; | |
2af7c653 | 3480 | mtd->panic_write = panic_nand_write; |
1da177e4 LT |
3481 | mtd->read_oob = nand_read_oob; |
3482 | mtd->write_oob = nand_write_oob; | |
1da177e4 LT |
3483 | mtd->sync = nand_sync; |
3484 | mtd->lock = NULL; | |
3485 | mtd->unlock = NULL; | |
962034f4 VW |
3486 | mtd->suspend = nand_suspend; |
3487 | mtd->resume = nand_resume; | |
1da177e4 LT |
3488 | mtd->block_isbad = nand_block_isbad; |
3489 | mtd->block_markbad = nand_block_markbad; | |
cbcab65a | 3490 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 3491 | |
5bd34c09 TG |
3492 | /* propagate ecc.layout to mtd_info */ |
3493 | mtd->ecclayout = chip->ecc.layout; | |
1da177e4 | 3494 | |
0040bf38 | 3495 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 3496 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 3497 | return 0; |
1da177e4 LT |
3498 | |
3499 | /* Build bad block table */ | |
ace4dfee | 3500 | return chip->scan_bbt(mtd); |
1da177e4 | 3501 | } |
7351d3a5 | 3502 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 3503 | |
8b6e50c9 BN |
3504 | /* |
3505 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 3506 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
3507 | * to call us from in-kernel code if the core NAND support is modular. |
3508 | */ | |
3b85c321 DW |
3509 | #ifdef MODULE |
3510 | #define caller_is_module() (1) | |
3511 | #else | |
3512 | #define caller_is_module() \ | |
a6e6abd5 | 3513 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
3514 | #endif |
3515 | ||
3516 | /** | |
3517 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
3518 | * @mtd: MTD device structure |
3519 | * @maxchips: number of chips to scan for | |
3b85c321 | 3520 | * |
8b6e50c9 BN |
3521 | * This fills out all the uninitialized function pointers with the defaults. |
3522 | * The flash ID is read and the mtd/chip structures are filled with the | |
3523 | * appropriate values. The mtd->owner field must be set to the module of the | |
3524 | * caller. | |
3b85c321 DW |
3525 | */ |
3526 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
3527 | { | |
3528 | int ret; | |
3529 | ||
3530 | /* Many callers got this wrong, so check for it for a while... */ | |
3531 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 3532 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
3533 | BUG(); |
3534 | } | |
3535 | ||
5e81e88a | 3536 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
3537 | if (!ret) |
3538 | ret = nand_scan_tail(mtd); | |
3539 | return ret; | |
3540 | } | |
7351d3a5 | 3541 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 3542 | |
1da177e4 | 3543 | /** |
61b03bd7 | 3544 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
3545 | * @mtd: MTD device structure |
3546 | */ | |
e0c7d767 | 3547 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 3548 | { |
ace4dfee | 3549 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 3550 | |
193bd400 ID |
3551 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
3552 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
3553 | ||
5ffcaf3d | 3554 | mtd_device_unregister(mtd); |
1da177e4 | 3555 | |
fa671646 | 3556 | /* Free bad block table memory */ |
ace4dfee | 3557 | kfree(chip->bbt); |
4bf63fcb DW |
3558 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3559 | kfree(chip->buffers); | |
58373ff0 BN |
3560 | |
3561 | /* Free bad block descriptor memory */ | |
3562 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
3563 | & NAND_BBT_DYNAMICSTRUCT) | |
3564 | kfree(chip->badblock_pattern); | |
1da177e4 | 3565 | } |
e0c7d767 | 3566 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
3567 | |
3568 | static int __init nand_base_init(void) | |
3569 | { | |
3570 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
3571 | return 0; | |
3572 | } | |
3573 | ||
3574 | static void __exit nand_base_exit(void) | |
3575 | { | |
3576 | led_trigger_unregister_simple(nand_led_trigger); | |
3577 | } | |
3578 | ||
3579 | module_init(nand_base_init); | |
3580 | module_exit(nand_base_exit); | |
3581 | ||
e0c7d767 | 3582 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
3583 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
3584 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 3585 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |