Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Additional technical information is available on |
8b2b403c | 10 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 24 | * if we have HW ECC support. |
1da177e4 LT |
25 | * The AG-AND chips have nice features for speed improvement, |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
c0b8ba7b | 27 | * BBT table is not serialized, has to be fixed |
1da177e4 | 28 | * |
1da177e4 LT |
29 | * This program is free software; you can redistribute it and/or modify |
30 | * it under the terms of the GNU General Public License version 2 as | |
31 | * published by the Free Software Foundation. | |
32 | * | |
33 | */ | |
34 | ||
552d9205 | 35 | #include <linux/module.h> |
1da177e4 LT |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
7aa65bfd | 38 | #include <linux/err.h> |
1da177e4 LT |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 45 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
46 | #include <linux/interrupt.h> |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
7351d3a5 | 49 | #include <linux/io.h> |
1da177e4 | 50 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
51 | |
52 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 53 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
54 | .eccbytes = 3, |
55 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
56 | .oobfree = { |
57 | {.offset = 3, | |
58 | .length = 2}, | |
59 | {.offset = 6, | |
f8ac0414 | 60 | .length = 2} } |
1da177e4 LT |
61 | }; |
62 | ||
5bd34c09 | 63 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
64 | .eccbytes = 6, |
65 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
66 | .oobfree = { |
67 | {.offset = 8, | |
f8ac0414 | 68 | . length = 8} } |
1da177e4 LT |
69 | }; |
70 | ||
5bd34c09 | 71 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
72 | .eccbytes = 24, |
73 | .eccpos = { | |
e0c7d767 DW |
74 | 40, 41, 42, 43, 44, 45, 46, 47, |
75 | 48, 49, 50, 51, 52, 53, 54, 55, | |
76 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
77 | .oobfree = { |
78 | {.offset = 2, | |
f8ac0414 | 79 | .length = 38} } |
1da177e4 LT |
80 | }; |
81 | ||
81ec5364 TG |
82 | static struct nand_ecclayout nand_oob_128 = { |
83 | .eccbytes = 48, | |
84 | .eccpos = { | |
85 | 80, 81, 82, 83, 84, 85, 86, 87, | |
86 | 88, 89, 90, 91, 92, 93, 94, 95, | |
87 | 96, 97, 98, 99, 100, 101, 102, 103, | |
88 | 104, 105, 106, 107, 108, 109, 110, 111, | |
89 | 112, 113, 114, 115, 116, 117, 118, 119, | |
90 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
91 | .oobfree = { | |
92 | {.offset = 2, | |
f8ac0414 | 93 | .length = 78} } |
81ec5364 TG |
94 | }; |
95 | ||
ace4dfee | 96 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 97 | int new_state); |
1da177e4 | 98 | |
8593fbc6 TG |
99 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
100 | struct mtd_oob_ops *ops); | |
101 | ||
d470a97c | 102 | /* |
8e87d782 | 103 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
104 | * compiled away when LED support is disabled. |
105 | */ | |
106 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
107 | ||
6fe5a6ac VS |
108 | static int check_offs_len(struct mtd_info *mtd, |
109 | loff_t ofs, uint64_t len) | |
110 | { | |
111 | struct nand_chip *chip = mtd->priv; | |
112 | int ret = 0; | |
113 | ||
114 | /* Start address must align on block boundary */ | |
115 | if (ofs & ((1 << chip->phys_erase_shift) - 1)) { | |
289c0522 | 116 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
117 | ret = -EINVAL; |
118 | } | |
119 | ||
120 | /* Length must align on block boundary */ | |
121 | if (len & ((1 << chip->phys_erase_shift) - 1)) { | |
289c0522 | 122 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
123 | ret = -EINVAL; |
124 | } | |
125 | ||
6fe5a6ac VS |
126 | return ret; |
127 | } | |
128 | ||
1da177e4 LT |
129 | /** |
130 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 131 | * @mtd: MTD device structure |
61b03bd7 | 132 | * |
8b6e50c9 | 133 | * Deselect, release chip lock and wake up anyone waiting on the device. |
1da177e4 | 134 | */ |
e0c7d767 | 135 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 136 | { |
ace4dfee | 137 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
138 | |
139 | /* De-select the NAND device */ | |
ace4dfee | 140 | chip->select_chip(mtd, -1); |
0dfc6246 | 141 | |
a36ed299 | 142 | /* Release the controller and the chip */ |
ace4dfee TG |
143 | spin_lock(&chip->controller->lock); |
144 | chip->controller->active = NULL; | |
145 | chip->state = FL_READY; | |
146 | wake_up(&chip->controller->wq); | |
147 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
148 | } |
149 | ||
150 | /** | |
151 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 152 | * @mtd: MTD device structure |
1da177e4 | 153 | * |
7854d3f7 | 154 | * Default read function for 8bit buswidth |
1da177e4 | 155 | */ |
58dd8f2b | 156 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 157 | { |
ace4dfee TG |
158 | struct nand_chip *chip = mtd->priv; |
159 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
160 | } |
161 | ||
1da177e4 LT |
162 | /** |
163 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip | |
7854d3f7 | 164 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 165 | * @mtd: MTD device structure |
1da177e4 | 166 | * |
7854d3f7 BN |
167 | * Default read function for 16bit buswidth with endianness conversion. |
168 | * | |
1da177e4 | 169 | */ |
58dd8f2b | 170 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 171 | { |
ace4dfee TG |
172 | struct nand_chip *chip = mtd->priv; |
173 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
174 | } |
175 | ||
1da177e4 LT |
176 | /** |
177 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 178 | * @mtd: MTD device structure |
1da177e4 | 179 | * |
7854d3f7 | 180 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
181 | */ |
182 | static u16 nand_read_word(struct mtd_info *mtd) | |
183 | { | |
ace4dfee TG |
184 | struct nand_chip *chip = mtd->priv; |
185 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
186 | } |
187 | ||
1da177e4 LT |
188 | /** |
189 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
190 | * @mtd: MTD device structure |
191 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
192 | * |
193 | * Default select function for 1 chip devices. | |
194 | */ | |
ace4dfee | 195 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 196 | { |
ace4dfee TG |
197 | struct nand_chip *chip = mtd->priv; |
198 | ||
199 | switch (chipnr) { | |
1da177e4 | 200 | case -1: |
ace4dfee | 201 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
202 | break; |
203 | case 0: | |
1da177e4 LT |
204 | break; |
205 | ||
206 | default: | |
207 | BUG(); | |
208 | } | |
209 | } | |
210 | ||
211 | /** | |
212 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
213 | * @mtd: MTD device structure |
214 | * @buf: data buffer | |
215 | * @len: number of bytes to write | |
1da177e4 | 216 | * |
7854d3f7 | 217 | * Default write function for 8bit buswidth. |
1da177e4 | 218 | */ |
58dd8f2b | 219 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
220 | { |
221 | int i; | |
ace4dfee | 222 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 223 | |
e0c7d767 | 224 | for (i = 0; i < len; i++) |
ace4dfee | 225 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
226 | } |
227 | ||
228 | /** | |
61b03bd7 | 229 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
230 | * @mtd: MTD device structure |
231 | * @buf: buffer to store date | |
232 | * @len: number of bytes to read | |
1da177e4 | 233 | * |
7854d3f7 | 234 | * Default read function for 8bit buswidth. |
1da177e4 | 235 | */ |
58dd8f2b | 236 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
237 | { |
238 | int i; | |
ace4dfee | 239 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 240 | |
e0c7d767 | 241 | for (i = 0; i < len; i++) |
ace4dfee | 242 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
243 | } |
244 | ||
245 | /** | |
61b03bd7 | 246 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
8b6e50c9 BN |
247 | * @mtd: MTD device structure |
248 | * @buf: buffer containing the data to compare | |
249 | * @len: number of bytes to compare | |
1da177e4 | 250 | * |
7854d3f7 | 251 | * Default verify function for 8bit buswidth. |
1da177e4 | 252 | */ |
58dd8f2b | 253 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
254 | { |
255 | int i; | |
ace4dfee | 256 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 257 | |
e0c7d767 | 258 | for (i = 0; i < len; i++) |
ace4dfee | 259 | if (buf[i] != readb(chip->IO_ADDR_R)) |
1da177e4 | 260 | return -EFAULT; |
1da177e4 LT |
261 | return 0; |
262 | } | |
263 | ||
264 | /** | |
265 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
266 | * @mtd: MTD device structure |
267 | * @buf: data buffer | |
268 | * @len: number of bytes to write | |
1da177e4 | 269 | * |
7854d3f7 | 270 | * Default write function for 16bit buswidth. |
1da177e4 | 271 | */ |
58dd8f2b | 272 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
273 | { |
274 | int i; | |
ace4dfee | 275 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
276 | u16 *p = (u16 *) buf; |
277 | len >>= 1; | |
61b03bd7 | 278 | |
e0c7d767 | 279 | for (i = 0; i < len; i++) |
ace4dfee | 280 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 281 | |
1da177e4 LT |
282 | } |
283 | ||
284 | /** | |
61b03bd7 | 285 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
286 | * @mtd: MTD device structure |
287 | * @buf: buffer to store date | |
288 | * @len: number of bytes to read | |
1da177e4 | 289 | * |
7854d3f7 | 290 | * Default read function for 16bit buswidth. |
1da177e4 | 291 | */ |
58dd8f2b | 292 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
293 | { |
294 | int i; | |
ace4dfee | 295 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
296 | u16 *p = (u16 *) buf; |
297 | len >>= 1; | |
298 | ||
e0c7d767 | 299 | for (i = 0; i < len; i++) |
ace4dfee | 300 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
301 | } |
302 | ||
303 | /** | |
61b03bd7 | 304 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
8b6e50c9 BN |
305 | * @mtd: MTD device structure |
306 | * @buf: buffer containing the data to compare | |
307 | * @len: number of bytes to compare | |
1da177e4 | 308 | * |
7854d3f7 | 309 | * Default verify function for 16bit buswidth. |
1da177e4 | 310 | */ |
58dd8f2b | 311 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
312 | { |
313 | int i; | |
ace4dfee | 314 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
315 | u16 *p = (u16 *) buf; |
316 | len >>= 1; | |
317 | ||
e0c7d767 | 318 | for (i = 0; i < len; i++) |
ace4dfee | 319 | if (p[i] != readw(chip->IO_ADDR_R)) |
1da177e4 LT |
320 | return -EFAULT; |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | /** | |
326 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
327 | * @mtd: MTD device structure |
328 | * @ofs: offset from device start | |
329 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 330 | * |
61b03bd7 | 331 | * Check, if the block is bad. |
1da177e4 LT |
332 | */ |
333 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
334 | { | |
cdbec050 | 335 | int page, chipnr, res = 0, i = 0; |
ace4dfee | 336 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
337 | u16 bad; |
338 | ||
5fb1549d | 339 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
340 | ofs += mtd->erasesize - mtd->writesize; |
341 | ||
1a12f46a TK |
342 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
343 | ||
1da177e4 | 344 | if (getchip) { |
ace4dfee | 345 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 346 | |
ace4dfee | 347 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
348 | |
349 | /* Select the NAND device */ | |
ace4dfee | 350 | chip->select_chip(mtd, chipnr); |
1a12f46a | 351 | } |
1da177e4 | 352 | |
cdbec050 BN |
353 | do { |
354 | if (chip->options & NAND_BUSWIDTH_16) { | |
355 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
356 | chip->badblockpos & 0xFE, page); | |
357 | bad = cpu_to_le16(chip->read_word(mtd)); | |
358 | if (chip->badblockpos & 0x1) | |
359 | bad >>= 8; | |
360 | else | |
361 | bad &= 0xFF; | |
362 | } else { | |
363 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
364 | page); | |
365 | bad = chip->read_byte(mtd); | |
366 | } | |
367 | ||
368 | if (likely(chip->badblockbits == 8)) | |
369 | res = bad != 0xFF; | |
e0b58d0a | 370 | else |
cdbec050 BN |
371 | res = hweight8(bad) < chip->badblockbits; |
372 | ofs += mtd->writesize; | |
373 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
374 | i++; | |
375 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 376 | |
ace4dfee | 377 | if (getchip) |
1da177e4 | 378 | nand_release_device(mtd); |
61b03bd7 | 379 | |
1da177e4 LT |
380 | return res; |
381 | } | |
382 | ||
383 | /** | |
384 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
8b6e50c9 BN |
385 | * @mtd: MTD device structure |
386 | * @ofs: offset from device start | |
1da177e4 | 387 | * |
8b6e50c9 | 388 | * This is the default implementation, which can be overridden by a hardware |
e2414f4c BN |
389 | * specific driver. We try operations in the following order, according to our |
390 | * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH): | |
391 | * (1) erase the affected block, to allow OOB marker to be written cleanly | |
392 | * (2) update in-memory BBT | |
393 | * (3) write bad block marker to OOB area of affected block | |
394 | * (4) update flash-based BBT | |
395 | * Note that we retain the first error encountered in (3) or (4), finish the | |
396 | * procedures, and dump the error in the end. | |
1da177e4 LT |
397 | */ |
398 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
399 | { | |
ace4dfee | 400 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 401 | uint8_t buf[2] = { 0, 0 }; |
e2414f4c BN |
402 | int block, res, ret = 0, i = 0; |
403 | int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM); | |
61b03bd7 | 404 | |
e2414f4c | 405 | if (write_oob) { |
00918429 BN |
406 | struct erase_info einfo; |
407 | ||
408 | /* Attempt erase before marking OOB */ | |
409 | memset(&einfo, 0, sizeof(einfo)); | |
410 | einfo.mtd = mtd; | |
411 | einfo.addr = ofs; | |
412 | einfo.len = 1 << chip->phys_erase_shift; | |
413 | nand_erase_nand(mtd, &einfo, 0); | |
414 | } | |
415 | ||
1da177e4 | 416 | /* Get block number */ |
4226b510 | 417 | block = (int)(ofs >> chip->bbt_erase_shift); |
e2414f4c | 418 | /* Mark block bad in memory-based BBT */ |
ace4dfee TG |
419 | if (chip->bbt) |
420 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 | 421 | |
e2414f4c BN |
422 | /* Write bad block marker to OOB */ |
423 | if (write_oob) { | |
4a89ff88 | 424 | struct mtd_oob_ops ops; |
df698621 | 425 | loff_t wr_ofs = ofs; |
4a89ff88 | 426 | |
c0b8ba7b | 427 | nand_get_device(chip, mtd, FL_WRITING); |
f1a28c02 | 428 | |
4a89ff88 BN |
429 | ops.datbuf = NULL; |
430 | ops.oobbuf = buf; | |
85443319 BN |
431 | ops.ooboffs = chip->badblockpos; |
432 | if (chip->options & NAND_BUSWIDTH_16) { | |
433 | ops.ooboffs &= ~0x01; | |
434 | ops.len = ops.ooblen = 2; | |
435 | } else { | |
436 | ops.len = ops.ooblen = 1; | |
437 | } | |
23b1a99b | 438 | ops.mode = MTD_OPS_PLACE_OOB; |
df698621 | 439 | |
e2414f4c | 440 | /* Write to first/last page(s) if necessary */ |
df698621 BN |
441 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
442 | wr_ofs += mtd->erasesize - mtd->writesize; | |
02ed70bb | 443 | do { |
e2414f4c BN |
444 | res = nand_do_write_oob(mtd, wr_ofs, &ops); |
445 | if (!ret) | |
446 | ret = res; | |
02ed70bb | 447 | |
02ed70bb | 448 | i++; |
df698621 | 449 | wr_ofs += mtd->writesize; |
e2414f4c | 450 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); |
02ed70bb | 451 | |
c0b8ba7b | 452 | nand_release_device(mtd); |
f1a28c02 | 453 | } |
e2414f4c BN |
454 | |
455 | /* Update flash-based bad block table */ | |
456 | if (chip->bbt_options & NAND_BBT_USE_FLASH) { | |
457 | res = nand_update_bbt(mtd, ofs); | |
458 | if (!ret) | |
459 | ret = res; | |
460 | } | |
461 | ||
f1a28c02 TG |
462 | if (!ret) |
463 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 464 | |
f1a28c02 | 465 | return ret; |
1da177e4 LT |
466 | } |
467 | ||
61b03bd7 | 468 | /** |
1da177e4 | 469 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 470 | * @mtd: MTD device structure |
1da177e4 | 471 | * |
8b6e50c9 BN |
472 | * Check, if the device is write protected. The function expects, that the |
473 | * device is already selected. | |
1da177e4 | 474 | */ |
e0c7d767 | 475 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 476 | { |
ace4dfee | 477 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 478 | |
8b6e50c9 | 479 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
480 | if (chip->options & NAND_BROKEN_XD) |
481 | return 0; | |
482 | ||
1da177e4 | 483 | /* Check the WP bit */ |
ace4dfee TG |
484 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
485 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
486 | } |
487 | ||
488 | /** | |
489 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
490 | * @mtd: MTD device structure |
491 | * @ofs: offset from device start | |
492 | * @getchip: 0, if the chip is already selected | |
493 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
494 | * |
495 | * Check, if the block is bad. Either by reading the bad block table or | |
496 | * calling of the scan function. | |
497 | */ | |
2c0a2bed TG |
498 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
499 | int allowbbt) | |
1da177e4 | 500 | { |
ace4dfee | 501 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 502 | |
ace4dfee TG |
503 | if (!chip->bbt) |
504 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 505 | |
1da177e4 | 506 | /* Return info from the table */ |
e0c7d767 | 507 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
508 | } |
509 | ||
2af7c653 SK |
510 | /** |
511 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
512 | * @mtd: MTD device structure |
513 | * @timeo: Timeout | |
2af7c653 SK |
514 | * |
515 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
516 | * context. | |
517 | */ | |
518 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
519 | { | |
520 | struct nand_chip *chip = mtd->priv; | |
521 | int i; | |
522 | ||
523 | /* Wait for the device to get ready */ | |
524 | for (i = 0; i < timeo; i++) { | |
525 | if (chip->dev_ready(mtd)) | |
526 | break; | |
527 | touch_softlockup_watchdog(); | |
528 | mdelay(1); | |
529 | } | |
530 | } | |
531 | ||
7854d3f7 | 532 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 533 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 534 | { |
ace4dfee | 535 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 536 | unsigned long timeo = jiffies + 2; |
3b88775c | 537 | |
2af7c653 SK |
538 | /* 400ms timeout */ |
539 | if (in_interrupt() || oops_in_progress) | |
540 | return panic_nand_wait_ready(mtd, 400); | |
541 | ||
8fe833c1 | 542 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 543 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 544 | do { |
ace4dfee | 545 | if (chip->dev_ready(mtd)) |
8fe833c1 | 546 | break; |
8446f1d3 | 547 | touch_softlockup_watchdog(); |
61b03bd7 | 548 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 549 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 550 | } |
4b648b02 | 551 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 552 | |
1da177e4 LT |
553 | /** |
554 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
555 | * @mtd: MTD device structure |
556 | * @command: the command to be sent | |
557 | * @column: the column address for this command, -1 if none | |
558 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 559 | * |
8b6e50c9 BN |
560 | * Send command to NAND device. This function is used for small page devices |
561 | * (256/512 Bytes per page). | |
1da177e4 | 562 | */ |
7abd3ef9 TG |
563 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
564 | int column, int page_addr) | |
1da177e4 | 565 | { |
ace4dfee | 566 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 567 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 568 | |
8b6e50c9 | 569 | /* Write out the command to the device */ |
1da177e4 LT |
570 | if (command == NAND_CMD_SEQIN) { |
571 | int readcmd; | |
572 | ||
28318776 | 573 | if (column >= mtd->writesize) { |
1da177e4 | 574 | /* OOB area */ |
28318776 | 575 | column -= mtd->writesize; |
1da177e4 LT |
576 | readcmd = NAND_CMD_READOOB; |
577 | } else if (column < 256) { | |
578 | /* First 256 bytes --> READ0 */ | |
579 | readcmd = NAND_CMD_READ0; | |
580 | } else { | |
581 | column -= 256; | |
582 | readcmd = NAND_CMD_READ1; | |
583 | } | |
ace4dfee | 584 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 585 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 586 | } |
ace4dfee | 587 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 588 | |
8b6e50c9 | 589 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
590 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
591 | /* Serially input address */ | |
592 | if (column != -1) { | |
593 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 594 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 595 | column >>= 1; |
ace4dfee | 596 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
597 | ctrl &= ~NAND_CTRL_CHANGE; |
598 | } | |
599 | if (page_addr != -1) { | |
ace4dfee | 600 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 601 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 602 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 603 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
604 | if (chip->chipsize > (32 << 20)) |
605 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 606 | } |
ace4dfee | 607 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
608 | |
609 | /* | |
8b6e50c9 BN |
610 | * Program and erase have their own busy handlers status and sequential |
611 | * in needs no delay | |
e0c7d767 | 612 | */ |
1da177e4 | 613 | switch (command) { |
61b03bd7 | 614 | |
1da177e4 LT |
615 | case NAND_CMD_PAGEPROG: |
616 | case NAND_CMD_ERASE1: | |
617 | case NAND_CMD_ERASE2: | |
618 | case NAND_CMD_SEQIN: | |
619 | case NAND_CMD_STATUS: | |
620 | return; | |
621 | ||
622 | case NAND_CMD_RESET: | |
ace4dfee | 623 | if (chip->dev_ready) |
1da177e4 | 624 | break; |
ace4dfee TG |
625 | udelay(chip->chip_delay); |
626 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 627 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
628 | chip->cmd_ctrl(mtd, |
629 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
630 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
631 | ; | |
1da177e4 LT |
632 | return; |
633 | ||
e0c7d767 | 634 | /* This applies to read commands */ |
1da177e4 | 635 | default: |
61b03bd7 | 636 | /* |
1da177e4 LT |
637 | * If we don't have access to the busy pin, we apply the given |
638 | * command delay | |
e0c7d767 | 639 | */ |
ace4dfee TG |
640 | if (!chip->dev_ready) { |
641 | udelay(chip->chip_delay); | |
1da177e4 | 642 | return; |
61b03bd7 | 643 | } |
1da177e4 | 644 | } |
8b6e50c9 BN |
645 | /* |
646 | * Apply this short delay always to ensure that we do wait tWB in | |
647 | * any case on any machine. | |
648 | */ | |
e0c7d767 | 649 | ndelay(100); |
3b88775c TG |
650 | |
651 | nand_wait_ready(mtd); | |
1da177e4 LT |
652 | } |
653 | ||
654 | /** | |
655 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
656 | * @mtd: MTD device structure |
657 | * @command: the command to be sent | |
658 | * @column: the column address for this command, -1 if none | |
659 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 660 | * |
7abd3ef9 | 661 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
662 | * devices. We don't have the separate regions as we have in the small page |
663 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 664 | */ |
7abd3ef9 TG |
665 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
666 | int column, int page_addr) | |
1da177e4 | 667 | { |
ace4dfee | 668 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
669 | |
670 | /* Emulate NAND_CMD_READOOB */ | |
671 | if (command == NAND_CMD_READOOB) { | |
28318776 | 672 | column += mtd->writesize; |
1da177e4 LT |
673 | command = NAND_CMD_READ0; |
674 | } | |
61b03bd7 | 675 | |
7abd3ef9 | 676 | /* Command latch cycle */ |
ace4dfee | 677 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 678 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
679 | |
680 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 681 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
682 | |
683 | /* Serially input address */ | |
684 | if (column != -1) { | |
685 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 686 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 687 | column >>= 1; |
ace4dfee | 688 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 689 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 690 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 691 | } |
1da177e4 | 692 | if (page_addr != -1) { |
ace4dfee TG |
693 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
694 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 695 | NAND_NCE | NAND_ALE); |
1da177e4 | 696 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
697 | if (chip->chipsize > (128 << 20)) |
698 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 699 | NAND_NCE | NAND_ALE); |
1da177e4 | 700 | } |
1da177e4 | 701 | } |
ace4dfee | 702 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
703 | |
704 | /* | |
8b6e50c9 BN |
705 | * Program and erase have their own busy handlers status, sequential |
706 | * in, and deplete1 need no delay. | |
30f464b7 | 707 | */ |
1da177e4 | 708 | switch (command) { |
61b03bd7 | 709 | |
1da177e4 LT |
710 | case NAND_CMD_CACHEDPROG: |
711 | case NAND_CMD_PAGEPROG: | |
712 | case NAND_CMD_ERASE1: | |
713 | case NAND_CMD_ERASE2: | |
714 | case NAND_CMD_SEQIN: | |
7bc3312b | 715 | case NAND_CMD_RNDIN: |
1da177e4 | 716 | case NAND_CMD_STATUS: |
30f464b7 | 717 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
718 | return; |
719 | ||
30f464b7 DM |
720 | case NAND_CMD_STATUS_ERROR: |
721 | case NAND_CMD_STATUS_ERROR0: | |
722 | case NAND_CMD_STATUS_ERROR1: | |
723 | case NAND_CMD_STATUS_ERROR2: | |
724 | case NAND_CMD_STATUS_ERROR3: | |
8b6e50c9 | 725 | /* Read error status commands require only a short delay */ |
ace4dfee | 726 | udelay(chip->chip_delay); |
30f464b7 | 727 | return; |
1da177e4 LT |
728 | |
729 | case NAND_CMD_RESET: | |
ace4dfee | 730 | if (chip->dev_ready) |
1da177e4 | 731 | break; |
ace4dfee | 732 | udelay(chip->chip_delay); |
12efdde3 TG |
733 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
734 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
735 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
736 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
737 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
738 | ; | |
1da177e4 LT |
739 | return; |
740 | ||
7bc3312b TG |
741 | case NAND_CMD_RNDOUT: |
742 | /* No ready / busy check necessary */ | |
743 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
744 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
745 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
746 | NAND_NCE | NAND_CTRL_CHANGE); | |
747 | return; | |
748 | ||
1da177e4 | 749 | case NAND_CMD_READ0: |
12efdde3 TG |
750 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
751 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
752 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
753 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 754 | |
e0c7d767 | 755 | /* This applies to read commands */ |
1da177e4 | 756 | default: |
61b03bd7 | 757 | /* |
1da177e4 | 758 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 759 | * command delay. |
e0c7d767 | 760 | */ |
ace4dfee TG |
761 | if (!chip->dev_ready) { |
762 | udelay(chip->chip_delay); | |
1da177e4 | 763 | return; |
61b03bd7 | 764 | } |
1da177e4 | 765 | } |
3b88775c | 766 | |
8b6e50c9 BN |
767 | /* |
768 | * Apply this short delay always to ensure that we do wait tWB in | |
769 | * any case on any machine. | |
770 | */ | |
e0c7d767 | 771 | ndelay(100); |
3b88775c TG |
772 | |
773 | nand_wait_ready(mtd); | |
1da177e4 LT |
774 | } |
775 | ||
2af7c653 SK |
776 | /** |
777 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
778 | * @chip: the nand chip descriptor |
779 | * @mtd: MTD device structure | |
780 | * @new_state: the state which is requested | |
2af7c653 SK |
781 | * |
782 | * Used when in panic, no locks are taken. | |
783 | */ | |
784 | static void panic_nand_get_device(struct nand_chip *chip, | |
785 | struct mtd_info *mtd, int new_state) | |
786 | { | |
7854d3f7 | 787 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
788 | chip->controller->active = chip; |
789 | chip->state = new_state; | |
790 | } | |
791 | ||
1da177e4 LT |
792 | /** |
793 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
794 | * @chip: the nand chip descriptor |
795 | * @mtd: MTD device structure | |
796 | * @new_state: the state which is requested | |
1da177e4 LT |
797 | * |
798 | * Get the device and lock it for exclusive access | |
799 | */ | |
2c0a2bed | 800 | static int |
ace4dfee | 801 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 802 | { |
ace4dfee TG |
803 | spinlock_t *lock = &chip->controller->lock; |
804 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 805 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 806 | retry: |
0dfc6246 TG |
807 | spin_lock(lock); |
808 | ||
b8b3ee9a | 809 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
810 | if (!chip->controller->active) |
811 | chip->controller->active = chip; | |
a36ed299 | 812 | |
ace4dfee TG |
813 | if (chip->controller->active == chip && chip->state == FL_READY) { |
814 | chip->state = new_state; | |
0dfc6246 | 815 | spin_unlock(lock); |
962034f4 VW |
816 | return 0; |
817 | } | |
818 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
819 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
820 | chip->state = FL_PM_SUSPENDED; | |
821 | spin_unlock(lock); | |
822 | return 0; | |
6b0d9a84 | 823 | } |
0dfc6246 TG |
824 | } |
825 | set_current_state(TASK_UNINTERRUPTIBLE); | |
826 | add_wait_queue(wq, &wait); | |
827 | spin_unlock(lock); | |
828 | schedule(); | |
829 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
830 | goto retry; |
831 | } | |
832 | ||
2af7c653 | 833 | /** |
8b6e50c9 BN |
834 | * panic_nand_wait - [GENERIC] wait until the command is done |
835 | * @mtd: MTD device structure | |
836 | * @chip: NAND chip structure | |
837 | * @timeo: timeout | |
2af7c653 SK |
838 | * |
839 | * Wait for command done. This is a helper function for nand_wait used when | |
840 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 841 | * an oops through mtdoops. |
2af7c653 SK |
842 | */ |
843 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
844 | unsigned long timeo) | |
845 | { | |
846 | int i; | |
847 | for (i = 0; i < timeo; i++) { | |
848 | if (chip->dev_ready) { | |
849 | if (chip->dev_ready(mtd)) | |
850 | break; | |
851 | } else { | |
852 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
853 | break; | |
854 | } | |
855 | mdelay(1); | |
f8ac0414 | 856 | } |
2af7c653 SK |
857 | } |
858 | ||
1da177e4 | 859 | /** |
8b6e50c9 BN |
860 | * nand_wait - [DEFAULT] wait until the command is done |
861 | * @mtd: MTD device structure | |
862 | * @chip: NAND chip structure | |
1da177e4 | 863 | * |
8b6e50c9 BN |
864 | * Wait for command done. This applies to erase and program only. Erase can |
865 | * take up to 400ms and program up to 20ms according to general NAND and | |
866 | * SmartMedia specs. | |
844d3b42 | 867 | */ |
7bc3312b | 868 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
869 | { |
870 | ||
e0c7d767 | 871 | unsigned long timeo = jiffies; |
7bc3312b | 872 | int status, state = chip->state; |
61b03bd7 | 873 | |
1da177e4 | 874 | if (state == FL_ERASING) |
e0c7d767 | 875 | timeo += (HZ * 400) / 1000; |
1da177e4 | 876 | else |
e0c7d767 | 877 | timeo += (HZ * 20) / 1000; |
1da177e4 | 878 | |
8fe833c1 RP |
879 | led_trigger_event(nand_led_trigger, LED_FULL); |
880 | ||
8b6e50c9 BN |
881 | /* |
882 | * Apply this short delay always to ensure that we do wait tWB in any | |
883 | * case on any machine. | |
884 | */ | |
e0c7d767 | 885 | ndelay(100); |
1da177e4 | 886 | |
ace4dfee TG |
887 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
888 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 889 | else |
ace4dfee | 890 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 891 | |
2af7c653 SK |
892 | if (in_interrupt() || oops_in_progress) |
893 | panic_nand_wait(mtd, chip, timeo); | |
894 | else { | |
895 | while (time_before(jiffies, timeo)) { | |
896 | if (chip->dev_ready) { | |
897 | if (chip->dev_ready(mtd)) | |
898 | break; | |
899 | } else { | |
900 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
901 | break; | |
902 | } | |
903 | cond_resched(); | |
1da177e4 | 904 | } |
1da177e4 | 905 | } |
8fe833c1 RP |
906 | led_trigger_event(nand_led_trigger, LED_OFF); |
907 | ||
ace4dfee | 908 | status = (int)chip->read_byte(mtd); |
1da177e4 LT |
909 | return status; |
910 | } | |
911 | ||
7d70f334 | 912 | /** |
b6d676db | 913 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
914 | * @mtd: mtd info |
915 | * @ofs: offset to start unlock from | |
916 | * @len: length to unlock | |
8b6e50c9 BN |
917 | * @invert: when = 0, unlock the range of blocks within the lower and |
918 | * upper boundary address | |
919 | * when = 1, unlock the range of blocks outside the boundaries | |
920 | * of the lower and upper boundary address | |
7d70f334 | 921 | * |
8b6e50c9 | 922 | * Returs unlock status. |
7d70f334 VS |
923 | */ |
924 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
925 | uint64_t len, int invert) | |
926 | { | |
927 | int ret = 0; | |
928 | int status, page; | |
929 | struct nand_chip *chip = mtd->priv; | |
930 | ||
931 | /* Submit address of first page to unlock */ | |
932 | page = ofs >> chip->page_shift; | |
933 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
934 | ||
935 | /* Submit address of last page to unlock */ | |
936 | page = (ofs + len) >> chip->page_shift; | |
937 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
938 | (page | invert) & chip->pagemask); | |
939 | ||
940 | /* Call wait ready function */ | |
941 | status = chip->waitfunc(mtd, chip); | |
7d70f334 VS |
942 | /* See if device thinks it succeeded */ |
943 | if (status & 0x01) { | |
289c0522 | 944 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
945 | __func__, status); |
946 | ret = -EIO; | |
947 | } | |
948 | ||
949 | return ret; | |
950 | } | |
951 | ||
952 | /** | |
b6d676db | 953 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
954 | * @mtd: mtd info |
955 | * @ofs: offset to start unlock from | |
956 | * @len: length to unlock | |
7d70f334 | 957 | * |
8b6e50c9 | 958 | * Returns unlock status. |
7d70f334 VS |
959 | */ |
960 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
961 | { | |
962 | int ret = 0; | |
963 | int chipnr; | |
964 | struct nand_chip *chip = mtd->priv; | |
965 | ||
289c0522 | 966 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
967 | __func__, (unsigned long long)ofs, len); |
968 | ||
969 | if (check_offs_len(mtd, ofs, len)) | |
970 | ret = -EINVAL; | |
971 | ||
972 | /* Align to last block address if size addresses end of the device */ | |
973 | if (ofs + len == mtd->size) | |
974 | len -= mtd->erasesize; | |
975 | ||
976 | nand_get_device(chip, mtd, FL_UNLOCKING); | |
977 | ||
978 | /* Shift to get chip number */ | |
979 | chipnr = ofs >> chip->chip_shift; | |
980 | ||
981 | chip->select_chip(mtd, chipnr); | |
982 | ||
983 | /* Check, if it is write protected */ | |
984 | if (nand_check_wp(mtd)) { | |
289c0522 | 985 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
986 | __func__); |
987 | ret = -EIO; | |
988 | goto out; | |
989 | } | |
990 | ||
991 | ret = __nand_unlock(mtd, ofs, len, 0); | |
992 | ||
993 | out: | |
7d70f334 VS |
994 | nand_release_device(mtd); |
995 | ||
996 | return ret; | |
997 | } | |
7351d3a5 | 998 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
999 | |
1000 | /** | |
b6d676db | 1001 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
1002 | * @mtd: mtd info |
1003 | * @ofs: offset to start unlock from | |
1004 | * @len: length to unlock | |
7d70f334 | 1005 | * |
8b6e50c9 BN |
1006 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
1007 | * have this feature, but it allows only to lock all blocks, not for specified | |
1008 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
1009 | * now. | |
7d70f334 | 1010 | * |
8b6e50c9 | 1011 | * Returns lock status. |
7d70f334 VS |
1012 | */ |
1013 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1014 | { | |
1015 | int ret = 0; | |
1016 | int chipnr, status, page; | |
1017 | struct nand_chip *chip = mtd->priv; | |
1018 | ||
289c0522 | 1019 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1020 | __func__, (unsigned long long)ofs, len); |
1021 | ||
1022 | if (check_offs_len(mtd, ofs, len)) | |
1023 | ret = -EINVAL; | |
1024 | ||
1025 | nand_get_device(chip, mtd, FL_LOCKING); | |
1026 | ||
1027 | /* Shift to get chip number */ | |
1028 | chipnr = ofs >> chip->chip_shift; | |
1029 | ||
1030 | chip->select_chip(mtd, chipnr); | |
1031 | ||
1032 | /* Check, if it is write protected */ | |
1033 | if (nand_check_wp(mtd)) { | |
289c0522 | 1034 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1035 | __func__); |
1036 | status = MTD_ERASE_FAILED; | |
1037 | ret = -EIO; | |
1038 | goto out; | |
1039 | } | |
1040 | ||
1041 | /* Submit address of first page to lock */ | |
1042 | page = ofs >> chip->page_shift; | |
1043 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1044 | ||
1045 | /* Call wait ready function */ | |
1046 | status = chip->waitfunc(mtd, chip); | |
7d70f334 VS |
1047 | /* See if device thinks it succeeded */ |
1048 | if (status & 0x01) { | |
289c0522 | 1049 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1050 | __func__, status); |
1051 | ret = -EIO; | |
1052 | goto out; | |
1053 | } | |
1054 | ||
1055 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1056 | ||
1057 | out: | |
7d70f334 VS |
1058 | nand_release_device(mtd); |
1059 | ||
1060 | return ret; | |
1061 | } | |
7351d3a5 | 1062 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1063 | |
8593fbc6 | 1064 | /** |
7854d3f7 | 1065 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1066 | * @mtd: mtd info structure |
1067 | * @chip: nand chip info structure | |
1068 | * @buf: buffer to store read data | |
1069 | * @page: page number to read | |
52ff49df | 1070 | * |
7854d3f7 | 1071 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1072 | */ |
1073 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1074 | uint8_t *buf, int page) |
8593fbc6 TG |
1075 | { |
1076 | chip->read_buf(mtd, buf, mtd->writesize); | |
1077 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1078 | return 0; | |
1079 | } | |
1080 | ||
52ff49df | 1081 | /** |
7854d3f7 | 1082 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1083 | * @mtd: mtd info structure |
1084 | * @chip: nand chip info structure | |
1085 | * @buf: buffer to store read data | |
1086 | * @page: page number to read | |
52ff49df DB |
1087 | * |
1088 | * We need a special oob layout and handling even when OOB isn't used. | |
1089 | */ | |
7351d3a5 FF |
1090 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1091 | struct nand_chip *chip, | |
1092 | uint8_t *buf, int page) | |
52ff49df DB |
1093 | { |
1094 | int eccsize = chip->ecc.size; | |
1095 | int eccbytes = chip->ecc.bytes; | |
1096 | uint8_t *oob = chip->oob_poi; | |
1097 | int steps, size; | |
1098 | ||
1099 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1100 | chip->read_buf(mtd, buf, eccsize); | |
1101 | buf += eccsize; | |
1102 | ||
1103 | if (chip->ecc.prepad) { | |
1104 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1105 | oob += chip->ecc.prepad; | |
1106 | } | |
1107 | ||
1108 | chip->read_buf(mtd, oob, eccbytes); | |
1109 | oob += eccbytes; | |
1110 | ||
1111 | if (chip->ecc.postpad) { | |
1112 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1113 | oob += chip->ecc.postpad; | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1118 | if (size) | |
1119 | chip->read_buf(mtd, oob, size); | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1da177e4 | 1124 | /** |
7854d3f7 | 1125 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1126 | * @mtd: mtd info structure |
1127 | * @chip: nand chip info structure | |
1128 | * @buf: buffer to store read data | |
1129 | * @page: page number to read | |
068e3c0a | 1130 | */ |
f5bbdacc | 1131 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1132 | uint8_t *buf, int page) |
1da177e4 | 1133 | { |
f5bbdacc TG |
1134 | int i, eccsize = chip->ecc.size; |
1135 | int eccbytes = chip->ecc.bytes; | |
1136 | int eccsteps = chip->ecc.steps; | |
1137 | uint8_t *p = buf; | |
4bf63fcb DW |
1138 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1139 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1140 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc | 1141 | |
46a8cf2d | 1142 | chip->ecc.read_page_raw(mtd, chip, buf, page); |
f5bbdacc TG |
1143 | |
1144 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1145 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1146 | ||
1147 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1148 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1149 | |
1150 | eccsteps = chip->ecc.steps; | |
1151 | p = buf; | |
1152 | ||
1153 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1154 | int stat; | |
1155 | ||
1156 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
c32b8dcc | 1157 | if (stat < 0) |
f5bbdacc TG |
1158 | mtd->ecc_stats.failed++; |
1159 | else | |
1160 | mtd->ecc_stats.corrected += stat; | |
1161 | } | |
1162 | return 0; | |
22c60f5f | 1163 | } |
1da177e4 | 1164 | |
3d459559 | 1165 | /** |
7854d3f7 | 1166 | * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function |
8b6e50c9 BN |
1167 | * @mtd: mtd info structure |
1168 | * @chip: nand chip info structure | |
1169 | * @data_offs: offset of requested data within the page | |
1170 | * @readlen: data length | |
1171 | * @bufpoi: buffer to store read data | |
3d459559 | 1172 | */ |
7351d3a5 FF |
1173 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
1174 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) | |
3d459559 AK |
1175 | { |
1176 | int start_step, end_step, num_steps; | |
1177 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1178 | uint8_t *p; | |
1179 | int data_col_addr, i, gaps = 0; | |
1180 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1181 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
7351d3a5 | 1182 | int index = 0; |
3d459559 | 1183 | |
7854d3f7 | 1184 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1185 | start_step = data_offs / chip->ecc.size; |
1186 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1187 | num_steps = end_step - start_step + 1; | |
1188 | ||
8b6e50c9 | 1189 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1190 | datafrag_len = num_steps * chip->ecc.size; |
1191 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1192 | ||
1193 | data_col_addr = start_step * chip->ecc.size; | |
1194 | /* If we read not a page aligned data */ | |
1195 | if (data_col_addr != 0) | |
1196 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1197 | ||
1198 | p = bufpoi + data_col_addr; | |
1199 | chip->read_buf(mtd, p, datafrag_len); | |
1200 | ||
8b6e50c9 | 1201 | /* Calculate ECC */ |
3d459559 AK |
1202 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1203 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1204 | ||
8b6e50c9 BN |
1205 | /* |
1206 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1207 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1208 | */ |
3d459559 AK |
1209 | for (i = 0; i < eccfrag_len - 1; i++) { |
1210 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1211 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1212 | gaps = 1; | |
1213 | break; | |
1214 | } | |
1215 | } | |
1216 | if (gaps) { | |
1217 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1218 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1219 | } else { | |
8b6e50c9 | 1220 | /* |
7854d3f7 | 1221 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1222 | * about buswidth alignment in read_buf. |
1223 | */ | |
7351d3a5 FF |
1224 | index = start_step * chip->ecc.bytes; |
1225 | ||
1226 | aligned_pos = eccpos[index] & ~(busw - 1); | |
3d459559 | 1227 | aligned_len = eccfrag_len; |
7351d3a5 | 1228 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1229 | aligned_len++; |
7351d3a5 | 1230 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1231 | aligned_len++; |
1232 | ||
7351d3a5 FF |
1233 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1234 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1235 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1236 | } | |
1237 | ||
1238 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1239 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1240 | |
1241 | p = bufpoi + data_col_addr; | |
1242 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1243 | int stat; | |
1244 | ||
7351d3a5 FF |
1245 | stat = chip->ecc.correct(mtd, p, |
1246 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
12c8eb98 | 1247 | if (stat < 0) |
3d459559 AK |
1248 | mtd->ecc_stats.failed++; |
1249 | else | |
1250 | mtd->ecc_stats.corrected += stat; | |
1251 | } | |
1252 | return 0; | |
1253 | } | |
1254 | ||
068e3c0a | 1255 | /** |
7854d3f7 | 1256 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1257 | * @mtd: mtd info structure |
1258 | * @chip: nand chip info structure | |
1259 | * @buf: buffer to store read data | |
1260 | * @page: page number to read | |
068e3c0a | 1261 | * |
7854d3f7 | 1262 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1263 | */ |
f5bbdacc | 1264 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1265 | uint8_t *buf, int page) |
1da177e4 | 1266 | { |
f5bbdacc TG |
1267 | int i, eccsize = chip->ecc.size; |
1268 | int eccbytes = chip->ecc.bytes; | |
1269 | int eccsteps = chip->ecc.steps; | |
1270 | uint8_t *p = buf; | |
4bf63fcb DW |
1271 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1272 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1273 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc TG |
1274 | |
1275 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1276 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1277 | chip->read_buf(mtd, p, eccsize); | |
1278 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1279 | } |
f75e5097 | 1280 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1281 | |
f5bbdacc | 1282 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1283 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1284 | |
f5bbdacc TG |
1285 | eccsteps = chip->ecc.steps; |
1286 | p = buf; | |
61b03bd7 | 1287 | |
f5bbdacc TG |
1288 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1289 | int stat; | |
1da177e4 | 1290 | |
f5bbdacc | 1291 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
c32b8dcc | 1292 | if (stat < 0) |
f5bbdacc TG |
1293 | mtd->ecc_stats.failed++; |
1294 | else | |
1295 | mtd->ecc_stats.corrected += stat; | |
1296 | } | |
1297 | return 0; | |
1298 | } | |
1da177e4 | 1299 | |
6e0cb135 | 1300 | /** |
7854d3f7 | 1301 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1302 | * @mtd: mtd info structure |
1303 | * @chip: nand chip info structure | |
1304 | * @buf: buffer to store read data | |
1305 | * @page: page number to read | |
6e0cb135 | 1306 | * |
8b6e50c9 BN |
1307 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1308 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1309 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1310 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1311 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1312 | */ |
1313 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1314 | struct nand_chip *chip, uint8_t *buf, int page) | |
1315 | { | |
1316 | int i, eccsize = chip->ecc.size; | |
1317 | int eccbytes = chip->ecc.bytes; | |
1318 | int eccsteps = chip->ecc.steps; | |
1319 | uint8_t *p = buf; | |
1320 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1321 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1322 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1323 | ||
1324 | /* Read the OOB area first */ | |
1325 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1326 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1327 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1328 | ||
1329 | for (i = 0; i < chip->ecc.total; i++) | |
1330 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1331 | ||
1332 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1333 | int stat; | |
1334 | ||
1335 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1336 | chip->read_buf(mtd, p, eccsize); | |
1337 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1338 | ||
1339 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
1340 | if (stat < 0) | |
1341 | mtd->ecc_stats.failed++; | |
1342 | else | |
1343 | mtd->ecc_stats.corrected += stat; | |
1344 | } | |
1345 | return 0; | |
1346 | } | |
1347 | ||
f5bbdacc | 1348 | /** |
7854d3f7 | 1349 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1350 | * @mtd: mtd info structure |
1351 | * @chip: nand chip info structure | |
1352 | * @buf: buffer to store read data | |
1353 | * @page: page number to read | |
f5bbdacc | 1354 | * |
8b6e50c9 BN |
1355 | * The hw generator calculates the error syndrome automatically. Therefore we |
1356 | * need a special oob layout and handling. | |
f5bbdacc TG |
1357 | */ |
1358 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1359 | uint8_t *buf, int page) |
f5bbdacc TG |
1360 | { |
1361 | int i, eccsize = chip->ecc.size; | |
1362 | int eccbytes = chip->ecc.bytes; | |
1363 | int eccsteps = chip->ecc.steps; | |
1364 | uint8_t *p = buf; | |
f75e5097 | 1365 | uint8_t *oob = chip->oob_poi; |
1da177e4 | 1366 | |
f5bbdacc TG |
1367 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1368 | int stat; | |
61b03bd7 | 1369 | |
f5bbdacc TG |
1370 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1371 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1372 | |
f5bbdacc TG |
1373 | if (chip->ecc.prepad) { |
1374 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1375 | oob += chip->ecc.prepad; | |
1376 | } | |
1da177e4 | 1377 | |
f5bbdacc TG |
1378 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1379 | chip->read_buf(mtd, oob, eccbytes); | |
1380 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1381 | |
c32b8dcc | 1382 | if (stat < 0) |
f5bbdacc | 1383 | mtd->ecc_stats.failed++; |
61b03bd7 | 1384 | else |
f5bbdacc | 1385 | mtd->ecc_stats.corrected += stat; |
61b03bd7 | 1386 | |
f5bbdacc | 1387 | oob += eccbytes; |
1da177e4 | 1388 | |
f5bbdacc TG |
1389 | if (chip->ecc.postpad) { |
1390 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1391 | oob += chip->ecc.postpad; | |
61b03bd7 | 1392 | } |
f5bbdacc | 1393 | } |
1da177e4 | 1394 | |
f5bbdacc | 1395 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1396 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1397 | if (i) |
1398 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1399 | |
f5bbdacc TG |
1400 | return 0; |
1401 | } | |
1da177e4 | 1402 | |
f5bbdacc | 1403 | /** |
7854d3f7 | 1404 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1405 | * @chip: nand chip structure |
1406 | * @oob: oob destination address | |
1407 | * @ops: oob ops structure | |
1408 | * @len: size of oob to transfer | |
8593fbc6 TG |
1409 | */ |
1410 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1411 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1412 | { |
f8ac0414 | 1413 | switch (ops->mode) { |
8593fbc6 | 1414 | |
0612b9dd BN |
1415 | case MTD_OPS_PLACE_OOB: |
1416 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1417 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1418 | return oob + len; | |
1419 | ||
0612b9dd | 1420 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1421 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1422 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1423 | size_t bytes = 0; | |
8593fbc6 | 1424 | |
f8ac0414 | 1425 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1426 | /* Read request not from offset 0? */ |
7bc3312b TG |
1427 | if (unlikely(roffs)) { |
1428 | if (roffs >= free->length) { | |
1429 | roffs -= free->length; | |
1430 | continue; | |
1431 | } | |
1432 | boffs = free->offset + roffs; | |
1433 | bytes = min_t(size_t, len, | |
1434 | (free->length - roffs)); | |
1435 | roffs = 0; | |
1436 | } else { | |
1437 | bytes = min_t(size_t, len, free->length); | |
1438 | boffs = free->offset; | |
1439 | } | |
1440 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1441 | oob += bytes; |
1442 | } | |
1443 | return oob; | |
1444 | } | |
1445 | default: | |
1446 | BUG(); | |
1447 | } | |
1448 | return NULL; | |
1449 | } | |
1450 | ||
1451 | /** | |
7854d3f7 | 1452 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1453 | * @mtd: MTD device structure |
1454 | * @from: offset to read from | |
1455 | * @ops: oob ops structure | |
f5bbdacc TG |
1456 | * |
1457 | * Internal function. Called with chip held. | |
1458 | */ | |
8593fbc6 TG |
1459 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1460 | struct mtd_oob_ops *ops) | |
f5bbdacc TG |
1461 | { |
1462 | int chipnr, page, realpage, col, bytes, aligned; | |
1463 | struct nand_chip *chip = mtd->priv; | |
1464 | struct mtd_ecc_stats stats; | |
1465 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
1466 | int sndcmd = 1; | |
1467 | int ret = 0; | |
8593fbc6 | 1468 | uint32_t readlen = ops->len; |
7014568b | 1469 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1470 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1471 | mtd->oobavail : mtd->oobsize; |
1472 | ||
8593fbc6 | 1473 | uint8_t *bufpoi, *oob, *buf; |
1da177e4 | 1474 | |
f5bbdacc | 1475 | stats = mtd->ecc_stats; |
1da177e4 | 1476 | |
f5bbdacc TG |
1477 | chipnr = (int)(from >> chip->chip_shift); |
1478 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1479 | |
f5bbdacc TG |
1480 | realpage = (int)(from >> chip->page_shift); |
1481 | page = realpage & chip->pagemask; | |
1da177e4 | 1482 | |
f5bbdacc | 1483 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1484 | |
8593fbc6 TG |
1485 | buf = ops->datbuf; |
1486 | oob = ops->oobbuf; | |
1487 | ||
f8ac0414 | 1488 | while (1) { |
f5bbdacc TG |
1489 | bytes = min(mtd->writesize - col, readlen); |
1490 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1491 | |
8b6e50c9 | 1492 | /* Is the current page in the buffer? */ |
8593fbc6 | 1493 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1494 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1495 | |
f5bbdacc TG |
1496 | if (likely(sndcmd)) { |
1497 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
1498 | sndcmd = 0; | |
1da177e4 | 1499 | } |
1da177e4 | 1500 | |
f5bbdacc | 1501 | /* Now read the page into the buffer */ |
0612b9dd | 1502 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
46a8cf2d SN |
1503 | ret = chip->ecc.read_page_raw(mtd, chip, |
1504 | bufpoi, page); | |
3d459559 | 1505 | else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) |
7351d3a5 FF |
1506 | ret = chip->ecc.read_subpage(mtd, chip, |
1507 | col, bytes, bufpoi); | |
956e944c | 1508 | else |
46a8cf2d SN |
1509 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
1510 | page); | |
6d77b9d0 BN |
1511 | if (ret < 0) { |
1512 | if (!aligned) | |
1513 | /* Invalidate page cache */ | |
1514 | chip->pagebuf = -1; | |
1da177e4 | 1515 | break; |
6d77b9d0 | 1516 | } |
f5bbdacc TG |
1517 | |
1518 | /* Transfer not aligned data */ | |
1519 | if (!aligned) { | |
c1194c79 | 1520 | if (!NAND_SUBPAGE_READ(chip) && !oob && |
6d77b9d0 BN |
1521 | !(mtd->ecc_stats.failed - stats.failed) && |
1522 | (ops->mode != MTD_OPS_RAW)) | |
3d459559 | 1523 | chip->pagebuf = realpage; |
6d77b9d0 BN |
1524 | else |
1525 | /* Invalidate page cache */ | |
1526 | chip->pagebuf = -1; | |
4bf63fcb | 1527 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1528 | } |
1529 | ||
8593fbc6 TG |
1530 | buf += bytes; |
1531 | ||
1532 | if (unlikely(oob)) { | |
9aca334e | 1533 | |
b64d39d8 ML |
1534 | int toread = min(oobreadlen, max_oobsize); |
1535 | ||
1536 | if (toread) { | |
1537 | oob = nand_transfer_oob(chip, | |
1538 | oob, ops, toread); | |
1539 | oobreadlen -= toread; | |
1540 | } | |
8593fbc6 TG |
1541 | } |
1542 | ||
f5bbdacc TG |
1543 | if (!(chip->options & NAND_NO_READRDY)) { |
1544 | /* | |
1545 | * Apply delay or wait for ready/busy pin. Do | |
1546 | * this before the AUTOINCR check, so no | |
1547 | * problems arise if a chip which does auto | |
1548 | * increment is marked as NOAUTOINCR by the | |
1549 | * board driver. | |
1550 | */ | |
1551 | if (!chip->dev_ready) | |
1552 | udelay(chip->chip_delay); | |
1553 | else | |
1554 | nand_wait_ready(mtd); | |
1da177e4 | 1555 | } |
8593fbc6 | 1556 | } else { |
4bf63fcb | 1557 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 TG |
1558 | buf += bytes; |
1559 | } | |
1da177e4 | 1560 | |
f5bbdacc | 1561 | readlen -= bytes; |
61b03bd7 | 1562 | |
f5bbdacc | 1563 | if (!readlen) |
61b03bd7 | 1564 | break; |
1da177e4 | 1565 | |
8b6e50c9 | 1566 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1567 | col = 0; |
1568 | /* Increment page address */ | |
1569 | realpage++; | |
1570 | ||
ace4dfee | 1571 | page = realpage & chip->pagemask; |
1da177e4 LT |
1572 | /* Check, if we cross a chip boundary */ |
1573 | if (!page) { | |
1574 | chipnr++; | |
ace4dfee TG |
1575 | chip->select_chip(mtd, -1); |
1576 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1577 | } |
f5bbdacc | 1578 | |
8b6e50c9 BN |
1579 | /* |
1580 | * Check, if the chip supports auto page increment or if we | |
1581 | * have hit a block boundary. | |
e0c7d767 | 1582 | */ |
f5bbdacc | 1583 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
61b03bd7 | 1584 | sndcmd = 1; |
1da177e4 LT |
1585 | } |
1586 | ||
8593fbc6 | 1587 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1588 | if (oob) |
1589 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1590 | |
f5bbdacc TG |
1591 | if (ret) |
1592 | return ret; | |
1593 | ||
9a1fcdfd TG |
1594 | if (mtd->ecc_stats.failed - stats.failed) |
1595 | return -EBADMSG; | |
1596 | ||
1597 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
f5bbdacc TG |
1598 | } |
1599 | ||
1600 | /** | |
25985edc | 1601 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1602 | * @mtd: MTD device structure |
1603 | * @from: offset to read from | |
1604 | * @len: number of bytes to read | |
1605 | * @retlen: pointer to variable to store the number of read bytes | |
1606 | * @buf: the databuffer to put data | |
f5bbdacc | 1607 | * |
8b6e50c9 | 1608 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1609 | */ |
1610 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1611 | size_t *retlen, uint8_t *buf) | |
1612 | { | |
8593fbc6 | 1613 | struct nand_chip *chip = mtd->priv; |
4a89ff88 | 1614 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1615 | int ret; |
1616 | ||
8593fbc6 | 1617 | nand_get_device(chip, mtd, FL_READING); |
4a89ff88 BN |
1618 | ops.len = len; |
1619 | ops.datbuf = buf; | |
1620 | ops.oobbuf = NULL; | |
23b1a99b | 1621 | ops.mode = 0; |
4a89ff88 | 1622 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1623 | *retlen = ops.retlen; |
f5bbdacc | 1624 | nand_release_device(mtd); |
f5bbdacc | 1625 | return ret; |
1da177e4 LT |
1626 | } |
1627 | ||
7bc3312b | 1628 | /** |
7854d3f7 | 1629 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1630 | * @mtd: mtd info structure |
1631 | * @chip: nand chip info structure | |
1632 | * @page: page number to read | |
1633 | * @sndcmd: flag whether to issue read command or not | |
7bc3312b TG |
1634 | */ |
1635 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1636 | int page, int sndcmd) | |
1637 | { | |
1638 | if (sndcmd) { | |
1639 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1640 | sndcmd = 0; | |
1641 | } | |
1642 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1643 | return sndcmd; | |
1644 | } | |
1645 | ||
1646 | /** | |
7854d3f7 | 1647 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1648 | * with syndromes |
8b6e50c9 BN |
1649 | * @mtd: mtd info structure |
1650 | * @chip: nand chip info structure | |
1651 | * @page: page number to read | |
1652 | * @sndcmd: flag whether to issue read command or not | |
7bc3312b TG |
1653 | */ |
1654 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1655 | int page, int sndcmd) | |
1656 | { | |
1657 | uint8_t *buf = chip->oob_poi; | |
1658 | int length = mtd->oobsize; | |
1659 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1660 | int eccsize = chip->ecc.size; | |
1661 | uint8_t *bufpoi = buf; | |
1662 | int i, toread, sndrnd = 0, pos; | |
1663 | ||
1664 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1665 | for (i = 0; i < chip->ecc.steps; i++) { | |
1666 | if (sndrnd) { | |
1667 | pos = eccsize + i * (eccsize + chunk); | |
1668 | if (mtd->writesize > 512) | |
1669 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1670 | else | |
1671 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1672 | } else | |
1673 | sndrnd = 1; | |
1674 | toread = min_t(int, length, chunk); | |
1675 | chip->read_buf(mtd, bufpoi, toread); | |
1676 | bufpoi += toread; | |
1677 | length -= toread; | |
1678 | } | |
1679 | if (length > 0) | |
1680 | chip->read_buf(mtd, bufpoi, length); | |
1681 | ||
1682 | return 1; | |
1683 | } | |
1684 | ||
1685 | /** | |
7854d3f7 | 1686 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1687 | * @mtd: mtd info structure |
1688 | * @chip: nand chip info structure | |
1689 | * @page: page number to write | |
7bc3312b TG |
1690 | */ |
1691 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1692 | int page) | |
1693 | { | |
1694 | int status = 0; | |
1695 | const uint8_t *buf = chip->oob_poi; | |
1696 | int length = mtd->oobsize; | |
1697 | ||
1698 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1699 | chip->write_buf(mtd, buf, length); | |
1700 | /* Send command to program the OOB data */ | |
1701 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1702 | ||
1703 | status = chip->waitfunc(mtd, chip); | |
1704 | ||
0d420f9d | 1705 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1706 | } |
1707 | ||
1708 | /** | |
7854d3f7 | 1709 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1710 | * with syndrome - only for large page flash |
1711 | * @mtd: mtd info structure | |
1712 | * @chip: nand chip info structure | |
1713 | * @page: page number to write | |
7bc3312b TG |
1714 | */ |
1715 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1716 | struct nand_chip *chip, int page) | |
1717 | { | |
1718 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1719 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1720 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1721 | const uint8_t *bufpoi = chip->oob_poi; | |
1722 | ||
1723 | /* | |
1724 | * data-ecc-data-ecc ... ecc-oob | |
1725 | * or | |
1726 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1727 | */ | |
1728 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1729 | pos = steps * (eccsize + chunk); | |
1730 | steps = 0; | |
1731 | } else | |
8b0036ee | 1732 | pos = eccsize; |
7bc3312b TG |
1733 | |
1734 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1735 | for (i = 0; i < steps; i++) { | |
1736 | if (sndcmd) { | |
1737 | if (mtd->writesize <= 512) { | |
1738 | uint32_t fill = 0xFFFFFFFF; | |
1739 | ||
1740 | len = eccsize; | |
1741 | while (len > 0) { | |
1742 | int num = min_t(int, len, 4); | |
1743 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1744 | num); | |
1745 | len -= num; | |
1746 | } | |
1747 | } else { | |
1748 | pos = eccsize + i * (eccsize + chunk); | |
1749 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1750 | } | |
1751 | } else | |
1752 | sndcmd = 1; | |
1753 | len = min_t(int, length, chunk); | |
1754 | chip->write_buf(mtd, bufpoi, len); | |
1755 | bufpoi += len; | |
1756 | length -= len; | |
1757 | } | |
1758 | if (length > 0) | |
1759 | chip->write_buf(mtd, bufpoi, length); | |
1760 | ||
1761 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1762 | status = chip->waitfunc(mtd, chip); | |
1763 | ||
1764 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1765 | } | |
1766 | ||
1da177e4 | 1767 | /** |
7854d3f7 | 1768 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
1769 | * @mtd: MTD device structure |
1770 | * @from: offset to read from | |
1771 | * @ops: oob operations description structure | |
1da177e4 | 1772 | * |
8b6e50c9 | 1773 | * NAND read out-of-band data from the spare area. |
1da177e4 | 1774 | */ |
8593fbc6 TG |
1775 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1776 | struct mtd_oob_ops *ops) | |
1da177e4 | 1777 | { |
7bc3312b | 1778 | int page, realpage, chipnr, sndcmd = 1; |
ace4dfee | 1779 | struct nand_chip *chip = mtd->priv; |
041e4575 | 1780 | struct mtd_ecc_stats stats; |
7314e9e7 | 1781 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
7014568b VW |
1782 | int readlen = ops->ooblen; |
1783 | int len; | |
7bc3312b | 1784 | uint8_t *buf = ops->oobbuf; |
61b03bd7 | 1785 | |
289c0522 | 1786 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 1787 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 1788 | |
041e4575 BN |
1789 | stats = mtd->ecc_stats; |
1790 | ||
0612b9dd | 1791 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 1792 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1793 | else |
1794 | len = mtd->oobsize; | |
1795 | ||
1796 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
1797 | pr_debug("%s: attempt to start read outside oob\n", |
1798 | __func__); | |
03736155 AH |
1799 | return -EINVAL; |
1800 | } | |
1801 | ||
1802 | /* Do not allow reads past end of device */ | |
1803 | if (unlikely(from >= mtd->size || | |
1804 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1805 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
1806 | pr_debug("%s: attempt to read beyond end of device\n", |
1807 | __func__); | |
03736155 AH |
1808 | return -EINVAL; |
1809 | } | |
7014568b | 1810 | |
7314e9e7 | 1811 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1812 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1813 | |
7314e9e7 TG |
1814 | /* Shift to get page */ |
1815 | realpage = (int)(from >> chip->page_shift); | |
1816 | page = realpage & chip->pagemask; | |
1da177e4 | 1817 | |
f8ac0414 | 1818 | while (1) { |
0612b9dd | 1819 | if (ops->mode == MTD_OPS_RAW) |
c46f6483 BN |
1820 | sndcmd = chip->ecc.read_oob_raw(mtd, chip, page, sndcmd); |
1821 | else | |
1822 | sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); | |
7014568b VW |
1823 | |
1824 | len = min(len, readlen); | |
1825 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1826 | |
7314e9e7 TG |
1827 | if (!(chip->options & NAND_NO_READRDY)) { |
1828 | /* | |
1829 | * Apply delay or wait for ready/busy pin. Do this | |
1830 | * before the AUTOINCR check, so no problems arise if a | |
1831 | * chip which does auto increment is marked as | |
1832 | * NOAUTOINCR by the board driver. | |
19870da7 | 1833 | */ |
ace4dfee TG |
1834 | if (!chip->dev_ready) |
1835 | udelay(chip->chip_delay); | |
19870da7 TG |
1836 | else |
1837 | nand_wait_ready(mtd); | |
7314e9e7 | 1838 | } |
19870da7 | 1839 | |
7014568b | 1840 | readlen -= len; |
0d420f9d SZ |
1841 | if (!readlen) |
1842 | break; | |
1843 | ||
7314e9e7 TG |
1844 | /* Increment page address */ |
1845 | realpage++; | |
1846 | ||
1847 | page = realpage & chip->pagemask; | |
1848 | /* Check, if we cross a chip boundary */ | |
1849 | if (!page) { | |
1850 | chipnr++; | |
1851 | chip->select_chip(mtd, -1); | |
1852 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1853 | } |
7314e9e7 | 1854 | |
8b6e50c9 BN |
1855 | /* |
1856 | * Check, if the chip supports auto page increment or if we | |
1857 | * have hit a block boundary. | |
7314e9e7 TG |
1858 | */ |
1859 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) | |
1860 | sndcmd = 1; | |
1da177e4 LT |
1861 | } |
1862 | ||
7014568b | 1863 | ops->oobretlen = ops->ooblen; |
041e4575 BN |
1864 | |
1865 | if (mtd->ecc_stats.failed - stats.failed) | |
1866 | return -EBADMSG; | |
1867 | ||
1868 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
1869 | } |
1870 | ||
1871 | /** | |
8593fbc6 | 1872 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
1873 | * @mtd: MTD device structure |
1874 | * @from: offset to read from | |
1875 | * @ops: oob operation description structure | |
1da177e4 | 1876 | * |
8b6e50c9 | 1877 | * NAND read data and/or out-of-band data. |
1da177e4 | 1878 | */ |
8593fbc6 TG |
1879 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1880 | struct mtd_oob_ops *ops) | |
1da177e4 | 1881 | { |
ace4dfee | 1882 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1883 | int ret = -ENOTSUPP; |
1884 | ||
1885 | ops->retlen = 0; | |
1da177e4 LT |
1886 | |
1887 | /* Do not allow reads past end of device */ | |
7014568b | 1888 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
1889 | pr_debug("%s: attempt to read beyond end of device\n", |
1890 | __func__); | |
1da177e4 LT |
1891 | return -EINVAL; |
1892 | } | |
1893 | ||
ace4dfee | 1894 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1895 | |
f8ac0414 | 1896 | switch (ops->mode) { |
0612b9dd BN |
1897 | case MTD_OPS_PLACE_OOB: |
1898 | case MTD_OPS_AUTO_OOB: | |
1899 | case MTD_OPS_RAW: | |
8593fbc6 | 1900 | break; |
1da177e4 | 1901 | |
8593fbc6 TG |
1902 | default: |
1903 | goto out; | |
1904 | } | |
1da177e4 | 1905 | |
8593fbc6 TG |
1906 | if (!ops->datbuf) |
1907 | ret = nand_do_read_oob(mtd, from, ops); | |
1908 | else | |
1909 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1910 | |
7351d3a5 | 1911 | out: |
8593fbc6 TG |
1912 | nand_release_device(mtd); |
1913 | return ret; | |
1914 | } | |
61b03bd7 | 1915 | |
1da177e4 | 1916 | |
8593fbc6 | 1917 | /** |
7854d3f7 | 1918 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
1919 | * @mtd: mtd info structure |
1920 | * @chip: nand chip info structure | |
1921 | * @buf: data buffer | |
52ff49df | 1922 | * |
7854d3f7 | 1923 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1924 | */ |
1925 | static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1926 | const uint8_t *buf) | |
1927 | { | |
1928 | chip->write_buf(mtd, buf, mtd->writesize); | |
1929 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1da177e4 LT |
1930 | } |
1931 | ||
52ff49df | 1932 | /** |
7854d3f7 | 1933 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
1934 | * @mtd: mtd info structure |
1935 | * @chip: nand chip info structure | |
1936 | * @buf: data buffer | |
52ff49df DB |
1937 | * |
1938 | * We need a special oob layout and handling even when ECC isn't checked. | |
1939 | */ | |
7351d3a5 FF |
1940 | static void nand_write_page_raw_syndrome(struct mtd_info *mtd, |
1941 | struct nand_chip *chip, | |
1942 | const uint8_t *buf) | |
52ff49df DB |
1943 | { |
1944 | int eccsize = chip->ecc.size; | |
1945 | int eccbytes = chip->ecc.bytes; | |
1946 | uint8_t *oob = chip->oob_poi; | |
1947 | int steps, size; | |
1948 | ||
1949 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1950 | chip->write_buf(mtd, buf, eccsize); | |
1951 | buf += eccsize; | |
1952 | ||
1953 | if (chip->ecc.prepad) { | |
1954 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1955 | oob += chip->ecc.prepad; | |
1956 | } | |
1957 | ||
1958 | chip->read_buf(mtd, oob, eccbytes); | |
1959 | oob += eccbytes; | |
1960 | ||
1961 | if (chip->ecc.postpad) { | |
1962 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1963 | oob += chip->ecc.postpad; | |
1964 | } | |
1965 | } | |
1966 | ||
1967 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1968 | if (size) | |
1969 | chip->write_buf(mtd, oob, size); | |
1970 | } | |
9223a456 | 1971 | /** |
7854d3f7 | 1972 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
1973 | * @mtd: mtd info structure |
1974 | * @chip: nand chip info structure | |
1975 | * @buf: data buffer | |
9223a456 | 1976 | */ |
f75e5097 TG |
1977 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1978 | const uint8_t *buf) | |
9223a456 | 1979 | { |
f75e5097 TG |
1980 | int i, eccsize = chip->ecc.size; |
1981 | int eccbytes = chip->ecc.bytes; | |
1982 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1983 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1984 | const uint8_t *p = buf; |
8b099a39 | 1985 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1986 | |
7854d3f7 | 1987 | /* Software ECC calculation */ |
8593fbc6 TG |
1988 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
1989 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1990 | |
8593fbc6 TG |
1991 | for (i = 0; i < chip->ecc.total; i++) |
1992 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1993 | |
90424de8 | 1994 | chip->ecc.write_page_raw(mtd, chip, buf); |
f75e5097 | 1995 | } |
9223a456 | 1996 | |
f75e5097 | 1997 | /** |
7854d3f7 | 1998 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
1999 | * @mtd: mtd info structure |
2000 | * @chip: nand chip info structure | |
2001 | * @buf: data buffer | |
f75e5097 TG |
2002 | */ |
2003 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
2004 | const uint8_t *buf) | |
2005 | { | |
2006 | int i, eccsize = chip->ecc.size; | |
2007 | int eccbytes = chip->ecc.bytes; | |
2008 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2009 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2010 | const uint8_t *p = buf; |
8b099a39 | 2011 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2012 | |
f75e5097 TG |
2013 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2014 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2015 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2016 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2017 | } |
2018 | ||
f75e5097 TG |
2019 | for (i = 0; i < chip->ecc.total; i++) |
2020 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2021 | ||
2022 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
9223a456 TG |
2023 | } |
2024 | ||
61b03bd7 | 2025 | /** |
7854d3f7 | 2026 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2027 | * @mtd: mtd info structure |
2028 | * @chip: nand chip info structure | |
2029 | * @buf: data buffer | |
1da177e4 | 2030 | * |
8b6e50c9 BN |
2031 | * The hw generator calculates the error syndrome automatically. Therefore we |
2032 | * need a special oob layout and handling. | |
f75e5097 TG |
2033 | */ |
2034 | static void nand_write_page_syndrome(struct mtd_info *mtd, | |
2035 | struct nand_chip *chip, const uint8_t *buf) | |
1da177e4 | 2036 | { |
f75e5097 TG |
2037 | int i, eccsize = chip->ecc.size; |
2038 | int eccbytes = chip->ecc.bytes; | |
2039 | int eccsteps = chip->ecc.steps; | |
2040 | const uint8_t *p = buf; | |
2041 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2042 | |
f75e5097 | 2043 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2044 | |
f75e5097 TG |
2045 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2046 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2047 | |
f75e5097 TG |
2048 | if (chip->ecc.prepad) { |
2049 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2050 | oob += chip->ecc.prepad; | |
2051 | } | |
2052 | ||
2053 | chip->ecc.calculate(mtd, p, oob); | |
2054 | chip->write_buf(mtd, oob, eccbytes); | |
2055 | oob += eccbytes; | |
2056 | ||
2057 | if (chip->ecc.postpad) { | |
2058 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2059 | oob += chip->ecc.postpad; | |
1da177e4 | 2060 | } |
1da177e4 | 2061 | } |
f75e5097 TG |
2062 | |
2063 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2064 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2065 | if (i) |
2066 | chip->write_buf(mtd, oob, i); | |
2067 | } | |
2068 | ||
2069 | /** | |
956e944c | 2070 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2071 | * @mtd: MTD device structure |
2072 | * @chip: NAND chip descriptor | |
2073 | * @buf: the data to write | |
2074 | * @page: page number to write | |
2075 | * @cached: cached programming | |
2076 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2077 | */ |
2078 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
956e944c | 2079 | const uint8_t *buf, int page, int cached, int raw) |
f75e5097 TG |
2080 | { |
2081 | int status; | |
2082 | ||
2083 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2084 | ||
956e944c DW |
2085 | if (unlikely(raw)) |
2086 | chip->ecc.write_page_raw(mtd, chip, buf); | |
2087 | else | |
2088 | chip->ecc.write_page(mtd, chip, buf); | |
f75e5097 TG |
2089 | |
2090 | /* | |
7854d3f7 | 2091 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2092 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2093 | */ |
2094 | cached = 0; | |
2095 | ||
2096 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
2097 | ||
2098 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2099 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2100 | /* |
2101 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2102 | * available. |
f75e5097 TG |
2103 | */ |
2104 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2105 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2106 | page); | |
2107 | ||
2108 | if (status & NAND_STATUS_FAIL) | |
2109 | return -EIO; | |
2110 | } else { | |
2111 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2112 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2113 | } |
2114 | ||
2115 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
2116 | /* Send command to read back the data */ | |
2117 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
2118 | ||
2119 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
2120 | return -EIO; | |
09cbe581 BH |
2121 | |
2122 | /* Make sure the next page prog is preceded by a status read */ | |
2123 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); | |
f75e5097 TG |
2124 | #endif |
2125 | return 0; | |
1da177e4 LT |
2126 | } |
2127 | ||
8593fbc6 | 2128 | /** |
7854d3f7 | 2129 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2130 | * @mtd: MTD device structure |
8b6e50c9 BN |
2131 | * @oob: oob data buffer |
2132 | * @len: oob data write length | |
2133 | * @ops: oob ops structure | |
8593fbc6 | 2134 | */ |
f722013e TAA |
2135 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2136 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2137 | { |
f722013e TAA |
2138 | struct nand_chip *chip = mtd->priv; |
2139 | ||
2140 | /* | |
2141 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2142 | * data from a previous OOB read. | |
2143 | */ | |
2144 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2145 | ||
f8ac0414 | 2146 | switch (ops->mode) { |
8593fbc6 | 2147 | |
0612b9dd BN |
2148 | case MTD_OPS_PLACE_OOB: |
2149 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2150 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2151 | return oob + len; | |
2152 | ||
0612b9dd | 2153 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2154 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2155 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2156 | size_t bytes = 0; | |
8593fbc6 | 2157 | |
f8ac0414 | 2158 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2159 | /* Write request not from offset 0? */ |
7bc3312b TG |
2160 | if (unlikely(woffs)) { |
2161 | if (woffs >= free->length) { | |
2162 | woffs -= free->length; | |
2163 | continue; | |
2164 | } | |
2165 | boffs = free->offset + woffs; | |
2166 | bytes = min_t(size_t, len, | |
2167 | (free->length - woffs)); | |
2168 | woffs = 0; | |
2169 | } else { | |
2170 | bytes = min_t(size_t, len, free->length); | |
2171 | boffs = free->offset; | |
2172 | } | |
8b0036ee | 2173 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2174 | oob += bytes; |
2175 | } | |
2176 | return oob; | |
2177 | } | |
2178 | default: | |
2179 | BUG(); | |
2180 | } | |
2181 | return NULL; | |
2182 | } | |
2183 | ||
f8ac0414 | 2184 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2185 | |
2186 | /** | |
7854d3f7 | 2187 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2188 | * @mtd: MTD device structure |
2189 | * @to: offset to write to | |
2190 | * @ops: oob operations description structure | |
1da177e4 | 2191 | * |
8b6e50c9 | 2192 | * NAND write with ECC. |
1da177e4 | 2193 | */ |
8593fbc6 TG |
2194 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2195 | struct mtd_oob_ops *ops) | |
1da177e4 | 2196 | { |
29072b96 | 2197 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2198 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2199 | uint32_t writelen = ops->len; |
782ce79a ML |
2200 | |
2201 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2202 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2203 | mtd->oobavail : mtd->oobsize; |
2204 | ||
8593fbc6 TG |
2205 | uint8_t *oob = ops->oobbuf; |
2206 | uint8_t *buf = ops->datbuf; | |
29072b96 | 2207 | int ret, subpage; |
1da177e4 | 2208 | |
8593fbc6 | 2209 | ops->retlen = 0; |
29072b96 TG |
2210 | if (!writelen) |
2211 | return 0; | |
1da177e4 | 2212 | |
8b6e50c9 | 2213 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2214 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2215 | pr_notice("%s: attempt to write non page aligned data\n", |
2216 | __func__); | |
1da177e4 LT |
2217 | return -EINVAL; |
2218 | } | |
2219 | ||
29072b96 TG |
2220 | column = to & (mtd->writesize - 1); |
2221 | subpage = column || (writelen & (mtd->writesize - 1)); | |
2222 | ||
2223 | if (subpage && oob) | |
2224 | return -EINVAL; | |
1da177e4 | 2225 | |
6a930961 TG |
2226 | chipnr = (int)(to >> chip->chip_shift); |
2227 | chip->select_chip(mtd, chipnr); | |
2228 | ||
1da177e4 LT |
2229 | /* Check, if it is write protected */ |
2230 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2231 | return -EIO; |
1da177e4 | 2232 | |
f75e5097 TG |
2233 | realpage = (int)(to >> chip->page_shift); |
2234 | page = realpage & chip->pagemask; | |
2235 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2236 | ||
2237 | /* Invalidate the page cache, when we write to the cached page */ | |
2238 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2239 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2240 | chip->pagebuf = -1; |
61b03bd7 | 2241 | |
782ce79a | 2242 | /* Don't allow multipage oob writes with offset */ |
cdcf12b2 | 2243 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) |
782ce79a ML |
2244 | return -EINVAL; |
2245 | ||
f8ac0414 | 2246 | while (1) { |
29072b96 | 2247 | int bytes = mtd->writesize; |
f75e5097 | 2248 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2249 | uint8_t *wbuf = buf; |
2250 | ||
8b6e50c9 | 2251 | /* Partial page write? */ |
29072b96 TG |
2252 | if (unlikely(column || writelen < (mtd->writesize - 1))) { |
2253 | cached = 0; | |
2254 | bytes = min_t(int, bytes - column, (int) writelen); | |
2255 | chip->pagebuf = -1; | |
2256 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2257 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2258 | wbuf = chip->buffers->databuf; | |
2259 | } | |
1da177e4 | 2260 | |
782ce79a ML |
2261 | if (unlikely(oob)) { |
2262 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2263 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2264 | oobwritelen -= len; |
f722013e TAA |
2265 | } else { |
2266 | /* We still need to erase leftover OOB data */ | |
2267 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2268 | } |
8593fbc6 | 2269 | |
29072b96 | 2270 | ret = chip->write_page(mtd, chip, wbuf, page, cached, |
0612b9dd | 2271 | (ops->mode == MTD_OPS_RAW)); |
f75e5097 TG |
2272 | if (ret) |
2273 | break; | |
2274 | ||
2275 | writelen -= bytes; | |
2276 | if (!writelen) | |
2277 | break; | |
2278 | ||
29072b96 | 2279 | column = 0; |
f75e5097 TG |
2280 | buf += bytes; |
2281 | realpage++; | |
2282 | ||
2283 | page = realpage & chip->pagemask; | |
2284 | /* Check, if we cross a chip boundary */ | |
2285 | if (!page) { | |
2286 | chipnr++; | |
2287 | chip->select_chip(mtd, -1); | |
2288 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2289 | } |
2290 | } | |
8593fbc6 | 2291 | |
8593fbc6 | 2292 | ops->retlen = ops->len - writelen; |
7014568b VW |
2293 | if (unlikely(oob)) |
2294 | ops->oobretlen = ops->ooblen; | |
1da177e4 LT |
2295 | return ret; |
2296 | } | |
2297 | ||
2af7c653 SK |
2298 | /** |
2299 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2300 | * @mtd: MTD device structure |
2301 | * @to: offset to write to | |
2302 | * @len: number of bytes to write | |
2303 | * @retlen: pointer to variable to store the number of written bytes | |
2304 | * @buf: the data to write | |
2af7c653 SK |
2305 | * |
2306 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2307 | * may for example be called by mtdoops when writing an oops while in panic. | |
2308 | */ | |
2309 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2310 | size_t *retlen, const uint8_t *buf) | |
2311 | { | |
2312 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2313 | struct mtd_oob_ops ops; |
2af7c653 SK |
2314 | int ret; |
2315 | ||
8b6e50c9 | 2316 | /* Wait for the device to get ready */ |
2af7c653 SK |
2317 | panic_nand_wait(mtd, chip, 400); |
2318 | ||
8b6e50c9 | 2319 | /* Grab the device */ |
2af7c653 SK |
2320 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2321 | ||
4a89ff88 BN |
2322 | ops.len = len; |
2323 | ops.datbuf = (uint8_t *)buf; | |
2324 | ops.oobbuf = NULL; | |
23b1a99b | 2325 | ops.mode = 0; |
2af7c653 | 2326 | |
4a89ff88 | 2327 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2328 | |
4a89ff88 | 2329 | *retlen = ops.retlen; |
2af7c653 SK |
2330 | return ret; |
2331 | } | |
2332 | ||
f75e5097 | 2333 | /** |
8593fbc6 | 2334 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2335 | * @mtd: MTD device structure |
2336 | * @to: offset to write to | |
2337 | * @len: number of bytes to write | |
2338 | * @retlen: pointer to variable to store the number of written bytes | |
2339 | * @buf: the data to write | |
f75e5097 | 2340 | * |
8b6e50c9 | 2341 | * NAND write with ECC. |
f75e5097 | 2342 | */ |
8593fbc6 TG |
2343 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2344 | size_t *retlen, const uint8_t *buf) | |
f75e5097 TG |
2345 | { |
2346 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2347 | struct mtd_oob_ops ops; |
f75e5097 TG |
2348 | int ret; |
2349 | ||
7bc3312b | 2350 | nand_get_device(chip, mtd, FL_WRITING); |
4a89ff88 BN |
2351 | ops.len = len; |
2352 | ops.datbuf = (uint8_t *)buf; | |
2353 | ops.oobbuf = NULL; | |
23b1a99b | 2354 | ops.mode = 0; |
4a89ff88 | 2355 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2356 | *retlen = ops.retlen; |
f75e5097 | 2357 | nand_release_device(mtd); |
8593fbc6 | 2358 | return ret; |
f75e5097 | 2359 | } |
7314e9e7 | 2360 | |
1da177e4 | 2361 | /** |
8593fbc6 | 2362 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2363 | * @mtd: MTD device structure |
2364 | * @to: offset to write to | |
2365 | * @ops: oob operation description structure | |
1da177e4 | 2366 | * |
8b6e50c9 | 2367 | * NAND write out-of-band. |
1da177e4 | 2368 | */ |
8593fbc6 TG |
2369 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2370 | struct mtd_oob_ops *ops) | |
1da177e4 | 2371 | { |
03736155 | 2372 | int chipnr, page, status, len; |
ace4dfee | 2373 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2374 | |
289c0522 | 2375 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2376 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2377 | |
0612b9dd | 2378 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2379 | len = chip->ecc.layout->oobavail; |
2380 | else | |
2381 | len = mtd->oobsize; | |
2382 | ||
1da177e4 | 2383 | /* Do not allow write past end of page */ |
03736155 | 2384 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2385 | pr_debug("%s: attempt to write past end of page\n", |
2386 | __func__); | |
1da177e4 LT |
2387 | return -EINVAL; |
2388 | } | |
2389 | ||
03736155 | 2390 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2391 | pr_debug("%s: attempt to start write outside oob\n", |
2392 | __func__); | |
03736155 AH |
2393 | return -EINVAL; |
2394 | } | |
2395 | ||
775adc3d | 2396 | /* Do not allow write past end of device */ |
03736155 AH |
2397 | if (unlikely(to >= mtd->size || |
2398 | ops->ooboffs + ops->ooblen > | |
2399 | ((mtd->size >> chip->page_shift) - | |
2400 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2401 | pr_debug("%s: attempt to write beyond end of device\n", |
2402 | __func__); | |
03736155 AH |
2403 | return -EINVAL; |
2404 | } | |
2405 | ||
7314e9e7 | 2406 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2407 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2408 | |
7314e9e7 TG |
2409 | /* Shift to get page */ |
2410 | page = (int)(to >> chip->page_shift); | |
2411 | ||
2412 | /* | |
2413 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2414 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2415 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2416 | * it in the doc2000 driver in August 1999. dwmw2. | |
2417 | */ | |
ace4dfee | 2418 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2419 | |
2420 | /* Check, if it is write protected */ | |
2421 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2422 | return -EROFS; |
61b03bd7 | 2423 | |
1da177e4 | 2424 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2425 | if (page == chip->pagebuf) |
2426 | chip->pagebuf = -1; | |
1da177e4 | 2427 | |
f722013e | 2428 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2429 | |
0612b9dd | 2430 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2431 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2432 | else | |
2433 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2434 | |
7bc3312b TG |
2435 | if (status) |
2436 | return status; | |
1da177e4 | 2437 | |
7014568b | 2438 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2439 | |
7bc3312b | 2440 | return 0; |
8593fbc6 TG |
2441 | } |
2442 | ||
2443 | /** | |
2444 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2445 | * @mtd: MTD device structure |
2446 | * @to: offset to write to | |
2447 | * @ops: oob operation description structure | |
8593fbc6 TG |
2448 | */ |
2449 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2450 | struct mtd_oob_ops *ops) | |
2451 | { | |
8593fbc6 TG |
2452 | struct nand_chip *chip = mtd->priv; |
2453 | int ret = -ENOTSUPP; | |
2454 | ||
2455 | ops->retlen = 0; | |
2456 | ||
2457 | /* Do not allow writes past end of device */ | |
7014568b | 2458 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2459 | pr_debug("%s: attempt to write beyond end of device\n", |
2460 | __func__); | |
8593fbc6 TG |
2461 | return -EINVAL; |
2462 | } | |
2463 | ||
7bc3312b | 2464 | nand_get_device(chip, mtd, FL_WRITING); |
8593fbc6 | 2465 | |
f8ac0414 | 2466 | switch (ops->mode) { |
0612b9dd BN |
2467 | case MTD_OPS_PLACE_OOB: |
2468 | case MTD_OPS_AUTO_OOB: | |
2469 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2470 | break; |
2471 | ||
2472 | default: | |
2473 | goto out; | |
2474 | } | |
2475 | ||
2476 | if (!ops->datbuf) | |
2477 | ret = nand_do_write_oob(mtd, to, ops); | |
2478 | else | |
2479 | ret = nand_do_write_ops(mtd, to, ops); | |
2480 | ||
7351d3a5 | 2481 | out: |
1da177e4 | 2482 | nand_release_device(mtd); |
1da177e4 LT |
2483 | return ret; |
2484 | } | |
2485 | ||
1da177e4 | 2486 | /** |
7854d3f7 | 2487 | * single_erase_cmd - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2488 | * @mtd: MTD device structure |
2489 | * @page: the page address of the block which will be erased | |
1da177e4 | 2490 | * |
8b6e50c9 | 2491 | * Standard erase command for NAND chips. |
1da177e4 | 2492 | */ |
e0c7d767 | 2493 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2494 | { |
ace4dfee | 2495 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2496 | /* Send commands to erase a block */ |
ace4dfee TG |
2497 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2498 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2499 | } |
2500 | ||
2501 | /** | |
7854d3f7 | 2502 | * multi_erase_cmd - [GENERIC] AND specific block erase command function |
8b6e50c9 BN |
2503 | * @mtd: MTD device structure |
2504 | * @page: the page address of the block which will be erased | |
1da177e4 | 2505 | * |
8b6e50c9 | 2506 | * AND multi block erase command function. Erase 4 consecutive blocks. |
1da177e4 | 2507 | */ |
e0c7d767 | 2508 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2509 | { |
ace4dfee | 2510 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2511 | /* Send commands to erase a block */ |
ace4dfee TG |
2512 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2513 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2514 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2515 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
2516 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2517 | } |
2518 | ||
2519 | /** | |
2520 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2521 | * @mtd: MTD device structure |
2522 | * @instr: erase instruction | |
1da177e4 | 2523 | * |
8b6e50c9 | 2524 | * Erase one ore more blocks. |
1da177e4 | 2525 | */ |
e0c7d767 | 2526 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2527 | { |
e0c7d767 | 2528 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2529 | } |
61b03bd7 | 2530 | |
30f464b7 | 2531 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 2532 | /** |
7854d3f7 | 2533 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2534 | * @mtd: MTD device structure |
2535 | * @instr: erase instruction | |
2536 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2537 | * |
8b6e50c9 | 2538 | * Erase one ore more blocks. |
1da177e4 | 2539 | */ |
ace4dfee TG |
2540 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2541 | int allowbbt) | |
1da177e4 | 2542 | { |
69423d99 | 2543 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2544 | struct nand_chip *chip = mtd->priv; |
f8ac0414 | 2545 | loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0}; |
ace4dfee | 2546 | unsigned int bbt_masked_page = 0xffffffff; |
69423d99 | 2547 | loff_t len; |
1da177e4 | 2548 | |
289c0522 BN |
2549 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2550 | __func__, (unsigned long long)instr->addr, | |
2551 | (unsigned long long)instr->len); | |
1da177e4 | 2552 | |
6fe5a6ac | 2553 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2554 | return -EINVAL; |
1da177e4 | 2555 | |
1da177e4 | 2556 | /* Grab the lock and see if the device is available */ |
ace4dfee | 2557 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
2558 | |
2559 | /* Shift to get first page */ | |
ace4dfee TG |
2560 | page = (int)(instr->addr >> chip->page_shift); |
2561 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2562 | |
2563 | /* Calculate pages in each block */ | |
ace4dfee | 2564 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2565 | |
2566 | /* Select the NAND device */ | |
ace4dfee | 2567 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2568 | |
1da177e4 LT |
2569 | /* Check, if it is write protected */ |
2570 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2571 | pr_debug("%s: device is write protected!\n", |
2572 | __func__); | |
1da177e4 LT |
2573 | instr->state = MTD_ERASE_FAILED; |
2574 | goto erase_exit; | |
2575 | } | |
2576 | ||
ace4dfee TG |
2577 | /* |
2578 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
2579 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
2580 | * can not be matched. This is also done when the bbt is actually | |
7854d3f7 | 2581 | * erased to avoid recursive updates. |
ace4dfee TG |
2582 | */ |
2583 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
2584 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 2585 | |
1da177e4 LT |
2586 | /* Loop through the pages */ |
2587 | len = instr->len; | |
2588 | ||
2589 | instr->state = MTD_ERASING; | |
2590 | ||
2591 | while (len) { | |
12183a20 | 2592 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2593 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2594 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2595 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2596 | __func__, page); | |
1da177e4 LT |
2597 | instr->state = MTD_ERASE_FAILED; |
2598 | goto erase_exit; | |
2599 | } | |
61b03bd7 | 2600 | |
ace4dfee TG |
2601 | /* |
2602 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2603 | * contains the current cached page. |
ace4dfee TG |
2604 | */ |
2605 | if (page <= chip->pagebuf && chip->pagebuf < | |
2606 | (page + pages_per_block)) | |
2607 | chip->pagebuf = -1; | |
1da177e4 | 2608 | |
ace4dfee | 2609 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2610 | |
7bc3312b | 2611 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2612 | |
ace4dfee TG |
2613 | /* |
2614 | * See if operation failed and additional status checks are | |
2615 | * available | |
2616 | */ | |
2617 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2618 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2619 | status, page); | |
068e3c0a | 2620 | |
1da177e4 | 2621 | /* See if block erase succeeded */ |
a4ab4c5d | 2622 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2623 | pr_debug("%s: failed erase, page 0x%08x\n", |
2624 | __func__, page); | |
1da177e4 | 2625 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2626 | instr->fail_addr = |
2627 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2628 | goto erase_exit; |
2629 | } | |
30f464b7 | 2630 | |
ace4dfee TG |
2631 | /* |
2632 | * If BBT requires refresh, set the BBT rewrite flag to the | |
8b6e50c9 | 2633 | * page being erased. |
ace4dfee TG |
2634 | */ |
2635 | if (bbt_masked_page != 0xffffffff && | |
2636 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
69423d99 AH |
2637 | rewrite_bbt[chipnr] = |
2638 | ((loff_t)page << chip->page_shift); | |
61b03bd7 | 2639 | |
1da177e4 | 2640 | /* Increment page address and decrement length */ |
ace4dfee | 2641 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
2642 | page += pages_per_block; |
2643 | ||
2644 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2645 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2646 | chipnr++; |
ace4dfee TG |
2647 | chip->select_chip(mtd, -1); |
2648 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 2649 | |
ace4dfee TG |
2650 | /* |
2651 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
8b6e50c9 | 2652 | * page mask to see if this BBT should be rewritten. |
ace4dfee TG |
2653 | */ |
2654 | if (bbt_masked_page != 0xffffffff && | |
2655 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
2656 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
2657 | BBT_PAGE_MASK; | |
1da177e4 LT |
2658 | } |
2659 | } | |
2660 | instr->state = MTD_ERASE_DONE; | |
2661 | ||
7351d3a5 | 2662 | erase_exit: |
1da177e4 LT |
2663 | |
2664 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2665 | |
2666 | /* Deselect and wake up anyone waiting on the device */ | |
2667 | nand_release_device(mtd); | |
2668 | ||
49defc01 DW |
2669 | /* Do call back function */ |
2670 | if (!ret) | |
2671 | mtd_erase_callback(instr); | |
2672 | ||
ace4dfee TG |
2673 | /* |
2674 | * If BBT requires refresh and erase was successful, rewrite any | |
8b6e50c9 | 2675 | * selected bad block tables. |
ace4dfee TG |
2676 | */ |
2677 | if (bbt_masked_page == 0xffffffff || ret) | |
2678 | return ret; | |
2679 | ||
2680 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2681 | if (!rewrite_bbt[chipnr]) | |
2682 | continue; | |
8b6e50c9 | 2683 | /* Update the BBT for chip */ |
289c0522 BN |
2684 | pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n", |
2685 | __func__, chipnr, rewrite_bbt[chipnr], | |
2686 | chip->bbt_td->pages[chipnr]); | |
ace4dfee | 2687 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); |
30f464b7 DM |
2688 | } |
2689 | ||
1da177e4 LT |
2690 | /* Return more or less happy */ |
2691 | return ret; | |
2692 | } | |
2693 | ||
2694 | /** | |
2695 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2696 | * @mtd: MTD device structure |
1da177e4 | 2697 | * |
8b6e50c9 | 2698 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2699 | */ |
e0c7d767 | 2700 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2701 | { |
ace4dfee | 2702 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2703 | |
289c0522 | 2704 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2705 | |
2706 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2707 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 2708 | /* Release it and go back */ |
e0c7d767 | 2709 | nand_release_device(mtd); |
1da177e4 LT |
2710 | } |
2711 | ||
1da177e4 | 2712 | /** |
ace4dfee | 2713 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2714 | * @mtd: MTD device structure |
2715 | * @offs: offset relative to mtd start | |
1da177e4 | 2716 | */ |
ace4dfee | 2717 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 2718 | { |
ace4dfee | 2719 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2720 | } |
2721 | ||
2722 | /** | |
ace4dfee | 2723 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2724 | * @mtd: MTD device structure |
2725 | * @ofs: offset relative to mtd start | |
1da177e4 | 2726 | */ |
e0c7d767 | 2727 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2728 | { |
ace4dfee | 2729 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2730 | int ret; |
2731 | ||
f8ac0414 FF |
2732 | ret = nand_block_isbad(mtd, ofs); |
2733 | if (ret) { | |
8b6e50c9 | 2734 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
2735 | if (ret > 0) |
2736 | return 0; | |
e0c7d767 DW |
2737 | return ret; |
2738 | } | |
1da177e4 | 2739 | |
ace4dfee | 2740 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2741 | } |
2742 | ||
962034f4 VW |
2743 | /** |
2744 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 2745 | * @mtd: MTD device structure |
962034f4 VW |
2746 | */ |
2747 | static int nand_suspend(struct mtd_info *mtd) | |
2748 | { | |
ace4dfee | 2749 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2750 | |
ace4dfee | 2751 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2752 | } |
2753 | ||
2754 | /** | |
2755 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 2756 | * @mtd: MTD device structure |
962034f4 VW |
2757 | */ |
2758 | static void nand_resume(struct mtd_info *mtd) | |
2759 | { | |
ace4dfee | 2760 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2761 | |
ace4dfee | 2762 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2763 | nand_release_device(mtd); |
2764 | else | |
d0370219 BN |
2765 | pr_err("%s called for a chip which is not in suspended state\n", |
2766 | __func__); | |
962034f4 VW |
2767 | } |
2768 | ||
8b6e50c9 | 2769 | /* Set default functions */ |
ace4dfee | 2770 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2771 | { |
1da177e4 | 2772 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2773 | if (!chip->chip_delay) |
2774 | chip->chip_delay = 20; | |
1da177e4 LT |
2775 | |
2776 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2777 | if (chip->cmdfunc == NULL) |
2778 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2779 | |
2780 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2781 | if (chip->waitfunc == NULL) |
2782 | chip->waitfunc = nand_wait; | |
2783 | ||
2784 | if (!chip->select_chip) | |
2785 | chip->select_chip = nand_select_chip; | |
2786 | if (!chip->read_byte) | |
2787 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2788 | if (!chip->read_word) | |
2789 | chip->read_word = nand_read_word; | |
2790 | if (!chip->block_bad) | |
2791 | chip->block_bad = nand_block_bad; | |
2792 | if (!chip->block_markbad) | |
2793 | chip->block_markbad = nand_default_block_markbad; | |
2794 | if (!chip->write_buf) | |
2795 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2796 | if (!chip->read_buf) | |
2797 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
2798 | if (!chip->verify_buf) | |
2799 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; | |
2800 | if (!chip->scan_bbt) | |
2801 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2802 | |
2803 | if (!chip->controller) { | |
2804 | chip->controller = &chip->hwcontrol; | |
2805 | spin_lock_init(&chip->controller->lock); | |
2806 | init_waitqueue_head(&chip->controller->wq); | |
2807 | } | |
2808 | ||
7aa65bfd TG |
2809 | } |
2810 | ||
8b6e50c9 | 2811 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
2812 | static void sanitize_string(uint8_t *s, size_t len) |
2813 | { | |
2814 | ssize_t i; | |
2815 | ||
8b6e50c9 | 2816 | /* Null terminate */ |
d1e1f4e4 FF |
2817 | s[len - 1] = 0; |
2818 | ||
8b6e50c9 | 2819 | /* Remove non printable chars */ |
d1e1f4e4 FF |
2820 | for (i = 0; i < len - 1; i++) { |
2821 | if (s[i] < ' ' || s[i] > 127) | |
2822 | s[i] = '?'; | |
2823 | } | |
2824 | ||
8b6e50c9 | 2825 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
2826 | strim(s); |
2827 | } | |
2828 | ||
2829 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
2830 | { | |
2831 | int i; | |
2832 | while (len--) { | |
2833 | crc ^= *p++ << 8; | |
2834 | for (i = 0; i < 8; i++) | |
2835 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
2836 | } | |
2837 | ||
2838 | return crc; | |
2839 | } | |
2840 | ||
6fb277ba | 2841 | /* |
8b6e50c9 | 2842 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
2843 | */ |
2844 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 2845 | int *busw) |
6fb277ba FF |
2846 | { |
2847 | struct nand_onfi_params *p = &chip->onfi_params; | |
2848 | int i; | |
2849 | int val; | |
2850 | ||
7854d3f7 | 2851 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
2852 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
2853 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
2854 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
2855 | return 0; | |
2856 | ||
6fb277ba FF |
2857 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
2858 | for (i = 0; i < 3; i++) { | |
2859 | chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); | |
2860 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == | |
2861 | le16_to_cpu(p->crc)) { | |
9a4d4d69 | 2862 | pr_info("ONFI param page %d valid\n", i); |
6fb277ba FF |
2863 | break; |
2864 | } | |
2865 | } | |
2866 | ||
2867 | if (i == 3) | |
2868 | return 0; | |
2869 | ||
8b6e50c9 | 2870 | /* Check version */ |
6fb277ba | 2871 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
2872 | if (val & (1 << 5)) |
2873 | chip->onfi_version = 23; | |
2874 | else if (val & (1 << 4)) | |
6fb277ba FF |
2875 | chip->onfi_version = 22; |
2876 | else if (val & (1 << 3)) | |
2877 | chip->onfi_version = 21; | |
2878 | else if (val & (1 << 2)) | |
2879 | chip->onfi_version = 20; | |
b7b1a29d | 2880 | else if (val & (1 << 1)) |
6fb277ba | 2881 | chip->onfi_version = 10; |
b7b1a29d BN |
2882 | else |
2883 | chip->onfi_version = 0; | |
2884 | ||
2885 | if (!chip->onfi_version) { | |
d0370219 | 2886 | pr_info("%s: unsupported ONFI version: %d\n", __func__, val); |
b7b1a29d BN |
2887 | return 0; |
2888 | } | |
6fb277ba FF |
2889 | |
2890 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
2891 | sanitize_string(p->model, sizeof(p->model)); | |
2892 | if (!mtd->name) | |
2893 | mtd->name = p->model; | |
2894 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
2895 | mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; | |
2896 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
63795755 MC |
2897 | chip->chipsize = le32_to_cpu(p->blocks_per_lun); |
2898 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
08c248fb | 2899 | *busw = 0; |
6fb277ba | 2900 | if (le16_to_cpu(p->features) & 1) |
08c248fb | 2901 | *busw = NAND_BUSWIDTH_16; |
6fb277ba FF |
2902 | |
2903 | chip->options &= ~NAND_CHIPOPTIONS_MSK; | |
2904 | chip->options |= (NAND_NO_READRDY | | |
2905 | NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK; | |
2906 | ||
d42b5de3 | 2907 | pr_info("ONFI flash detected\n"); |
6fb277ba FF |
2908 | return 1; |
2909 | } | |
2910 | ||
7aa65bfd | 2911 | /* |
8b6e50c9 | 2912 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
2913 | */ |
2914 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 2915 | struct nand_chip *chip, |
7351d3a5 FF |
2916 | int busw, |
2917 | int *maf_id, int *dev_id, | |
5e81e88a | 2918 | struct nand_flash_dev *type) |
7aa65bfd | 2919 | { |
d1e1f4e4 | 2920 | int i, maf_idx; |
426c457a | 2921 | u8 id_data[8]; |
6fb277ba | 2922 | int ret; |
1da177e4 LT |
2923 | |
2924 | /* Select the device */ | |
ace4dfee | 2925 | chip->select_chip(mtd, 0); |
1da177e4 | 2926 | |
ef89a880 KB |
2927 | /* |
2928 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 2929 | * after power-up. |
ef89a880 KB |
2930 | */ |
2931 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
2932 | ||
1da177e4 | 2933 | /* Send the command for reading device ID */ |
ace4dfee | 2934 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
2935 | |
2936 | /* Read manufacturer and device IDs */ | |
ace4dfee | 2937 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 2938 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 2939 | |
8b6e50c9 BN |
2940 | /* |
2941 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
2942 | * interface concerns can cause random data which looks like a |
2943 | * possibly credible NAND flash to appear. If the two results do | |
2944 | * not match, ignore the device completely. | |
2945 | */ | |
2946 | ||
2947 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
2948 | ||
d1e1f4e4 | 2949 | for (i = 0; i < 2; i++) |
426c457a | 2950 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 2951 | |
d1e1f4e4 | 2952 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
9a4d4d69 | 2953 | pr_info("%s: second ID read did not match " |
d0370219 BN |
2954 | "%02x,%02x against %02x,%02x\n", __func__, |
2955 | *maf_id, *dev_id, id_data[0], id_data[1]); | |
ed8165c7 BD |
2956 | return ERR_PTR(-ENODEV); |
2957 | } | |
2958 | ||
7aa65bfd | 2959 | if (!type) |
5e81e88a DW |
2960 | type = nand_flash_ids; |
2961 | ||
2962 | for (; type->name != NULL; type++) | |
d1e1f4e4 | 2963 | if (*dev_id == type->id) |
f8ac0414 | 2964 | break; |
5e81e88a | 2965 | |
d1e1f4e4 FF |
2966 | chip->onfi_version = 0; |
2967 | if (!type->name || !type->pagesize) { | |
6fb277ba | 2968 | /* Check is chip is ONFI compliant */ |
08c248fb | 2969 | ret = nand_flash_detect_onfi(mtd, chip, &busw); |
6fb277ba FF |
2970 | if (ret) |
2971 | goto ident_done; | |
d1e1f4e4 FF |
2972 | } |
2973 | ||
2974 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
2975 | ||
2976 | /* Read entire ID string */ | |
2977 | ||
2978 | for (i = 0; i < 8; i++) | |
2979 | id_data[i] = chip->read_byte(mtd); | |
2980 | ||
5e81e88a | 2981 | if (!type->name) |
7aa65bfd TG |
2982 | return ERR_PTR(-ENODEV); |
2983 | ||
ba0251fe TG |
2984 | if (!mtd->name) |
2985 | mtd->name = type->name; | |
2986 | ||
69423d99 | 2987 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 2988 | |
12a40a57 | 2989 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 2990 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
2991 | busw = chip->init_size(mtd, chip, id_data); |
2992 | } else if (!type->pagesize) { | |
7aa65bfd | 2993 | int extid; |
29072b96 | 2994 | /* The 3rd id byte holds MLC / multichip data */ |
426c457a | 2995 | chip->cellinfo = id_data[2]; |
7aa65bfd | 2996 | /* The 4th id byte is the important one */ |
426c457a | 2997 | extid = id_data[3]; |
61b03bd7 | 2998 | |
426c457a KC |
2999 | /* |
3000 | * Field definitions are in the following datasheets: | |
3001 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
34c5bf6c | 3002 | * New style (6 byte ID): Samsung K9GBG08U0M (p.40) |
426c457a KC |
3003 | * |
3004 | * Check for wraparound + Samsung ID + nonzero 6th byte | |
3005 | * to decide what to do. | |
3006 | */ | |
3007 | if (id_data[0] == id_data[6] && id_data[1] == id_data[7] && | |
3008 | id_data[0] == NAND_MFR_SAMSUNG && | |
cfe3fdad | 3009 | (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && |
426c457a KC |
3010 | id_data[5] != 0x00) { |
3011 | /* Calc pagesize */ | |
3012 | mtd->writesize = 2048 << (extid & 0x03); | |
3013 | extid >>= 2; | |
3014 | /* Calc oobsize */ | |
34c5bf6c BN |
3015 | switch (extid & 0x03) { |
3016 | case 1: | |
3017 | mtd->oobsize = 128; | |
3018 | break; | |
3019 | case 2: | |
3020 | mtd->oobsize = 218; | |
3021 | break; | |
3022 | case 3: | |
3023 | mtd->oobsize = 400; | |
3024 | break; | |
3025 | default: | |
3026 | mtd->oobsize = 436; | |
3027 | break; | |
3028 | } | |
426c457a KC |
3029 | extid >>= 2; |
3030 | /* Calc blocksize */ | |
3031 | mtd->erasesize = (128 * 1024) << | |
3032 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3033 | busw = 0; | |
3034 | } else { | |
3035 | /* Calc pagesize */ | |
3036 | mtd->writesize = 1024 << (extid & 0x03); | |
3037 | extid >>= 2; | |
3038 | /* Calc oobsize */ | |
3039 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3040 | (mtd->writesize >> 9); | |
3041 | extid >>= 2; | |
3042 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3043 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3044 | extid >>= 2; | |
3045 | /* Get buswidth information */ | |
3046 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
3047 | } | |
7aa65bfd TG |
3048 | } else { |
3049 | /* | |
8b6e50c9 | 3050 | * Old devices have chip data hardcoded in the device id table. |
7aa65bfd | 3051 | */ |
ba0251fe TG |
3052 | mtd->erasesize = type->erasesize; |
3053 | mtd->writesize = type->pagesize; | |
4cbb9b80 | 3054 | mtd->oobsize = mtd->writesize / 32; |
ba0251fe | 3055 | busw = type->options & NAND_BUSWIDTH_16; |
2173bae8 BN |
3056 | |
3057 | /* | |
3058 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3059 | * some Spansion chips have erasesize that conflicts with size | |
8b6e50c9 | 3060 | * listed in nand_ids table. |
2173bae8 BN |
3061 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) |
3062 | */ | |
3063 | if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && | |
3064 | id_data[5] == 0x00 && id_data[6] == 0x00 && | |
3065 | id_data[7] == 0x00 && mtd->writesize == 512) { | |
3066 | mtd->erasesize = 128 * 1024; | |
3067 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3068 | } | |
7aa65bfd | 3069 | } |
d1e1f4e4 FF |
3070 | /* Get chip options, preserve non chip based options */ |
3071 | chip->options &= ~NAND_CHIPOPTIONS_MSK; | |
3072 | chip->options |= type->options & NAND_CHIPOPTIONS_MSK; | |
3073 | ||
8b6e50c9 BN |
3074 | /* |
3075 | * Check if chip is not a Samsung device. Do not clear the | |
3076 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3077 | */ |
3078 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3079 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3080 | ident_done: | |
3081 | ||
3082 | /* | |
8b6e50c9 | 3083 | * Set chip as a default. Board drivers can override it, if necessary. |
d1e1f4e4 FF |
3084 | */ |
3085 | chip->options |= NAND_NO_AUTOINCR; | |
1da177e4 | 3086 | |
7aa65bfd | 3087 | /* Try to identify manufacturer */ |
9a909867 | 3088 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3089 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3090 | break; | |
3091 | } | |
0ea4a755 | 3092 | |
7aa65bfd TG |
3093 | /* |
3094 | * Check, if buswidth is correct. Hardware drivers should set | |
8b6e50c9 | 3095 | * chip correct! |
7aa65bfd | 3096 | */ |
ace4dfee | 3097 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
9a4d4d69 | 3098 | pr_info("NAND device: Manufacturer ID:" |
d0370219 BN |
3099 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, |
3100 | *dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
9a4d4d69 | 3101 | pr_warn("NAND bus width %d instead %d bit\n", |
d0370219 BN |
3102 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3103 | busw ? 16 : 8); | |
7aa65bfd TG |
3104 | return ERR_PTR(-EINVAL); |
3105 | } | |
61b03bd7 | 3106 | |
7aa65bfd | 3107 | /* Calculate the address shift from the page size */ |
ace4dfee | 3108 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3109 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3110 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3111 | |
ace4dfee | 3112 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3113 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3114 | if (chip->chipsize & 0xffffffff) |
3115 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3116 | else { |
3117 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3118 | chip->chip_shift += 32 - 1; | |
3119 | } | |
1da177e4 | 3120 | |
26d9be11 AB |
3121 | chip->badblockbits = 8; |
3122 | ||
7aa65bfd | 3123 | /* Set the bad block position */ |
065a1ed8 | 3124 | if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16)) |
c7b28e25 | 3125 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; |
065a1ed8 BN |
3126 | else |
3127 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
61b03bd7 | 3128 | |
b60b08b0 KC |
3129 | /* |
3130 | * Bad block marker is stored in the last page of each block | |
c7b28e25 BN |
3131 | * on Samsung and Hynix MLC devices; stored in first two pages |
3132 | * of each block on Micron devices with 2KiB pages and on | |
8c342335 BN |
3133 | * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix. |
3134 | * All others scan only the first page. | |
b60b08b0 KC |
3135 | */ |
3136 | if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && | |
3137 | (*maf_id == NAND_MFR_SAMSUNG || | |
3138 | *maf_id == NAND_MFR_HYNIX)) | |
5fb1549d | 3139 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; |
c7b28e25 BN |
3140 | else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && |
3141 | (*maf_id == NAND_MFR_SAMSUNG || | |
3142 | *maf_id == NAND_MFR_HYNIX || | |
13ed7aed | 3143 | *maf_id == NAND_MFR_TOSHIBA || |
8c342335 BN |
3144 | *maf_id == NAND_MFR_AMD || |
3145 | *maf_id == NAND_MFR_MACRONIX)) || | |
c7b28e25 BN |
3146 | (mtd->writesize == 2048 && |
3147 | *maf_id == NAND_MFR_MICRON)) | |
5fb1549d | 3148 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; |
c7b28e25 | 3149 | |
7aa65bfd | 3150 | /* Check for AND chips with 4 page planes */ |
ace4dfee TG |
3151 | if (chip->options & NAND_4PAGE_ARRAY) |
3152 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 3153 | else |
ace4dfee | 3154 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd | 3155 | |
8b6e50c9 | 3156 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3157 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3158 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3159 | |
886bd33d HS |
3160 | pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s)," |
3161 | " page size: %d, OOB size: %d\n", | |
3162 | *maf_id, *dev_id, nand_manuf_ids[maf_idx].name, | |
3163 | chip->onfi_version ? chip->onfi_params.model : type->name, | |
3164 | mtd->writesize, mtd->oobsize); | |
7aa65bfd TG |
3165 | |
3166 | return type; | |
3167 | } | |
3168 | ||
7aa65bfd | 3169 | /** |
3b85c321 | 3170 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3171 | * @mtd: MTD device structure |
3172 | * @maxchips: number of chips to scan for | |
3173 | * @table: alternative NAND ID table | |
7aa65bfd | 3174 | * |
8b6e50c9 BN |
3175 | * This is the first phase of the normal nand_scan() function. It reads the |
3176 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3177 | * |
3b85c321 | 3178 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3179 | */ |
5e81e88a DW |
3180 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3181 | struct nand_flash_dev *table) | |
7aa65bfd | 3182 | { |
d1e1f4e4 | 3183 | int i, busw, nand_maf_id, nand_dev_id; |
ace4dfee | 3184 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3185 | struct nand_flash_dev *type; |
3186 | ||
7aa65bfd | 3187 | /* Get buswidth to select the correct functions */ |
ace4dfee | 3188 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 3189 | /* Set the default functions */ |
ace4dfee | 3190 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
3191 | |
3192 | /* Read the flash type */ | |
7351d3a5 FF |
3193 | type = nand_get_flash_type(mtd, chip, busw, |
3194 | &nand_maf_id, &nand_dev_id, table); | |
7aa65bfd TG |
3195 | |
3196 | if (IS_ERR(type)) { | |
b1c6e6db | 3197 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3198 | pr_warn("No NAND device found\n"); |
ace4dfee | 3199 | chip->select_chip(mtd, -1); |
7aa65bfd | 3200 | return PTR_ERR(type); |
1da177e4 LT |
3201 | } |
3202 | ||
7aa65bfd | 3203 | /* Check for a chip array */ |
e0c7d767 | 3204 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3205 | chip->select_chip(mtd, i); |
ef89a880 KB |
3206 | /* See comment in nand_get_flash_type for reset */ |
3207 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3208 | /* Send the command for reading device ID */ |
ace4dfee | 3209 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3210 | /* Read manufacturer and device IDs */ |
ace4dfee | 3211 | if (nand_maf_id != chip->read_byte(mtd) || |
d1e1f4e4 | 3212 | nand_dev_id != chip->read_byte(mtd)) |
1da177e4 LT |
3213 | break; |
3214 | } | |
3215 | if (i > 1) | |
9a4d4d69 | 3216 | pr_info("%d NAND chips detected\n", i); |
61b03bd7 | 3217 | |
1da177e4 | 3218 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3219 | chip->numchips = i; |
3220 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3221 | |
3b85c321 DW |
3222 | return 0; |
3223 | } | |
7351d3a5 | 3224 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 DW |
3225 | |
3226 | ||
3227 | /** | |
3228 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 3229 | * @mtd: MTD device structure |
3b85c321 | 3230 | * |
8b6e50c9 BN |
3231 | * This is the second phase of the normal nand_scan() function. It fills out |
3232 | * all the uninitialized function pointers with the defaults and scans for a | |
3233 | * bad block table if appropriate. | |
3b85c321 DW |
3234 | */ |
3235 | int nand_scan_tail(struct mtd_info *mtd) | |
3236 | { | |
3237 | int i; | |
3238 | struct nand_chip *chip = mtd->priv; | |
3239 | ||
e2414f4c BN |
3240 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
3241 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
3242 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
3243 | ||
4bf63fcb DW |
3244 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3245 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
3246 | if (!chip->buffers) | |
3247 | return -ENOMEM; | |
3248 | ||
7dcdcbef | 3249 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3250 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3251 | |
7aa65bfd | 3252 | /* |
8b6e50c9 | 3253 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 3254 | */ |
193bd400 | 3255 | if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3256 | switch (mtd->oobsize) { |
1da177e4 | 3257 | case 8: |
5bd34c09 | 3258 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
3259 | break; |
3260 | case 16: | |
5bd34c09 | 3261 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
3262 | break; |
3263 | case 64: | |
5bd34c09 | 3264 | chip->ecc.layout = &nand_oob_64; |
1da177e4 | 3265 | break; |
81ec5364 TG |
3266 | case 128: |
3267 | chip->ecc.layout = &nand_oob_128; | |
3268 | break; | |
1da177e4 | 3269 | default: |
d0370219 BN |
3270 | pr_warn("No oob scheme defined for oobsize %d\n", |
3271 | mtd->oobsize); | |
1da177e4 LT |
3272 | BUG(); |
3273 | } | |
3274 | } | |
61b03bd7 | 3275 | |
956e944c DW |
3276 | if (!chip->write_page) |
3277 | chip->write_page = nand_write_page; | |
3278 | ||
61b03bd7 | 3279 | /* |
8b6e50c9 | 3280 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 3281 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 3282 | */ |
956e944c | 3283 | |
ace4dfee | 3284 | switch (chip->ecc.mode) { |
6e0cb135 SN |
3285 | case NAND_ECC_HW_OOB_FIRST: |
3286 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
3287 | if (!chip->ecc.calculate || !chip->ecc.correct || | |
3288 | !chip->ecc.hwctl) { | |
9a4d4d69 | 3289 | pr_warn("No ECC functions supplied; " |
d0370219 | 3290 | "hardware ECC not possible\n"); |
6e0cb135 SN |
3291 | BUG(); |
3292 | } | |
3293 | if (!chip->ecc.read_page) | |
3294 | chip->ecc.read_page = nand_read_page_hwecc_oob_first; | |
3295 | ||
6dfc6d25 | 3296 | case NAND_ECC_HW: |
8b6e50c9 | 3297 | /* Use standard hwecc read page function? */ |
f5bbdacc TG |
3298 | if (!chip->ecc.read_page) |
3299 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
3300 | if (!chip->ecc.write_page) |
3301 | chip->ecc.write_page = nand_write_page_hwecc; | |
52ff49df DB |
3302 | if (!chip->ecc.read_page_raw) |
3303 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3304 | if (!chip->ecc.write_page_raw) | |
3305 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3306 | if (!chip->ecc.read_oob) |
3307 | chip->ecc.read_oob = nand_read_oob_std; | |
3308 | if (!chip->ecc.write_oob) | |
3309 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 3310 | |
6dfc6d25 | 3311 | case NAND_ECC_HW_SYNDROME: |
78b65179 SW |
3312 | if ((!chip->ecc.calculate || !chip->ecc.correct || |
3313 | !chip->ecc.hwctl) && | |
3314 | (!chip->ecc.read_page || | |
1c45f604 | 3315 | chip->ecc.read_page == nand_read_page_hwecc || |
78b65179 | 3316 | !chip->ecc.write_page || |
1c45f604 | 3317 | chip->ecc.write_page == nand_write_page_hwecc)) { |
9a4d4d69 | 3318 | pr_warn("No ECC functions supplied; " |
d0370219 | 3319 | "hardware ECC not possible\n"); |
6dfc6d25 TG |
3320 | BUG(); |
3321 | } | |
8b6e50c9 | 3322 | /* Use standard syndrome read/write page function? */ |
f5bbdacc TG |
3323 | if (!chip->ecc.read_page) |
3324 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
3325 | if (!chip->ecc.write_page) |
3326 | chip->ecc.write_page = nand_write_page_syndrome; | |
52ff49df DB |
3327 | if (!chip->ecc.read_page_raw) |
3328 | chip->ecc.read_page_raw = nand_read_page_raw_syndrome; | |
3329 | if (!chip->ecc.write_page_raw) | |
3330 | chip->ecc.write_page_raw = nand_write_page_raw_syndrome; | |
7bc3312b TG |
3331 | if (!chip->ecc.read_oob) |
3332 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
3333 | if (!chip->ecc.write_oob) | |
3334 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 3335 | |
ace4dfee | 3336 | if (mtd->writesize >= chip->ecc.size) |
6dfc6d25 | 3337 | break; |
9a4d4d69 | 3338 | pr_warn("%d byte HW ECC not possible on " |
d0370219 BN |
3339 | "%d byte page size, fallback to SW ECC\n", |
3340 | chip->ecc.size, mtd->writesize); | |
ace4dfee | 3341 | chip->ecc.mode = NAND_ECC_SOFT; |
61b03bd7 | 3342 | |
6dfc6d25 | 3343 | case NAND_ECC_SOFT: |
ace4dfee TG |
3344 | chip->ecc.calculate = nand_calculate_ecc; |
3345 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 3346 | chip->ecc.read_page = nand_read_page_swecc; |
3d459559 | 3347 | chip->ecc.read_subpage = nand_read_subpage; |
f75e5097 | 3348 | chip->ecc.write_page = nand_write_page_swecc; |
52ff49df DB |
3349 | chip->ecc.read_page_raw = nand_read_page_raw; |
3350 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3351 | chip->ecc.read_oob = nand_read_oob_std; |
3352 | chip->ecc.write_oob = nand_write_oob_std; | |
9a73290d SV |
3353 | if (!chip->ecc.size) |
3354 | chip->ecc.size = 256; | |
ace4dfee | 3355 | chip->ecc.bytes = 3; |
6a918bad | 3356 | chip->ecc.strength = 1; |
1da177e4 | 3357 | break; |
61b03bd7 | 3358 | |
193bd400 ID |
3359 | case NAND_ECC_SOFT_BCH: |
3360 | if (!mtd_nand_has_bch()) { | |
9a4d4d69 | 3361 | pr_warn("CONFIG_MTD_ECC_BCH not enabled\n"); |
193bd400 ID |
3362 | BUG(); |
3363 | } | |
3364 | chip->ecc.calculate = nand_bch_calculate_ecc; | |
3365 | chip->ecc.correct = nand_bch_correct_data; | |
3366 | chip->ecc.read_page = nand_read_page_swecc; | |
3367 | chip->ecc.read_subpage = nand_read_subpage; | |
3368 | chip->ecc.write_page = nand_write_page_swecc; | |
3369 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3370 | chip->ecc.write_page_raw = nand_write_page_raw; | |
3371 | chip->ecc.read_oob = nand_read_oob_std; | |
3372 | chip->ecc.write_oob = nand_write_oob_std; | |
3373 | /* | |
3374 | * Board driver should supply ecc.size and ecc.bytes values to | |
3375 | * select how many bits are correctable; see nand_bch_init() | |
8b6e50c9 BN |
3376 | * for details. Otherwise, default to 4 bits for large page |
3377 | * devices. | |
193bd400 ID |
3378 | */ |
3379 | if (!chip->ecc.size && (mtd->oobsize >= 64)) { | |
3380 | chip->ecc.size = 512; | |
3381 | chip->ecc.bytes = 7; | |
3382 | } | |
3383 | chip->ecc.priv = nand_bch_init(mtd, | |
3384 | chip->ecc.size, | |
3385 | chip->ecc.bytes, | |
3386 | &chip->ecc.layout); | |
3387 | if (!chip->ecc.priv) { | |
9a4d4d69 | 3388 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
3389 | BUG(); |
3390 | } | |
6a918bad MD |
3391 | chip->ecc.strength = |
3392 | chip->ecc.bytes*8 / fls(8*chip->ecc.size); | |
193bd400 ID |
3393 | break; |
3394 | ||
61b03bd7 | 3395 | case NAND_ECC_NONE: |
9a4d4d69 | 3396 | pr_warn("NAND_ECC_NONE selected by board driver. " |
d0370219 | 3397 | "This is not recommended!\n"); |
8593fbc6 TG |
3398 | chip->ecc.read_page = nand_read_page_raw; |
3399 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b | 3400 | chip->ecc.read_oob = nand_read_oob_std; |
52ff49df DB |
3401 | chip->ecc.read_page_raw = nand_read_page_raw; |
3402 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b | 3403 | chip->ecc.write_oob = nand_write_oob_std; |
ace4dfee TG |
3404 | chip->ecc.size = mtd->writesize; |
3405 | chip->ecc.bytes = 0; | |
6a918bad | 3406 | chip->ecc.strength = 0; |
1da177e4 | 3407 | break; |
956e944c | 3408 | |
1da177e4 | 3409 | default: |
d0370219 | 3410 | pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode); |
61b03bd7 | 3411 | BUG(); |
1da177e4 | 3412 | } |
61b03bd7 | 3413 | |
9ce244b3 | 3414 | /* For many systems, the standard OOB write also works for raw */ |
c46f6483 BN |
3415 | if (!chip->ecc.read_oob_raw) |
3416 | chip->ecc.read_oob_raw = chip->ecc.read_oob; | |
9ce244b3 BN |
3417 | if (!chip->ecc.write_oob_raw) |
3418 | chip->ecc.write_oob_raw = chip->ecc.write_oob; | |
3419 | ||
5bd34c09 TG |
3420 | /* |
3421 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 3422 | * the out of band area. |
5bd34c09 TG |
3423 | */ |
3424 | chip->ecc.layout->oobavail = 0; | |
81d19b04 DB |
3425 | for (i = 0; chip->ecc.layout->oobfree[i].length |
3426 | && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) | |
5bd34c09 TG |
3427 | chip->ecc.layout->oobavail += |
3428 | chip->ecc.layout->oobfree[i].length; | |
1f92267c | 3429 | mtd->oobavail = chip->ecc.layout->oobavail; |
5bd34c09 | 3430 | |
7aa65bfd TG |
3431 | /* |
3432 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 3433 | * mode. |
7aa65bfd | 3434 | */ |
ace4dfee | 3435 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
f8ac0414 | 3436 | if (chip->ecc.steps * chip->ecc.size != mtd->writesize) { |
9a4d4d69 | 3437 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 3438 | BUG(); |
1da177e4 | 3439 | } |
f5bbdacc | 3440 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 3441 | |
8b6e50c9 | 3442 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
29072b96 TG |
3443 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && |
3444 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
f8ac0414 | 3445 | switch (chip->ecc.steps) { |
29072b96 TG |
3446 | case 2: |
3447 | mtd->subpage_sft = 1; | |
3448 | break; | |
3449 | case 4: | |
3450 | case 8: | |
81ec5364 | 3451 | case 16: |
29072b96 TG |
3452 | mtd->subpage_sft = 2; |
3453 | break; | |
3454 | } | |
3455 | } | |
3456 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
3457 | ||
04bbd0ea | 3458 | /* Initialize state */ |
ace4dfee | 3459 | chip->state = FL_READY; |
1da177e4 LT |
3460 | |
3461 | /* De-select the device */ | |
ace4dfee | 3462 | chip->select_chip(mtd, -1); |
1da177e4 LT |
3463 | |
3464 | /* Invalidate the pagebuffer reference */ | |
ace4dfee | 3465 | chip->pagebuf = -1; |
1da177e4 LT |
3466 | |
3467 | /* Fill in remaining MTD driver data */ | |
3468 | mtd->type = MTD_NANDFLASH; | |
93edbad6 ML |
3469 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
3470 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
3471 | mtd->_erase = nand_erase; |
3472 | mtd->_point = NULL; | |
3473 | mtd->_unpoint = NULL; | |
3474 | mtd->_read = nand_read; | |
3475 | mtd->_write = nand_write; | |
3476 | mtd->_panic_write = panic_nand_write; | |
3477 | mtd->_read_oob = nand_read_oob; | |
3478 | mtd->_write_oob = nand_write_oob; | |
3479 | mtd->_sync = nand_sync; | |
3480 | mtd->_lock = NULL; | |
3481 | mtd->_unlock = NULL; | |
3482 | mtd->_suspend = nand_suspend; | |
3483 | mtd->_resume = nand_resume; | |
3484 | mtd->_block_isbad = nand_block_isbad; | |
3485 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 3486 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 3487 | |
6a918bad | 3488 | /* propagate ecc info to mtd_info */ |
5bd34c09 | 3489 | mtd->ecclayout = chip->ecc.layout; |
6a918bad | 3490 | mtd->ecc_strength = chip->ecc.strength * chip->ecc.steps; |
1da177e4 | 3491 | |
0040bf38 | 3492 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 3493 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 3494 | return 0; |
1da177e4 LT |
3495 | |
3496 | /* Build bad block table */ | |
ace4dfee | 3497 | return chip->scan_bbt(mtd); |
1da177e4 | 3498 | } |
7351d3a5 | 3499 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 3500 | |
8b6e50c9 BN |
3501 | /* |
3502 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 3503 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
3504 | * to call us from in-kernel code if the core NAND support is modular. |
3505 | */ | |
3b85c321 DW |
3506 | #ifdef MODULE |
3507 | #define caller_is_module() (1) | |
3508 | #else | |
3509 | #define caller_is_module() \ | |
a6e6abd5 | 3510 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
3511 | #endif |
3512 | ||
3513 | /** | |
3514 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
3515 | * @mtd: MTD device structure |
3516 | * @maxchips: number of chips to scan for | |
3b85c321 | 3517 | * |
8b6e50c9 BN |
3518 | * This fills out all the uninitialized function pointers with the defaults. |
3519 | * The flash ID is read and the mtd/chip structures are filled with the | |
3520 | * appropriate values. The mtd->owner field must be set to the module of the | |
3521 | * caller. | |
3b85c321 DW |
3522 | */ |
3523 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
3524 | { | |
3525 | int ret; | |
3526 | ||
3527 | /* Many callers got this wrong, so check for it for a while... */ | |
3528 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 3529 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
3530 | BUG(); |
3531 | } | |
3532 | ||
5e81e88a | 3533 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
3534 | if (!ret) |
3535 | ret = nand_scan_tail(mtd); | |
3536 | return ret; | |
3537 | } | |
7351d3a5 | 3538 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 3539 | |
1da177e4 | 3540 | /** |
61b03bd7 | 3541 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
3542 | * @mtd: MTD device structure |
3543 | */ | |
e0c7d767 | 3544 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 3545 | { |
ace4dfee | 3546 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 3547 | |
193bd400 ID |
3548 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
3549 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
3550 | ||
5ffcaf3d | 3551 | mtd_device_unregister(mtd); |
1da177e4 | 3552 | |
fa671646 | 3553 | /* Free bad block table memory */ |
ace4dfee | 3554 | kfree(chip->bbt); |
4bf63fcb DW |
3555 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3556 | kfree(chip->buffers); | |
58373ff0 BN |
3557 | |
3558 | /* Free bad block descriptor memory */ | |
3559 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
3560 | & NAND_BBT_DYNAMICSTRUCT) | |
3561 | kfree(chip->badblock_pattern); | |
1da177e4 | 3562 | } |
e0c7d767 | 3563 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
3564 | |
3565 | static int __init nand_base_init(void) | |
3566 | { | |
3567 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
3568 | return 0; | |
3569 | } | |
3570 | ||
3571 | static void __exit nand_base_exit(void) | |
3572 | { | |
3573 | led_trigger_unregister_simple(nand_led_trigger); | |
3574 | } | |
3575 | ||
3576 | module_init(nand_base_init); | |
3577 | module_exit(nand_base_exit); | |
3578 | ||
e0c7d767 | 3579 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
3580 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
3581 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 3582 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |