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mtd: onenand: samsung: add missing iounmap
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 24 * if we have HW ECC support.
1da177e4
LT		 25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4 50#include <linux/mtd/partitions.h>
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
ace4dfee 96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 97 int new_state);
1da177e4 98
8593fbc6
TG		 99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
d470a97c 102/*
8e87d782 103 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
6fe5a6ac
VS		 108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 116 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 122 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 123 ret = -EINVAL;
124 }
125
126 /* Do not allow past end of device */
127 if (ofs + len > mtd->size) {
289c0522 128 pr_debug("%s: past end of device\n", __func__);
6fe5a6ac
VS		 129 ret = -EINVAL;
130 }
131
132 return ret;
133}
134
1da177e4
LT		 135/**
136 * nand_release_device - [GENERIC] release chip
8b6e50c9 137 * @mtd: MTD device structure
61b03bd7 138 *
8b6e50c9 139 * Deselect, release chip lock and wake up anyone waiting on the device.
1da177e4 140 */
e0c7d767 141static void nand_release_device(struct mtd_info *mtd)
1da177e4 142{
ace4dfee 143 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 144
145 /* De-select the NAND device */
ace4dfee 146 chip->select_chip(mtd, -1);
0dfc6246 147
a36ed299 148 /* Release the controller and the chip */
ace4dfee
TG		 149 spin_lock(&chip->controller->lock);
150 chip->controller->active = NULL;
151 chip->state = FL_READY;
152 wake_up(&chip->controller->wq);
153 spin_unlock(&chip->controller->lock);
1da177e4
LT		 154}
155
156/**
157 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 158 * @mtd: MTD device structure
1da177e4 159 *
7854d3f7 160 * Default read function for 8bit buswidth
1da177e4 161 */
58dd8f2b 162static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 163{
ace4dfee
TG		 164 struct nand_chip *chip = mtd->priv;
165 return readb(chip->IO_ADDR_R);
1da177e4
LT		 166}
167
1da177e4
LT		 168/**
169 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
7854d3f7 170 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 171 * @mtd: MTD device structure
1da177e4 172 *
7854d3f7
BN		 173 * Default read function for 16bit buswidth with endianness conversion.
174 *
1da177e4 175 */
58dd8f2b 176static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 177{
ace4dfee
TG		 178 struct nand_chip *chip = mtd->priv;
179 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 180}
181
1da177e4
LT		 182/**
183 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 184 * @mtd: MTD device structure
1da177e4 185 *
7854d3f7 186 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 187 */
188static u16 nand_read_word(struct mtd_info *mtd)
189{
ace4dfee
TG		 190 struct nand_chip *chip = mtd->priv;
191 return readw(chip->IO_ADDR_R);
1da177e4
LT		 192}
193
1da177e4
LT		 194/**
195 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 196 * @mtd: MTD device structure
197 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 198 *
199 * Default select function for 1 chip devices.
200 */
ace4dfee 201static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 202{
ace4dfee
TG		 203 struct nand_chip *chip = mtd->priv;
204
205 switch (chipnr) {
1da177e4 206 case -1:
ace4dfee 207 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 208 break;
209 case 0:
1da177e4
LT		 210 break;
211
212 default:
213 BUG();
214 }
215}
216
217/**
218 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 219 * @mtd: MTD device structure
220 * @buf: data buffer
221 * @len: number of bytes to write
1da177e4 222 *
7854d3f7 223 * Default write function for 8bit buswidth.
1da177e4 224 */
58dd8f2b 225static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 226{
227 int i;
ace4dfee 228 struct nand_chip *chip = mtd->priv;
1da177e4 229
e0c7d767 230 for (i = 0; i < len; i++)
ace4dfee 231 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 232}
233
234/**
61b03bd7 235 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 236 * @mtd: MTD device structure
237 * @buf: buffer to store date
238 * @len: number of bytes to read
1da177e4 239 *
7854d3f7 240 * Default read function for 8bit buswidth.
1da177e4 241 */
58dd8f2b 242static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 243{
244 int i;
ace4dfee 245 struct nand_chip *chip = mtd->priv;
1da177e4 246
e0c7d767 247 for (i = 0; i < len; i++)
ace4dfee 248 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 249}
250
251/**
61b03bd7 252 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 253 * @mtd: MTD device structure
254 * @buf: buffer containing the data to compare
255 * @len: number of bytes to compare
1da177e4 256 *
7854d3f7 257 * Default verify function for 8bit buswidth.
1da177e4 258 */
58dd8f2b 259static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 260{
261 int i;
ace4dfee 262 struct nand_chip *chip = mtd->priv;
1da177e4 263
e0c7d767 264 for (i = 0; i < len; i++)
ace4dfee 265 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 266 return -EFAULT;
1da177e4
LT		 267 return 0;
268}
269
270/**
271 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 272 * @mtd: MTD device structure
273 * @buf: data buffer
274 * @len: number of bytes to write
1da177e4 275 *
7854d3f7 276 * Default write function for 16bit buswidth.
1da177e4 277 */
58dd8f2b 278static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 279{
280 int i;
ace4dfee 281 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 282 u16 *p = (u16 *) buf;
283 len >>= 1;
61b03bd7 284
e0c7d767 285 for (i = 0; i < len; i++)
ace4dfee 286 writew(p[i], chip->IO_ADDR_W);
61b03bd7 287
1da177e4
LT		 288}
289
290/**
61b03bd7 291 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 292 * @mtd: MTD device structure
293 * @buf: buffer to store date
294 * @len: number of bytes to read
1da177e4 295 *
7854d3f7 296 * Default read function for 16bit buswidth.
1da177e4 297 */
58dd8f2b 298static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 299{
300 int i;
ace4dfee 301 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 302 u16 *p = (u16 *) buf;
303 len >>= 1;
304
e0c7d767 305 for (i = 0; i < len; i++)
ace4dfee 306 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 307}
308
309/**
61b03bd7 310 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 311 * @mtd: MTD device structure
312 * @buf: buffer containing the data to compare
313 * @len: number of bytes to compare
1da177e4 314 *
7854d3f7 315 * Default verify function for 16bit buswidth.
1da177e4 316 */
58dd8f2b 317static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 318{
319 int i;
ace4dfee 320 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 321 u16 *p = (u16 *) buf;
322 len >>= 1;
323
e0c7d767 324 for (i = 0; i < len; i++)
ace4dfee 325 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 326 return -EFAULT;
327
328 return 0;
329}
330
331/**
332 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 333 * @mtd: MTD device structure
334 * @ofs: offset from device start
335 * @getchip: 0, if the chip is already selected
1da177e4 336 *
61b03bd7 337 * Check, if the block is bad.
1da177e4
LT		 338 */
339static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
340{
341 int page, chipnr, res = 0;
ace4dfee 342 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 343 u16 bad;
344
5fb1549d 345 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 346 ofs += mtd->erasesize - mtd->writesize;
347
1a12f46a
TK		 348 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
349
1da177e4 350 if (getchip) {
ace4dfee 351 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 352
ace4dfee 353 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 354
355 /* Select the NAND device */
ace4dfee 356 chip->select_chip(mtd, chipnr);
1a12f46a 357 }
1da177e4 358
ace4dfee
TG		 359 if (chip->options & NAND_BUSWIDTH_16) {
360 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 361 page);
ace4dfee
TG		 362 bad = cpu_to_le16(chip->read_word(mtd));
363 if (chip->badblockpos & 0x1)
49196f33 364 bad >>= 8;
e0b58d0a
ML		 365 else
366 bad &= 0xFF;
1da177e4 367 } else {
1a12f46a 368 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
e0b58d0a 369 bad = chip->read_byte(mtd);
1da177e4 370 }
61b03bd7 371
e0b58d0a
ML		 372 if (likely(chip->badblockbits == 8))
373 res = bad != 0xFF;
374 else
375 res = hweight8(bad) < chip->badblockbits;
376
ace4dfee 377 if (getchip)
1da177e4 378 nand_release_device(mtd);
61b03bd7 379
1da177e4
LT		 380 return res;
381}
382
383/**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 385 * @mtd: MTD device structure
386 * @ofs: offset from device start
1da177e4 387 *
8b6e50c9
BN		 388 * This is the default implementation, which can be overridden by a hardware
389 * specific driver.
1da177e4
LT		 390*/
391static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
392{
ace4dfee 393 struct nand_chip *chip = mtd->priv;
58dd8f2b 394 uint8_t buf[2] = { 0, 0 };
02ed70bb 395 int block, ret, i = 0;
61b03bd7 396
5fb1549d 397 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 398 ofs += mtd->erasesize - mtd->writesize;
399
1da177e4 400 /* Get block number */
4226b510 401 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 402 if (chip->bbt)
403 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 404
8b6e50c9 405 /* Do we have a flash based bad block table? */
bb9ebd4e 406 if (chip->bbt_options & NAND_BBT_USE_FLASH)
f1a28c02
TG		 407 ret = nand_update_bbt(mtd, ofs);
408 else {
4a89ff88
BN		 409 struct mtd_oob_ops ops;
410
c0b8ba7b 411 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 412
a0dc5529
BN		 413 /*
414 * Write to first two pages if necessary. If we write to more
415 * than one location, the first error encountered quits the
416 * procedure. We write two bytes per location, so we dont have
417 * to mess with 16 bit access.
02ed70bb 418 */
4a89ff88
BN		 419 ops.len = ops.ooblen = 2;
420 ops.datbuf = NULL;
421 ops.oobbuf = buf;
422 ops.ooboffs = chip->badblockpos & ~0x01;
23b1a99b 423 ops.mode = MTD_OPS_PLACE_OOB;
02ed70bb 424 do {
4a89ff88 425 ret = nand_do_write_oob(mtd, ofs, &ops);
02ed70bb 426
02ed70bb
BN		 427 i++;
428 ofs += mtd->writesize;
5fb1549d 429 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
02ed70bb
BN		 430 i < 2);
431
c0b8ba7b 432 nand_release_device(mtd);
f1a28c02
TG		 433 }
434 if (!ret)
435 mtd->ecc_stats.badblocks++;
c0b8ba7b 436
f1a28c02 437 return ret;
1da177e4
LT		 438}
439
61b03bd7 440/**
1da177e4 441 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 442 * @mtd: MTD device structure
1da177e4 443 *
8b6e50c9
BN		 444 * Check, if the device is write protected. The function expects, that the
445 * device is already selected.
1da177e4 446 */
e0c7d767 447static int nand_check_wp(struct mtd_info *mtd)
1da177e4 448{
ace4dfee 449 struct nand_chip *chip = mtd->priv;
93edbad6 450
8b6e50c9 451 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 452 if (chip->options & NAND_BROKEN_XD)
453 return 0;
454
1da177e4 455 /* Check the WP bit */
ace4dfee
TG		 456 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
457 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 458}
459
460/**
461 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 462 * @mtd: MTD device structure
463 * @ofs: offset from device start
464 * @getchip: 0, if the chip is already selected
465 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 466 *
467 * Check, if the block is bad. Either by reading the bad block table or
468 * calling of the scan function.
469 */
2c0a2bed
TG		 470static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
471 int allowbbt)
1da177e4 472{
ace4dfee 473 struct nand_chip *chip = mtd->priv;
61b03bd7 474
ace4dfee
TG		 475 if (!chip->bbt)
476 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 477
1da177e4 478 /* Return info from the table */
e0c7d767 479 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 480}
481
2af7c653
SK		 482/**
483 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 484 * @mtd: MTD device structure
485 * @timeo: Timeout
2af7c653
SK		 486 *
487 * Helper function for nand_wait_ready used when needing to wait in interrupt
488 * context.
489 */
490static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
491{
492 struct nand_chip *chip = mtd->priv;
493 int i;
494
495 /* Wait for the device to get ready */
496 for (i = 0; i < timeo; i++) {
497 if (chip->dev_ready(mtd))
498 break;
499 touch_softlockup_watchdog();
500 mdelay(1);
501 }
502}
503
7854d3f7 504/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 505void nand_wait_ready(struct mtd_info *mtd)
3b88775c 506{
ace4dfee 507 struct nand_chip *chip = mtd->priv;
e0c7d767 508 unsigned long timeo = jiffies + 2;
3b88775c 509
2af7c653
SK		 510 /* 400ms timeout */
511 if (in_interrupt() || oops_in_progress)
512 return panic_nand_wait_ready(mtd, 400);
513
8fe833c1 514 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 515 /* Wait until command is processed or timeout occurs */
3b88775c 516 do {
ace4dfee 517 if (chip->dev_ready(mtd))
8fe833c1 518 break;
8446f1d3 519 touch_softlockup_watchdog();
61b03bd7 520 } while (time_before(jiffies, timeo));
8fe833c1 521 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 522}
4b648b02 523EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 524
1da177e4
LT		 525/**
526 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 527 * @mtd: MTD device structure
528 * @command: the command to be sent
529 * @column: the column address for this command, -1 if none
530 * @page_addr: the page address for this command, -1 if none
1da177e4 531 *
8b6e50c9
BN		 532 * Send command to NAND device. This function is used for small page devices
533 * (256/512 Bytes per page).
1da177e4 534 */
7abd3ef9
TG		 535static void nand_command(struct mtd_info *mtd, unsigned int command,
536 int column, int page_addr)
1da177e4 537{
ace4dfee 538 register struct nand_chip *chip = mtd->priv;
7abd3ef9 539 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 540
8b6e50c9 541 /* Write out the command to the device */
1da177e4
LT		 542 if (command == NAND_CMD_SEQIN) {
543 int readcmd;
544
28318776 545 if (column >= mtd->writesize) {
1da177e4 546 /* OOB area */
28318776 547 column -= mtd->writesize;
1da177e4
LT		 548 readcmd = NAND_CMD_READOOB;
549 } else if (column < 256) {
550 /* First 256 bytes --> READ0 */
551 readcmd = NAND_CMD_READ0;
552 } else {
553 column -= 256;
554 readcmd = NAND_CMD_READ1;
555 }
ace4dfee 556 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 557 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 558 }
ace4dfee 559 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 560
8b6e50c9 561 /* Address cycle, when necessary */
7abd3ef9
TG		 562 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
563 /* Serially input address */
564 if (column != -1) {
565 /* Adjust columns for 16 bit buswidth */
ace4dfee 566 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 567 column >>= 1;
ace4dfee 568 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 569 ctrl &= ~NAND_CTRL_CHANGE;
570 }
571 if (page_addr != -1) {
ace4dfee 572 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 573 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 574 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 575 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 576 if (chip->chipsize > (32 << 20))
577 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 578 }
ace4dfee 579 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 580
581 /*
8b6e50c9
BN		 582 * Program and erase have their own busy handlers status and sequential
583 * in needs no delay
e0c7d767 584 */
1da177e4 585 switch (command) {
61b03bd7 586
1da177e4
LT		 587 case NAND_CMD_PAGEPROG:
588 case NAND_CMD_ERASE1:
589 case NAND_CMD_ERASE2:
590 case NAND_CMD_SEQIN:
591 case NAND_CMD_STATUS:
592 return;
593
594 case NAND_CMD_RESET:
ace4dfee 595 if (chip->dev_ready)
1da177e4 596 break;
ace4dfee
TG		 597 udelay(chip->chip_delay);
598 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 599 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 600 chip->cmd_ctrl(mtd,
601 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 602 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
603 ;
1da177e4
LT		 604 return;
605
e0c7d767 606 /* This applies to read commands */
1da177e4 607 default:
61b03bd7 608 /*
1da177e4
LT		 609 * If we don't have access to the busy pin, we apply the given
610 * command delay
e0c7d767 611 */
ace4dfee
TG		 612 if (!chip->dev_ready) {
613 udelay(chip->chip_delay);
1da177e4 614 return;
61b03bd7 615 }
1da177e4 616 }
8b6e50c9
BN		 617 /*
618 * Apply this short delay always to ensure that we do wait tWB in
619 * any case on any machine.
620 */
e0c7d767 621 ndelay(100);
3b88775c
TG		 622
623 nand_wait_ready(mtd);
1da177e4
LT		 624}
625
626/**
627 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 628 * @mtd: MTD device structure
629 * @command: the command to be sent
630 * @column: the column address for this command, -1 if none
631 * @page_addr: the page address for this command, -1 if none
1da177e4 632 *
7abd3ef9 633 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 634 * devices. We don't have the separate regions as we have in the small page
635 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 636 */
7abd3ef9
TG		 637static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
638 int column, int page_addr)
1da177e4 639{
ace4dfee 640 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 641
642 /* Emulate NAND_CMD_READOOB */
643 if (command == NAND_CMD_READOOB) {
28318776 644 column += mtd->writesize;
1da177e4
LT		 645 command = NAND_CMD_READ0;
646 }
61b03bd7 647
7abd3ef9 648 /* Command latch cycle */
ace4dfee 649 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 650 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 651
652 if (column != -1 || page_addr != -1) {
7abd3ef9 653 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 654
655 /* Serially input address */
656 if (column != -1) {
657 /* Adjust columns for 16 bit buswidth */
ace4dfee 658 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 659 column >>= 1;
ace4dfee 660 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 661 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 662 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 663 }
1da177e4 664 if (page_addr != -1) {
ace4dfee
TG		 665 chip->cmd_ctrl(mtd, page_addr, ctrl);
666 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 667 NAND_NCE | NAND_ALE);
1da177e4 668 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 669 if (chip->chipsize > (128 << 20))
670 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 671 NAND_NCE | NAND_ALE);
1da177e4 672 }
1da177e4 673 }
ace4dfee 674 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 675
676 /*
8b6e50c9
BN		 677 * Program and erase have their own busy handlers status, sequential
678 * in, and deplete1 need no delay.
30f464b7 679 */
1da177e4 680 switch (command) {
61b03bd7 681
1da177e4
LT		 682 case NAND_CMD_CACHEDPROG:
683 case NAND_CMD_PAGEPROG:
684 case NAND_CMD_ERASE1:
685 case NAND_CMD_ERASE2:
686 case NAND_CMD_SEQIN:
7bc3312b 687 case NAND_CMD_RNDIN:
1da177e4 688 case NAND_CMD_STATUS:
30f464b7 689 case NAND_CMD_DEPLETE1:
1da177e4
LT		 690 return;
691
30f464b7
DM		 692 case NAND_CMD_STATUS_ERROR:
693 case NAND_CMD_STATUS_ERROR0:
694 case NAND_CMD_STATUS_ERROR1:
695 case NAND_CMD_STATUS_ERROR2:
696 case NAND_CMD_STATUS_ERROR3:
8b6e50c9 697 /* Read error status commands require only a short delay */
ace4dfee 698 udelay(chip->chip_delay);
30f464b7 699 return;
1da177e4
LT		 700
701 case NAND_CMD_RESET:
ace4dfee 702 if (chip->dev_ready)
1da177e4 703 break;
ace4dfee 704 udelay(chip->chip_delay);
12efdde3
TG		 705 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
706 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
707 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
708 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 709 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
710 ;
1da177e4
LT		 711 return;
712
7bc3312b
TG		 713 case NAND_CMD_RNDOUT:
714 /* No ready / busy check necessary */
715 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
716 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
717 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
718 NAND_NCE | NAND_CTRL_CHANGE);
719 return;
720
1da177e4 721 case NAND_CMD_READ0:
12efdde3
TG		 722 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
723 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
724 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
725 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 726
e0c7d767 727 /* This applies to read commands */
1da177e4 728 default:
61b03bd7 729 /*
1da177e4 730 * If we don't have access to the busy pin, we apply the given
8b6e50c9 731 * command delay.
e0c7d767 732 */
ace4dfee
TG		 733 if (!chip->dev_ready) {
734 udelay(chip->chip_delay);
1da177e4 735 return;
61b03bd7 736 }
1da177e4 737 }
3b88775c 738
8b6e50c9
BN		 739 /*
740 * Apply this short delay always to ensure that we do wait tWB in
741 * any case on any machine.
742 */
e0c7d767 743 ndelay(100);
3b88775c
TG		 744
745 nand_wait_ready(mtd);
1da177e4
LT		 746}
747
2af7c653
SK		 748/**
749 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 750 * @chip: the nand chip descriptor
751 * @mtd: MTD device structure
752 * @new_state: the state which is requested
2af7c653
SK		 753 *
754 * Used when in panic, no locks are taken.
755 */
756static void panic_nand_get_device(struct nand_chip *chip,
757 struct mtd_info *mtd, int new_state)
758{
7854d3f7 759 /* Hardware controller shared among independent devices */
2af7c653
SK		 760 chip->controller->active = chip;
761 chip->state = new_state;
762}
763
1da177e4
LT		 764/**
765 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 766 * @chip: the nand chip descriptor
767 * @mtd: MTD device structure
768 * @new_state: the state which is requested
1da177e4
LT		 769 *
770 * Get the device and lock it for exclusive access
771 */
2c0a2bed 772static int
ace4dfee 773nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 774{
ace4dfee
TG		 775 spinlock_t *lock = &chip->controller->lock;
776 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 777 DECLARE_WAITQUEUE(wait, current);
7351d3a5 778retry:
0dfc6246
TG		 779 spin_lock(lock);
780
b8b3ee9a 781 /* Hardware controller shared among independent devices */
ace4dfee
TG		 782 if (!chip->controller->active)
783 chip->controller->active = chip;
a36ed299 784
ace4dfee
TG		 785 if (chip->controller->active == chip && chip->state == FL_READY) {
786 chip->state = new_state;
0dfc6246 787 spin_unlock(lock);
962034f4
VW		 788 return 0;
789 }
790 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 791 if (chip->controller->active->state == FL_PM_SUSPENDED) {
792 chip->state = FL_PM_SUSPENDED;
793 spin_unlock(lock);
794 return 0;
6b0d9a84 795 }
0dfc6246
TG		 796 }
797 set_current_state(TASK_UNINTERRUPTIBLE);
798 add_wait_queue(wq, &wait);
799 spin_unlock(lock);
800 schedule();
801 remove_wait_queue(wq, &wait);
1da177e4
LT		 802 goto retry;
803}
804
2af7c653 805/**
8b6e50c9
BN		 806 * panic_nand_wait - [GENERIC] wait until the command is done
807 * @mtd: MTD device structure
808 * @chip: NAND chip structure
809 * @timeo: timeout
2af7c653
SK		 810 *
811 * Wait for command done. This is a helper function for nand_wait used when
812 * we are in interrupt context. May happen when in panic and trying to write
b595076a 813 * an oops through mtdoops.
2af7c653
SK		 814 */
815static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
816 unsigned long timeo)
817{
818 int i;
819 for (i = 0; i < timeo; i++) {
820 if (chip->dev_ready) {
821 if (chip->dev_ready(mtd))
822 break;
823 } else {
824 if (chip->read_byte(mtd) & NAND_STATUS_READY)
825 break;
826 }
827 mdelay(1);
f8ac0414 828 }
2af7c653
SK		 829}
830
1da177e4 831/**
8b6e50c9
BN		 832 * nand_wait - [DEFAULT] wait until the command is done
833 * @mtd: MTD device structure
834 * @chip: NAND chip structure
1da177e4 835 *
8b6e50c9
BN		 836 * Wait for command done. This applies to erase and program only. Erase can
837 * take up to 400ms and program up to 20ms according to general NAND and
838 * SmartMedia specs.
844d3b42 839 */
7bc3312b 840static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 841{
842
e0c7d767 843 unsigned long timeo = jiffies;
7bc3312b 844 int status, state = chip->state;
61b03bd7 845
1da177e4 846 if (state == FL_ERASING)
e0c7d767 847 timeo += (HZ * 400) / 1000;
1da177e4 848 else
e0c7d767 849 timeo += (HZ * 20) / 1000;
1da177e4 850
8fe833c1
RP		 851 led_trigger_event(nand_led_trigger, LED_FULL);
852
8b6e50c9
BN		 853 /*
854 * Apply this short delay always to ensure that we do wait tWB in any
855 * case on any machine.
856 */
e0c7d767 857 ndelay(100);
1da177e4 858
ace4dfee
TG		 859 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
860 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 861 else
ace4dfee 862 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 863
2af7c653
SK		 864 if (in_interrupt() || oops_in_progress)
865 panic_nand_wait(mtd, chip, timeo);
866 else {
867 while (time_before(jiffies, timeo)) {
868 if (chip->dev_ready) {
869 if (chip->dev_ready(mtd))
870 break;
871 } else {
872 if (chip->read_byte(mtd) & NAND_STATUS_READY)
873 break;
874 }
875 cond_resched();
1da177e4 876 }
1da177e4 877 }
8fe833c1
RP		 878 led_trigger_event(nand_led_trigger, LED_OFF);
879
ace4dfee 880 status = (int)chip->read_byte(mtd);
1da177e4
LT		 881 return status;
882}
883
7d70f334 884/**
b6d676db 885 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 886 * @mtd: mtd info
887 * @ofs: offset to start unlock from
888 * @len: length to unlock
8b6e50c9
BN		 889 * @invert: when = 0, unlock the range of blocks within the lower and
890 * upper boundary address
891 * when = 1, unlock the range of blocks outside the boundaries
892 * of the lower and upper boundary address
7d70f334 893 *
8b6e50c9 894 * Returs unlock status.
7d70f334
VS		 895 */
896static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
897 uint64_t len, int invert)
898{
899 int ret = 0;
900 int status, page;
901 struct nand_chip *chip = mtd->priv;
902
903 /* Submit address of first page to unlock */
904 page = ofs >> chip->page_shift;
905 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
906
907 /* Submit address of last page to unlock */
908 page = (ofs + len) >> chip->page_shift;
909 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
910 (page | invert) & chip->pagemask);
911
912 /* Call wait ready function */
913 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 914 /* See if device thinks it succeeded */
915 if (status & 0x01) {
289c0522 916 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 917 __func__, status);
918 ret = -EIO;
919 }
920
921 return ret;
922}
923
924/**
b6d676db 925 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 926 * @mtd: mtd info
927 * @ofs: offset to start unlock from
928 * @len: length to unlock
7d70f334 929 *
8b6e50c9 930 * Returns unlock status.
7d70f334
VS		 931 */
932int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
933{
934 int ret = 0;
935 int chipnr;
936 struct nand_chip *chip = mtd->priv;
937
289c0522 938 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 939 __func__, (unsigned long long)ofs, len);
940
941 if (check_offs_len(mtd, ofs, len))
942 ret = -EINVAL;
943
944 /* Align to last block address if size addresses end of the device */
945 if (ofs + len == mtd->size)
946 len -= mtd->erasesize;
947
948 nand_get_device(chip, mtd, FL_UNLOCKING);
949
950 /* Shift to get chip number */
951 chipnr = ofs >> chip->chip_shift;
952
953 chip->select_chip(mtd, chipnr);
954
955 /* Check, if it is write protected */
956 if (nand_check_wp(mtd)) {
289c0522 957 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 958 __func__);
959 ret = -EIO;
960 goto out;
961 }
962
963 ret = __nand_unlock(mtd, ofs, len, 0);
964
965out:
7d70f334
VS		 966 nand_release_device(mtd);
967
968 return ret;
969}
7351d3a5 970EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 971
972/**
b6d676db 973 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 974 * @mtd: mtd info
975 * @ofs: offset to start unlock from
976 * @len: length to unlock
7d70f334 977 *
8b6e50c9
BN		 978 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
979 * have this feature, but it allows only to lock all blocks, not for specified
980 * range for block. Implementing 'lock' feature by making use of 'unlock', for
981 * now.
7d70f334 982 *
8b6e50c9 983 * Returns lock status.
7d70f334
VS		 984 */
985int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
986{
987 int ret = 0;
988 int chipnr, status, page;
989 struct nand_chip *chip = mtd->priv;
990
289c0522 991 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 992 __func__, (unsigned long long)ofs, len);
993
994 if (check_offs_len(mtd, ofs, len))
995 ret = -EINVAL;
996
997 nand_get_device(chip, mtd, FL_LOCKING);
998
999 /* Shift to get chip number */
1000 chipnr = ofs >> chip->chip_shift;
1001
1002 chip->select_chip(mtd, chipnr);
1003
1004 /* Check, if it is write protected */
1005 if (nand_check_wp(mtd)) {
289c0522 1006 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1007 __func__);
1008 status = MTD_ERASE_FAILED;
1009 ret = -EIO;
1010 goto out;
1011 }
1012
1013 /* Submit address of first page to lock */
1014 page = ofs >> chip->page_shift;
1015 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1016
1017 /* Call wait ready function */
1018 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 1019 /* See if device thinks it succeeded */
1020 if (status & 0x01) {
289c0522 1021 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1022 __func__, status);
1023 ret = -EIO;
1024 goto out;
1025 }
1026
1027 ret = __nand_unlock(mtd, ofs, len, 0x1);
1028
1029out:
7d70f334
VS		 1030 nand_release_device(mtd);
1031
1032 return ret;
1033}
7351d3a5 1034EXPORT_SYMBOL(nand_lock);
7d70f334 1035
8593fbc6 1036/**
7854d3f7 1037 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1038 * @mtd: mtd info structure
1039 * @chip: nand chip info structure
1040 * @buf: buffer to store read data
1041 * @page: page number to read
52ff49df 1042 *
7854d3f7 1043 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1044 */
1045static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1046 uint8_t *buf, int page)
8593fbc6
TG		 1047{
1048 chip->read_buf(mtd, buf, mtd->writesize);
1049 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1050 return 0;
1051}
1052
52ff49df 1053/**
7854d3f7 1054 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1055 * @mtd: mtd info structure
1056 * @chip: nand chip info structure
1057 * @buf: buffer to store read data
1058 * @page: page number to read
52ff49df
DB		 1059 *
1060 * We need a special oob layout and handling even when OOB isn't used.
1061 */
7351d3a5
FF		 1062static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1063 struct nand_chip *chip,
1064 uint8_t *buf, int page)
52ff49df
DB		 1065{
1066 int eccsize = chip->ecc.size;
1067 int eccbytes = chip->ecc.bytes;
1068 uint8_t *oob = chip->oob_poi;
1069 int steps, size;
1070
1071 for (steps = chip->ecc.steps; steps > 0; steps--) {
1072 chip->read_buf(mtd, buf, eccsize);
1073 buf += eccsize;
1074
1075 if (chip->ecc.prepad) {
1076 chip->read_buf(mtd, oob, chip->ecc.prepad);
1077 oob += chip->ecc.prepad;
1078 }
1079
1080 chip->read_buf(mtd, oob, eccbytes);
1081 oob += eccbytes;
1082
1083 if (chip->ecc.postpad) {
1084 chip->read_buf(mtd, oob, chip->ecc.postpad);
1085 oob += chip->ecc.postpad;
1086 }
1087 }
1088
1089 size = mtd->oobsize - (oob - chip->oob_poi);
1090 if (size)
1091 chip->read_buf(mtd, oob, size);
1092
1093 return 0;
1094}
1095
1da177e4 1096/**
7854d3f7 1097 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1098 * @mtd: mtd info structure
1099 * @chip: nand chip info structure
1100 * @buf: buffer to store read data
1101 * @page: page number to read
068e3c0a 1102 */
f5bbdacc 1103static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1104 uint8_t *buf, int page)
1da177e4 1105{
f5bbdacc
TG		 1106 int i, eccsize = chip->ecc.size;
1107 int eccbytes = chip->ecc.bytes;
1108 int eccsteps = chip->ecc.steps;
1109 uint8_t *p = buf;
4bf63fcb
DW		 1110 uint8_t *ecc_calc = chip->buffers->ecccalc;
1111 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1112 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 1113
46a8cf2d 1114 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 1115
1116 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1117 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1118
1119 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1120 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1121
1122 eccsteps = chip->ecc.steps;
1123 p = buf;
1124
1125 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1126 int stat;
1127
1128 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1129 if (stat < 0)
f5bbdacc
TG		 1130 mtd->ecc_stats.failed++;
1131 else
1132 mtd->ecc_stats.corrected += stat;
1133 }
1134 return 0;
22c60f5f 1135}
1da177e4 1136
3d459559 1137/**
7854d3f7 1138 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
8b6e50c9
BN		 1139 * @mtd: mtd info structure
1140 * @chip: nand chip info structure
1141 * @data_offs: offset of requested data within the page
1142 * @readlen: data length
1143 * @bufpoi: buffer to store read data
3d459559 1144 */
7351d3a5
FF		 1145static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1146 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1147{
1148 int start_step, end_step, num_steps;
1149 uint32_t *eccpos = chip->ecc.layout->eccpos;
1150 uint8_t *p;
1151 int data_col_addr, i, gaps = 0;
1152 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1153 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1154 int index = 0;
3d459559 1155
7854d3f7 1156 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1157 start_step = data_offs / chip->ecc.size;
1158 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1159 num_steps = end_step - start_step + 1;
1160
8b6e50c9 1161 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1162 datafrag_len = num_steps * chip->ecc.size;
1163 eccfrag_len = num_steps * chip->ecc.bytes;
1164
1165 data_col_addr = start_step * chip->ecc.size;
1166 /* If we read not a page aligned data */
1167 if (data_col_addr != 0)
1168 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1169
1170 p = bufpoi + data_col_addr;
1171 chip->read_buf(mtd, p, datafrag_len);
1172
8b6e50c9 1173 /* Calculate ECC */
3d459559
AK		 1174 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1175 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1176
8b6e50c9
BN		 1177 /*
1178 * The performance is faster if we position offsets according to
7854d3f7 1179 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1180 */
3d459559
AK		 1181 for (i = 0; i < eccfrag_len - 1; i++) {
1182 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1183 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1184 gaps = 1;
1185 break;
1186 }
1187 }
1188 if (gaps) {
1189 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1190 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1191 } else {
8b6e50c9 1192 /*
7854d3f7 1193 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1194 * about buswidth alignment in read_buf.
1195 */
7351d3a5
FF		 1196 index = start_step * chip->ecc.bytes;
1197
1198 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1199 aligned_len = eccfrag_len;
7351d3a5 1200 if (eccpos[index] & (busw - 1))
3d459559 1201 aligned_len++;
7351d3a5 1202 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1203 aligned_len++;
1204
7351d3a5
FF		 1205 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1206 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1207 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1208 }
1209
1210 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1211 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1212
1213 p = bufpoi + data_col_addr;
1214 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1215 int stat;
1216
7351d3a5
FF		 1217 stat = chip->ecc.correct(mtd, p,
1218 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
12c8eb98 1219 if (stat < 0)
3d459559
AK		 1220 mtd->ecc_stats.failed++;
1221 else
1222 mtd->ecc_stats.corrected += stat;
1223 }
1224 return 0;
1225}
1226
068e3c0a 1227/**
7854d3f7 1228 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1229 * @mtd: mtd info structure
1230 * @chip: nand chip info structure
1231 * @buf: buffer to store read data
1232 * @page: page number to read
068e3c0a 1233 *
7854d3f7 1234 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1235 */
f5bbdacc 1236static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1237 uint8_t *buf, int page)
1da177e4 1238{
f5bbdacc
TG		 1239 int i, eccsize = chip->ecc.size;
1240 int eccbytes = chip->ecc.bytes;
1241 int eccsteps = chip->ecc.steps;
1242 uint8_t *p = buf;
4bf63fcb
DW		 1243 uint8_t *ecc_calc = chip->buffers->ecccalc;
1244 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1245 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1246
1247 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1248 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1249 chip->read_buf(mtd, p, eccsize);
1250 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1251 }
f75e5097 1252 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1253
f5bbdacc 1254 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1255 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1256
f5bbdacc
TG		 1257 eccsteps = chip->ecc.steps;
1258 p = buf;
61b03bd7 1259
f5bbdacc
TG		 1260 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1261 int stat;
1da177e4 1262
f5bbdacc 1263 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1264 if (stat < 0)
f5bbdacc
TG		 1265 mtd->ecc_stats.failed++;
1266 else
1267 mtd->ecc_stats.corrected += stat;
1268 }
1269 return 0;
1270}
1da177e4 1271
6e0cb135 1272/**
7854d3f7 1273 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1274 * @mtd: mtd info structure
1275 * @chip: nand chip info structure
1276 * @buf: buffer to store read data
1277 * @page: page number to read
6e0cb135 1278 *
8b6e50c9
BN		 1279 * Hardware ECC for large page chips, require OOB to be read first. For this
1280 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1281 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1282 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1283 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1284 */
1285static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1286 struct nand_chip *chip, uint8_t *buf, int page)
1287{
1288 int i, eccsize = chip->ecc.size;
1289 int eccbytes = chip->ecc.bytes;
1290 int eccsteps = chip->ecc.steps;
1291 uint8_t *p = buf;
1292 uint8_t *ecc_code = chip->buffers->ecccode;
1293 uint32_t *eccpos = chip->ecc.layout->eccpos;
1294 uint8_t *ecc_calc = chip->buffers->ecccalc;
1295
1296 /* Read the OOB area first */
1297 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1298 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1299 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1300
1301 for (i = 0; i < chip->ecc.total; i++)
1302 ecc_code[i] = chip->oob_poi[eccpos[i]];
1303
1304 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1305 int stat;
1306
1307 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1308 chip->read_buf(mtd, p, eccsize);
1309 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1310
1311 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1312 if (stat < 0)
1313 mtd->ecc_stats.failed++;
1314 else
1315 mtd->ecc_stats.corrected += stat;
1316 }
1317 return 0;
1318}
1319
f5bbdacc 1320/**
7854d3f7 1321 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1322 * @mtd: mtd info structure
1323 * @chip: nand chip info structure
1324 * @buf: buffer to store read data
1325 * @page: page number to read
f5bbdacc 1326 *
8b6e50c9
BN		 1327 * The hw generator calculates the error syndrome automatically. Therefore we
1328 * need a special oob layout and handling.
f5bbdacc
TG		 1329 */
1330static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1331 uint8_t *buf, int page)
f5bbdacc
TG		 1332{
1333 int i, eccsize = chip->ecc.size;
1334 int eccbytes = chip->ecc.bytes;
1335 int eccsteps = chip->ecc.steps;
1336 uint8_t *p = buf;
f75e5097 1337 uint8_t *oob = chip->oob_poi;
1da177e4 1338
f5bbdacc
TG		 1339 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1340 int stat;
61b03bd7 1341
f5bbdacc
TG		 1342 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1343 chip->read_buf(mtd, p, eccsize);
1da177e4 1344
f5bbdacc
TG		 1345 if (chip->ecc.prepad) {
1346 chip->read_buf(mtd, oob, chip->ecc.prepad);
1347 oob += chip->ecc.prepad;
1348 }
1da177e4 1349
f5bbdacc
TG		 1350 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1351 chip->read_buf(mtd, oob, eccbytes);
1352 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1353
c32b8dcc 1354 if (stat < 0)
f5bbdacc 1355 mtd->ecc_stats.failed++;
61b03bd7 1356 else
f5bbdacc 1357 mtd->ecc_stats.corrected += stat;
61b03bd7 1358
f5bbdacc 1359 oob += eccbytes;
1da177e4 1360
f5bbdacc
TG		 1361 if (chip->ecc.postpad) {
1362 chip->read_buf(mtd, oob, chip->ecc.postpad);
1363 oob += chip->ecc.postpad;
61b03bd7 1364 }
f5bbdacc 1365 }
1da177e4 1366
f5bbdacc 1367 /* Calculate remaining oob bytes */
7e4178f9 1368 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1369 if (i)
1370 chip->read_buf(mtd, oob, i);
61b03bd7 1371
f5bbdacc
TG		 1372 return 0;
1373}
1da177e4 1374
f5bbdacc 1375/**
7854d3f7 1376 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1377 * @chip: nand chip structure
1378 * @oob: oob destination address
1379 * @ops: oob ops structure
1380 * @len: size of oob to transfer
8593fbc6
TG		 1381 */
1382static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1383 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1384{
f8ac0414 1385 switch (ops->mode) {
8593fbc6 1386
0612b9dd
BN		 1387 case MTD_OPS_PLACE_OOB:
1388 case MTD_OPS_RAW:
8593fbc6
TG		 1389 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1390 return oob + len;
1391
0612b9dd 1392 case MTD_OPS_AUTO_OOB: {
8593fbc6 1393 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1394 uint32_t boffs = 0, roffs = ops->ooboffs;
1395 size_t bytes = 0;
8593fbc6 1396
f8ac0414 1397 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1398 /* Read request not from offset 0? */
7bc3312b
TG		 1399 if (unlikely(roffs)) {
1400 if (roffs >= free->length) {
1401 roffs -= free->length;
1402 continue;
1403 }
1404 boffs = free->offset + roffs;
1405 bytes = min_t(size_t, len,
1406 (free->length - roffs));
1407 roffs = 0;
1408 } else {
1409 bytes = min_t(size_t, len, free->length);
1410 boffs = free->offset;
1411 }
1412 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1413 oob += bytes;
1414 }
1415 return oob;
1416 }
1417 default:
1418 BUG();
1419 }
1420 return NULL;
1421}
1422
1423/**
7854d3f7 1424 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1425 * @mtd: MTD device structure
1426 * @from: offset to read from
1427 * @ops: oob ops structure
f5bbdacc
TG		 1428 *
1429 * Internal function. Called with chip held.
1430 */
8593fbc6
TG		 1431static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1432 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1433{
1434 int chipnr, page, realpage, col, bytes, aligned;
1435 struct nand_chip *chip = mtd->priv;
1436 struct mtd_ecc_stats stats;
1437 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1438 int sndcmd = 1;
1439 int ret = 0;
8593fbc6 1440 uint32_t readlen = ops->len;
7014568b 1441 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1442 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1443 mtd->oobavail : mtd->oobsize;
1444
8593fbc6 1445 uint8_t *bufpoi, *oob, *buf;
1da177e4 1446
f5bbdacc 1447 stats = mtd->ecc_stats;
1da177e4 1448
f5bbdacc
TG		 1449 chipnr = (int)(from >> chip->chip_shift);
1450 chip->select_chip(mtd, chipnr);
61b03bd7 1451
f5bbdacc
TG		 1452 realpage = (int)(from >> chip->page_shift);
1453 page = realpage & chip->pagemask;
1da177e4 1454
f5bbdacc 1455 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1456
8593fbc6
TG		 1457 buf = ops->datbuf;
1458 oob = ops->oobbuf;
1459
f8ac0414 1460 while (1) {
f5bbdacc
TG		 1461 bytes = min(mtd->writesize - col, readlen);
1462 aligned = (bytes == mtd->writesize);
61b03bd7 1463
8b6e50c9 1464 /* Is the current page in the buffer? */
8593fbc6 1465 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1466 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1467
f5bbdacc
TG		 1468 if (likely(sndcmd)) {
1469 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1470 sndcmd = 0;
1da177e4 1471 }
1da177e4 1472
f5bbdacc 1473 /* Now read the page into the buffer */
0612b9dd 1474 if (unlikely(ops->mode == MTD_OPS_RAW))
46a8cf2d
SN		 1475 ret = chip->ecc.read_page_raw(mtd, chip,
1476 bufpoi, page);
3d459559 1477 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1478 ret = chip->ecc.read_subpage(mtd, chip,
1479 col, bytes, bufpoi);
956e944c 1480 else
46a8cf2d
SN		 1481 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1482 page);
6d77b9d0
BN		 1483 if (ret < 0) {
1484 if (!aligned)
1485 /* Invalidate page cache */
1486 chip->pagebuf = -1;
1da177e4 1487 break;
6d77b9d0 1488 }
f5bbdacc
TG		 1489
1490 /* Transfer not aligned data */
1491 if (!aligned) {
c1194c79 1492 if (!NAND_SUBPAGE_READ(chip) && !oob &&
6d77b9d0
BN		 1493 !(mtd->ecc_stats.failed - stats.failed) &&
1494 (ops->mode != MTD_OPS_RAW))
3d459559 1495 chip->pagebuf = realpage;
6d77b9d0
BN		 1496 else
1497 /* Invalidate page cache */
1498 chip->pagebuf = -1;
4bf63fcb 1499 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1500 }
1501
8593fbc6
TG		 1502 buf += bytes;
1503
1504 if (unlikely(oob)) {
9aca334e 1505
b64d39d8
ML		 1506 int toread = min(oobreadlen, max_oobsize);
1507
1508 if (toread) {
1509 oob = nand_transfer_oob(chip,
1510 oob, ops, toread);
1511 oobreadlen -= toread;
1512 }
8593fbc6
TG		 1513 }
1514
f5bbdacc
TG		 1515 if (!(chip->options & NAND_NO_READRDY)) {
1516 /*
1517 * Apply delay or wait for ready/busy pin. Do
1518 * this before the AUTOINCR check, so no
1519 * problems arise if a chip which does auto
1520 * increment is marked as NOAUTOINCR by the
1521 * board driver.
1522 */
1523 if (!chip->dev_ready)
1524 udelay(chip->chip_delay);
1525 else
1526 nand_wait_ready(mtd);
1da177e4 1527 }
8593fbc6 1528 } else {
4bf63fcb 1529 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1530 buf += bytes;
1531 }
1da177e4 1532
f5bbdacc 1533 readlen -= bytes;
61b03bd7 1534
f5bbdacc 1535 if (!readlen)
61b03bd7 1536 break;
1da177e4 1537
8b6e50c9 1538 /* For subsequent reads align to page boundary */
1da177e4
LT		 1539 col = 0;
1540 /* Increment page address */
1541 realpage++;
1542
ace4dfee 1543 page = realpage & chip->pagemask;
1da177e4
LT		 1544 /* Check, if we cross a chip boundary */
1545 if (!page) {
1546 chipnr++;
ace4dfee
TG		 1547 chip->select_chip(mtd, -1);
1548 chip->select_chip(mtd, chipnr);
1da177e4 1549 }
f5bbdacc 1550
8b6e50c9
BN		 1551 /*
1552 * Check, if the chip supports auto page increment or if we
1553 * have hit a block boundary.
e0c7d767 1554 */
f5bbdacc 1555 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1556 sndcmd = 1;
1da177e4
LT		 1557 }
1558
8593fbc6 1559 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1560 if (oob)
1561 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1562
f5bbdacc
TG		 1563 if (ret)
1564 return ret;
1565
9a1fcdfd
TG		 1566 if (mtd->ecc_stats.failed - stats.failed)
1567 return -EBADMSG;
1568
1569 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1570}
1571
1572/**
25985edc 1573 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1574 * @mtd: MTD device structure
1575 * @from: offset to read from
1576 * @len: number of bytes to read
1577 * @retlen: pointer to variable to store the number of read bytes
1578 * @buf: the databuffer to put data
f5bbdacc 1579 *
8b6e50c9 1580 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1581 */
1582static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1583 size_t *retlen, uint8_t *buf)
1584{
8593fbc6 1585 struct nand_chip *chip = mtd->priv;
4a89ff88 1586 struct mtd_oob_ops ops;
f5bbdacc
TG		 1587 int ret;
1588
f5bbdacc
TG		 1589 /* Do not allow reads past end of device */
1590 if ((from + len) > mtd->size)
1591 return -EINVAL;
1592 if (!len)
1593 return 0;
1594
8593fbc6 1595 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1596
4a89ff88
BN		 1597 ops.len = len;
1598 ops.datbuf = buf;
1599 ops.oobbuf = NULL;
23b1a99b 1600 ops.mode = 0;
8593fbc6 1601
4a89ff88 1602 ret = nand_do_read_ops(mtd, from, &ops);
f5bbdacc 1603
4a89ff88 1604 *retlen = ops.retlen;
7fd5aecc 1605
f5bbdacc
TG		 1606 nand_release_device(mtd);
1607
1608 return ret;
1da177e4
LT		 1609}
1610
7bc3312b 1611/**
7854d3f7 1612 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1613 * @mtd: mtd info structure
1614 * @chip: nand chip info structure
1615 * @page: page number to read
1616 * @sndcmd: flag whether to issue read command or not
7bc3312b
TG		 1617 */
1618static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1619 int page, int sndcmd)
1620{
1621 if (sndcmd) {
1622 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1623 sndcmd = 0;
1624 }
1625 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1626 return sndcmd;
1627}
1628
1629/**
7854d3f7 1630 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1631 * with syndromes
8b6e50c9
BN		 1632 * @mtd: mtd info structure
1633 * @chip: nand chip info structure
1634 * @page: page number to read
1635 * @sndcmd: flag whether to issue read command or not
7bc3312b
TG		 1636 */
1637static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1638 int page, int sndcmd)
1639{
1640 uint8_t *buf = chip->oob_poi;
1641 int length = mtd->oobsize;
1642 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1643 int eccsize = chip->ecc.size;
1644 uint8_t *bufpoi = buf;
1645 int i, toread, sndrnd = 0, pos;
1646
1647 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1648 for (i = 0; i < chip->ecc.steps; i++) {
1649 if (sndrnd) {
1650 pos = eccsize + i * (eccsize + chunk);
1651 if (mtd->writesize > 512)
1652 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1653 else
1654 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1655 } else
1656 sndrnd = 1;
1657 toread = min_t(int, length, chunk);
1658 chip->read_buf(mtd, bufpoi, toread);
1659 bufpoi += toread;
1660 length -= toread;
1661 }
1662 if (length > 0)
1663 chip->read_buf(mtd, bufpoi, length);
1664
1665 return 1;
1666}
1667
1668/**
7854d3f7 1669 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1670 * @mtd: mtd info structure
1671 * @chip: nand chip info structure
1672 * @page: page number to write
7bc3312b
TG		 1673 */
1674static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1675 int page)
1676{
1677 int status = 0;
1678 const uint8_t *buf = chip->oob_poi;
1679 int length = mtd->oobsize;
1680
1681 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1682 chip->write_buf(mtd, buf, length);
1683 /* Send command to program the OOB data */
1684 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1685
1686 status = chip->waitfunc(mtd, chip);
1687
0d420f9d 1688 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1689}
1690
1691/**
7854d3f7 1692 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1693 * with syndrome - only for large page flash
1694 * @mtd: mtd info structure
1695 * @chip: nand chip info structure
1696 * @page: page number to write
7bc3312b
TG		 1697 */
1698static int nand_write_oob_syndrome(struct mtd_info *mtd,
1699 struct nand_chip *chip, int page)
1700{
1701 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1702 int eccsize = chip->ecc.size, length = mtd->oobsize;
1703 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1704 const uint8_t *bufpoi = chip->oob_poi;
1705
1706 /*
1707 * data-ecc-data-ecc ... ecc-oob
1708 * or
1709 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1710 */
1711 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1712 pos = steps * (eccsize + chunk);
1713 steps = 0;
1714 } else
8b0036ee 1715 pos = eccsize;
7bc3312b
TG		 1716
1717 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1718 for (i = 0; i < steps; i++) {
1719 if (sndcmd) {
1720 if (mtd->writesize <= 512) {
1721 uint32_t fill = 0xFFFFFFFF;
1722
1723 len = eccsize;
1724 while (len > 0) {
1725 int num = min_t(int, len, 4);
1726 chip->write_buf(mtd, (uint8_t *)&fill,
1727 num);
1728 len -= num;
1729 }
1730 } else {
1731 pos = eccsize + i * (eccsize + chunk);
1732 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1733 }
1734 } else
1735 sndcmd = 1;
1736 len = min_t(int, length, chunk);
1737 chip->write_buf(mtd, bufpoi, len);
1738 bufpoi += len;
1739 length -= len;
1740 }
1741 if (length > 0)
1742 chip->write_buf(mtd, bufpoi, length);
1743
1744 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1745 status = chip->waitfunc(mtd, chip);
1746
1747 return status & NAND_STATUS_FAIL ? -EIO : 0;
1748}
1749
1da177e4 1750/**
7854d3f7 1751 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1752 * @mtd: MTD device structure
1753 * @from: offset to read from
1754 * @ops: oob operations description structure
1da177e4 1755 *
8b6e50c9 1756 * NAND read out-of-band data from the spare area.
1da177e4 1757 */
8593fbc6
TG		 1758static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1759 struct mtd_oob_ops *ops)
1da177e4 1760{
7bc3312b 1761 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1762 struct nand_chip *chip = mtd->priv;
041e4575 1763 struct mtd_ecc_stats stats;
7314e9e7 1764 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1765 int readlen = ops->ooblen;
1766 int len;
7bc3312b 1767 uint8_t *buf = ops->oobbuf;
61b03bd7 1768
289c0522 1769 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1770 __func__, (unsigned long long)from, readlen);
1da177e4 1771
041e4575
BN		 1772 stats = mtd->ecc_stats;
1773
0612b9dd 1774 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1775 len = chip->ecc.layout->oobavail;
03736155
AH		 1776 else
1777 len = mtd->oobsize;
1778
1779 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1780 pr_debug("%s: attempt to start read outside oob\n",
1781 __func__);
03736155
AH		 1782 return -EINVAL;
1783 }
1784
1785 /* Do not allow reads past end of device */
1786 if (unlikely(from >= mtd->size ||
1787 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1788 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1789 pr_debug("%s: attempt to read beyond end of device\n",
1790 __func__);
03736155
AH		 1791 return -EINVAL;
1792 }
7014568b 1793
7314e9e7 1794 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1795 chip->select_chip(mtd, chipnr);
1da177e4 1796
7314e9e7
TG		 1797 /* Shift to get page */
1798 realpage = (int)(from >> chip->page_shift);
1799 page = realpage & chip->pagemask;
1da177e4 1800
f8ac0414 1801 while (1) {
0612b9dd 1802 if (ops->mode == MTD_OPS_RAW)
c46f6483
BN		 1803 sndcmd = chip->ecc.read_oob_raw(mtd, chip, page, sndcmd);
1804 else
1805 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1806
1807 len = min(len, readlen);
1808 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1809
7314e9e7
TG		 1810 if (!(chip->options & NAND_NO_READRDY)) {
1811 /*
1812 * Apply delay or wait for ready/busy pin. Do this
1813 * before the AUTOINCR check, so no problems arise if a
1814 * chip which does auto increment is marked as
1815 * NOAUTOINCR by the board driver.
19870da7 1816 */
ace4dfee
TG		 1817 if (!chip->dev_ready)
1818 udelay(chip->chip_delay);
19870da7
TG		 1819 else
1820 nand_wait_ready(mtd);
7314e9e7 1821 }
19870da7 1822
7014568b 1823 readlen -= len;
0d420f9d
SZ		 1824 if (!readlen)
1825 break;
1826
7314e9e7
TG		 1827 /* Increment page address */
1828 realpage++;
1829
1830 page = realpage & chip->pagemask;
1831 /* Check, if we cross a chip boundary */
1832 if (!page) {
1833 chipnr++;
1834 chip->select_chip(mtd, -1);
1835 chip->select_chip(mtd, chipnr);
1da177e4 1836 }
7314e9e7 1837
8b6e50c9
BN		 1838 /*
1839 * Check, if the chip supports auto page increment or if we
1840 * have hit a block boundary.
7314e9e7
TG		 1841 */
1842 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1843 sndcmd = 1;
1da177e4
LT		 1844 }
1845
7014568b 1846 ops->oobretlen = ops->ooblen;
041e4575
BN		 1847
1848 if (mtd->ecc_stats.failed - stats.failed)
1849 return -EBADMSG;
1850
1851 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1852}
1853
1854/**
8593fbc6 1855 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1856 * @mtd: MTD device structure
1857 * @from: offset to read from
1858 * @ops: oob operation description structure
1da177e4 1859 *
8b6e50c9 1860 * NAND read data and/or out-of-band data.
1da177e4 1861 */
8593fbc6
TG		 1862static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1863 struct mtd_oob_ops *ops)
1da177e4 1864{
ace4dfee 1865 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1866 int ret = -ENOTSUPP;
1867
1868 ops->retlen = 0;
1da177e4
LT		 1869
1870 /* Do not allow reads past end of device */
7014568b 1871 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1872 pr_debug("%s: attempt to read beyond end of device\n",
1873 __func__);
1da177e4
LT		 1874 return -EINVAL;
1875 }
1876
ace4dfee 1877 nand_get_device(chip, mtd, FL_READING);
1da177e4 1878
f8ac0414 1879 switch (ops->mode) {
0612b9dd
BN		 1880 case MTD_OPS_PLACE_OOB:
1881 case MTD_OPS_AUTO_OOB:
1882 case MTD_OPS_RAW:
8593fbc6 1883 break;
1da177e4 1884
8593fbc6
TG		 1885 default:
1886 goto out;
1887 }
1da177e4 1888
8593fbc6
TG		 1889 if (!ops->datbuf)
1890 ret = nand_do_read_oob(mtd, from, ops);
1891 else
1892 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1893
7351d3a5 1894out:
8593fbc6
TG		 1895 nand_release_device(mtd);
1896 return ret;
1897}
61b03bd7 1898
1da177e4 1899
8593fbc6 1900/**
7854d3f7 1901 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1902 * @mtd: mtd info structure
1903 * @chip: nand chip info structure
1904 * @buf: data buffer
52ff49df 1905 *
7854d3f7 1906 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1907 */
1908static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1909 const uint8_t *buf)
1910{
1911 chip->write_buf(mtd, buf, mtd->writesize);
1912 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1913}
1914
52ff49df 1915/**
7854d3f7 1916 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1917 * @mtd: mtd info structure
1918 * @chip: nand chip info structure
1919 * @buf: data buffer
52ff49df
DB		 1920 *
1921 * We need a special oob layout and handling even when ECC isn't checked.
1922 */
7351d3a5
FF		 1923static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1924 struct nand_chip *chip,
1925 const uint8_t *buf)
52ff49df
DB		 1926{
1927 int eccsize = chip->ecc.size;
1928 int eccbytes = chip->ecc.bytes;
1929 uint8_t *oob = chip->oob_poi;
1930 int steps, size;
1931
1932 for (steps = chip->ecc.steps; steps > 0; steps--) {
1933 chip->write_buf(mtd, buf, eccsize);
1934 buf += eccsize;
1935
1936 if (chip->ecc.prepad) {
1937 chip->write_buf(mtd, oob, chip->ecc.prepad);
1938 oob += chip->ecc.prepad;
1939 }
1940
1941 chip->read_buf(mtd, oob, eccbytes);
1942 oob += eccbytes;
1943
1944 if (chip->ecc.postpad) {
1945 chip->write_buf(mtd, oob, chip->ecc.postpad);
1946 oob += chip->ecc.postpad;
1947 }
1948 }
1949
1950 size = mtd->oobsize - (oob - chip->oob_poi);
1951 if (size)
1952 chip->write_buf(mtd, oob, size);
1953}
9223a456 1954/**
7854d3f7 1955 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1956 * @mtd: mtd info structure
1957 * @chip: nand chip info structure
1958 * @buf: data buffer
9223a456 1959 */
f75e5097
TG		 1960static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1961 const uint8_t *buf)
9223a456 1962{
f75e5097
TG		 1963 int i, eccsize = chip->ecc.size;
1964 int eccbytes = chip->ecc.bytes;
1965 int eccsteps = chip->ecc.steps;
4bf63fcb 1966 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1967 const uint8_t *p = buf;
8b099a39 1968 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1969
7854d3f7 1970 /* Software ECC calculation */
8593fbc6
TG		 1971 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1972 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1973
8593fbc6
TG		 1974 for (i = 0; i < chip->ecc.total; i++)
1975 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1976
90424de8 1977 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1978}
9223a456 1979
f75e5097 1980/**
7854d3f7 1981 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 1982 * @mtd: mtd info structure
1983 * @chip: nand chip info structure
1984 * @buf: data buffer
f75e5097
TG		 1985 */
1986static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1987 const uint8_t *buf)
1988{
1989 int i, eccsize = chip->ecc.size;
1990 int eccbytes = chip->ecc.bytes;
1991 int eccsteps = chip->ecc.steps;
4bf63fcb 1992 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1993 const uint8_t *p = buf;
8b099a39 1994 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1995
f75e5097
TG		 1996 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1997 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1998 chip->write_buf(mtd, p, eccsize);
f75e5097 1999 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2000 }
2001
f75e5097
TG		 2002 for (i = 0; i < chip->ecc.total; i++)
2003 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2004
2005 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 2006}
2007
61b03bd7 2008/**
7854d3f7 2009 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2010 * @mtd: mtd info structure
2011 * @chip: nand chip info structure
2012 * @buf: data buffer
1da177e4 2013 *
8b6e50c9
BN		 2014 * The hw generator calculates the error syndrome automatically. Therefore we
2015 * need a special oob layout and handling.
f75e5097
TG		 2016 */
2017static void nand_write_page_syndrome(struct mtd_info *mtd,
2018 struct nand_chip *chip, const uint8_t *buf)
1da177e4 2019{
f75e5097
TG		 2020 int i, eccsize = chip->ecc.size;
2021 int eccbytes = chip->ecc.bytes;
2022 int eccsteps = chip->ecc.steps;
2023 const uint8_t *p = buf;
2024 uint8_t *oob = chip->oob_poi;
1da177e4 2025
f75e5097 2026 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2027
f75e5097
TG		 2028 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2029 chip->write_buf(mtd, p, eccsize);
61b03bd7 2030
f75e5097
TG		 2031 if (chip->ecc.prepad) {
2032 chip->write_buf(mtd, oob, chip->ecc.prepad);
2033 oob += chip->ecc.prepad;
2034 }
2035
2036 chip->ecc.calculate(mtd, p, oob);
2037 chip->write_buf(mtd, oob, eccbytes);
2038 oob += eccbytes;
2039
2040 if (chip->ecc.postpad) {
2041 chip->write_buf(mtd, oob, chip->ecc.postpad);
2042 oob += chip->ecc.postpad;
1da177e4 2043 }
1da177e4 2044 }
f75e5097
TG		 2045
2046 /* Calculate remaining oob bytes */
7e4178f9 2047 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2048 if (i)
2049 chip->write_buf(mtd, oob, i);
2050}
2051
2052/**
956e944c 2053 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2054 * @mtd: MTD device structure
2055 * @chip: NAND chip descriptor
2056 * @buf: the data to write
2057 * @page: page number to write
2058 * @cached: cached programming
2059 * @raw: use _raw version of write_page
f75e5097
TG		 2060 */
2061static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 2062 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 2063{
2064 int status;
2065
2066 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2067
956e944c
DW		 2068 if (unlikely(raw))
2069 chip->ecc.write_page_raw(mtd, chip, buf);
2070 else
2071 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 2072
2073 /*
7854d3f7 2074 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2075 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2076 */
2077 cached = 0;
2078
2079 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2080
2081 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2082 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2083 /*
2084 * See if operation failed and additional status checks are
8b6e50c9 2085 * available.
f75e5097
TG		 2086 */
2087 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2088 status = chip->errstat(mtd, chip, FL_WRITING, status,
2089 page);
2090
2091 if (status & NAND_STATUS_FAIL)
2092 return -EIO;
2093 } else {
2094 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2095 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2096 }
2097
2098#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2099 /* Send command to read back the data */
2100 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2101
2102 if (chip->verify_buf(mtd, buf, mtd->writesize))
2103 return -EIO;
2104#endif
2105 return 0;
1da177e4
LT		 2106}
2107
8593fbc6 2108/**
7854d3f7 2109 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2110 * @mtd: MTD device structure
8b6e50c9
BN		 2111 * @oob: oob data buffer
2112 * @len: oob data write length
2113 * @ops: oob ops structure
8593fbc6 2114 */
f722013e
TAA		 2115static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2116 struct mtd_oob_ops *ops)
8593fbc6 2117{
f722013e
TAA		 2118 struct nand_chip *chip = mtd->priv;
2119
2120 /*
2121 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2122 * data from a previous OOB read.
2123 */
2124 memset(chip->oob_poi, 0xff, mtd->oobsize);
2125
f8ac0414 2126 switch (ops->mode) {
8593fbc6 2127
0612b9dd
BN		 2128 case MTD_OPS_PLACE_OOB:
2129 case MTD_OPS_RAW:
8593fbc6
TG		 2130 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2131 return oob + len;
2132
0612b9dd 2133 case MTD_OPS_AUTO_OOB: {
8593fbc6 2134 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2135 uint32_t boffs = 0, woffs = ops->ooboffs;
2136 size_t bytes = 0;
8593fbc6 2137
f8ac0414 2138 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2139 /* Write request not from offset 0? */
7bc3312b
TG		 2140 if (unlikely(woffs)) {
2141 if (woffs >= free->length) {
2142 woffs -= free->length;
2143 continue;
2144 }
2145 boffs = free->offset + woffs;
2146 bytes = min_t(size_t, len,
2147 (free->length - woffs));
2148 woffs = 0;
2149 } else {
2150 bytes = min_t(size_t, len, free->length);
2151 boffs = free->offset;
2152 }
8b0036ee 2153 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2154 oob += bytes;
2155 }
2156 return oob;
2157 }
2158 default:
2159 BUG();
2160 }
2161 return NULL;
2162}
2163
f8ac0414 2164#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2165
2166/**
7854d3f7 2167 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2168 * @mtd: MTD device structure
2169 * @to: offset to write to
2170 * @ops: oob operations description structure
1da177e4 2171 *
8b6e50c9 2172 * NAND write with ECC.
1da177e4 2173 */
8593fbc6
TG		 2174static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2175 struct mtd_oob_ops *ops)
1da177e4 2176{
29072b96 2177 int chipnr, realpage, page, blockmask, column;
ace4dfee 2178 struct nand_chip *chip = mtd->priv;
8593fbc6 2179 uint32_t writelen = ops->len;
782ce79a
ML		 2180
2181 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2182 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2183 mtd->oobavail : mtd->oobsize;
2184
8593fbc6
TG		 2185 uint8_t *oob = ops->oobbuf;
2186 uint8_t *buf = ops->datbuf;
29072b96 2187 int ret, subpage;
1da177e4 2188
8593fbc6 2189 ops->retlen = 0;
29072b96
TG		 2190 if (!writelen)
2191 return 0;
1da177e4 2192
8b6e50c9 2193 /* Reject writes, which are not page aligned */
8593fbc6 2194 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2195 pr_notice("%s: attempt to write non page aligned data\n",
2196 __func__);
1da177e4
LT		 2197 return -EINVAL;
2198 }
2199
29072b96
TG		 2200 column = to & (mtd->writesize - 1);
2201 subpage = column || (writelen & (mtd->writesize - 1));
2202
2203 if (subpage && oob)
2204 return -EINVAL;
1da177e4 2205
6a930961
TG		 2206 chipnr = (int)(to >> chip->chip_shift);
2207 chip->select_chip(mtd, chipnr);
2208
1da177e4
LT		 2209 /* Check, if it is write protected */
2210 if (nand_check_wp(mtd))
8593fbc6 2211 return -EIO;
1da177e4 2212
f75e5097
TG		 2213 realpage = (int)(to >> chip->page_shift);
2214 page = realpage & chip->pagemask;
2215 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2216
2217 /* Invalidate the page cache, when we write to the cached page */
2218 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2219 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2220 chip->pagebuf = -1;
61b03bd7 2221
782ce79a 2222 /* Don't allow multipage oob writes with offset */
cdcf12b2 2223 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2224 return -EINVAL;
2225
f8ac0414 2226 while (1) {
29072b96 2227 int bytes = mtd->writesize;
f75e5097 2228 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2229 uint8_t *wbuf = buf;
2230
8b6e50c9 2231 /* Partial page write? */
29072b96
TG		 2232 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2233 cached = 0;
2234 bytes = min_t(int, bytes - column, (int) writelen);
2235 chip->pagebuf = -1;
2236 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2237 memcpy(&chip->buffers->databuf[column], buf, bytes);
2238 wbuf = chip->buffers->databuf;
2239 }
1da177e4 2240
782ce79a
ML		 2241 if (unlikely(oob)) {
2242 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2243 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2244 oobwritelen -= len;
f722013e
TAA		 2245 } else {
2246 /* We still need to erase leftover OOB data */
2247 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2248 }
8593fbc6 2249
29072b96 2250 ret = chip->write_page(mtd, chip, wbuf, page, cached,
0612b9dd 2251 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2252 if (ret)
2253 break;
2254
2255 writelen -= bytes;
2256 if (!writelen)
2257 break;
2258
29072b96 2259 column = 0;
f75e5097
TG		 2260 buf += bytes;
2261 realpage++;
2262
2263 page = realpage & chip->pagemask;
2264 /* Check, if we cross a chip boundary */
2265 if (!page) {
2266 chipnr++;
2267 chip->select_chip(mtd, -1);
2268 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2269 }
2270 }
8593fbc6 2271
8593fbc6 2272 ops->retlen = ops->len - writelen;
7014568b
VW		 2273 if (unlikely(oob))
2274 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2275 return ret;
2276}
2277
2af7c653
SK		 2278/**
2279 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2280 * @mtd: MTD device structure
2281 * @to: offset to write to
2282 * @len: number of bytes to write
2283 * @retlen: pointer to variable to store the number of written bytes
2284 * @buf: the data to write
2af7c653
SK		 2285 *
2286 * NAND write with ECC. Used when performing writes in interrupt context, this
2287 * may for example be called by mtdoops when writing an oops while in panic.
2288 */
2289static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2290 size_t *retlen, const uint8_t *buf)
2291{
2292 struct nand_chip *chip = mtd->priv;
4a89ff88 2293 struct mtd_oob_ops ops;
2af7c653
SK		 2294 int ret;
2295
2296 /* Do not allow reads past end of device */
2297 if ((to + len) > mtd->size)
2298 return -EINVAL;
2299 if (!len)
2300 return 0;
2301
8b6e50c9 2302 /* Wait for the device to get ready */
2af7c653
SK		 2303 panic_nand_wait(mtd, chip, 400);
2304
8b6e50c9 2305 /* Grab the device */
2af7c653
SK		 2306 panic_nand_get_device(chip, mtd, FL_WRITING);
2307
4a89ff88
BN		 2308 ops.len = len;
2309 ops.datbuf = (uint8_t *)buf;
2310 ops.oobbuf = NULL;
23b1a99b 2311 ops.mode = 0;
2af7c653 2312
4a89ff88 2313 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2314
4a89ff88 2315 *retlen = ops.retlen;
2af7c653
SK		 2316 return ret;
2317}
2318
f75e5097 2319/**
8593fbc6 2320 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2321 * @mtd: MTD device structure
2322 * @to: offset to write to
2323 * @len: number of bytes to write
2324 * @retlen: pointer to variable to store the number of written bytes
2325 * @buf: the data to write
f75e5097 2326 *
8b6e50c9 2327 * NAND write with ECC.
f75e5097 2328 */
8593fbc6
TG		 2329static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2330 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2331{
2332 struct nand_chip *chip = mtd->priv;
4a89ff88 2333 struct mtd_oob_ops ops;
f75e5097
TG		 2334 int ret;
2335
8593fbc6
TG		 2336 /* Do not allow reads past end of device */
2337 if ((to + len) > mtd->size)
f75e5097 2338 return -EINVAL;
8593fbc6
TG		 2339 if (!len)
2340 return 0;
f75e5097 2341
7bc3312b 2342 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 2343
4a89ff88
BN		 2344 ops.len = len;
2345 ops.datbuf = (uint8_t *)buf;
2346 ops.oobbuf = NULL;
23b1a99b 2347 ops.mode = 0;
f75e5097 2348
4a89ff88 2349 ret = nand_do_write_ops(mtd, to, &ops);
f75e5097 2350
4a89ff88 2351 *retlen = ops.retlen;
7fd5aecc 2352
f75e5097 2353 nand_release_device(mtd);
8593fbc6 2354
8593fbc6 2355 return ret;
f75e5097 2356}
7314e9e7 2357
1da177e4 2358/**
8593fbc6 2359 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2360 * @mtd: MTD device structure
2361 * @to: offset to write to
2362 * @ops: oob operation description structure
1da177e4 2363 *
8b6e50c9 2364 * NAND write out-of-band.
1da177e4 2365 */
8593fbc6
TG		 2366static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2367 struct mtd_oob_ops *ops)
1da177e4 2368{
03736155 2369 int chipnr, page, status, len;
ace4dfee 2370 struct nand_chip *chip = mtd->priv;
1da177e4 2371
289c0522 2372 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2373 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2374
0612b9dd 2375 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2376 len = chip->ecc.layout->oobavail;
2377 else
2378 len = mtd->oobsize;
2379
1da177e4 2380 /* Do not allow write past end of page */
03736155 2381 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2382 pr_debug("%s: attempt to write past end of page\n",
2383 __func__);
1da177e4
LT		 2384 return -EINVAL;
2385 }
2386
03736155 2387 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2388 pr_debug("%s: attempt to start write outside oob\n",
2389 __func__);
03736155
AH		 2390 return -EINVAL;
2391 }
2392
775adc3d 2393 /* Do not allow write past end of device */
03736155
AH		 2394 if (unlikely(to >= mtd->size ||
2395 ops->ooboffs + ops->ooblen >
2396 ((mtd->size >> chip->page_shift) -
2397 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2398 pr_debug("%s: attempt to write beyond end of device\n",
2399 __func__);
03736155
AH		 2400 return -EINVAL;
2401 }
2402
7314e9e7 2403 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2404 chip->select_chip(mtd, chipnr);
1da177e4 2405
7314e9e7
TG		 2406 /* Shift to get page */
2407 page = (int)(to >> chip->page_shift);
2408
2409 /*
2410 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2411 * of my DiskOnChip 2000 test units) will clear the whole data page too
2412 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2413 * it in the doc2000 driver in August 1999. dwmw2.
2414 */
ace4dfee 2415 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2416
2417 /* Check, if it is write protected */
2418 if (nand_check_wp(mtd))
8593fbc6 2419 return -EROFS;
61b03bd7 2420
1da177e4 2421 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2422 if (page == chip->pagebuf)
2423 chip->pagebuf = -1;
1da177e4 2424
f722013e 2425 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2426
0612b9dd 2427 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2428 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2429 else
2430 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2431
7bc3312b
TG		 2432 if (status)
2433 return status;
1da177e4 2434
7014568b 2435 ops->oobretlen = ops->ooblen;
1da177e4 2436
7bc3312b 2437 return 0;
8593fbc6
TG		 2438}
2439
2440/**
2441 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2442 * @mtd: MTD device structure
2443 * @to: offset to write to
2444 * @ops: oob operation description structure
8593fbc6
TG		 2445 */
2446static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2447 struct mtd_oob_ops *ops)
2448{
8593fbc6
TG		 2449 struct nand_chip *chip = mtd->priv;
2450 int ret = -ENOTSUPP;
2451
2452 ops->retlen = 0;
2453
2454 /* Do not allow writes past end of device */
7014568b 2455 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2456 pr_debug("%s: attempt to write beyond end of device\n",
2457 __func__);
8593fbc6
TG		 2458 return -EINVAL;
2459 }
2460
7bc3312b 2461 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2462
f8ac0414 2463 switch (ops->mode) {
0612b9dd
BN		 2464 case MTD_OPS_PLACE_OOB:
2465 case MTD_OPS_AUTO_OOB:
2466 case MTD_OPS_RAW:
8593fbc6
TG		 2467 break;
2468
2469 default:
2470 goto out;
2471 }
2472
2473 if (!ops->datbuf)
2474 ret = nand_do_write_oob(mtd, to, ops);
2475 else
2476 ret = nand_do_write_ops(mtd, to, ops);
2477
7351d3a5 2478out:
1da177e4 2479 nand_release_device(mtd);
1da177e4
LT		 2480 return ret;
2481}
2482
1da177e4 2483/**
7854d3f7 2484 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2485 * @mtd: MTD device structure
2486 * @page: the page address of the block which will be erased
1da177e4 2487 *
8b6e50c9 2488 * Standard erase command for NAND chips.
1da177e4 2489 */
e0c7d767 2490static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2491{
ace4dfee 2492 struct nand_chip *chip = mtd->priv;
1da177e4 2493 /* Send commands to erase a block */
ace4dfee
TG		 2494 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2495 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2496}
2497
2498/**
7854d3f7 2499 * multi_erase_cmd - [GENERIC] AND specific block erase command function
8b6e50c9
BN		 2500 * @mtd: MTD device structure
2501 * @page: the page address of the block which will be erased
1da177e4 2502 *
8b6e50c9 2503 * AND multi block erase command function. Erase 4 consecutive blocks.
1da177e4 2504 */
e0c7d767 2505static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2506{
ace4dfee 2507 struct nand_chip *chip = mtd->priv;
1da177e4 2508 /* Send commands to erase a block */
ace4dfee
TG		 2509 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2510 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2511 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2512 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2513 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2514}
2515
2516/**
2517 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2518 * @mtd: MTD device structure
2519 * @instr: erase instruction
1da177e4 2520 *
8b6e50c9 2521 * Erase one ore more blocks.
1da177e4 2522 */
e0c7d767 2523static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2524{
e0c7d767 2525 return nand_erase_nand(mtd, instr, 0);
1da177e4 2526}
61b03bd7 2527
30f464b7 2528#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2529/**
7854d3f7 2530 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2531 * @mtd: MTD device structure
2532 * @instr: erase instruction
2533 * @allowbbt: allow erasing the bbt area
1da177e4 2534 *
8b6e50c9 2535 * Erase one ore more blocks.
1da177e4 2536 */
ace4dfee
TG		 2537int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2538 int allowbbt)
1da177e4 2539{
69423d99 2540 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2541 struct nand_chip *chip = mtd->priv;
f8ac0414 2542 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2543 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2544 loff_t len;
1da177e4 2545
289c0522
BN		 2546 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2547 __func__, (unsigned long long)instr->addr,
2548 (unsigned long long)instr->len);
1da177e4 2549
6fe5a6ac 2550 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2551 return -EINVAL;
1da177e4 2552
bb0eb217 2553 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2554
2555 /* Grab the lock and see if the device is available */
ace4dfee 2556 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2557
2558 /* Shift to get first page */
ace4dfee
TG		 2559 page = (int)(instr->addr >> chip->page_shift);
2560 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2561
2562 /* Calculate pages in each block */
ace4dfee 2563 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2564
2565 /* Select the NAND device */
ace4dfee 2566 chip->select_chip(mtd, chipnr);
1da177e4 2567
1da177e4
LT		 2568 /* Check, if it is write protected */
2569 if (nand_check_wp(mtd)) {
289c0522
BN		 2570 pr_debug("%s: device is write protected!\n",
2571 __func__);
1da177e4
LT		 2572 instr->state = MTD_ERASE_FAILED;
2573 goto erase_exit;
2574 }
2575
ace4dfee
TG		 2576 /*
2577 * If BBT requires refresh, set the BBT page mask to see if the BBT
2578 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2579 * can not be matched. This is also done when the bbt is actually
7854d3f7 2580 * erased to avoid recursive updates.
ace4dfee
TG		 2581 */
2582 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2583 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2584
1da177e4
LT		 2585 /* Loop through the pages */
2586 len = instr->len;
2587
2588 instr->state = MTD_ERASING;
2589
2590 while (len) {
12183a20 2591 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2592 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2593 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2594 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2595 __func__, page);
1da177e4
LT		 2596 instr->state = MTD_ERASE_FAILED;
2597 goto erase_exit;
2598 }
61b03bd7 2599
ace4dfee
TG		 2600 /*
2601 * Invalidate the page cache, if we erase the block which
8b6e50c9 2602 * contains the current cached page.
ace4dfee
TG		 2603 */
2604 if (page <= chip->pagebuf && chip->pagebuf <
2605 (page + pages_per_block))
2606 chip->pagebuf = -1;
1da177e4 2607
ace4dfee 2608 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2609
7bc3312b 2610 status = chip->waitfunc(mtd, chip);
1da177e4 2611
ace4dfee
TG		 2612 /*
2613 * See if operation failed and additional status checks are
2614 * available
2615 */
2616 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2617 status = chip->errstat(mtd, chip, FL_ERASING,
2618 status, page);
068e3c0a 2619
1da177e4 2620 /* See if block erase succeeded */
a4ab4c5d 2621 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2622 pr_debug("%s: failed erase, page 0x%08x\n",
2623 __func__, page);
1da177e4 2624 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2625 instr->fail_addr =
2626 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2627 goto erase_exit;
2628 }
30f464b7 2629
ace4dfee
TG		 2630 /*
2631 * If BBT requires refresh, set the BBT rewrite flag to the
8b6e50c9 2632 * page being erased.
ace4dfee
TG		 2633 */
2634 if (bbt_masked_page != 0xffffffff &&
2635 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2636 rewrite_bbt[chipnr] =
2637 ((loff_t)page << chip->page_shift);
61b03bd7 2638
1da177e4 2639 /* Increment page address and decrement length */
ace4dfee 2640 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2641 page += pages_per_block;
2642
2643 /* Check, if we cross a chip boundary */
ace4dfee 2644 if (len && !(page & chip->pagemask)) {
1da177e4 2645 chipnr++;
ace4dfee
TG		 2646 chip->select_chip(mtd, -1);
2647 chip->select_chip(mtd, chipnr);
30f464b7 2648
ace4dfee
TG		 2649 /*
2650 * If BBT requires refresh and BBT-PERCHIP, set the BBT
8b6e50c9 2651 * page mask to see if this BBT should be rewritten.
ace4dfee
TG		 2652 */
2653 if (bbt_masked_page != 0xffffffff &&
2654 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2655 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2656 BBT_PAGE_MASK;
1da177e4
LT		 2657 }
2658 }
2659 instr->state = MTD_ERASE_DONE;
2660
7351d3a5 2661erase_exit:
1da177e4
LT		 2662
2663 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2664
2665 /* Deselect and wake up anyone waiting on the device */
2666 nand_release_device(mtd);
2667
49defc01
DW		 2668 /* Do call back function */
2669 if (!ret)
2670 mtd_erase_callback(instr);
2671
ace4dfee
TG		 2672 /*
2673 * If BBT requires refresh and erase was successful, rewrite any
8b6e50c9 2674 * selected bad block tables.
ace4dfee
TG		 2675 */
2676 if (bbt_masked_page == 0xffffffff || ret)
2677 return ret;
2678
2679 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2680 if (!rewrite_bbt[chipnr])
2681 continue;
8b6e50c9 2682 /* Update the BBT for chip */
289c0522
BN		 2683 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2684 __func__, chipnr, rewrite_bbt[chipnr],
2685 chip->bbt_td->pages[chipnr]);
ace4dfee 2686 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2687 }
2688
1da177e4
LT		 2689 /* Return more or less happy */
2690 return ret;
2691}
2692
2693/**
2694 * nand_sync - [MTD Interface] sync
8b6e50c9 2695 * @mtd: MTD device structure
1da177e4 2696 *
8b6e50c9 2697 * Sync is actually a wait for chip ready function.
1da177e4 2698 */
e0c7d767 2699static void nand_sync(struct mtd_info *mtd)
1da177e4 2700{
ace4dfee 2701 struct nand_chip *chip = mtd->priv;
1da177e4 2702
289c0522 2703 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2704
2705 /* Grab the lock and see if the device is available */
ace4dfee 2706 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2707 /* Release it and go back */
e0c7d767 2708 nand_release_device(mtd);
1da177e4
LT		 2709}
2710
1da177e4 2711/**
ace4dfee 2712 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2713 * @mtd: MTD device structure
2714 * @offs: offset relative to mtd start
1da177e4 2715 */
ace4dfee 2716static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2717{
2718 /* Check for invalid offset */
ace4dfee 2719 if (offs > mtd->size)
1da177e4 2720 return -EINVAL;
61b03bd7 2721
ace4dfee 2722 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2723}
2724
2725/**
ace4dfee 2726 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2727 * @mtd: MTD device structure
2728 * @ofs: offset relative to mtd start
1da177e4 2729 */
e0c7d767 2730static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2731{
ace4dfee 2732 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2733 int ret;
2734
f8ac0414
FF		 2735 ret = nand_block_isbad(mtd, ofs);
2736 if (ret) {
8b6e50c9 2737 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2738 if (ret > 0)
2739 return 0;
e0c7d767
DW		 2740 return ret;
2741 }
1da177e4 2742
ace4dfee 2743 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2744}
2745
962034f4
VW		 2746/**
2747 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2748 * @mtd: MTD device structure
962034f4
VW		 2749 */
2750static int nand_suspend(struct mtd_info *mtd)
2751{
ace4dfee 2752 struct nand_chip *chip = mtd->priv;
962034f4 2753
ace4dfee 2754 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2755}
2756
2757/**
2758 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2759 * @mtd: MTD device structure
962034f4
VW		 2760 */
2761static void nand_resume(struct mtd_info *mtd)
2762{
ace4dfee 2763 struct nand_chip *chip = mtd->priv;
962034f4 2764
ace4dfee 2765 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2766 nand_release_device(mtd);
2767 else
d0370219
BN		 2768 pr_err("%s called for a chip which is not in suspended state\n",
2769 __func__);
962034f4
VW		 2770}
2771
8b6e50c9 2772/* Set default functions */
ace4dfee 2773static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2774{
1da177e4 2775 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2776 if (!chip->chip_delay)
2777 chip->chip_delay = 20;
1da177e4
LT		 2778
2779 /* check, if a user supplied command function given */
ace4dfee
TG		 2780 if (chip->cmdfunc == NULL)
2781 chip->cmdfunc = nand_command;
1da177e4
LT		 2782
2783 /* check, if a user supplied wait function given */
ace4dfee
TG		 2784 if (chip->waitfunc == NULL)
2785 chip->waitfunc = nand_wait;
2786
2787 if (!chip->select_chip)
2788 chip->select_chip = nand_select_chip;
2789 if (!chip->read_byte)
2790 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2791 if (!chip->read_word)
2792 chip->read_word = nand_read_word;
2793 if (!chip->block_bad)
2794 chip->block_bad = nand_block_bad;
2795 if (!chip->block_markbad)
2796 chip->block_markbad = nand_default_block_markbad;
2797 if (!chip->write_buf)
2798 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2799 if (!chip->read_buf)
2800 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2801 if (!chip->verify_buf)
2802 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2803 if (!chip->scan_bbt)
2804 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2805
2806 if (!chip->controller) {
2807 chip->controller = &chip->hwcontrol;
2808 spin_lock_init(&chip->controller->lock);
2809 init_waitqueue_head(&chip->controller->wq);
2810 }
2811
7aa65bfd
TG		 2812}
2813
8b6e50c9 2814/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2815static void sanitize_string(uint8_t *s, size_t len)
2816{
2817 ssize_t i;
2818
8b6e50c9 2819 /* Null terminate */
d1e1f4e4
FF		 2820 s[len - 1] = 0;
2821
8b6e50c9 2822 /* Remove non printable chars */
d1e1f4e4
FF		 2823 for (i = 0; i < len - 1; i++) {
2824 if (s[i] < ' ' || s[i] > 127)
2825 s[i] = '?';
2826 }
2827
8b6e50c9 2828 /* Remove trailing spaces */
d1e1f4e4
FF		 2829 strim(s);
2830}
2831
2832static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2833{
2834 int i;
2835 while (len--) {
2836 crc ^= *p++ << 8;
2837 for (i = 0; i < 8; i++)
2838 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2839 }
2840
2841 return crc;
2842}
2843
6fb277ba 2844/*
8b6e50c9 2845 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2846 */
2847static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2848 int *busw)
6fb277ba
FF		 2849{
2850 struct nand_onfi_params *p = &chip->onfi_params;
2851 int i;
2852 int val;
2853
7854d3f7 2854 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2855 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2856 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2857 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2858 return 0;
2859
9a4d4d69 2860 pr_info("ONFI flash detected\n");
6fb277ba
FF		 2861 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2862 for (i = 0; i < 3; i++) {
2863 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2864 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2865 le16_to_cpu(p->crc)) {
9a4d4d69 2866 pr_info("ONFI param page %d valid\n", i);
6fb277ba
FF		 2867 break;
2868 }
2869 }
2870
2871 if (i == 3)
2872 return 0;
2873
8b6e50c9 2874 /* Check version */
6fb277ba 2875 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2876 if (val & (1 << 5))
2877 chip->onfi_version = 23;
2878 else if (val & (1 << 4))
6fb277ba
FF		 2879 chip->onfi_version = 22;
2880 else if (val & (1 << 3))
2881 chip->onfi_version = 21;
2882 else if (val & (1 << 2))
2883 chip->onfi_version = 20;
b7b1a29d 2884 else if (val & (1 << 1))
6fb277ba 2885 chip->onfi_version = 10;
b7b1a29d
BN		 2886 else
2887 chip->onfi_version = 0;
2888
2889 if (!chip->onfi_version) {
d0370219 2890 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 2891 return 0;
2892 }
6fb277ba
FF		 2893
2894 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2895 sanitize_string(p->model, sizeof(p->model));
2896 if (!mtd->name)
2897 mtd->name = p->model;
2898 mtd->writesize = le32_to_cpu(p->byte_per_page);
2899 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2900 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4ccb3b44 2901 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
08c248fb 2902 *busw = 0;
6fb277ba 2903 if (le16_to_cpu(p->features) & 1)
08c248fb 2904 *busw = NAND_BUSWIDTH_16;
6fb277ba
FF		 2905
2906 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2907 chip->options |= (NAND_NO_READRDY |
2908 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2909
2910 return 1;
2911}
2912
7aa65bfd 2913/*
8b6e50c9 2914 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 2915 */
2916static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2917 struct nand_chip *chip,
7351d3a5
FF		 2918 int busw,
2919 int *maf_id, int *dev_id,
5e81e88a 2920 struct nand_flash_dev *type)
7aa65bfd 2921{
d1e1f4e4 2922 int i, maf_idx;
426c457a 2923 u8 id_data[8];
6fb277ba 2924 int ret;
1da177e4
LT		 2925
2926 /* Select the device */
ace4dfee 2927 chip->select_chip(mtd, 0);
1da177e4 2928
ef89a880
KB		 2929 /*
2930 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 2931 * after power-up.
ef89a880
KB		 2932 */
2933 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2934
1da177e4 2935 /* Send the command for reading device ID */
ace4dfee 2936 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2937
2938 /* Read manufacturer and device IDs */
ace4dfee 2939 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2940 *dev_id = chip->read_byte(mtd);
1da177e4 2941
8b6e50c9
BN		 2942 /*
2943 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 2944 * interface concerns can cause random data which looks like a
2945 * possibly credible NAND flash to appear. If the two results do
2946 * not match, ignore the device completely.
2947 */
2948
2949 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2950
d1e1f4e4 2951 for (i = 0; i < 2; i++)
426c457a 2952 id_data[i] = chip->read_byte(mtd);
ed8165c7 2953
d1e1f4e4 2954 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 2955 pr_info("%s: second ID read did not match "
d0370219
BN		 2956 "%02x,%02x against %02x,%02x\n", __func__,
2957 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2958 return ERR_PTR(-ENODEV);
2959 }
2960
7aa65bfd 2961 if (!type)
5e81e88a
DW		 2962 type = nand_flash_ids;
2963
2964 for (; type->name != NULL; type++)
d1e1f4e4 2965 if (*dev_id == type->id)
f8ac0414 2966 break;
5e81e88a 2967
d1e1f4e4
FF		 2968 chip->onfi_version = 0;
2969 if (!type->name || !type->pagesize) {
6fb277ba 2970 /* Check is chip is ONFI compliant */
08c248fb 2971 ret = nand_flash_detect_onfi(mtd, chip, &busw);
6fb277ba
FF		 2972 if (ret)
2973 goto ident_done;
d1e1f4e4
FF		 2974 }
2975
2976 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2977
2978 /* Read entire ID string */
2979
2980 for (i = 0; i < 8; i++)
2981 id_data[i] = chip->read_byte(mtd);
2982
5e81e88a 2983 if (!type->name)
7aa65bfd
TG		 2984 return ERR_PTR(-ENODEV);
2985
ba0251fe
TG		 2986 if (!mtd->name)
2987 mtd->name = type->name;
2988
69423d99 2989 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 2990
12a40a57 2991 if (!type->pagesize && chip->init_size) {
8b6e50c9 2992 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 2993 busw = chip->init_size(mtd, chip, id_data);
2994 } else if (!type->pagesize) {
7aa65bfd 2995 int extid;
29072b96 2996 /* The 3rd id byte holds MLC / multichip data */
426c457a 2997 chip->cellinfo = id_data[2];
7aa65bfd 2998 /* The 4th id byte is the important one */
426c457a 2999 extid = id_data[3];
61b03bd7 3000
426c457a
KC		 3001 /*
3002 * Field definitions are in the following datasheets:
3003 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 3004 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 3005 *
3006 * Check for wraparound + Samsung ID + nonzero 6th byte
3007 * to decide what to do.
3008 */
3009 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3010 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 3011 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 3012 id_data[5] != 0x00) {
3013 /* Calc pagesize */
3014 mtd->writesize = 2048 << (extid & 0x03);
3015 extid >>= 2;
3016 /* Calc oobsize */
34c5bf6c
BN		 3017 switch (extid & 0x03) {
3018 case 1:
3019 mtd->oobsize = 128;
3020 break;
3021 case 2:
3022 mtd->oobsize = 218;
3023 break;
3024 case 3:
3025 mtd->oobsize = 400;
3026 break;
3027 default:
3028 mtd->oobsize = 436;
3029 break;
3030 }
426c457a
KC		 3031 extid >>= 2;
3032 /* Calc blocksize */
3033 mtd->erasesize = (128 * 1024) <<
3034 (((extid >> 1) & 0x04) | (extid & 0x03));
3035 busw = 0;
3036 } else {
3037 /* Calc pagesize */
3038 mtd->writesize = 1024 << (extid & 0x03);
3039 extid >>= 2;
3040 /* Calc oobsize */
3041 mtd->oobsize = (8 << (extid & 0x01)) *
3042 (mtd->writesize >> 9);
3043 extid >>= 2;
3044 /* Calc blocksize. Blocksize is multiples of 64KiB */
3045 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3046 extid >>= 2;
3047 /* Get buswidth information */
3048 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3049 }
7aa65bfd
TG		 3050 } else {
3051 /*
8b6e50c9 3052 * Old devices have chip data hardcoded in the device id table.
7aa65bfd 3053 */
ba0251fe
TG		 3054 mtd->erasesize = type->erasesize;
3055 mtd->writesize = type->pagesize;
4cbb9b80 3056 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3057 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3058
3059 /*
3060 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3061 * some Spansion chips have erasesize that conflicts with size
8b6e50c9 3062 * listed in nand_ids table.
2173bae8
BN		 3063 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3064 */
3065 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3066 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3067 id_data[7] == 0x00 && mtd->writesize == 512) {
3068 mtd->erasesize = 128 * 1024;
3069 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3070 }
7aa65bfd 3071 }
d1e1f4e4
FF		 3072 /* Get chip options, preserve non chip based options */
3073 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3074 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3075
8b6e50c9
BN		 3076 /*
3077 * Check if chip is not a Samsung device. Do not clear the
3078 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3079 */
3080 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3081 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3082ident_done:
3083
3084 /*
8b6e50c9 3085 * Set chip as a default. Board drivers can override it, if necessary.
d1e1f4e4
FF		 3086 */
3087 chip->options |= NAND_NO_AUTOINCR;
1da177e4 3088
7aa65bfd 3089 /* Try to identify manufacturer */
9a909867 3090 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3091 if (nand_manuf_ids[maf_idx].id == *maf_id)
3092 break;
3093 }
0ea4a755 3094
7aa65bfd
TG		 3095 /*
3096 * Check, if buswidth is correct. Hardware drivers should set
8b6e50c9 3097 * chip correct!
7aa65bfd 3098 */
ace4dfee 3099 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
9a4d4d69 3100 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 3101 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3102 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 3103 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 3104 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3105 busw ? 16 : 8);
7aa65bfd
TG		 3106 return ERR_PTR(-EINVAL);
3107 }
61b03bd7 3108
7aa65bfd 3109 /* Calculate the address shift from the page size */
ace4dfee 3110 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3111 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3112 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3113
ace4dfee 3114 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3115 ffs(mtd->erasesize) - 1;
69423d99
AH		 3116 if (chip->chipsize & 0xffffffff)
3117 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3118 else {
3119 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3120 chip->chip_shift += 32 - 1;
3121 }
1da177e4 3122
26d9be11
AB		 3123 chip->badblockbits = 8;
3124
7aa65bfd 3125 /* Set the bad block position */
065a1ed8 3126 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3127 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3128 else
3129 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3130
b60b08b0
KC		 3131 /*
3132 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3133 * on Samsung and Hynix MLC devices; stored in first two pages
3134 * of each block on Micron devices with 2KiB pages and on
8c342335
BN		 3135 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
3136 * All others scan only the first page.
b60b08b0
KC		 3137 */
3138 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3139 (*maf_id == NAND_MFR_SAMSUNG ||
3140 *maf_id == NAND_MFR_HYNIX))
5fb1549d 3141 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3142 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3143 (*maf_id == NAND_MFR_SAMSUNG ||
3144 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3145 *maf_id == NAND_MFR_TOSHIBA ||
8c342335
BN		 3146 *maf_id == NAND_MFR_AMD ||
3147 *maf_id == NAND_MFR_MACRONIX)) ||
c7b28e25
BN		 3148 (mtd->writesize == 2048 &&
3149 *maf_id == NAND_MFR_MICRON))
5fb1549d 3150 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
c7b28e25 3151
7aa65bfd 3152 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3153 if (chip->options & NAND_4PAGE_ARRAY)
3154 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3155 else
ace4dfee 3156 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3157
8b6e50c9 3158 /* Do not replace user supplied command function! */
ace4dfee
TG		 3159 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3160 chip->cmdfunc = nand_command_lp;
7aa65bfd 3161
9a4d4d69 3162 pr_info("NAND device: Manufacturer ID:"
d1e1f4e4
FF		 3163 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3164 nand_manuf_ids[maf_idx].name,
0b524fb9 3165 chip->onfi_version ? chip->onfi_params.model : type->name);
7aa65bfd
TG		 3166
3167 return type;
3168}
3169
7aa65bfd 3170/**
3b85c321 3171 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3172 * @mtd: MTD device structure
3173 * @maxchips: number of chips to scan for
3174 * @table: alternative NAND ID table
7aa65bfd 3175 *
8b6e50c9
BN		 3176 * This is the first phase of the normal nand_scan() function. It reads the
3177 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3178 *
3b85c321 3179 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3180 */
5e81e88a
DW		 3181int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3182 struct nand_flash_dev *table)
7aa65bfd 3183{
d1e1f4e4 3184 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3185 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3186 struct nand_flash_dev *type;
3187
7aa65bfd 3188 /* Get buswidth to select the correct functions */
ace4dfee 3189 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3190 /* Set the default functions */
ace4dfee 3191 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3192
3193 /* Read the flash type */
7351d3a5
FF		 3194 type = nand_get_flash_type(mtd, chip, busw,
3195 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3196
3197 if (IS_ERR(type)) {
b1c6e6db 3198 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3199 pr_warn("No NAND device found\n");
ace4dfee 3200 chip->select_chip(mtd, -1);
7aa65bfd 3201 return PTR_ERR(type);
1da177e4
LT		 3202 }
3203
7aa65bfd 3204 /* Check for a chip array */
e0c7d767 3205 for (i = 1; i < maxchips; i++) {
ace4dfee 3206 chip->select_chip(mtd, i);
ef89a880
KB		 3207 /* See comment in nand_get_flash_type for reset */
3208 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3209 /* Send the command for reading device ID */
ace4dfee 3210 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3211 /* Read manufacturer and device IDs */
ace4dfee 3212 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3213 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3214 break;
3215 }
3216 if (i > 1)
9a4d4d69 3217 pr_info("%d NAND chips detected\n", i);
61b03bd7 3218
1da177e4 3219 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3220 chip->numchips = i;
3221 mtd->size = i * chip->chipsize;
7aa65bfd 3222
3b85c321
DW		 3223 return 0;
3224}
7351d3a5 3225EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3226
3227
3228/**
3229 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3230 * @mtd: MTD device structure
3b85c321 3231 *
8b6e50c9
BN		 3232 * This is the second phase of the normal nand_scan() function. It fills out
3233 * all the uninitialized function pointers with the defaults and scans for a
3234 * bad block table if appropriate.
3b85c321
DW		 3235 */
3236int nand_scan_tail(struct mtd_info *mtd)
3237{
3238 int i;
3239 struct nand_chip *chip = mtd->priv;
3240
4bf63fcb
DW		 3241 if (!(chip->options & NAND_OWN_BUFFERS))
3242 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3243 if (!chip->buffers)
3244 return -ENOMEM;
3245
7dcdcbef 3246 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3247 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3248
7aa65bfd 3249 /*
8b6e50c9 3250 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3251 */
193bd400 3252 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3253 switch (mtd->oobsize) {
1da177e4 3254 case 8:
5bd34c09 3255 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3256 break;
3257 case 16:
5bd34c09 3258 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3259 break;
3260 case 64:
5bd34c09 3261 chip->ecc.layout = &nand_oob_64;
1da177e4 3262 break;
81ec5364
TG		 3263 case 128:
3264 chip->ecc.layout = &nand_oob_128;
3265 break;
1da177e4 3266 default:
d0370219
BN		 3267 pr_warn("No oob scheme defined for oobsize %d\n",
3268 mtd->oobsize);
1da177e4
LT		 3269 BUG();
3270 }
3271 }
61b03bd7 3272
956e944c
DW		 3273 if (!chip->write_page)
3274 chip->write_page = nand_write_page;
3275
61b03bd7 3276 /*
8b6e50c9 3277 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3278 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3279 */
956e944c 3280
ace4dfee 3281 switch (chip->ecc.mode) {
6e0cb135
SN		 3282 case NAND_ECC_HW_OOB_FIRST:
3283 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3284 if (!chip->ecc.calculate || !chip->ecc.correct ||
3285 !chip->ecc.hwctl) {
9a4d4d69 3286 pr_warn("No ECC functions supplied; "
d0370219 3287 "hardware ECC not possible\n");
6e0cb135
SN		 3288 BUG();
3289 }
3290 if (!chip->ecc.read_page)
3291 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3292
6dfc6d25 3293 case NAND_ECC_HW:
8b6e50c9 3294 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3295 if (!chip->ecc.read_page)
3296 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3297 if (!chip->ecc.write_page)
3298 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3299 if (!chip->ecc.read_page_raw)
3300 chip->ecc.read_page_raw = nand_read_page_raw;
3301 if (!chip->ecc.write_page_raw)
3302 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3303 if (!chip->ecc.read_oob)
3304 chip->ecc.read_oob = nand_read_oob_std;
3305 if (!chip->ecc.write_oob)
3306 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3307
6dfc6d25 3308 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3309 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3310 !chip->ecc.hwctl) &&
3311 (!chip->ecc.read_page ||
1c45f604 3312 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3313 !chip->ecc.write_page ||
1c45f604 3314 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 3315 pr_warn("No ECC functions supplied; "
d0370219 3316 "hardware ECC not possible\n");
6dfc6d25
TG		 3317 BUG();
3318 }
8b6e50c9 3319 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3320 if (!chip->ecc.read_page)
3321 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3322 if (!chip->ecc.write_page)
3323 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3324 if (!chip->ecc.read_page_raw)
3325 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3326 if (!chip->ecc.write_page_raw)
3327 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3328 if (!chip->ecc.read_oob)
3329 chip->ecc.read_oob = nand_read_oob_syndrome;
3330 if (!chip->ecc.write_oob)
3331 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3332
ace4dfee 3333 if (mtd->writesize >= chip->ecc.size)
6dfc6d25 3334 break;
9a4d4d69 3335 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 3336 "%d byte page size, fallback to SW ECC\n",
3337 chip->ecc.size, mtd->writesize);
ace4dfee 3338 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3339
6dfc6d25 3340 case NAND_ECC_SOFT:
ace4dfee
TG		 3341 chip->ecc.calculate = nand_calculate_ecc;
3342 chip->ecc.correct = nand_correct_data;
f5bbdacc 3343 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3344 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3345 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3346 chip->ecc.read_page_raw = nand_read_page_raw;
3347 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3348 chip->ecc.read_oob = nand_read_oob_std;
3349 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3350 if (!chip->ecc.size)
3351 chip->ecc.size = 256;
ace4dfee 3352 chip->ecc.bytes = 3;
1da177e4 3353 break;
61b03bd7 3354
193bd400
ID		 3355 case NAND_ECC_SOFT_BCH:
3356 if (!mtd_nand_has_bch()) {
9a4d4d69 3357 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3358 BUG();
3359 }
3360 chip->ecc.calculate = nand_bch_calculate_ecc;
3361 chip->ecc.correct = nand_bch_correct_data;
3362 chip->ecc.read_page = nand_read_page_swecc;
3363 chip->ecc.read_subpage = nand_read_subpage;
3364 chip->ecc.write_page = nand_write_page_swecc;
3365 chip->ecc.read_page_raw = nand_read_page_raw;
3366 chip->ecc.write_page_raw = nand_write_page_raw;
3367 chip->ecc.read_oob = nand_read_oob_std;
3368 chip->ecc.write_oob = nand_write_oob_std;
3369 /*
3370 * Board driver should supply ecc.size and ecc.bytes values to
3371 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3372 * for details. Otherwise, default to 4 bits for large page
3373 * devices.
193bd400
ID		 3374 */
3375 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3376 chip->ecc.size = 512;
3377 chip->ecc.bytes = 7;
3378 }
3379 chip->ecc.priv = nand_bch_init(mtd,
3380 chip->ecc.size,
3381 chip->ecc.bytes,
3382 &chip->ecc.layout);
3383 if (!chip->ecc.priv) {
9a4d4d69 3384 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3385 BUG();
3386 }
3387 break;
3388
61b03bd7 3389 case NAND_ECC_NONE:
9a4d4d69 3390 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3391 "This is not recommended!\n");
8593fbc6
TG		 3392 chip->ecc.read_page = nand_read_page_raw;
3393 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3394 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3395 chip->ecc.read_page_raw = nand_read_page_raw;
3396 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3397 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3398 chip->ecc.size = mtd->writesize;
3399 chip->ecc.bytes = 0;
1da177e4 3400 break;
956e944c 3401
1da177e4 3402 default:
d0370219 3403 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 3404 BUG();
1da177e4 3405 }
61b03bd7 3406
9ce244b3 3407 /* For many systems, the standard OOB write also works for raw */
c46f6483
BN		 3408 if (!chip->ecc.read_oob_raw)
3409 chip->ecc.read_oob_raw = chip->ecc.read_oob;
9ce244b3
BN		 3410 if (!chip->ecc.write_oob_raw)
3411 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3412
5bd34c09
TG		 3413 /*
3414 * The number of bytes available for a client to place data into
8b6e50c9 3415 * the out of band area.
5bd34c09
TG		 3416 */
3417 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3418 for (i = 0; chip->ecc.layout->oobfree[i].length
3419 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3420 chip->ecc.layout->oobavail +=
3421 chip->ecc.layout->oobfree[i].length;
1f92267c 3422 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3423
7aa65bfd
TG		 3424 /*
3425 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3426 * mode.
7aa65bfd 3427 */
ace4dfee 3428 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3429 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 3430 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3431 BUG();
1da177e4 3432 }
f5bbdacc 3433 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3434
8b6e50c9 3435 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 3436 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3437 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3438 switch (chip->ecc.steps) {
29072b96
TG		 3439 case 2:
3440 mtd->subpage_sft = 1;
3441 break;
3442 case 4:
3443 case 8:
81ec5364 3444 case 16:
29072b96
TG		 3445 mtd->subpage_sft = 2;
3446 break;
3447 }
3448 }
3449 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3450
04bbd0ea 3451 /* Initialize state */
ace4dfee 3452 chip->state = FL_READY;
1da177e4
LT		 3453
3454 /* De-select the device */
ace4dfee 3455 chip->select_chip(mtd, -1);
1da177e4
LT		 3456
3457 /* Invalidate the pagebuffer reference */
ace4dfee 3458 chip->pagebuf = -1;
1da177e4
LT		 3459
3460 /* Fill in remaining MTD driver data */
3461 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3462 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3463 MTD_CAP_NANDFLASH;
1da177e4
LT		 3464 mtd->erase = nand_erase;
3465 mtd->point = NULL;
3466 mtd->unpoint = NULL;
3467 mtd->read = nand_read;
3468 mtd->write = nand_write;
2af7c653 3469 mtd->panic_write = panic_nand_write;
1da177e4
LT		 3470 mtd->read_oob = nand_read_oob;
3471 mtd->write_oob = nand_write_oob;
1da177e4
LT		 3472 mtd->sync = nand_sync;
3473 mtd->lock = NULL;
3474 mtd->unlock = NULL;
962034f4
VW		 3475 mtd->suspend = nand_suspend;
3476 mtd->resume = nand_resume;
1da177e4
LT		 3477 mtd->block_isbad = nand_block_isbad;
3478 mtd->block_markbad = nand_block_markbad;
cbcab65a 3479 mtd->writebufsize = mtd->writesize;
1da177e4 3480
5bd34c09
TG		 3481 /* propagate ecc.layout to mtd_info */
3482 mtd->ecclayout = chip->ecc.layout;
1da177e4 3483
0040bf38 3484 /* Check, if we should skip the bad block table scan */
ace4dfee 3485 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3486 return 0;
1da177e4
LT		 3487
3488 /* Build bad block table */
ace4dfee 3489 return chip->scan_bbt(mtd);
1da177e4 3490}
7351d3a5 3491EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3492
8b6e50c9
BN		 3493/*
3494 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3495 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3496 * to call us from in-kernel code if the core NAND support is modular.
3497 */
3b85c321
DW		 3498#ifdef MODULE
3499#define caller_is_module() (1)
3500#else
3501#define caller_is_module() \
a6e6abd5 3502 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3503#endif
3504
3505/**
3506 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3507 * @mtd: MTD device structure
3508 * @maxchips: number of chips to scan for
3b85c321 3509 *
8b6e50c9
BN		 3510 * This fills out all the uninitialized function pointers with the defaults.
3511 * The flash ID is read and the mtd/chip structures are filled with the
3512 * appropriate values. The mtd->owner field must be set to the module of the
3513 * caller.
3b85c321
DW		 3514 */
3515int nand_scan(struct mtd_info *mtd, int maxchips)
3516{
3517 int ret;
3518
3519 /* Many callers got this wrong, so check for it for a while... */
3520 if (!mtd->owner && caller_is_module()) {
d0370219 3521 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3522 BUG();
3523 }
3524
5e81e88a 3525 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3526 if (!ret)
3527 ret = nand_scan_tail(mtd);
3528 return ret;
3529}
7351d3a5 3530EXPORT_SYMBOL(nand_scan);
3b85c321 3531
1da177e4 3532/**
61b03bd7 3533 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3534 * @mtd: MTD device structure
3535 */
e0c7d767 3536void nand_release(struct mtd_info *mtd)
1da177e4 3537{
ace4dfee 3538 struct nand_chip *chip = mtd->priv;
1da177e4 3539
193bd400
ID		 3540 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3541 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3542
5ffcaf3d 3543 mtd_device_unregister(mtd);
1da177e4 3544
fa671646 3545 /* Free bad block table memory */
ace4dfee 3546 kfree(chip->bbt);
4bf63fcb
DW		 3547 if (!(chip->options & NAND_OWN_BUFFERS))
3548 kfree(chip->buffers);
58373ff0
BN		 3549
3550 /* Free bad block descriptor memory */
3551 if (chip->badblock_pattern && chip->badblock_pattern->options
3552 & NAND_BBT_DYNAMICSTRUCT)
3553 kfree(chip->badblock_pattern);
1da177e4 3554}
e0c7d767 3555EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3556
3557static int __init nand_base_init(void)
3558{
3559 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3560 return 0;
3561}
3562
3563static void __exit nand_base_exit(void)
3564{
3565 led_trigger_unregister_simple(nand_led_trigger);
3566}
3567
3568module_init(nand_base_init);
3569module_exit(nand_base_exit);
3570
e0c7d767 3571MODULE_LICENSE("GPL");
7351d3a5
FF		 3572MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3573MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3574MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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