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mtd: nand: pxa3xx: Add "armada370-nand" compatible
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
61b03bd7 7 *
1da177e4 8 * Additional technical information is available on
8b2b403c 9 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 10 *
1da177e4 11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 13 *
ace4dfee 14 * Credits:
61b03bd7
TG		 15 * David Woodhouse for adding multichip support
16 *
1da177e4
LT		 17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
19 *
ace4dfee 20 * TODO:
1da177e4
LT		 21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 23 * if we have HW ECC support.
c0b8ba7b 24 * BBT table is not serialized, has to be fixed
1da177e4 25 *
1da177e4
LT		 26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
29 *
30 */
31
20171642
EG		 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
552d9205 34#include <linux/module.h>
1da177e4
LT		 35#include <linux/delay.h>
36#include <linux/errno.h>
7aa65bfd 37#include <linux/err.h>
1da177e4
LT		 38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/types.h>
41#include <linux/mtd/mtd.h>
42#include <linux/mtd/nand.h>
43#include <linux/mtd/nand_ecc.h>
193bd400 44#include <linux/mtd/nand_bch.h>
1da177e4
LT		 45#include <linux/interrupt.h>
46#include <linux/bitops.h>
8fe833c1 47#include <linux/leds.h>
7351d3a5 48#include <linux/io.h>
1da177e4 49#include <linux/mtd/partitions.h>
1da177e4
LT		 50
51/* Define default oob placement schemes for large and small page devices */
5bd34c09 52static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 53 .eccbytes = 3,
54 .eccpos = {0, 1, 2},
5bd34c09
TG		 55 .oobfree = {
56 {.offset = 3,
57 .length = 2},
58 {.offset = 6,
f8ac0414 59 .length = 2} }
1da177e4
LT		 60};
61
5bd34c09 62static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 63 .eccbytes = 6,
64 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 65 .oobfree = {
66 {.offset = 8,
f8ac0414 67 . length = 8} }
1da177e4
LT		 68};
69
5bd34c09 70static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 71 .eccbytes = 24,
72 .eccpos = {
e0c7d767
DW		 73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 76 .oobfree = {
77 {.offset = 2,
f8ac0414 78 .length = 38} }
1da177e4
LT		 79};
80
81ec5364
TG		 81static struct nand_ecclayout nand_oob_128 = {
82 .eccbytes = 48,
83 .eccpos = {
84 80, 81, 82, 83, 84, 85, 86, 87,
85 88, 89, 90, 91, 92, 93, 94, 95,
86 96, 97, 98, 99, 100, 101, 102, 103,
87 104, 105, 106, 107, 108, 109, 110, 111,
88 112, 113, 114, 115, 116, 117, 118, 119,
89 120, 121, 122, 123, 124, 125, 126, 127},
90 .oobfree = {
91 {.offset = 2,
f8ac0414 92 .length = 78} }
81ec5364
TG		 93};
94
6a8214aa 95static int nand_get_device(struct mtd_info *mtd, int new_state);
1da177e4 96
8593fbc6
TG		 97static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
98 struct mtd_oob_ops *ops);
99
d470a97c 100/*
8e87d782 101 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 102 * compiled away when LED support is disabled.
103 */
104DEFINE_LED_TRIGGER(nand_led_trigger);
105
6fe5a6ac
VS		 106static int check_offs_len(struct mtd_info *mtd,
107 loff_t ofs, uint64_t len)
108{
109 struct nand_chip *chip = mtd->priv;
110 int ret = 0;
111
112 /* Start address must align on block boundary */
daae74ca 113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 114 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 115 ret = -EINVAL;
116 }
117
118 /* Length must align on block boundary */
daae74ca 119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 120 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 121 ret = -EINVAL;
122 }
123
6fe5a6ac
VS		 124 return ret;
125}
126
1da177e4
LT		 127/**
128 * nand_release_device - [GENERIC] release chip
8b6e50c9 129 * @mtd: MTD device structure
61b03bd7 130 *
b0bb6903 131 * Release chip lock and wake up anyone waiting on the device.
1da177e4 132 */
e0c7d767 133static void nand_release_device(struct mtd_info *mtd)
1da177e4 134{
ace4dfee 135 struct nand_chip *chip = mtd->priv;
1da177e4 136
a36ed299 137 /* Release the controller and the chip */
ace4dfee
TG		 138 spin_lock(&chip->controller->lock);
139 chip->controller->active = NULL;
140 chip->state = FL_READY;
141 wake_up(&chip->controller->wq);
142 spin_unlock(&chip->controller->lock);
1da177e4
LT		 143}
144
145/**
146 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 147 * @mtd: MTD device structure
1da177e4 148 *
7854d3f7 149 * Default read function for 8bit buswidth
1da177e4 150 */
58dd8f2b 151static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 152{
ace4dfee
TG		 153 struct nand_chip *chip = mtd->priv;
154 return readb(chip->IO_ADDR_R);
1da177e4
LT		 155}
156
1da177e4 157/**
064a7694 158 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
7854d3f7 159 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 160 * @mtd: MTD device structure
1da177e4 161 *
7854d3f7
BN		 162 * Default read function for 16bit buswidth with endianness conversion.
163 *
1da177e4 164 */
58dd8f2b 165static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 166{
ace4dfee
TG		 167 struct nand_chip *chip = mtd->priv;
168 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 169}
170
1da177e4
LT		 171/**
172 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 173 * @mtd: MTD device structure
1da177e4 174 *
7854d3f7 175 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 176 */
177static u16 nand_read_word(struct mtd_info *mtd)
178{
ace4dfee
TG		 179 struct nand_chip *chip = mtd->priv;
180 return readw(chip->IO_ADDR_R);
1da177e4
LT		 181}
182
1da177e4
LT		 183/**
184 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 185 * @mtd: MTD device structure
186 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 187 *
188 * Default select function for 1 chip devices.
189 */
ace4dfee 190static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 191{
ace4dfee
TG		 192 struct nand_chip *chip = mtd->priv;
193
194 switch (chipnr) {
1da177e4 195 case -1:
ace4dfee 196 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 197 break;
198 case 0:
1da177e4
LT		 199 break;
200
201 default:
202 BUG();
203 }
204}
205
206/**
207 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 208 * @mtd: MTD device structure
209 * @buf: data buffer
210 * @len: number of bytes to write
1da177e4 211 *
7854d3f7 212 * Default write function for 8bit buswidth.
1da177e4 213 */
58dd8f2b 214static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 215{
ace4dfee 216 struct nand_chip *chip = mtd->priv;
1da177e4 217
76413839 218 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 219}
220
221/**
61b03bd7 222 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 223 * @mtd: MTD device structure
224 * @buf: buffer to store date
225 * @len: number of bytes to read
1da177e4 226 *
7854d3f7 227 * Default read function for 8bit buswidth.
1da177e4 228 */
58dd8f2b 229static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 230{
ace4dfee 231 struct nand_chip *chip = mtd->priv;
1da177e4 232
76413839 233 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 234}
235
1da177e4
LT		 236/**
237 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 238 * @mtd: MTD device structure
239 * @buf: data buffer
240 * @len: number of bytes to write
1da177e4 241 *
7854d3f7 242 * Default write function for 16bit buswidth.
1da177e4 243 */
58dd8f2b 244static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 245{
ace4dfee 246 struct nand_chip *chip = mtd->priv;
1da177e4 247 u16 *p = (u16 *) buf;
61b03bd7 248
76413839 249 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 250}
251
252/**
61b03bd7 253 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 254 * @mtd: MTD device structure
255 * @buf: buffer to store date
256 * @len: number of bytes to read
1da177e4 257 *
7854d3f7 258 * Default read function for 16bit buswidth.
1da177e4 259 */
58dd8f2b 260static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 261{
ace4dfee 262 struct nand_chip *chip = mtd->priv;
1da177e4 263 u16 *p = (u16 *) buf;
1da177e4 264
76413839 265 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 266}
267
1da177e4
LT		 268/**
269 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 270 * @mtd: MTD device structure
271 * @ofs: offset from device start
272 * @getchip: 0, if the chip is already selected
1da177e4 273 *
61b03bd7 274 * Check, if the block is bad.
1da177e4
LT		 275 */
276static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
277{
cdbec050 278 int page, chipnr, res = 0, i = 0;
ace4dfee 279 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 280 u16 bad;
281
5fb1549d 282 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 283 ofs += mtd->erasesize - mtd->writesize;
284
1a12f46a
TK		 285 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
286
1da177e4 287 if (getchip) {
ace4dfee 288 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 289
6a8214aa 290 nand_get_device(mtd, FL_READING);
1da177e4
LT		 291
292 /* Select the NAND device */
ace4dfee 293 chip->select_chip(mtd, chipnr);
1a12f46a 294 }
1da177e4 295
cdbec050
BN		 296 do {
297 if (chip->options & NAND_BUSWIDTH_16) {
298 chip->cmdfunc(mtd, NAND_CMD_READOOB,
299 chip->badblockpos & 0xFE, page);
300 bad = cpu_to_le16(chip->read_word(mtd));
301 if (chip->badblockpos & 0x1)
302 bad >>= 8;
303 else
304 bad &= 0xFF;
305 } else {
306 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
307 page);
308 bad = chip->read_byte(mtd);
309 }
310
311 if (likely(chip->badblockbits == 8))
312 res = bad != 0xFF;
e0b58d0a 313 else
cdbec050
BN		 314 res = hweight8(bad) < chip->badblockbits;
315 ofs += mtd->writesize;
316 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
317 i++;
318 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 319
b0bb6903
HS		 320 if (getchip) {
321 chip->select_chip(mtd, -1);
1da177e4 322 nand_release_device(mtd);
b0bb6903 323 }
61b03bd7 324
1da177e4
LT		 325 return res;
326}
327
328/**
5a0edb25 329 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
8b6e50c9
BN		 330 * @mtd: MTD device structure
331 * @ofs: offset from device start
1da177e4 332 *
8b6e50c9 333 * This is the default implementation, which can be overridden by a hardware
5a0edb25
BN		 334 * specific driver. It provides the details for writing a bad block marker to a
335 * block.
336 */
337static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
338{
339 struct nand_chip *chip = mtd->priv;
340 struct mtd_oob_ops ops;
341 uint8_t buf[2] = { 0, 0 };
342 int ret = 0, res, i = 0;
343
344 ops.datbuf = NULL;
345 ops.oobbuf = buf;
346 ops.ooboffs = chip->badblockpos;
347 if (chip->options & NAND_BUSWIDTH_16) {
348 ops.ooboffs &= ~0x01;
349 ops.len = ops.ooblen = 2;
350 } else {
351 ops.len = ops.ooblen = 1;
352 }
353 ops.mode = MTD_OPS_PLACE_OOB;
354
355 /* Write to first/last page(s) if necessary */
356 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
357 ofs += mtd->erasesize - mtd->writesize;
358 do {
359 res = nand_do_write_oob(mtd, ofs, &ops);
360 if (!ret)
361 ret = res;
362
363 i++;
364 ofs += mtd->writesize;
365 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
366
367 return ret;
368}
369
370/**
371 * nand_block_markbad_lowlevel - mark a block bad
372 * @mtd: MTD device structure
373 * @ofs: offset from device start
374 *
375 * This function performs the generic NAND bad block marking steps (i.e., bad
376 * block table(s) and/or marker(s)). We only allow the hardware driver to
377 * specify how to write bad block markers to OOB (chip->block_markbad).
378 *
b32843b7 379 * We try operations in the following order:
e2414f4c 380 * (1) erase the affected block, to allow OOB marker to be written cleanly
b32843b7
BN		 381 * (2) write bad block marker to OOB area of affected block (unless flag
382 * NAND_BBT_NO_OOB_BBM is present)
383 * (3) update the BBT
384 * Note that we retain the first error encountered in (2) or (3), finish the
e2414f4c 385 * procedures, and dump the error in the end.
1da177e4 386*/
5a0edb25 387static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
1da177e4 388{
ace4dfee 389 struct nand_chip *chip = mtd->priv;
b32843b7 390 int res, ret = 0;
61b03bd7 391
b32843b7 392 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
00918429
BN		 393 struct erase_info einfo;
394
395 /* Attempt erase before marking OOB */
396 memset(&einfo, 0, sizeof(einfo));
397 einfo.mtd = mtd;
398 einfo.addr = ofs;
daae74ca 399 einfo.len = 1ULL << chip->phys_erase_shift;
00918429 400 nand_erase_nand(mtd, &einfo, 0);
1da177e4 401
b32843b7 402 /* Write bad block marker to OOB */
6a8214aa 403 nand_get_device(mtd, FL_WRITING);
5a0edb25 404 ret = chip->block_markbad(mtd, ofs);
c0b8ba7b 405 nand_release_device(mtd);
f1a28c02 406 }
e2414f4c 407
b32843b7
BN		 408 /* Mark block bad in BBT */
409 if (chip->bbt) {
410 res = nand_markbad_bbt(mtd, ofs);
e2414f4c
BN		 411 if (!ret)
412 ret = res;
413 }
414
f1a28c02
TG		 415 if (!ret)
416 mtd->ecc_stats.badblocks++;
c0b8ba7b 417
f1a28c02 418 return ret;
1da177e4
LT		 419}
420
61b03bd7 421/**
1da177e4 422 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 423 * @mtd: MTD device structure
1da177e4 424 *
8b6e50c9
BN		 425 * Check, if the device is write protected. The function expects, that the
426 * device is already selected.
1da177e4 427 */
e0c7d767 428static int nand_check_wp(struct mtd_info *mtd)
1da177e4 429{
ace4dfee 430 struct nand_chip *chip = mtd->priv;
93edbad6 431
8b6e50c9 432 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 433 if (chip->options & NAND_BROKEN_XD)
434 return 0;
435
1da177e4 436 /* Check the WP bit */
ace4dfee
TG		 437 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
438 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 439}
440
441/**
442 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 443 * @mtd: MTD device structure
444 * @ofs: offset from device start
445 * @getchip: 0, if the chip is already selected
446 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 447 *
448 * Check, if the block is bad. Either by reading the bad block table or
449 * calling of the scan function.
450 */
2c0a2bed
TG		 451static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
452 int allowbbt)
1da177e4 453{
ace4dfee 454 struct nand_chip *chip = mtd->priv;
61b03bd7 455
ace4dfee
TG		 456 if (!chip->bbt)
457 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 458
1da177e4 459 /* Return info from the table */
e0c7d767 460 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 461}
462
2af7c653
SK		 463/**
464 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 465 * @mtd: MTD device structure
466 * @timeo: Timeout
2af7c653
SK		 467 *
468 * Helper function for nand_wait_ready used when needing to wait in interrupt
469 * context.
470 */
471static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
472{
473 struct nand_chip *chip = mtd->priv;
474 int i;
475
476 /* Wait for the device to get ready */
477 for (i = 0; i < timeo; i++) {
478 if (chip->dev_ready(mtd))
479 break;
480 touch_softlockup_watchdog();
481 mdelay(1);
482 }
483}
484
7854d3f7 485/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 486void nand_wait_ready(struct mtd_info *mtd)
3b88775c 487{
ace4dfee 488 struct nand_chip *chip = mtd->priv;
ca6a2489 489 unsigned long timeo = jiffies + msecs_to_jiffies(20);
3b88775c 490
2af7c653
SK		 491 /* 400ms timeout */
492 if (in_interrupt() || oops_in_progress)
493 return panic_nand_wait_ready(mtd, 400);
494
8fe833c1 495 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 496 /* Wait until command is processed or timeout occurs */
3b88775c 497 do {
ace4dfee 498 if (chip->dev_ready(mtd))
8fe833c1 499 break;
8446f1d3 500 touch_softlockup_watchdog();
61b03bd7 501 } while (time_before(jiffies, timeo));
8fe833c1 502 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 503}
4b648b02 504EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 505
1da177e4
LT		 506/**
507 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 508 * @mtd: MTD device structure
509 * @command: the command to be sent
510 * @column: the column address for this command, -1 if none
511 * @page_addr: the page address for this command, -1 if none
1da177e4 512 *
8b6e50c9 513 * Send command to NAND device. This function is used for small page devices
51148f1f 514 * (512 Bytes per page).
1da177e4 515 */
7abd3ef9
TG		 516static void nand_command(struct mtd_info *mtd, unsigned int command,
517 int column, int page_addr)
1da177e4 518{
ace4dfee 519 register struct nand_chip *chip = mtd->priv;
7abd3ef9 520 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 521
8b6e50c9 522 /* Write out the command to the device */
1da177e4
LT		 523 if (command == NAND_CMD_SEQIN) {
524 int readcmd;
525
28318776 526 if (column >= mtd->writesize) {
1da177e4 527 /* OOB area */
28318776 528 column -= mtd->writesize;
1da177e4
LT		 529 readcmd = NAND_CMD_READOOB;
530 } else if (column < 256) {
531 /* First 256 bytes --> READ0 */
532 readcmd = NAND_CMD_READ0;
533 } else {
534 column -= 256;
535 readcmd = NAND_CMD_READ1;
536 }
ace4dfee 537 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 538 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 539 }
ace4dfee 540 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 541
8b6e50c9 542 /* Address cycle, when necessary */
7abd3ef9
TG		 543 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
544 /* Serially input address */
545 if (column != -1) {
546 /* Adjust columns for 16 bit buswidth */
ace4dfee 547 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 548 column >>= 1;
ace4dfee 549 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 550 ctrl &= ~NAND_CTRL_CHANGE;
551 }
552 if (page_addr != -1) {
ace4dfee 553 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 554 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 555 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 556 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 557 if (chip->chipsize > (32 << 20))
558 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 559 }
ace4dfee 560 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 561
562 /*
8b6e50c9
BN		 563 * Program and erase have their own busy handlers status and sequential
564 * in needs no delay
e0c7d767 565 */
1da177e4 566 switch (command) {
61b03bd7 567
1da177e4
LT		 568 case NAND_CMD_PAGEPROG:
569 case NAND_CMD_ERASE1:
570 case NAND_CMD_ERASE2:
571 case NAND_CMD_SEQIN:
572 case NAND_CMD_STATUS:
573 return;
574
575 case NAND_CMD_RESET:
ace4dfee 576 if (chip->dev_ready)
1da177e4 577 break;
ace4dfee
TG		 578 udelay(chip->chip_delay);
579 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 580 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 581 chip->cmd_ctrl(mtd,
582 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 583 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
584 ;
1da177e4
LT		 585 return;
586
e0c7d767 587 /* This applies to read commands */
1da177e4 588 default:
61b03bd7 589 /*
1da177e4
LT		 590 * If we don't have access to the busy pin, we apply the given
591 * command delay
e0c7d767 592 */
ace4dfee
TG		 593 if (!chip->dev_ready) {
594 udelay(chip->chip_delay);
1da177e4 595 return;
61b03bd7 596 }
1da177e4 597 }
8b6e50c9
BN		 598 /*
599 * Apply this short delay always to ensure that we do wait tWB in
600 * any case on any machine.
601 */
e0c7d767 602 ndelay(100);
3b88775c
TG		 603
604 nand_wait_ready(mtd);
1da177e4
LT		 605}
606
607/**
608 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 609 * @mtd: MTD device structure
610 * @command: the command to be sent
611 * @column: the column address for this command, -1 if none
612 * @page_addr: the page address for this command, -1 if none
1da177e4 613 *
7abd3ef9 614 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 615 * devices. We don't have the separate regions as we have in the small page
616 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 617 */
7abd3ef9
TG		 618static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
619 int column, int page_addr)
1da177e4 620{
ace4dfee 621 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 622
623 /* Emulate NAND_CMD_READOOB */
624 if (command == NAND_CMD_READOOB) {
28318776 625 column += mtd->writesize;
1da177e4
LT		 626 command = NAND_CMD_READ0;
627 }
61b03bd7 628
7abd3ef9 629 /* Command latch cycle */
fb066ada 630 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 631
632 if (column != -1 || page_addr != -1) {
7abd3ef9 633 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 634
635 /* Serially input address */
636 if (column != -1) {
637 /* Adjust columns for 16 bit buswidth */
ace4dfee 638 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 639 column >>= 1;
ace4dfee 640 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 641 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 642 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 643 }
1da177e4 644 if (page_addr != -1) {
ace4dfee
TG		 645 chip->cmd_ctrl(mtd, page_addr, ctrl);
646 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 647 NAND_NCE | NAND_ALE);
1da177e4 648 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 649 if (chip->chipsize > (128 << 20))
650 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 651 NAND_NCE | NAND_ALE);
1da177e4 652 }
1da177e4 653 }
ace4dfee 654 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 655
656 /*
8b6e50c9
BN		 657 * Program and erase have their own busy handlers status, sequential
658 * in, and deplete1 need no delay.
30f464b7 659 */
1da177e4 660 switch (command) {
61b03bd7 661
1da177e4
LT		 662 case NAND_CMD_CACHEDPROG:
663 case NAND_CMD_PAGEPROG:
664 case NAND_CMD_ERASE1:
665 case NAND_CMD_ERASE2:
666 case NAND_CMD_SEQIN:
7bc3312b 667 case NAND_CMD_RNDIN:
1da177e4 668 case NAND_CMD_STATUS:
30f464b7 669 return;
1da177e4
LT		 670
671 case NAND_CMD_RESET:
ace4dfee 672 if (chip->dev_ready)
1da177e4 673 break;
ace4dfee 674 udelay(chip->chip_delay);
12efdde3
TG		 675 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
676 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
677 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
678 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 679 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
680 ;
1da177e4
LT		 681 return;
682
7bc3312b
TG		 683 case NAND_CMD_RNDOUT:
684 /* No ready / busy check necessary */
685 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
686 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
687 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
688 NAND_NCE | NAND_CTRL_CHANGE);
689 return;
690
1da177e4 691 case NAND_CMD_READ0:
12efdde3
TG		 692 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
693 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
694 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
695 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 696
e0c7d767 697 /* This applies to read commands */
1da177e4 698 default:
61b03bd7 699 /*
1da177e4 700 * If we don't have access to the busy pin, we apply the given
8b6e50c9 701 * command delay.
e0c7d767 702 */
ace4dfee
TG		 703 if (!chip->dev_ready) {
704 udelay(chip->chip_delay);
1da177e4 705 return;
61b03bd7 706 }
1da177e4 707 }
3b88775c 708
8b6e50c9
BN		 709 /*
710 * Apply this short delay always to ensure that we do wait tWB in
711 * any case on any machine.
712 */
e0c7d767 713 ndelay(100);
3b88775c
TG		 714
715 nand_wait_ready(mtd);
1da177e4
LT		 716}
717
2af7c653
SK		 718/**
719 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 720 * @chip: the nand chip descriptor
721 * @mtd: MTD device structure
722 * @new_state: the state which is requested
2af7c653
SK		 723 *
724 * Used when in panic, no locks are taken.
725 */
726static void panic_nand_get_device(struct nand_chip *chip,
727 struct mtd_info *mtd, int new_state)
728{
7854d3f7 729 /* Hardware controller shared among independent devices */
2af7c653
SK		 730 chip->controller->active = chip;
731 chip->state = new_state;
732}
733
1da177e4
LT		 734/**
735 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 736 * @mtd: MTD device structure
737 * @new_state: the state which is requested
1da177e4
LT		 738 *
739 * Get the device and lock it for exclusive access
740 */
2c0a2bed 741static int
6a8214aa 742nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 743{
6a8214aa 744 struct nand_chip *chip = mtd->priv;
ace4dfee
TG		 745 spinlock_t *lock = &chip->controller->lock;
746 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 747 DECLARE_WAITQUEUE(wait, current);
7351d3a5 748retry:
0dfc6246
TG		 749 spin_lock(lock);
750
b8b3ee9a 751 /* Hardware controller shared among independent devices */
ace4dfee
TG		 752 if (!chip->controller->active)
753 chip->controller->active = chip;
a36ed299 754
ace4dfee
TG		 755 if (chip->controller->active == chip && chip->state == FL_READY) {
756 chip->state = new_state;
0dfc6246 757 spin_unlock(lock);
962034f4
VW		 758 return 0;
759 }
760 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 761 if (chip->controller->active->state == FL_PM_SUSPENDED) {
762 chip->state = FL_PM_SUSPENDED;
763 spin_unlock(lock);
764 return 0;
6b0d9a84 765 }
0dfc6246
TG		 766 }
767 set_current_state(TASK_UNINTERRUPTIBLE);
768 add_wait_queue(wq, &wait);
769 spin_unlock(lock);
770 schedule();
771 remove_wait_queue(wq, &wait);
1da177e4
LT		 772 goto retry;
773}
774
2af7c653 775/**
8b6e50c9
BN		 776 * panic_nand_wait - [GENERIC] wait until the command is done
777 * @mtd: MTD device structure
778 * @chip: NAND chip structure
779 * @timeo: timeout
2af7c653
SK		 780 *
781 * Wait for command done. This is a helper function for nand_wait used when
782 * we are in interrupt context. May happen when in panic and trying to write
b595076a 783 * an oops through mtdoops.
2af7c653
SK		 784 */
785static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
786 unsigned long timeo)
787{
788 int i;
789 for (i = 0; i < timeo; i++) {
790 if (chip->dev_ready) {
791 if (chip->dev_ready(mtd))
792 break;
793 } else {
794 if (chip->read_byte(mtd) & NAND_STATUS_READY)
795 break;
796 }
797 mdelay(1);
f8ac0414 798 }
2af7c653
SK		 799}
800
1da177e4 801/**
8b6e50c9
BN		 802 * nand_wait - [DEFAULT] wait until the command is done
803 * @mtd: MTD device structure
804 * @chip: NAND chip structure
1da177e4 805 *
8b6e50c9
BN		 806 * Wait for command done. This applies to erase and program only. Erase can
807 * take up to 400ms and program up to 20ms according to general NAND and
808 * SmartMedia specs.
844d3b42 809 */
7bc3312b 810static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 811{
812
7bc3312b 813 int status, state = chip->state;
6d2559f8 814 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1da177e4 815
8fe833c1
RP		 816 led_trigger_event(nand_led_trigger, LED_FULL);
817
8b6e50c9
BN		 818 /*
819 * Apply this short delay always to ensure that we do wait tWB in any
820 * case on any machine.
821 */
e0c7d767 822 ndelay(100);
1da177e4 823
14c65786 824 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 825
2af7c653
SK		 826 if (in_interrupt() || oops_in_progress)
827 panic_nand_wait(mtd, chip, timeo);
828 else {
6d2559f8 829 timeo = jiffies + msecs_to_jiffies(timeo);
2af7c653
SK		 830 while (time_before(jiffies, timeo)) {
831 if (chip->dev_ready) {
832 if (chip->dev_ready(mtd))
833 break;
834 } else {
835 if (chip->read_byte(mtd) & NAND_STATUS_READY)
836 break;
837 }
838 cond_resched();
1da177e4 839 }
1da177e4 840 }
8fe833c1
RP		 841 led_trigger_event(nand_led_trigger, LED_OFF);
842
ace4dfee 843 status = (int)chip->read_byte(mtd);
f251b8df
MC		 844 /* This can happen if in case of timeout or buggy dev_ready */
845 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 846 return status;
847}
848
7d70f334 849/**
b6d676db 850 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 851 * @mtd: mtd info
852 * @ofs: offset to start unlock from
853 * @len: length to unlock
8b6e50c9
BN		 854 * @invert: when = 0, unlock the range of blocks within the lower and
855 * upper boundary address
856 * when = 1, unlock the range of blocks outside the boundaries
857 * of the lower and upper boundary address
7d70f334 858 *
8b6e50c9 859 * Returs unlock status.
7d70f334
VS		 860 */
861static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
862 uint64_t len, int invert)
863{
864 int ret = 0;
865 int status, page;
866 struct nand_chip *chip = mtd->priv;
867
868 /* Submit address of first page to unlock */
869 page = ofs >> chip->page_shift;
870 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
871
872 /* Submit address of last page to unlock */
873 page = (ofs + len) >> chip->page_shift;
874 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
875 (page | invert) & chip->pagemask);
876
877 /* Call wait ready function */
878 status = chip->waitfunc(mtd, chip);
7d70f334 879 /* See if device thinks it succeeded */
74830966 880 if (status & NAND_STATUS_FAIL) {
289c0522 881 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 882 __func__, status);
883 ret = -EIO;
884 }
885
886 return ret;
887}
888
889/**
b6d676db 890 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 891 * @mtd: mtd info
892 * @ofs: offset to start unlock from
893 * @len: length to unlock
7d70f334 894 *
8b6e50c9 895 * Returns unlock status.
7d70f334
VS		 896 */
897int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
898{
899 int ret = 0;
900 int chipnr;
901 struct nand_chip *chip = mtd->priv;
902
289c0522 903 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 904 __func__, (unsigned long long)ofs, len);
905
906 if (check_offs_len(mtd, ofs, len))
907 ret = -EINVAL;
908
909 /* Align to last block address if size addresses end of the device */
910 if (ofs + len == mtd->size)
911 len -= mtd->erasesize;
912
6a8214aa 913 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 914
915 /* Shift to get chip number */
916 chipnr = ofs >> chip->chip_shift;
917
918 chip->select_chip(mtd, chipnr);
919
920 /* Check, if it is write protected */
921 if (nand_check_wp(mtd)) {
289c0522 922 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 923 __func__);
924 ret = -EIO;
925 goto out;
926 }
927
928 ret = __nand_unlock(mtd, ofs, len, 0);
929
930out:
b0bb6903 931 chip->select_chip(mtd, -1);
7d70f334
VS		 932 nand_release_device(mtd);
933
934 return ret;
935}
7351d3a5 936EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 937
938/**
b6d676db 939 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 940 * @mtd: mtd info
941 * @ofs: offset to start unlock from
942 * @len: length to unlock
7d70f334 943 *
8b6e50c9
BN		 944 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
945 * have this feature, but it allows only to lock all blocks, not for specified
946 * range for block. Implementing 'lock' feature by making use of 'unlock', for
947 * now.
7d70f334 948 *
8b6e50c9 949 * Returns lock status.
7d70f334
VS		 950 */
951int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
952{
953 int ret = 0;
954 int chipnr, status, page;
955 struct nand_chip *chip = mtd->priv;
956
289c0522 957 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 958 __func__, (unsigned long long)ofs, len);
959
960 if (check_offs_len(mtd, ofs, len))
961 ret = -EINVAL;
962
6a8214aa 963 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 964
965 /* Shift to get chip number */
966 chipnr = ofs >> chip->chip_shift;
967
968 chip->select_chip(mtd, chipnr);
969
970 /* Check, if it is write protected */
971 if (nand_check_wp(mtd)) {
289c0522 972 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 973 __func__);
974 status = MTD_ERASE_FAILED;
975 ret = -EIO;
976 goto out;
977 }
978
979 /* Submit address of first page to lock */
980 page = ofs >> chip->page_shift;
981 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
982
983 /* Call wait ready function */
984 status = chip->waitfunc(mtd, chip);
7d70f334 985 /* See if device thinks it succeeded */
74830966 986 if (status & NAND_STATUS_FAIL) {
289c0522 987 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 988 __func__, status);
989 ret = -EIO;
990 goto out;
991 }
992
993 ret = __nand_unlock(mtd, ofs, len, 0x1);
994
995out:
b0bb6903 996 chip->select_chip(mtd, -1);
7d70f334
VS		 997 nand_release_device(mtd);
998
999 return ret;
1000}
7351d3a5 1001EXPORT_SYMBOL(nand_lock);
7d70f334 1002
8593fbc6 1003/**
7854d3f7 1004 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1005 * @mtd: mtd info structure
1006 * @chip: nand chip info structure
1007 * @buf: buffer to store read data
1fbb938d 1008 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1009 * @page: page number to read
52ff49df 1010 *
7854d3f7 1011 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1012 */
1013static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1014 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1015{
1016 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1017 if (oob_required)
1018 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1019 return 0;
1020}
1021
52ff49df 1022/**
7854d3f7 1023 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1024 * @mtd: mtd info structure
1025 * @chip: nand chip info structure
1026 * @buf: buffer to store read data
1fbb938d 1027 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1028 * @page: page number to read
52ff49df
DB		 1029 *
1030 * We need a special oob layout and handling even when OOB isn't used.
1031 */
7351d3a5 1032static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1033 struct nand_chip *chip, uint8_t *buf,
1034 int oob_required, int page)
52ff49df
DB		 1035{
1036 int eccsize = chip->ecc.size;
1037 int eccbytes = chip->ecc.bytes;
1038 uint8_t *oob = chip->oob_poi;
1039 int steps, size;
1040
1041 for (steps = chip->ecc.steps; steps > 0; steps--) {
1042 chip->read_buf(mtd, buf, eccsize);
1043 buf += eccsize;
1044
1045 if (chip->ecc.prepad) {
1046 chip->read_buf(mtd, oob, chip->ecc.prepad);
1047 oob += chip->ecc.prepad;
1048 }
1049
1050 chip->read_buf(mtd, oob, eccbytes);
1051 oob += eccbytes;
1052
1053 if (chip->ecc.postpad) {
1054 chip->read_buf(mtd, oob, chip->ecc.postpad);
1055 oob += chip->ecc.postpad;
1056 }
1057 }
1058
1059 size = mtd->oobsize - (oob - chip->oob_poi);
1060 if (size)
1061 chip->read_buf(mtd, oob, size);
1062
1063 return 0;
1064}
1065
1da177e4 1066/**
7854d3f7 1067 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1068 * @mtd: mtd info structure
1069 * @chip: nand chip info structure
1070 * @buf: buffer to store read data
1fbb938d 1071 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1072 * @page: page number to read
068e3c0a 1073 */
f5bbdacc 1074static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1075 uint8_t *buf, int oob_required, int page)
1da177e4 1076{
f5bbdacc
TG		 1077 int i, eccsize = chip->ecc.size;
1078 int eccbytes = chip->ecc.bytes;
1079 int eccsteps = chip->ecc.steps;
1080 uint8_t *p = buf;
4bf63fcb
DW		 1081 uint8_t *ecc_calc = chip->buffers->ecccalc;
1082 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1083 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1084 unsigned int max_bitflips = 0;
f5bbdacc 1085
1fbb938d 1086 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1087
1088 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1089 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1090
1091 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1092 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1093
1094 eccsteps = chip->ecc.steps;
1095 p = buf;
1096
1097 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1098 int stat;
1099
1100 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1101 if (stat < 0) {
f5bbdacc 1102 mtd->ecc_stats.failed++;
3f91e94f 1103 } else {
f5bbdacc 1104 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1105 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1106 }
f5bbdacc 1107 }
3f91e94f 1108 return max_bitflips;
22c60f5f 1109}
1da177e4 1110
3d459559 1111/**
837a6ba4 1112 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1113 * @mtd: mtd info structure
1114 * @chip: nand chip info structure
1115 * @data_offs: offset of requested data within the page
1116 * @readlen: data length
1117 * @bufpoi: buffer to store read data
3d459559 1118 */
7351d3a5
FF		 1119static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1120 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1121{
1122 int start_step, end_step, num_steps;
1123 uint32_t *eccpos = chip->ecc.layout->eccpos;
1124 uint8_t *p;
1125 int data_col_addr, i, gaps = 0;
1126 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1127 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1128 int index = 0;
3f91e94f 1129 unsigned int max_bitflips = 0;
3d459559 1130
7854d3f7 1131 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1132 start_step = data_offs / chip->ecc.size;
1133 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1134 num_steps = end_step - start_step + 1;
1135
8b6e50c9 1136 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1137 datafrag_len = num_steps * chip->ecc.size;
1138 eccfrag_len = num_steps * chip->ecc.bytes;
1139
1140 data_col_addr = start_step * chip->ecc.size;
1141 /* If we read not a page aligned data */
1142 if (data_col_addr != 0)
1143 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1144
1145 p = bufpoi + data_col_addr;
1146 chip->read_buf(mtd, p, datafrag_len);
1147
8b6e50c9 1148 /* Calculate ECC */
3d459559
AK		 1149 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1150 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1151
8b6e50c9
BN		 1152 /*
1153 * The performance is faster if we position offsets according to
7854d3f7 1154 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1155 */
3d459559
AK		 1156 for (i = 0; i < eccfrag_len - 1; i++) {
1157 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1158 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1159 gaps = 1;
1160 break;
1161 }
1162 }
1163 if (gaps) {
1164 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1165 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1166 } else {
8b6e50c9 1167 /*
7854d3f7 1168 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1169 * about buswidth alignment in read_buf.
1170 */
7351d3a5
FF		 1171 index = start_step * chip->ecc.bytes;
1172
1173 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1174 aligned_len = eccfrag_len;
7351d3a5 1175 if (eccpos[index] & (busw - 1))
3d459559 1176 aligned_len++;
7351d3a5 1177 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1178 aligned_len++;
1179
7351d3a5
FF		 1180 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1181 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1182 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1183 }
1184
1185 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1186 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1187
1188 p = bufpoi + data_col_addr;
1189 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1190 int stat;
1191
7351d3a5
FF		 1192 stat = chip->ecc.correct(mtd, p,
1193 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1194 if (stat < 0) {
3d459559 1195 mtd->ecc_stats.failed++;
3f91e94f 1196 } else {
3d459559 1197 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1198 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1199 }
3d459559 1200 }
3f91e94f 1201 return max_bitflips;
3d459559
AK		 1202}
1203
068e3c0a 1204/**
7854d3f7 1205 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1206 * @mtd: mtd info structure
1207 * @chip: nand chip info structure
1208 * @buf: buffer to store read data
1fbb938d 1209 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1210 * @page: page number to read
068e3c0a 1211 *
7854d3f7 1212 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1213 */
f5bbdacc 1214static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1215 uint8_t *buf, int oob_required, int page)
1da177e4 1216{
f5bbdacc
TG		 1217 int i, eccsize = chip->ecc.size;
1218 int eccbytes = chip->ecc.bytes;
1219 int eccsteps = chip->ecc.steps;
1220 uint8_t *p = buf;
4bf63fcb
DW		 1221 uint8_t *ecc_calc = chip->buffers->ecccalc;
1222 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1223 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1224 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1225
1226 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1227 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1228 chip->read_buf(mtd, p, eccsize);
1229 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1230 }
f75e5097 1231 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1232
f5bbdacc 1233 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1234 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1235
f5bbdacc
TG		 1236 eccsteps = chip->ecc.steps;
1237 p = buf;
61b03bd7 1238
f5bbdacc
TG		 1239 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1240 int stat;
1da177e4 1241
f5bbdacc 1242 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1243 if (stat < 0) {
f5bbdacc 1244 mtd->ecc_stats.failed++;
3f91e94f 1245 } else {
f5bbdacc 1246 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1247 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1248 }
f5bbdacc 1249 }
3f91e94f 1250 return max_bitflips;
f5bbdacc 1251}
1da177e4 1252
6e0cb135 1253/**
7854d3f7 1254 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1255 * @mtd: mtd info structure
1256 * @chip: nand chip info structure
1257 * @buf: buffer to store read data
1fbb938d 1258 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1259 * @page: page number to read
6e0cb135 1260 *
8b6e50c9
BN		 1261 * Hardware ECC for large page chips, require OOB to be read first. For this
1262 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1263 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1264 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1265 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1266 */
1267static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1268 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1269{
1270 int i, eccsize = chip->ecc.size;
1271 int eccbytes = chip->ecc.bytes;
1272 int eccsteps = chip->ecc.steps;
1273 uint8_t *p = buf;
1274 uint8_t *ecc_code = chip->buffers->ecccode;
1275 uint32_t *eccpos = chip->ecc.layout->eccpos;
1276 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1277 unsigned int max_bitflips = 0;
6e0cb135
SN		 1278
1279 /* Read the OOB area first */
1280 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1281 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1282 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1283
1284 for (i = 0; i < chip->ecc.total; i++)
1285 ecc_code[i] = chip->oob_poi[eccpos[i]];
1286
1287 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1288 int stat;
1289
1290 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1291 chip->read_buf(mtd, p, eccsize);
1292 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1293
1294 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1295 if (stat < 0) {
6e0cb135 1296 mtd->ecc_stats.failed++;
3f91e94f 1297 } else {
6e0cb135 1298 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1299 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1300 }
6e0cb135 1301 }
3f91e94f 1302 return max_bitflips;
6e0cb135
SN		 1303}
1304
f5bbdacc 1305/**
7854d3f7 1306 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1307 * @mtd: mtd info structure
1308 * @chip: nand chip info structure
1309 * @buf: buffer to store read data
1fbb938d 1310 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1311 * @page: page number to read
f5bbdacc 1312 *
8b6e50c9
BN		 1313 * The hw generator calculates the error syndrome automatically. Therefore we
1314 * need a special oob layout and handling.
f5bbdacc
TG		 1315 */
1316static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1317 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1318{
1319 int i, eccsize = chip->ecc.size;
1320 int eccbytes = chip->ecc.bytes;
1321 int eccsteps = chip->ecc.steps;
1322 uint8_t *p = buf;
f75e5097 1323 uint8_t *oob = chip->oob_poi;
3f91e94f 1324 unsigned int max_bitflips = 0;
1da177e4 1325
f5bbdacc
TG		 1326 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1327 int stat;
61b03bd7 1328
f5bbdacc
TG		 1329 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1330 chip->read_buf(mtd, p, eccsize);
1da177e4 1331
f5bbdacc
TG		 1332 if (chip->ecc.prepad) {
1333 chip->read_buf(mtd, oob, chip->ecc.prepad);
1334 oob += chip->ecc.prepad;
1335 }
1da177e4 1336
f5bbdacc
TG		 1337 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1338 chip->read_buf(mtd, oob, eccbytes);
1339 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1340
3f91e94f 1341 if (stat < 0) {
f5bbdacc 1342 mtd->ecc_stats.failed++;
3f91e94f 1343 } else {
f5bbdacc 1344 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1345 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1346 }
61b03bd7 1347
f5bbdacc 1348 oob += eccbytes;
1da177e4 1349
f5bbdacc
TG		 1350 if (chip->ecc.postpad) {
1351 chip->read_buf(mtd, oob, chip->ecc.postpad);
1352 oob += chip->ecc.postpad;
61b03bd7 1353 }
f5bbdacc 1354 }
1da177e4 1355
f5bbdacc 1356 /* Calculate remaining oob bytes */
7e4178f9 1357 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1358 if (i)
1359 chip->read_buf(mtd, oob, i);
61b03bd7 1360
3f91e94f 1361 return max_bitflips;
f5bbdacc 1362}
1da177e4 1363
f5bbdacc 1364/**
7854d3f7 1365 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1366 * @chip: nand chip structure
1367 * @oob: oob destination address
1368 * @ops: oob ops structure
1369 * @len: size of oob to transfer
8593fbc6
TG		 1370 */
1371static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1372 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1373{
f8ac0414 1374 switch (ops->mode) {
8593fbc6 1375
0612b9dd
BN		 1376 case MTD_OPS_PLACE_OOB:
1377 case MTD_OPS_RAW:
8593fbc6
TG		 1378 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1379 return oob + len;
1380
0612b9dd 1381 case MTD_OPS_AUTO_OOB: {
8593fbc6 1382 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1383 uint32_t boffs = 0, roffs = ops->ooboffs;
1384 size_t bytes = 0;
8593fbc6 1385
f8ac0414 1386 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1387 /* Read request not from offset 0? */
7bc3312b
TG		 1388 if (unlikely(roffs)) {
1389 if (roffs >= free->length) {
1390 roffs -= free->length;
1391 continue;
1392 }
1393 boffs = free->offset + roffs;
1394 bytes = min_t(size_t, len,
1395 (free->length - roffs));
1396 roffs = 0;
1397 } else {
1398 bytes = min_t(size_t, len, free->length);
1399 boffs = free->offset;
1400 }
1401 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1402 oob += bytes;
1403 }
1404 return oob;
1405 }
1406 default:
1407 BUG();
1408 }
1409 return NULL;
1410}
1411
1412/**
7854d3f7 1413 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1414 * @mtd: MTD device structure
1415 * @from: offset to read from
1416 * @ops: oob ops structure
f5bbdacc
TG		 1417 *
1418 * Internal function. Called with chip held.
1419 */
8593fbc6
TG		 1420static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1421 struct mtd_oob_ops *ops)
f5bbdacc 1422{
e47f3db4 1423 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc
TG		 1424 struct nand_chip *chip = mtd->priv;
1425 struct mtd_ecc_stats stats;
f5bbdacc 1426 int ret = 0;
8593fbc6 1427 uint32_t readlen = ops->len;
7014568b 1428 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1429 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1430 mtd->oobavail : mtd->oobsize;
1431
8593fbc6 1432 uint8_t *bufpoi, *oob, *buf;
edbc4540 1433 unsigned int max_bitflips = 0;
1da177e4 1434
f5bbdacc 1435 stats = mtd->ecc_stats;
1da177e4 1436
f5bbdacc
TG		 1437 chipnr = (int)(from >> chip->chip_shift);
1438 chip->select_chip(mtd, chipnr);
61b03bd7 1439
f5bbdacc
TG		 1440 realpage = (int)(from >> chip->page_shift);
1441 page = realpage & chip->pagemask;
1da177e4 1442
f5bbdacc 1443 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1444
8593fbc6
TG		 1445 buf = ops->datbuf;
1446 oob = ops->oobbuf;
e47f3db4 1447 oob_required = oob ? 1 : 0;
8593fbc6 1448
f8ac0414 1449 while (1) {
f5bbdacc
TG		 1450 bytes = min(mtd->writesize - col, readlen);
1451 aligned = (bytes == mtd->writesize);
61b03bd7 1452
8b6e50c9 1453 /* Is the current page in the buffer? */
8593fbc6 1454 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1455 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1456
c00a0991 1457 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1458
edbc4540
MD		 1459 /*
1460 * Now read the page into the buffer. Absent an error,
1461 * the read methods return max bitflips per ecc step.
1462 */
0612b9dd 1463 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1464 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1465 oob_required,
1466 page);
a5ff4f10
JW		 1467 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1468 !oob)
7351d3a5
FF		 1469 ret = chip->ecc.read_subpage(mtd, chip,
1470 col, bytes, bufpoi);
956e944c 1471 else
46a8cf2d 1472 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1473 oob_required, page);
6d77b9d0
BN		 1474 if (ret < 0) {
1475 if (!aligned)
1476 /* Invalidate page cache */
1477 chip->pagebuf = -1;
1da177e4 1478 break;
6d77b9d0 1479 }
f5bbdacc 1480
edbc4540
MD		 1481 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1482
f5bbdacc
TG		 1483 /* Transfer not aligned data */
1484 if (!aligned) {
a5ff4f10 1485 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
6d77b9d0 1486 !(mtd->ecc_stats.failed - stats.failed) &&
edbc4540 1487 (ops->mode != MTD_OPS_RAW)) {
3d459559 1488 chip->pagebuf = realpage;
edbc4540
MD		 1489 chip->pagebuf_bitflips = ret;
1490 } else {
6d77b9d0
BN		 1491 /* Invalidate page cache */
1492 chip->pagebuf = -1;
edbc4540 1493 }
4bf63fcb 1494 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1495 }
1496
8593fbc6
TG		 1497 buf += bytes;
1498
1499 if (unlikely(oob)) {
b64d39d8
ML		 1500 int toread = min(oobreadlen, max_oobsize);
1501
1502 if (toread) {
1503 oob = nand_transfer_oob(chip,
1504 oob, ops, toread);
1505 oobreadlen -= toread;
1506 }
8593fbc6 1507 }
5bc7c33c
BN		 1508
1509 if (chip->options & NAND_NEED_READRDY) {
1510 /* Apply delay or wait for ready/busy pin */
1511 if (!chip->dev_ready)
1512 udelay(chip->chip_delay);
1513 else
1514 nand_wait_ready(mtd);
1515 }
8593fbc6 1516 } else {
4bf63fcb 1517 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1518 buf += bytes;
edbc4540
MD		 1519 max_bitflips = max_t(unsigned int, max_bitflips,
1520 chip->pagebuf_bitflips);
8593fbc6 1521 }
1da177e4 1522
f5bbdacc 1523 readlen -= bytes;
61b03bd7 1524
f5bbdacc 1525 if (!readlen)
61b03bd7 1526 break;
1da177e4 1527
8b6e50c9 1528 /* For subsequent reads align to page boundary */
1da177e4
LT		 1529 col = 0;
1530 /* Increment page address */
1531 realpage++;
1532
ace4dfee 1533 page = realpage & chip->pagemask;
1da177e4
LT		 1534 /* Check, if we cross a chip boundary */
1535 if (!page) {
1536 chipnr++;
ace4dfee
TG		 1537 chip->select_chip(mtd, -1);
1538 chip->select_chip(mtd, chipnr);
1da177e4 1539 }
1da177e4 1540 }
b0bb6903 1541 chip->select_chip(mtd, -1);
1da177e4 1542
8593fbc6 1543 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1544 if (oob)
1545 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1546
3f91e94f 1547 if (ret < 0)
f5bbdacc
TG		 1548 return ret;
1549
9a1fcdfd
TG		 1550 if (mtd->ecc_stats.failed - stats.failed)
1551 return -EBADMSG;
1552
edbc4540 1553 return max_bitflips;
f5bbdacc
TG		 1554}
1555
1556/**
25985edc 1557 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1558 * @mtd: MTD device structure
1559 * @from: offset to read from
1560 * @len: number of bytes to read
1561 * @retlen: pointer to variable to store the number of read bytes
1562 * @buf: the databuffer to put data
f5bbdacc 1563 *
8b6e50c9 1564 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1565 */
1566static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1567 size_t *retlen, uint8_t *buf)
1568{
4a89ff88 1569 struct mtd_oob_ops ops;
f5bbdacc
TG		 1570 int ret;
1571
6a8214aa 1572 nand_get_device(mtd, FL_READING);
4a89ff88
BN		 1573 ops.len = len;
1574 ops.datbuf = buf;
1575 ops.oobbuf = NULL;
11041ae6 1576 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1577 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1578 *retlen = ops.retlen;
f5bbdacc 1579 nand_release_device(mtd);
f5bbdacc 1580 return ret;
1da177e4
LT		 1581}
1582
7bc3312b 1583/**
7854d3f7 1584 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1585 * @mtd: mtd info structure
1586 * @chip: nand chip info structure
1587 * @page: page number to read
7bc3312b
TG		 1588 */
1589static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1590 int page)
7bc3312b 1591{
5c2ffb11 1592 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1593 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1594 return 0;
7bc3312b
TG		 1595}
1596
1597/**
7854d3f7 1598 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1599 * with syndromes
8b6e50c9
BN		 1600 * @mtd: mtd info structure
1601 * @chip: nand chip info structure
1602 * @page: page number to read
7bc3312b
TG		 1603 */
1604static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1605 int page)
7bc3312b
TG		 1606{
1607 uint8_t *buf = chip->oob_poi;
1608 int length = mtd->oobsize;
1609 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1610 int eccsize = chip->ecc.size;
1611 uint8_t *bufpoi = buf;
1612 int i, toread, sndrnd = 0, pos;
1613
1614 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1615 for (i = 0; i < chip->ecc.steps; i++) {
1616 if (sndrnd) {
1617 pos = eccsize + i * (eccsize + chunk);
1618 if (mtd->writesize > 512)
1619 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1620 else
1621 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1622 } else
1623 sndrnd = 1;
1624 toread = min_t(int, length, chunk);
1625 chip->read_buf(mtd, bufpoi, toread);
1626 bufpoi += toread;
1627 length -= toread;
1628 }
1629 if (length > 0)
1630 chip->read_buf(mtd, bufpoi, length);
1631
5c2ffb11 1632 return 0;
7bc3312b
TG		 1633}
1634
1635/**
7854d3f7 1636 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1637 * @mtd: mtd info structure
1638 * @chip: nand chip info structure
1639 * @page: page number to write
7bc3312b
TG		 1640 */
1641static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1642 int page)
1643{
1644 int status = 0;
1645 const uint8_t *buf = chip->oob_poi;
1646 int length = mtd->oobsize;
1647
1648 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1649 chip->write_buf(mtd, buf, length);
1650 /* Send command to program the OOB data */
1651 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1652
1653 status = chip->waitfunc(mtd, chip);
1654
0d420f9d 1655 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1656}
1657
1658/**
7854d3f7 1659 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1660 * with syndrome - only for large page flash
1661 * @mtd: mtd info structure
1662 * @chip: nand chip info structure
1663 * @page: page number to write
7bc3312b
TG		 1664 */
1665static int nand_write_oob_syndrome(struct mtd_info *mtd,
1666 struct nand_chip *chip, int page)
1667{
1668 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1669 int eccsize = chip->ecc.size, length = mtd->oobsize;
1670 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1671 const uint8_t *bufpoi = chip->oob_poi;
1672
1673 /*
1674 * data-ecc-data-ecc ... ecc-oob
1675 * or
1676 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1677 */
1678 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1679 pos = steps * (eccsize + chunk);
1680 steps = 0;
1681 } else
8b0036ee 1682 pos = eccsize;
7bc3312b
TG		 1683
1684 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1685 for (i = 0; i < steps; i++) {
1686 if (sndcmd) {
1687 if (mtd->writesize <= 512) {
1688 uint32_t fill = 0xFFFFFFFF;
1689
1690 len = eccsize;
1691 while (len > 0) {
1692 int num = min_t(int, len, 4);
1693 chip->write_buf(mtd, (uint8_t *)&fill,
1694 num);
1695 len -= num;
1696 }
1697 } else {
1698 pos = eccsize + i * (eccsize + chunk);
1699 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1700 }
1701 } else
1702 sndcmd = 1;
1703 len = min_t(int, length, chunk);
1704 chip->write_buf(mtd, bufpoi, len);
1705 bufpoi += len;
1706 length -= len;
1707 }
1708 if (length > 0)
1709 chip->write_buf(mtd, bufpoi, length);
1710
1711 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1712 status = chip->waitfunc(mtd, chip);
1713
1714 return status & NAND_STATUS_FAIL ? -EIO : 0;
1715}
1716
1da177e4 1717/**
7854d3f7 1718 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1719 * @mtd: MTD device structure
1720 * @from: offset to read from
1721 * @ops: oob operations description structure
1da177e4 1722 *
8b6e50c9 1723 * NAND read out-of-band data from the spare area.
1da177e4 1724 */
8593fbc6
TG		 1725static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1726 struct mtd_oob_ops *ops)
1da177e4 1727{
c00a0991 1728 int page, realpage, chipnr;
ace4dfee 1729 struct nand_chip *chip = mtd->priv;
041e4575 1730 struct mtd_ecc_stats stats;
7014568b
VW		 1731 int readlen = ops->ooblen;
1732 int len;
7bc3312b 1733 uint8_t *buf = ops->oobbuf;
1951f2f7 1734 int ret = 0;
61b03bd7 1735
289c0522 1736 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1737 __func__, (unsigned long long)from, readlen);
1da177e4 1738
041e4575
BN		 1739 stats = mtd->ecc_stats;
1740
0612b9dd 1741 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1742 len = chip->ecc.layout->oobavail;
03736155
AH		 1743 else
1744 len = mtd->oobsize;
1745
1746 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1747 pr_debug("%s: attempt to start read outside oob\n",
1748 __func__);
03736155
AH		 1749 return -EINVAL;
1750 }
1751
1752 /* Do not allow reads past end of device */
1753 if (unlikely(from >= mtd->size ||
1754 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1755 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1756 pr_debug("%s: attempt to read beyond end of device\n",
1757 __func__);
03736155
AH		 1758 return -EINVAL;
1759 }
7014568b 1760
7314e9e7 1761 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1762 chip->select_chip(mtd, chipnr);
1da177e4 1763
7314e9e7
TG		 1764 /* Shift to get page */
1765 realpage = (int)(from >> chip->page_shift);
1766 page = realpage & chip->pagemask;
1da177e4 1767
f8ac0414 1768 while (1) {
0612b9dd 1769 if (ops->mode == MTD_OPS_RAW)
1951f2f7 1770 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 1771 else
1951f2f7
SL		 1772 ret = chip->ecc.read_oob(mtd, chip, page);
1773
1774 if (ret < 0)
1775 break;
7014568b
VW		 1776
1777 len = min(len, readlen);
1778 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1779
5bc7c33c
BN		 1780 if (chip->options & NAND_NEED_READRDY) {
1781 /* Apply delay or wait for ready/busy pin */
1782 if (!chip->dev_ready)
1783 udelay(chip->chip_delay);
1784 else
1785 nand_wait_ready(mtd);
1786 }
1787
7014568b 1788 readlen -= len;
0d420f9d
SZ		 1789 if (!readlen)
1790 break;
1791
7314e9e7
TG		 1792 /* Increment page address */
1793 realpage++;
1794
1795 page = realpage & chip->pagemask;
1796 /* Check, if we cross a chip boundary */
1797 if (!page) {
1798 chipnr++;
1799 chip->select_chip(mtd, -1);
1800 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1801 }
1802 }
b0bb6903 1803 chip->select_chip(mtd, -1);
1da177e4 1804
1951f2f7
SL		 1805 ops->oobretlen = ops->ooblen - readlen;
1806
1807 if (ret < 0)
1808 return ret;
041e4575
BN		 1809
1810 if (mtd->ecc_stats.failed - stats.failed)
1811 return -EBADMSG;
1812
1813 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1814}
1815
1816/**
8593fbc6 1817 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1818 * @mtd: MTD device structure
1819 * @from: offset to read from
1820 * @ops: oob operation description structure
1da177e4 1821 *
8b6e50c9 1822 * NAND read data and/or out-of-band data.
1da177e4 1823 */
8593fbc6
TG		 1824static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1825 struct mtd_oob_ops *ops)
1da177e4 1826{
8593fbc6
TG		 1827 int ret = -ENOTSUPP;
1828
1829 ops->retlen = 0;
1da177e4
LT		 1830
1831 /* Do not allow reads past end of device */
7014568b 1832 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1833 pr_debug("%s: attempt to read beyond end of device\n",
1834 __func__);
1da177e4
LT		 1835 return -EINVAL;
1836 }
1837
6a8214aa 1838 nand_get_device(mtd, FL_READING);
1da177e4 1839
f8ac0414 1840 switch (ops->mode) {
0612b9dd
BN		 1841 case MTD_OPS_PLACE_OOB:
1842 case MTD_OPS_AUTO_OOB:
1843 case MTD_OPS_RAW:
8593fbc6 1844 break;
1da177e4 1845
8593fbc6
TG		 1846 default:
1847 goto out;
1848 }
1da177e4 1849
8593fbc6
TG		 1850 if (!ops->datbuf)
1851 ret = nand_do_read_oob(mtd, from, ops);
1852 else
1853 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1854
7351d3a5 1855out:
8593fbc6
TG		 1856 nand_release_device(mtd);
1857 return ret;
1858}
61b03bd7 1859
1da177e4 1860
8593fbc6 1861/**
7854d3f7 1862 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1863 * @mtd: mtd info structure
1864 * @chip: nand chip info structure
1865 * @buf: data buffer
1fbb938d 1866 * @oob_required: must write chip->oob_poi to OOB
52ff49df 1867 *
7854d3f7 1868 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 1869 */
fdbad98d 1870static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1871 const uint8_t *buf, int oob_required)
8593fbc6
TG		 1872{
1873 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1874 if (oob_required)
1875 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1876
1877 return 0;
1da177e4
LT		 1878}
1879
52ff49df 1880/**
7854d3f7 1881 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1882 * @mtd: mtd info structure
1883 * @chip: nand chip info structure
1884 * @buf: data buffer
1fbb938d 1885 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 1886 *
1887 * We need a special oob layout and handling even when ECC isn't checked.
1888 */
fdbad98d 1889static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 1890 struct nand_chip *chip,
1fbb938d 1891 const uint8_t *buf, int oob_required)
52ff49df
DB		 1892{
1893 int eccsize = chip->ecc.size;
1894 int eccbytes = chip->ecc.bytes;
1895 uint8_t *oob = chip->oob_poi;
1896 int steps, size;
1897
1898 for (steps = chip->ecc.steps; steps > 0; steps--) {
1899 chip->write_buf(mtd, buf, eccsize);
1900 buf += eccsize;
1901
1902 if (chip->ecc.prepad) {
1903 chip->write_buf(mtd, oob, chip->ecc.prepad);
1904 oob += chip->ecc.prepad;
1905 }
1906
1907 chip->read_buf(mtd, oob, eccbytes);
1908 oob += eccbytes;
1909
1910 if (chip->ecc.postpad) {
1911 chip->write_buf(mtd, oob, chip->ecc.postpad);
1912 oob += chip->ecc.postpad;
1913 }
1914 }
1915
1916 size = mtd->oobsize - (oob - chip->oob_poi);
1917 if (size)
1918 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 1919
1920 return 0;
52ff49df 1921}
9223a456 1922/**
7854d3f7 1923 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1924 * @mtd: mtd info structure
1925 * @chip: nand chip info structure
1926 * @buf: data buffer
1fbb938d 1927 * @oob_required: must write chip->oob_poi to OOB
9223a456 1928 */
fdbad98d 1929static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1930 const uint8_t *buf, int oob_required)
9223a456 1931{
f75e5097
TG		 1932 int i, eccsize = chip->ecc.size;
1933 int eccbytes = chip->ecc.bytes;
1934 int eccsteps = chip->ecc.steps;
4bf63fcb 1935 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1936 const uint8_t *p = buf;
8b099a39 1937 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1938
7854d3f7 1939 /* Software ECC calculation */
8593fbc6
TG		 1940 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1941 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1942
8593fbc6
TG		 1943 for (i = 0; i < chip->ecc.total; i++)
1944 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1945
fdbad98d 1946 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 1947}
9223a456 1948
f75e5097 1949/**
7854d3f7 1950 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 1951 * @mtd: mtd info structure
1952 * @chip: nand chip info structure
1953 * @buf: data buffer
1fbb938d 1954 * @oob_required: must write chip->oob_poi to OOB
f75e5097 1955 */
fdbad98d 1956static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1957 const uint8_t *buf, int oob_required)
f75e5097
TG		 1958{
1959 int i, eccsize = chip->ecc.size;
1960 int eccbytes = chip->ecc.bytes;
1961 int eccsteps = chip->ecc.steps;
4bf63fcb 1962 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1963 const uint8_t *p = buf;
8b099a39 1964 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1965
f75e5097
TG		 1966 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1967 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1968 chip->write_buf(mtd, p, eccsize);
f75e5097 1969 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1970 }
1971
f75e5097
TG		 1972 for (i = 0; i < chip->ecc.total; i++)
1973 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1974
1975 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1976
1977 return 0;
9223a456
TG		 1978}
1979
837a6ba4
GP		 1980
1981/**
1982 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
1983 * @mtd: mtd info structure
1984 * @chip: nand chip info structure
d6a95080 1985 * @offset: column address of subpage within the page
837a6ba4 1986 * @data_len: data length
d6a95080 1987 * @buf: data buffer
837a6ba4
GP		 1988 * @oob_required: must write chip->oob_poi to OOB
1989 */
1990static int nand_write_subpage_hwecc(struct mtd_info *mtd,
1991 struct nand_chip *chip, uint32_t offset,
d6a95080 1992 uint32_t data_len, const uint8_t *buf,
837a6ba4
GP		 1993 int oob_required)
1994{
1995 uint8_t *oob_buf = chip->oob_poi;
1996 uint8_t *ecc_calc = chip->buffers->ecccalc;
1997 int ecc_size = chip->ecc.size;
1998 int ecc_bytes = chip->ecc.bytes;
1999 int ecc_steps = chip->ecc.steps;
2000 uint32_t *eccpos = chip->ecc.layout->eccpos;
2001 uint32_t start_step = offset / ecc_size;
2002 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2003 int oob_bytes = mtd->oobsize / ecc_steps;
2004 int step, i;
2005
2006 for (step = 0; step < ecc_steps; step++) {
2007 /* configure controller for WRITE access */
2008 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2009
2010 /* write data (untouched subpages already masked by 0xFF) */
d6a95080 2011 chip->write_buf(mtd, buf, ecc_size);
837a6ba4
GP		 2012
2013 /* mask ECC of un-touched subpages by padding 0xFF */
2014 if ((step < start_step) || (step > end_step))
2015 memset(ecc_calc, 0xff, ecc_bytes);
2016 else
d6a95080 2017 chip->ecc.calculate(mtd, buf, ecc_calc);
837a6ba4
GP		 2018
2019 /* mask OOB of un-touched subpages by padding 0xFF */
2020 /* if oob_required, preserve OOB metadata of written subpage */
2021 if (!oob_required || (step < start_step) || (step > end_step))
2022 memset(oob_buf, 0xff, oob_bytes);
2023
d6a95080 2024 buf += ecc_size;
837a6ba4
GP		 2025 ecc_calc += ecc_bytes;
2026 oob_buf += oob_bytes;
2027 }
2028
2029 /* copy calculated ECC for whole page to chip->buffer->oob */
2030 /* this include masked-value(0xFF) for unwritten subpages */
2031 ecc_calc = chip->buffers->ecccalc;
2032 for (i = 0; i < chip->ecc.total; i++)
2033 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2034
2035 /* write OOB buffer to NAND device */
2036 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2037
2038 return 0;
2039}
2040
2041
61b03bd7 2042/**
7854d3f7 2043 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2044 * @mtd: mtd info structure
2045 * @chip: nand chip info structure
2046 * @buf: data buffer
1fbb938d 2047 * @oob_required: must write chip->oob_poi to OOB
1da177e4 2048 *
8b6e50c9
BN		 2049 * The hw generator calculates the error syndrome automatically. Therefore we
2050 * need a special oob layout and handling.
f75e5097 2051 */
fdbad98d 2052static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 2053 struct nand_chip *chip,
2054 const uint8_t *buf, int oob_required)
1da177e4 2055{
f75e5097
TG		 2056 int i, eccsize = chip->ecc.size;
2057 int eccbytes = chip->ecc.bytes;
2058 int eccsteps = chip->ecc.steps;
2059 const uint8_t *p = buf;
2060 uint8_t *oob = chip->oob_poi;
1da177e4 2061
f75e5097 2062 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2063
f75e5097
TG		 2064 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2065 chip->write_buf(mtd, p, eccsize);
61b03bd7 2066
f75e5097
TG		 2067 if (chip->ecc.prepad) {
2068 chip->write_buf(mtd, oob, chip->ecc.prepad);
2069 oob += chip->ecc.prepad;
2070 }
2071
2072 chip->ecc.calculate(mtd, p, oob);
2073 chip->write_buf(mtd, oob, eccbytes);
2074 oob += eccbytes;
2075
2076 if (chip->ecc.postpad) {
2077 chip->write_buf(mtd, oob, chip->ecc.postpad);
2078 oob += chip->ecc.postpad;
1da177e4 2079 }
1da177e4 2080 }
f75e5097
TG		 2081
2082 /* Calculate remaining oob bytes */
7e4178f9 2083 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2084 if (i)
2085 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2086
2087 return 0;
f75e5097
TG		 2088}
2089
2090/**
956e944c 2091 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2092 * @mtd: MTD device structure
2093 * @chip: NAND chip descriptor
837a6ba4
GP		 2094 * @offset: address offset within the page
2095 * @data_len: length of actual data to be written
8b6e50c9 2096 * @buf: the data to write
1fbb938d 2097 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2098 * @page: page number to write
2099 * @cached: cached programming
2100 * @raw: use _raw version of write_page
f75e5097
TG		 2101 */
2102static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4
GP		 2103 uint32_t offset, int data_len, const uint8_t *buf,
2104 int oob_required, int page, int cached, int raw)
f75e5097 2105{
837a6ba4
GP		 2106 int status, subpage;
2107
2108 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2109 chip->ecc.write_subpage)
2110 subpage = offset || (data_len < mtd->writesize);
2111 else
2112 subpage = 0;
f75e5097
TG		 2113
2114 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2115
956e944c 2116 if (unlikely(raw))
837a6ba4
GP		 2117 status = chip->ecc.write_page_raw(mtd, chip, buf,
2118 oob_required);
2119 else if (subpage)
2120 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2121 buf, oob_required);
956e944c 2122 else
fdbad98d
JW		 2123 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2124
2125 if (status < 0)
2126 return status;
f75e5097
TG		 2127
2128 /*
7854d3f7 2129 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2130 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2131 */
2132 cached = 0;
2133
3239a6cd 2134 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2135
2136 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2137 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2138 /*
2139 * See if operation failed and additional status checks are
8b6e50c9 2140 * available.
f75e5097
TG		 2141 */
2142 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2143 status = chip->errstat(mtd, chip, FL_WRITING, status,
2144 page);
2145
2146 if (status & NAND_STATUS_FAIL)
2147 return -EIO;
2148 } else {
2149 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2150 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2151 }
2152
f75e5097 2153 return 0;
1da177e4
LT		 2154}
2155
8593fbc6 2156/**
7854d3f7 2157 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2158 * @mtd: MTD device structure
8b6e50c9
BN		 2159 * @oob: oob data buffer
2160 * @len: oob data write length
2161 * @ops: oob ops structure
8593fbc6 2162 */
f722013e
TAA		 2163static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2164 struct mtd_oob_ops *ops)
8593fbc6 2165{
f722013e
TAA		 2166 struct nand_chip *chip = mtd->priv;
2167
2168 /*
2169 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2170 * data from a previous OOB read.
2171 */
2172 memset(chip->oob_poi, 0xff, mtd->oobsize);
2173
f8ac0414 2174 switch (ops->mode) {
8593fbc6 2175
0612b9dd
BN		 2176 case MTD_OPS_PLACE_OOB:
2177 case MTD_OPS_RAW:
8593fbc6
TG		 2178 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2179 return oob + len;
2180
0612b9dd 2181 case MTD_OPS_AUTO_OOB: {
8593fbc6 2182 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2183 uint32_t boffs = 0, woffs = ops->ooboffs;
2184 size_t bytes = 0;
8593fbc6 2185
f8ac0414 2186 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2187 /* Write request not from offset 0? */
7bc3312b
TG		 2188 if (unlikely(woffs)) {
2189 if (woffs >= free->length) {
2190 woffs -= free->length;
2191 continue;
2192 }
2193 boffs = free->offset + woffs;
2194 bytes = min_t(size_t, len,
2195 (free->length - woffs));
2196 woffs = 0;
2197 } else {
2198 bytes = min_t(size_t, len, free->length);
2199 boffs = free->offset;
2200 }
8b0036ee 2201 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2202 oob += bytes;
2203 }
2204 return oob;
2205 }
2206 default:
2207 BUG();
2208 }
2209 return NULL;
2210}
2211
f8ac0414 2212#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2213
2214/**
7854d3f7 2215 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2216 * @mtd: MTD device structure
2217 * @to: offset to write to
2218 * @ops: oob operations description structure
1da177e4 2219 *
8b6e50c9 2220 * NAND write with ECC.
1da177e4 2221 */
8593fbc6
TG		 2222static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2223 struct mtd_oob_ops *ops)
1da177e4 2224{
29072b96 2225 int chipnr, realpage, page, blockmask, column;
ace4dfee 2226 struct nand_chip *chip = mtd->priv;
8593fbc6 2227 uint32_t writelen = ops->len;
782ce79a
ML		 2228
2229 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2230 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2231 mtd->oobavail : mtd->oobsize;
2232
8593fbc6
TG		 2233 uint8_t *oob = ops->oobbuf;
2234 uint8_t *buf = ops->datbuf;
837a6ba4 2235 int ret;
e47f3db4 2236 int oob_required = oob ? 1 : 0;
1da177e4 2237
8593fbc6 2238 ops->retlen = 0;
29072b96
TG		 2239 if (!writelen)
2240 return 0;
1da177e4 2241
8b6e50c9 2242 /* Reject writes, which are not page aligned */
8593fbc6 2243 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2244 pr_notice("%s: attempt to write non page aligned data\n",
2245 __func__);
1da177e4
LT		 2246 return -EINVAL;
2247 }
2248
29072b96 2249 column = to & (mtd->writesize - 1);
1da177e4 2250
6a930961
TG		 2251 chipnr = (int)(to >> chip->chip_shift);
2252 chip->select_chip(mtd, chipnr);
2253
1da177e4 2254 /* Check, if it is write protected */
b0bb6903
HS		 2255 if (nand_check_wp(mtd)) {
2256 ret = -EIO;
2257 goto err_out;
2258 }
1da177e4 2259
f75e5097
TG		 2260 realpage = (int)(to >> chip->page_shift);
2261 page = realpage & chip->pagemask;
2262 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2263
2264 /* Invalidate the page cache, when we write to the cached page */
2265 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2266 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2267 chip->pagebuf = -1;
61b03bd7 2268
782ce79a 2269 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2270 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2271 ret = -EINVAL;
2272 goto err_out;
2273 }
782ce79a 2274
f8ac0414 2275 while (1) {
29072b96 2276 int bytes = mtd->writesize;
f75e5097 2277 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2278 uint8_t *wbuf = buf;
2279
8b6e50c9 2280 /* Partial page write? */
29072b96
TG		 2281 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2282 cached = 0;
2283 bytes = min_t(int, bytes - column, (int) writelen);
2284 chip->pagebuf = -1;
2285 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2286 memcpy(&chip->buffers->databuf[column], buf, bytes);
2287 wbuf = chip->buffers->databuf;
2288 }
1da177e4 2289
782ce79a
ML		 2290 if (unlikely(oob)) {
2291 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2292 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2293 oobwritelen -= len;
f722013e
TAA		 2294 } else {
2295 /* We still need to erase leftover OOB data */
2296 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2297 }
837a6ba4
GP		 2298 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2299 oob_required, page, cached,
2300 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2301 if (ret)
2302 break;
2303
2304 writelen -= bytes;
2305 if (!writelen)
2306 break;
2307
29072b96 2308 column = 0;
f75e5097
TG		 2309 buf += bytes;
2310 realpage++;
2311
2312 page = realpage & chip->pagemask;
2313 /* Check, if we cross a chip boundary */
2314 if (!page) {
2315 chipnr++;
2316 chip->select_chip(mtd, -1);
2317 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2318 }
2319 }
8593fbc6 2320
8593fbc6 2321 ops->retlen = ops->len - writelen;
7014568b
VW		 2322 if (unlikely(oob))
2323 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2324
2325err_out:
2326 chip->select_chip(mtd, -1);
1da177e4
LT		 2327 return ret;
2328}
2329
2af7c653
SK		 2330/**
2331 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2332 * @mtd: MTD device structure
2333 * @to: offset to write to
2334 * @len: number of bytes to write
2335 * @retlen: pointer to variable to store the number of written bytes
2336 * @buf: the data to write
2af7c653
SK		 2337 *
2338 * NAND write with ECC. Used when performing writes in interrupt context, this
2339 * may for example be called by mtdoops when writing an oops while in panic.
2340 */
2341static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2342 size_t *retlen, const uint8_t *buf)
2343{
2344 struct nand_chip *chip = mtd->priv;
4a89ff88 2345 struct mtd_oob_ops ops;
2af7c653
SK		 2346 int ret;
2347
8b6e50c9 2348 /* Wait for the device to get ready */
2af7c653
SK		 2349 panic_nand_wait(mtd, chip, 400);
2350
8b6e50c9 2351 /* Grab the device */
2af7c653
SK		 2352 panic_nand_get_device(chip, mtd, FL_WRITING);
2353
4a89ff88
BN		 2354 ops.len = len;
2355 ops.datbuf = (uint8_t *)buf;
2356 ops.oobbuf = NULL;
11041ae6 2357 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2358
4a89ff88 2359 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2360
4a89ff88 2361 *retlen = ops.retlen;
2af7c653
SK		 2362 return ret;
2363}
2364
f75e5097 2365/**
8593fbc6 2366 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2367 * @mtd: MTD device structure
2368 * @to: offset to write to
2369 * @len: number of bytes to write
2370 * @retlen: pointer to variable to store the number of written bytes
2371 * @buf: the data to write
f75e5097 2372 *
8b6e50c9 2373 * NAND write with ECC.
f75e5097 2374 */
8593fbc6
TG		 2375static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2376 size_t *retlen, const uint8_t *buf)
f75e5097 2377{
4a89ff88 2378 struct mtd_oob_ops ops;
f75e5097
TG		 2379 int ret;
2380
6a8214aa 2381 nand_get_device(mtd, FL_WRITING);
4a89ff88
BN		 2382 ops.len = len;
2383 ops.datbuf = (uint8_t *)buf;
2384 ops.oobbuf = NULL;
11041ae6 2385 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2386 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2387 *retlen = ops.retlen;
f75e5097 2388 nand_release_device(mtd);
8593fbc6 2389 return ret;
f75e5097 2390}
7314e9e7 2391
1da177e4 2392/**
8593fbc6 2393 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2394 * @mtd: MTD device structure
2395 * @to: offset to write to
2396 * @ops: oob operation description structure
1da177e4 2397 *
8b6e50c9 2398 * NAND write out-of-band.
1da177e4 2399 */
8593fbc6
TG		 2400static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2401 struct mtd_oob_ops *ops)
1da177e4 2402{
03736155 2403 int chipnr, page, status, len;
ace4dfee 2404 struct nand_chip *chip = mtd->priv;
1da177e4 2405
289c0522 2406 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2407 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2408
0612b9dd 2409 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2410 len = chip->ecc.layout->oobavail;
2411 else
2412 len = mtd->oobsize;
2413
1da177e4 2414 /* Do not allow write past end of page */
03736155 2415 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2416 pr_debug("%s: attempt to write past end of page\n",
2417 __func__);
1da177e4
LT		 2418 return -EINVAL;
2419 }
2420
03736155 2421 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2422 pr_debug("%s: attempt to start write outside oob\n",
2423 __func__);
03736155
AH		 2424 return -EINVAL;
2425 }
2426
775adc3d 2427 /* Do not allow write past end of device */
03736155
AH		 2428 if (unlikely(to >= mtd->size ||
2429 ops->ooboffs + ops->ooblen >
2430 ((mtd->size >> chip->page_shift) -
2431 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2432 pr_debug("%s: attempt to write beyond end of device\n",
2433 __func__);
03736155
AH		 2434 return -EINVAL;
2435 }
2436
7314e9e7 2437 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2438 chip->select_chip(mtd, chipnr);
1da177e4 2439
7314e9e7
TG		 2440 /* Shift to get page */
2441 page = (int)(to >> chip->page_shift);
2442
2443 /*
2444 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2445 * of my DiskOnChip 2000 test units) will clear the whole data page too
2446 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2447 * it in the doc2000 driver in August 1999. dwmw2.
2448 */
ace4dfee 2449 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2450
2451 /* Check, if it is write protected */
b0bb6903
HS		 2452 if (nand_check_wp(mtd)) {
2453 chip->select_chip(mtd, -1);
8593fbc6 2454 return -EROFS;
b0bb6903 2455 }
61b03bd7 2456
1da177e4 2457 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2458 if (page == chip->pagebuf)
2459 chip->pagebuf = -1;
1da177e4 2460
f722013e 2461 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2462
0612b9dd 2463 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2464 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2465 else
2466 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2467
b0bb6903
HS		 2468 chip->select_chip(mtd, -1);
2469
7bc3312b
TG		 2470 if (status)
2471 return status;
1da177e4 2472
7014568b 2473 ops->oobretlen = ops->ooblen;
1da177e4 2474
7bc3312b 2475 return 0;
8593fbc6
TG		 2476}
2477
2478/**
2479 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2480 * @mtd: MTD device structure
2481 * @to: offset to write to
2482 * @ops: oob operation description structure
8593fbc6
TG		 2483 */
2484static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2485 struct mtd_oob_ops *ops)
2486{
8593fbc6
TG		 2487 int ret = -ENOTSUPP;
2488
2489 ops->retlen = 0;
2490
2491 /* Do not allow writes past end of device */
7014568b 2492 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2493 pr_debug("%s: attempt to write beyond end of device\n",
2494 __func__);
8593fbc6
TG		 2495 return -EINVAL;
2496 }
2497
6a8214aa 2498 nand_get_device(mtd, FL_WRITING);
8593fbc6 2499
f8ac0414 2500 switch (ops->mode) {
0612b9dd
BN		 2501 case MTD_OPS_PLACE_OOB:
2502 case MTD_OPS_AUTO_OOB:
2503 case MTD_OPS_RAW:
8593fbc6
TG		 2504 break;
2505
2506 default:
2507 goto out;
2508 }
2509
2510 if (!ops->datbuf)
2511 ret = nand_do_write_oob(mtd, to, ops);
2512 else
2513 ret = nand_do_write_ops(mtd, to, ops);
2514
7351d3a5 2515out:
1da177e4 2516 nand_release_device(mtd);
1da177e4
LT		 2517 return ret;
2518}
2519
1da177e4 2520/**
7854d3f7 2521 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2522 * @mtd: MTD device structure
2523 * @page: the page address of the block which will be erased
1da177e4 2524 *
8b6e50c9 2525 * Standard erase command for NAND chips.
1da177e4 2526 */
e0c7d767 2527static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2528{
ace4dfee 2529 struct nand_chip *chip = mtd->priv;
1da177e4 2530 /* Send commands to erase a block */
ace4dfee
TG		 2531 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2532 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2533}
2534
1da177e4
LT		 2535/**
2536 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2537 * @mtd: MTD device structure
2538 * @instr: erase instruction
1da177e4 2539 *
8b6e50c9 2540 * Erase one ore more blocks.
1da177e4 2541 */
e0c7d767 2542static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2543{
e0c7d767 2544 return nand_erase_nand(mtd, instr, 0);
1da177e4 2545}
61b03bd7 2546
1da177e4 2547/**
7854d3f7 2548 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2549 * @mtd: MTD device structure
2550 * @instr: erase instruction
2551 * @allowbbt: allow erasing the bbt area
1da177e4 2552 *
8b6e50c9 2553 * Erase one ore more blocks.
1da177e4 2554 */
ace4dfee
TG		 2555int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2556 int allowbbt)
1da177e4 2557{
69423d99 2558 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2559 struct nand_chip *chip = mtd->priv;
69423d99 2560 loff_t len;
1da177e4 2561
289c0522
BN		 2562 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2563 __func__, (unsigned long long)instr->addr,
2564 (unsigned long long)instr->len);
1da177e4 2565
6fe5a6ac 2566 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2567 return -EINVAL;
1da177e4 2568
1da177e4 2569 /* Grab the lock and see if the device is available */
6a8214aa 2570 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 2571
2572 /* Shift to get first page */
ace4dfee
TG		 2573 page = (int)(instr->addr >> chip->page_shift);
2574 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2575
2576 /* Calculate pages in each block */
ace4dfee 2577 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2578
2579 /* Select the NAND device */
ace4dfee 2580 chip->select_chip(mtd, chipnr);
1da177e4 2581
1da177e4
LT		 2582 /* Check, if it is write protected */
2583 if (nand_check_wp(mtd)) {
289c0522
BN		 2584 pr_debug("%s: device is write protected!\n",
2585 __func__);
1da177e4
LT		 2586 instr->state = MTD_ERASE_FAILED;
2587 goto erase_exit;
2588 }
2589
2590 /* Loop through the pages */
2591 len = instr->len;
2592
2593 instr->state = MTD_ERASING;
2594
2595 while (len) {
12183a20 2596 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2597 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2598 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2599 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2600 __func__, page);
1da177e4
LT		 2601 instr->state = MTD_ERASE_FAILED;
2602 goto erase_exit;
2603 }
61b03bd7 2604
ace4dfee
TG		 2605 /*
2606 * Invalidate the page cache, if we erase the block which
8b6e50c9 2607 * contains the current cached page.
ace4dfee
TG		 2608 */
2609 if (page <= chip->pagebuf && chip->pagebuf <
2610 (page + pages_per_block))
2611 chip->pagebuf = -1;
1da177e4 2612
ace4dfee 2613 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2614
7bc3312b 2615 status = chip->waitfunc(mtd, chip);
1da177e4 2616
ace4dfee
TG		 2617 /*
2618 * See if operation failed and additional status checks are
2619 * available
2620 */
2621 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2622 status = chip->errstat(mtd, chip, FL_ERASING,
2623 status, page);
068e3c0a 2624
1da177e4 2625 /* See if block erase succeeded */
a4ab4c5d 2626 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2627 pr_debug("%s: failed erase, page 0x%08x\n",
2628 __func__, page);
1da177e4 2629 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2630 instr->fail_addr =
2631 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2632 goto erase_exit;
2633 }
30f464b7 2634
1da177e4 2635 /* Increment page address and decrement length */
daae74ca 2636 len -= (1ULL << chip->phys_erase_shift);
1da177e4
LT		 2637 page += pages_per_block;
2638
2639 /* Check, if we cross a chip boundary */
ace4dfee 2640 if (len && !(page & chip->pagemask)) {
1da177e4 2641 chipnr++;
ace4dfee
TG		 2642 chip->select_chip(mtd, -1);
2643 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2644 }
2645 }
2646 instr->state = MTD_ERASE_DONE;
2647
7351d3a5 2648erase_exit:
1da177e4
LT		 2649
2650 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2651
2652 /* Deselect and wake up anyone waiting on the device */
b0bb6903 2653 chip->select_chip(mtd, -1);
1da177e4
LT		 2654 nand_release_device(mtd);
2655
49defc01
DW		 2656 /* Do call back function */
2657 if (!ret)
2658 mtd_erase_callback(instr);
2659
1da177e4
LT		 2660 /* Return more or less happy */
2661 return ret;
2662}
2663
2664/**
2665 * nand_sync - [MTD Interface] sync
8b6e50c9 2666 * @mtd: MTD device structure
1da177e4 2667 *
8b6e50c9 2668 * Sync is actually a wait for chip ready function.
1da177e4 2669 */
e0c7d767 2670static void nand_sync(struct mtd_info *mtd)
1da177e4 2671{
289c0522 2672 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2673
2674 /* Grab the lock and see if the device is available */
6a8214aa 2675 nand_get_device(mtd, FL_SYNCING);
1da177e4 2676 /* Release it and go back */
e0c7d767 2677 nand_release_device(mtd);
1da177e4
LT		 2678}
2679
1da177e4 2680/**
ace4dfee 2681 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2682 * @mtd: MTD device structure
2683 * @offs: offset relative to mtd start
1da177e4 2684 */
ace4dfee 2685static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2686{
ace4dfee 2687 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2688}
2689
2690/**
ace4dfee 2691 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2692 * @mtd: MTD device structure
2693 * @ofs: offset relative to mtd start
1da177e4 2694 */
e0c7d767 2695static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2696{
1da177e4
LT		 2697 int ret;
2698
f8ac0414
FF		 2699 ret = nand_block_isbad(mtd, ofs);
2700 if (ret) {
8b6e50c9 2701 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2702 if (ret > 0)
2703 return 0;
e0c7d767
DW		 2704 return ret;
2705 }
1da177e4 2706
5a0edb25 2707 return nand_block_markbad_lowlevel(mtd, ofs);
1da177e4
LT		 2708}
2709
7db03ecc
HS		 2710/**
2711 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2712 * @mtd: MTD device structure
2713 * @chip: nand chip info structure
2714 * @addr: feature address.
2715 * @subfeature_param: the subfeature parameters, a four bytes array.
2716 */
2717static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2718 int addr, uint8_t *subfeature_param)
2719{
2720 int status;
2721
d914c932
DM		 2722 if (!chip->onfi_version ||
2723 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2724 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 2725 return -EINVAL;
2726
2727 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2728 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2729 status = chip->waitfunc(mtd, chip);
2730 if (status & NAND_STATUS_FAIL)
2731 return -EIO;
2732 return 0;
2733}
2734
2735/**
2736 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2737 * @mtd: MTD device structure
2738 * @chip: nand chip info structure
2739 * @addr: feature address.
2740 * @subfeature_param: the subfeature parameters, a four bytes array.
2741 */
2742static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2743 int addr, uint8_t *subfeature_param)
2744{
d914c932
DM		 2745 if (!chip->onfi_version ||
2746 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2747 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 2748 return -EINVAL;
2749
2750 /* clear the sub feature parameters */
2751 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2752
2753 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2754 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2755 return 0;
2756}
2757
962034f4
VW		 2758/**
2759 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2760 * @mtd: MTD device structure
962034f4
VW		 2761 */
2762static int nand_suspend(struct mtd_info *mtd)
2763{
6a8214aa 2764 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 2765}
2766
2767/**
2768 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2769 * @mtd: MTD device structure
962034f4
VW		 2770 */
2771static void nand_resume(struct mtd_info *mtd)
2772{
ace4dfee 2773 struct nand_chip *chip = mtd->priv;
962034f4 2774
ace4dfee 2775 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2776 nand_release_device(mtd);
2777 else
d0370219
BN		 2778 pr_err("%s called for a chip which is not in suspended state\n",
2779 __func__);
962034f4
VW		 2780}
2781
8b6e50c9 2782/* Set default functions */
ace4dfee 2783static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2784{
1da177e4 2785 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2786 if (!chip->chip_delay)
2787 chip->chip_delay = 20;
1da177e4
LT		 2788
2789 /* check, if a user supplied command function given */
ace4dfee
TG		 2790 if (chip->cmdfunc == NULL)
2791 chip->cmdfunc = nand_command;
1da177e4
LT		 2792
2793 /* check, if a user supplied wait function given */
ace4dfee
TG		 2794 if (chip->waitfunc == NULL)
2795 chip->waitfunc = nand_wait;
2796
2797 if (!chip->select_chip)
2798 chip->select_chip = nand_select_chip;
68e80780 2799
4204cccd
HS		 2800 /* set for ONFI nand */
2801 if (!chip->onfi_set_features)
2802 chip->onfi_set_features = nand_onfi_set_features;
2803 if (!chip->onfi_get_features)
2804 chip->onfi_get_features = nand_onfi_get_features;
2805
68e80780
BN		 2806 /* If called twice, pointers that depend on busw may need to be reset */
2807 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 2808 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2809 if (!chip->read_word)
2810 chip->read_word = nand_read_word;
2811 if (!chip->block_bad)
2812 chip->block_bad = nand_block_bad;
2813 if (!chip->block_markbad)
2814 chip->block_markbad = nand_default_block_markbad;
68e80780 2815 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 2816 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
68e80780 2817 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 2818 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 2819 if (!chip->scan_bbt)
2820 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2821
2822 if (!chip->controller) {
2823 chip->controller = &chip->hwcontrol;
2824 spin_lock_init(&chip->controller->lock);
2825 init_waitqueue_head(&chip->controller->wq);
2826 }
2827
7aa65bfd
TG		 2828}
2829
8b6e50c9 2830/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2831static void sanitize_string(uint8_t *s, size_t len)
2832{
2833 ssize_t i;
2834
8b6e50c9 2835 /* Null terminate */
d1e1f4e4
FF		 2836 s[len - 1] = 0;
2837
8b6e50c9 2838 /* Remove non printable chars */
d1e1f4e4
FF		 2839 for (i = 0; i < len - 1; i++) {
2840 if (s[i] < ' ' || s[i] > 127)
2841 s[i] = '?';
2842 }
2843
8b6e50c9 2844 /* Remove trailing spaces */
d1e1f4e4
FF		 2845 strim(s);
2846}
2847
2848static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2849{
2850 int i;
2851 while (len--) {
2852 crc ^= *p++ << 8;
2853 for (i = 0; i < 8; i++)
2854 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2855 }
2856
2857 return crc;
2858}
2859
6dcbe0cd
HS		 2860/* Parse the Extended Parameter Page. */
2861static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
2862 struct nand_chip *chip, struct nand_onfi_params *p)
2863{
2864 struct onfi_ext_param_page *ep;
2865 struct onfi_ext_section *s;
2866 struct onfi_ext_ecc_info *ecc;
2867 uint8_t *cursor;
2868 int ret = -EINVAL;
2869 int len;
2870 int i;
2871
2872 len = le16_to_cpu(p->ext_param_page_length) * 16;
2873 ep = kmalloc(len, GFP_KERNEL);
5cb13271
BN		 2874 if (!ep)
2875 return -ENOMEM;
6dcbe0cd
HS		 2876
2877 /* Send our own NAND_CMD_PARAM. */
2878 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2879
2880 /* Use the Change Read Column command to skip the ONFI param pages. */
2881 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
2882 sizeof(*p) * p->num_of_param_pages , -1);
2883
2884 /* Read out the Extended Parameter Page. */
2885 chip->read_buf(mtd, (uint8_t *)ep, len);
2886 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
2887 != le16_to_cpu(ep->crc))) {
2888 pr_debug("fail in the CRC.\n");
2889 goto ext_out;
2890 }
2891
2892 /*
2893 * Check the signature.
2894 * Do not strictly follow the ONFI spec, maybe changed in future.
2895 */
2896 if (strncmp(ep->sig, "EPPS", 4)) {
2897 pr_debug("The signature is invalid.\n");
2898 goto ext_out;
2899 }
2900
2901 /* find the ECC section. */
2902 cursor = (uint8_t *)(ep + 1);
2903 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
2904 s = ep->sections + i;
2905 if (s->type == ONFI_SECTION_TYPE_2)
2906 break;
2907 cursor += s->length * 16;
2908 }
2909 if (i == ONFI_EXT_SECTION_MAX) {
2910 pr_debug("We can not find the ECC section.\n");
2911 goto ext_out;
2912 }
2913
2914 /* get the info we want. */
2915 ecc = (struct onfi_ext_ecc_info *)cursor;
2916
4ae7d228
BN		 2917 if (!ecc->codeword_size) {
2918 pr_debug("Invalid codeword size\n");
2919 goto ext_out;
6dcbe0cd
HS		 2920 }
2921
4ae7d228
BN		 2922 chip->ecc_strength_ds = ecc->ecc_bits;
2923 chip->ecc_step_ds = 1 << ecc->codeword_size;
5cb13271 2924 ret = 0;
6dcbe0cd
HS		 2925
2926ext_out:
2927 kfree(ep);
2928 return ret;
2929}
2930
6fb277ba 2931/*
8b6e50c9 2932 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2933 */
2934static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2935 int *busw)
6fb277ba
FF		 2936{
2937 struct nand_onfi_params *p = &chip->onfi_params;
2938 int i;
2939 int val;
2940
7854d3f7 2941 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2942 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2943 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2944 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2945 return 0;
2946
c7f23a70
BN		 2947 /*
2948 * ONFI must be probed in 8-bit mode or with NAND_BUSWIDTH_AUTO, not
2949 * with NAND_BUSWIDTH_16
2950 */
2951 if (chip->options & NAND_BUSWIDTH_16) {
2952 pr_err("ONFI cannot be probed in 16-bit mode; aborting\n");
2953 return 0;
2954 }
2955
6fb277ba
FF		 2956 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2957 for (i = 0; i < 3; i++) {
2958 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2959 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2960 le16_to_cpu(p->crc)) {
6fb277ba
FF		 2961 break;
2962 }
2963 }
2964
c7f23a70
BN		 2965 if (i == 3) {
2966 pr_err("Could not find valid ONFI parameter page; aborting\n");
6fb277ba 2967 return 0;
c7f23a70 2968 }
6fb277ba 2969
8b6e50c9 2970 /* Check version */
6fb277ba 2971 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2972 if (val & (1 << 5))
2973 chip->onfi_version = 23;
2974 else if (val & (1 << 4))
6fb277ba
FF		 2975 chip->onfi_version = 22;
2976 else if (val & (1 << 3))
2977 chip->onfi_version = 21;
2978 else if (val & (1 << 2))
2979 chip->onfi_version = 20;
b7b1a29d 2980 else if (val & (1 << 1))
6fb277ba 2981 chip->onfi_version = 10;
b7b1a29d
BN		 2982
2983 if (!chip->onfi_version) {
20171642 2984 pr_info("unsupported ONFI version: %d\n", val);
b7b1a29d
BN		 2985 return 0;
2986 }
6fb277ba
FF		 2987
2988 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2989 sanitize_string(p->model, sizeof(p->model));
2990 if (!mtd->name)
2991 mtd->name = p->model;
4355b70c 2992
6fb277ba 2993 mtd->writesize = le32_to_cpu(p->byte_per_page);
4355b70c
BN		 2994
2995 /*
2996 * pages_per_block and blocks_per_lun may not be a power-of-2 size
2997 * (don't ask me who thought of this...). MTD assumes that these
2998 * dimensions will be power-of-2, so just truncate the remaining area.
2999 */
3000 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3001 mtd->erasesize *= mtd->writesize;
3002
6fb277ba 3003 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4355b70c
BN		 3004
3005 /* See erasesize comment */
3006 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3007 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
13fbd179 3008 chip->bits_per_cell = p->bits_per_cell;
e2985fc1
HS		 3009
3010 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
08c248fb 3011 *busw = NAND_BUSWIDTH_16;
e2985fc1
HS		 3012 else
3013 *busw = 0;
6fb277ba 3014
10c86bab
HS		 3015 if (p->ecc_bits != 0xff) {
3016 chip->ecc_strength_ds = p->ecc_bits;
3017 chip->ecc_step_ds = 512;
6dcbe0cd
HS		 3018 } else if (chip->onfi_version >= 21 &&
3019 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3020
3021 /*
3022 * The nand_flash_detect_ext_param_page() uses the
3023 * Change Read Column command which maybe not supported
3024 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3025 * now. We do not replace user supplied command function.
3026 */
3027 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3028 chip->cmdfunc = nand_command_lp;
3029
3030 /* The Extended Parameter Page is supported since ONFI 2.1. */
3031 if (nand_flash_detect_ext_param_page(mtd, chip, p))
c7f23a70
BN		 3032 pr_warn("Failed to detect ONFI extended param page\n");
3033 } else {
3034 pr_warn("Could not retrieve ONFI ECC requirements\n");
10c86bab
HS		 3035 }
3036
6fb277ba
FF		 3037 return 1;
3038}
3039
e3b88bd6
BN		 3040/*
3041 * nand_id_has_period - Check if an ID string has a given wraparound period
3042 * @id_data: the ID string
3043 * @arrlen: the length of the @id_data array
3044 * @period: the period of repitition
3045 *
3046 * Check if an ID string is repeated within a given sequence of bytes at
3047 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3048 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3049 * if the repetition has a period of @period; otherwise, returns zero.
3050 */
3051static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3052{
3053 int i, j;
3054 for (i = 0; i < period; i++)
3055 for (j = i + period; j < arrlen; j += period)
3056 if (id_data[i] != id_data[j])
3057 return 0;
3058 return 1;
3059}
3060
3061/*
3062 * nand_id_len - Get the length of an ID string returned by CMD_READID
3063 * @id_data: the ID string
3064 * @arrlen: the length of the @id_data array
3065
3066 * Returns the length of the ID string, according to known wraparound/trailing
3067 * zero patterns. If no pattern exists, returns the length of the array.
3068 */
3069static int nand_id_len(u8 *id_data, int arrlen)
3070{
3071 int last_nonzero, period;
3072
3073 /* Find last non-zero byte */
3074 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3075 if (id_data[last_nonzero])
3076 break;
3077
3078 /* All zeros */
3079 if (last_nonzero < 0)
3080 return 0;
3081
3082 /* Calculate wraparound period */
3083 for (period = 1; period < arrlen; period++)
3084 if (nand_id_has_period(id_data, arrlen, period))
3085 break;
3086
3087 /* There's a repeated pattern */
3088 if (period < arrlen)
3089 return period;
3090
3091 /* There are trailing zeros */
3092 if (last_nonzero < arrlen - 1)
3093 return last_nonzero + 1;
3094
3095 /* No pattern detected */
3096 return arrlen;
3097}
3098
7db906b7
HS		 3099/* Extract the bits of per cell from the 3rd byte of the extended ID */
3100static int nand_get_bits_per_cell(u8 cellinfo)
3101{
3102 int bits;
3103
3104 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3105 bits >>= NAND_CI_CELLTYPE_SHIFT;
3106 return bits + 1;
3107}
3108
fc09bbc0
BN		 3109/*
3110 * Many new NAND share similar device ID codes, which represent the size of the
3111 * chip. The rest of the parameters must be decoded according to generic or
3112 * manufacturer-specific "extended ID" decoding patterns.
3113 */
3114static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3115 u8 id_data[8], int *busw)
3116{
e3b88bd6 3117 int extid, id_len;
fc09bbc0 3118 /* The 3rd id byte holds MLC / multichip data */
7db906b7 3119 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
fc09bbc0
BN		 3120 /* The 4th id byte is the important one */
3121 extid = id_data[3];
3122
e3b88bd6
BN		 3123 id_len = nand_id_len(id_data, 8);
3124
fc09bbc0
BN		 3125 /*
3126 * Field definitions are in the following datasheets:
3127 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 3128 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 3129 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 3130 *
af451af4
BN		 3131 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3132 * ID to decide what to do.
fc09bbc0 3133 */
af451af4 3134 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
1d0ed69d 3135 !nand_is_slc(chip) && id_data[5] != 0x00) {
fc09bbc0
BN		 3136 /* Calc pagesize */
3137 mtd->writesize = 2048 << (extid & 0x03);
3138 extid >>= 2;
3139 /* Calc oobsize */
e2d3a35e 3140 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 3141 case 1:
3142 mtd->oobsize = 128;
3143 break;
3144 case 2:
3145 mtd->oobsize = 218;
3146 break;
3147 case 3:
3148 mtd->oobsize = 400;
3149 break;
e2d3a35e 3150 case 4:
fc09bbc0
BN		 3151 mtd->oobsize = 436;
3152 break;
e2d3a35e
BN		 3153 case 5:
3154 mtd->oobsize = 512;
3155 break;
3156 case 6:
3157 default: /* Other cases are "reserved" (unknown) */
3158 mtd->oobsize = 640;
3159 break;
fc09bbc0
BN		 3160 }
3161 extid >>= 2;
3162 /* Calc blocksize */
3163 mtd->erasesize = (128 * 1024) <<
3164 (((extid >> 1) & 0x04) | (extid & 0x03));
3165 *busw = 0;
73ca392f 3166 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
1d0ed69d 3167 !nand_is_slc(chip)) {
73ca392f
BN		 3168 unsigned int tmp;
3169
3170 /* Calc pagesize */
3171 mtd->writesize = 2048 << (extid & 0x03);
3172 extid >>= 2;
3173 /* Calc oobsize */
3174 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3175 case 0:
3176 mtd->oobsize = 128;
3177 break;
3178 case 1:
3179 mtd->oobsize = 224;
3180 break;
3181 case 2:
3182 mtd->oobsize = 448;
3183 break;
3184 case 3:
3185 mtd->oobsize = 64;
3186 break;
3187 case 4:
3188 mtd->oobsize = 32;
3189 break;
3190 case 5:
3191 mtd->oobsize = 16;
3192 break;
3193 default:
3194 mtd->oobsize = 640;
3195 break;
3196 }
3197 extid >>= 2;
3198 /* Calc blocksize */
3199 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3200 if (tmp < 0x03)
3201 mtd->erasesize = (128 * 1024) << tmp;
3202 else if (tmp == 0x03)
3203 mtd->erasesize = 768 * 1024;
3204 else
3205 mtd->erasesize = (64 * 1024) << tmp;
3206 *busw = 0;
fc09bbc0
BN		 3207 } else {
3208 /* Calc pagesize */
3209 mtd->writesize = 1024 << (extid & 0x03);
3210 extid >>= 2;
3211 /* Calc oobsize */
3212 mtd->oobsize = (8 << (extid & 0x01)) *
3213 (mtd->writesize >> 9);
3214 extid >>= 2;
3215 /* Calc blocksize. Blocksize is multiples of 64KiB */
3216 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3217 extid >>= 2;
3218 /* Get buswidth information */
3219 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
60c67382
BN		 3220
3221 /*
3222 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3223 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3224 * follows:
3225 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3226 * 110b -> 24nm
3227 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3228 */
3229 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
1d0ed69d 3230 nand_is_slc(chip) &&
60c67382
BN		 3231 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3232 !(id_data[4] & 0x80) /* !BENAND */) {
3233 mtd->oobsize = 32 * mtd->writesize >> 9;
3234 }
3235
fc09bbc0
BN		 3236 }
3237}
3238
f23a481c
BN		 3239/*
3240 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3241 * decodes a matching ID table entry and assigns the MTD size parameters for
3242 * the chip.
3243 */
3244static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3245 struct nand_flash_dev *type, u8 id_data[8],
3246 int *busw)
3247{
3248 int maf_id = id_data[0];
3249
3250 mtd->erasesize = type->erasesize;
3251 mtd->writesize = type->pagesize;
3252 mtd->oobsize = mtd->writesize / 32;
3253 *busw = type->options & NAND_BUSWIDTH_16;
3254
1c195e90
HS		 3255 /* All legacy ID NAND are small-page, SLC */
3256 chip->bits_per_cell = 1;
3257
f23a481c
BN		 3258 /*
3259 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3260 * some Spansion chips have erasesize that conflicts with size
3261 * listed in nand_ids table.
3262 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3263 */
3264 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3265 && id_data[6] == 0x00 && id_data[7] == 0x00
3266 && mtd->writesize == 512) {
3267 mtd->erasesize = 128 * 1024;
3268 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3269 }
3270}
3271
7e74c2d7
BN		 3272/*
3273 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3274 * heuristic patterns using various detected parameters (e.g., manufacturer,
3275 * page size, cell-type information).
3276 */
3277static void nand_decode_bbm_options(struct mtd_info *mtd,
3278 struct nand_chip *chip, u8 id_data[8])
3279{
3280 int maf_id = id_data[0];
3281
3282 /* Set the bad block position */
3283 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3284 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3285 else
3286 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3287
3288 /*
3289 * Bad block marker is stored in the last page of each block on Samsung
3290 * and Hynix MLC devices; stored in first two pages of each block on
3291 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3292 * AMD/Spansion, and Macronix. All others scan only the first page.
3293 */
1d0ed69d 3294 if (!nand_is_slc(chip) &&
7e74c2d7
BN		 3295 (maf_id == NAND_MFR_SAMSUNG ||
3296 maf_id == NAND_MFR_HYNIX))
3297 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
1d0ed69d 3298 else if ((nand_is_slc(chip) &&
7e74c2d7
BN		 3299 (maf_id == NAND_MFR_SAMSUNG ||
3300 maf_id == NAND_MFR_HYNIX ||
3301 maf_id == NAND_MFR_TOSHIBA ||
3302 maf_id == NAND_MFR_AMD ||
3303 maf_id == NAND_MFR_MACRONIX)) ||
3304 (mtd->writesize == 2048 &&
3305 maf_id == NAND_MFR_MICRON))
3306 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3307}
3308
ec6e87e3
HS		 3309static inline bool is_full_id_nand(struct nand_flash_dev *type)
3310{
3311 return type->id_len;
3312}
3313
3314static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3315 struct nand_flash_dev *type, u8 *id_data, int *busw)
3316{
3317 if (!strncmp(type->id, id_data, type->id_len)) {
3318 mtd->writesize = type->pagesize;
3319 mtd->erasesize = type->erasesize;
3320 mtd->oobsize = type->oobsize;
3321
7db906b7 3322 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
ec6e87e3
HS		 3323 chip->chipsize = (uint64_t)type->chipsize << 20;
3324 chip->options |= type->options;
57219342
HS		 3325 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3326 chip->ecc_step_ds = NAND_ECC_STEP(type);
ec6e87e3
HS		 3327
3328 *busw = type->options & NAND_BUSWIDTH_16;
3329
092b6a1d
CZ		 3330 if (!mtd->name)
3331 mtd->name = type->name;
3332
ec6e87e3
HS		 3333 return true;
3334 }
3335 return false;
3336}
3337
7aa65bfd 3338/*
8b6e50c9 3339 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3340 */
3341static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3342 struct nand_chip *chip,
7351d3a5
FF		 3343 int busw,
3344 int *maf_id, int *dev_id,
5e81e88a 3345 struct nand_flash_dev *type)
7aa65bfd 3346{
d1e1f4e4 3347 int i, maf_idx;
426c457a 3348 u8 id_data[8];
1da177e4
LT		 3349
3350 /* Select the device */
ace4dfee 3351 chip->select_chip(mtd, 0);
1da177e4 3352
ef89a880
KB		 3353 /*
3354 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3355 * after power-up.
ef89a880
KB		 3356 */
3357 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3358
1da177e4 3359 /* Send the command for reading device ID */
ace4dfee 3360 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3361
3362 /* Read manufacturer and device IDs */
ace4dfee 3363 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3364 *dev_id = chip->read_byte(mtd);
1da177e4 3365
8b6e50c9
BN		 3366 /*
3367 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3368 * interface concerns can cause random data which looks like a
3369 * possibly credible NAND flash to appear. If the two results do
3370 * not match, ignore the device completely.
3371 */
3372
3373 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3374
4aef9b78
BN		 3375 /* Read entire ID string */
3376 for (i = 0; i < 8; i++)
426c457a 3377 id_data[i] = chip->read_byte(mtd);
ed8165c7 3378
d1e1f4e4 3379 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
20171642 3380 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
d0370219 3381 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3382 return ERR_PTR(-ENODEV);
3383 }
3384
7aa65bfd 3385 if (!type)
5e81e88a
DW		 3386 type = nand_flash_ids;
3387
ec6e87e3
HS		 3388 for (; type->name != NULL; type++) {
3389 if (is_full_id_nand(type)) {
3390 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3391 goto ident_done;
3392 } else if (*dev_id == type->dev_id) {
3393 break;
3394 }
3395 }
5e81e88a 3396
d1e1f4e4
FF		 3397 chip->onfi_version = 0;
3398 if (!type->name || !type->pagesize) {
6fb277ba 3399 /* Check is chip is ONFI compliant */
47450b35 3400 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3401 goto ident_done;
d1e1f4e4
FF		 3402 }
3403
5e81e88a 3404 if (!type->name)
7aa65bfd
TG		 3405 return ERR_PTR(-ENODEV);
3406
ba0251fe
TG		 3407 if (!mtd->name)
3408 mtd->name = type->name;
3409
69423d99 3410 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3411
12a40a57 3412 if (!type->pagesize && chip->init_size) {
8b6e50c9 3413 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3414 busw = chip->init_size(mtd, chip, id_data);
3415 } else if (!type->pagesize) {
fc09bbc0
BN		 3416 /* Decode parameters from extended ID */
3417 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3418 } else {
f23a481c 3419 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3420 }
bf7a01bf
BN		 3421 /* Get chip options */
3422 chip->options |= type->options;
d1e1f4e4 3423
8b6e50c9
BN		 3424 /*
3425 * Check if chip is not a Samsung device. Do not clear the
3426 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3427 */
3428 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3429 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3430ident_done:
3431
7aa65bfd 3432 /* Try to identify manufacturer */
9a909867 3433 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3434 if (nand_manuf_ids[maf_idx].id == *maf_id)
3435 break;
3436 }
0ea4a755 3437
64b37b2a
MC		 3438 if (chip->options & NAND_BUSWIDTH_AUTO) {
3439 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3440 chip->options |= busw;
3441 nand_set_defaults(chip, busw);
3442 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3443 /*
3444 * Check, if buswidth is correct. Hardware drivers should set
3445 * chip correct!
3446 */
20171642
EG		 3447 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3448 *maf_id, *dev_id);
3449 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3450 pr_warn("bus width %d instead %d bit\n",
d0370219
BN		 3451 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3452 busw ? 16 : 8);
7aa65bfd
TG		 3453 return ERR_PTR(-EINVAL);
3454 }
61b03bd7 3455
7e74c2d7
BN		 3456 nand_decode_bbm_options(mtd, chip, id_data);
3457
7aa65bfd 3458 /* Calculate the address shift from the page size */
ace4dfee 3459 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3460 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3461 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3462
ace4dfee 3463 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3464 ffs(mtd->erasesize) - 1;
69423d99
AH		 3465 if (chip->chipsize & 0xffffffff)
3466 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3467 else {
3468 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3469 chip->chip_shift += 32 - 1;
3470 }
1da177e4 3471
26d9be11 3472 chip->badblockbits = 8;
14c65786 3473 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3474
8b6e50c9 3475 /* Do not replace user supplied command function! */
ace4dfee
TG		 3476 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3477 chip->cmdfunc = nand_command_lp;
7aa65bfd 3478
20171642
EG		 3479 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3480 *maf_id, *dev_id);
3481 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3723e93c 3482 chip->onfi_version ? chip->onfi_params.model : type->name);
20171642 3483 pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3723e93c
HS		 3484 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3485 mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3486 return type;
3487}
3488
7aa65bfd 3489/**
3b85c321 3490 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3491 * @mtd: MTD device structure
3492 * @maxchips: number of chips to scan for
3493 * @table: alternative NAND ID table
7aa65bfd 3494 *
8b6e50c9
BN		 3495 * This is the first phase of the normal nand_scan() function. It reads the
3496 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3497 *
3b85c321 3498 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3499 */
5e81e88a
DW		 3500int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3501 struct nand_flash_dev *table)
7aa65bfd 3502{
d1e1f4e4 3503 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3504 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3505 struct nand_flash_dev *type;
3506
7aa65bfd 3507 /* Get buswidth to select the correct functions */
ace4dfee 3508 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3509 /* Set the default functions */
ace4dfee 3510 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3511
3512 /* Read the flash type */
7351d3a5
FF		 3513 type = nand_get_flash_type(mtd, chip, busw,
3514 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3515
3516 if (IS_ERR(type)) {
b1c6e6db 3517 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3518 pr_warn("No NAND device found\n");
ace4dfee 3519 chip->select_chip(mtd, -1);
7aa65bfd 3520 return PTR_ERR(type);
1da177e4
LT		 3521 }
3522
07300164
HS		 3523 chip->select_chip(mtd, -1);
3524
7aa65bfd 3525 /* Check for a chip array */
e0c7d767 3526 for (i = 1; i < maxchips; i++) {
ace4dfee 3527 chip->select_chip(mtd, i);
ef89a880
KB		 3528 /* See comment in nand_get_flash_type for reset */
3529 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3530 /* Send the command for reading device ID */
ace4dfee 3531 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3532 /* Read manufacturer and device IDs */
ace4dfee 3533 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 3534 nand_dev_id != chip->read_byte(mtd)) {
3535 chip->select_chip(mtd, -1);
1da177e4 3536 break;
07300164
HS		 3537 }
3538 chip->select_chip(mtd, -1);
1da177e4
LT		 3539 }
3540 if (i > 1)
20171642 3541 pr_info("%d chips detected\n", i);
61b03bd7 3542
1da177e4 3543 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3544 chip->numchips = i;
3545 mtd->size = i * chip->chipsize;
7aa65bfd 3546
3b85c321
DW		 3547 return 0;
3548}
7351d3a5 3549EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3550
3551
3552/**
3553 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3554 * @mtd: MTD device structure
3b85c321 3555 *
8b6e50c9
BN		 3556 * This is the second phase of the normal nand_scan() function. It fills out
3557 * all the uninitialized function pointers with the defaults and scans for a
3558 * bad block table if appropriate.
3b85c321
DW		 3559 */
3560int nand_scan_tail(struct mtd_info *mtd)
3561{
3562 int i;
3563 struct nand_chip *chip = mtd->priv;
97de79e0 3564 struct nand_ecc_ctrl *ecc = &chip->ecc;
3b85c321 3565
e2414f4c
BN		 3566 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3567 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3568 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3569
4bf63fcb
DW		 3570 if (!(chip->options & NAND_OWN_BUFFERS))
3571 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3572 if (!chip->buffers)
3573 return -ENOMEM;
3574
7dcdcbef 3575 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3576 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3577
7aa65bfd 3578 /*
8b6e50c9 3579 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3580 */
97de79e0 3581 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3582 switch (mtd->oobsize) {
1da177e4 3583 case 8:
97de79e0 3584 ecc->layout = &nand_oob_8;
1da177e4
LT		 3585 break;
3586 case 16:
97de79e0 3587 ecc->layout = &nand_oob_16;
1da177e4
LT		 3588 break;
3589 case 64:
97de79e0 3590 ecc->layout = &nand_oob_64;
1da177e4 3591 break;
81ec5364 3592 case 128:
97de79e0 3593 ecc->layout = &nand_oob_128;
81ec5364 3594 break;
1da177e4 3595 default:
d0370219
BN		 3596 pr_warn("No oob scheme defined for oobsize %d\n",
3597 mtd->oobsize);
1da177e4
LT		 3598 BUG();
3599 }
3600 }
61b03bd7 3601
956e944c
DW		 3602 if (!chip->write_page)
3603 chip->write_page = nand_write_page;
3604
61b03bd7 3605 /*
8b6e50c9 3606 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3607 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3608 */
956e944c 3609
97de79e0 3610 switch (ecc->mode) {
6e0cb135
SN		 3611 case NAND_ECC_HW_OOB_FIRST:
3612 /* Similar to NAND_ECC_HW, but a separate read_page handle */
97de79e0 3613 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
9a4d4d69 3614 pr_warn("No ECC functions supplied; "
d0370219 3615 "hardware ECC not possible\n");
6e0cb135
SN		 3616 BUG();
3617 }
97de79e0
HS		 3618 if (!ecc->read_page)
3619 ecc->read_page = nand_read_page_hwecc_oob_first;
6e0cb135 3620
6dfc6d25 3621 case NAND_ECC_HW:
8b6e50c9 3622 /* Use standard hwecc read page function? */
97de79e0
HS		 3623 if (!ecc->read_page)
3624 ecc->read_page = nand_read_page_hwecc;
3625 if (!ecc->write_page)
3626 ecc->write_page = nand_write_page_hwecc;
3627 if (!ecc->read_page_raw)
3628 ecc->read_page_raw = nand_read_page_raw;
3629 if (!ecc->write_page_raw)
3630 ecc->write_page_raw = nand_write_page_raw;
3631 if (!ecc->read_oob)
3632 ecc->read_oob = nand_read_oob_std;
3633 if (!ecc->write_oob)
3634 ecc->write_oob = nand_write_oob_std;
3635 if (!ecc->read_subpage)
3636 ecc->read_subpage = nand_read_subpage;
3637 if (!ecc->write_subpage)
3638 ecc->write_subpage = nand_write_subpage_hwecc;
f5bbdacc 3639
6dfc6d25 3640 case NAND_ECC_HW_SYNDROME:
97de79e0
HS		 3641 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
3642 (!ecc->read_page ||
3643 ecc->read_page == nand_read_page_hwecc ||
3644 !ecc->write_page ||
3645 ecc->write_page == nand_write_page_hwecc)) {
9a4d4d69 3646 pr_warn("No ECC functions supplied; "
d0370219 3647 "hardware ECC not possible\n");
6dfc6d25
TG		 3648 BUG();
3649 }
8b6e50c9 3650 /* Use standard syndrome read/write page function? */
97de79e0
HS		 3651 if (!ecc->read_page)
3652 ecc->read_page = nand_read_page_syndrome;
3653 if (!ecc->write_page)
3654 ecc->write_page = nand_write_page_syndrome;
3655 if (!ecc->read_page_raw)
3656 ecc->read_page_raw = nand_read_page_raw_syndrome;
3657 if (!ecc->write_page_raw)
3658 ecc->write_page_raw = nand_write_page_raw_syndrome;
3659 if (!ecc->read_oob)
3660 ecc->read_oob = nand_read_oob_syndrome;
3661 if (!ecc->write_oob)
3662 ecc->write_oob = nand_write_oob_syndrome;
3663
3664 if (mtd->writesize >= ecc->size) {
3665 if (!ecc->strength) {
e2788c98
MD		 3666 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3667 BUG();
3668 }
6dfc6d25 3669 break;
e2788c98 3670 }
9a4d4d69 3671 pr_warn("%d byte HW ECC not possible on "
d0370219 3672 "%d byte page size, fallback to SW ECC\n",
97de79e0
HS		 3673 ecc->size, mtd->writesize);
3674 ecc->mode = NAND_ECC_SOFT;
61b03bd7 3675
6dfc6d25 3676 case NAND_ECC_SOFT:
97de79e0
HS		 3677 ecc->calculate = nand_calculate_ecc;
3678 ecc->correct = nand_correct_data;
3679 ecc->read_page = nand_read_page_swecc;
3680 ecc->read_subpage = nand_read_subpage;
3681 ecc->write_page = nand_write_page_swecc;
3682 ecc->read_page_raw = nand_read_page_raw;
3683 ecc->write_page_raw = nand_write_page_raw;
3684 ecc->read_oob = nand_read_oob_std;
3685 ecc->write_oob = nand_write_oob_std;
3686 if (!ecc->size)
3687 ecc->size = 256;
3688 ecc->bytes = 3;
3689 ecc->strength = 1;
1da177e4 3690 break;
61b03bd7 3691
193bd400
ID		 3692 case NAND_ECC_SOFT_BCH:
3693 if (!mtd_nand_has_bch()) {
9a4d4d69 3694 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3695 BUG();
3696 }
97de79e0
HS		 3697 ecc->calculate = nand_bch_calculate_ecc;
3698 ecc->correct = nand_bch_correct_data;
3699 ecc->read_page = nand_read_page_swecc;
3700 ecc->read_subpage = nand_read_subpage;
3701 ecc->write_page = nand_write_page_swecc;
3702 ecc->read_page_raw = nand_read_page_raw;
3703 ecc->write_page_raw = nand_write_page_raw;
3704 ecc->read_oob = nand_read_oob_std;
3705 ecc->write_oob = nand_write_oob_std;
193bd400
ID		 3706 /*
3707 * Board driver should supply ecc.size and ecc.bytes values to
3708 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3709 * for details. Otherwise, default to 4 bits for large page
3710 * devices.
193bd400 3711 */
97de79e0
HS		 3712 if (!ecc->size && (mtd->oobsize >= 64)) {
3713 ecc->size = 512;
3714 ecc->bytes = 7;
193bd400 3715 }
97de79e0
HS		 3716 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
3717 &ecc->layout);
3718 if (!ecc->priv) {
9a4d4d69 3719 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3720 BUG();
3721 }
97de79e0 3722 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
193bd400
ID		 3723 break;
3724
61b03bd7 3725 case NAND_ECC_NONE:
9a4d4d69 3726 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3727 "This is not recommended!\n");
97de79e0
HS		 3728 ecc->read_page = nand_read_page_raw;
3729 ecc->write_page = nand_write_page_raw;
3730 ecc->read_oob = nand_read_oob_std;
3731 ecc->read_page_raw = nand_read_page_raw;
3732 ecc->write_page_raw = nand_write_page_raw;
3733 ecc->write_oob = nand_write_oob_std;
3734 ecc->size = mtd->writesize;
3735 ecc->bytes = 0;
3736 ecc->strength = 0;
1da177e4 3737 break;
956e944c 3738
1da177e4 3739 default:
97de79e0 3740 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
61b03bd7 3741 BUG();
1da177e4 3742 }
61b03bd7 3743
9ce244b3 3744 /* For many systems, the standard OOB write also works for raw */
97de79e0
HS		 3745 if (!ecc->read_oob_raw)
3746 ecc->read_oob_raw = ecc->read_oob;
3747 if (!ecc->write_oob_raw)
3748 ecc->write_oob_raw = ecc->write_oob;
9ce244b3 3749
5bd34c09
TG		 3750 /*
3751 * The number of bytes available for a client to place data into
8b6e50c9 3752 * the out of band area.
5bd34c09 3753 */
97de79e0
HS		 3754 ecc->layout->oobavail = 0;
3755 for (i = 0; ecc->layout->oobfree[i].length
3756 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
3757 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
3758 mtd->oobavail = ecc->layout->oobavail;
5bd34c09 3759
7aa65bfd
TG		 3760 /*
3761 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3762 * mode.
7aa65bfd 3763 */
97de79e0
HS		 3764 ecc->steps = mtd->writesize / ecc->size;
3765 if (ecc->steps * ecc->size != mtd->writesize) {
9a4d4d69 3766 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3767 BUG();
1da177e4 3768 }
97de79e0 3769 ecc->total = ecc->steps * ecc->bytes;
61b03bd7 3770
8b6e50c9 3771 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
1d0ed69d 3772 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
97de79e0 3773 switch (ecc->steps) {
29072b96
TG		 3774 case 2:
3775 mtd->subpage_sft = 1;
3776 break;
3777 case 4:
3778 case 8:
81ec5364 3779 case 16:
29072b96
TG		 3780 mtd->subpage_sft = 2;
3781 break;
3782 }
3783 }
3784 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3785
04bbd0ea 3786 /* Initialize state */
ace4dfee 3787 chip->state = FL_READY;
1da177e4 3788
1da177e4 3789 /* Invalidate the pagebuffer reference */
ace4dfee 3790 chip->pagebuf = -1;
1da177e4 3791
a5ff4f10 3792 /* Large page NAND with SOFT_ECC should support subpage reads */
97de79e0 3793 if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
a5ff4f10
JW		 3794 chip->options |= NAND_SUBPAGE_READ;
3795
1da177e4 3796 /* Fill in remaining MTD driver data */
963d1c28 3797 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
93edbad6
ML		 3798 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3799 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 3800 mtd->_erase = nand_erase;
3801 mtd->_point = NULL;
3802 mtd->_unpoint = NULL;
3803 mtd->_read = nand_read;
3804 mtd->_write = nand_write;
3805 mtd->_panic_write = panic_nand_write;
3806 mtd->_read_oob = nand_read_oob;
3807 mtd->_write_oob = nand_write_oob;
3808 mtd->_sync = nand_sync;
3809 mtd->_lock = NULL;
3810 mtd->_unlock = NULL;
3811 mtd->_suspend = nand_suspend;
3812 mtd->_resume = nand_resume;
3813 mtd->_block_isbad = nand_block_isbad;
3814 mtd->_block_markbad = nand_block_markbad;
cbcab65a 3815 mtd->writebufsize = mtd->writesize;
1da177e4 3816
6a918bad 3817 /* propagate ecc info to mtd_info */
97de79e0
HS		 3818 mtd->ecclayout = ecc->layout;
3819 mtd->ecc_strength = ecc->strength;
3820 mtd->ecc_step_size = ecc->size;
ea3b2ea2
SL		 3821 /*
3822 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3823 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3824 * properly set.
3825 */
3826 if (!mtd->bitflip_threshold)
3827 mtd->bitflip_threshold = mtd->ecc_strength;
1da177e4 3828
0040bf38 3829 /* Check, if we should skip the bad block table scan */
ace4dfee 3830 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3831 return 0;
1da177e4
LT		 3832
3833 /* Build bad block table */
ace4dfee 3834 return chip->scan_bbt(mtd);
1da177e4 3835}
7351d3a5 3836EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3837
8b6e50c9
BN		 3838/*
3839 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3840 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3841 * to call us from in-kernel code if the core NAND support is modular.
3842 */
3b85c321
DW		 3843#ifdef MODULE
3844#define caller_is_module() (1)
3845#else
3846#define caller_is_module() \
a6e6abd5 3847 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3848#endif
3849
3850/**
3851 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3852 * @mtd: MTD device structure
3853 * @maxchips: number of chips to scan for
3b85c321 3854 *
8b6e50c9
BN		 3855 * This fills out all the uninitialized function pointers with the defaults.
3856 * The flash ID is read and the mtd/chip structures are filled with the
3857 * appropriate values. The mtd->owner field must be set to the module of the
3858 * caller.
3b85c321
DW		 3859 */
3860int nand_scan(struct mtd_info *mtd, int maxchips)
3861{
3862 int ret;
3863
3864 /* Many callers got this wrong, so check for it for a while... */
3865 if (!mtd->owner && caller_is_module()) {
d0370219 3866 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3867 BUG();
3868 }
3869
5e81e88a 3870 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3871 if (!ret)
3872 ret = nand_scan_tail(mtd);
3873 return ret;
3874}
7351d3a5 3875EXPORT_SYMBOL(nand_scan);
3b85c321 3876
1da177e4 3877/**
61b03bd7 3878 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3879 * @mtd: MTD device structure
3880 */
e0c7d767 3881void nand_release(struct mtd_info *mtd)
1da177e4 3882{
ace4dfee 3883 struct nand_chip *chip = mtd->priv;
1da177e4 3884
193bd400
ID		 3885 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3886 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3887
5ffcaf3d 3888 mtd_device_unregister(mtd);
1da177e4 3889
fa671646 3890 /* Free bad block table memory */
ace4dfee 3891 kfree(chip->bbt);
4bf63fcb
DW		 3892 if (!(chip->options & NAND_OWN_BUFFERS))
3893 kfree(chip->buffers);
58373ff0
BN		 3894
3895 /* Free bad block descriptor memory */
3896 if (chip->badblock_pattern && chip->badblock_pattern->options
3897 & NAND_BBT_DYNAMICSTRUCT)
3898 kfree(chip->badblock_pattern);
1da177e4 3899}
e0c7d767 3900EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3901
3902static int __init nand_base_init(void)
3903{
3904 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3905 return 0;
3906}
3907
3908static void __exit nand_base_exit(void)
3909{
3910 led_trigger_unregister_simple(nand_led_trigger);
3911}
3912
3913module_init(nand_base_init);
3914module_exit(nand_base_exit);
3915
e0c7d767 3916MODULE_LICENSE("GPL");
7351d3a5
FF		 3917MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3918MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3919MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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