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mtd: replace DEBUG() with pr_debug()
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 24 * if we have HW ECC support.
1da177e4
LT		 25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4 50#include <linux/mtd/partitions.h>
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
ace4dfee 96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 97 int new_state);
1da177e4 98
8593fbc6
TG		 99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
d470a97c 102/*
8e87d782 103 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
6fe5a6ac
VS		 108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 116 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 122 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 123 ret = -EINVAL;
124 }
125
126 /* Do not allow past end of device */
127 if (ofs + len > mtd->size) {
289c0522 128 pr_debug("%s: past end of device\n", __func__);
6fe5a6ac
VS		 129 ret = -EINVAL;
130 }
131
132 return ret;
133}
134
1da177e4
LT		 135/**
136 * nand_release_device - [GENERIC] release chip
8b6e50c9 137 * @mtd: MTD device structure
61b03bd7 138 *
8b6e50c9 139 * Deselect, release chip lock and wake up anyone waiting on the device.
1da177e4 140 */
e0c7d767 141static void nand_release_device(struct mtd_info *mtd)
1da177e4 142{
ace4dfee 143 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 144
145 /* De-select the NAND device */
ace4dfee 146 chip->select_chip(mtd, -1);
0dfc6246 147
a36ed299 148 /* Release the controller and the chip */
ace4dfee
TG		 149 spin_lock(&chip->controller->lock);
150 chip->controller->active = NULL;
151 chip->state = FL_READY;
152 wake_up(&chip->controller->wq);
153 spin_unlock(&chip->controller->lock);
1da177e4
LT		 154}
155
156/**
157 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 158 * @mtd: MTD device structure
1da177e4 159 *
7854d3f7 160 * Default read function for 8bit buswidth
1da177e4 161 */
58dd8f2b 162static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 163{
ace4dfee
TG		 164 struct nand_chip *chip = mtd->priv;
165 return readb(chip->IO_ADDR_R);
1da177e4
LT		 166}
167
1da177e4
LT		 168/**
169 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
7854d3f7 170 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 171 * @mtd: MTD device structure
1da177e4 172 *
7854d3f7
BN		 173 * Default read function for 16bit buswidth with endianness conversion.
174 *
1da177e4 175 */
58dd8f2b 176static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 177{
ace4dfee
TG		 178 struct nand_chip *chip = mtd->priv;
179 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 180}
181
1da177e4
LT		 182/**
183 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 184 * @mtd: MTD device structure
1da177e4 185 *
7854d3f7 186 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 187 */
188static u16 nand_read_word(struct mtd_info *mtd)
189{
ace4dfee
TG		 190 struct nand_chip *chip = mtd->priv;
191 return readw(chip->IO_ADDR_R);
1da177e4
LT		 192}
193
1da177e4
LT		 194/**
195 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 196 * @mtd: MTD device structure
197 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 198 *
199 * Default select function for 1 chip devices.
200 */
ace4dfee 201static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 202{
ace4dfee
TG		 203 struct nand_chip *chip = mtd->priv;
204
205 switch (chipnr) {
1da177e4 206 case -1:
ace4dfee 207 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 208 break;
209 case 0:
1da177e4
LT		 210 break;
211
212 default:
213 BUG();
214 }
215}
216
217/**
218 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 219 * @mtd: MTD device structure
220 * @buf: data buffer
221 * @len: number of bytes to write
1da177e4 222 *
7854d3f7 223 * Default write function for 8bit buswidth.
1da177e4 224 */
58dd8f2b 225static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 226{
227 int i;
ace4dfee 228 struct nand_chip *chip = mtd->priv;
1da177e4 229
e0c7d767 230 for (i = 0; i < len; i++)
ace4dfee 231 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 232}
233
234/**
61b03bd7 235 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 236 * @mtd: MTD device structure
237 * @buf: buffer to store date
238 * @len: number of bytes to read
1da177e4 239 *
7854d3f7 240 * Default read function for 8bit buswidth.
1da177e4 241 */
58dd8f2b 242static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 243{
244 int i;
ace4dfee 245 struct nand_chip *chip = mtd->priv;
1da177e4 246
e0c7d767 247 for (i = 0; i < len; i++)
ace4dfee 248 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 249}
250
251/**
61b03bd7 252 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 253 * @mtd: MTD device structure
254 * @buf: buffer containing the data to compare
255 * @len: number of bytes to compare
1da177e4 256 *
7854d3f7 257 * Default verify function for 8bit buswidth.
1da177e4 258 */
58dd8f2b 259static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 260{
261 int i;
ace4dfee 262 struct nand_chip *chip = mtd->priv;
1da177e4 263
e0c7d767 264 for (i = 0; i < len; i++)
ace4dfee 265 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 266 return -EFAULT;
1da177e4
LT		 267 return 0;
268}
269
270/**
271 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 272 * @mtd: MTD device structure
273 * @buf: data buffer
274 * @len: number of bytes to write
1da177e4 275 *
7854d3f7 276 * Default write function for 16bit buswidth.
1da177e4 277 */
58dd8f2b 278static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 279{
280 int i;
ace4dfee 281 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 282 u16 *p = (u16 *) buf;
283 len >>= 1;
61b03bd7 284
e0c7d767 285 for (i = 0; i < len; i++)
ace4dfee 286 writew(p[i], chip->IO_ADDR_W);
61b03bd7 287
1da177e4
LT		 288}
289
290/**
61b03bd7 291 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 292 * @mtd: MTD device structure
293 * @buf: buffer to store date
294 * @len: number of bytes to read
1da177e4 295 *
7854d3f7 296 * Default read function for 16bit buswidth.
1da177e4 297 */
58dd8f2b 298static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 299{
300 int i;
ace4dfee 301 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 302 u16 *p = (u16 *) buf;
303 len >>= 1;
304
e0c7d767 305 for (i = 0; i < len; i++)
ace4dfee 306 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 307}
308
309/**
61b03bd7 310 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 311 * @mtd: MTD device structure
312 * @buf: buffer containing the data to compare
313 * @len: number of bytes to compare
1da177e4 314 *
7854d3f7 315 * Default verify function for 16bit buswidth.
1da177e4 316 */
58dd8f2b 317static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 318{
319 int i;
ace4dfee 320 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 321 u16 *p = (u16 *) buf;
322 len >>= 1;
323
e0c7d767 324 for (i = 0; i < len; i++)
ace4dfee 325 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 326 return -EFAULT;
327
328 return 0;
329}
330
331/**
332 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 333 * @mtd: MTD device structure
334 * @ofs: offset from device start
335 * @getchip: 0, if the chip is already selected
1da177e4 336 *
61b03bd7 337 * Check, if the block is bad.
1da177e4
LT		 338 */
339static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
340{
341 int page, chipnr, res = 0;
ace4dfee 342 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 343 u16 bad;
344
5fb1549d 345 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 346 ofs += mtd->erasesize - mtd->writesize;
347
1a12f46a
TK		 348 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
349
1da177e4 350 if (getchip) {
ace4dfee 351 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 352
ace4dfee 353 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 354
355 /* Select the NAND device */
ace4dfee 356 chip->select_chip(mtd, chipnr);
1a12f46a 357 }
1da177e4 358
ace4dfee
TG		 359 if (chip->options & NAND_BUSWIDTH_16) {
360 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 361 page);
ace4dfee
TG		 362 bad = cpu_to_le16(chip->read_word(mtd));
363 if (chip->badblockpos & 0x1)
49196f33 364 bad >>= 8;
e0b58d0a
ML		 365 else
366 bad &= 0xFF;
1da177e4 367 } else {
1a12f46a 368 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
e0b58d0a 369 bad = chip->read_byte(mtd);
1da177e4 370 }
61b03bd7 371
e0b58d0a
ML		 372 if (likely(chip->badblockbits == 8))
373 res = bad != 0xFF;
374 else
375 res = hweight8(bad) < chip->badblockbits;
376
ace4dfee 377 if (getchip)
1da177e4 378 nand_release_device(mtd);
61b03bd7 379
1da177e4
LT		 380 return res;
381}
382
383/**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 385 * @mtd: MTD device structure
386 * @ofs: offset from device start
1da177e4 387 *
8b6e50c9
BN		 388 * This is the default implementation, which can be overridden by a hardware
389 * specific driver.
1da177e4
LT		 390*/
391static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
392{
ace4dfee 393 struct nand_chip *chip = mtd->priv;
58dd8f2b 394 uint8_t buf[2] = { 0, 0 };
02ed70bb 395 int block, ret, i = 0;
61b03bd7 396
5fb1549d 397 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 398 ofs += mtd->erasesize - mtd->writesize;
399
1da177e4 400 /* Get block number */
4226b510 401 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 402 if (chip->bbt)
403 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 404
8b6e50c9 405 /* Do we have a flash based bad block table? */
bb9ebd4e 406 if (chip->bbt_options & NAND_BBT_USE_FLASH)
f1a28c02
TG		 407 ret = nand_update_bbt(mtd, ofs);
408 else {
c0b8ba7b 409 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 410
a0dc5529
BN		 411 /*
412 * Write to first two pages if necessary. If we write to more
413 * than one location, the first error encountered quits the
414 * procedure. We write two bytes per location, so we dont have
415 * to mess with 16 bit access.
02ed70bb
BN		 416 */
417 do {
418 chip->ops.len = chip->ops.ooblen = 2;
419 chip->ops.datbuf = NULL;
420 chip->ops.oobbuf = buf;
421 chip->ops.ooboffs = chip->badblockpos & ~0x01;
422
423 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
424
02ed70bb
BN		 425 i++;
426 ofs += mtd->writesize;
5fb1549d 427 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
02ed70bb
BN		 428 i < 2);
429
c0b8ba7b 430 nand_release_device(mtd);
f1a28c02
TG		 431 }
432 if (!ret)
433 mtd->ecc_stats.badblocks++;
c0b8ba7b 434
f1a28c02 435 return ret;
1da177e4
LT		 436}
437
61b03bd7 438/**
1da177e4 439 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 440 * @mtd: MTD device structure
1da177e4 441 *
8b6e50c9
BN		 442 * Check, if the device is write protected. The function expects, that the
443 * device is already selected.
1da177e4 444 */
e0c7d767 445static int nand_check_wp(struct mtd_info *mtd)
1da177e4 446{
ace4dfee 447 struct nand_chip *chip = mtd->priv;
93edbad6 448
8b6e50c9 449 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 450 if (chip->options & NAND_BROKEN_XD)
451 return 0;
452
1da177e4 453 /* Check the WP bit */
ace4dfee
TG		 454 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
455 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 456}
457
458/**
459 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 460 * @mtd: MTD device structure
461 * @ofs: offset from device start
462 * @getchip: 0, if the chip is already selected
463 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 464 *
465 * Check, if the block is bad. Either by reading the bad block table or
466 * calling of the scan function.
467 */
2c0a2bed
TG		 468static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
469 int allowbbt)
1da177e4 470{
ace4dfee 471 struct nand_chip *chip = mtd->priv;
61b03bd7 472
ace4dfee
TG		 473 if (!chip->bbt)
474 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 475
1da177e4 476 /* Return info from the table */
e0c7d767 477 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 478}
479
2af7c653
SK		 480/**
481 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 482 * @mtd: MTD device structure
483 * @timeo: Timeout
2af7c653
SK		 484 *
485 * Helper function for nand_wait_ready used when needing to wait in interrupt
486 * context.
487 */
488static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
489{
490 struct nand_chip *chip = mtd->priv;
491 int i;
492
493 /* Wait for the device to get ready */
494 for (i = 0; i < timeo; i++) {
495 if (chip->dev_ready(mtd))
496 break;
497 touch_softlockup_watchdog();
498 mdelay(1);
499 }
500}
501
7854d3f7 502/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 503void nand_wait_ready(struct mtd_info *mtd)
3b88775c 504{
ace4dfee 505 struct nand_chip *chip = mtd->priv;
e0c7d767 506 unsigned long timeo = jiffies + 2;
3b88775c 507
2af7c653
SK		 508 /* 400ms timeout */
509 if (in_interrupt() || oops_in_progress)
510 return panic_nand_wait_ready(mtd, 400);
511
8fe833c1 512 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 513 /* Wait until command is processed or timeout occurs */
3b88775c 514 do {
ace4dfee 515 if (chip->dev_ready(mtd))
8fe833c1 516 break;
8446f1d3 517 touch_softlockup_watchdog();
61b03bd7 518 } while (time_before(jiffies, timeo));
8fe833c1 519 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 520}
4b648b02 521EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 522
1da177e4
LT		 523/**
524 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 525 * @mtd: MTD device structure
526 * @command: the command to be sent
527 * @column: the column address for this command, -1 if none
528 * @page_addr: the page address for this command, -1 if none
1da177e4 529 *
8b6e50c9
BN		 530 * Send command to NAND device. This function is used for small page devices
531 * (256/512 Bytes per page).
1da177e4 532 */
7abd3ef9
TG		 533static void nand_command(struct mtd_info *mtd, unsigned int command,
534 int column, int page_addr)
1da177e4 535{
ace4dfee 536 register struct nand_chip *chip = mtd->priv;
7abd3ef9 537 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 538
8b6e50c9 539 /* Write out the command to the device */
1da177e4
LT		 540 if (command == NAND_CMD_SEQIN) {
541 int readcmd;
542
28318776 543 if (column >= mtd->writesize) {
1da177e4 544 /* OOB area */
28318776 545 column -= mtd->writesize;
1da177e4
LT		 546 readcmd = NAND_CMD_READOOB;
547 } else if (column < 256) {
548 /* First 256 bytes --> READ0 */
549 readcmd = NAND_CMD_READ0;
550 } else {
551 column -= 256;
552 readcmd = NAND_CMD_READ1;
553 }
ace4dfee 554 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 555 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 556 }
ace4dfee 557 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 558
8b6e50c9 559 /* Address cycle, when necessary */
7abd3ef9
TG		 560 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
561 /* Serially input address */
562 if (column != -1) {
563 /* Adjust columns for 16 bit buswidth */
ace4dfee 564 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 565 column >>= 1;
ace4dfee 566 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 567 ctrl &= ~NAND_CTRL_CHANGE;
568 }
569 if (page_addr != -1) {
ace4dfee 570 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 571 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 572 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 573 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 574 if (chip->chipsize > (32 << 20))
575 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 576 }
ace4dfee 577 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 578
579 /*
8b6e50c9
BN		 580 * Program and erase have their own busy handlers status and sequential
581 * in needs no delay
e0c7d767 582 */
1da177e4 583 switch (command) {
61b03bd7 584
1da177e4
LT		 585 case NAND_CMD_PAGEPROG:
586 case NAND_CMD_ERASE1:
587 case NAND_CMD_ERASE2:
588 case NAND_CMD_SEQIN:
589 case NAND_CMD_STATUS:
590 return;
591
592 case NAND_CMD_RESET:
ace4dfee 593 if (chip->dev_ready)
1da177e4 594 break;
ace4dfee
TG		 595 udelay(chip->chip_delay);
596 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 597 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 598 chip->cmd_ctrl(mtd,
599 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 600 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
601 ;
1da177e4
LT		 602 return;
603
e0c7d767 604 /* This applies to read commands */
1da177e4 605 default:
61b03bd7 606 /*
1da177e4
LT		 607 * If we don't have access to the busy pin, we apply the given
608 * command delay
e0c7d767 609 */
ace4dfee
TG		 610 if (!chip->dev_ready) {
611 udelay(chip->chip_delay);
1da177e4 612 return;
61b03bd7 613 }
1da177e4 614 }
8b6e50c9
BN		 615 /*
616 * Apply this short delay always to ensure that we do wait tWB in
617 * any case on any machine.
618 */
e0c7d767 619 ndelay(100);
3b88775c
TG		 620
621 nand_wait_ready(mtd);
1da177e4
LT		 622}
623
624/**
625 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 626 * @mtd: MTD device structure
627 * @command: the command to be sent
628 * @column: the column address for this command, -1 if none
629 * @page_addr: the page address for this command, -1 if none
1da177e4 630 *
7abd3ef9 631 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 632 * devices. We don't have the separate regions as we have in the small page
633 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 634 */
7abd3ef9
TG		 635static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
636 int column, int page_addr)
1da177e4 637{
ace4dfee 638 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 639
640 /* Emulate NAND_CMD_READOOB */
641 if (command == NAND_CMD_READOOB) {
28318776 642 column += mtd->writesize;
1da177e4
LT		 643 command = NAND_CMD_READ0;
644 }
61b03bd7 645
7abd3ef9 646 /* Command latch cycle */
ace4dfee 647 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 648 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 649
650 if (column != -1 || page_addr != -1) {
7abd3ef9 651 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 652
653 /* Serially input address */
654 if (column != -1) {
655 /* Adjust columns for 16 bit buswidth */
ace4dfee 656 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 657 column >>= 1;
ace4dfee 658 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 659 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 660 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 661 }
1da177e4 662 if (page_addr != -1) {
ace4dfee
TG		 663 chip->cmd_ctrl(mtd, page_addr, ctrl);
664 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 665 NAND_NCE | NAND_ALE);
1da177e4 666 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 667 if (chip->chipsize > (128 << 20))
668 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 669 NAND_NCE | NAND_ALE);
1da177e4 670 }
1da177e4 671 }
ace4dfee 672 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 673
674 /*
8b6e50c9
BN		 675 * Program and erase have their own busy handlers status, sequential
676 * in, and deplete1 need no delay.
30f464b7 677 */
1da177e4 678 switch (command) {
61b03bd7 679
1da177e4
LT		 680 case NAND_CMD_CACHEDPROG:
681 case NAND_CMD_PAGEPROG:
682 case NAND_CMD_ERASE1:
683 case NAND_CMD_ERASE2:
684 case NAND_CMD_SEQIN:
7bc3312b 685 case NAND_CMD_RNDIN:
1da177e4 686 case NAND_CMD_STATUS:
30f464b7 687 case NAND_CMD_DEPLETE1:
1da177e4
LT		 688 return;
689
30f464b7
DM		 690 case NAND_CMD_STATUS_ERROR:
691 case NAND_CMD_STATUS_ERROR0:
692 case NAND_CMD_STATUS_ERROR1:
693 case NAND_CMD_STATUS_ERROR2:
694 case NAND_CMD_STATUS_ERROR3:
8b6e50c9 695 /* Read error status commands require only a short delay */
ace4dfee 696 udelay(chip->chip_delay);
30f464b7 697 return;
1da177e4
LT		 698
699 case NAND_CMD_RESET:
ace4dfee 700 if (chip->dev_ready)
1da177e4 701 break;
ace4dfee 702 udelay(chip->chip_delay);
12efdde3
TG		 703 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
704 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
705 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
706 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 707 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
708 ;
1da177e4
LT		 709 return;
710
7bc3312b
TG		 711 case NAND_CMD_RNDOUT:
712 /* No ready / busy check necessary */
713 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
714 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
715 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
716 NAND_NCE | NAND_CTRL_CHANGE);
717 return;
718
1da177e4 719 case NAND_CMD_READ0:
12efdde3
TG		 720 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
721 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
722 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
723 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 724
e0c7d767 725 /* This applies to read commands */
1da177e4 726 default:
61b03bd7 727 /*
1da177e4 728 * If we don't have access to the busy pin, we apply the given
8b6e50c9 729 * command delay.
e0c7d767 730 */
ace4dfee
TG		 731 if (!chip->dev_ready) {
732 udelay(chip->chip_delay);
1da177e4 733 return;
61b03bd7 734 }
1da177e4 735 }
3b88775c 736
8b6e50c9
BN		 737 /*
738 * Apply this short delay always to ensure that we do wait tWB in
739 * any case on any machine.
740 */
e0c7d767 741 ndelay(100);
3b88775c
TG		 742
743 nand_wait_ready(mtd);
1da177e4
LT		 744}
745
2af7c653
SK		 746/**
747 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 748 * @chip: the nand chip descriptor
749 * @mtd: MTD device structure
750 * @new_state: the state which is requested
2af7c653
SK		 751 *
752 * Used when in panic, no locks are taken.
753 */
754static void panic_nand_get_device(struct nand_chip *chip,
755 struct mtd_info *mtd, int new_state)
756{
7854d3f7 757 /* Hardware controller shared among independent devices */
2af7c653
SK		 758 chip->controller->active = chip;
759 chip->state = new_state;
760}
761
1da177e4
LT		 762/**
763 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 764 * @chip: the nand chip descriptor
765 * @mtd: MTD device structure
766 * @new_state: the state which is requested
1da177e4
LT		 767 *
768 * Get the device and lock it for exclusive access
769 */
2c0a2bed 770static int
ace4dfee 771nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 772{
ace4dfee
TG		 773 spinlock_t *lock = &chip->controller->lock;
774 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 775 DECLARE_WAITQUEUE(wait, current);
7351d3a5 776retry:
0dfc6246
TG		 777 spin_lock(lock);
778
b8b3ee9a 779 /* Hardware controller shared among independent devices */
ace4dfee
TG		 780 if (!chip->controller->active)
781 chip->controller->active = chip;
a36ed299 782
ace4dfee
TG		 783 if (chip->controller->active == chip && chip->state == FL_READY) {
784 chip->state = new_state;
0dfc6246 785 spin_unlock(lock);
962034f4
VW		 786 return 0;
787 }
788 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 789 if (chip->controller->active->state == FL_PM_SUSPENDED) {
790 chip->state = FL_PM_SUSPENDED;
791 spin_unlock(lock);
792 return 0;
6b0d9a84 793 }
0dfc6246
TG		 794 }
795 set_current_state(TASK_UNINTERRUPTIBLE);
796 add_wait_queue(wq, &wait);
797 spin_unlock(lock);
798 schedule();
799 remove_wait_queue(wq, &wait);
1da177e4
LT		 800 goto retry;
801}
802
2af7c653 803/**
8b6e50c9
BN		 804 * panic_nand_wait - [GENERIC] wait until the command is done
805 * @mtd: MTD device structure
806 * @chip: NAND chip structure
807 * @timeo: timeout
2af7c653
SK		 808 *
809 * Wait for command done. This is a helper function for nand_wait used when
810 * we are in interrupt context. May happen when in panic and trying to write
b595076a 811 * an oops through mtdoops.
2af7c653
SK		 812 */
813static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
814 unsigned long timeo)
815{
816 int i;
817 for (i = 0; i < timeo; i++) {
818 if (chip->dev_ready) {
819 if (chip->dev_ready(mtd))
820 break;
821 } else {
822 if (chip->read_byte(mtd) & NAND_STATUS_READY)
823 break;
824 }
825 mdelay(1);
f8ac0414 826 }
2af7c653
SK		 827}
828
1da177e4 829/**
8b6e50c9
BN		 830 * nand_wait - [DEFAULT] wait until the command is done
831 * @mtd: MTD device structure
832 * @chip: NAND chip structure
1da177e4 833 *
8b6e50c9
BN		 834 * Wait for command done. This applies to erase and program only. Erase can
835 * take up to 400ms and program up to 20ms according to general NAND and
836 * SmartMedia specs.
844d3b42 837 */
7bc3312b 838static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 839{
840
e0c7d767 841 unsigned long timeo = jiffies;
7bc3312b 842 int status, state = chip->state;
61b03bd7 843
1da177e4 844 if (state == FL_ERASING)
e0c7d767 845 timeo += (HZ * 400) / 1000;
1da177e4 846 else
e0c7d767 847 timeo += (HZ * 20) / 1000;
1da177e4 848
8fe833c1
RP		 849 led_trigger_event(nand_led_trigger, LED_FULL);
850
8b6e50c9
BN		 851 /*
852 * Apply this short delay always to ensure that we do wait tWB in any
853 * case on any machine.
854 */
e0c7d767 855 ndelay(100);
1da177e4 856
ace4dfee
TG		 857 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
858 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 859 else
ace4dfee 860 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 861
2af7c653
SK		 862 if (in_interrupt() || oops_in_progress)
863 panic_nand_wait(mtd, chip, timeo);
864 else {
865 while (time_before(jiffies, timeo)) {
866 if (chip->dev_ready) {
867 if (chip->dev_ready(mtd))
868 break;
869 } else {
870 if (chip->read_byte(mtd) & NAND_STATUS_READY)
871 break;
872 }
873 cond_resched();
1da177e4 874 }
1da177e4 875 }
8fe833c1
RP		 876 led_trigger_event(nand_led_trigger, LED_OFF);
877
ace4dfee 878 status = (int)chip->read_byte(mtd);
1da177e4
LT		 879 return status;
880}
881
7d70f334 882/**
b6d676db 883 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 884 * @mtd: mtd info
885 * @ofs: offset to start unlock from
886 * @len: length to unlock
8b6e50c9
BN		 887 * @invert: when = 0, unlock the range of blocks within the lower and
888 * upper boundary address
889 * when = 1, unlock the range of blocks outside the boundaries
890 * of the lower and upper boundary address
7d70f334 891 *
8b6e50c9 892 * Returs unlock status.
7d70f334
VS		 893 */
894static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
895 uint64_t len, int invert)
896{
897 int ret = 0;
898 int status, page;
899 struct nand_chip *chip = mtd->priv;
900
901 /* Submit address of first page to unlock */
902 page = ofs >> chip->page_shift;
903 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
904
905 /* Submit address of last page to unlock */
906 page = (ofs + len) >> chip->page_shift;
907 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
908 (page | invert) & chip->pagemask);
909
910 /* Call wait ready function */
911 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 912 /* See if device thinks it succeeded */
913 if (status & 0x01) {
289c0522 914 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 915 __func__, status);
916 ret = -EIO;
917 }
918
919 return ret;
920}
921
922/**
b6d676db 923 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 924 * @mtd: mtd info
925 * @ofs: offset to start unlock from
926 * @len: length to unlock
7d70f334 927 *
8b6e50c9 928 * Returns unlock status.
7d70f334
VS		 929 */
930int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
931{
932 int ret = 0;
933 int chipnr;
934 struct nand_chip *chip = mtd->priv;
935
289c0522 936 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 937 __func__, (unsigned long long)ofs, len);
938
939 if (check_offs_len(mtd, ofs, len))
940 ret = -EINVAL;
941
942 /* Align to last block address if size addresses end of the device */
943 if (ofs + len == mtd->size)
944 len -= mtd->erasesize;
945
946 nand_get_device(chip, mtd, FL_UNLOCKING);
947
948 /* Shift to get chip number */
949 chipnr = ofs >> chip->chip_shift;
950
951 chip->select_chip(mtd, chipnr);
952
953 /* Check, if it is write protected */
954 if (nand_check_wp(mtd)) {
289c0522 955 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 956 __func__);
957 ret = -EIO;
958 goto out;
959 }
960
961 ret = __nand_unlock(mtd, ofs, len, 0);
962
963out:
7d70f334
VS		 964 nand_release_device(mtd);
965
966 return ret;
967}
7351d3a5 968EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 969
970/**
b6d676db 971 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 972 * @mtd: mtd info
973 * @ofs: offset to start unlock from
974 * @len: length to unlock
7d70f334 975 *
8b6e50c9
BN		 976 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
977 * have this feature, but it allows only to lock all blocks, not for specified
978 * range for block. Implementing 'lock' feature by making use of 'unlock', for
979 * now.
7d70f334 980 *
8b6e50c9 981 * Returns lock status.
7d70f334
VS		 982 */
983int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
984{
985 int ret = 0;
986 int chipnr, status, page;
987 struct nand_chip *chip = mtd->priv;
988
289c0522 989 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 990 __func__, (unsigned long long)ofs, len);
991
992 if (check_offs_len(mtd, ofs, len))
993 ret = -EINVAL;
994
995 nand_get_device(chip, mtd, FL_LOCKING);
996
997 /* Shift to get chip number */
998 chipnr = ofs >> chip->chip_shift;
999
1000 chip->select_chip(mtd, chipnr);
1001
1002 /* Check, if it is write protected */
1003 if (nand_check_wp(mtd)) {
289c0522 1004 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1005 __func__);
1006 status = MTD_ERASE_FAILED;
1007 ret = -EIO;
1008 goto out;
1009 }
1010
1011 /* Submit address of first page to lock */
1012 page = ofs >> chip->page_shift;
1013 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1014
1015 /* Call wait ready function */
1016 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 1017 /* See if device thinks it succeeded */
1018 if (status & 0x01) {
289c0522 1019 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1020 __func__, status);
1021 ret = -EIO;
1022 goto out;
1023 }
1024
1025 ret = __nand_unlock(mtd, ofs, len, 0x1);
1026
1027out:
7d70f334
VS		 1028 nand_release_device(mtd);
1029
1030 return ret;
1031}
7351d3a5 1032EXPORT_SYMBOL(nand_lock);
7d70f334 1033
8593fbc6 1034/**
7854d3f7 1035 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1036 * @mtd: mtd info structure
1037 * @chip: nand chip info structure
1038 * @buf: buffer to store read data
1039 * @page: page number to read
52ff49df 1040 *
7854d3f7 1041 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1042 */
1043static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1044 uint8_t *buf, int page)
8593fbc6
TG		 1045{
1046 chip->read_buf(mtd, buf, mtd->writesize);
1047 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1048 return 0;
1049}
1050
52ff49df 1051/**
7854d3f7 1052 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1053 * @mtd: mtd info structure
1054 * @chip: nand chip info structure
1055 * @buf: buffer to store read data
1056 * @page: page number to read
52ff49df
DB		 1057 *
1058 * We need a special oob layout and handling even when OOB isn't used.
1059 */
7351d3a5
FF		 1060static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1061 struct nand_chip *chip,
1062 uint8_t *buf, int page)
52ff49df
DB		 1063{
1064 int eccsize = chip->ecc.size;
1065 int eccbytes = chip->ecc.bytes;
1066 uint8_t *oob = chip->oob_poi;
1067 int steps, size;
1068
1069 for (steps = chip->ecc.steps; steps > 0; steps--) {
1070 chip->read_buf(mtd, buf, eccsize);
1071 buf += eccsize;
1072
1073 if (chip->ecc.prepad) {
1074 chip->read_buf(mtd, oob, chip->ecc.prepad);
1075 oob += chip->ecc.prepad;
1076 }
1077
1078 chip->read_buf(mtd, oob, eccbytes);
1079 oob += eccbytes;
1080
1081 if (chip->ecc.postpad) {
1082 chip->read_buf(mtd, oob, chip->ecc.postpad);
1083 oob += chip->ecc.postpad;
1084 }
1085 }
1086
1087 size = mtd->oobsize - (oob - chip->oob_poi);
1088 if (size)
1089 chip->read_buf(mtd, oob, size);
1090
1091 return 0;
1092}
1093
1da177e4 1094/**
7854d3f7 1095 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1096 * @mtd: mtd info structure
1097 * @chip: nand chip info structure
1098 * @buf: buffer to store read data
1099 * @page: page number to read
068e3c0a 1100 */
f5bbdacc 1101static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1102 uint8_t *buf, int page)
1da177e4 1103{
f5bbdacc
TG		 1104 int i, eccsize = chip->ecc.size;
1105 int eccbytes = chip->ecc.bytes;
1106 int eccsteps = chip->ecc.steps;
1107 uint8_t *p = buf;
4bf63fcb
DW		 1108 uint8_t *ecc_calc = chip->buffers->ecccalc;
1109 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1110 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 1111
46a8cf2d 1112 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 1113
1114 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1115 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1116
1117 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1118 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1119
1120 eccsteps = chip->ecc.steps;
1121 p = buf;
1122
1123 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1124 int stat;
1125
1126 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1127 if (stat < 0)
f5bbdacc
TG		 1128 mtd->ecc_stats.failed++;
1129 else
1130 mtd->ecc_stats.corrected += stat;
1131 }
1132 return 0;
22c60f5f 1133}
1da177e4 1134
3d459559 1135/**
7854d3f7 1136 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
8b6e50c9
BN		 1137 * @mtd: mtd info structure
1138 * @chip: nand chip info structure
1139 * @data_offs: offset of requested data within the page
1140 * @readlen: data length
1141 * @bufpoi: buffer to store read data
3d459559 1142 */
7351d3a5
FF		 1143static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1144 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1145{
1146 int start_step, end_step, num_steps;
1147 uint32_t *eccpos = chip->ecc.layout->eccpos;
1148 uint8_t *p;
1149 int data_col_addr, i, gaps = 0;
1150 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1151 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1152 int index = 0;
3d459559 1153
7854d3f7 1154 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1155 start_step = data_offs / chip->ecc.size;
1156 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1157 num_steps = end_step - start_step + 1;
1158
8b6e50c9 1159 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1160 datafrag_len = num_steps * chip->ecc.size;
1161 eccfrag_len = num_steps * chip->ecc.bytes;
1162
1163 data_col_addr = start_step * chip->ecc.size;
1164 /* If we read not a page aligned data */
1165 if (data_col_addr != 0)
1166 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1167
1168 p = bufpoi + data_col_addr;
1169 chip->read_buf(mtd, p, datafrag_len);
1170
8b6e50c9 1171 /* Calculate ECC */
3d459559
AK		 1172 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1173 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1174
8b6e50c9
BN		 1175 /*
1176 * The performance is faster if we position offsets according to
7854d3f7 1177 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1178 */
3d459559
AK		 1179 for (i = 0; i < eccfrag_len - 1; i++) {
1180 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1181 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1182 gaps = 1;
1183 break;
1184 }
1185 }
1186 if (gaps) {
1187 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1188 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1189 } else {
8b6e50c9 1190 /*
7854d3f7 1191 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1192 * about buswidth alignment in read_buf.
1193 */
7351d3a5
FF		 1194 index = start_step * chip->ecc.bytes;
1195
1196 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1197 aligned_len = eccfrag_len;
7351d3a5 1198 if (eccpos[index] & (busw - 1))
3d459559 1199 aligned_len++;
7351d3a5 1200 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1201 aligned_len++;
1202
7351d3a5
FF		 1203 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1204 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1205 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1206 }
1207
1208 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1209 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1210
1211 p = bufpoi + data_col_addr;
1212 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1213 int stat;
1214
7351d3a5
FF		 1215 stat = chip->ecc.correct(mtd, p,
1216 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
12c8eb98 1217 if (stat < 0)
3d459559
AK		 1218 mtd->ecc_stats.failed++;
1219 else
1220 mtd->ecc_stats.corrected += stat;
1221 }
1222 return 0;
1223}
1224
068e3c0a 1225/**
7854d3f7 1226 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1227 * @mtd: mtd info structure
1228 * @chip: nand chip info structure
1229 * @buf: buffer to store read data
1230 * @page: page number to read
068e3c0a 1231 *
7854d3f7 1232 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1233 */
f5bbdacc 1234static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1235 uint8_t *buf, int page)
1da177e4 1236{
f5bbdacc
TG		 1237 int i, eccsize = chip->ecc.size;
1238 int eccbytes = chip->ecc.bytes;
1239 int eccsteps = chip->ecc.steps;
1240 uint8_t *p = buf;
4bf63fcb
DW		 1241 uint8_t *ecc_calc = chip->buffers->ecccalc;
1242 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1243 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1244
1245 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1246 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1247 chip->read_buf(mtd, p, eccsize);
1248 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1249 }
f75e5097 1250 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1251
f5bbdacc 1252 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1253 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1254
f5bbdacc
TG		 1255 eccsteps = chip->ecc.steps;
1256 p = buf;
61b03bd7 1257
f5bbdacc
TG		 1258 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1259 int stat;
1da177e4 1260
f5bbdacc 1261 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1262 if (stat < 0)
f5bbdacc
TG		 1263 mtd->ecc_stats.failed++;
1264 else
1265 mtd->ecc_stats.corrected += stat;
1266 }
1267 return 0;
1268}
1da177e4 1269
6e0cb135 1270/**
7854d3f7 1271 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1272 * @mtd: mtd info structure
1273 * @chip: nand chip info structure
1274 * @buf: buffer to store read data
1275 * @page: page number to read
6e0cb135 1276 *
8b6e50c9
BN		 1277 * Hardware ECC for large page chips, require OOB to be read first. For this
1278 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1279 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1280 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1281 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1282 */
1283static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1284 struct nand_chip *chip, uint8_t *buf, int page)
1285{
1286 int i, eccsize = chip->ecc.size;
1287 int eccbytes = chip->ecc.bytes;
1288 int eccsteps = chip->ecc.steps;
1289 uint8_t *p = buf;
1290 uint8_t *ecc_code = chip->buffers->ecccode;
1291 uint32_t *eccpos = chip->ecc.layout->eccpos;
1292 uint8_t *ecc_calc = chip->buffers->ecccalc;
1293
1294 /* Read the OOB area first */
1295 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1296 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1297 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1298
1299 for (i = 0; i < chip->ecc.total; i++)
1300 ecc_code[i] = chip->oob_poi[eccpos[i]];
1301
1302 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1303 int stat;
1304
1305 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1306 chip->read_buf(mtd, p, eccsize);
1307 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1308
1309 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1310 if (stat < 0)
1311 mtd->ecc_stats.failed++;
1312 else
1313 mtd->ecc_stats.corrected += stat;
1314 }
1315 return 0;
1316}
1317
f5bbdacc 1318/**
7854d3f7 1319 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1320 * @mtd: mtd info structure
1321 * @chip: nand chip info structure
1322 * @buf: buffer to store read data
1323 * @page: page number to read
f5bbdacc 1324 *
8b6e50c9
BN		 1325 * The hw generator calculates the error syndrome automatically. Therefore we
1326 * need a special oob layout and handling.
f5bbdacc
TG		 1327 */
1328static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1329 uint8_t *buf, int page)
f5bbdacc
TG		 1330{
1331 int i, eccsize = chip->ecc.size;
1332 int eccbytes = chip->ecc.bytes;
1333 int eccsteps = chip->ecc.steps;
1334 uint8_t *p = buf;
f75e5097 1335 uint8_t *oob = chip->oob_poi;
1da177e4 1336
f5bbdacc
TG		 1337 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1338 int stat;
61b03bd7 1339
f5bbdacc
TG		 1340 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1341 chip->read_buf(mtd, p, eccsize);
1da177e4 1342
f5bbdacc
TG		 1343 if (chip->ecc.prepad) {
1344 chip->read_buf(mtd, oob, chip->ecc.prepad);
1345 oob += chip->ecc.prepad;
1346 }
1da177e4 1347
f5bbdacc
TG		 1348 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1349 chip->read_buf(mtd, oob, eccbytes);
1350 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1351
c32b8dcc 1352 if (stat < 0)
f5bbdacc 1353 mtd->ecc_stats.failed++;
61b03bd7 1354 else
f5bbdacc 1355 mtd->ecc_stats.corrected += stat;
61b03bd7 1356
f5bbdacc 1357 oob += eccbytes;
1da177e4 1358
f5bbdacc
TG		 1359 if (chip->ecc.postpad) {
1360 chip->read_buf(mtd, oob, chip->ecc.postpad);
1361 oob += chip->ecc.postpad;
61b03bd7 1362 }
f5bbdacc 1363 }
1da177e4 1364
f5bbdacc 1365 /* Calculate remaining oob bytes */
7e4178f9 1366 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1367 if (i)
1368 chip->read_buf(mtd, oob, i);
61b03bd7 1369
f5bbdacc
TG		 1370 return 0;
1371}
1da177e4 1372
f5bbdacc 1373/**
7854d3f7 1374 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1375 * @chip: nand chip structure
1376 * @oob: oob destination address
1377 * @ops: oob ops structure
1378 * @len: size of oob to transfer
8593fbc6
TG		 1379 */
1380static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1381 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1382{
f8ac0414 1383 switch (ops->mode) {
8593fbc6
TG		 1384
1385 case MTD_OOB_PLACE:
1386 case MTD_OOB_RAW:
1387 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1388 return oob + len;
1389
1390 case MTD_OOB_AUTO: {
1391 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1392 uint32_t boffs = 0, roffs = ops->ooboffs;
1393 size_t bytes = 0;
8593fbc6 1394
f8ac0414 1395 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1396 /* Read request not from offset 0? */
7bc3312b
TG		 1397 if (unlikely(roffs)) {
1398 if (roffs >= free->length) {
1399 roffs -= free->length;
1400 continue;
1401 }
1402 boffs = free->offset + roffs;
1403 bytes = min_t(size_t, len,
1404 (free->length - roffs));
1405 roffs = 0;
1406 } else {
1407 bytes = min_t(size_t, len, free->length);
1408 boffs = free->offset;
1409 }
1410 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1411 oob += bytes;
1412 }
1413 return oob;
1414 }
1415 default:
1416 BUG();
1417 }
1418 return NULL;
1419}
1420
1421/**
7854d3f7 1422 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1423 * @mtd: MTD device structure
1424 * @from: offset to read from
1425 * @ops: oob ops structure
f5bbdacc
TG		 1426 *
1427 * Internal function. Called with chip held.
1428 */
8593fbc6
TG		 1429static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1430 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1431{
1432 int chipnr, page, realpage, col, bytes, aligned;
1433 struct nand_chip *chip = mtd->priv;
1434 struct mtd_ecc_stats stats;
1435 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1436 int sndcmd = 1;
1437 int ret = 0;
8593fbc6 1438 uint32_t readlen = ops->len;
7014568b 1439 uint32_t oobreadlen = ops->ooblen;
9aca334e
ML		 1440 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1441 mtd->oobavail : mtd->oobsize;
1442
8593fbc6 1443 uint8_t *bufpoi, *oob, *buf;
1da177e4 1444
f5bbdacc 1445 stats = mtd->ecc_stats;
1da177e4 1446
f5bbdacc
TG		 1447 chipnr = (int)(from >> chip->chip_shift);
1448 chip->select_chip(mtd, chipnr);
61b03bd7 1449
f5bbdacc
TG		 1450 realpage = (int)(from >> chip->page_shift);
1451 page = realpage & chip->pagemask;
1da177e4 1452
f5bbdacc 1453 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1454
8593fbc6
TG		 1455 buf = ops->datbuf;
1456 oob = ops->oobbuf;
1457
f8ac0414 1458 while (1) {
f5bbdacc
TG		 1459 bytes = min(mtd->writesize - col, readlen);
1460 aligned = (bytes == mtd->writesize);
61b03bd7 1461
8b6e50c9 1462 /* Is the current page in the buffer? */
8593fbc6 1463 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1464 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1465
f5bbdacc
TG		 1466 if (likely(sndcmd)) {
1467 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1468 sndcmd = 0;
1da177e4 1469 }
1da177e4 1470
f5bbdacc 1471 /* Now read the page into the buffer */
956e944c 1472 if (unlikely(ops->mode == MTD_OOB_RAW))
46a8cf2d
SN		 1473 ret = chip->ecc.read_page_raw(mtd, chip,
1474 bufpoi, page);
3d459559 1475 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1476 ret = chip->ecc.read_subpage(mtd, chip,
1477 col, bytes, bufpoi);
956e944c 1478 else
46a8cf2d
SN		 1479 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1480 page);
f5bbdacc 1481 if (ret < 0)
1da177e4 1482 break;
f5bbdacc
TG		 1483
1484 /* Transfer not aligned data */
1485 if (!aligned) {
c1194c79
AB		 1486 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1487 !(mtd->ecc_stats.failed - stats.failed))
3d459559 1488 chip->pagebuf = realpage;
4bf63fcb 1489 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1490 }
1491
8593fbc6
TG		 1492 buf += bytes;
1493
1494 if (unlikely(oob)) {
9aca334e 1495
b64d39d8
ML		 1496 int toread = min(oobreadlen, max_oobsize);
1497
1498 if (toread) {
1499 oob = nand_transfer_oob(chip,
1500 oob, ops, toread);
1501 oobreadlen -= toread;
1502 }
8593fbc6
TG		 1503 }
1504
f5bbdacc
TG		 1505 if (!(chip->options & NAND_NO_READRDY)) {
1506 /*
1507 * Apply delay or wait for ready/busy pin. Do
1508 * this before the AUTOINCR check, so no
1509 * problems arise if a chip which does auto
1510 * increment is marked as NOAUTOINCR by the
1511 * board driver.
1512 */
1513 if (!chip->dev_ready)
1514 udelay(chip->chip_delay);
1515 else
1516 nand_wait_ready(mtd);
1da177e4 1517 }
8593fbc6 1518 } else {
4bf63fcb 1519 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1520 buf += bytes;
1521 }
1da177e4 1522
f5bbdacc 1523 readlen -= bytes;
61b03bd7 1524
f5bbdacc 1525 if (!readlen)
61b03bd7 1526 break;
1da177e4 1527
8b6e50c9 1528 /* For subsequent reads align to page boundary */
1da177e4
LT		 1529 col = 0;
1530 /* Increment page address */
1531 realpage++;
1532
ace4dfee 1533 page = realpage & chip->pagemask;
1da177e4
LT		 1534 /* Check, if we cross a chip boundary */
1535 if (!page) {
1536 chipnr++;
ace4dfee
TG		 1537 chip->select_chip(mtd, -1);
1538 chip->select_chip(mtd, chipnr);
1da177e4 1539 }
f5bbdacc 1540
8b6e50c9
BN		 1541 /*
1542 * Check, if the chip supports auto page increment or if we
1543 * have hit a block boundary.
e0c7d767 1544 */
f5bbdacc 1545 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1546 sndcmd = 1;
1da177e4
LT		 1547 }
1548
8593fbc6 1549 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1550 if (oob)
1551 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1552
f5bbdacc
TG		 1553 if (ret)
1554 return ret;
1555
9a1fcdfd
TG		 1556 if (mtd->ecc_stats.failed - stats.failed)
1557 return -EBADMSG;
1558
1559 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1560}
1561
1562/**
25985edc 1563 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1564 * @mtd: MTD device structure
1565 * @from: offset to read from
1566 * @len: number of bytes to read
1567 * @retlen: pointer to variable to store the number of read bytes
1568 * @buf: the databuffer to put data
f5bbdacc 1569 *
8b6e50c9 1570 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1571 */
1572static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1573 size_t *retlen, uint8_t *buf)
1574{
8593fbc6 1575 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1576 int ret;
1577
f5bbdacc
TG		 1578 /* Do not allow reads past end of device */
1579 if ((from + len) > mtd->size)
1580 return -EINVAL;
1581 if (!len)
1582 return 0;
1583
8593fbc6 1584 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1585
8593fbc6
TG		 1586 chip->ops.len = len;
1587 chip->ops.datbuf = buf;
1588 chip->ops.oobbuf = NULL;
1589
1590 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1591
7fd5aecc
RP		 1592 *retlen = chip->ops.retlen;
1593
f5bbdacc
TG		 1594 nand_release_device(mtd);
1595
1596 return ret;
1da177e4
LT		 1597}
1598
7bc3312b 1599/**
7854d3f7 1600 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1601 * @mtd: mtd info structure
1602 * @chip: nand chip info structure
1603 * @page: page number to read
1604 * @sndcmd: flag whether to issue read command or not
7bc3312b
TG		 1605 */
1606static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1607 int page, int sndcmd)
1608{
1609 if (sndcmd) {
1610 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1611 sndcmd = 0;
1612 }
1613 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1614 return sndcmd;
1615}
1616
1617/**
7854d3f7 1618 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1619 * with syndromes
8b6e50c9
BN		 1620 * @mtd: mtd info structure
1621 * @chip: nand chip info structure
1622 * @page: page number to read
1623 * @sndcmd: flag whether to issue read command or not
7bc3312b
TG		 1624 */
1625static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1626 int page, int sndcmd)
1627{
1628 uint8_t *buf = chip->oob_poi;
1629 int length = mtd->oobsize;
1630 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1631 int eccsize = chip->ecc.size;
1632 uint8_t *bufpoi = buf;
1633 int i, toread, sndrnd = 0, pos;
1634
1635 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1636 for (i = 0; i < chip->ecc.steps; i++) {
1637 if (sndrnd) {
1638 pos = eccsize + i * (eccsize + chunk);
1639 if (mtd->writesize > 512)
1640 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1641 else
1642 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1643 } else
1644 sndrnd = 1;
1645 toread = min_t(int, length, chunk);
1646 chip->read_buf(mtd, bufpoi, toread);
1647 bufpoi += toread;
1648 length -= toread;
1649 }
1650 if (length > 0)
1651 chip->read_buf(mtd, bufpoi, length);
1652
1653 return 1;
1654}
1655
1656/**
7854d3f7 1657 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1658 * @mtd: mtd info structure
1659 * @chip: nand chip info structure
1660 * @page: page number to write
7bc3312b
TG		 1661 */
1662static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1663 int page)
1664{
1665 int status = 0;
1666 const uint8_t *buf = chip->oob_poi;
1667 int length = mtd->oobsize;
1668
1669 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1670 chip->write_buf(mtd, buf, length);
1671 /* Send command to program the OOB data */
1672 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1673
1674 status = chip->waitfunc(mtd, chip);
1675
0d420f9d 1676 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1677}
1678
1679/**
7854d3f7 1680 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1681 * with syndrome - only for large page flash
1682 * @mtd: mtd info structure
1683 * @chip: nand chip info structure
1684 * @page: page number to write
7bc3312b
TG		 1685 */
1686static int nand_write_oob_syndrome(struct mtd_info *mtd,
1687 struct nand_chip *chip, int page)
1688{
1689 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1690 int eccsize = chip->ecc.size, length = mtd->oobsize;
1691 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1692 const uint8_t *bufpoi = chip->oob_poi;
1693
1694 /*
1695 * data-ecc-data-ecc ... ecc-oob
1696 * or
1697 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1698 */
1699 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1700 pos = steps * (eccsize + chunk);
1701 steps = 0;
1702 } else
8b0036ee 1703 pos = eccsize;
7bc3312b
TG		 1704
1705 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1706 for (i = 0; i < steps; i++) {
1707 if (sndcmd) {
1708 if (mtd->writesize <= 512) {
1709 uint32_t fill = 0xFFFFFFFF;
1710
1711 len = eccsize;
1712 while (len > 0) {
1713 int num = min_t(int, len, 4);
1714 chip->write_buf(mtd, (uint8_t *)&fill,
1715 num);
1716 len -= num;
1717 }
1718 } else {
1719 pos = eccsize + i * (eccsize + chunk);
1720 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1721 }
1722 } else
1723 sndcmd = 1;
1724 len = min_t(int, length, chunk);
1725 chip->write_buf(mtd, bufpoi, len);
1726 bufpoi += len;
1727 length -= len;
1728 }
1729 if (length > 0)
1730 chip->write_buf(mtd, bufpoi, length);
1731
1732 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1733 status = chip->waitfunc(mtd, chip);
1734
1735 return status & NAND_STATUS_FAIL ? -EIO : 0;
1736}
1737
1da177e4 1738/**
7854d3f7 1739 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1740 * @mtd: MTD device structure
1741 * @from: offset to read from
1742 * @ops: oob operations description structure
1da177e4 1743 *
8b6e50c9 1744 * NAND read out-of-band data from the spare area.
1da177e4 1745 */
8593fbc6
TG		 1746static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1747 struct mtd_oob_ops *ops)
1da177e4 1748{
7bc3312b 1749 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1750 struct nand_chip *chip = mtd->priv;
041e4575 1751 struct mtd_ecc_stats stats;
7314e9e7 1752 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1753 int readlen = ops->ooblen;
1754 int len;
7bc3312b 1755 uint8_t *buf = ops->oobbuf;
61b03bd7 1756
289c0522 1757 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1758 __func__, (unsigned long long)from, readlen);
1da177e4 1759
041e4575
BN		 1760 stats = mtd->ecc_stats;
1761
03736155 1762 if (ops->mode == MTD_OOB_AUTO)
7014568b 1763 len = chip->ecc.layout->oobavail;
03736155
AH		 1764 else
1765 len = mtd->oobsize;
1766
1767 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1768 pr_debug("%s: attempt to start read outside oob\n",
1769 __func__);
03736155
AH		 1770 return -EINVAL;
1771 }
1772
1773 /* Do not allow reads past end of device */
1774 if (unlikely(from >= mtd->size ||
1775 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1776 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1777 pr_debug("%s: attempt to read beyond end of device\n",
1778 __func__);
03736155
AH		 1779 return -EINVAL;
1780 }
7014568b 1781
7314e9e7 1782 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1783 chip->select_chip(mtd, chipnr);
1da177e4 1784
7314e9e7
TG		 1785 /* Shift to get page */
1786 realpage = (int)(from >> chip->page_shift);
1787 page = realpage & chip->pagemask;
1da177e4 1788
f8ac0414 1789 while (1) {
7bc3312b 1790 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1791
1792 len = min(len, readlen);
1793 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1794
7314e9e7
TG		 1795 if (!(chip->options & NAND_NO_READRDY)) {
1796 /*
1797 * Apply delay or wait for ready/busy pin. Do this
1798 * before the AUTOINCR check, so no problems arise if a
1799 * chip which does auto increment is marked as
1800 * NOAUTOINCR by the board driver.
19870da7 1801 */
ace4dfee
TG		 1802 if (!chip->dev_ready)
1803 udelay(chip->chip_delay);
19870da7
TG		 1804 else
1805 nand_wait_ready(mtd);
7314e9e7 1806 }
19870da7 1807
7014568b 1808 readlen -= len;
0d420f9d
SZ		 1809 if (!readlen)
1810 break;
1811
7314e9e7
TG		 1812 /* Increment page address */
1813 realpage++;
1814
1815 page = realpage & chip->pagemask;
1816 /* Check, if we cross a chip boundary */
1817 if (!page) {
1818 chipnr++;
1819 chip->select_chip(mtd, -1);
1820 chip->select_chip(mtd, chipnr);
1da177e4 1821 }
7314e9e7 1822
8b6e50c9
BN		 1823 /*
1824 * Check, if the chip supports auto page increment or if we
1825 * have hit a block boundary.
7314e9e7
TG		 1826 */
1827 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1828 sndcmd = 1;
1da177e4
LT		 1829 }
1830
7014568b 1831 ops->oobretlen = ops->ooblen;
041e4575
BN		 1832
1833 if (mtd->ecc_stats.failed - stats.failed)
1834 return -EBADMSG;
1835
1836 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1837}
1838
1839/**
8593fbc6 1840 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1841 * @mtd: MTD device structure
1842 * @from: offset to read from
1843 * @ops: oob operation description structure
1da177e4 1844 *
8b6e50c9 1845 * NAND read data and/or out-of-band data.
1da177e4 1846 */
8593fbc6
TG		 1847static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1848 struct mtd_oob_ops *ops)
1da177e4 1849{
ace4dfee 1850 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1851 int ret = -ENOTSUPP;
1852
1853 ops->retlen = 0;
1da177e4
LT		 1854
1855 /* Do not allow reads past end of device */
7014568b 1856 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1857 pr_debug("%s: attempt to read beyond end of device\n",
1858 __func__);
1da177e4
LT		 1859 return -EINVAL;
1860 }
1861
ace4dfee 1862 nand_get_device(chip, mtd, FL_READING);
1da177e4 1863
f8ac0414 1864 switch (ops->mode) {
8593fbc6
TG		 1865 case MTD_OOB_PLACE:
1866 case MTD_OOB_AUTO:
8593fbc6 1867 case MTD_OOB_RAW:
8593fbc6 1868 break;
1da177e4 1869
8593fbc6
TG		 1870 default:
1871 goto out;
1872 }
1da177e4 1873
8593fbc6
TG		 1874 if (!ops->datbuf)
1875 ret = nand_do_read_oob(mtd, from, ops);
1876 else
1877 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1878
7351d3a5 1879out:
8593fbc6
TG		 1880 nand_release_device(mtd);
1881 return ret;
1882}
61b03bd7 1883
1da177e4 1884
8593fbc6 1885/**
7854d3f7 1886 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1887 * @mtd: mtd info structure
1888 * @chip: nand chip info structure
1889 * @buf: data buffer
52ff49df 1890 *
7854d3f7 1891 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1892 */
1893static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1894 const uint8_t *buf)
1895{
1896 chip->write_buf(mtd, buf, mtd->writesize);
1897 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1898}
1899
52ff49df 1900/**
7854d3f7 1901 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1902 * @mtd: mtd info structure
1903 * @chip: nand chip info structure
1904 * @buf: data buffer
52ff49df
DB		 1905 *
1906 * We need a special oob layout and handling even when ECC isn't checked.
1907 */
7351d3a5
FF		 1908static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1909 struct nand_chip *chip,
1910 const uint8_t *buf)
52ff49df
DB		 1911{
1912 int eccsize = chip->ecc.size;
1913 int eccbytes = chip->ecc.bytes;
1914 uint8_t *oob = chip->oob_poi;
1915 int steps, size;
1916
1917 for (steps = chip->ecc.steps; steps > 0; steps--) {
1918 chip->write_buf(mtd, buf, eccsize);
1919 buf += eccsize;
1920
1921 if (chip->ecc.prepad) {
1922 chip->write_buf(mtd, oob, chip->ecc.prepad);
1923 oob += chip->ecc.prepad;
1924 }
1925
1926 chip->read_buf(mtd, oob, eccbytes);
1927 oob += eccbytes;
1928
1929 if (chip->ecc.postpad) {
1930 chip->write_buf(mtd, oob, chip->ecc.postpad);
1931 oob += chip->ecc.postpad;
1932 }
1933 }
1934
1935 size = mtd->oobsize - (oob - chip->oob_poi);
1936 if (size)
1937 chip->write_buf(mtd, oob, size);
1938}
9223a456 1939/**
7854d3f7 1940 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1941 * @mtd: mtd info structure
1942 * @chip: nand chip info structure
1943 * @buf: data buffer
9223a456 1944 */
f75e5097
TG		 1945static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1946 const uint8_t *buf)
9223a456 1947{
f75e5097
TG		 1948 int i, eccsize = chip->ecc.size;
1949 int eccbytes = chip->ecc.bytes;
1950 int eccsteps = chip->ecc.steps;
4bf63fcb 1951 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1952 const uint8_t *p = buf;
8b099a39 1953 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1954
7854d3f7 1955 /* Software ECC calculation */
8593fbc6
TG		 1956 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1957 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1958
8593fbc6
TG		 1959 for (i = 0; i < chip->ecc.total; i++)
1960 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1961
90424de8 1962 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1963}
9223a456 1964
f75e5097 1965/**
7854d3f7 1966 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 1967 * @mtd: mtd info structure
1968 * @chip: nand chip info structure
1969 * @buf: data buffer
f75e5097
TG		 1970 */
1971static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1972 const uint8_t *buf)
1973{
1974 int i, eccsize = chip->ecc.size;
1975 int eccbytes = chip->ecc.bytes;
1976 int eccsteps = chip->ecc.steps;
4bf63fcb 1977 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1978 const uint8_t *p = buf;
8b099a39 1979 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1980
f75e5097
TG		 1981 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1982 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1983 chip->write_buf(mtd, p, eccsize);
f75e5097 1984 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1985 }
1986
f75e5097
TG		 1987 for (i = 0; i < chip->ecc.total; i++)
1988 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1989
1990 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 1991}
1992
61b03bd7 1993/**
7854d3f7 1994 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 1995 * @mtd: mtd info structure
1996 * @chip: nand chip info structure
1997 * @buf: data buffer
1da177e4 1998 *
8b6e50c9
BN		 1999 * The hw generator calculates the error syndrome automatically. Therefore we
2000 * need a special oob layout and handling.
f75e5097
TG		 2001 */
2002static void nand_write_page_syndrome(struct mtd_info *mtd,
2003 struct nand_chip *chip, const uint8_t *buf)
1da177e4 2004{
f75e5097
TG		 2005 int i, eccsize = chip->ecc.size;
2006 int eccbytes = chip->ecc.bytes;
2007 int eccsteps = chip->ecc.steps;
2008 const uint8_t *p = buf;
2009 uint8_t *oob = chip->oob_poi;
1da177e4 2010
f75e5097 2011 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2012
f75e5097
TG		 2013 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2014 chip->write_buf(mtd, p, eccsize);
61b03bd7 2015
f75e5097
TG		 2016 if (chip->ecc.prepad) {
2017 chip->write_buf(mtd, oob, chip->ecc.prepad);
2018 oob += chip->ecc.prepad;
2019 }
2020
2021 chip->ecc.calculate(mtd, p, oob);
2022 chip->write_buf(mtd, oob, eccbytes);
2023 oob += eccbytes;
2024
2025 if (chip->ecc.postpad) {
2026 chip->write_buf(mtd, oob, chip->ecc.postpad);
2027 oob += chip->ecc.postpad;
1da177e4 2028 }
1da177e4 2029 }
f75e5097
TG		 2030
2031 /* Calculate remaining oob bytes */
7e4178f9 2032 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2033 if (i)
2034 chip->write_buf(mtd, oob, i);
2035}
2036
2037/**
956e944c 2038 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2039 * @mtd: MTD device structure
2040 * @chip: NAND chip descriptor
2041 * @buf: the data to write
2042 * @page: page number to write
2043 * @cached: cached programming
2044 * @raw: use _raw version of write_page
f75e5097
TG		 2045 */
2046static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 2047 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 2048{
2049 int status;
2050
2051 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2052
956e944c
DW		 2053 if (unlikely(raw))
2054 chip->ecc.write_page_raw(mtd, chip, buf);
2055 else
2056 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 2057
2058 /*
7854d3f7 2059 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2060 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2061 */
2062 cached = 0;
2063
2064 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2065
2066 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2067 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2068 /*
2069 * See if operation failed and additional status checks are
8b6e50c9 2070 * available.
f75e5097
TG		 2071 */
2072 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2073 status = chip->errstat(mtd, chip, FL_WRITING, status,
2074 page);
2075
2076 if (status & NAND_STATUS_FAIL)
2077 return -EIO;
2078 } else {
2079 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2080 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2081 }
2082
2083#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2084 /* Send command to read back the data */
2085 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2086
2087 if (chip->verify_buf(mtd, buf, mtd->writesize))
2088 return -EIO;
2089#endif
2090 return 0;
1da177e4
LT		 2091}
2092
8593fbc6 2093/**
7854d3f7 2094 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2095 * @mtd: MTD device structure
8b6e50c9
BN		 2096 * @oob: oob data buffer
2097 * @len: oob data write length
2098 * @ops: oob ops structure
8593fbc6 2099 */
f722013e
TAA		 2100static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2101 struct mtd_oob_ops *ops)
8593fbc6 2102{
f722013e
TAA		 2103 struct nand_chip *chip = mtd->priv;
2104
2105 /*
2106 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2107 * data from a previous OOB read.
2108 */
2109 memset(chip->oob_poi, 0xff, mtd->oobsize);
2110
f8ac0414 2111 switch (ops->mode) {
8593fbc6
TG		 2112
2113 case MTD_OOB_PLACE:
2114 case MTD_OOB_RAW:
2115 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2116 return oob + len;
2117
2118 case MTD_OOB_AUTO: {
2119 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2120 uint32_t boffs = 0, woffs = ops->ooboffs;
2121 size_t bytes = 0;
8593fbc6 2122
f8ac0414 2123 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2124 /* Write request not from offset 0? */
7bc3312b
TG		 2125 if (unlikely(woffs)) {
2126 if (woffs >= free->length) {
2127 woffs -= free->length;
2128 continue;
2129 }
2130 boffs = free->offset + woffs;
2131 bytes = min_t(size_t, len,
2132 (free->length - woffs));
2133 woffs = 0;
2134 } else {
2135 bytes = min_t(size_t, len, free->length);
2136 boffs = free->offset;
2137 }
8b0036ee 2138 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2139 oob += bytes;
2140 }
2141 return oob;
2142 }
2143 default:
2144 BUG();
2145 }
2146 return NULL;
2147}
2148
f8ac0414 2149#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2150
2151/**
7854d3f7 2152 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2153 * @mtd: MTD device structure
2154 * @to: offset to write to
2155 * @ops: oob operations description structure
1da177e4 2156 *
8b6e50c9 2157 * NAND write with ECC.
1da177e4 2158 */
8593fbc6
TG		 2159static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2160 struct mtd_oob_ops *ops)
1da177e4 2161{
29072b96 2162 int chipnr, realpage, page, blockmask, column;
ace4dfee 2163 struct nand_chip *chip = mtd->priv;
8593fbc6 2164 uint32_t writelen = ops->len;
782ce79a
ML		 2165
2166 uint32_t oobwritelen = ops->ooblen;
2167 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2168 mtd->oobavail : mtd->oobsize;
2169
8593fbc6
TG		 2170 uint8_t *oob = ops->oobbuf;
2171 uint8_t *buf = ops->datbuf;
29072b96 2172 int ret, subpage;
1da177e4 2173
8593fbc6 2174 ops->retlen = 0;
29072b96
TG		 2175 if (!writelen)
2176 return 0;
1da177e4 2177
8b6e50c9 2178 /* Reject writes, which are not page aligned */
8593fbc6 2179 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2180 pr_notice("%s: attempt to write non page aligned data\n",
2181 __func__);
1da177e4
LT		 2182 return -EINVAL;
2183 }
2184
29072b96
TG		 2185 column = to & (mtd->writesize - 1);
2186 subpage = column || (writelen & (mtd->writesize - 1));
2187
2188 if (subpage && oob)
2189 return -EINVAL;
1da177e4 2190
6a930961
TG		 2191 chipnr = (int)(to >> chip->chip_shift);
2192 chip->select_chip(mtd, chipnr);
2193
1da177e4
LT		 2194 /* Check, if it is write protected */
2195 if (nand_check_wp(mtd))
8593fbc6 2196 return -EIO;
1da177e4 2197
f75e5097
TG		 2198 realpage = (int)(to >> chip->page_shift);
2199 page = realpage & chip->pagemask;
2200 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2201
2202 /* Invalidate the page cache, when we write to the cached page */
2203 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2204 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2205 chip->pagebuf = -1;
61b03bd7 2206
782ce79a 2207 /* Don't allow multipage oob writes with offset */
cdcf12b2 2208 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2209 return -EINVAL;
2210
f8ac0414 2211 while (1) {
29072b96 2212 int bytes = mtd->writesize;
f75e5097 2213 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2214 uint8_t *wbuf = buf;
2215
8b6e50c9 2216 /* Partial page write? */
29072b96
TG		 2217 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2218 cached = 0;
2219 bytes = min_t(int, bytes - column, (int) writelen);
2220 chip->pagebuf = -1;
2221 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2222 memcpy(&chip->buffers->databuf[column], buf, bytes);
2223 wbuf = chip->buffers->databuf;
2224 }
1da177e4 2225
782ce79a
ML		 2226 if (unlikely(oob)) {
2227 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2228 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2229 oobwritelen -= len;
f722013e
TAA		 2230 } else {
2231 /* We still need to erase leftover OOB data */
2232 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2233 }
8593fbc6 2234
29072b96 2235 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 2236 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 2237 if (ret)
2238 break;
2239
2240 writelen -= bytes;
2241 if (!writelen)
2242 break;
2243
29072b96 2244 column = 0;
f75e5097
TG		 2245 buf += bytes;
2246 realpage++;
2247
2248 page = realpage & chip->pagemask;
2249 /* Check, if we cross a chip boundary */
2250 if (!page) {
2251 chipnr++;
2252 chip->select_chip(mtd, -1);
2253 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2254 }
2255 }
8593fbc6 2256
8593fbc6 2257 ops->retlen = ops->len - writelen;
7014568b
VW		 2258 if (unlikely(oob))
2259 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2260 return ret;
2261}
2262
2af7c653
SK		 2263/**
2264 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2265 * @mtd: MTD device structure
2266 * @to: offset to write to
2267 * @len: number of bytes to write
2268 * @retlen: pointer to variable to store the number of written bytes
2269 * @buf: the data to write
2af7c653
SK		 2270 *
2271 * NAND write with ECC. Used when performing writes in interrupt context, this
2272 * may for example be called by mtdoops when writing an oops while in panic.
2273 */
2274static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2275 size_t *retlen, const uint8_t *buf)
2276{
2277 struct nand_chip *chip = mtd->priv;
2278 int ret;
2279
2280 /* Do not allow reads past end of device */
2281 if ((to + len) > mtd->size)
2282 return -EINVAL;
2283 if (!len)
2284 return 0;
2285
8b6e50c9 2286 /* Wait for the device to get ready */
2af7c653
SK		 2287 panic_nand_wait(mtd, chip, 400);
2288
8b6e50c9 2289 /* Grab the device */
2af7c653
SK		 2290 panic_nand_get_device(chip, mtd, FL_WRITING);
2291
2292 chip->ops.len = len;
2293 chip->ops.datbuf = (uint8_t *)buf;
2294 chip->ops.oobbuf = NULL;
2295
2296 ret = nand_do_write_ops(mtd, to, &chip->ops);
2297
2298 *retlen = chip->ops.retlen;
2299 return ret;
2300}
2301
f75e5097 2302/**
8593fbc6 2303 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2304 * @mtd: MTD device structure
2305 * @to: offset to write to
2306 * @len: number of bytes to write
2307 * @retlen: pointer to variable to store the number of written bytes
2308 * @buf: the data to write
f75e5097 2309 *
8b6e50c9 2310 * NAND write with ECC.
f75e5097 2311 */
8593fbc6
TG		 2312static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2313 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2314{
2315 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 2316 int ret;
2317
8593fbc6
TG		 2318 /* Do not allow reads past end of device */
2319 if ((to + len) > mtd->size)
f75e5097 2320 return -EINVAL;
8593fbc6
TG		 2321 if (!len)
2322 return 0;
f75e5097 2323
7bc3312b 2324 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 2325
8593fbc6
TG		 2326 chip->ops.len = len;
2327 chip->ops.datbuf = (uint8_t *)buf;
2328 chip->ops.oobbuf = NULL;
f75e5097 2329
8593fbc6 2330 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 2331
7fd5aecc
RP		 2332 *retlen = chip->ops.retlen;
2333
f75e5097 2334 nand_release_device(mtd);
8593fbc6 2335
8593fbc6 2336 return ret;
f75e5097 2337}
7314e9e7 2338
1da177e4 2339/**
8593fbc6 2340 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2341 * @mtd: MTD device structure
2342 * @to: offset to write to
2343 * @ops: oob operation description structure
1da177e4 2344 *
8b6e50c9 2345 * NAND write out-of-band.
1da177e4 2346 */
8593fbc6
TG		 2347static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2348 struct mtd_oob_ops *ops)
1da177e4 2349{
03736155 2350 int chipnr, page, status, len;
ace4dfee 2351 struct nand_chip *chip = mtd->priv;
1da177e4 2352
289c0522 2353 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2354 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2355
03736155
AH		 2356 if (ops->mode == MTD_OOB_AUTO)
2357 len = chip->ecc.layout->oobavail;
2358 else
2359 len = mtd->oobsize;
2360
1da177e4 2361 /* Do not allow write past end of page */
03736155 2362 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2363 pr_debug("%s: attempt to write past end of page\n",
2364 __func__);
1da177e4
LT		 2365 return -EINVAL;
2366 }
2367
03736155 2368 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2369 pr_debug("%s: attempt to start write outside oob\n",
2370 __func__);
03736155
AH		 2371 return -EINVAL;
2372 }
2373
775adc3d 2374 /* Do not allow write past end of device */
03736155
AH		 2375 if (unlikely(to >= mtd->size ||
2376 ops->ooboffs + ops->ooblen >
2377 ((mtd->size >> chip->page_shift) -
2378 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2379 pr_debug("%s: attempt to write beyond end of device\n",
2380 __func__);
03736155
AH		 2381 return -EINVAL;
2382 }
2383
7314e9e7 2384 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2385 chip->select_chip(mtd, chipnr);
1da177e4 2386
7314e9e7
TG		 2387 /* Shift to get page */
2388 page = (int)(to >> chip->page_shift);
2389
2390 /*
2391 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2392 * of my DiskOnChip 2000 test units) will clear the whole data page too
2393 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2394 * it in the doc2000 driver in August 1999. dwmw2.
2395 */
ace4dfee 2396 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2397
2398 /* Check, if it is write protected */
2399 if (nand_check_wp(mtd))
8593fbc6 2400 return -EROFS;
61b03bd7 2401
1da177e4 2402 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2403 if (page == chip->pagebuf)
2404 chip->pagebuf = -1;
1da177e4 2405
f722013e 2406 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
7bc3312b 2407 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2408
7bc3312b
TG		 2409 if (status)
2410 return status;
1da177e4 2411
7014568b 2412 ops->oobretlen = ops->ooblen;
1da177e4 2413
7bc3312b 2414 return 0;
8593fbc6
TG		 2415}
2416
2417/**
2418 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2419 * @mtd: MTD device structure
2420 * @to: offset to write to
2421 * @ops: oob operation description structure
8593fbc6
TG		 2422 */
2423static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2424 struct mtd_oob_ops *ops)
2425{
8593fbc6
TG		 2426 struct nand_chip *chip = mtd->priv;
2427 int ret = -ENOTSUPP;
2428
2429 ops->retlen = 0;
2430
2431 /* Do not allow writes past end of device */
7014568b 2432 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2433 pr_debug("%s: attempt to write beyond end of device\n",
2434 __func__);
8593fbc6
TG		 2435 return -EINVAL;
2436 }
2437
7bc3312b 2438 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2439
f8ac0414 2440 switch (ops->mode) {
8593fbc6
TG		 2441 case MTD_OOB_PLACE:
2442 case MTD_OOB_AUTO:
8593fbc6 2443 case MTD_OOB_RAW:
8593fbc6
TG		 2444 break;
2445
2446 default:
2447 goto out;
2448 }
2449
2450 if (!ops->datbuf)
2451 ret = nand_do_write_oob(mtd, to, ops);
2452 else
2453 ret = nand_do_write_ops(mtd, to, ops);
2454
7351d3a5 2455out:
1da177e4 2456 nand_release_device(mtd);
1da177e4
LT		 2457 return ret;
2458}
2459
1da177e4 2460/**
7854d3f7 2461 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2462 * @mtd: MTD device structure
2463 * @page: the page address of the block which will be erased
1da177e4 2464 *
8b6e50c9 2465 * Standard erase command for NAND chips.
1da177e4 2466 */
e0c7d767 2467static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2468{
ace4dfee 2469 struct nand_chip *chip = mtd->priv;
1da177e4 2470 /* Send commands to erase a block */
ace4dfee
TG		 2471 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2472 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2473}
2474
2475/**
7854d3f7 2476 * multi_erase_cmd - [GENERIC] AND specific block erase command function
8b6e50c9
BN		 2477 * @mtd: MTD device structure
2478 * @page: the page address of the block which will be erased
1da177e4 2479 *
8b6e50c9 2480 * AND multi block erase command function. Erase 4 consecutive blocks.
1da177e4 2481 */
e0c7d767 2482static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2483{
ace4dfee 2484 struct nand_chip *chip = mtd->priv;
1da177e4 2485 /* Send commands to erase a block */
ace4dfee
TG		 2486 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2487 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2488 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2489 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2490 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2491}
2492
2493/**
2494 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2495 * @mtd: MTD device structure
2496 * @instr: erase instruction
1da177e4 2497 *
8b6e50c9 2498 * Erase one ore more blocks.
1da177e4 2499 */
e0c7d767 2500static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2501{
e0c7d767 2502 return nand_erase_nand(mtd, instr, 0);
1da177e4 2503}
61b03bd7 2504
30f464b7 2505#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2506/**
7854d3f7 2507 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2508 * @mtd: MTD device structure
2509 * @instr: erase instruction
2510 * @allowbbt: allow erasing the bbt area
1da177e4 2511 *
8b6e50c9 2512 * Erase one ore more blocks.
1da177e4 2513 */
ace4dfee
TG		 2514int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2515 int allowbbt)
1da177e4 2516{
69423d99 2517 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2518 struct nand_chip *chip = mtd->priv;
f8ac0414 2519 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2520 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2521 loff_t len;
1da177e4 2522
289c0522
BN		 2523 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2524 __func__, (unsigned long long)instr->addr,
2525 (unsigned long long)instr->len);
1da177e4 2526
6fe5a6ac 2527 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2528 return -EINVAL;
1da177e4 2529
bb0eb217 2530 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2531
2532 /* Grab the lock and see if the device is available */
ace4dfee 2533 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2534
2535 /* Shift to get first page */
ace4dfee
TG		 2536 page = (int)(instr->addr >> chip->page_shift);
2537 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2538
2539 /* Calculate pages in each block */
ace4dfee 2540 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2541
2542 /* Select the NAND device */
ace4dfee 2543 chip->select_chip(mtd, chipnr);
1da177e4 2544
1da177e4
LT		 2545 /* Check, if it is write protected */
2546 if (nand_check_wp(mtd)) {
289c0522
BN		 2547 pr_debug("%s: device is write protected!\n",
2548 __func__);
1da177e4
LT		 2549 instr->state = MTD_ERASE_FAILED;
2550 goto erase_exit;
2551 }
2552
ace4dfee
TG		 2553 /*
2554 * If BBT requires refresh, set the BBT page mask to see if the BBT
2555 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2556 * can not be matched. This is also done when the bbt is actually
7854d3f7 2557 * erased to avoid recursive updates.
ace4dfee
TG		 2558 */
2559 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2560 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2561
1da177e4
LT		 2562 /* Loop through the pages */
2563 len = instr->len;
2564
2565 instr->state = MTD_ERASING;
2566
2567 while (len) {
8b6e50c9 2568 /* Heck if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2569 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2570 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2571 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2572 __func__, page);
1da177e4
LT		 2573 instr->state = MTD_ERASE_FAILED;
2574 goto erase_exit;
2575 }
61b03bd7 2576
ace4dfee
TG		 2577 /*
2578 * Invalidate the page cache, if we erase the block which
8b6e50c9 2579 * contains the current cached page.
ace4dfee
TG		 2580 */
2581 if (page <= chip->pagebuf && chip->pagebuf <
2582 (page + pages_per_block))
2583 chip->pagebuf = -1;
1da177e4 2584
ace4dfee 2585 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2586
7bc3312b 2587 status = chip->waitfunc(mtd, chip);
1da177e4 2588
ace4dfee
TG		 2589 /*
2590 * See if operation failed and additional status checks are
2591 * available
2592 */
2593 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2594 status = chip->errstat(mtd, chip, FL_ERASING,
2595 status, page);
068e3c0a 2596
1da177e4 2597 /* See if block erase succeeded */
a4ab4c5d 2598 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2599 pr_debug("%s: failed erase, page 0x%08x\n",
2600 __func__, page);
1da177e4 2601 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2602 instr->fail_addr =
2603 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2604 goto erase_exit;
2605 }
30f464b7 2606
ace4dfee
TG		 2607 /*
2608 * If BBT requires refresh, set the BBT rewrite flag to the
8b6e50c9 2609 * page being erased.
ace4dfee
TG		 2610 */
2611 if (bbt_masked_page != 0xffffffff &&
2612 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2613 rewrite_bbt[chipnr] =
2614 ((loff_t)page << chip->page_shift);
61b03bd7 2615
1da177e4 2616 /* Increment page address and decrement length */
ace4dfee 2617 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2618 page += pages_per_block;
2619
2620 /* Check, if we cross a chip boundary */
ace4dfee 2621 if (len && !(page & chip->pagemask)) {
1da177e4 2622 chipnr++;
ace4dfee
TG		 2623 chip->select_chip(mtd, -1);
2624 chip->select_chip(mtd, chipnr);
30f464b7 2625
ace4dfee
TG		 2626 /*
2627 * If BBT requires refresh and BBT-PERCHIP, set the BBT
8b6e50c9 2628 * page mask to see if this BBT should be rewritten.
ace4dfee
TG		 2629 */
2630 if (bbt_masked_page != 0xffffffff &&
2631 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2632 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2633 BBT_PAGE_MASK;
1da177e4
LT		 2634 }
2635 }
2636 instr->state = MTD_ERASE_DONE;
2637
7351d3a5 2638erase_exit:
1da177e4
LT		 2639
2640 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2641
2642 /* Deselect and wake up anyone waiting on the device */
2643 nand_release_device(mtd);
2644
49defc01
DW		 2645 /* Do call back function */
2646 if (!ret)
2647 mtd_erase_callback(instr);
2648
ace4dfee
TG		 2649 /*
2650 * If BBT requires refresh and erase was successful, rewrite any
8b6e50c9 2651 * selected bad block tables.
ace4dfee
TG		 2652 */
2653 if (bbt_masked_page == 0xffffffff || ret)
2654 return ret;
2655
2656 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2657 if (!rewrite_bbt[chipnr])
2658 continue;
8b6e50c9 2659 /* Update the BBT for chip */
289c0522
BN		 2660 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2661 __func__, chipnr, rewrite_bbt[chipnr],
2662 chip->bbt_td->pages[chipnr]);
ace4dfee 2663 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2664 }
2665
1da177e4
LT		 2666 /* Return more or less happy */
2667 return ret;
2668}
2669
2670/**
2671 * nand_sync - [MTD Interface] sync
8b6e50c9 2672 * @mtd: MTD device structure
1da177e4 2673 *
8b6e50c9 2674 * Sync is actually a wait for chip ready function.
1da177e4 2675 */
e0c7d767 2676static void nand_sync(struct mtd_info *mtd)
1da177e4 2677{
ace4dfee 2678 struct nand_chip *chip = mtd->priv;
1da177e4 2679
289c0522 2680 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2681
2682 /* Grab the lock and see if the device is available */
ace4dfee 2683 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2684 /* Release it and go back */
e0c7d767 2685 nand_release_device(mtd);
1da177e4
LT		 2686}
2687
1da177e4 2688/**
ace4dfee 2689 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2690 * @mtd: MTD device structure
2691 * @offs: offset relative to mtd start
1da177e4 2692 */
ace4dfee 2693static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2694{
2695 /* Check for invalid offset */
ace4dfee 2696 if (offs > mtd->size)
1da177e4 2697 return -EINVAL;
61b03bd7 2698
ace4dfee 2699 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2700}
2701
2702/**
ace4dfee 2703 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2704 * @mtd: MTD device structure
2705 * @ofs: offset relative to mtd start
1da177e4 2706 */
e0c7d767 2707static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2708{
ace4dfee 2709 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2710 int ret;
2711
f8ac0414
FF		 2712 ret = nand_block_isbad(mtd, ofs);
2713 if (ret) {
8b6e50c9 2714 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2715 if (ret > 0)
2716 return 0;
e0c7d767
DW		 2717 return ret;
2718 }
1da177e4 2719
ace4dfee 2720 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2721}
2722
962034f4
VW		 2723/**
2724 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2725 * @mtd: MTD device structure
962034f4
VW		 2726 */
2727static int nand_suspend(struct mtd_info *mtd)
2728{
ace4dfee 2729 struct nand_chip *chip = mtd->priv;
962034f4 2730
ace4dfee 2731 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2732}
2733
2734/**
2735 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2736 * @mtd: MTD device structure
962034f4
VW		 2737 */
2738static void nand_resume(struct mtd_info *mtd)
2739{
ace4dfee 2740 struct nand_chip *chip = mtd->priv;
962034f4 2741
ace4dfee 2742 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2743 nand_release_device(mtd);
2744 else
d0370219
BN		 2745 pr_err("%s called for a chip which is not in suspended state\n",
2746 __func__);
962034f4
VW		 2747}
2748
8b6e50c9 2749/* Set default functions */
ace4dfee 2750static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2751{
1da177e4 2752 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2753 if (!chip->chip_delay)
2754 chip->chip_delay = 20;
1da177e4
LT		 2755
2756 /* check, if a user supplied command function given */
ace4dfee
TG		 2757 if (chip->cmdfunc == NULL)
2758 chip->cmdfunc = nand_command;
1da177e4
LT		 2759
2760 /* check, if a user supplied wait function given */
ace4dfee
TG		 2761 if (chip->waitfunc == NULL)
2762 chip->waitfunc = nand_wait;
2763
2764 if (!chip->select_chip)
2765 chip->select_chip = nand_select_chip;
2766 if (!chip->read_byte)
2767 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2768 if (!chip->read_word)
2769 chip->read_word = nand_read_word;
2770 if (!chip->block_bad)
2771 chip->block_bad = nand_block_bad;
2772 if (!chip->block_markbad)
2773 chip->block_markbad = nand_default_block_markbad;
2774 if (!chip->write_buf)
2775 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2776 if (!chip->read_buf)
2777 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2778 if (!chip->verify_buf)
2779 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2780 if (!chip->scan_bbt)
2781 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2782
2783 if (!chip->controller) {
2784 chip->controller = &chip->hwcontrol;
2785 spin_lock_init(&chip->controller->lock);
2786 init_waitqueue_head(&chip->controller->wq);
2787 }
2788
7aa65bfd
TG		 2789}
2790
8b6e50c9 2791/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2792static void sanitize_string(uint8_t *s, size_t len)
2793{
2794 ssize_t i;
2795
8b6e50c9 2796 /* Null terminate */
d1e1f4e4
FF		 2797 s[len - 1] = 0;
2798
8b6e50c9 2799 /* Remove non printable chars */
d1e1f4e4
FF		 2800 for (i = 0; i < len - 1; i++) {
2801 if (s[i] < ' ' || s[i] > 127)
2802 s[i] = '?';
2803 }
2804
8b6e50c9 2805 /* Remove trailing spaces */
d1e1f4e4
FF		 2806 strim(s);
2807}
2808
2809static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2810{
2811 int i;
2812 while (len--) {
2813 crc ^= *p++ << 8;
2814 for (i = 0; i < 8; i++)
2815 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2816 }
2817
2818 return crc;
2819}
2820
6fb277ba 2821/*
8b6e50c9 2822 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2823 */
2824static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2825 int *busw)
6fb277ba
FF		 2826{
2827 struct nand_onfi_params *p = &chip->onfi_params;
2828 int i;
2829 int val;
2830
7854d3f7 2831 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2832 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2833 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2834 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2835 return 0;
2836
9a4d4d69 2837 pr_info("ONFI flash detected\n");
6fb277ba
FF		 2838 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2839 for (i = 0; i < 3; i++) {
2840 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2841 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2842 le16_to_cpu(p->crc)) {
9a4d4d69 2843 pr_info("ONFI param page %d valid\n", i);
6fb277ba
FF		 2844 break;
2845 }
2846 }
2847
2848 if (i == 3)
2849 return 0;
2850
8b6e50c9 2851 /* Check version */
6fb277ba 2852 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2853 if (val & (1 << 5))
2854 chip->onfi_version = 23;
2855 else if (val & (1 << 4))
6fb277ba
FF		 2856 chip->onfi_version = 22;
2857 else if (val & (1 << 3))
2858 chip->onfi_version = 21;
2859 else if (val & (1 << 2))
2860 chip->onfi_version = 20;
b7b1a29d 2861 else if (val & (1 << 1))
6fb277ba 2862 chip->onfi_version = 10;
b7b1a29d
BN		 2863 else
2864 chip->onfi_version = 0;
2865
2866 if (!chip->onfi_version) {
d0370219 2867 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 2868 return 0;
2869 }
6fb277ba
FF		 2870
2871 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2872 sanitize_string(p->model, sizeof(p->model));
2873 if (!mtd->name)
2874 mtd->name = p->model;
2875 mtd->writesize = le32_to_cpu(p->byte_per_page);
2876 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2877 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4ccb3b44 2878 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
08c248fb 2879 *busw = 0;
6fb277ba 2880 if (le16_to_cpu(p->features) & 1)
08c248fb 2881 *busw = NAND_BUSWIDTH_16;
6fb277ba
FF		 2882
2883 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2884 chip->options |= (NAND_NO_READRDY |
2885 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2886
2887 return 1;
2888}
2889
7aa65bfd 2890/*
8b6e50c9 2891 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 2892 */
2893static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2894 struct nand_chip *chip,
7351d3a5
FF		 2895 int busw,
2896 int *maf_id, int *dev_id,
5e81e88a 2897 struct nand_flash_dev *type)
7aa65bfd 2898{
d1e1f4e4 2899 int i, maf_idx;
426c457a 2900 u8 id_data[8];
6fb277ba 2901 int ret;
1da177e4
LT		 2902
2903 /* Select the device */
ace4dfee 2904 chip->select_chip(mtd, 0);
1da177e4 2905
ef89a880
KB		 2906 /*
2907 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 2908 * after power-up.
ef89a880
KB		 2909 */
2910 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2911
1da177e4 2912 /* Send the command for reading device ID */
ace4dfee 2913 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2914
2915 /* Read manufacturer and device IDs */
ace4dfee 2916 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2917 *dev_id = chip->read_byte(mtd);
1da177e4 2918
8b6e50c9
BN		 2919 /*
2920 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 2921 * interface concerns can cause random data which looks like a
2922 * possibly credible NAND flash to appear. If the two results do
2923 * not match, ignore the device completely.
2924 */
2925
2926 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2927
d1e1f4e4 2928 for (i = 0; i < 2; i++)
426c457a 2929 id_data[i] = chip->read_byte(mtd);
ed8165c7 2930
d1e1f4e4 2931 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 2932 pr_info("%s: second ID read did not match "
d0370219
BN		 2933 "%02x,%02x against %02x,%02x\n", __func__,
2934 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2935 return ERR_PTR(-ENODEV);
2936 }
2937
7aa65bfd 2938 if (!type)
5e81e88a
DW		 2939 type = nand_flash_ids;
2940
2941 for (; type->name != NULL; type++)
d1e1f4e4 2942 if (*dev_id == type->id)
f8ac0414 2943 break;
5e81e88a 2944
d1e1f4e4
FF		 2945 chip->onfi_version = 0;
2946 if (!type->name || !type->pagesize) {
6fb277ba 2947 /* Check is chip is ONFI compliant */
08c248fb 2948 ret = nand_flash_detect_onfi(mtd, chip, &busw);
6fb277ba
FF		 2949 if (ret)
2950 goto ident_done;
d1e1f4e4
FF		 2951 }
2952
2953 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2954
2955 /* Read entire ID string */
2956
2957 for (i = 0; i < 8; i++)
2958 id_data[i] = chip->read_byte(mtd);
2959
5e81e88a 2960 if (!type->name)
7aa65bfd
TG		 2961 return ERR_PTR(-ENODEV);
2962
ba0251fe
TG		 2963 if (!mtd->name)
2964 mtd->name = type->name;
2965
69423d99 2966 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 2967
12a40a57 2968 if (!type->pagesize && chip->init_size) {
8b6e50c9 2969 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 2970 busw = chip->init_size(mtd, chip, id_data);
2971 } else if (!type->pagesize) {
7aa65bfd 2972 int extid;
29072b96 2973 /* The 3rd id byte holds MLC / multichip data */
426c457a 2974 chip->cellinfo = id_data[2];
7aa65bfd 2975 /* The 4th id byte is the important one */
426c457a 2976 extid = id_data[3];
61b03bd7 2977
426c457a
KC		 2978 /*
2979 * Field definitions are in the following datasheets:
2980 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 2981 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 2982 *
2983 * Check for wraparound + Samsung ID + nonzero 6th byte
2984 * to decide what to do.
2985 */
2986 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2987 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 2988 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 2989 id_data[5] != 0x00) {
2990 /* Calc pagesize */
2991 mtd->writesize = 2048 << (extid & 0x03);
2992 extid >>= 2;
2993 /* Calc oobsize */
34c5bf6c
BN		 2994 switch (extid & 0x03) {
2995 case 1:
2996 mtd->oobsize = 128;
2997 break;
2998 case 2:
2999 mtd->oobsize = 218;
3000 break;
3001 case 3:
3002 mtd->oobsize = 400;
3003 break;
3004 default:
3005 mtd->oobsize = 436;
3006 break;
3007 }
426c457a
KC		 3008 extid >>= 2;
3009 /* Calc blocksize */
3010 mtd->erasesize = (128 * 1024) <<
3011 (((extid >> 1) & 0x04) | (extid & 0x03));
3012 busw = 0;
3013 } else {
3014 /* Calc pagesize */
3015 mtd->writesize = 1024 << (extid & 0x03);
3016 extid >>= 2;
3017 /* Calc oobsize */
3018 mtd->oobsize = (8 << (extid & 0x01)) *
3019 (mtd->writesize >> 9);
3020 extid >>= 2;
3021 /* Calc blocksize. Blocksize is multiples of 64KiB */
3022 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3023 extid >>= 2;
3024 /* Get buswidth information */
3025 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3026 }
7aa65bfd
TG		 3027 } else {
3028 /*
8b6e50c9 3029 * Old devices have chip data hardcoded in the device id table.
7aa65bfd 3030 */
ba0251fe
TG		 3031 mtd->erasesize = type->erasesize;
3032 mtd->writesize = type->pagesize;
4cbb9b80 3033 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3034 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3035
3036 /*
3037 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3038 * some Spansion chips have erasesize that conflicts with size
8b6e50c9 3039 * listed in nand_ids table.
2173bae8
BN		 3040 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3041 */
3042 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3043 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3044 id_data[7] == 0x00 && mtd->writesize == 512) {
3045 mtd->erasesize = 128 * 1024;
3046 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3047 }
7aa65bfd 3048 }
d1e1f4e4
FF		 3049 /* Get chip options, preserve non chip based options */
3050 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3051 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3052
8b6e50c9
BN		 3053 /*
3054 * Check if chip is not a Samsung device. Do not clear the
3055 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3056 */
3057 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3058 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3059ident_done:
3060
3061 /*
8b6e50c9 3062 * Set chip as a default. Board drivers can override it, if necessary.
d1e1f4e4
FF		 3063 */
3064 chip->options |= NAND_NO_AUTOINCR;
1da177e4 3065
7aa65bfd 3066 /* Try to identify manufacturer */
9a909867 3067 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3068 if (nand_manuf_ids[maf_idx].id == *maf_id)
3069 break;
3070 }
0ea4a755 3071
7aa65bfd
TG		 3072 /*
3073 * Check, if buswidth is correct. Hardware drivers should set
8b6e50c9 3074 * chip correct!
7aa65bfd 3075 */
ace4dfee 3076 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
9a4d4d69 3077 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 3078 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3079 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 3080 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 3081 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3082 busw ? 16 : 8);
7aa65bfd
TG		 3083 return ERR_PTR(-EINVAL);
3084 }
61b03bd7 3085
7aa65bfd 3086 /* Calculate the address shift from the page size */
ace4dfee 3087 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3088 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3089 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3090
ace4dfee 3091 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3092 ffs(mtd->erasesize) - 1;
69423d99
AH		 3093 if (chip->chipsize & 0xffffffff)
3094 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3095 else {
3096 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3097 chip->chip_shift += 32 - 1;
3098 }
1da177e4 3099
26d9be11
AB		 3100 chip->badblockbits = 8;
3101
7aa65bfd 3102 /* Set the bad block position */
065a1ed8 3103 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3104 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3105 else
3106 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3107
b60b08b0
KC		 3108 /*
3109 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3110 * on Samsung and Hynix MLC devices; stored in first two pages
3111 * of each block on Micron devices with 2KiB pages and on
13ed7aed
BN		 3112 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3113 * only the first page.
b60b08b0
KC		 3114 */
3115 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3116 (*maf_id == NAND_MFR_SAMSUNG ||
3117 *maf_id == NAND_MFR_HYNIX))
5fb1549d 3118 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3119 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3120 (*maf_id == NAND_MFR_SAMSUNG ||
3121 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3122 *maf_id == NAND_MFR_TOSHIBA ||
c7b28e25
BN		 3123 *maf_id == NAND_MFR_AMD)) ||
3124 (mtd->writesize == 2048 &&
3125 *maf_id == NAND_MFR_MICRON))
5fb1549d 3126 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
c7b28e25 3127
7aa65bfd 3128 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3129 if (chip->options & NAND_4PAGE_ARRAY)
3130 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3131 else
ace4dfee 3132 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3133
8b6e50c9 3134 /* Do not replace user supplied command function! */
ace4dfee
TG		 3135 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3136 chip->cmdfunc = nand_command_lp;
7aa65bfd 3137
9a4d4d69 3138 pr_info("NAND device: Manufacturer ID:"
d1e1f4e4
FF		 3139 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3140 nand_manuf_ids[maf_idx].name,
0b524fb9 3141 chip->onfi_version ? chip->onfi_params.model : type->name);
7aa65bfd
TG		 3142
3143 return type;
3144}
3145
7aa65bfd 3146/**
3b85c321 3147 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3148 * @mtd: MTD device structure
3149 * @maxchips: number of chips to scan for
3150 * @table: alternative NAND ID table
7aa65bfd 3151 *
8b6e50c9
BN		 3152 * This is the first phase of the normal nand_scan() function. It reads the
3153 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3154 *
3b85c321 3155 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3156 */
5e81e88a
DW		 3157int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3158 struct nand_flash_dev *table)
7aa65bfd 3159{
d1e1f4e4 3160 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3161 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3162 struct nand_flash_dev *type;
3163
7aa65bfd 3164 /* Get buswidth to select the correct functions */
ace4dfee 3165 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3166 /* Set the default functions */
ace4dfee 3167 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3168
3169 /* Read the flash type */
7351d3a5
FF		 3170 type = nand_get_flash_type(mtd, chip, busw,
3171 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3172
3173 if (IS_ERR(type)) {
b1c6e6db 3174 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3175 pr_warn("No NAND device found\n");
ace4dfee 3176 chip->select_chip(mtd, -1);
7aa65bfd 3177 return PTR_ERR(type);
1da177e4
LT		 3178 }
3179
7aa65bfd 3180 /* Check for a chip array */
e0c7d767 3181 for (i = 1; i < maxchips; i++) {
ace4dfee 3182 chip->select_chip(mtd, i);
ef89a880
KB		 3183 /* See comment in nand_get_flash_type for reset */
3184 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3185 /* Send the command for reading device ID */
ace4dfee 3186 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3187 /* Read manufacturer and device IDs */
ace4dfee 3188 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3189 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3190 break;
3191 }
3192 if (i > 1)
9a4d4d69 3193 pr_info("%d NAND chips detected\n", i);
61b03bd7 3194
1da177e4 3195 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3196 chip->numchips = i;
3197 mtd->size = i * chip->chipsize;
7aa65bfd 3198
3b85c321
DW		 3199 return 0;
3200}
7351d3a5 3201EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3202
3203
3204/**
3205 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3206 * @mtd: MTD device structure
3b85c321 3207 *
8b6e50c9
BN		 3208 * This is the second phase of the normal nand_scan() function. It fills out
3209 * all the uninitialized function pointers with the defaults and scans for a
3210 * bad block table if appropriate.
3b85c321
DW		 3211 */
3212int nand_scan_tail(struct mtd_info *mtd)
3213{
3214 int i;
3215 struct nand_chip *chip = mtd->priv;
3216
4bf63fcb
DW		 3217 if (!(chip->options & NAND_OWN_BUFFERS))
3218 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3219 if (!chip->buffers)
3220 return -ENOMEM;
3221
7dcdcbef 3222 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3223 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3224
7aa65bfd 3225 /*
8b6e50c9 3226 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3227 */
193bd400 3228 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3229 switch (mtd->oobsize) {
1da177e4 3230 case 8:
5bd34c09 3231 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3232 break;
3233 case 16:
5bd34c09 3234 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3235 break;
3236 case 64:
5bd34c09 3237 chip->ecc.layout = &nand_oob_64;
1da177e4 3238 break;
81ec5364
TG		 3239 case 128:
3240 chip->ecc.layout = &nand_oob_128;
3241 break;
1da177e4 3242 default:
d0370219
BN		 3243 pr_warn("No oob scheme defined for oobsize %d\n",
3244 mtd->oobsize);
1da177e4
LT		 3245 BUG();
3246 }
3247 }
61b03bd7 3248
956e944c
DW		 3249 if (!chip->write_page)
3250 chip->write_page = nand_write_page;
3251
61b03bd7 3252 /*
8b6e50c9 3253 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3254 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3255 */
956e944c 3256
ace4dfee 3257 switch (chip->ecc.mode) {
6e0cb135
SN		 3258 case NAND_ECC_HW_OOB_FIRST:
3259 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3260 if (!chip->ecc.calculate || !chip->ecc.correct ||
3261 !chip->ecc.hwctl) {
9a4d4d69 3262 pr_warn("No ECC functions supplied; "
d0370219 3263 "hardware ECC not possible\n");
6e0cb135
SN		 3264 BUG();
3265 }
3266 if (!chip->ecc.read_page)
3267 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3268
6dfc6d25 3269 case NAND_ECC_HW:
8b6e50c9 3270 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3271 if (!chip->ecc.read_page)
3272 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3273 if (!chip->ecc.write_page)
3274 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3275 if (!chip->ecc.read_page_raw)
3276 chip->ecc.read_page_raw = nand_read_page_raw;
3277 if (!chip->ecc.write_page_raw)
3278 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3279 if (!chip->ecc.read_oob)
3280 chip->ecc.read_oob = nand_read_oob_std;
3281 if (!chip->ecc.write_oob)
3282 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3283
6dfc6d25 3284 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3285 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3286 !chip->ecc.hwctl) &&
3287 (!chip->ecc.read_page ||
1c45f604 3288 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3289 !chip->ecc.write_page ||
1c45f604 3290 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 3291 pr_warn("No ECC functions supplied; "
d0370219 3292 "hardware ECC not possible\n");
6dfc6d25
TG		 3293 BUG();
3294 }
8b6e50c9 3295 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3296 if (!chip->ecc.read_page)
3297 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3298 if (!chip->ecc.write_page)
3299 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3300 if (!chip->ecc.read_page_raw)
3301 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3302 if (!chip->ecc.write_page_raw)
3303 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3304 if (!chip->ecc.read_oob)
3305 chip->ecc.read_oob = nand_read_oob_syndrome;
3306 if (!chip->ecc.write_oob)
3307 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3308
ace4dfee 3309 if (mtd->writesize >= chip->ecc.size)
6dfc6d25 3310 break;
9a4d4d69 3311 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 3312 "%d byte page size, fallback to SW ECC\n",
3313 chip->ecc.size, mtd->writesize);
ace4dfee 3314 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3315
6dfc6d25 3316 case NAND_ECC_SOFT:
ace4dfee
TG		 3317 chip->ecc.calculate = nand_calculate_ecc;
3318 chip->ecc.correct = nand_correct_data;
f5bbdacc 3319 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3320 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3321 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3322 chip->ecc.read_page_raw = nand_read_page_raw;
3323 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3324 chip->ecc.read_oob = nand_read_oob_std;
3325 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3326 if (!chip->ecc.size)
3327 chip->ecc.size = 256;
ace4dfee 3328 chip->ecc.bytes = 3;
1da177e4 3329 break;
61b03bd7 3330
193bd400
ID		 3331 case NAND_ECC_SOFT_BCH:
3332 if (!mtd_nand_has_bch()) {
9a4d4d69 3333 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3334 BUG();
3335 }
3336 chip->ecc.calculate = nand_bch_calculate_ecc;
3337 chip->ecc.correct = nand_bch_correct_data;
3338 chip->ecc.read_page = nand_read_page_swecc;
3339 chip->ecc.read_subpage = nand_read_subpage;
3340 chip->ecc.write_page = nand_write_page_swecc;
3341 chip->ecc.read_page_raw = nand_read_page_raw;
3342 chip->ecc.write_page_raw = nand_write_page_raw;
3343 chip->ecc.read_oob = nand_read_oob_std;
3344 chip->ecc.write_oob = nand_write_oob_std;
3345 /*
3346 * Board driver should supply ecc.size and ecc.bytes values to
3347 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3348 * for details. Otherwise, default to 4 bits for large page
3349 * devices.
193bd400
ID		 3350 */
3351 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3352 chip->ecc.size = 512;
3353 chip->ecc.bytes = 7;
3354 }
3355 chip->ecc.priv = nand_bch_init(mtd,
3356 chip->ecc.size,
3357 chip->ecc.bytes,
3358 &chip->ecc.layout);
3359 if (!chip->ecc.priv) {
9a4d4d69 3360 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3361 BUG();
3362 }
3363 break;
3364
61b03bd7 3365 case NAND_ECC_NONE:
9a4d4d69 3366 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3367 "This is not recommended!\n");
8593fbc6
TG		 3368 chip->ecc.read_page = nand_read_page_raw;
3369 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3370 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3371 chip->ecc.read_page_raw = nand_read_page_raw;
3372 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3373 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3374 chip->ecc.size = mtd->writesize;
3375 chip->ecc.bytes = 0;
1da177e4 3376 break;
956e944c 3377
1da177e4 3378 default:
d0370219 3379 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 3380 BUG();
1da177e4 3381 }
61b03bd7 3382
5bd34c09
TG		 3383 /*
3384 * The number of bytes available for a client to place data into
8b6e50c9 3385 * the out of band area.
5bd34c09
TG		 3386 */
3387 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3388 for (i = 0; chip->ecc.layout->oobfree[i].length
3389 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3390 chip->ecc.layout->oobavail +=
3391 chip->ecc.layout->oobfree[i].length;
1f92267c 3392 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3393
7aa65bfd
TG		 3394 /*
3395 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3396 * mode.
7aa65bfd 3397 */
ace4dfee 3398 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3399 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 3400 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3401 BUG();
1da177e4 3402 }
f5bbdacc 3403 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3404
8b6e50c9 3405 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 3406 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3407 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3408 switch (chip->ecc.steps) {
29072b96
TG		 3409 case 2:
3410 mtd->subpage_sft = 1;
3411 break;
3412 case 4:
3413 case 8:
81ec5364 3414 case 16:
29072b96
TG		 3415 mtd->subpage_sft = 2;
3416 break;
3417 }
3418 }
3419 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3420
04bbd0ea 3421 /* Initialize state */
ace4dfee 3422 chip->state = FL_READY;
1da177e4
LT		 3423
3424 /* De-select the device */
ace4dfee 3425 chip->select_chip(mtd, -1);
1da177e4
LT		 3426
3427 /* Invalidate the pagebuffer reference */
ace4dfee 3428 chip->pagebuf = -1;
1da177e4
LT		 3429
3430 /* Fill in remaining MTD driver data */
3431 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3432 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3433 MTD_CAP_NANDFLASH;
1da177e4
LT		 3434 mtd->erase = nand_erase;
3435 mtd->point = NULL;
3436 mtd->unpoint = NULL;
3437 mtd->read = nand_read;
3438 mtd->write = nand_write;
2af7c653 3439 mtd->panic_write = panic_nand_write;
1da177e4
LT		 3440 mtd->read_oob = nand_read_oob;
3441 mtd->write_oob = nand_write_oob;
1da177e4
LT		 3442 mtd->sync = nand_sync;
3443 mtd->lock = NULL;
3444 mtd->unlock = NULL;
962034f4
VW		 3445 mtd->suspend = nand_suspend;
3446 mtd->resume = nand_resume;
1da177e4
LT		 3447 mtd->block_isbad = nand_block_isbad;
3448 mtd->block_markbad = nand_block_markbad;
cbcab65a 3449 mtd->writebufsize = mtd->writesize;
1da177e4 3450
5bd34c09
TG		 3451 /* propagate ecc.layout to mtd_info */
3452 mtd->ecclayout = chip->ecc.layout;
1da177e4 3453
0040bf38 3454 /* Check, if we should skip the bad block table scan */
ace4dfee 3455 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3456 return 0;
1da177e4
LT		 3457
3458 /* Build bad block table */
ace4dfee 3459 return chip->scan_bbt(mtd);
1da177e4 3460}
7351d3a5 3461EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3462
8b6e50c9
BN		 3463/*
3464 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3465 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3466 * to call us from in-kernel code if the core NAND support is modular.
3467 */
3b85c321
DW		 3468#ifdef MODULE
3469#define caller_is_module() (1)
3470#else
3471#define caller_is_module() \
a6e6abd5 3472 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3473#endif
3474
3475/**
3476 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3477 * @mtd: MTD device structure
3478 * @maxchips: number of chips to scan for
3b85c321 3479 *
8b6e50c9
BN		 3480 * This fills out all the uninitialized function pointers with the defaults.
3481 * The flash ID is read and the mtd/chip structures are filled with the
3482 * appropriate values. The mtd->owner field must be set to the module of the
3483 * caller.
3b85c321
DW		 3484 */
3485int nand_scan(struct mtd_info *mtd, int maxchips)
3486{
3487 int ret;
3488
3489 /* Many callers got this wrong, so check for it for a while... */
3490 if (!mtd->owner && caller_is_module()) {
d0370219 3491 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3492 BUG();
3493 }
3494
5e81e88a 3495 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3496 if (!ret)
3497 ret = nand_scan_tail(mtd);
3498 return ret;
3499}
7351d3a5 3500EXPORT_SYMBOL(nand_scan);
3b85c321 3501
1da177e4 3502/**
61b03bd7 3503 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3504 * @mtd: MTD device structure
3505 */
e0c7d767 3506void nand_release(struct mtd_info *mtd)
1da177e4 3507{
ace4dfee 3508 struct nand_chip *chip = mtd->priv;
1da177e4 3509
193bd400
ID		 3510 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3511 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3512
5ffcaf3d 3513 mtd_device_unregister(mtd);
1da177e4 3514
fa671646 3515 /* Free bad block table memory */
ace4dfee 3516 kfree(chip->bbt);
4bf63fcb
DW		 3517 if (!(chip->options & NAND_OWN_BUFFERS))
3518 kfree(chip->buffers);
58373ff0
BN		 3519
3520 /* Free bad block descriptor memory */
3521 if (chip->badblock_pattern && chip->badblock_pattern->options
3522 & NAND_BBT_DYNAMICSTRUCT)
3523 kfree(chip->badblock_pattern);
1da177e4 3524}
e0c7d767 3525EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3526
3527static int __init nand_base_init(void)
3528{
3529 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3530 return 0;
3531}
3532
3533static void __exit nand_base_exit(void)
3534{
3535 led_trigger_unregister_simple(nand_led_trigger);
3536}
3537
3538module_init(nand_base_init);
3539module_exit(nand_base_exit);
3540
e0c7d767 3541MODULE_LICENSE("GPL");
7351d3a5
FF		 3542MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3543MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3544MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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