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mtd: unify initialization of erase_info->fail_addr
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 24 * if we have HW ECC support.
1da177e4
LT		 25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4 50#include <linux/mtd/partitions.h>
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
ace4dfee 96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 97 int new_state);
1da177e4 98
8593fbc6
TG		 99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
d470a97c 102/*
8e87d782 103 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
6fe5a6ac
VS		 108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 116 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 122 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 123 ret = -EINVAL;
124 }
125
6fe5a6ac
VS		 126 return ret;
127}
128
1da177e4
LT		 129/**
130 * nand_release_device - [GENERIC] release chip
8b6e50c9 131 * @mtd: MTD device structure
61b03bd7 132 *
8b6e50c9 133 * Deselect, release chip lock and wake up anyone waiting on the device.
1da177e4 134 */
e0c7d767 135static void nand_release_device(struct mtd_info *mtd)
1da177e4 136{
ace4dfee 137 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 138
139 /* De-select the NAND device */
ace4dfee 140 chip->select_chip(mtd, -1);
0dfc6246 141
a36ed299 142 /* Release the controller and the chip */
ace4dfee
TG		 143 spin_lock(&chip->controller->lock);
144 chip->controller->active = NULL;
145 chip->state = FL_READY;
146 wake_up(&chip->controller->wq);
147 spin_unlock(&chip->controller->lock);
1da177e4
LT		 148}
149
150/**
151 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 152 * @mtd: MTD device structure
1da177e4 153 *
7854d3f7 154 * Default read function for 8bit buswidth
1da177e4 155 */
58dd8f2b 156static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 157{
ace4dfee
TG		 158 struct nand_chip *chip = mtd->priv;
159 return readb(chip->IO_ADDR_R);
1da177e4
LT		 160}
161
1da177e4
LT		 162/**
163 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
7854d3f7 164 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 165 * @mtd: MTD device structure
1da177e4 166 *
7854d3f7
BN		 167 * Default read function for 16bit buswidth with endianness conversion.
168 *
1da177e4 169 */
58dd8f2b 170static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 171{
ace4dfee
TG		 172 struct nand_chip *chip = mtd->priv;
173 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 174}
175
1da177e4
LT		 176/**
177 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 178 * @mtd: MTD device structure
1da177e4 179 *
7854d3f7 180 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 181 */
182static u16 nand_read_word(struct mtd_info *mtd)
183{
ace4dfee
TG		 184 struct nand_chip *chip = mtd->priv;
185 return readw(chip->IO_ADDR_R);
1da177e4
LT		 186}
187
1da177e4
LT		 188/**
189 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 190 * @mtd: MTD device structure
191 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 192 *
193 * Default select function for 1 chip devices.
194 */
ace4dfee 195static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 196{
ace4dfee
TG		 197 struct nand_chip *chip = mtd->priv;
198
199 switch (chipnr) {
1da177e4 200 case -1:
ace4dfee 201 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 202 break;
203 case 0:
1da177e4
LT		 204 break;
205
206 default:
207 BUG();
208 }
209}
210
211/**
212 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 213 * @mtd: MTD device structure
214 * @buf: data buffer
215 * @len: number of bytes to write
1da177e4 216 *
7854d3f7 217 * Default write function for 8bit buswidth.
1da177e4 218 */
58dd8f2b 219static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 220{
221 int i;
ace4dfee 222 struct nand_chip *chip = mtd->priv;
1da177e4 223
e0c7d767 224 for (i = 0; i < len; i++)
ace4dfee 225 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 226}
227
228/**
61b03bd7 229 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
1da177e4 233 *
7854d3f7 234 * Default read function for 8bit buswidth.
1da177e4 235 */
58dd8f2b 236static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 237{
238 int i;
ace4dfee 239 struct nand_chip *chip = mtd->priv;
1da177e4 240
e0c7d767 241 for (i = 0; i < len; i++)
ace4dfee 242 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 243}
244
245/**
61b03bd7 246 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 247 * @mtd: MTD device structure
248 * @buf: buffer containing the data to compare
249 * @len: number of bytes to compare
1da177e4 250 *
7854d3f7 251 * Default verify function for 8bit buswidth.
1da177e4 252 */
58dd8f2b 253static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 254{
255 int i;
ace4dfee 256 struct nand_chip *chip = mtd->priv;
1da177e4 257
e0c7d767 258 for (i = 0; i < len; i++)
ace4dfee 259 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 260 return -EFAULT;
1da177e4
LT		 261 return 0;
262}
263
264/**
265 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 266 * @mtd: MTD device structure
267 * @buf: data buffer
268 * @len: number of bytes to write
1da177e4 269 *
7854d3f7 270 * Default write function for 16bit buswidth.
1da177e4 271 */
58dd8f2b 272static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 273{
274 int i;
ace4dfee 275 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 276 u16 *p = (u16 *) buf;
277 len >>= 1;
61b03bd7 278
e0c7d767 279 for (i = 0; i < len; i++)
ace4dfee 280 writew(p[i], chip->IO_ADDR_W);
61b03bd7 281
1da177e4
LT		 282}
283
284/**
61b03bd7 285 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 286 * @mtd: MTD device structure
287 * @buf: buffer to store date
288 * @len: number of bytes to read
1da177e4 289 *
7854d3f7 290 * Default read function for 16bit buswidth.
1da177e4 291 */
58dd8f2b 292static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 293{
294 int i;
ace4dfee 295 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 296 u16 *p = (u16 *) buf;
297 len >>= 1;
298
e0c7d767 299 for (i = 0; i < len; i++)
ace4dfee 300 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 301}
302
303/**
61b03bd7 304 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 305 * @mtd: MTD device structure
306 * @buf: buffer containing the data to compare
307 * @len: number of bytes to compare
1da177e4 308 *
7854d3f7 309 * Default verify function for 16bit buswidth.
1da177e4 310 */
58dd8f2b 311static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 312{
313 int i;
ace4dfee 314 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 315 u16 *p = (u16 *) buf;
316 len >>= 1;
317
e0c7d767 318 for (i = 0; i < len; i++)
ace4dfee 319 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 320 return -EFAULT;
321
322 return 0;
323}
324
325/**
326 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 327 * @mtd: MTD device structure
328 * @ofs: offset from device start
329 * @getchip: 0, if the chip is already selected
1da177e4 330 *
61b03bd7 331 * Check, if the block is bad.
1da177e4
LT		 332 */
333static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
334{
cdbec050 335 int page, chipnr, res = 0, i = 0;
ace4dfee 336 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 337 u16 bad;
338
5fb1549d 339 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 340 ofs += mtd->erasesize - mtd->writesize;
341
1a12f46a
TK		 342 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
343
1da177e4 344 if (getchip) {
ace4dfee 345 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 346
ace4dfee 347 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 348
349 /* Select the NAND device */
ace4dfee 350 chip->select_chip(mtd, chipnr);
1a12f46a 351 }
1da177e4 352
cdbec050
BN		 353 do {
354 if (chip->options & NAND_BUSWIDTH_16) {
355 chip->cmdfunc(mtd, NAND_CMD_READOOB,
356 chip->badblockpos & 0xFE, page);
357 bad = cpu_to_le16(chip->read_word(mtd));
358 if (chip->badblockpos & 0x1)
359 bad >>= 8;
360 else
361 bad &= 0xFF;
362 } else {
363 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
364 page);
365 bad = chip->read_byte(mtd);
366 }
367
368 if (likely(chip->badblockbits == 8))
369 res = bad != 0xFF;
e0b58d0a 370 else
cdbec050
BN		 371 res = hweight8(bad) < chip->badblockbits;
372 ofs += mtd->writesize;
373 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
374 i++;
375 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 376
ace4dfee 377 if (getchip)
1da177e4 378 nand_release_device(mtd);
61b03bd7 379
1da177e4
LT		 380 return res;
381}
382
383/**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 385 * @mtd: MTD device structure
386 * @ofs: offset from device start
1da177e4 387 *
8b6e50c9 388 * This is the default implementation, which can be overridden by a hardware
e2414f4c
BN		 389 * specific driver. We try operations in the following order, according to our
390 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
391 * (1) erase the affected block, to allow OOB marker to be written cleanly
392 * (2) update in-memory BBT
393 * (3) write bad block marker to OOB area of affected block
394 * (4) update flash-based BBT
395 * Note that we retain the first error encountered in (3) or (4), finish the
396 * procedures, and dump the error in the end.
1da177e4
LT		 397*/
398static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
399{
ace4dfee 400 struct nand_chip *chip = mtd->priv;
58dd8f2b 401 uint8_t buf[2] = { 0, 0 };
e2414f4c
BN		 402 int block, res, ret = 0, i = 0;
403 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
61b03bd7 404
e2414f4c 405 if (write_oob) {
00918429
BN		 406 struct erase_info einfo;
407
408 /* Attempt erase before marking OOB */
409 memset(&einfo, 0, sizeof(einfo));
410 einfo.mtd = mtd;
411 einfo.addr = ofs;
412 einfo.len = 1 << chip->phys_erase_shift;
413 nand_erase_nand(mtd, &einfo, 0);
414 }
415
1da177e4 416 /* Get block number */
4226b510 417 block = (int)(ofs >> chip->bbt_erase_shift);
e2414f4c 418 /* Mark block bad in memory-based BBT */
ace4dfee
TG		 419 if (chip->bbt)
420 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 421
e2414f4c
BN		 422 /* Write bad block marker to OOB */
423 if (write_oob) {
4a89ff88 424 struct mtd_oob_ops ops;
df698621 425 loff_t wr_ofs = ofs;
4a89ff88 426
c0b8ba7b 427 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 428
4a89ff88
BN		 429 ops.datbuf = NULL;
430 ops.oobbuf = buf;
85443319
BN		 431 ops.ooboffs = chip->badblockpos;
432 if (chip->options & NAND_BUSWIDTH_16) {
433 ops.ooboffs &= ~0x01;
434 ops.len = ops.ooblen = 2;
435 } else {
436 ops.len = ops.ooblen = 1;
437 }
23b1a99b 438 ops.mode = MTD_OPS_PLACE_OOB;
df698621 439
e2414f4c 440 /* Write to first/last page(s) if necessary */
df698621
BN		 441 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
442 wr_ofs += mtd->erasesize - mtd->writesize;
02ed70bb 443 do {
e2414f4c
BN		 444 res = nand_do_write_oob(mtd, wr_ofs, &ops);
445 if (!ret)
446 ret = res;
02ed70bb 447
02ed70bb 448 i++;
df698621 449 wr_ofs += mtd->writesize;
e2414f4c 450 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
02ed70bb 451
c0b8ba7b 452 nand_release_device(mtd);
f1a28c02 453 }
e2414f4c
BN		 454
455 /* Update flash-based bad block table */
456 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
457 res = nand_update_bbt(mtd, ofs);
458 if (!ret)
459 ret = res;
460 }
461
f1a28c02
TG		 462 if (!ret)
463 mtd->ecc_stats.badblocks++;
c0b8ba7b 464
f1a28c02 465 return ret;
1da177e4
LT		 466}
467
61b03bd7 468/**
1da177e4 469 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 470 * @mtd: MTD device structure
1da177e4 471 *
8b6e50c9
BN		 472 * Check, if the device is write protected. The function expects, that the
473 * device is already selected.
1da177e4 474 */
e0c7d767 475static int nand_check_wp(struct mtd_info *mtd)
1da177e4 476{
ace4dfee 477 struct nand_chip *chip = mtd->priv;
93edbad6 478
8b6e50c9 479 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 480 if (chip->options & NAND_BROKEN_XD)
481 return 0;
482
1da177e4 483 /* Check the WP bit */
ace4dfee
TG		 484 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
485 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 486}
487
488/**
489 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 490 * @mtd: MTD device structure
491 * @ofs: offset from device start
492 * @getchip: 0, if the chip is already selected
493 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 494 *
495 * Check, if the block is bad. Either by reading the bad block table or
496 * calling of the scan function.
497 */
2c0a2bed
TG		 498static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
499 int allowbbt)
1da177e4 500{
ace4dfee 501 struct nand_chip *chip = mtd->priv;
61b03bd7 502
ace4dfee
TG		 503 if (!chip->bbt)
504 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 505
1da177e4 506 /* Return info from the table */
e0c7d767 507 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 508}
509
2af7c653
SK		 510/**
511 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 512 * @mtd: MTD device structure
513 * @timeo: Timeout
2af7c653
SK		 514 *
515 * Helper function for nand_wait_ready used when needing to wait in interrupt
516 * context.
517 */
518static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
519{
520 struct nand_chip *chip = mtd->priv;
521 int i;
522
523 /* Wait for the device to get ready */
524 for (i = 0; i < timeo; i++) {
525 if (chip->dev_ready(mtd))
526 break;
527 touch_softlockup_watchdog();
528 mdelay(1);
529 }
530}
531
7854d3f7 532/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 533void nand_wait_ready(struct mtd_info *mtd)
3b88775c 534{
ace4dfee 535 struct nand_chip *chip = mtd->priv;
e0c7d767 536 unsigned long timeo = jiffies + 2;
3b88775c 537
2af7c653
SK		 538 /* 400ms timeout */
539 if (in_interrupt() || oops_in_progress)
540 return panic_nand_wait_ready(mtd, 400);
541
8fe833c1 542 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 543 /* Wait until command is processed or timeout occurs */
3b88775c 544 do {
ace4dfee 545 if (chip->dev_ready(mtd))
8fe833c1 546 break;
8446f1d3 547 touch_softlockup_watchdog();
61b03bd7 548 } while (time_before(jiffies, timeo));
8fe833c1 549 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 550}
4b648b02 551EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 552
1da177e4
LT		 553/**
554 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 555 * @mtd: MTD device structure
556 * @command: the command to be sent
557 * @column: the column address for this command, -1 if none
558 * @page_addr: the page address for this command, -1 if none
1da177e4 559 *
8b6e50c9
BN		 560 * Send command to NAND device. This function is used for small page devices
561 * (256/512 Bytes per page).
1da177e4 562 */
7abd3ef9
TG		 563static void nand_command(struct mtd_info *mtd, unsigned int command,
564 int column, int page_addr)
1da177e4 565{
ace4dfee 566 register struct nand_chip *chip = mtd->priv;
7abd3ef9 567 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 568
8b6e50c9 569 /* Write out the command to the device */
1da177e4
LT		 570 if (command == NAND_CMD_SEQIN) {
571 int readcmd;
572
28318776 573 if (column >= mtd->writesize) {
1da177e4 574 /* OOB area */
28318776 575 column -= mtd->writesize;
1da177e4
LT		 576 readcmd = NAND_CMD_READOOB;
577 } else if (column < 256) {
578 /* First 256 bytes --> READ0 */
579 readcmd = NAND_CMD_READ0;
580 } else {
581 column -= 256;
582 readcmd = NAND_CMD_READ1;
583 }
ace4dfee 584 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 585 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 586 }
ace4dfee 587 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 588
8b6e50c9 589 /* Address cycle, when necessary */
7abd3ef9
TG		 590 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
591 /* Serially input address */
592 if (column != -1) {
593 /* Adjust columns for 16 bit buswidth */
ace4dfee 594 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 595 column >>= 1;
ace4dfee 596 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 597 ctrl &= ~NAND_CTRL_CHANGE;
598 }
599 if (page_addr != -1) {
ace4dfee 600 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 601 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 602 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 603 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 604 if (chip->chipsize > (32 << 20))
605 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 606 }
ace4dfee 607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 608
609 /*
8b6e50c9
BN		 610 * Program and erase have their own busy handlers status and sequential
611 * in needs no delay
e0c7d767 612 */
1da177e4 613 switch (command) {
61b03bd7 614
1da177e4
LT		 615 case NAND_CMD_PAGEPROG:
616 case NAND_CMD_ERASE1:
617 case NAND_CMD_ERASE2:
618 case NAND_CMD_SEQIN:
619 case NAND_CMD_STATUS:
620 return;
621
622 case NAND_CMD_RESET:
ace4dfee 623 if (chip->dev_ready)
1da177e4 624 break;
ace4dfee
TG		 625 udelay(chip->chip_delay);
626 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 627 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 628 chip->cmd_ctrl(mtd,
629 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 630 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
631 ;
1da177e4
LT		 632 return;
633
e0c7d767 634 /* This applies to read commands */
1da177e4 635 default:
61b03bd7 636 /*
1da177e4
LT		 637 * If we don't have access to the busy pin, we apply the given
638 * command delay
e0c7d767 639 */
ace4dfee
TG		 640 if (!chip->dev_ready) {
641 udelay(chip->chip_delay);
1da177e4 642 return;
61b03bd7 643 }
1da177e4 644 }
8b6e50c9
BN		 645 /*
646 * Apply this short delay always to ensure that we do wait tWB in
647 * any case on any machine.
648 */
e0c7d767 649 ndelay(100);
3b88775c
TG		 650
651 nand_wait_ready(mtd);
1da177e4
LT		 652}
653
654/**
655 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 656 * @mtd: MTD device structure
657 * @command: the command to be sent
658 * @column: the column address for this command, -1 if none
659 * @page_addr: the page address for this command, -1 if none
1da177e4 660 *
7abd3ef9 661 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 662 * devices. We don't have the separate regions as we have in the small page
663 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 664 */
7abd3ef9
TG		 665static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
666 int column, int page_addr)
1da177e4 667{
ace4dfee 668 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 669
670 /* Emulate NAND_CMD_READOOB */
671 if (command == NAND_CMD_READOOB) {
28318776 672 column += mtd->writesize;
1da177e4
LT		 673 command = NAND_CMD_READ0;
674 }
61b03bd7 675
7abd3ef9 676 /* Command latch cycle */
ace4dfee 677 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 678 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 679
680 if (column != -1 || page_addr != -1) {
7abd3ef9 681 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 682
683 /* Serially input address */
684 if (column != -1) {
685 /* Adjust columns for 16 bit buswidth */
ace4dfee 686 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 687 column >>= 1;
ace4dfee 688 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 689 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 690 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 691 }
1da177e4 692 if (page_addr != -1) {
ace4dfee
TG		 693 chip->cmd_ctrl(mtd, page_addr, ctrl);
694 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 695 NAND_NCE | NAND_ALE);
1da177e4 696 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 697 if (chip->chipsize > (128 << 20))
698 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 699 NAND_NCE | NAND_ALE);
1da177e4 700 }
1da177e4 701 }
ace4dfee 702 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 703
704 /*
8b6e50c9
BN		 705 * Program and erase have their own busy handlers status, sequential
706 * in, and deplete1 need no delay.
30f464b7 707 */
1da177e4 708 switch (command) {
61b03bd7 709
1da177e4
LT		 710 case NAND_CMD_CACHEDPROG:
711 case NAND_CMD_PAGEPROG:
712 case NAND_CMD_ERASE1:
713 case NAND_CMD_ERASE2:
714 case NAND_CMD_SEQIN:
7bc3312b 715 case NAND_CMD_RNDIN:
1da177e4 716 case NAND_CMD_STATUS:
30f464b7 717 case NAND_CMD_DEPLETE1:
1da177e4
LT		 718 return;
719
30f464b7
DM		 720 case NAND_CMD_STATUS_ERROR:
721 case NAND_CMD_STATUS_ERROR0:
722 case NAND_CMD_STATUS_ERROR1:
723 case NAND_CMD_STATUS_ERROR2:
724 case NAND_CMD_STATUS_ERROR3:
8b6e50c9 725 /* Read error status commands require only a short delay */
ace4dfee 726 udelay(chip->chip_delay);
30f464b7 727 return;
1da177e4
LT		 728
729 case NAND_CMD_RESET:
ace4dfee 730 if (chip->dev_ready)
1da177e4 731 break;
ace4dfee 732 udelay(chip->chip_delay);
12efdde3
TG		 733 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
735 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
736 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 737 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
738 ;
1da177e4
LT		 739 return;
740
7bc3312b
TG		 741 case NAND_CMD_RNDOUT:
742 /* No ready / busy check necessary */
743 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
744 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
745 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
746 NAND_NCE | NAND_CTRL_CHANGE);
747 return;
748
1da177e4 749 case NAND_CMD_READ0:
12efdde3
TG		 750 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
751 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
752 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
753 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 754
e0c7d767 755 /* This applies to read commands */
1da177e4 756 default:
61b03bd7 757 /*
1da177e4 758 * If we don't have access to the busy pin, we apply the given
8b6e50c9 759 * command delay.
e0c7d767 760 */
ace4dfee
TG		 761 if (!chip->dev_ready) {
762 udelay(chip->chip_delay);
1da177e4 763 return;
61b03bd7 764 }
1da177e4 765 }
3b88775c 766
8b6e50c9
BN		 767 /*
768 * Apply this short delay always to ensure that we do wait tWB in
769 * any case on any machine.
770 */
e0c7d767 771 ndelay(100);
3b88775c
TG		 772
773 nand_wait_ready(mtd);
1da177e4
LT		 774}
775
2af7c653
SK		 776/**
777 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 778 * @chip: the nand chip descriptor
779 * @mtd: MTD device structure
780 * @new_state: the state which is requested
2af7c653
SK		 781 *
782 * Used when in panic, no locks are taken.
783 */
784static void panic_nand_get_device(struct nand_chip *chip,
785 struct mtd_info *mtd, int new_state)
786{
7854d3f7 787 /* Hardware controller shared among independent devices */
2af7c653
SK		 788 chip->controller->active = chip;
789 chip->state = new_state;
790}
791
1da177e4
LT		 792/**
793 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 794 * @chip: the nand chip descriptor
795 * @mtd: MTD device structure
796 * @new_state: the state which is requested
1da177e4
LT		 797 *
798 * Get the device and lock it for exclusive access
799 */
2c0a2bed 800static int
ace4dfee 801nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 802{
ace4dfee
TG		 803 spinlock_t *lock = &chip->controller->lock;
804 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 805 DECLARE_WAITQUEUE(wait, current);
7351d3a5 806retry:
0dfc6246
TG		 807 spin_lock(lock);
808
b8b3ee9a 809 /* Hardware controller shared among independent devices */
ace4dfee
TG		 810 if (!chip->controller->active)
811 chip->controller->active = chip;
a36ed299 812
ace4dfee
TG		 813 if (chip->controller->active == chip && chip->state == FL_READY) {
814 chip->state = new_state;
0dfc6246 815 spin_unlock(lock);
962034f4
VW		 816 return 0;
817 }
818 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 819 if (chip->controller->active->state == FL_PM_SUSPENDED) {
820 chip->state = FL_PM_SUSPENDED;
821 spin_unlock(lock);
822 return 0;
6b0d9a84 823 }
0dfc6246
TG		 824 }
825 set_current_state(TASK_UNINTERRUPTIBLE);
826 add_wait_queue(wq, &wait);
827 spin_unlock(lock);
828 schedule();
829 remove_wait_queue(wq, &wait);
1da177e4
LT		 830 goto retry;
831}
832
2af7c653 833/**
8b6e50c9
BN		 834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
837 * @timeo: timeout
2af7c653
SK		 838 *
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
b595076a 841 * an oops through mtdoops.
2af7c653
SK		 842 */
843static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
844 unsigned long timeo)
845{
846 int i;
847 for (i = 0; i < timeo; i++) {
848 if (chip->dev_ready) {
849 if (chip->dev_ready(mtd))
850 break;
851 } else {
852 if (chip->read_byte(mtd) & NAND_STATUS_READY)
853 break;
854 }
855 mdelay(1);
f8ac0414 856 }
2af7c653
SK		 857}
858
1da177e4 859/**
8b6e50c9
BN		 860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
1da177e4 863 *
8b6e50c9
BN		 864 * Wait for command done. This applies to erase and program only. Erase can
865 * take up to 400ms and program up to 20ms according to general NAND and
866 * SmartMedia specs.
844d3b42 867 */
7bc3312b 868static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 869{
870
e0c7d767 871 unsigned long timeo = jiffies;
7bc3312b 872 int status, state = chip->state;
61b03bd7 873
1da177e4 874 if (state == FL_ERASING)
e0c7d767 875 timeo += (HZ * 400) / 1000;
1da177e4 876 else
e0c7d767 877 timeo += (HZ * 20) / 1000;
1da177e4 878
8fe833c1
RP		 879 led_trigger_event(nand_led_trigger, LED_FULL);
880
8b6e50c9
BN		 881 /*
882 * Apply this short delay always to ensure that we do wait tWB in any
883 * case on any machine.
884 */
e0c7d767 885 ndelay(100);
1da177e4 886
ace4dfee
TG		 887 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
888 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 889 else
ace4dfee 890 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 891
2af7c653
SK		 892 if (in_interrupt() || oops_in_progress)
893 panic_nand_wait(mtd, chip, timeo);
894 else {
895 while (time_before(jiffies, timeo)) {
896 if (chip->dev_ready) {
897 if (chip->dev_ready(mtd))
898 break;
899 } else {
900 if (chip->read_byte(mtd) & NAND_STATUS_READY)
901 break;
902 }
903 cond_resched();
1da177e4 904 }
1da177e4 905 }
8fe833c1
RP		 906 led_trigger_event(nand_led_trigger, LED_OFF);
907
ace4dfee 908 status = (int)chip->read_byte(mtd);
1da177e4
LT		 909 return status;
910}
911
7d70f334 912/**
b6d676db 913 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 914 * @mtd: mtd info
915 * @ofs: offset to start unlock from
916 * @len: length to unlock
8b6e50c9
BN		 917 * @invert: when = 0, unlock the range of blocks within the lower and
918 * upper boundary address
919 * when = 1, unlock the range of blocks outside the boundaries
920 * of the lower and upper boundary address
7d70f334 921 *
8b6e50c9 922 * Returs unlock status.
7d70f334
VS		 923 */
924static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
925 uint64_t len, int invert)
926{
927 int ret = 0;
928 int status, page;
929 struct nand_chip *chip = mtd->priv;
930
931 /* Submit address of first page to unlock */
932 page = ofs >> chip->page_shift;
933 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
934
935 /* Submit address of last page to unlock */
936 page = (ofs + len) >> chip->page_shift;
937 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
938 (page | invert) & chip->pagemask);
939
940 /* Call wait ready function */
941 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 942 /* See if device thinks it succeeded */
943 if (status & 0x01) {
289c0522 944 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 945 __func__, status);
946 ret = -EIO;
947 }
948
949 return ret;
950}
951
952/**
b6d676db 953 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 954 * @mtd: mtd info
955 * @ofs: offset to start unlock from
956 * @len: length to unlock
7d70f334 957 *
8b6e50c9 958 * Returns unlock status.
7d70f334
VS		 959 */
960int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
961{
962 int ret = 0;
963 int chipnr;
964 struct nand_chip *chip = mtd->priv;
965
289c0522 966 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 967 __func__, (unsigned long long)ofs, len);
968
969 if (check_offs_len(mtd, ofs, len))
970 ret = -EINVAL;
971
972 /* Align to last block address if size addresses end of the device */
973 if (ofs + len == mtd->size)
974 len -= mtd->erasesize;
975
976 nand_get_device(chip, mtd, FL_UNLOCKING);
977
978 /* Shift to get chip number */
979 chipnr = ofs >> chip->chip_shift;
980
981 chip->select_chip(mtd, chipnr);
982
983 /* Check, if it is write protected */
984 if (nand_check_wp(mtd)) {
289c0522 985 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 986 __func__);
987 ret = -EIO;
988 goto out;
989 }
990
991 ret = __nand_unlock(mtd, ofs, len, 0);
992
993out:
7d70f334
VS		 994 nand_release_device(mtd);
995
996 return ret;
997}
7351d3a5 998EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 999
1000/**
b6d676db 1001 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 1002 * @mtd: mtd info
1003 * @ofs: offset to start unlock from
1004 * @len: length to unlock
7d70f334 1005 *
8b6e50c9
BN		 1006 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1007 * have this feature, but it allows only to lock all blocks, not for specified
1008 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1009 * now.
7d70f334 1010 *
8b6e50c9 1011 * Returns lock status.
7d70f334
VS		 1012 */
1013int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1014{
1015 int ret = 0;
1016 int chipnr, status, page;
1017 struct nand_chip *chip = mtd->priv;
1018
289c0522 1019 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1020 __func__, (unsigned long long)ofs, len);
1021
1022 if (check_offs_len(mtd, ofs, len))
1023 ret = -EINVAL;
1024
1025 nand_get_device(chip, mtd, FL_LOCKING);
1026
1027 /* Shift to get chip number */
1028 chipnr = ofs >> chip->chip_shift;
1029
1030 chip->select_chip(mtd, chipnr);
1031
1032 /* Check, if it is write protected */
1033 if (nand_check_wp(mtd)) {
289c0522 1034 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1035 __func__);
1036 status = MTD_ERASE_FAILED;
1037 ret = -EIO;
1038 goto out;
1039 }
1040
1041 /* Submit address of first page to lock */
1042 page = ofs >> chip->page_shift;
1043 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1044
1045 /* Call wait ready function */
1046 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 1047 /* See if device thinks it succeeded */
1048 if (status & 0x01) {
289c0522 1049 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1050 __func__, status);
1051 ret = -EIO;
1052 goto out;
1053 }
1054
1055 ret = __nand_unlock(mtd, ofs, len, 0x1);
1056
1057out:
7d70f334
VS		 1058 nand_release_device(mtd);
1059
1060 return ret;
1061}
7351d3a5 1062EXPORT_SYMBOL(nand_lock);
7d70f334 1063
8593fbc6 1064/**
7854d3f7 1065 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1069 * @page: page number to read
52ff49df 1070 *
7854d3f7 1071 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1072 */
1073static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1074 uint8_t *buf, int page)
8593fbc6
TG		 1075{
1076 chip->read_buf(mtd, buf, mtd->writesize);
1077 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1078 return 0;
1079}
1080
52ff49df 1081/**
7854d3f7 1082 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1083 * @mtd: mtd info structure
1084 * @chip: nand chip info structure
1085 * @buf: buffer to store read data
1086 * @page: page number to read
52ff49df
DB		 1087 *
1088 * We need a special oob layout and handling even when OOB isn't used.
1089 */
7351d3a5
FF		 1090static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1091 struct nand_chip *chip,
1092 uint8_t *buf, int page)
52ff49df
DB		 1093{
1094 int eccsize = chip->ecc.size;
1095 int eccbytes = chip->ecc.bytes;
1096 uint8_t *oob = chip->oob_poi;
1097 int steps, size;
1098
1099 for (steps = chip->ecc.steps; steps > 0; steps--) {
1100 chip->read_buf(mtd, buf, eccsize);
1101 buf += eccsize;
1102
1103 if (chip->ecc.prepad) {
1104 chip->read_buf(mtd, oob, chip->ecc.prepad);
1105 oob += chip->ecc.prepad;
1106 }
1107
1108 chip->read_buf(mtd, oob, eccbytes);
1109 oob += eccbytes;
1110
1111 if (chip->ecc.postpad) {
1112 chip->read_buf(mtd, oob, chip->ecc.postpad);
1113 oob += chip->ecc.postpad;
1114 }
1115 }
1116
1117 size = mtd->oobsize - (oob - chip->oob_poi);
1118 if (size)
1119 chip->read_buf(mtd, oob, size);
1120
1121 return 0;
1122}
1123
1da177e4 1124/**
7854d3f7 1125 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1126 * @mtd: mtd info structure
1127 * @chip: nand chip info structure
1128 * @buf: buffer to store read data
1129 * @page: page number to read
068e3c0a 1130 */
f5bbdacc 1131static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1132 uint8_t *buf, int page)
1da177e4 1133{
f5bbdacc
TG		 1134 int i, eccsize = chip->ecc.size;
1135 int eccbytes = chip->ecc.bytes;
1136 int eccsteps = chip->ecc.steps;
1137 uint8_t *p = buf;
4bf63fcb
DW		 1138 uint8_t *ecc_calc = chip->buffers->ecccalc;
1139 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1140 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 1141
46a8cf2d 1142 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 1143
1144 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1145 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1146
1147 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1148 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1149
1150 eccsteps = chip->ecc.steps;
1151 p = buf;
1152
1153 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1154 int stat;
1155
1156 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1157 if (stat < 0)
f5bbdacc
TG		 1158 mtd->ecc_stats.failed++;
1159 else
1160 mtd->ecc_stats.corrected += stat;
1161 }
1162 return 0;
22c60f5f 1163}
1da177e4 1164
3d459559 1165/**
7854d3f7 1166 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
8b6e50c9
BN		 1167 * @mtd: mtd info structure
1168 * @chip: nand chip info structure
1169 * @data_offs: offset of requested data within the page
1170 * @readlen: data length
1171 * @bufpoi: buffer to store read data
3d459559 1172 */
7351d3a5
FF		 1173static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1174 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1175{
1176 int start_step, end_step, num_steps;
1177 uint32_t *eccpos = chip->ecc.layout->eccpos;
1178 uint8_t *p;
1179 int data_col_addr, i, gaps = 0;
1180 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1181 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1182 int index = 0;
3d459559 1183
7854d3f7 1184 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1185 start_step = data_offs / chip->ecc.size;
1186 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1187 num_steps = end_step - start_step + 1;
1188
8b6e50c9 1189 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1190 datafrag_len = num_steps * chip->ecc.size;
1191 eccfrag_len = num_steps * chip->ecc.bytes;
1192
1193 data_col_addr = start_step * chip->ecc.size;
1194 /* If we read not a page aligned data */
1195 if (data_col_addr != 0)
1196 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1197
1198 p = bufpoi + data_col_addr;
1199 chip->read_buf(mtd, p, datafrag_len);
1200
8b6e50c9 1201 /* Calculate ECC */
3d459559
AK		 1202 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1203 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1204
8b6e50c9
BN		 1205 /*
1206 * The performance is faster if we position offsets according to
7854d3f7 1207 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1208 */
3d459559
AK		 1209 for (i = 0; i < eccfrag_len - 1; i++) {
1210 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1211 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1212 gaps = 1;
1213 break;
1214 }
1215 }
1216 if (gaps) {
1217 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1218 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1219 } else {
8b6e50c9 1220 /*
7854d3f7 1221 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1222 * about buswidth alignment in read_buf.
1223 */
7351d3a5
FF		 1224 index = start_step * chip->ecc.bytes;
1225
1226 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1227 aligned_len = eccfrag_len;
7351d3a5 1228 if (eccpos[index] & (busw - 1))
3d459559 1229 aligned_len++;
7351d3a5 1230 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1231 aligned_len++;
1232
7351d3a5
FF		 1233 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1234 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1235 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1236 }
1237
1238 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1239 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1240
1241 p = bufpoi + data_col_addr;
1242 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1243 int stat;
1244
7351d3a5
FF		 1245 stat = chip->ecc.correct(mtd, p,
1246 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
12c8eb98 1247 if (stat < 0)
3d459559
AK		 1248 mtd->ecc_stats.failed++;
1249 else
1250 mtd->ecc_stats.corrected += stat;
1251 }
1252 return 0;
1253}
1254
068e3c0a 1255/**
7854d3f7 1256 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1257 * @mtd: mtd info structure
1258 * @chip: nand chip info structure
1259 * @buf: buffer to store read data
1260 * @page: page number to read
068e3c0a 1261 *
7854d3f7 1262 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1263 */
f5bbdacc 1264static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1265 uint8_t *buf, int page)
1da177e4 1266{
f5bbdacc
TG		 1267 int i, eccsize = chip->ecc.size;
1268 int eccbytes = chip->ecc.bytes;
1269 int eccsteps = chip->ecc.steps;
1270 uint8_t *p = buf;
4bf63fcb
DW		 1271 uint8_t *ecc_calc = chip->buffers->ecccalc;
1272 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1273 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1274
1275 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1276 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1277 chip->read_buf(mtd, p, eccsize);
1278 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1279 }
f75e5097 1280 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1281
f5bbdacc 1282 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1283 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1284
f5bbdacc
TG		 1285 eccsteps = chip->ecc.steps;
1286 p = buf;
61b03bd7 1287
f5bbdacc
TG		 1288 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1289 int stat;
1da177e4 1290
f5bbdacc 1291 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1292 if (stat < 0)
f5bbdacc
TG		 1293 mtd->ecc_stats.failed++;
1294 else
1295 mtd->ecc_stats.corrected += stat;
1296 }
1297 return 0;
1298}
1da177e4 1299
6e0cb135 1300/**
7854d3f7 1301 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1302 * @mtd: mtd info structure
1303 * @chip: nand chip info structure
1304 * @buf: buffer to store read data
1305 * @page: page number to read
6e0cb135 1306 *
8b6e50c9
BN		 1307 * Hardware ECC for large page chips, require OOB to be read first. For this
1308 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1309 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1310 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1311 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1312 */
1313static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1314 struct nand_chip *chip, uint8_t *buf, int page)
1315{
1316 int i, eccsize = chip->ecc.size;
1317 int eccbytes = chip->ecc.bytes;
1318 int eccsteps = chip->ecc.steps;
1319 uint8_t *p = buf;
1320 uint8_t *ecc_code = chip->buffers->ecccode;
1321 uint32_t *eccpos = chip->ecc.layout->eccpos;
1322 uint8_t *ecc_calc = chip->buffers->ecccalc;
1323
1324 /* Read the OOB area first */
1325 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1326 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1327 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1328
1329 for (i = 0; i < chip->ecc.total; i++)
1330 ecc_code[i] = chip->oob_poi[eccpos[i]];
1331
1332 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1333 int stat;
1334
1335 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1336 chip->read_buf(mtd, p, eccsize);
1337 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1338
1339 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1340 if (stat < 0)
1341 mtd->ecc_stats.failed++;
1342 else
1343 mtd->ecc_stats.corrected += stat;
1344 }
1345 return 0;
1346}
1347
f5bbdacc 1348/**
7854d3f7 1349 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1350 * @mtd: mtd info structure
1351 * @chip: nand chip info structure
1352 * @buf: buffer to store read data
1353 * @page: page number to read
f5bbdacc 1354 *
8b6e50c9
BN		 1355 * The hw generator calculates the error syndrome automatically. Therefore we
1356 * need a special oob layout and handling.
f5bbdacc
TG		 1357 */
1358static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1359 uint8_t *buf, int page)
f5bbdacc
TG		 1360{
1361 int i, eccsize = chip->ecc.size;
1362 int eccbytes = chip->ecc.bytes;
1363 int eccsteps = chip->ecc.steps;
1364 uint8_t *p = buf;
f75e5097 1365 uint8_t *oob = chip->oob_poi;
1da177e4 1366
f5bbdacc
TG		 1367 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1368 int stat;
61b03bd7 1369
f5bbdacc
TG		 1370 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1371 chip->read_buf(mtd, p, eccsize);
1da177e4 1372
f5bbdacc
TG		 1373 if (chip->ecc.prepad) {
1374 chip->read_buf(mtd, oob, chip->ecc.prepad);
1375 oob += chip->ecc.prepad;
1376 }
1da177e4 1377
f5bbdacc
TG		 1378 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1379 chip->read_buf(mtd, oob, eccbytes);
1380 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1381
c32b8dcc 1382 if (stat < 0)
f5bbdacc 1383 mtd->ecc_stats.failed++;
61b03bd7 1384 else
f5bbdacc 1385 mtd->ecc_stats.corrected += stat;
61b03bd7 1386
f5bbdacc 1387 oob += eccbytes;
1da177e4 1388
f5bbdacc
TG		 1389 if (chip->ecc.postpad) {
1390 chip->read_buf(mtd, oob, chip->ecc.postpad);
1391 oob += chip->ecc.postpad;
61b03bd7 1392 }
f5bbdacc 1393 }
1da177e4 1394
f5bbdacc 1395 /* Calculate remaining oob bytes */
7e4178f9 1396 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1397 if (i)
1398 chip->read_buf(mtd, oob, i);
61b03bd7 1399
f5bbdacc
TG		 1400 return 0;
1401}
1da177e4 1402
f5bbdacc 1403/**
7854d3f7 1404 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1405 * @chip: nand chip structure
1406 * @oob: oob destination address
1407 * @ops: oob ops structure
1408 * @len: size of oob to transfer
8593fbc6
TG		 1409 */
1410static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1411 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1412{
f8ac0414 1413 switch (ops->mode) {
8593fbc6 1414
0612b9dd
BN		 1415 case MTD_OPS_PLACE_OOB:
1416 case MTD_OPS_RAW:
8593fbc6
TG		 1417 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1418 return oob + len;
1419
0612b9dd 1420 case MTD_OPS_AUTO_OOB: {
8593fbc6 1421 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1422 uint32_t boffs = 0, roffs = ops->ooboffs;
1423 size_t bytes = 0;
8593fbc6 1424
f8ac0414 1425 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1426 /* Read request not from offset 0? */
7bc3312b
TG		 1427 if (unlikely(roffs)) {
1428 if (roffs >= free->length) {
1429 roffs -= free->length;
1430 continue;
1431 }
1432 boffs = free->offset + roffs;
1433 bytes = min_t(size_t, len,
1434 (free->length - roffs));
1435 roffs = 0;
1436 } else {
1437 bytes = min_t(size_t, len, free->length);
1438 boffs = free->offset;
1439 }
1440 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1441 oob += bytes;
1442 }
1443 return oob;
1444 }
1445 default:
1446 BUG();
1447 }
1448 return NULL;
1449}
1450
1451/**
7854d3f7 1452 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1453 * @mtd: MTD device structure
1454 * @from: offset to read from
1455 * @ops: oob ops structure
f5bbdacc
TG		 1456 *
1457 * Internal function. Called with chip held.
1458 */
8593fbc6
TG		 1459static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1460 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1461{
1462 int chipnr, page, realpage, col, bytes, aligned;
1463 struct nand_chip *chip = mtd->priv;
1464 struct mtd_ecc_stats stats;
1465 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1466 int sndcmd = 1;
1467 int ret = 0;
8593fbc6 1468 uint32_t readlen = ops->len;
7014568b 1469 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1470 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1471 mtd->oobavail : mtd->oobsize;
1472
8593fbc6 1473 uint8_t *bufpoi, *oob, *buf;
1da177e4 1474
f5bbdacc 1475 stats = mtd->ecc_stats;
1da177e4 1476
f5bbdacc
TG		 1477 chipnr = (int)(from >> chip->chip_shift);
1478 chip->select_chip(mtd, chipnr);
61b03bd7 1479
f5bbdacc
TG		 1480 realpage = (int)(from >> chip->page_shift);
1481 page = realpage & chip->pagemask;
1da177e4 1482
f5bbdacc 1483 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1484
8593fbc6
TG		 1485 buf = ops->datbuf;
1486 oob = ops->oobbuf;
1487
f8ac0414 1488 while (1) {
f5bbdacc
TG		 1489 bytes = min(mtd->writesize - col, readlen);
1490 aligned = (bytes == mtd->writesize);
61b03bd7 1491
8b6e50c9 1492 /* Is the current page in the buffer? */
8593fbc6 1493 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1494 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1495
f5bbdacc
TG		 1496 if (likely(sndcmd)) {
1497 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1498 sndcmd = 0;
1da177e4 1499 }
1da177e4 1500
f5bbdacc 1501 /* Now read the page into the buffer */
0612b9dd 1502 if (unlikely(ops->mode == MTD_OPS_RAW))
46a8cf2d
SN		 1503 ret = chip->ecc.read_page_raw(mtd, chip,
1504 bufpoi, page);
3d459559 1505 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1506 ret = chip->ecc.read_subpage(mtd, chip,
1507 col, bytes, bufpoi);
956e944c 1508 else
46a8cf2d
SN		 1509 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1510 page);
6d77b9d0
BN		 1511 if (ret < 0) {
1512 if (!aligned)
1513 /* Invalidate page cache */
1514 chip->pagebuf = -1;
1da177e4 1515 break;
6d77b9d0 1516 }
f5bbdacc
TG		 1517
1518 /* Transfer not aligned data */
1519 if (!aligned) {
c1194c79 1520 if (!NAND_SUBPAGE_READ(chip) && !oob &&
6d77b9d0
BN		 1521 !(mtd->ecc_stats.failed - stats.failed) &&
1522 (ops->mode != MTD_OPS_RAW))
3d459559 1523 chip->pagebuf = realpage;
6d77b9d0
BN		 1524 else
1525 /* Invalidate page cache */
1526 chip->pagebuf = -1;
4bf63fcb 1527 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1528 }
1529
8593fbc6
TG		 1530 buf += bytes;
1531
1532 if (unlikely(oob)) {
9aca334e 1533
b64d39d8
ML		 1534 int toread = min(oobreadlen, max_oobsize);
1535
1536 if (toread) {
1537 oob = nand_transfer_oob(chip,
1538 oob, ops, toread);
1539 oobreadlen -= toread;
1540 }
8593fbc6
TG		 1541 }
1542
f5bbdacc
TG		 1543 if (!(chip->options & NAND_NO_READRDY)) {
1544 /*
1545 * Apply delay or wait for ready/busy pin. Do
1546 * this before the AUTOINCR check, so no
1547 * problems arise if a chip which does auto
1548 * increment is marked as NOAUTOINCR by the
1549 * board driver.
1550 */
1551 if (!chip->dev_ready)
1552 udelay(chip->chip_delay);
1553 else
1554 nand_wait_ready(mtd);
1da177e4 1555 }
8593fbc6 1556 } else {
4bf63fcb 1557 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1558 buf += bytes;
1559 }
1da177e4 1560
f5bbdacc 1561 readlen -= bytes;
61b03bd7 1562
f5bbdacc 1563 if (!readlen)
61b03bd7 1564 break;
1da177e4 1565
8b6e50c9 1566 /* For subsequent reads align to page boundary */
1da177e4
LT		 1567 col = 0;
1568 /* Increment page address */
1569 realpage++;
1570
ace4dfee 1571 page = realpage & chip->pagemask;
1da177e4
LT		 1572 /* Check, if we cross a chip boundary */
1573 if (!page) {
1574 chipnr++;
ace4dfee
TG		 1575 chip->select_chip(mtd, -1);
1576 chip->select_chip(mtd, chipnr);
1da177e4 1577 }
f5bbdacc 1578
8b6e50c9
BN		 1579 /*
1580 * Check, if the chip supports auto page increment or if we
1581 * have hit a block boundary.
e0c7d767 1582 */
f5bbdacc 1583 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1584 sndcmd = 1;
1da177e4
LT		 1585 }
1586
8593fbc6 1587 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1588 if (oob)
1589 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1590
f5bbdacc
TG		 1591 if (ret)
1592 return ret;
1593
9a1fcdfd
TG		 1594 if (mtd->ecc_stats.failed - stats.failed)
1595 return -EBADMSG;
1596
1597 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1598}
1599
1600/**
25985edc 1601 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1602 * @mtd: MTD device structure
1603 * @from: offset to read from
1604 * @len: number of bytes to read
1605 * @retlen: pointer to variable to store the number of read bytes
1606 * @buf: the databuffer to put data
f5bbdacc 1607 *
8b6e50c9 1608 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1609 */
1610static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1611 size_t *retlen, uint8_t *buf)
1612{
8593fbc6 1613 struct nand_chip *chip = mtd->priv;
4a89ff88 1614 struct mtd_oob_ops ops;
f5bbdacc
TG		 1615 int ret;
1616
8593fbc6 1617 nand_get_device(chip, mtd, FL_READING);
4a89ff88
BN		 1618 ops.len = len;
1619 ops.datbuf = buf;
1620 ops.oobbuf = NULL;
23b1a99b 1621 ops.mode = 0;
4a89ff88 1622 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1623 *retlen = ops.retlen;
f5bbdacc 1624 nand_release_device(mtd);
f5bbdacc 1625 return ret;
1da177e4
LT		 1626}
1627
7bc3312b 1628/**
7854d3f7 1629 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1630 * @mtd: mtd info structure
1631 * @chip: nand chip info structure
1632 * @page: page number to read
1633 * @sndcmd: flag whether to issue read command or not
7bc3312b
TG		 1634 */
1635static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1636 int page, int sndcmd)
1637{
1638 if (sndcmd) {
1639 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1640 sndcmd = 0;
1641 }
1642 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1643 return sndcmd;
1644}
1645
1646/**
7854d3f7 1647 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1648 * with syndromes
8b6e50c9
BN		 1649 * @mtd: mtd info structure
1650 * @chip: nand chip info structure
1651 * @page: page number to read
1652 * @sndcmd: flag whether to issue read command or not
7bc3312b
TG		 1653 */
1654static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1655 int page, int sndcmd)
1656{
1657 uint8_t *buf = chip->oob_poi;
1658 int length = mtd->oobsize;
1659 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1660 int eccsize = chip->ecc.size;
1661 uint8_t *bufpoi = buf;
1662 int i, toread, sndrnd = 0, pos;
1663
1664 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1665 for (i = 0; i < chip->ecc.steps; i++) {
1666 if (sndrnd) {
1667 pos = eccsize + i * (eccsize + chunk);
1668 if (mtd->writesize > 512)
1669 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1670 else
1671 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1672 } else
1673 sndrnd = 1;
1674 toread = min_t(int, length, chunk);
1675 chip->read_buf(mtd, bufpoi, toread);
1676 bufpoi += toread;
1677 length -= toread;
1678 }
1679 if (length > 0)
1680 chip->read_buf(mtd, bufpoi, length);
1681
1682 return 1;
1683}
1684
1685/**
7854d3f7 1686 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1687 * @mtd: mtd info structure
1688 * @chip: nand chip info structure
1689 * @page: page number to write
7bc3312b
TG		 1690 */
1691static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1692 int page)
1693{
1694 int status = 0;
1695 const uint8_t *buf = chip->oob_poi;
1696 int length = mtd->oobsize;
1697
1698 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1699 chip->write_buf(mtd, buf, length);
1700 /* Send command to program the OOB data */
1701 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1702
1703 status = chip->waitfunc(mtd, chip);
1704
0d420f9d 1705 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1706}
1707
1708/**
7854d3f7 1709 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1710 * with syndrome - only for large page flash
1711 * @mtd: mtd info structure
1712 * @chip: nand chip info structure
1713 * @page: page number to write
7bc3312b
TG		 1714 */
1715static int nand_write_oob_syndrome(struct mtd_info *mtd,
1716 struct nand_chip *chip, int page)
1717{
1718 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1719 int eccsize = chip->ecc.size, length = mtd->oobsize;
1720 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1721 const uint8_t *bufpoi = chip->oob_poi;
1722
1723 /*
1724 * data-ecc-data-ecc ... ecc-oob
1725 * or
1726 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1727 */
1728 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1729 pos = steps * (eccsize + chunk);
1730 steps = 0;
1731 } else
8b0036ee 1732 pos = eccsize;
7bc3312b
TG		 1733
1734 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1735 for (i = 0; i < steps; i++) {
1736 if (sndcmd) {
1737 if (mtd->writesize <= 512) {
1738 uint32_t fill = 0xFFFFFFFF;
1739
1740 len = eccsize;
1741 while (len > 0) {
1742 int num = min_t(int, len, 4);
1743 chip->write_buf(mtd, (uint8_t *)&fill,
1744 num);
1745 len -= num;
1746 }
1747 } else {
1748 pos = eccsize + i * (eccsize + chunk);
1749 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1750 }
1751 } else
1752 sndcmd = 1;
1753 len = min_t(int, length, chunk);
1754 chip->write_buf(mtd, bufpoi, len);
1755 bufpoi += len;
1756 length -= len;
1757 }
1758 if (length > 0)
1759 chip->write_buf(mtd, bufpoi, length);
1760
1761 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1762 status = chip->waitfunc(mtd, chip);
1763
1764 return status & NAND_STATUS_FAIL ? -EIO : 0;
1765}
1766
1da177e4 1767/**
7854d3f7 1768 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1769 * @mtd: MTD device structure
1770 * @from: offset to read from
1771 * @ops: oob operations description structure
1da177e4 1772 *
8b6e50c9 1773 * NAND read out-of-band data from the spare area.
1da177e4 1774 */
8593fbc6
TG		 1775static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1776 struct mtd_oob_ops *ops)
1da177e4 1777{
7bc3312b 1778 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1779 struct nand_chip *chip = mtd->priv;
041e4575 1780 struct mtd_ecc_stats stats;
7314e9e7 1781 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1782 int readlen = ops->ooblen;
1783 int len;
7bc3312b 1784 uint8_t *buf = ops->oobbuf;
61b03bd7 1785
289c0522 1786 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1787 __func__, (unsigned long long)from, readlen);
1da177e4 1788
041e4575
BN		 1789 stats = mtd->ecc_stats;
1790
0612b9dd 1791 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1792 len = chip->ecc.layout->oobavail;
03736155
AH		 1793 else
1794 len = mtd->oobsize;
1795
1796 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1797 pr_debug("%s: attempt to start read outside oob\n",
1798 __func__);
03736155
AH		 1799 return -EINVAL;
1800 }
1801
1802 /* Do not allow reads past end of device */
1803 if (unlikely(from >= mtd->size ||
1804 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1805 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1806 pr_debug("%s: attempt to read beyond end of device\n",
1807 __func__);
03736155
AH		 1808 return -EINVAL;
1809 }
7014568b 1810
7314e9e7 1811 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1812 chip->select_chip(mtd, chipnr);
1da177e4 1813
7314e9e7
TG		 1814 /* Shift to get page */
1815 realpage = (int)(from >> chip->page_shift);
1816 page = realpage & chip->pagemask;
1da177e4 1817
f8ac0414 1818 while (1) {
0612b9dd 1819 if (ops->mode == MTD_OPS_RAW)
c46f6483
BN		 1820 sndcmd = chip->ecc.read_oob_raw(mtd, chip, page, sndcmd);
1821 else
1822 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1823
1824 len = min(len, readlen);
1825 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1826
7314e9e7
TG		 1827 if (!(chip->options & NAND_NO_READRDY)) {
1828 /*
1829 * Apply delay or wait for ready/busy pin. Do this
1830 * before the AUTOINCR check, so no problems arise if a
1831 * chip which does auto increment is marked as
1832 * NOAUTOINCR by the board driver.
19870da7 1833 */
ace4dfee
TG		 1834 if (!chip->dev_ready)
1835 udelay(chip->chip_delay);
19870da7
TG		 1836 else
1837 nand_wait_ready(mtd);
7314e9e7 1838 }
19870da7 1839
7014568b 1840 readlen -= len;
0d420f9d
SZ		 1841 if (!readlen)
1842 break;
1843
7314e9e7
TG		 1844 /* Increment page address */
1845 realpage++;
1846
1847 page = realpage & chip->pagemask;
1848 /* Check, if we cross a chip boundary */
1849 if (!page) {
1850 chipnr++;
1851 chip->select_chip(mtd, -1);
1852 chip->select_chip(mtd, chipnr);
1da177e4 1853 }
7314e9e7 1854
8b6e50c9
BN		 1855 /*
1856 * Check, if the chip supports auto page increment or if we
1857 * have hit a block boundary.
7314e9e7
TG		 1858 */
1859 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1860 sndcmd = 1;
1da177e4
LT		 1861 }
1862
7014568b 1863 ops->oobretlen = ops->ooblen;
041e4575
BN		 1864
1865 if (mtd->ecc_stats.failed - stats.failed)
1866 return -EBADMSG;
1867
1868 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1869}
1870
1871/**
8593fbc6 1872 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1873 * @mtd: MTD device structure
1874 * @from: offset to read from
1875 * @ops: oob operation description structure
1da177e4 1876 *
8b6e50c9 1877 * NAND read data and/or out-of-band data.
1da177e4 1878 */
8593fbc6
TG		 1879static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1880 struct mtd_oob_ops *ops)
1da177e4 1881{
ace4dfee 1882 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1883 int ret = -ENOTSUPP;
1884
1885 ops->retlen = 0;
1da177e4
LT		 1886
1887 /* Do not allow reads past end of device */
7014568b 1888 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1889 pr_debug("%s: attempt to read beyond end of device\n",
1890 __func__);
1da177e4
LT		 1891 return -EINVAL;
1892 }
1893
ace4dfee 1894 nand_get_device(chip, mtd, FL_READING);
1da177e4 1895
f8ac0414 1896 switch (ops->mode) {
0612b9dd
BN		 1897 case MTD_OPS_PLACE_OOB:
1898 case MTD_OPS_AUTO_OOB:
1899 case MTD_OPS_RAW:
8593fbc6 1900 break;
1da177e4 1901
8593fbc6
TG		 1902 default:
1903 goto out;
1904 }
1da177e4 1905
8593fbc6
TG		 1906 if (!ops->datbuf)
1907 ret = nand_do_read_oob(mtd, from, ops);
1908 else
1909 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1910
7351d3a5 1911out:
8593fbc6
TG		 1912 nand_release_device(mtd);
1913 return ret;
1914}
61b03bd7 1915
1da177e4 1916
8593fbc6 1917/**
7854d3f7 1918 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1919 * @mtd: mtd info structure
1920 * @chip: nand chip info structure
1921 * @buf: data buffer
52ff49df 1922 *
7854d3f7 1923 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1924 */
1925static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1926 const uint8_t *buf)
1927{
1928 chip->write_buf(mtd, buf, mtd->writesize);
1929 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1930}
1931
52ff49df 1932/**
7854d3f7 1933 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1934 * @mtd: mtd info structure
1935 * @chip: nand chip info structure
1936 * @buf: data buffer
52ff49df
DB		 1937 *
1938 * We need a special oob layout and handling even when ECC isn't checked.
1939 */
7351d3a5
FF		 1940static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1941 struct nand_chip *chip,
1942 const uint8_t *buf)
52ff49df
DB		 1943{
1944 int eccsize = chip->ecc.size;
1945 int eccbytes = chip->ecc.bytes;
1946 uint8_t *oob = chip->oob_poi;
1947 int steps, size;
1948
1949 for (steps = chip->ecc.steps; steps > 0; steps--) {
1950 chip->write_buf(mtd, buf, eccsize);
1951 buf += eccsize;
1952
1953 if (chip->ecc.prepad) {
1954 chip->write_buf(mtd, oob, chip->ecc.prepad);
1955 oob += chip->ecc.prepad;
1956 }
1957
1958 chip->read_buf(mtd, oob, eccbytes);
1959 oob += eccbytes;
1960
1961 if (chip->ecc.postpad) {
1962 chip->write_buf(mtd, oob, chip->ecc.postpad);
1963 oob += chip->ecc.postpad;
1964 }
1965 }
1966
1967 size = mtd->oobsize - (oob - chip->oob_poi);
1968 if (size)
1969 chip->write_buf(mtd, oob, size);
1970}
9223a456 1971/**
7854d3f7 1972 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1973 * @mtd: mtd info structure
1974 * @chip: nand chip info structure
1975 * @buf: data buffer
9223a456 1976 */
f75e5097
TG		 1977static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1978 const uint8_t *buf)
9223a456 1979{
f75e5097
TG		 1980 int i, eccsize = chip->ecc.size;
1981 int eccbytes = chip->ecc.bytes;
1982 int eccsteps = chip->ecc.steps;
4bf63fcb 1983 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1984 const uint8_t *p = buf;
8b099a39 1985 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1986
7854d3f7 1987 /* Software ECC calculation */
8593fbc6
TG		 1988 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1989 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1990
8593fbc6
TG		 1991 for (i = 0; i < chip->ecc.total; i++)
1992 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1993
90424de8 1994 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1995}
9223a456 1996
f75e5097 1997/**
7854d3f7 1998 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 1999 * @mtd: mtd info structure
2000 * @chip: nand chip info structure
2001 * @buf: data buffer
f75e5097
TG		 2002 */
2003static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2004 const uint8_t *buf)
2005{
2006 int i, eccsize = chip->ecc.size;
2007 int eccbytes = chip->ecc.bytes;
2008 int eccsteps = chip->ecc.steps;
4bf63fcb 2009 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2010 const uint8_t *p = buf;
8b099a39 2011 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2012
f75e5097
TG		 2013 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2014 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2015 chip->write_buf(mtd, p, eccsize);
f75e5097 2016 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2017 }
2018
f75e5097
TG		 2019 for (i = 0; i < chip->ecc.total; i++)
2020 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2021
2022 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 2023}
2024
61b03bd7 2025/**
7854d3f7 2026 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2027 * @mtd: mtd info structure
2028 * @chip: nand chip info structure
2029 * @buf: data buffer
1da177e4 2030 *
8b6e50c9
BN		 2031 * The hw generator calculates the error syndrome automatically. Therefore we
2032 * need a special oob layout and handling.
f75e5097
TG		 2033 */
2034static void nand_write_page_syndrome(struct mtd_info *mtd,
2035 struct nand_chip *chip, const uint8_t *buf)
1da177e4 2036{
f75e5097
TG		 2037 int i, eccsize = chip->ecc.size;
2038 int eccbytes = chip->ecc.bytes;
2039 int eccsteps = chip->ecc.steps;
2040 const uint8_t *p = buf;
2041 uint8_t *oob = chip->oob_poi;
1da177e4 2042
f75e5097 2043 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2044
f75e5097
TG		 2045 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2046 chip->write_buf(mtd, p, eccsize);
61b03bd7 2047
f75e5097
TG		 2048 if (chip->ecc.prepad) {
2049 chip->write_buf(mtd, oob, chip->ecc.prepad);
2050 oob += chip->ecc.prepad;
2051 }
2052
2053 chip->ecc.calculate(mtd, p, oob);
2054 chip->write_buf(mtd, oob, eccbytes);
2055 oob += eccbytes;
2056
2057 if (chip->ecc.postpad) {
2058 chip->write_buf(mtd, oob, chip->ecc.postpad);
2059 oob += chip->ecc.postpad;
1da177e4 2060 }
1da177e4 2061 }
f75e5097
TG		 2062
2063 /* Calculate remaining oob bytes */
7e4178f9 2064 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2065 if (i)
2066 chip->write_buf(mtd, oob, i);
2067}
2068
2069/**
956e944c 2070 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2071 * @mtd: MTD device structure
2072 * @chip: NAND chip descriptor
2073 * @buf: the data to write
2074 * @page: page number to write
2075 * @cached: cached programming
2076 * @raw: use _raw version of write_page
f75e5097
TG		 2077 */
2078static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 2079 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 2080{
2081 int status;
2082
2083 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2084
956e944c
DW		 2085 if (unlikely(raw))
2086 chip->ecc.write_page_raw(mtd, chip, buf);
2087 else
2088 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 2089
2090 /*
7854d3f7 2091 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2092 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2093 */
2094 cached = 0;
2095
2096 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2097
2098 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2099 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2100 /*
2101 * See if operation failed and additional status checks are
8b6e50c9 2102 * available.
f75e5097
TG		 2103 */
2104 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2105 status = chip->errstat(mtd, chip, FL_WRITING, status,
2106 page);
2107
2108 if (status & NAND_STATUS_FAIL)
2109 return -EIO;
2110 } else {
2111 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2112 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2113 }
2114
2115#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2116 /* Send command to read back the data */
2117 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2118
2119 if (chip->verify_buf(mtd, buf, mtd->writesize))
2120 return -EIO;
2121#endif
2122 return 0;
1da177e4
LT		 2123}
2124
8593fbc6 2125/**
7854d3f7 2126 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2127 * @mtd: MTD device structure
8b6e50c9
BN		 2128 * @oob: oob data buffer
2129 * @len: oob data write length
2130 * @ops: oob ops structure
8593fbc6 2131 */
f722013e
TAA		 2132static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2133 struct mtd_oob_ops *ops)
8593fbc6 2134{
f722013e
TAA		 2135 struct nand_chip *chip = mtd->priv;
2136
2137 /*
2138 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2139 * data from a previous OOB read.
2140 */
2141 memset(chip->oob_poi, 0xff, mtd->oobsize);
2142
f8ac0414 2143 switch (ops->mode) {
8593fbc6 2144
0612b9dd
BN		 2145 case MTD_OPS_PLACE_OOB:
2146 case MTD_OPS_RAW:
8593fbc6
TG		 2147 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2148 return oob + len;
2149
0612b9dd 2150 case MTD_OPS_AUTO_OOB: {
8593fbc6 2151 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2152 uint32_t boffs = 0, woffs = ops->ooboffs;
2153 size_t bytes = 0;
8593fbc6 2154
f8ac0414 2155 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2156 /* Write request not from offset 0? */
7bc3312b
TG		 2157 if (unlikely(woffs)) {
2158 if (woffs >= free->length) {
2159 woffs -= free->length;
2160 continue;
2161 }
2162 boffs = free->offset + woffs;
2163 bytes = min_t(size_t, len,
2164 (free->length - woffs));
2165 woffs = 0;
2166 } else {
2167 bytes = min_t(size_t, len, free->length);
2168 boffs = free->offset;
2169 }
8b0036ee 2170 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2171 oob += bytes;
2172 }
2173 return oob;
2174 }
2175 default:
2176 BUG();
2177 }
2178 return NULL;
2179}
2180
f8ac0414 2181#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2182
2183/**
7854d3f7 2184 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2185 * @mtd: MTD device structure
2186 * @to: offset to write to
2187 * @ops: oob operations description structure
1da177e4 2188 *
8b6e50c9 2189 * NAND write with ECC.
1da177e4 2190 */
8593fbc6
TG		 2191static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2192 struct mtd_oob_ops *ops)
1da177e4 2193{
29072b96 2194 int chipnr, realpage, page, blockmask, column;
ace4dfee 2195 struct nand_chip *chip = mtd->priv;
8593fbc6 2196 uint32_t writelen = ops->len;
782ce79a
ML		 2197
2198 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2199 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2200 mtd->oobavail : mtd->oobsize;
2201
8593fbc6
TG		 2202 uint8_t *oob = ops->oobbuf;
2203 uint8_t *buf = ops->datbuf;
29072b96 2204 int ret, subpage;
1da177e4 2205
8593fbc6 2206 ops->retlen = 0;
29072b96
TG		 2207 if (!writelen)
2208 return 0;
1da177e4 2209
8b6e50c9 2210 /* Reject writes, which are not page aligned */
8593fbc6 2211 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2212 pr_notice("%s: attempt to write non page aligned data\n",
2213 __func__);
1da177e4
LT		 2214 return -EINVAL;
2215 }
2216
29072b96
TG		 2217 column = to & (mtd->writesize - 1);
2218 subpage = column || (writelen & (mtd->writesize - 1));
2219
2220 if (subpage && oob)
2221 return -EINVAL;
1da177e4 2222
6a930961
TG		 2223 chipnr = (int)(to >> chip->chip_shift);
2224 chip->select_chip(mtd, chipnr);
2225
1da177e4
LT		 2226 /* Check, if it is write protected */
2227 if (nand_check_wp(mtd))
8593fbc6 2228 return -EIO;
1da177e4 2229
f75e5097
TG		 2230 realpage = (int)(to >> chip->page_shift);
2231 page = realpage & chip->pagemask;
2232 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2233
2234 /* Invalidate the page cache, when we write to the cached page */
2235 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2236 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2237 chip->pagebuf = -1;
61b03bd7 2238
782ce79a 2239 /* Don't allow multipage oob writes with offset */
cdcf12b2 2240 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2241 return -EINVAL;
2242
f8ac0414 2243 while (1) {
29072b96 2244 int bytes = mtd->writesize;
f75e5097 2245 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2246 uint8_t *wbuf = buf;
2247
8b6e50c9 2248 /* Partial page write? */
29072b96
TG		 2249 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2250 cached = 0;
2251 bytes = min_t(int, bytes - column, (int) writelen);
2252 chip->pagebuf = -1;
2253 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2254 memcpy(&chip->buffers->databuf[column], buf, bytes);
2255 wbuf = chip->buffers->databuf;
2256 }
1da177e4 2257
782ce79a
ML		 2258 if (unlikely(oob)) {
2259 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2260 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2261 oobwritelen -= len;
f722013e
TAA		 2262 } else {
2263 /* We still need to erase leftover OOB data */
2264 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2265 }
8593fbc6 2266
29072b96 2267 ret = chip->write_page(mtd, chip, wbuf, page, cached,
0612b9dd 2268 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2269 if (ret)
2270 break;
2271
2272 writelen -= bytes;
2273 if (!writelen)
2274 break;
2275
29072b96 2276 column = 0;
f75e5097
TG		 2277 buf += bytes;
2278 realpage++;
2279
2280 page = realpage & chip->pagemask;
2281 /* Check, if we cross a chip boundary */
2282 if (!page) {
2283 chipnr++;
2284 chip->select_chip(mtd, -1);
2285 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2286 }
2287 }
8593fbc6 2288
8593fbc6 2289 ops->retlen = ops->len - writelen;
7014568b
VW		 2290 if (unlikely(oob))
2291 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2292 return ret;
2293}
2294
2af7c653
SK		 2295/**
2296 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2297 * @mtd: MTD device structure
2298 * @to: offset to write to
2299 * @len: number of bytes to write
2300 * @retlen: pointer to variable to store the number of written bytes
2301 * @buf: the data to write
2af7c653
SK		 2302 *
2303 * NAND write with ECC. Used when performing writes in interrupt context, this
2304 * may for example be called by mtdoops when writing an oops while in panic.
2305 */
2306static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2307 size_t *retlen, const uint8_t *buf)
2308{
2309 struct nand_chip *chip = mtd->priv;
4a89ff88 2310 struct mtd_oob_ops ops;
2af7c653
SK		 2311 int ret;
2312
8b6e50c9 2313 /* Wait for the device to get ready */
2af7c653
SK		 2314 panic_nand_wait(mtd, chip, 400);
2315
8b6e50c9 2316 /* Grab the device */
2af7c653
SK		 2317 panic_nand_get_device(chip, mtd, FL_WRITING);
2318
4a89ff88
BN		 2319 ops.len = len;
2320 ops.datbuf = (uint8_t *)buf;
2321 ops.oobbuf = NULL;
23b1a99b 2322 ops.mode = 0;
2af7c653 2323
4a89ff88 2324 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2325
4a89ff88 2326 *retlen = ops.retlen;
2af7c653
SK		 2327 return ret;
2328}
2329
f75e5097 2330/**
8593fbc6 2331 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2332 * @mtd: MTD device structure
2333 * @to: offset to write to
2334 * @len: number of bytes to write
2335 * @retlen: pointer to variable to store the number of written bytes
2336 * @buf: the data to write
f75e5097 2337 *
8b6e50c9 2338 * NAND write with ECC.
f75e5097 2339 */
8593fbc6
TG		 2340static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2341 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2342{
2343 struct nand_chip *chip = mtd->priv;
4a89ff88 2344 struct mtd_oob_ops ops;
f75e5097
TG		 2345 int ret;
2346
7bc3312b 2347 nand_get_device(chip, mtd, FL_WRITING);
4a89ff88
BN		 2348 ops.len = len;
2349 ops.datbuf = (uint8_t *)buf;
2350 ops.oobbuf = NULL;
23b1a99b 2351 ops.mode = 0;
4a89ff88 2352 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2353 *retlen = ops.retlen;
f75e5097 2354 nand_release_device(mtd);
8593fbc6 2355 return ret;
f75e5097 2356}
7314e9e7 2357
1da177e4 2358/**
8593fbc6 2359 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2360 * @mtd: MTD device structure
2361 * @to: offset to write to
2362 * @ops: oob operation description structure
1da177e4 2363 *
8b6e50c9 2364 * NAND write out-of-band.
1da177e4 2365 */
8593fbc6
TG		 2366static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2367 struct mtd_oob_ops *ops)
1da177e4 2368{
03736155 2369 int chipnr, page, status, len;
ace4dfee 2370 struct nand_chip *chip = mtd->priv;
1da177e4 2371
289c0522 2372 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2373 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2374
0612b9dd 2375 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2376 len = chip->ecc.layout->oobavail;
2377 else
2378 len = mtd->oobsize;
2379
1da177e4 2380 /* Do not allow write past end of page */
03736155 2381 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2382 pr_debug("%s: attempt to write past end of page\n",
2383 __func__);
1da177e4
LT		 2384 return -EINVAL;
2385 }
2386
03736155 2387 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2388 pr_debug("%s: attempt to start write outside oob\n",
2389 __func__);
03736155
AH		 2390 return -EINVAL;
2391 }
2392
775adc3d 2393 /* Do not allow write past end of device */
03736155
AH		 2394 if (unlikely(to >= mtd->size ||
2395 ops->ooboffs + ops->ooblen >
2396 ((mtd->size >> chip->page_shift) -
2397 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2398 pr_debug("%s: attempt to write beyond end of device\n",
2399 __func__);
03736155
AH		 2400 return -EINVAL;
2401 }
2402
7314e9e7 2403 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2404 chip->select_chip(mtd, chipnr);
1da177e4 2405
7314e9e7
TG		 2406 /* Shift to get page */
2407 page = (int)(to >> chip->page_shift);
2408
2409 /*
2410 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2411 * of my DiskOnChip 2000 test units) will clear the whole data page too
2412 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2413 * it in the doc2000 driver in August 1999. dwmw2.
2414 */
ace4dfee 2415 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2416
2417 /* Check, if it is write protected */
2418 if (nand_check_wp(mtd))
8593fbc6 2419 return -EROFS;
61b03bd7 2420
1da177e4 2421 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2422 if (page == chip->pagebuf)
2423 chip->pagebuf = -1;
1da177e4 2424
f722013e 2425 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2426
0612b9dd 2427 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2428 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2429 else
2430 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2431
7bc3312b
TG		 2432 if (status)
2433 return status;
1da177e4 2434
7014568b 2435 ops->oobretlen = ops->ooblen;
1da177e4 2436
7bc3312b 2437 return 0;
8593fbc6
TG		 2438}
2439
2440/**
2441 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2442 * @mtd: MTD device structure
2443 * @to: offset to write to
2444 * @ops: oob operation description structure
8593fbc6
TG		 2445 */
2446static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2447 struct mtd_oob_ops *ops)
2448{
8593fbc6
TG		 2449 struct nand_chip *chip = mtd->priv;
2450 int ret = -ENOTSUPP;
2451
2452 ops->retlen = 0;
2453
2454 /* Do not allow writes past end of device */
7014568b 2455 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2456 pr_debug("%s: attempt to write beyond end of device\n",
2457 __func__);
8593fbc6
TG		 2458 return -EINVAL;
2459 }
2460
7bc3312b 2461 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2462
f8ac0414 2463 switch (ops->mode) {
0612b9dd
BN		 2464 case MTD_OPS_PLACE_OOB:
2465 case MTD_OPS_AUTO_OOB:
2466 case MTD_OPS_RAW:
8593fbc6
TG		 2467 break;
2468
2469 default:
2470 goto out;
2471 }
2472
2473 if (!ops->datbuf)
2474 ret = nand_do_write_oob(mtd, to, ops);
2475 else
2476 ret = nand_do_write_ops(mtd, to, ops);
2477
7351d3a5 2478out:
1da177e4 2479 nand_release_device(mtd);
1da177e4
LT		 2480 return ret;
2481}
2482
1da177e4 2483/**
7854d3f7 2484 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2485 * @mtd: MTD device structure
2486 * @page: the page address of the block which will be erased
1da177e4 2487 *
8b6e50c9 2488 * Standard erase command for NAND chips.
1da177e4 2489 */
e0c7d767 2490static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2491{
ace4dfee 2492 struct nand_chip *chip = mtd->priv;
1da177e4 2493 /* Send commands to erase a block */
ace4dfee
TG		 2494 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2495 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2496}
2497
2498/**
7854d3f7 2499 * multi_erase_cmd - [GENERIC] AND specific block erase command function
8b6e50c9
BN		 2500 * @mtd: MTD device structure
2501 * @page: the page address of the block which will be erased
1da177e4 2502 *
8b6e50c9 2503 * AND multi block erase command function. Erase 4 consecutive blocks.
1da177e4 2504 */
e0c7d767 2505static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2506{
ace4dfee 2507 struct nand_chip *chip = mtd->priv;
1da177e4 2508 /* Send commands to erase a block */
ace4dfee
TG		 2509 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2510 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2511 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2512 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2513 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2514}
2515
2516/**
2517 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2518 * @mtd: MTD device structure
2519 * @instr: erase instruction
1da177e4 2520 *
8b6e50c9 2521 * Erase one ore more blocks.
1da177e4 2522 */
e0c7d767 2523static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2524{
e0c7d767 2525 return nand_erase_nand(mtd, instr, 0);
1da177e4 2526}
61b03bd7 2527
30f464b7 2528#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2529/**
7854d3f7 2530 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2531 * @mtd: MTD device structure
2532 * @instr: erase instruction
2533 * @allowbbt: allow erasing the bbt area
1da177e4 2534 *
8b6e50c9 2535 * Erase one ore more blocks.
1da177e4 2536 */
ace4dfee
TG		 2537int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2538 int allowbbt)
1da177e4 2539{
69423d99 2540 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2541 struct nand_chip *chip = mtd->priv;
f8ac0414 2542 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2543 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2544 loff_t len;
1da177e4 2545
289c0522
BN		 2546 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2547 __func__, (unsigned long long)instr->addr,
2548 (unsigned long long)instr->len);
1da177e4 2549
6fe5a6ac 2550 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2551 return -EINVAL;
1da177e4 2552
1da177e4 2553 /* Grab the lock and see if the device is available */
ace4dfee 2554 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2555
2556 /* Shift to get first page */
ace4dfee
TG		 2557 page = (int)(instr->addr >> chip->page_shift);
2558 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2559
2560 /* Calculate pages in each block */
ace4dfee 2561 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2562
2563 /* Select the NAND device */
ace4dfee 2564 chip->select_chip(mtd, chipnr);
1da177e4 2565
1da177e4
LT		 2566 /* Check, if it is write protected */
2567 if (nand_check_wp(mtd)) {
289c0522
BN		 2568 pr_debug("%s: device is write protected!\n",
2569 __func__);
1da177e4
LT		 2570 instr->state = MTD_ERASE_FAILED;
2571 goto erase_exit;
2572 }
2573
ace4dfee
TG		 2574 /*
2575 * If BBT requires refresh, set the BBT page mask to see if the BBT
2576 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2577 * can not be matched. This is also done when the bbt is actually
7854d3f7 2578 * erased to avoid recursive updates.
ace4dfee
TG		 2579 */
2580 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2581 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2582
1da177e4
LT		 2583 /* Loop through the pages */
2584 len = instr->len;
2585
2586 instr->state = MTD_ERASING;
2587
2588 while (len) {
12183a20 2589 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2590 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2591 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2592 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2593 __func__, page);
1da177e4
LT		 2594 instr->state = MTD_ERASE_FAILED;
2595 goto erase_exit;
2596 }
61b03bd7 2597
ace4dfee
TG		 2598 /*
2599 * Invalidate the page cache, if we erase the block which
8b6e50c9 2600 * contains the current cached page.
ace4dfee
TG		 2601 */
2602 if (page <= chip->pagebuf && chip->pagebuf <
2603 (page + pages_per_block))
2604 chip->pagebuf = -1;
1da177e4 2605
ace4dfee 2606 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2607
7bc3312b 2608 status = chip->waitfunc(mtd, chip);
1da177e4 2609
ace4dfee
TG		 2610 /*
2611 * See if operation failed and additional status checks are
2612 * available
2613 */
2614 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2615 status = chip->errstat(mtd, chip, FL_ERASING,
2616 status, page);
068e3c0a 2617
1da177e4 2618 /* See if block erase succeeded */
a4ab4c5d 2619 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2620 pr_debug("%s: failed erase, page 0x%08x\n",
2621 __func__, page);
1da177e4 2622 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2623 instr->fail_addr =
2624 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2625 goto erase_exit;
2626 }
30f464b7 2627
ace4dfee
TG		 2628 /*
2629 * If BBT requires refresh, set the BBT rewrite flag to the
8b6e50c9 2630 * page being erased.
ace4dfee
TG		 2631 */
2632 if (bbt_masked_page != 0xffffffff &&
2633 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2634 rewrite_bbt[chipnr] =
2635 ((loff_t)page << chip->page_shift);
61b03bd7 2636
1da177e4 2637 /* Increment page address and decrement length */
ace4dfee 2638 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2639 page += pages_per_block;
2640
2641 /* Check, if we cross a chip boundary */
ace4dfee 2642 if (len && !(page & chip->pagemask)) {
1da177e4 2643 chipnr++;
ace4dfee
TG		 2644 chip->select_chip(mtd, -1);
2645 chip->select_chip(mtd, chipnr);
30f464b7 2646
ace4dfee
TG		 2647 /*
2648 * If BBT requires refresh and BBT-PERCHIP, set the BBT
8b6e50c9 2649 * page mask to see if this BBT should be rewritten.
ace4dfee
TG		 2650 */
2651 if (bbt_masked_page != 0xffffffff &&
2652 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2653 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2654 BBT_PAGE_MASK;
1da177e4
LT		 2655 }
2656 }
2657 instr->state = MTD_ERASE_DONE;
2658
7351d3a5 2659erase_exit:
1da177e4
LT		 2660
2661 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2662
2663 /* Deselect and wake up anyone waiting on the device */
2664 nand_release_device(mtd);
2665
49defc01
DW		 2666 /* Do call back function */
2667 if (!ret)
2668 mtd_erase_callback(instr);
2669
ace4dfee
TG		 2670 /*
2671 * If BBT requires refresh and erase was successful, rewrite any
8b6e50c9 2672 * selected bad block tables.
ace4dfee
TG		 2673 */
2674 if (bbt_masked_page == 0xffffffff || ret)
2675 return ret;
2676
2677 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2678 if (!rewrite_bbt[chipnr])
2679 continue;
8b6e50c9 2680 /* Update the BBT for chip */
289c0522
BN		 2681 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2682 __func__, chipnr, rewrite_bbt[chipnr],
2683 chip->bbt_td->pages[chipnr]);
ace4dfee 2684 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2685 }
2686
1da177e4
LT		 2687 /* Return more or less happy */
2688 return ret;
2689}
2690
2691/**
2692 * nand_sync - [MTD Interface] sync
8b6e50c9 2693 * @mtd: MTD device structure
1da177e4 2694 *
8b6e50c9 2695 * Sync is actually a wait for chip ready function.
1da177e4 2696 */
e0c7d767 2697static void nand_sync(struct mtd_info *mtd)
1da177e4 2698{
ace4dfee 2699 struct nand_chip *chip = mtd->priv;
1da177e4 2700
289c0522 2701 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2702
2703 /* Grab the lock and see if the device is available */
ace4dfee 2704 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2705 /* Release it and go back */
e0c7d767 2706 nand_release_device(mtd);
1da177e4
LT		 2707}
2708
1da177e4 2709/**
ace4dfee 2710 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2711 * @mtd: MTD device structure
2712 * @offs: offset relative to mtd start
1da177e4 2713 */
ace4dfee 2714static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2715{
ace4dfee 2716 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2717}
2718
2719/**
ace4dfee 2720 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2721 * @mtd: MTD device structure
2722 * @ofs: offset relative to mtd start
1da177e4 2723 */
e0c7d767 2724static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2725{
ace4dfee 2726 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2727 int ret;
2728
f8ac0414
FF		 2729 ret = nand_block_isbad(mtd, ofs);
2730 if (ret) {
8b6e50c9 2731 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2732 if (ret > 0)
2733 return 0;
e0c7d767
DW		 2734 return ret;
2735 }
1da177e4 2736
ace4dfee 2737 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2738}
2739
962034f4
VW		 2740/**
2741 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2742 * @mtd: MTD device structure
962034f4
VW		 2743 */
2744static int nand_suspend(struct mtd_info *mtd)
2745{
ace4dfee 2746 struct nand_chip *chip = mtd->priv;
962034f4 2747
ace4dfee 2748 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2749}
2750
2751/**
2752 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2753 * @mtd: MTD device structure
962034f4
VW		 2754 */
2755static void nand_resume(struct mtd_info *mtd)
2756{
ace4dfee 2757 struct nand_chip *chip = mtd->priv;
962034f4 2758
ace4dfee 2759 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2760 nand_release_device(mtd);
2761 else
d0370219
BN		 2762 pr_err("%s called for a chip which is not in suspended state\n",
2763 __func__);
962034f4
VW		 2764}
2765
8b6e50c9 2766/* Set default functions */
ace4dfee 2767static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2768{
1da177e4 2769 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2770 if (!chip->chip_delay)
2771 chip->chip_delay = 20;
1da177e4
LT		 2772
2773 /* check, if a user supplied command function given */
ace4dfee
TG		 2774 if (chip->cmdfunc == NULL)
2775 chip->cmdfunc = nand_command;
1da177e4
LT		 2776
2777 /* check, if a user supplied wait function given */
ace4dfee
TG		 2778 if (chip->waitfunc == NULL)
2779 chip->waitfunc = nand_wait;
2780
2781 if (!chip->select_chip)
2782 chip->select_chip = nand_select_chip;
2783 if (!chip->read_byte)
2784 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2785 if (!chip->read_word)
2786 chip->read_word = nand_read_word;
2787 if (!chip->block_bad)
2788 chip->block_bad = nand_block_bad;
2789 if (!chip->block_markbad)
2790 chip->block_markbad = nand_default_block_markbad;
2791 if (!chip->write_buf)
2792 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2793 if (!chip->read_buf)
2794 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2795 if (!chip->verify_buf)
2796 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2797 if (!chip->scan_bbt)
2798 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2799
2800 if (!chip->controller) {
2801 chip->controller = &chip->hwcontrol;
2802 spin_lock_init(&chip->controller->lock);
2803 init_waitqueue_head(&chip->controller->wq);
2804 }
2805
7aa65bfd
TG		 2806}
2807
8b6e50c9 2808/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2809static void sanitize_string(uint8_t *s, size_t len)
2810{
2811 ssize_t i;
2812
8b6e50c9 2813 /* Null terminate */
d1e1f4e4
FF		 2814 s[len - 1] = 0;
2815
8b6e50c9 2816 /* Remove non printable chars */
d1e1f4e4
FF		 2817 for (i = 0; i < len - 1; i++) {
2818 if (s[i] < ' ' || s[i] > 127)
2819 s[i] = '?';
2820 }
2821
8b6e50c9 2822 /* Remove trailing spaces */
d1e1f4e4
FF		 2823 strim(s);
2824}
2825
2826static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2827{
2828 int i;
2829 while (len--) {
2830 crc ^= *p++ << 8;
2831 for (i = 0; i < 8; i++)
2832 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2833 }
2834
2835 return crc;
2836}
2837
6fb277ba 2838/*
8b6e50c9 2839 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2840 */
2841static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2842 int *busw)
6fb277ba
FF		 2843{
2844 struct nand_onfi_params *p = &chip->onfi_params;
2845 int i;
2846 int val;
2847
7854d3f7 2848 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2849 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2850 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2851 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2852 return 0;
2853
6fb277ba
FF		 2854 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2855 for (i = 0; i < 3; i++) {
2856 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2857 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2858 le16_to_cpu(p->crc)) {
9a4d4d69 2859 pr_info("ONFI param page %d valid\n", i);
6fb277ba
FF		 2860 break;
2861 }
2862 }
2863
2864 if (i == 3)
2865 return 0;
2866
8b6e50c9 2867 /* Check version */
6fb277ba 2868 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2869 if (val & (1 << 5))
2870 chip->onfi_version = 23;
2871 else if (val & (1 << 4))
6fb277ba
FF		 2872 chip->onfi_version = 22;
2873 else if (val & (1 << 3))
2874 chip->onfi_version = 21;
2875 else if (val & (1 << 2))
2876 chip->onfi_version = 20;
b7b1a29d 2877 else if (val & (1 << 1))
6fb277ba 2878 chip->onfi_version = 10;
b7b1a29d
BN		 2879 else
2880 chip->onfi_version = 0;
2881
2882 if (!chip->onfi_version) {
d0370219 2883 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 2884 return 0;
2885 }
6fb277ba
FF		 2886
2887 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2888 sanitize_string(p->model, sizeof(p->model));
2889 if (!mtd->name)
2890 mtd->name = p->model;
2891 mtd->writesize = le32_to_cpu(p->byte_per_page);
2892 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2893 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
63795755
MC		 2894 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2895 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
08c248fb 2896 *busw = 0;
6fb277ba 2897 if (le16_to_cpu(p->features) & 1)
08c248fb 2898 *busw = NAND_BUSWIDTH_16;
6fb277ba
FF		 2899
2900 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2901 chip->options |= (NAND_NO_READRDY |
2902 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2903
d42b5de3 2904 pr_info("ONFI flash detected\n");
6fb277ba
FF		 2905 return 1;
2906}
2907
7aa65bfd 2908/*
8b6e50c9 2909 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 2910 */
2911static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2912 struct nand_chip *chip,
7351d3a5
FF		 2913 int busw,
2914 int *maf_id, int *dev_id,
5e81e88a 2915 struct nand_flash_dev *type)
7aa65bfd 2916{
d1e1f4e4 2917 int i, maf_idx;
426c457a 2918 u8 id_data[8];
6fb277ba 2919 int ret;
1da177e4
LT		 2920
2921 /* Select the device */
ace4dfee 2922 chip->select_chip(mtd, 0);
1da177e4 2923
ef89a880
KB		 2924 /*
2925 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 2926 * after power-up.
ef89a880
KB		 2927 */
2928 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2929
1da177e4 2930 /* Send the command for reading device ID */
ace4dfee 2931 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2932
2933 /* Read manufacturer and device IDs */
ace4dfee 2934 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2935 *dev_id = chip->read_byte(mtd);
1da177e4 2936
8b6e50c9
BN		 2937 /*
2938 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 2939 * interface concerns can cause random data which looks like a
2940 * possibly credible NAND flash to appear. If the two results do
2941 * not match, ignore the device completely.
2942 */
2943
2944 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2945
d1e1f4e4 2946 for (i = 0; i < 2; i++)
426c457a 2947 id_data[i] = chip->read_byte(mtd);
ed8165c7 2948
d1e1f4e4 2949 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 2950 pr_info("%s: second ID read did not match "
d0370219
BN		 2951 "%02x,%02x against %02x,%02x\n", __func__,
2952 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2953 return ERR_PTR(-ENODEV);
2954 }
2955
7aa65bfd 2956 if (!type)
5e81e88a
DW		 2957 type = nand_flash_ids;
2958
2959 for (; type->name != NULL; type++)
d1e1f4e4 2960 if (*dev_id == type->id)
f8ac0414 2961 break;
5e81e88a 2962
d1e1f4e4
FF		 2963 chip->onfi_version = 0;
2964 if (!type->name || !type->pagesize) {
6fb277ba 2965 /* Check is chip is ONFI compliant */
08c248fb 2966 ret = nand_flash_detect_onfi(mtd, chip, &busw);
6fb277ba
FF		 2967 if (ret)
2968 goto ident_done;
d1e1f4e4
FF		 2969 }
2970
2971 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2972
2973 /* Read entire ID string */
2974
2975 for (i = 0; i < 8; i++)
2976 id_data[i] = chip->read_byte(mtd);
2977
5e81e88a 2978 if (!type->name)
7aa65bfd
TG		 2979 return ERR_PTR(-ENODEV);
2980
ba0251fe
TG		 2981 if (!mtd->name)
2982 mtd->name = type->name;
2983
69423d99 2984 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 2985
12a40a57 2986 if (!type->pagesize && chip->init_size) {
8b6e50c9 2987 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 2988 busw = chip->init_size(mtd, chip, id_data);
2989 } else if (!type->pagesize) {
7aa65bfd 2990 int extid;
29072b96 2991 /* The 3rd id byte holds MLC / multichip data */
426c457a 2992 chip->cellinfo = id_data[2];
7aa65bfd 2993 /* The 4th id byte is the important one */
426c457a 2994 extid = id_data[3];
61b03bd7 2995
426c457a
KC		 2996 /*
2997 * Field definitions are in the following datasheets:
2998 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 2999 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 3000 *
3001 * Check for wraparound + Samsung ID + nonzero 6th byte
3002 * to decide what to do.
3003 */
3004 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3005 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 3006 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 3007 id_data[5] != 0x00) {
3008 /* Calc pagesize */
3009 mtd->writesize = 2048 << (extid & 0x03);
3010 extid >>= 2;
3011 /* Calc oobsize */
34c5bf6c
BN		 3012 switch (extid & 0x03) {
3013 case 1:
3014 mtd->oobsize = 128;
3015 break;
3016 case 2:
3017 mtd->oobsize = 218;
3018 break;
3019 case 3:
3020 mtd->oobsize = 400;
3021 break;
3022 default:
3023 mtd->oobsize = 436;
3024 break;
3025 }
426c457a
KC		 3026 extid >>= 2;
3027 /* Calc blocksize */
3028 mtd->erasesize = (128 * 1024) <<
3029 (((extid >> 1) & 0x04) | (extid & 0x03));
3030 busw = 0;
3031 } else {
3032 /* Calc pagesize */
3033 mtd->writesize = 1024 << (extid & 0x03);
3034 extid >>= 2;
3035 /* Calc oobsize */
3036 mtd->oobsize = (8 << (extid & 0x01)) *
3037 (mtd->writesize >> 9);
3038 extid >>= 2;
3039 /* Calc blocksize. Blocksize is multiples of 64KiB */
3040 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3041 extid >>= 2;
3042 /* Get buswidth information */
3043 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3044 }
7aa65bfd
TG		 3045 } else {
3046 /*
8b6e50c9 3047 * Old devices have chip data hardcoded in the device id table.
7aa65bfd 3048 */
ba0251fe
TG		 3049 mtd->erasesize = type->erasesize;
3050 mtd->writesize = type->pagesize;
4cbb9b80 3051 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3052 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3053
3054 /*
3055 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3056 * some Spansion chips have erasesize that conflicts with size
8b6e50c9 3057 * listed in nand_ids table.
2173bae8
BN		 3058 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3059 */
3060 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3061 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3062 id_data[7] == 0x00 && mtd->writesize == 512) {
3063 mtd->erasesize = 128 * 1024;
3064 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3065 }
7aa65bfd 3066 }
d1e1f4e4
FF		 3067 /* Get chip options, preserve non chip based options */
3068 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3069 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3070
8b6e50c9
BN		 3071 /*
3072 * Check if chip is not a Samsung device. Do not clear the
3073 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3074 */
3075 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3076 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3077ident_done:
3078
3079 /*
8b6e50c9 3080 * Set chip as a default. Board drivers can override it, if necessary.
d1e1f4e4
FF		 3081 */
3082 chip->options |= NAND_NO_AUTOINCR;
1da177e4 3083
7aa65bfd 3084 /* Try to identify manufacturer */
9a909867 3085 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3086 if (nand_manuf_ids[maf_idx].id == *maf_id)
3087 break;
3088 }
0ea4a755 3089
7aa65bfd
TG		 3090 /*
3091 * Check, if buswidth is correct. Hardware drivers should set
8b6e50c9 3092 * chip correct!
7aa65bfd 3093 */
ace4dfee 3094 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
9a4d4d69 3095 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 3096 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3097 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 3098 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 3099 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3100 busw ? 16 : 8);
7aa65bfd
TG		 3101 return ERR_PTR(-EINVAL);
3102 }
61b03bd7 3103
7aa65bfd 3104 /* Calculate the address shift from the page size */
ace4dfee 3105 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3106 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3107 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3108
ace4dfee 3109 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3110 ffs(mtd->erasesize) - 1;
69423d99
AH		 3111 if (chip->chipsize & 0xffffffff)
3112 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3113 else {
3114 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3115 chip->chip_shift += 32 - 1;
3116 }
1da177e4 3117
26d9be11
AB		 3118 chip->badblockbits = 8;
3119
7aa65bfd 3120 /* Set the bad block position */
065a1ed8 3121 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3122 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3123 else
3124 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3125
b60b08b0
KC		 3126 /*
3127 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3128 * on Samsung and Hynix MLC devices; stored in first two pages
3129 * of each block on Micron devices with 2KiB pages and on
8c342335
BN		 3130 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
3131 * All others scan only the first page.
b60b08b0
KC		 3132 */
3133 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3134 (*maf_id == NAND_MFR_SAMSUNG ||
3135 *maf_id == NAND_MFR_HYNIX))
5fb1549d 3136 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3137 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3138 (*maf_id == NAND_MFR_SAMSUNG ||
3139 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3140 *maf_id == NAND_MFR_TOSHIBA ||
8c342335
BN		 3141 *maf_id == NAND_MFR_AMD ||
3142 *maf_id == NAND_MFR_MACRONIX)) ||
c7b28e25
BN		 3143 (mtd->writesize == 2048 &&
3144 *maf_id == NAND_MFR_MICRON))
5fb1549d 3145 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
c7b28e25 3146
7aa65bfd 3147 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3148 if (chip->options & NAND_4PAGE_ARRAY)
3149 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3150 else
ace4dfee 3151 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3152
8b6e50c9 3153 /* Do not replace user supplied command function! */
ace4dfee
TG		 3154 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3155 chip->cmdfunc = nand_command_lp;
7aa65bfd 3156
9a4d4d69 3157 pr_info("NAND device: Manufacturer ID:"
d1e1f4e4
FF		 3158 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3159 nand_manuf_ids[maf_idx].name,
0b524fb9 3160 chip->onfi_version ? chip->onfi_params.model : type->name);
7aa65bfd
TG		 3161
3162 return type;
3163}
3164
7aa65bfd 3165/**
3b85c321 3166 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3167 * @mtd: MTD device structure
3168 * @maxchips: number of chips to scan for
3169 * @table: alternative NAND ID table
7aa65bfd 3170 *
8b6e50c9
BN		 3171 * This is the first phase of the normal nand_scan() function. It reads the
3172 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3173 *
3b85c321 3174 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3175 */
5e81e88a
DW		 3176int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3177 struct nand_flash_dev *table)
7aa65bfd 3178{
d1e1f4e4 3179 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3180 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3181 struct nand_flash_dev *type;
3182
7aa65bfd 3183 /* Get buswidth to select the correct functions */
ace4dfee 3184 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3185 /* Set the default functions */
ace4dfee 3186 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3187
3188 /* Read the flash type */
7351d3a5
FF		 3189 type = nand_get_flash_type(mtd, chip, busw,
3190 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3191
3192 if (IS_ERR(type)) {
b1c6e6db 3193 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3194 pr_warn("No NAND device found\n");
ace4dfee 3195 chip->select_chip(mtd, -1);
7aa65bfd 3196 return PTR_ERR(type);
1da177e4
LT		 3197 }
3198
7aa65bfd 3199 /* Check for a chip array */
e0c7d767 3200 for (i = 1; i < maxchips; i++) {
ace4dfee 3201 chip->select_chip(mtd, i);
ef89a880
KB		 3202 /* See comment in nand_get_flash_type for reset */
3203 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3204 /* Send the command for reading device ID */
ace4dfee 3205 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3206 /* Read manufacturer and device IDs */
ace4dfee 3207 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3208 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3209 break;
3210 }
3211 if (i > 1)
9a4d4d69 3212 pr_info("%d NAND chips detected\n", i);
61b03bd7 3213
1da177e4 3214 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3215 chip->numchips = i;
3216 mtd->size = i * chip->chipsize;
7aa65bfd 3217
3b85c321
DW		 3218 return 0;
3219}
7351d3a5 3220EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3221
3222
3223/**
3224 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3225 * @mtd: MTD device structure
3b85c321 3226 *
8b6e50c9
BN		 3227 * This is the second phase of the normal nand_scan() function. It fills out
3228 * all the uninitialized function pointers with the defaults and scans for a
3229 * bad block table if appropriate.
3b85c321
DW		 3230 */
3231int nand_scan_tail(struct mtd_info *mtd)
3232{
3233 int i;
3234 struct nand_chip *chip = mtd->priv;
3235
e2414f4c
BN		 3236 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3237 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3238 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3239
4bf63fcb
DW		 3240 if (!(chip->options & NAND_OWN_BUFFERS))
3241 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3242 if (!chip->buffers)
3243 return -ENOMEM;
3244
7dcdcbef 3245 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3246 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3247
7aa65bfd 3248 /*
8b6e50c9 3249 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3250 */
193bd400 3251 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3252 switch (mtd->oobsize) {
1da177e4 3253 case 8:
5bd34c09 3254 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3255 break;
3256 case 16:
5bd34c09 3257 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3258 break;
3259 case 64:
5bd34c09 3260 chip->ecc.layout = &nand_oob_64;
1da177e4 3261 break;
81ec5364
TG		 3262 case 128:
3263 chip->ecc.layout = &nand_oob_128;
3264 break;
1da177e4 3265 default:
d0370219
BN		 3266 pr_warn("No oob scheme defined for oobsize %d\n",
3267 mtd->oobsize);
1da177e4
LT		 3268 BUG();
3269 }
3270 }
61b03bd7 3271
956e944c
DW		 3272 if (!chip->write_page)
3273 chip->write_page = nand_write_page;
3274
61b03bd7 3275 /*
8b6e50c9 3276 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3277 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3278 */
956e944c 3279
ace4dfee 3280 switch (chip->ecc.mode) {
6e0cb135
SN		 3281 case NAND_ECC_HW_OOB_FIRST:
3282 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3283 if (!chip->ecc.calculate || !chip->ecc.correct ||
3284 !chip->ecc.hwctl) {
9a4d4d69 3285 pr_warn("No ECC functions supplied; "
d0370219 3286 "hardware ECC not possible\n");
6e0cb135
SN		 3287 BUG();
3288 }
3289 if (!chip->ecc.read_page)
3290 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3291
6dfc6d25 3292 case NAND_ECC_HW:
8b6e50c9 3293 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3294 if (!chip->ecc.read_page)
3295 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3296 if (!chip->ecc.write_page)
3297 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3298 if (!chip->ecc.read_page_raw)
3299 chip->ecc.read_page_raw = nand_read_page_raw;
3300 if (!chip->ecc.write_page_raw)
3301 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3302 if (!chip->ecc.read_oob)
3303 chip->ecc.read_oob = nand_read_oob_std;
3304 if (!chip->ecc.write_oob)
3305 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3306
6dfc6d25 3307 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3308 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3309 !chip->ecc.hwctl) &&
3310 (!chip->ecc.read_page ||
1c45f604 3311 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3312 !chip->ecc.write_page ||
1c45f604 3313 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 3314 pr_warn("No ECC functions supplied; "
d0370219 3315 "hardware ECC not possible\n");
6dfc6d25
TG		 3316 BUG();
3317 }
8b6e50c9 3318 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3319 if (!chip->ecc.read_page)
3320 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3321 if (!chip->ecc.write_page)
3322 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3323 if (!chip->ecc.read_page_raw)
3324 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3325 if (!chip->ecc.write_page_raw)
3326 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3327 if (!chip->ecc.read_oob)
3328 chip->ecc.read_oob = nand_read_oob_syndrome;
3329 if (!chip->ecc.write_oob)
3330 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3331
ace4dfee 3332 if (mtd->writesize >= chip->ecc.size)
6dfc6d25 3333 break;
9a4d4d69 3334 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 3335 "%d byte page size, fallback to SW ECC\n",
3336 chip->ecc.size, mtd->writesize);
ace4dfee 3337 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3338
6dfc6d25 3339 case NAND_ECC_SOFT:
ace4dfee
TG		 3340 chip->ecc.calculate = nand_calculate_ecc;
3341 chip->ecc.correct = nand_correct_data;
f5bbdacc 3342 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3343 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3344 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3345 chip->ecc.read_page_raw = nand_read_page_raw;
3346 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3347 chip->ecc.read_oob = nand_read_oob_std;
3348 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3349 if (!chip->ecc.size)
3350 chip->ecc.size = 256;
ace4dfee 3351 chip->ecc.bytes = 3;
6a918bad 3352 chip->ecc.strength = 1;
1da177e4 3353 break;
61b03bd7 3354
193bd400
ID		 3355 case NAND_ECC_SOFT_BCH:
3356 if (!mtd_nand_has_bch()) {
9a4d4d69 3357 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3358 BUG();
3359 }
3360 chip->ecc.calculate = nand_bch_calculate_ecc;
3361 chip->ecc.correct = nand_bch_correct_data;
3362 chip->ecc.read_page = nand_read_page_swecc;
3363 chip->ecc.read_subpage = nand_read_subpage;
3364 chip->ecc.write_page = nand_write_page_swecc;
3365 chip->ecc.read_page_raw = nand_read_page_raw;
3366 chip->ecc.write_page_raw = nand_write_page_raw;
3367 chip->ecc.read_oob = nand_read_oob_std;
3368 chip->ecc.write_oob = nand_write_oob_std;
3369 /*
3370 * Board driver should supply ecc.size and ecc.bytes values to
3371 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3372 * for details. Otherwise, default to 4 bits for large page
3373 * devices.
193bd400
ID		 3374 */
3375 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3376 chip->ecc.size = 512;
3377 chip->ecc.bytes = 7;
3378 }
3379 chip->ecc.priv = nand_bch_init(mtd,
3380 chip->ecc.size,
3381 chip->ecc.bytes,
3382 &chip->ecc.layout);
3383 if (!chip->ecc.priv) {
9a4d4d69 3384 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3385 BUG();
3386 }
6a918bad
MD		 3387 chip->ecc.strength =
3388 chip->ecc.bytes*8 / fls(8*chip->ecc.size);
193bd400
ID		 3389 break;
3390
61b03bd7 3391 case NAND_ECC_NONE:
9a4d4d69 3392 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3393 "This is not recommended!\n");
8593fbc6
TG		 3394 chip->ecc.read_page = nand_read_page_raw;
3395 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3396 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3397 chip->ecc.read_page_raw = nand_read_page_raw;
3398 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3399 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3400 chip->ecc.size = mtd->writesize;
3401 chip->ecc.bytes = 0;
6a918bad 3402 chip->ecc.strength = 0;
1da177e4 3403 break;
956e944c 3404
1da177e4 3405 default:
d0370219 3406 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 3407 BUG();
1da177e4 3408 }
61b03bd7 3409
9ce244b3 3410 /* For many systems, the standard OOB write also works for raw */
c46f6483
BN		 3411 if (!chip->ecc.read_oob_raw)
3412 chip->ecc.read_oob_raw = chip->ecc.read_oob;
9ce244b3
BN		 3413 if (!chip->ecc.write_oob_raw)
3414 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3415
5bd34c09
TG		 3416 /*
3417 * The number of bytes available for a client to place data into
8b6e50c9 3418 * the out of band area.
5bd34c09
TG		 3419 */
3420 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3421 for (i = 0; chip->ecc.layout->oobfree[i].length
3422 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3423 chip->ecc.layout->oobavail +=
3424 chip->ecc.layout->oobfree[i].length;
1f92267c 3425 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3426
7aa65bfd
TG		 3427 /*
3428 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3429 * mode.
7aa65bfd 3430 */
ace4dfee 3431 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3432 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 3433 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3434 BUG();
1da177e4 3435 }
f5bbdacc 3436 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3437
8b6e50c9 3438 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 3439 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3440 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3441 switch (chip->ecc.steps) {
29072b96
TG		 3442 case 2:
3443 mtd->subpage_sft = 1;
3444 break;
3445 case 4:
3446 case 8:
81ec5364 3447 case 16:
29072b96
TG		 3448 mtd->subpage_sft = 2;
3449 break;
3450 }
3451 }
3452 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3453
04bbd0ea 3454 /* Initialize state */
ace4dfee 3455 chip->state = FL_READY;
1da177e4
LT		 3456
3457 /* De-select the device */
ace4dfee 3458 chip->select_chip(mtd, -1);
1da177e4
LT		 3459
3460 /* Invalidate the pagebuffer reference */
ace4dfee 3461 chip->pagebuf = -1;
1da177e4
LT		 3462
3463 /* Fill in remaining MTD driver data */
3464 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3465 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3466 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 3467 mtd->_erase = nand_erase;
3468 mtd->_point = NULL;
3469 mtd->_unpoint = NULL;
3470 mtd->_read = nand_read;
3471 mtd->_write = nand_write;
3472 mtd->_panic_write = panic_nand_write;
3473 mtd->_read_oob = nand_read_oob;
3474 mtd->_write_oob = nand_write_oob;
3475 mtd->_sync = nand_sync;
3476 mtd->_lock = NULL;
3477 mtd->_unlock = NULL;
3478 mtd->_suspend = nand_suspend;
3479 mtd->_resume = nand_resume;
3480 mtd->_block_isbad = nand_block_isbad;
3481 mtd->_block_markbad = nand_block_markbad;
cbcab65a 3482 mtd->writebufsize = mtd->writesize;
1da177e4 3483
6a918bad 3484 /* propagate ecc info to mtd_info */
5bd34c09 3485 mtd->ecclayout = chip->ecc.layout;
6a918bad 3486 mtd->ecc_strength = chip->ecc.strength * chip->ecc.steps;
1da177e4 3487
0040bf38 3488 /* Check, if we should skip the bad block table scan */
ace4dfee 3489 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3490 return 0;
1da177e4
LT		 3491
3492 /* Build bad block table */
ace4dfee 3493 return chip->scan_bbt(mtd);
1da177e4 3494}
7351d3a5 3495EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3496
8b6e50c9
BN		 3497/*
3498 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3499 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3500 * to call us from in-kernel code if the core NAND support is modular.
3501 */
3b85c321
DW		 3502#ifdef MODULE
3503#define caller_is_module() (1)
3504#else
3505#define caller_is_module() \
a6e6abd5 3506 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3507#endif
3508
3509/**
3510 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3511 * @mtd: MTD device structure
3512 * @maxchips: number of chips to scan for
3b85c321 3513 *
8b6e50c9
BN		 3514 * This fills out all the uninitialized function pointers with the defaults.
3515 * The flash ID is read and the mtd/chip structures are filled with the
3516 * appropriate values. The mtd->owner field must be set to the module of the
3517 * caller.
3b85c321
DW		 3518 */
3519int nand_scan(struct mtd_info *mtd, int maxchips)
3520{
3521 int ret;
3522
3523 /* Many callers got this wrong, so check for it for a while... */
3524 if (!mtd->owner && caller_is_module()) {
d0370219 3525 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3526 BUG();
3527 }
3528
5e81e88a 3529 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3530 if (!ret)
3531 ret = nand_scan_tail(mtd);
3532 return ret;
3533}
7351d3a5 3534EXPORT_SYMBOL(nand_scan);
3b85c321 3535
1da177e4 3536/**
61b03bd7 3537 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3538 * @mtd: MTD device structure
3539 */
e0c7d767 3540void nand_release(struct mtd_info *mtd)
1da177e4 3541{
ace4dfee 3542 struct nand_chip *chip = mtd->priv;
1da177e4 3543
193bd400
ID		 3544 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3545 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3546
5ffcaf3d 3547 mtd_device_unregister(mtd);
1da177e4 3548
fa671646 3549 /* Free bad block table memory */
ace4dfee 3550 kfree(chip->bbt);
4bf63fcb
DW		 3551 if (!(chip->options & NAND_OWN_BUFFERS))
3552 kfree(chip->buffers);
58373ff0
BN		 3553
3554 /* Free bad block descriptor memory */
3555 if (chip->badblock_pattern && chip->badblock_pattern->options
3556 & NAND_BBT_DYNAMICSTRUCT)
3557 kfree(chip->badblock_pattern);
1da177e4 3558}
e0c7d767 3559EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3560
3561static int __init nand_base_init(void)
3562{
3563 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3564 return 0;
3565}
3566
3567static void __exit nand_base_exit(void)
3568{
3569 led_trigger_unregister_simple(nand_led_trigger);
3570}
3571
3572module_init(nand_base_init);
3573module_exit(nand_base_exit);
3574
e0c7d767 3575MODULE_LICENSE("GPL");
7351d3a5
FF		 3576MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3577MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3578MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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