Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 7 | * |
1da177e4 | 8 | * Additional technical information is available on |
8b2b403c | 9 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 10 | * |
1da177e4 | 11 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 12 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 13 | * |
ace4dfee | 14 | * Credits: |
61b03bd7 TG |
15 | * David Woodhouse for adding multichip support |
16 | * | |
1da177e4 LT |
17 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
18 | * rework for 2K page size chips | |
19 | * | |
ace4dfee | 20 | * TODO: |
1da177e4 LT |
21 | * Enable cached programming for 2k page size chips |
22 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 23 | * if we have HW ECC support. |
c0b8ba7b | 24 | * BBT table is not serialized, has to be fixed |
1da177e4 | 25 | * |
1da177e4 LT |
26 | * This program is free software; you can redistribute it and/or modify |
27 | * it under the terms of the GNU General Public License version 2 as | |
28 | * published by the Free Software Foundation. | |
29 | * | |
30 | */ | |
31 | ||
20171642 EG |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
552d9205 | 34 | #include <linux/module.h> |
1da177e4 LT |
35 | #include <linux/delay.h> |
36 | #include <linux/errno.h> | |
7aa65bfd | 37 | #include <linux/err.h> |
1da177e4 LT |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
40 | #include <linux/types.h> | |
41 | #include <linux/mtd/mtd.h> | |
42 | #include <linux/mtd/nand.h> | |
43 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 44 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
45 | #include <linux/interrupt.h> |
46 | #include <linux/bitops.h> | |
8fe833c1 | 47 | #include <linux/leds.h> |
7351d3a5 | 48 | #include <linux/io.h> |
1da177e4 | 49 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
50 | |
51 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 52 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
53 | .eccbytes = 3, |
54 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
55 | .oobfree = { |
56 | {.offset = 3, | |
57 | .length = 2}, | |
58 | {.offset = 6, | |
f8ac0414 | 59 | .length = 2} } |
1da177e4 LT |
60 | }; |
61 | ||
5bd34c09 | 62 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
63 | .eccbytes = 6, |
64 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
65 | .oobfree = { |
66 | {.offset = 8, | |
f8ac0414 | 67 | . length = 8} } |
1da177e4 LT |
68 | }; |
69 | ||
5bd34c09 | 70 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
71 | .eccbytes = 24, |
72 | .eccpos = { | |
e0c7d767 DW |
73 | 40, 41, 42, 43, 44, 45, 46, 47, |
74 | 48, 49, 50, 51, 52, 53, 54, 55, | |
75 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
76 | .oobfree = { |
77 | {.offset = 2, | |
f8ac0414 | 78 | .length = 38} } |
1da177e4 LT |
79 | }; |
80 | ||
81ec5364 TG |
81 | static struct nand_ecclayout nand_oob_128 = { |
82 | .eccbytes = 48, | |
83 | .eccpos = { | |
84 | 80, 81, 82, 83, 84, 85, 86, 87, | |
85 | 88, 89, 90, 91, 92, 93, 94, 95, | |
86 | 96, 97, 98, 99, 100, 101, 102, 103, | |
87 | 104, 105, 106, 107, 108, 109, 110, 111, | |
88 | 112, 113, 114, 115, 116, 117, 118, 119, | |
89 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
90 | .oobfree = { | |
91 | {.offset = 2, | |
f8ac0414 | 92 | .length = 78} } |
81ec5364 TG |
93 | }; |
94 | ||
6a8214aa | 95 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
1da177e4 | 96 | |
8593fbc6 TG |
97 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
98 | struct mtd_oob_ops *ops); | |
99 | ||
d470a97c | 100 | /* |
8e87d782 | 101 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
102 | * compiled away when LED support is disabled. |
103 | */ | |
104 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
105 | ||
6fe5a6ac VS |
106 | static int check_offs_len(struct mtd_info *mtd, |
107 | loff_t ofs, uint64_t len) | |
108 | { | |
109 | struct nand_chip *chip = mtd->priv; | |
110 | int ret = 0; | |
111 | ||
112 | /* Start address must align on block boundary */ | |
daae74ca | 113 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 114 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
115 | ret = -EINVAL; |
116 | } | |
117 | ||
118 | /* Length must align on block boundary */ | |
daae74ca | 119 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 120 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
121 | ret = -EINVAL; |
122 | } | |
123 | ||
6fe5a6ac VS |
124 | return ret; |
125 | } | |
126 | ||
1da177e4 LT |
127 | /** |
128 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 129 | * @mtd: MTD device structure |
61b03bd7 | 130 | * |
b0bb6903 | 131 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 132 | */ |
e0c7d767 | 133 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 134 | { |
ace4dfee | 135 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 136 | |
a36ed299 | 137 | /* Release the controller and the chip */ |
ace4dfee TG |
138 | spin_lock(&chip->controller->lock); |
139 | chip->controller->active = NULL; | |
140 | chip->state = FL_READY; | |
141 | wake_up(&chip->controller->wq); | |
142 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
143 | } |
144 | ||
145 | /** | |
146 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 147 | * @mtd: MTD device structure |
1da177e4 | 148 | * |
7854d3f7 | 149 | * Default read function for 8bit buswidth |
1da177e4 | 150 | */ |
58dd8f2b | 151 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 152 | { |
ace4dfee TG |
153 | struct nand_chip *chip = mtd->priv; |
154 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
155 | } |
156 | ||
1da177e4 | 157 | /** |
064a7694 | 158 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
7854d3f7 | 159 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 160 | * @mtd: MTD device structure |
1da177e4 | 161 | * |
7854d3f7 BN |
162 | * Default read function for 16bit buswidth with endianness conversion. |
163 | * | |
1da177e4 | 164 | */ |
58dd8f2b | 165 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 166 | { |
ace4dfee TG |
167 | struct nand_chip *chip = mtd->priv; |
168 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
169 | } |
170 | ||
1da177e4 LT |
171 | /** |
172 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 173 | * @mtd: MTD device structure |
1da177e4 | 174 | * |
7854d3f7 | 175 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
176 | */ |
177 | static u16 nand_read_word(struct mtd_info *mtd) | |
178 | { | |
ace4dfee TG |
179 | struct nand_chip *chip = mtd->priv; |
180 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
181 | } |
182 | ||
1da177e4 LT |
183 | /** |
184 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
185 | * @mtd: MTD device structure |
186 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
187 | * |
188 | * Default select function for 1 chip devices. | |
189 | */ | |
ace4dfee | 190 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 191 | { |
ace4dfee TG |
192 | struct nand_chip *chip = mtd->priv; |
193 | ||
194 | switch (chipnr) { | |
1da177e4 | 195 | case -1: |
ace4dfee | 196 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
197 | break; |
198 | case 0: | |
1da177e4 LT |
199 | break; |
200 | ||
201 | default: | |
202 | BUG(); | |
203 | } | |
204 | } | |
205 | ||
05f78359 UKK |
206 | /** |
207 | * nand_write_byte - [DEFAULT] write single byte to chip | |
208 | * @mtd: MTD device structure | |
209 | * @byte: value to write | |
210 | * | |
211 | * Default function to write a byte to I/O[7:0] | |
212 | */ | |
213 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
214 | { | |
215 | struct nand_chip *chip = mtd->priv; | |
216 | ||
217 | chip->write_buf(mtd, &byte, 1); | |
218 | } | |
219 | ||
220 | /** | |
221 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
222 | * @mtd: MTD device structure | |
223 | * @byte: value to write | |
224 | * | |
225 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
226 | */ | |
227 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
228 | { | |
229 | struct nand_chip *chip = mtd->priv; | |
230 | uint16_t word = byte; | |
231 | ||
232 | /* | |
233 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
234 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
235 | * | |
236 | * When the host supports a 16-bit bus width, only data is | |
237 | * transferred at the 16-bit width. All address and command line | |
238 | * transfers shall use only the lower 8-bits of the data bus. During | |
239 | * command transfers, the host may place any value on the upper | |
240 | * 8-bits of the data bus. During address transfers, the host shall | |
241 | * set the upper 8-bits of the data bus to 00h. | |
242 | * | |
243 | * One user of the write_byte callback is nand_onfi_set_features. The | |
244 | * four parameters are specified to be written to I/O[7:0], but this is | |
245 | * neither an address nor a command transfer. Let's assume a 0 on the | |
246 | * upper I/O lines is OK. | |
247 | */ | |
248 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
249 | } | |
250 | ||
1da177e4 LT |
251 | /** |
252 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
253 | * @mtd: MTD device structure |
254 | * @buf: data buffer | |
255 | * @len: number of bytes to write | |
1da177e4 | 256 | * |
7854d3f7 | 257 | * Default write function for 8bit buswidth. |
1da177e4 | 258 | */ |
58dd8f2b | 259 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 260 | { |
ace4dfee | 261 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 262 | |
76413839 | 263 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
264 | } |
265 | ||
266 | /** | |
61b03bd7 | 267 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
268 | * @mtd: MTD device structure |
269 | * @buf: buffer to store date | |
270 | * @len: number of bytes to read | |
1da177e4 | 271 | * |
7854d3f7 | 272 | * Default read function for 8bit buswidth. |
1da177e4 | 273 | */ |
58dd8f2b | 274 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 275 | { |
ace4dfee | 276 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 277 | |
76413839 | 278 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
279 | } |
280 | ||
1da177e4 LT |
281 | /** |
282 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
283 | * @mtd: MTD device structure |
284 | * @buf: data buffer | |
285 | * @len: number of bytes to write | |
1da177e4 | 286 | * |
7854d3f7 | 287 | * Default write function for 16bit buswidth. |
1da177e4 | 288 | */ |
58dd8f2b | 289 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 290 | { |
ace4dfee | 291 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 292 | u16 *p = (u16 *) buf; |
61b03bd7 | 293 | |
76413839 | 294 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
295 | } |
296 | ||
297 | /** | |
61b03bd7 | 298 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
299 | * @mtd: MTD device structure |
300 | * @buf: buffer to store date | |
301 | * @len: number of bytes to read | |
1da177e4 | 302 | * |
7854d3f7 | 303 | * Default read function for 16bit buswidth. |
1da177e4 | 304 | */ |
58dd8f2b | 305 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 306 | { |
ace4dfee | 307 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 308 | u16 *p = (u16 *) buf; |
1da177e4 | 309 | |
76413839 | 310 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
311 | } |
312 | ||
1da177e4 LT |
313 | /** |
314 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
315 | * @mtd: MTD device structure |
316 | * @ofs: offset from device start | |
317 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 318 | * |
61b03bd7 | 319 | * Check, if the block is bad. |
1da177e4 LT |
320 | */ |
321 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
322 | { | |
cdbec050 | 323 | int page, chipnr, res = 0, i = 0; |
ace4dfee | 324 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
325 | u16 bad; |
326 | ||
5fb1549d | 327 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
328 | ofs += mtd->erasesize - mtd->writesize; |
329 | ||
1a12f46a TK |
330 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
331 | ||
1da177e4 | 332 | if (getchip) { |
ace4dfee | 333 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 334 | |
6a8214aa | 335 | nand_get_device(mtd, FL_READING); |
1da177e4 LT |
336 | |
337 | /* Select the NAND device */ | |
ace4dfee | 338 | chip->select_chip(mtd, chipnr); |
1a12f46a | 339 | } |
1da177e4 | 340 | |
cdbec050 BN |
341 | do { |
342 | if (chip->options & NAND_BUSWIDTH_16) { | |
343 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
344 | chip->badblockpos & 0xFE, page); | |
345 | bad = cpu_to_le16(chip->read_word(mtd)); | |
346 | if (chip->badblockpos & 0x1) | |
347 | bad >>= 8; | |
348 | else | |
349 | bad &= 0xFF; | |
350 | } else { | |
351 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
352 | page); | |
353 | bad = chip->read_byte(mtd); | |
354 | } | |
355 | ||
356 | if (likely(chip->badblockbits == 8)) | |
357 | res = bad != 0xFF; | |
e0b58d0a | 358 | else |
cdbec050 BN |
359 | res = hweight8(bad) < chip->badblockbits; |
360 | ofs += mtd->writesize; | |
361 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
362 | i++; | |
363 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 364 | |
b0bb6903 HS |
365 | if (getchip) { |
366 | chip->select_chip(mtd, -1); | |
1da177e4 | 367 | nand_release_device(mtd); |
b0bb6903 | 368 | } |
61b03bd7 | 369 | |
1da177e4 LT |
370 | return res; |
371 | } | |
372 | ||
373 | /** | |
5a0edb25 | 374 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
375 | * @mtd: MTD device structure |
376 | * @ofs: offset from device start | |
1da177e4 | 377 | * |
8b6e50c9 | 378 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
379 | * specific driver. It provides the details for writing a bad block marker to a |
380 | * block. | |
381 | */ | |
382 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
383 | { | |
384 | struct nand_chip *chip = mtd->priv; | |
385 | struct mtd_oob_ops ops; | |
386 | uint8_t buf[2] = { 0, 0 }; | |
387 | int ret = 0, res, i = 0; | |
388 | ||
389 | ops.datbuf = NULL; | |
390 | ops.oobbuf = buf; | |
391 | ops.ooboffs = chip->badblockpos; | |
392 | if (chip->options & NAND_BUSWIDTH_16) { | |
393 | ops.ooboffs &= ~0x01; | |
394 | ops.len = ops.ooblen = 2; | |
395 | } else { | |
396 | ops.len = ops.ooblen = 1; | |
397 | } | |
398 | ops.mode = MTD_OPS_PLACE_OOB; | |
399 | ||
400 | /* Write to first/last page(s) if necessary */ | |
401 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
402 | ofs += mtd->erasesize - mtd->writesize; | |
403 | do { | |
404 | res = nand_do_write_oob(mtd, ofs, &ops); | |
405 | if (!ret) | |
406 | ret = res; | |
407 | ||
408 | i++; | |
409 | ofs += mtd->writesize; | |
410 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
411 | ||
412 | return ret; | |
413 | } | |
414 | ||
415 | /** | |
416 | * nand_block_markbad_lowlevel - mark a block bad | |
417 | * @mtd: MTD device structure | |
418 | * @ofs: offset from device start | |
419 | * | |
420 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
421 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
422 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
423 | * | |
b32843b7 | 424 | * We try operations in the following order: |
e2414f4c | 425 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
426 | * (2) write bad block marker to OOB area of affected block (unless flag |
427 | * NAND_BBT_NO_OOB_BBM is present) | |
428 | * (3) update the BBT | |
429 | * Note that we retain the first error encountered in (2) or (3), finish the | |
e2414f4c | 430 | * procedures, and dump the error in the end. |
1da177e4 | 431 | */ |
5a0edb25 | 432 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 433 | { |
ace4dfee | 434 | struct nand_chip *chip = mtd->priv; |
b32843b7 | 435 | int res, ret = 0; |
61b03bd7 | 436 | |
b32843b7 | 437 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
438 | struct erase_info einfo; |
439 | ||
440 | /* Attempt erase before marking OOB */ | |
441 | memset(&einfo, 0, sizeof(einfo)); | |
442 | einfo.mtd = mtd; | |
443 | einfo.addr = ofs; | |
daae74ca | 444 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 445 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 446 | |
b32843b7 | 447 | /* Write bad block marker to OOB */ |
6a8214aa | 448 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 449 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 450 | nand_release_device(mtd); |
f1a28c02 | 451 | } |
e2414f4c | 452 | |
b32843b7 BN |
453 | /* Mark block bad in BBT */ |
454 | if (chip->bbt) { | |
455 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
456 | if (!ret) |
457 | ret = res; | |
458 | } | |
459 | ||
f1a28c02 TG |
460 | if (!ret) |
461 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 462 | |
f1a28c02 | 463 | return ret; |
1da177e4 LT |
464 | } |
465 | ||
61b03bd7 | 466 | /** |
1da177e4 | 467 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 468 | * @mtd: MTD device structure |
1da177e4 | 469 | * |
8b6e50c9 BN |
470 | * Check, if the device is write protected. The function expects, that the |
471 | * device is already selected. | |
1da177e4 | 472 | */ |
e0c7d767 | 473 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 474 | { |
ace4dfee | 475 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 476 | |
8b6e50c9 | 477 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
478 | if (chip->options & NAND_BROKEN_XD) |
479 | return 0; | |
480 | ||
1da177e4 | 481 | /* Check the WP bit */ |
ace4dfee TG |
482 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
483 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
484 | } |
485 | ||
486 | /** | |
487 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
488 | * @mtd: MTD device structure |
489 | * @ofs: offset from device start | |
490 | * @getchip: 0, if the chip is already selected | |
491 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
492 | * |
493 | * Check, if the block is bad. Either by reading the bad block table or | |
494 | * calling of the scan function. | |
495 | */ | |
2c0a2bed TG |
496 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
497 | int allowbbt) | |
1da177e4 | 498 | { |
ace4dfee | 499 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 500 | |
ace4dfee TG |
501 | if (!chip->bbt) |
502 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 503 | |
1da177e4 | 504 | /* Return info from the table */ |
e0c7d767 | 505 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
506 | } |
507 | ||
2af7c653 SK |
508 | /** |
509 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
510 | * @mtd: MTD device structure |
511 | * @timeo: Timeout | |
2af7c653 SK |
512 | * |
513 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
514 | * context. | |
515 | */ | |
516 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
517 | { | |
518 | struct nand_chip *chip = mtd->priv; | |
519 | int i; | |
520 | ||
521 | /* Wait for the device to get ready */ | |
522 | for (i = 0; i < timeo; i++) { | |
523 | if (chip->dev_ready(mtd)) | |
524 | break; | |
525 | touch_softlockup_watchdog(); | |
526 | mdelay(1); | |
527 | } | |
528 | } | |
529 | ||
7854d3f7 | 530 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 531 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 532 | { |
ace4dfee | 533 | struct nand_chip *chip = mtd->priv; |
ca6a2489 | 534 | unsigned long timeo = jiffies + msecs_to_jiffies(20); |
3b88775c | 535 | |
2af7c653 SK |
536 | /* 400ms timeout */ |
537 | if (in_interrupt() || oops_in_progress) | |
538 | return panic_nand_wait_ready(mtd, 400); | |
539 | ||
8fe833c1 | 540 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 541 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 542 | do { |
ace4dfee | 543 | if (chip->dev_ready(mtd)) |
8fe833c1 | 544 | break; |
8446f1d3 | 545 | touch_softlockup_watchdog(); |
61b03bd7 | 546 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 547 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 548 | } |
4b648b02 | 549 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 550 | |
1da177e4 LT |
551 | /** |
552 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
553 | * @mtd: MTD device structure |
554 | * @command: the command to be sent | |
555 | * @column: the column address for this command, -1 if none | |
556 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 557 | * |
8b6e50c9 | 558 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 559 | * (512 Bytes per page). |
1da177e4 | 560 | */ |
7abd3ef9 TG |
561 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
562 | int column, int page_addr) | |
1da177e4 | 563 | { |
ace4dfee | 564 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 565 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 566 | |
8b6e50c9 | 567 | /* Write out the command to the device */ |
1da177e4 LT |
568 | if (command == NAND_CMD_SEQIN) { |
569 | int readcmd; | |
570 | ||
28318776 | 571 | if (column >= mtd->writesize) { |
1da177e4 | 572 | /* OOB area */ |
28318776 | 573 | column -= mtd->writesize; |
1da177e4 LT |
574 | readcmd = NAND_CMD_READOOB; |
575 | } else if (column < 256) { | |
576 | /* First 256 bytes --> READ0 */ | |
577 | readcmd = NAND_CMD_READ0; | |
578 | } else { | |
579 | column -= 256; | |
580 | readcmd = NAND_CMD_READ1; | |
581 | } | |
ace4dfee | 582 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 583 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 584 | } |
ace4dfee | 585 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 586 | |
8b6e50c9 | 587 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
588 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
589 | /* Serially input address */ | |
590 | if (column != -1) { | |
591 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 592 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 593 | column >>= 1; |
ace4dfee | 594 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
595 | ctrl &= ~NAND_CTRL_CHANGE; |
596 | } | |
597 | if (page_addr != -1) { | |
ace4dfee | 598 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 599 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 600 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 601 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
602 | if (chip->chipsize > (32 << 20)) |
603 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 604 | } |
ace4dfee | 605 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
606 | |
607 | /* | |
8b6e50c9 BN |
608 | * Program and erase have their own busy handlers status and sequential |
609 | * in needs no delay | |
e0c7d767 | 610 | */ |
1da177e4 | 611 | switch (command) { |
61b03bd7 | 612 | |
1da177e4 LT |
613 | case NAND_CMD_PAGEPROG: |
614 | case NAND_CMD_ERASE1: | |
615 | case NAND_CMD_ERASE2: | |
616 | case NAND_CMD_SEQIN: | |
617 | case NAND_CMD_STATUS: | |
618 | return; | |
619 | ||
620 | case NAND_CMD_RESET: | |
ace4dfee | 621 | if (chip->dev_ready) |
1da177e4 | 622 | break; |
ace4dfee TG |
623 | udelay(chip->chip_delay); |
624 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 625 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
626 | chip->cmd_ctrl(mtd, |
627 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
628 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
629 | ; | |
1da177e4 LT |
630 | return; |
631 | ||
e0c7d767 | 632 | /* This applies to read commands */ |
1da177e4 | 633 | default: |
61b03bd7 | 634 | /* |
1da177e4 LT |
635 | * If we don't have access to the busy pin, we apply the given |
636 | * command delay | |
e0c7d767 | 637 | */ |
ace4dfee TG |
638 | if (!chip->dev_ready) { |
639 | udelay(chip->chip_delay); | |
1da177e4 | 640 | return; |
61b03bd7 | 641 | } |
1da177e4 | 642 | } |
8b6e50c9 BN |
643 | /* |
644 | * Apply this short delay always to ensure that we do wait tWB in | |
645 | * any case on any machine. | |
646 | */ | |
e0c7d767 | 647 | ndelay(100); |
3b88775c TG |
648 | |
649 | nand_wait_ready(mtd); | |
1da177e4 LT |
650 | } |
651 | ||
652 | /** | |
653 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
654 | * @mtd: MTD device structure |
655 | * @command: the command to be sent | |
656 | * @column: the column address for this command, -1 if none | |
657 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 658 | * |
7abd3ef9 | 659 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
660 | * devices. We don't have the separate regions as we have in the small page |
661 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 662 | */ |
7abd3ef9 TG |
663 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
664 | int column, int page_addr) | |
1da177e4 | 665 | { |
ace4dfee | 666 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
667 | |
668 | /* Emulate NAND_CMD_READOOB */ | |
669 | if (command == NAND_CMD_READOOB) { | |
28318776 | 670 | column += mtd->writesize; |
1da177e4 LT |
671 | command = NAND_CMD_READ0; |
672 | } | |
61b03bd7 | 673 | |
7abd3ef9 | 674 | /* Command latch cycle */ |
fb066ada | 675 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
676 | |
677 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 678 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
679 | |
680 | /* Serially input address */ | |
681 | if (column != -1) { | |
682 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 683 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 684 | column >>= 1; |
ace4dfee | 685 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 686 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 687 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 688 | } |
1da177e4 | 689 | if (page_addr != -1) { |
ace4dfee TG |
690 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
691 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 692 | NAND_NCE | NAND_ALE); |
1da177e4 | 693 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
694 | if (chip->chipsize > (128 << 20)) |
695 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 696 | NAND_NCE | NAND_ALE); |
1da177e4 | 697 | } |
1da177e4 | 698 | } |
ace4dfee | 699 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
700 | |
701 | /* | |
8b6e50c9 BN |
702 | * Program and erase have their own busy handlers status, sequential |
703 | * in, and deplete1 need no delay. | |
30f464b7 | 704 | */ |
1da177e4 | 705 | switch (command) { |
61b03bd7 | 706 | |
1da177e4 LT |
707 | case NAND_CMD_CACHEDPROG: |
708 | case NAND_CMD_PAGEPROG: | |
709 | case NAND_CMD_ERASE1: | |
710 | case NAND_CMD_ERASE2: | |
711 | case NAND_CMD_SEQIN: | |
7bc3312b | 712 | case NAND_CMD_RNDIN: |
1da177e4 | 713 | case NAND_CMD_STATUS: |
30f464b7 | 714 | return; |
1da177e4 LT |
715 | |
716 | case NAND_CMD_RESET: | |
ace4dfee | 717 | if (chip->dev_ready) |
1da177e4 | 718 | break; |
ace4dfee | 719 | udelay(chip->chip_delay); |
12efdde3 TG |
720 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
721 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
722 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
723 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
724 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
725 | ; | |
1da177e4 LT |
726 | return; |
727 | ||
7bc3312b TG |
728 | case NAND_CMD_RNDOUT: |
729 | /* No ready / busy check necessary */ | |
730 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
731 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
732 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
733 | NAND_NCE | NAND_CTRL_CHANGE); | |
734 | return; | |
735 | ||
1da177e4 | 736 | case NAND_CMD_READ0: |
12efdde3 TG |
737 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
738 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
739 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
740 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 741 | |
e0c7d767 | 742 | /* This applies to read commands */ |
1da177e4 | 743 | default: |
61b03bd7 | 744 | /* |
1da177e4 | 745 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 746 | * command delay. |
e0c7d767 | 747 | */ |
ace4dfee TG |
748 | if (!chip->dev_ready) { |
749 | udelay(chip->chip_delay); | |
1da177e4 | 750 | return; |
61b03bd7 | 751 | } |
1da177e4 | 752 | } |
3b88775c | 753 | |
8b6e50c9 BN |
754 | /* |
755 | * Apply this short delay always to ensure that we do wait tWB in | |
756 | * any case on any machine. | |
757 | */ | |
e0c7d767 | 758 | ndelay(100); |
3b88775c TG |
759 | |
760 | nand_wait_ready(mtd); | |
1da177e4 LT |
761 | } |
762 | ||
2af7c653 SK |
763 | /** |
764 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
765 | * @chip: the nand chip descriptor |
766 | * @mtd: MTD device structure | |
767 | * @new_state: the state which is requested | |
2af7c653 SK |
768 | * |
769 | * Used when in panic, no locks are taken. | |
770 | */ | |
771 | static void panic_nand_get_device(struct nand_chip *chip, | |
772 | struct mtd_info *mtd, int new_state) | |
773 | { | |
7854d3f7 | 774 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
775 | chip->controller->active = chip; |
776 | chip->state = new_state; | |
777 | } | |
778 | ||
1da177e4 LT |
779 | /** |
780 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
781 | * @mtd: MTD device structure |
782 | * @new_state: the state which is requested | |
1da177e4 LT |
783 | * |
784 | * Get the device and lock it for exclusive access | |
785 | */ | |
2c0a2bed | 786 | static int |
6a8214aa | 787 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 788 | { |
6a8214aa | 789 | struct nand_chip *chip = mtd->priv; |
ace4dfee TG |
790 | spinlock_t *lock = &chip->controller->lock; |
791 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 792 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 793 | retry: |
0dfc6246 TG |
794 | spin_lock(lock); |
795 | ||
b8b3ee9a | 796 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
797 | if (!chip->controller->active) |
798 | chip->controller->active = chip; | |
a36ed299 | 799 | |
ace4dfee TG |
800 | if (chip->controller->active == chip && chip->state == FL_READY) { |
801 | chip->state = new_state; | |
0dfc6246 | 802 | spin_unlock(lock); |
962034f4 VW |
803 | return 0; |
804 | } | |
805 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
806 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
807 | chip->state = FL_PM_SUSPENDED; | |
808 | spin_unlock(lock); | |
809 | return 0; | |
6b0d9a84 | 810 | } |
0dfc6246 TG |
811 | } |
812 | set_current_state(TASK_UNINTERRUPTIBLE); | |
813 | add_wait_queue(wq, &wait); | |
814 | spin_unlock(lock); | |
815 | schedule(); | |
816 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
817 | goto retry; |
818 | } | |
819 | ||
2af7c653 | 820 | /** |
8b6e50c9 BN |
821 | * panic_nand_wait - [GENERIC] wait until the command is done |
822 | * @mtd: MTD device structure | |
823 | * @chip: NAND chip structure | |
824 | * @timeo: timeout | |
2af7c653 SK |
825 | * |
826 | * Wait for command done. This is a helper function for nand_wait used when | |
827 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 828 | * an oops through mtdoops. |
2af7c653 SK |
829 | */ |
830 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
831 | unsigned long timeo) | |
832 | { | |
833 | int i; | |
834 | for (i = 0; i < timeo; i++) { | |
835 | if (chip->dev_ready) { | |
836 | if (chip->dev_ready(mtd)) | |
837 | break; | |
838 | } else { | |
839 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
840 | break; | |
841 | } | |
842 | mdelay(1); | |
f8ac0414 | 843 | } |
2af7c653 SK |
844 | } |
845 | ||
1da177e4 | 846 | /** |
8b6e50c9 BN |
847 | * nand_wait - [DEFAULT] wait until the command is done |
848 | * @mtd: MTD device structure | |
849 | * @chip: NAND chip structure | |
1da177e4 | 850 | * |
8b6e50c9 BN |
851 | * Wait for command done. This applies to erase and program only. Erase can |
852 | * take up to 400ms and program up to 20ms according to general NAND and | |
853 | * SmartMedia specs. | |
844d3b42 | 854 | */ |
7bc3312b | 855 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
856 | { |
857 | ||
7bc3312b | 858 | int status, state = chip->state; |
6d2559f8 | 859 | unsigned long timeo = (state == FL_ERASING ? 400 : 20); |
1da177e4 | 860 | |
8fe833c1 RP |
861 | led_trigger_event(nand_led_trigger, LED_FULL); |
862 | ||
8b6e50c9 BN |
863 | /* |
864 | * Apply this short delay always to ensure that we do wait tWB in any | |
865 | * case on any machine. | |
866 | */ | |
e0c7d767 | 867 | ndelay(100); |
1da177e4 | 868 | |
14c65786 | 869 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 870 | |
2af7c653 SK |
871 | if (in_interrupt() || oops_in_progress) |
872 | panic_nand_wait(mtd, chip, timeo); | |
873 | else { | |
6d2559f8 | 874 | timeo = jiffies + msecs_to_jiffies(timeo); |
2af7c653 SK |
875 | while (time_before(jiffies, timeo)) { |
876 | if (chip->dev_ready) { | |
877 | if (chip->dev_ready(mtd)) | |
878 | break; | |
879 | } else { | |
880 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
881 | break; | |
882 | } | |
883 | cond_resched(); | |
1da177e4 | 884 | } |
1da177e4 | 885 | } |
8fe833c1 RP |
886 | led_trigger_event(nand_led_trigger, LED_OFF); |
887 | ||
ace4dfee | 888 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
889 | /* This can happen if in case of timeout or buggy dev_ready */ |
890 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
891 | return status; |
892 | } | |
893 | ||
7d70f334 | 894 | /** |
b6d676db | 895 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
896 | * @mtd: mtd info |
897 | * @ofs: offset to start unlock from | |
898 | * @len: length to unlock | |
8b6e50c9 BN |
899 | * @invert: when = 0, unlock the range of blocks within the lower and |
900 | * upper boundary address | |
901 | * when = 1, unlock the range of blocks outside the boundaries | |
902 | * of the lower and upper boundary address | |
7d70f334 | 903 | * |
8b6e50c9 | 904 | * Returs unlock status. |
7d70f334 VS |
905 | */ |
906 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
907 | uint64_t len, int invert) | |
908 | { | |
909 | int ret = 0; | |
910 | int status, page; | |
911 | struct nand_chip *chip = mtd->priv; | |
912 | ||
913 | /* Submit address of first page to unlock */ | |
914 | page = ofs >> chip->page_shift; | |
915 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
916 | ||
917 | /* Submit address of last page to unlock */ | |
918 | page = (ofs + len) >> chip->page_shift; | |
919 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
920 | (page | invert) & chip->pagemask); | |
921 | ||
922 | /* Call wait ready function */ | |
923 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 924 | /* See if device thinks it succeeded */ |
74830966 | 925 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 926 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
927 | __func__, status); |
928 | ret = -EIO; | |
929 | } | |
930 | ||
931 | return ret; | |
932 | } | |
933 | ||
934 | /** | |
b6d676db | 935 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
936 | * @mtd: mtd info |
937 | * @ofs: offset to start unlock from | |
938 | * @len: length to unlock | |
7d70f334 | 939 | * |
8b6e50c9 | 940 | * Returns unlock status. |
7d70f334 VS |
941 | */ |
942 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
943 | { | |
944 | int ret = 0; | |
945 | int chipnr; | |
946 | struct nand_chip *chip = mtd->priv; | |
947 | ||
289c0522 | 948 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
949 | __func__, (unsigned long long)ofs, len); |
950 | ||
951 | if (check_offs_len(mtd, ofs, len)) | |
952 | ret = -EINVAL; | |
953 | ||
954 | /* Align to last block address if size addresses end of the device */ | |
955 | if (ofs + len == mtd->size) | |
956 | len -= mtd->erasesize; | |
957 | ||
6a8214aa | 958 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
959 | |
960 | /* Shift to get chip number */ | |
961 | chipnr = ofs >> chip->chip_shift; | |
962 | ||
963 | chip->select_chip(mtd, chipnr); | |
964 | ||
965 | /* Check, if it is write protected */ | |
966 | if (nand_check_wp(mtd)) { | |
289c0522 | 967 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
968 | __func__); |
969 | ret = -EIO; | |
970 | goto out; | |
971 | } | |
972 | ||
973 | ret = __nand_unlock(mtd, ofs, len, 0); | |
974 | ||
975 | out: | |
b0bb6903 | 976 | chip->select_chip(mtd, -1); |
7d70f334 VS |
977 | nand_release_device(mtd); |
978 | ||
979 | return ret; | |
980 | } | |
7351d3a5 | 981 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
982 | |
983 | /** | |
b6d676db | 984 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
985 | * @mtd: mtd info |
986 | * @ofs: offset to start unlock from | |
987 | * @len: length to unlock | |
7d70f334 | 988 | * |
8b6e50c9 BN |
989 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
990 | * have this feature, but it allows only to lock all blocks, not for specified | |
991 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
992 | * now. | |
7d70f334 | 993 | * |
8b6e50c9 | 994 | * Returns lock status. |
7d70f334 VS |
995 | */ |
996 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
997 | { | |
998 | int ret = 0; | |
999 | int chipnr, status, page; | |
1000 | struct nand_chip *chip = mtd->priv; | |
1001 | ||
289c0522 | 1002 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1003 | __func__, (unsigned long long)ofs, len); |
1004 | ||
1005 | if (check_offs_len(mtd, ofs, len)) | |
1006 | ret = -EINVAL; | |
1007 | ||
6a8214aa | 1008 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
1009 | |
1010 | /* Shift to get chip number */ | |
1011 | chipnr = ofs >> chip->chip_shift; | |
1012 | ||
1013 | chip->select_chip(mtd, chipnr); | |
1014 | ||
1015 | /* Check, if it is write protected */ | |
1016 | if (nand_check_wp(mtd)) { | |
289c0522 | 1017 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1018 | __func__); |
1019 | status = MTD_ERASE_FAILED; | |
1020 | ret = -EIO; | |
1021 | goto out; | |
1022 | } | |
1023 | ||
1024 | /* Submit address of first page to lock */ | |
1025 | page = ofs >> chip->page_shift; | |
1026 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1027 | ||
1028 | /* Call wait ready function */ | |
1029 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1030 | /* See if device thinks it succeeded */ |
74830966 | 1031 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1032 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1033 | __func__, status); |
1034 | ret = -EIO; | |
1035 | goto out; | |
1036 | } | |
1037 | ||
1038 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1039 | ||
1040 | out: | |
b0bb6903 | 1041 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1042 | nand_release_device(mtd); |
1043 | ||
1044 | return ret; | |
1045 | } | |
7351d3a5 | 1046 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1047 | |
8593fbc6 | 1048 | /** |
7854d3f7 | 1049 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1050 | * @mtd: mtd info structure |
1051 | * @chip: nand chip info structure | |
1052 | * @buf: buffer to store read data | |
1fbb938d | 1053 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1054 | * @page: page number to read |
52ff49df | 1055 | * |
7854d3f7 | 1056 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1057 | */ |
1058 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1059 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1060 | { |
1061 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1062 | if (oob_required) |
1063 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1064 | return 0; |
1065 | } | |
1066 | ||
52ff49df | 1067 | /** |
7854d3f7 | 1068 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1069 | * @mtd: mtd info structure |
1070 | * @chip: nand chip info structure | |
1071 | * @buf: buffer to store read data | |
1fbb938d | 1072 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1073 | * @page: page number to read |
52ff49df DB |
1074 | * |
1075 | * We need a special oob layout and handling even when OOB isn't used. | |
1076 | */ | |
7351d3a5 | 1077 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1078 | struct nand_chip *chip, uint8_t *buf, |
1079 | int oob_required, int page) | |
52ff49df DB |
1080 | { |
1081 | int eccsize = chip->ecc.size; | |
1082 | int eccbytes = chip->ecc.bytes; | |
1083 | uint8_t *oob = chip->oob_poi; | |
1084 | int steps, size; | |
1085 | ||
1086 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1087 | chip->read_buf(mtd, buf, eccsize); | |
1088 | buf += eccsize; | |
1089 | ||
1090 | if (chip->ecc.prepad) { | |
1091 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1092 | oob += chip->ecc.prepad; | |
1093 | } | |
1094 | ||
1095 | chip->read_buf(mtd, oob, eccbytes); | |
1096 | oob += eccbytes; | |
1097 | ||
1098 | if (chip->ecc.postpad) { | |
1099 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1100 | oob += chip->ecc.postpad; | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1105 | if (size) | |
1106 | chip->read_buf(mtd, oob, size); | |
1107 | ||
1108 | return 0; | |
1109 | } | |
1110 | ||
1da177e4 | 1111 | /** |
7854d3f7 | 1112 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1113 | * @mtd: mtd info structure |
1114 | * @chip: nand chip info structure | |
1115 | * @buf: buffer to store read data | |
1fbb938d | 1116 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1117 | * @page: page number to read |
068e3c0a | 1118 | */ |
f5bbdacc | 1119 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1120 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1121 | { |
f5bbdacc TG |
1122 | int i, eccsize = chip->ecc.size; |
1123 | int eccbytes = chip->ecc.bytes; | |
1124 | int eccsteps = chip->ecc.steps; | |
1125 | uint8_t *p = buf; | |
4bf63fcb DW |
1126 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1127 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1128 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1129 | unsigned int max_bitflips = 0; |
f5bbdacc | 1130 | |
1fbb938d | 1131 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1132 | |
1133 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1134 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1135 | ||
1136 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1137 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1138 | |
1139 | eccsteps = chip->ecc.steps; | |
1140 | p = buf; | |
1141 | ||
1142 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1143 | int stat; | |
1144 | ||
1145 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1146 | if (stat < 0) { |
f5bbdacc | 1147 | mtd->ecc_stats.failed++; |
3f91e94f | 1148 | } else { |
f5bbdacc | 1149 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1150 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1151 | } | |
f5bbdacc | 1152 | } |
3f91e94f | 1153 | return max_bitflips; |
22c60f5f | 1154 | } |
1da177e4 | 1155 | |
3d459559 | 1156 | /** |
837a6ba4 | 1157 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1158 | * @mtd: mtd info structure |
1159 | * @chip: nand chip info structure | |
1160 | * @data_offs: offset of requested data within the page | |
1161 | * @readlen: data length | |
1162 | * @bufpoi: buffer to store read data | |
3d459559 | 1163 | */ |
7351d3a5 FF |
1164 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
1165 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) | |
3d459559 AK |
1166 | { |
1167 | int start_step, end_step, num_steps; | |
1168 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1169 | uint8_t *p; | |
1170 | int data_col_addr, i, gaps = 0; | |
1171 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1172 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
7351d3a5 | 1173 | int index = 0; |
3f91e94f | 1174 | unsigned int max_bitflips = 0; |
3d459559 | 1175 | |
7854d3f7 | 1176 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1177 | start_step = data_offs / chip->ecc.size; |
1178 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1179 | num_steps = end_step - start_step + 1; | |
1180 | ||
8b6e50c9 | 1181 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1182 | datafrag_len = num_steps * chip->ecc.size; |
1183 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1184 | ||
1185 | data_col_addr = start_step * chip->ecc.size; | |
1186 | /* If we read not a page aligned data */ | |
1187 | if (data_col_addr != 0) | |
1188 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1189 | ||
1190 | p = bufpoi + data_col_addr; | |
1191 | chip->read_buf(mtd, p, datafrag_len); | |
1192 | ||
8b6e50c9 | 1193 | /* Calculate ECC */ |
3d459559 AK |
1194 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1195 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1196 | ||
8b6e50c9 BN |
1197 | /* |
1198 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1199 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1200 | */ |
3d459559 AK |
1201 | for (i = 0; i < eccfrag_len - 1; i++) { |
1202 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1203 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1204 | gaps = 1; | |
1205 | break; | |
1206 | } | |
1207 | } | |
1208 | if (gaps) { | |
1209 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1210 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1211 | } else { | |
8b6e50c9 | 1212 | /* |
7854d3f7 | 1213 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1214 | * about buswidth alignment in read_buf. |
1215 | */ | |
7351d3a5 FF |
1216 | index = start_step * chip->ecc.bytes; |
1217 | ||
1218 | aligned_pos = eccpos[index] & ~(busw - 1); | |
3d459559 | 1219 | aligned_len = eccfrag_len; |
7351d3a5 | 1220 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1221 | aligned_len++; |
7351d3a5 | 1222 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1223 | aligned_len++; |
1224 | ||
7351d3a5 FF |
1225 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1226 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1227 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1228 | } | |
1229 | ||
1230 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1231 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1232 | |
1233 | p = bufpoi + data_col_addr; | |
1234 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1235 | int stat; | |
1236 | ||
7351d3a5 FF |
1237 | stat = chip->ecc.correct(mtd, p, |
1238 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
3f91e94f | 1239 | if (stat < 0) { |
3d459559 | 1240 | mtd->ecc_stats.failed++; |
3f91e94f | 1241 | } else { |
3d459559 | 1242 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1243 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1244 | } | |
3d459559 | 1245 | } |
3f91e94f | 1246 | return max_bitflips; |
3d459559 AK |
1247 | } |
1248 | ||
068e3c0a | 1249 | /** |
7854d3f7 | 1250 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1251 | * @mtd: mtd info structure |
1252 | * @chip: nand chip info structure | |
1253 | * @buf: buffer to store read data | |
1fbb938d | 1254 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1255 | * @page: page number to read |
068e3c0a | 1256 | * |
7854d3f7 | 1257 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1258 | */ |
f5bbdacc | 1259 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1260 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1261 | { |
f5bbdacc TG |
1262 | int i, eccsize = chip->ecc.size; |
1263 | int eccbytes = chip->ecc.bytes; | |
1264 | int eccsteps = chip->ecc.steps; | |
1265 | uint8_t *p = buf; | |
4bf63fcb DW |
1266 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1267 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1268 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1269 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1270 | |
1271 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1272 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1273 | chip->read_buf(mtd, p, eccsize); | |
1274 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1275 | } |
f75e5097 | 1276 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1277 | |
f5bbdacc | 1278 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1279 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1280 | |
f5bbdacc TG |
1281 | eccsteps = chip->ecc.steps; |
1282 | p = buf; | |
61b03bd7 | 1283 | |
f5bbdacc TG |
1284 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1285 | int stat; | |
1da177e4 | 1286 | |
f5bbdacc | 1287 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
3f91e94f | 1288 | if (stat < 0) { |
f5bbdacc | 1289 | mtd->ecc_stats.failed++; |
3f91e94f | 1290 | } else { |
f5bbdacc | 1291 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1292 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1293 | } | |
f5bbdacc | 1294 | } |
3f91e94f | 1295 | return max_bitflips; |
f5bbdacc | 1296 | } |
1da177e4 | 1297 | |
6e0cb135 | 1298 | /** |
7854d3f7 | 1299 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1300 | * @mtd: mtd info structure |
1301 | * @chip: nand chip info structure | |
1302 | * @buf: buffer to store read data | |
1fbb938d | 1303 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1304 | * @page: page number to read |
6e0cb135 | 1305 | * |
8b6e50c9 BN |
1306 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1307 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1308 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1309 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1310 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1311 | */ |
1312 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1313 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1314 | { |
1315 | int i, eccsize = chip->ecc.size; | |
1316 | int eccbytes = chip->ecc.bytes; | |
1317 | int eccsteps = chip->ecc.steps; | |
1318 | uint8_t *p = buf; | |
1319 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1320 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1321 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1322 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1323 | |
1324 | /* Read the OOB area first */ | |
1325 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1326 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1327 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1328 | ||
1329 | for (i = 0; i < chip->ecc.total; i++) | |
1330 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1331 | ||
1332 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1333 | int stat; | |
1334 | ||
1335 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1336 | chip->read_buf(mtd, p, eccsize); | |
1337 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1338 | ||
1339 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
3f91e94f | 1340 | if (stat < 0) { |
6e0cb135 | 1341 | mtd->ecc_stats.failed++; |
3f91e94f | 1342 | } else { |
6e0cb135 | 1343 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1344 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1345 | } | |
6e0cb135 | 1346 | } |
3f91e94f | 1347 | return max_bitflips; |
6e0cb135 SN |
1348 | } |
1349 | ||
f5bbdacc | 1350 | /** |
7854d3f7 | 1351 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1352 | * @mtd: mtd info structure |
1353 | * @chip: nand chip info structure | |
1354 | * @buf: buffer to store read data | |
1fbb938d | 1355 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1356 | * @page: page number to read |
f5bbdacc | 1357 | * |
8b6e50c9 BN |
1358 | * The hw generator calculates the error syndrome automatically. Therefore we |
1359 | * need a special oob layout and handling. | |
f5bbdacc TG |
1360 | */ |
1361 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1362 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1363 | { |
1364 | int i, eccsize = chip->ecc.size; | |
1365 | int eccbytes = chip->ecc.bytes; | |
1366 | int eccsteps = chip->ecc.steps; | |
1367 | uint8_t *p = buf; | |
f75e5097 | 1368 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1369 | unsigned int max_bitflips = 0; |
1da177e4 | 1370 | |
f5bbdacc TG |
1371 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1372 | int stat; | |
61b03bd7 | 1373 | |
f5bbdacc TG |
1374 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1375 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1376 | |
f5bbdacc TG |
1377 | if (chip->ecc.prepad) { |
1378 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1379 | oob += chip->ecc.prepad; | |
1380 | } | |
1da177e4 | 1381 | |
f5bbdacc TG |
1382 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1383 | chip->read_buf(mtd, oob, eccbytes); | |
1384 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1385 | |
3f91e94f | 1386 | if (stat < 0) { |
f5bbdacc | 1387 | mtd->ecc_stats.failed++; |
3f91e94f | 1388 | } else { |
f5bbdacc | 1389 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1390 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1391 | } | |
61b03bd7 | 1392 | |
f5bbdacc | 1393 | oob += eccbytes; |
1da177e4 | 1394 | |
f5bbdacc TG |
1395 | if (chip->ecc.postpad) { |
1396 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1397 | oob += chip->ecc.postpad; | |
61b03bd7 | 1398 | } |
f5bbdacc | 1399 | } |
1da177e4 | 1400 | |
f5bbdacc | 1401 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1402 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1403 | if (i) |
1404 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1405 | |
3f91e94f | 1406 | return max_bitflips; |
f5bbdacc | 1407 | } |
1da177e4 | 1408 | |
f5bbdacc | 1409 | /** |
7854d3f7 | 1410 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1411 | * @chip: nand chip structure |
1412 | * @oob: oob destination address | |
1413 | * @ops: oob ops structure | |
1414 | * @len: size of oob to transfer | |
8593fbc6 TG |
1415 | */ |
1416 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1417 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1418 | { |
f8ac0414 | 1419 | switch (ops->mode) { |
8593fbc6 | 1420 | |
0612b9dd BN |
1421 | case MTD_OPS_PLACE_OOB: |
1422 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1423 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1424 | return oob + len; | |
1425 | ||
0612b9dd | 1426 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1427 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1428 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1429 | size_t bytes = 0; | |
8593fbc6 | 1430 | |
f8ac0414 | 1431 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1432 | /* Read request not from offset 0? */ |
7bc3312b TG |
1433 | if (unlikely(roffs)) { |
1434 | if (roffs >= free->length) { | |
1435 | roffs -= free->length; | |
1436 | continue; | |
1437 | } | |
1438 | boffs = free->offset + roffs; | |
1439 | bytes = min_t(size_t, len, | |
1440 | (free->length - roffs)); | |
1441 | roffs = 0; | |
1442 | } else { | |
1443 | bytes = min_t(size_t, len, free->length); | |
1444 | boffs = free->offset; | |
1445 | } | |
1446 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1447 | oob += bytes; |
1448 | } | |
1449 | return oob; | |
1450 | } | |
1451 | default: | |
1452 | BUG(); | |
1453 | } | |
1454 | return NULL; | |
1455 | } | |
1456 | ||
ba84fb59 BN |
1457 | /** |
1458 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1459 | * @mtd: MTD device structure | |
1460 | * @retry_mode: the retry mode to use | |
1461 | * | |
1462 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
1463 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
1464 | * a new threshold, the host should retry reading the page. | |
1465 | */ | |
1466 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
1467 | { | |
1468 | struct nand_chip *chip = mtd->priv; | |
1469 | ||
1470 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
1471 | ||
1472 | if (retry_mode >= chip->read_retries) | |
1473 | return -EINVAL; | |
1474 | ||
1475 | if (!chip->setup_read_retry) | |
1476 | return -EOPNOTSUPP; | |
1477 | ||
1478 | return chip->setup_read_retry(mtd, retry_mode); | |
1479 | } | |
1480 | ||
8593fbc6 | 1481 | /** |
7854d3f7 | 1482 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1483 | * @mtd: MTD device structure |
1484 | * @from: offset to read from | |
1485 | * @ops: oob ops structure | |
f5bbdacc TG |
1486 | * |
1487 | * Internal function. Called with chip held. | |
1488 | */ | |
8593fbc6 TG |
1489 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1490 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1491 | { |
e47f3db4 | 1492 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
f5bbdacc | 1493 | struct nand_chip *chip = mtd->priv; |
f5bbdacc | 1494 | int ret = 0; |
8593fbc6 | 1495 | uint32_t readlen = ops->len; |
7014568b | 1496 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1497 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1498 | mtd->oobavail : mtd->oobsize; |
1499 | ||
8593fbc6 | 1500 | uint8_t *bufpoi, *oob, *buf; |
edbc4540 | 1501 | unsigned int max_bitflips = 0; |
ba84fb59 | 1502 | int retry_mode = 0; |
b72f3dfb | 1503 | bool ecc_fail = false; |
1da177e4 | 1504 | |
f5bbdacc TG |
1505 | chipnr = (int)(from >> chip->chip_shift); |
1506 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1507 | |
f5bbdacc TG |
1508 | realpage = (int)(from >> chip->page_shift); |
1509 | page = realpage & chip->pagemask; | |
1da177e4 | 1510 | |
f5bbdacc | 1511 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1512 | |
8593fbc6 TG |
1513 | buf = ops->datbuf; |
1514 | oob = ops->oobbuf; | |
e47f3db4 | 1515 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1516 | |
f8ac0414 | 1517 | while (1) { |
b72f3dfb BN |
1518 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
1519 | ||
f5bbdacc TG |
1520 | bytes = min(mtd->writesize - col, readlen); |
1521 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1522 | |
8b6e50c9 | 1523 | /* Is the current page in the buffer? */ |
8593fbc6 | 1524 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1525 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1526 | |
ba84fb59 | 1527 | read_retry: |
c00a0991 | 1528 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1529 | |
edbc4540 MD |
1530 | /* |
1531 | * Now read the page into the buffer. Absent an error, | |
1532 | * the read methods return max bitflips per ecc step. | |
1533 | */ | |
0612b9dd | 1534 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1535 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1536 | oob_required, |
1537 | page); | |
a5ff4f10 JW |
1538 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1539 | !oob) | |
7351d3a5 FF |
1540 | ret = chip->ecc.read_subpage(mtd, chip, |
1541 | col, bytes, bufpoi); | |
956e944c | 1542 | else |
46a8cf2d | 1543 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1544 | oob_required, page); |
6d77b9d0 BN |
1545 | if (ret < 0) { |
1546 | if (!aligned) | |
1547 | /* Invalidate page cache */ | |
1548 | chip->pagebuf = -1; | |
1da177e4 | 1549 | break; |
6d77b9d0 | 1550 | } |
f5bbdacc | 1551 | |
edbc4540 MD |
1552 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1553 | ||
f5bbdacc TG |
1554 | /* Transfer not aligned data */ |
1555 | if (!aligned) { | |
a5ff4f10 | 1556 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 1557 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 1558 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1559 | chip->pagebuf = realpage; |
edbc4540 MD |
1560 | chip->pagebuf_bitflips = ret; |
1561 | } else { | |
6d77b9d0 BN |
1562 | /* Invalidate page cache */ |
1563 | chip->pagebuf = -1; | |
edbc4540 | 1564 | } |
4bf63fcb | 1565 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1566 | } |
1567 | ||
8593fbc6 | 1568 | if (unlikely(oob)) { |
b64d39d8 ML |
1569 | int toread = min(oobreadlen, max_oobsize); |
1570 | ||
1571 | if (toread) { | |
1572 | oob = nand_transfer_oob(chip, | |
1573 | oob, ops, toread); | |
1574 | oobreadlen -= toread; | |
1575 | } | |
8593fbc6 | 1576 | } |
5bc7c33c BN |
1577 | |
1578 | if (chip->options & NAND_NEED_READRDY) { | |
1579 | /* Apply delay or wait for ready/busy pin */ | |
1580 | if (!chip->dev_ready) | |
1581 | udelay(chip->chip_delay); | |
1582 | else | |
1583 | nand_wait_ready(mtd); | |
1584 | } | |
b72f3dfb | 1585 | |
ba84fb59 BN |
1586 | if (mtd->ecc_stats.failed - ecc_failures) { |
1587 | if (retry_mode + 1 <= chip->read_retries) { | |
1588 | retry_mode++; | |
1589 | ret = nand_setup_read_retry(mtd, | |
1590 | retry_mode); | |
1591 | if (ret < 0) | |
1592 | break; | |
1593 | ||
1594 | /* Reset failures; retry */ | |
1595 | mtd->ecc_stats.failed = ecc_failures; | |
1596 | goto read_retry; | |
1597 | } else { | |
1598 | /* No more retry modes; real failure */ | |
1599 | ecc_fail = true; | |
1600 | } | |
1601 | } | |
1602 | ||
1603 | buf += bytes; | |
8593fbc6 | 1604 | } else { |
4bf63fcb | 1605 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1606 | buf += bytes; |
edbc4540 MD |
1607 | max_bitflips = max_t(unsigned int, max_bitflips, |
1608 | chip->pagebuf_bitflips); | |
8593fbc6 | 1609 | } |
1da177e4 | 1610 | |
f5bbdacc | 1611 | readlen -= bytes; |
61b03bd7 | 1612 | |
ba84fb59 BN |
1613 | /* Reset to retry mode 0 */ |
1614 | if (retry_mode) { | |
1615 | ret = nand_setup_read_retry(mtd, 0); | |
1616 | if (ret < 0) | |
1617 | break; | |
1618 | retry_mode = 0; | |
1619 | } | |
1620 | ||
f5bbdacc | 1621 | if (!readlen) |
61b03bd7 | 1622 | break; |
1da177e4 | 1623 | |
8b6e50c9 | 1624 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1625 | col = 0; |
1626 | /* Increment page address */ | |
1627 | realpage++; | |
1628 | ||
ace4dfee | 1629 | page = realpage & chip->pagemask; |
1da177e4 LT |
1630 | /* Check, if we cross a chip boundary */ |
1631 | if (!page) { | |
1632 | chipnr++; | |
ace4dfee TG |
1633 | chip->select_chip(mtd, -1); |
1634 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1635 | } |
1da177e4 | 1636 | } |
b0bb6903 | 1637 | chip->select_chip(mtd, -1); |
1da177e4 | 1638 | |
8593fbc6 | 1639 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1640 | if (oob) |
1641 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1642 | |
3f91e94f | 1643 | if (ret < 0) |
f5bbdacc TG |
1644 | return ret; |
1645 | ||
b72f3dfb | 1646 | if (ecc_fail) |
9a1fcdfd TG |
1647 | return -EBADMSG; |
1648 | ||
edbc4540 | 1649 | return max_bitflips; |
f5bbdacc TG |
1650 | } |
1651 | ||
1652 | /** | |
25985edc | 1653 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1654 | * @mtd: MTD device structure |
1655 | * @from: offset to read from | |
1656 | * @len: number of bytes to read | |
1657 | * @retlen: pointer to variable to store the number of read bytes | |
1658 | * @buf: the databuffer to put data | |
f5bbdacc | 1659 | * |
8b6e50c9 | 1660 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1661 | */ |
1662 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1663 | size_t *retlen, uint8_t *buf) | |
1664 | { | |
4a89ff88 | 1665 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1666 | int ret; |
1667 | ||
6a8214aa | 1668 | nand_get_device(mtd, FL_READING); |
4a89ff88 BN |
1669 | ops.len = len; |
1670 | ops.datbuf = buf; | |
1671 | ops.oobbuf = NULL; | |
11041ae6 | 1672 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1673 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1674 | *retlen = ops.retlen; |
f5bbdacc | 1675 | nand_release_device(mtd); |
f5bbdacc | 1676 | return ret; |
1da177e4 LT |
1677 | } |
1678 | ||
7bc3312b | 1679 | /** |
7854d3f7 | 1680 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1681 | * @mtd: mtd info structure |
1682 | * @chip: nand chip info structure | |
1683 | * @page: page number to read | |
7bc3312b TG |
1684 | */ |
1685 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1686 | int page) |
7bc3312b | 1687 | { |
5c2ffb11 | 1688 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1689 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1690 | return 0; |
7bc3312b TG |
1691 | } |
1692 | ||
1693 | /** | |
7854d3f7 | 1694 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1695 | * with syndromes |
8b6e50c9 BN |
1696 | * @mtd: mtd info structure |
1697 | * @chip: nand chip info structure | |
1698 | * @page: page number to read | |
7bc3312b TG |
1699 | */ |
1700 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1701 | int page) |
7bc3312b TG |
1702 | { |
1703 | uint8_t *buf = chip->oob_poi; | |
1704 | int length = mtd->oobsize; | |
1705 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1706 | int eccsize = chip->ecc.size; | |
1707 | uint8_t *bufpoi = buf; | |
1708 | int i, toread, sndrnd = 0, pos; | |
1709 | ||
1710 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1711 | for (i = 0; i < chip->ecc.steps; i++) { | |
1712 | if (sndrnd) { | |
1713 | pos = eccsize + i * (eccsize + chunk); | |
1714 | if (mtd->writesize > 512) | |
1715 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1716 | else | |
1717 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1718 | } else | |
1719 | sndrnd = 1; | |
1720 | toread = min_t(int, length, chunk); | |
1721 | chip->read_buf(mtd, bufpoi, toread); | |
1722 | bufpoi += toread; | |
1723 | length -= toread; | |
1724 | } | |
1725 | if (length > 0) | |
1726 | chip->read_buf(mtd, bufpoi, length); | |
1727 | ||
5c2ffb11 | 1728 | return 0; |
7bc3312b TG |
1729 | } |
1730 | ||
1731 | /** | |
7854d3f7 | 1732 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1733 | * @mtd: mtd info structure |
1734 | * @chip: nand chip info structure | |
1735 | * @page: page number to write | |
7bc3312b TG |
1736 | */ |
1737 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1738 | int page) | |
1739 | { | |
1740 | int status = 0; | |
1741 | const uint8_t *buf = chip->oob_poi; | |
1742 | int length = mtd->oobsize; | |
1743 | ||
1744 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1745 | chip->write_buf(mtd, buf, length); | |
1746 | /* Send command to program the OOB data */ | |
1747 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1748 | ||
1749 | status = chip->waitfunc(mtd, chip); | |
1750 | ||
0d420f9d | 1751 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1752 | } |
1753 | ||
1754 | /** | |
7854d3f7 | 1755 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1756 | * with syndrome - only for large page flash |
1757 | * @mtd: mtd info structure | |
1758 | * @chip: nand chip info structure | |
1759 | * @page: page number to write | |
7bc3312b TG |
1760 | */ |
1761 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1762 | struct nand_chip *chip, int page) | |
1763 | { | |
1764 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1765 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1766 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1767 | const uint8_t *bufpoi = chip->oob_poi; | |
1768 | ||
1769 | /* | |
1770 | * data-ecc-data-ecc ... ecc-oob | |
1771 | * or | |
1772 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1773 | */ | |
1774 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1775 | pos = steps * (eccsize + chunk); | |
1776 | steps = 0; | |
1777 | } else | |
8b0036ee | 1778 | pos = eccsize; |
7bc3312b TG |
1779 | |
1780 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1781 | for (i = 0; i < steps; i++) { | |
1782 | if (sndcmd) { | |
1783 | if (mtd->writesize <= 512) { | |
1784 | uint32_t fill = 0xFFFFFFFF; | |
1785 | ||
1786 | len = eccsize; | |
1787 | while (len > 0) { | |
1788 | int num = min_t(int, len, 4); | |
1789 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1790 | num); | |
1791 | len -= num; | |
1792 | } | |
1793 | } else { | |
1794 | pos = eccsize + i * (eccsize + chunk); | |
1795 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1796 | } | |
1797 | } else | |
1798 | sndcmd = 1; | |
1799 | len = min_t(int, length, chunk); | |
1800 | chip->write_buf(mtd, bufpoi, len); | |
1801 | bufpoi += len; | |
1802 | length -= len; | |
1803 | } | |
1804 | if (length > 0) | |
1805 | chip->write_buf(mtd, bufpoi, length); | |
1806 | ||
1807 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1808 | status = chip->waitfunc(mtd, chip); | |
1809 | ||
1810 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1811 | } | |
1812 | ||
1da177e4 | 1813 | /** |
7854d3f7 | 1814 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
1815 | * @mtd: MTD device structure |
1816 | * @from: offset to read from | |
1817 | * @ops: oob operations description structure | |
1da177e4 | 1818 | * |
8b6e50c9 | 1819 | * NAND read out-of-band data from the spare area. |
1da177e4 | 1820 | */ |
8593fbc6 TG |
1821 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1822 | struct mtd_oob_ops *ops) | |
1da177e4 | 1823 | { |
c00a0991 | 1824 | int page, realpage, chipnr; |
ace4dfee | 1825 | struct nand_chip *chip = mtd->priv; |
041e4575 | 1826 | struct mtd_ecc_stats stats; |
7014568b VW |
1827 | int readlen = ops->ooblen; |
1828 | int len; | |
7bc3312b | 1829 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 1830 | int ret = 0; |
61b03bd7 | 1831 | |
289c0522 | 1832 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 1833 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 1834 | |
041e4575 BN |
1835 | stats = mtd->ecc_stats; |
1836 | ||
0612b9dd | 1837 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 1838 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1839 | else |
1840 | len = mtd->oobsize; | |
1841 | ||
1842 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
1843 | pr_debug("%s: attempt to start read outside oob\n", |
1844 | __func__); | |
03736155 AH |
1845 | return -EINVAL; |
1846 | } | |
1847 | ||
1848 | /* Do not allow reads past end of device */ | |
1849 | if (unlikely(from >= mtd->size || | |
1850 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1851 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
1852 | pr_debug("%s: attempt to read beyond end of device\n", |
1853 | __func__); | |
03736155 AH |
1854 | return -EINVAL; |
1855 | } | |
7014568b | 1856 | |
7314e9e7 | 1857 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1858 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1859 | |
7314e9e7 TG |
1860 | /* Shift to get page */ |
1861 | realpage = (int)(from >> chip->page_shift); | |
1862 | page = realpage & chip->pagemask; | |
1da177e4 | 1863 | |
f8ac0414 | 1864 | while (1) { |
0612b9dd | 1865 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 1866 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 1867 | else |
1951f2f7 SL |
1868 | ret = chip->ecc.read_oob(mtd, chip, page); |
1869 | ||
1870 | if (ret < 0) | |
1871 | break; | |
7014568b VW |
1872 | |
1873 | len = min(len, readlen); | |
1874 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1875 | |
5bc7c33c BN |
1876 | if (chip->options & NAND_NEED_READRDY) { |
1877 | /* Apply delay or wait for ready/busy pin */ | |
1878 | if (!chip->dev_ready) | |
1879 | udelay(chip->chip_delay); | |
1880 | else | |
1881 | nand_wait_ready(mtd); | |
1882 | } | |
1883 | ||
7014568b | 1884 | readlen -= len; |
0d420f9d SZ |
1885 | if (!readlen) |
1886 | break; | |
1887 | ||
7314e9e7 TG |
1888 | /* Increment page address */ |
1889 | realpage++; | |
1890 | ||
1891 | page = realpage & chip->pagemask; | |
1892 | /* Check, if we cross a chip boundary */ | |
1893 | if (!page) { | |
1894 | chipnr++; | |
1895 | chip->select_chip(mtd, -1); | |
1896 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1897 | } |
1898 | } | |
b0bb6903 | 1899 | chip->select_chip(mtd, -1); |
1da177e4 | 1900 | |
1951f2f7 SL |
1901 | ops->oobretlen = ops->ooblen - readlen; |
1902 | ||
1903 | if (ret < 0) | |
1904 | return ret; | |
041e4575 BN |
1905 | |
1906 | if (mtd->ecc_stats.failed - stats.failed) | |
1907 | return -EBADMSG; | |
1908 | ||
1909 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
1910 | } |
1911 | ||
1912 | /** | |
8593fbc6 | 1913 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
1914 | * @mtd: MTD device structure |
1915 | * @from: offset to read from | |
1916 | * @ops: oob operation description structure | |
1da177e4 | 1917 | * |
8b6e50c9 | 1918 | * NAND read data and/or out-of-band data. |
1da177e4 | 1919 | */ |
8593fbc6 TG |
1920 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1921 | struct mtd_oob_ops *ops) | |
1da177e4 | 1922 | { |
8593fbc6 TG |
1923 | int ret = -ENOTSUPP; |
1924 | ||
1925 | ops->retlen = 0; | |
1da177e4 LT |
1926 | |
1927 | /* Do not allow reads past end of device */ | |
7014568b | 1928 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
1929 | pr_debug("%s: attempt to read beyond end of device\n", |
1930 | __func__); | |
1da177e4 LT |
1931 | return -EINVAL; |
1932 | } | |
1933 | ||
6a8214aa | 1934 | nand_get_device(mtd, FL_READING); |
1da177e4 | 1935 | |
f8ac0414 | 1936 | switch (ops->mode) { |
0612b9dd BN |
1937 | case MTD_OPS_PLACE_OOB: |
1938 | case MTD_OPS_AUTO_OOB: | |
1939 | case MTD_OPS_RAW: | |
8593fbc6 | 1940 | break; |
1da177e4 | 1941 | |
8593fbc6 TG |
1942 | default: |
1943 | goto out; | |
1944 | } | |
1da177e4 | 1945 | |
8593fbc6 TG |
1946 | if (!ops->datbuf) |
1947 | ret = nand_do_read_oob(mtd, from, ops); | |
1948 | else | |
1949 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1950 | |
7351d3a5 | 1951 | out: |
8593fbc6 TG |
1952 | nand_release_device(mtd); |
1953 | return ret; | |
1954 | } | |
61b03bd7 | 1955 | |
1da177e4 | 1956 | |
8593fbc6 | 1957 | /** |
7854d3f7 | 1958 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
1959 | * @mtd: mtd info structure |
1960 | * @chip: nand chip info structure | |
1961 | * @buf: data buffer | |
1fbb938d | 1962 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df | 1963 | * |
7854d3f7 | 1964 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 1965 | */ |
fdbad98d | 1966 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1967 | const uint8_t *buf, int oob_required) |
8593fbc6 TG |
1968 | { |
1969 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1970 | if (oob_required) |
1971 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
1972 | |
1973 | return 0; | |
1da177e4 LT |
1974 | } |
1975 | ||
52ff49df | 1976 | /** |
7854d3f7 | 1977 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
1978 | * @mtd: mtd info structure |
1979 | * @chip: nand chip info structure | |
1980 | * @buf: data buffer | |
1fbb938d | 1981 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df DB |
1982 | * |
1983 | * We need a special oob layout and handling even when ECC isn't checked. | |
1984 | */ | |
fdbad98d | 1985 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 1986 | struct nand_chip *chip, |
1fbb938d | 1987 | const uint8_t *buf, int oob_required) |
52ff49df DB |
1988 | { |
1989 | int eccsize = chip->ecc.size; | |
1990 | int eccbytes = chip->ecc.bytes; | |
1991 | uint8_t *oob = chip->oob_poi; | |
1992 | int steps, size; | |
1993 | ||
1994 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1995 | chip->write_buf(mtd, buf, eccsize); | |
1996 | buf += eccsize; | |
1997 | ||
1998 | if (chip->ecc.prepad) { | |
1999 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2000 | oob += chip->ecc.prepad; | |
2001 | } | |
2002 | ||
2003 | chip->read_buf(mtd, oob, eccbytes); | |
2004 | oob += eccbytes; | |
2005 | ||
2006 | if (chip->ecc.postpad) { | |
2007 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2008 | oob += chip->ecc.postpad; | |
2009 | } | |
2010 | } | |
2011 | ||
2012 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2013 | if (size) | |
2014 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2015 | |
2016 | return 0; | |
52ff49df | 2017 | } |
9223a456 | 2018 | /** |
7854d3f7 | 2019 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2020 | * @mtd: mtd info structure |
2021 | * @chip: nand chip info structure | |
2022 | * @buf: data buffer | |
1fbb938d | 2023 | * @oob_required: must write chip->oob_poi to OOB |
9223a456 | 2024 | */ |
fdbad98d | 2025 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2026 | const uint8_t *buf, int oob_required) |
9223a456 | 2027 | { |
f75e5097 TG |
2028 | int i, eccsize = chip->ecc.size; |
2029 | int eccbytes = chip->ecc.bytes; | |
2030 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2031 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2032 | const uint8_t *p = buf; |
8b099a39 | 2033 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2034 | |
7854d3f7 | 2035 | /* Software ECC calculation */ |
8593fbc6 TG |
2036 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2037 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2038 | |
8593fbc6 TG |
2039 | for (i = 0; i < chip->ecc.total; i++) |
2040 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 2041 | |
fdbad98d | 2042 | return chip->ecc.write_page_raw(mtd, chip, buf, 1); |
f75e5097 | 2043 | } |
9223a456 | 2044 | |
f75e5097 | 2045 | /** |
7854d3f7 | 2046 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2047 | * @mtd: mtd info structure |
2048 | * @chip: nand chip info structure | |
2049 | * @buf: data buffer | |
1fbb938d | 2050 | * @oob_required: must write chip->oob_poi to OOB |
f75e5097 | 2051 | */ |
fdbad98d | 2052 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2053 | const uint8_t *buf, int oob_required) |
f75e5097 TG |
2054 | { |
2055 | int i, eccsize = chip->ecc.size; | |
2056 | int eccbytes = chip->ecc.bytes; | |
2057 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2058 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2059 | const uint8_t *p = buf; |
8b099a39 | 2060 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2061 | |
f75e5097 TG |
2062 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2063 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2064 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2065 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2066 | } |
2067 | ||
f75e5097 TG |
2068 | for (i = 0; i < chip->ecc.total; i++) |
2069 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2070 | ||
2071 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2072 | |
2073 | return 0; | |
9223a456 TG |
2074 | } |
2075 | ||
837a6ba4 GP |
2076 | |
2077 | /** | |
2078 | * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write | |
2079 | * @mtd: mtd info structure | |
2080 | * @chip: nand chip info structure | |
d6a95080 | 2081 | * @offset: column address of subpage within the page |
837a6ba4 | 2082 | * @data_len: data length |
d6a95080 | 2083 | * @buf: data buffer |
837a6ba4 GP |
2084 | * @oob_required: must write chip->oob_poi to OOB |
2085 | */ | |
2086 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2087 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2088 | uint32_t data_len, const uint8_t *buf, |
837a6ba4 GP |
2089 | int oob_required) |
2090 | { | |
2091 | uint8_t *oob_buf = chip->oob_poi; | |
2092 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2093 | int ecc_size = chip->ecc.size; | |
2094 | int ecc_bytes = chip->ecc.bytes; | |
2095 | int ecc_steps = chip->ecc.steps; | |
2096 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
2097 | uint32_t start_step = offset / ecc_size; | |
2098 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2099 | int oob_bytes = mtd->oobsize / ecc_steps; | |
2100 | int step, i; | |
2101 | ||
2102 | for (step = 0; step < ecc_steps; step++) { | |
2103 | /* configure controller for WRITE access */ | |
2104 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2105 | ||
2106 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2107 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2108 | |
2109 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2110 | if ((step < start_step) || (step > end_step)) | |
2111 | memset(ecc_calc, 0xff, ecc_bytes); | |
2112 | else | |
d6a95080 | 2113 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2114 | |
2115 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2116 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2117 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2118 | memset(oob_buf, 0xff, oob_bytes); | |
2119 | ||
d6a95080 | 2120 | buf += ecc_size; |
837a6ba4 GP |
2121 | ecc_calc += ecc_bytes; |
2122 | oob_buf += oob_bytes; | |
2123 | } | |
2124 | ||
2125 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2126 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2127 | ecc_calc = chip->buffers->ecccalc; | |
2128 | for (i = 0; i < chip->ecc.total; i++) | |
2129 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2130 | ||
2131 | /* write OOB buffer to NAND device */ | |
2132 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2133 | ||
2134 | return 0; | |
2135 | } | |
2136 | ||
2137 | ||
61b03bd7 | 2138 | /** |
7854d3f7 | 2139 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2140 | * @mtd: mtd info structure |
2141 | * @chip: nand chip info structure | |
2142 | * @buf: data buffer | |
1fbb938d | 2143 | * @oob_required: must write chip->oob_poi to OOB |
1da177e4 | 2144 | * |
8b6e50c9 BN |
2145 | * The hw generator calculates the error syndrome automatically. Therefore we |
2146 | * need a special oob layout and handling. | |
f75e5097 | 2147 | */ |
fdbad98d | 2148 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
2149 | struct nand_chip *chip, |
2150 | const uint8_t *buf, int oob_required) | |
1da177e4 | 2151 | { |
f75e5097 TG |
2152 | int i, eccsize = chip->ecc.size; |
2153 | int eccbytes = chip->ecc.bytes; | |
2154 | int eccsteps = chip->ecc.steps; | |
2155 | const uint8_t *p = buf; | |
2156 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2157 | |
f75e5097 | 2158 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2159 | |
f75e5097 TG |
2160 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2161 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2162 | |
f75e5097 TG |
2163 | if (chip->ecc.prepad) { |
2164 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2165 | oob += chip->ecc.prepad; | |
2166 | } | |
2167 | ||
2168 | chip->ecc.calculate(mtd, p, oob); | |
2169 | chip->write_buf(mtd, oob, eccbytes); | |
2170 | oob += eccbytes; | |
2171 | ||
2172 | if (chip->ecc.postpad) { | |
2173 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2174 | oob += chip->ecc.postpad; | |
1da177e4 | 2175 | } |
1da177e4 | 2176 | } |
f75e5097 TG |
2177 | |
2178 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2179 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2180 | if (i) |
2181 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2182 | |
2183 | return 0; | |
f75e5097 TG |
2184 | } |
2185 | ||
2186 | /** | |
956e944c | 2187 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2188 | * @mtd: MTD device structure |
2189 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2190 | * @offset: address offset within the page |
2191 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2192 | * @buf: the data to write |
1fbb938d | 2193 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2194 | * @page: page number to write |
2195 | * @cached: cached programming | |
2196 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2197 | */ |
2198 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
2199 | uint32_t offset, int data_len, const uint8_t *buf, |
2200 | int oob_required, int page, int cached, int raw) | |
f75e5097 | 2201 | { |
837a6ba4 GP |
2202 | int status, subpage; |
2203 | ||
2204 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2205 | chip->ecc.write_subpage) | |
2206 | subpage = offset || (data_len < mtd->writesize); | |
2207 | else | |
2208 | subpage = 0; | |
f75e5097 TG |
2209 | |
2210 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2211 | ||
956e944c | 2212 | if (unlikely(raw)) |
837a6ba4 GP |
2213 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
2214 | oob_required); | |
2215 | else if (subpage) | |
2216 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
2217 | buf, oob_required); | |
956e944c | 2218 | else |
fdbad98d JW |
2219 | status = chip->ecc.write_page(mtd, chip, buf, oob_required); |
2220 | ||
2221 | if (status < 0) | |
2222 | return status; | |
f75e5097 TG |
2223 | |
2224 | /* | |
7854d3f7 | 2225 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2226 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2227 | */ |
2228 | cached = 0; | |
2229 | ||
3239a6cd | 2230 | if (!cached || !NAND_HAS_CACHEPROG(chip)) { |
f75e5097 TG |
2231 | |
2232 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2233 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2234 | /* |
2235 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2236 | * available. |
f75e5097 TG |
2237 | */ |
2238 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2239 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2240 | page); | |
2241 | ||
2242 | if (status & NAND_STATUS_FAIL) | |
2243 | return -EIO; | |
2244 | } else { | |
2245 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2246 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2247 | } |
2248 | ||
f75e5097 | 2249 | return 0; |
1da177e4 LT |
2250 | } |
2251 | ||
8593fbc6 | 2252 | /** |
7854d3f7 | 2253 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2254 | * @mtd: MTD device structure |
8b6e50c9 BN |
2255 | * @oob: oob data buffer |
2256 | * @len: oob data write length | |
2257 | * @ops: oob ops structure | |
8593fbc6 | 2258 | */ |
f722013e TAA |
2259 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2260 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2261 | { |
f722013e TAA |
2262 | struct nand_chip *chip = mtd->priv; |
2263 | ||
2264 | /* | |
2265 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2266 | * data from a previous OOB read. | |
2267 | */ | |
2268 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2269 | ||
f8ac0414 | 2270 | switch (ops->mode) { |
8593fbc6 | 2271 | |
0612b9dd BN |
2272 | case MTD_OPS_PLACE_OOB: |
2273 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2274 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2275 | return oob + len; | |
2276 | ||
0612b9dd | 2277 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2278 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2279 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2280 | size_t bytes = 0; | |
8593fbc6 | 2281 | |
f8ac0414 | 2282 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2283 | /* Write request not from offset 0? */ |
7bc3312b TG |
2284 | if (unlikely(woffs)) { |
2285 | if (woffs >= free->length) { | |
2286 | woffs -= free->length; | |
2287 | continue; | |
2288 | } | |
2289 | boffs = free->offset + woffs; | |
2290 | bytes = min_t(size_t, len, | |
2291 | (free->length - woffs)); | |
2292 | woffs = 0; | |
2293 | } else { | |
2294 | bytes = min_t(size_t, len, free->length); | |
2295 | boffs = free->offset; | |
2296 | } | |
8b0036ee | 2297 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2298 | oob += bytes; |
2299 | } | |
2300 | return oob; | |
2301 | } | |
2302 | default: | |
2303 | BUG(); | |
2304 | } | |
2305 | return NULL; | |
2306 | } | |
2307 | ||
f8ac0414 | 2308 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2309 | |
2310 | /** | |
7854d3f7 | 2311 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2312 | * @mtd: MTD device structure |
2313 | * @to: offset to write to | |
2314 | * @ops: oob operations description structure | |
1da177e4 | 2315 | * |
8b6e50c9 | 2316 | * NAND write with ECC. |
1da177e4 | 2317 | */ |
8593fbc6 TG |
2318 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2319 | struct mtd_oob_ops *ops) | |
1da177e4 | 2320 | { |
29072b96 | 2321 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2322 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2323 | uint32_t writelen = ops->len; |
782ce79a ML |
2324 | |
2325 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2326 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2327 | mtd->oobavail : mtd->oobsize; |
2328 | ||
8593fbc6 TG |
2329 | uint8_t *oob = ops->oobbuf; |
2330 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2331 | int ret; |
e47f3db4 | 2332 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2333 | |
8593fbc6 | 2334 | ops->retlen = 0; |
29072b96 TG |
2335 | if (!writelen) |
2336 | return 0; | |
1da177e4 | 2337 | |
8b6e50c9 | 2338 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2339 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2340 | pr_notice("%s: attempt to write non page aligned data\n", |
2341 | __func__); | |
1da177e4 LT |
2342 | return -EINVAL; |
2343 | } | |
2344 | ||
29072b96 | 2345 | column = to & (mtd->writesize - 1); |
1da177e4 | 2346 | |
6a930961 TG |
2347 | chipnr = (int)(to >> chip->chip_shift); |
2348 | chip->select_chip(mtd, chipnr); | |
2349 | ||
1da177e4 | 2350 | /* Check, if it is write protected */ |
b0bb6903 HS |
2351 | if (nand_check_wp(mtd)) { |
2352 | ret = -EIO; | |
2353 | goto err_out; | |
2354 | } | |
1da177e4 | 2355 | |
f75e5097 TG |
2356 | realpage = (int)(to >> chip->page_shift); |
2357 | page = realpage & chip->pagemask; | |
2358 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2359 | ||
2360 | /* Invalidate the page cache, when we write to the cached page */ | |
2361 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2362 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2363 | chip->pagebuf = -1; |
61b03bd7 | 2364 | |
782ce79a | 2365 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2366 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2367 | ret = -EINVAL; | |
2368 | goto err_out; | |
2369 | } | |
782ce79a | 2370 | |
f8ac0414 | 2371 | while (1) { |
29072b96 | 2372 | int bytes = mtd->writesize; |
f75e5097 | 2373 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2374 | uint8_t *wbuf = buf; |
2375 | ||
8b6e50c9 | 2376 | /* Partial page write? */ |
29072b96 TG |
2377 | if (unlikely(column || writelen < (mtd->writesize - 1))) { |
2378 | cached = 0; | |
2379 | bytes = min_t(int, bytes - column, (int) writelen); | |
2380 | chip->pagebuf = -1; | |
2381 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2382 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2383 | wbuf = chip->buffers->databuf; | |
2384 | } | |
1da177e4 | 2385 | |
782ce79a ML |
2386 | if (unlikely(oob)) { |
2387 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2388 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2389 | oobwritelen -= len; |
f722013e TAA |
2390 | } else { |
2391 | /* We still need to erase leftover OOB data */ | |
2392 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2393 | } |
837a6ba4 GP |
2394 | ret = chip->write_page(mtd, chip, column, bytes, wbuf, |
2395 | oob_required, page, cached, | |
2396 | (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2397 | if (ret) |
2398 | break; | |
2399 | ||
2400 | writelen -= bytes; | |
2401 | if (!writelen) | |
2402 | break; | |
2403 | ||
29072b96 | 2404 | column = 0; |
f75e5097 TG |
2405 | buf += bytes; |
2406 | realpage++; | |
2407 | ||
2408 | page = realpage & chip->pagemask; | |
2409 | /* Check, if we cross a chip boundary */ | |
2410 | if (!page) { | |
2411 | chipnr++; | |
2412 | chip->select_chip(mtd, -1); | |
2413 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2414 | } |
2415 | } | |
8593fbc6 | 2416 | |
8593fbc6 | 2417 | ops->retlen = ops->len - writelen; |
7014568b VW |
2418 | if (unlikely(oob)) |
2419 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2420 | |
2421 | err_out: | |
2422 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2423 | return ret; |
2424 | } | |
2425 | ||
2af7c653 SK |
2426 | /** |
2427 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2428 | * @mtd: MTD device structure |
2429 | * @to: offset to write to | |
2430 | * @len: number of bytes to write | |
2431 | * @retlen: pointer to variable to store the number of written bytes | |
2432 | * @buf: the data to write | |
2af7c653 SK |
2433 | * |
2434 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2435 | * may for example be called by mtdoops when writing an oops while in panic. | |
2436 | */ | |
2437 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2438 | size_t *retlen, const uint8_t *buf) | |
2439 | { | |
2440 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2441 | struct mtd_oob_ops ops; |
2af7c653 SK |
2442 | int ret; |
2443 | ||
8b6e50c9 | 2444 | /* Wait for the device to get ready */ |
2af7c653 SK |
2445 | panic_nand_wait(mtd, chip, 400); |
2446 | ||
8b6e50c9 | 2447 | /* Grab the device */ |
2af7c653 SK |
2448 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2449 | ||
4a89ff88 BN |
2450 | ops.len = len; |
2451 | ops.datbuf = (uint8_t *)buf; | |
2452 | ops.oobbuf = NULL; | |
11041ae6 | 2453 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2454 | |
4a89ff88 | 2455 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2456 | |
4a89ff88 | 2457 | *retlen = ops.retlen; |
2af7c653 SK |
2458 | return ret; |
2459 | } | |
2460 | ||
f75e5097 | 2461 | /** |
8593fbc6 | 2462 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2463 | * @mtd: MTD device structure |
2464 | * @to: offset to write to | |
2465 | * @len: number of bytes to write | |
2466 | * @retlen: pointer to variable to store the number of written bytes | |
2467 | * @buf: the data to write | |
f75e5097 | 2468 | * |
8b6e50c9 | 2469 | * NAND write with ECC. |
f75e5097 | 2470 | */ |
8593fbc6 TG |
2471 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2472 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2473 | { |
4a89ff88 | 2474 | struct mtd_oob_ops ops; |
f75e5097 TG |
2475 | int ret; |
2476 | ||
6a8214aa | 2477 | nand_get_device(mtd, FL_WRITING); |
4a89ff88 BN |
2478 | ops.len = len; |
2479 | ops.datbuf = (uint8_t *)buf; | |
2480 | ops.oobbuf = NULL; | |
11041ae6 | 2481 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2482 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2483 | *retlen = ops.retlen; |
f75e5097 | 2484 | nand_release_device(mtd); |
8593fbc6 | 2485 | return ret; |
f75e5097 | 2486 | } |
7314e9e7 | 2487 | |
1da177e4 | 2488 | /** |
8593fbc6 | 2489 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2490 | * @mtd: MTD device structure |
2491 | * @to: offset to write to | |
2492 | * @ops: oob operation description structure | |
1da177e4 | 2493 | * |
8b6e50c9 | 2494 | * NAND write out-of-band. |
1da177e4 | 2495 | */ |
8593fbc6 TG |
2496 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2497 | struct mtd_oob_ops *ops) | |
1da177e4 | 2498 | { |
03736155 | 2499 | int chipnr, page, status, len; |
ace4dfee | 2500 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2501 | |
289c0522 | 2502 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2503 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2504 | |
0612b9dd | 2505 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2506 | len = chip->ecc.layout->oobavail; |
2507 | else | |
2508 | len = mtd->oobsize; | |
2509 | ||
1da177e4 | 2510 | /* Do not allow write past end of page */ |
03736155 | 2511 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2512 | pr_debug("%s: attempt to write past end of page\n", |
2513 | __func__); | |
1da177e4 LT |
2514 | return -EINVAL; |
2515 | } | |
2516 | ||
03736155 | 2517 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2518 | pr_debug("%s: attempt to start write outside oob\n", |
2519 | __func__); | |
03736155 AH |
2520 | return -EINVAL; |
2521 | } | |
2522 | ||
775adc3d | 2523 | /* Do not allow write past end of device */ |
03736155 AH |
2524 | if (unlikely(to >= mtd->size || |
2525 | ops->ooboffs + ops->ooblen > | |
2526 | ((mtd->size >> chip->page_shift) - | |
2527 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2528 | pr_debug("%s: attempt to write beyond end of device\n", |
2529 | __func__); | |
03736155 AH |
2530 | return -EINVAL; |
2531 | } | |
2532 | ||
7314e9e7 | 2533 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2534 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2535 | |
7314e9e7 TG |
2536 | /* Shift to get page */ |
2537 | page = (int)(to >> chip->page_shift); | |
2538 | ||
2539 | /* | |
2540 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2541 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2542 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2543 | * it in the doc2000 driver in August 1999. dwmw2. | |
2544 | */ | |
ace4dfee | 2545 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2546 | |
2547 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2548 | if (nand_check_wp(mtd)) { |
2549 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2550 | return -EROFS; |
b0bb6903 | 2551 | } |
61b03bd7 | 2552 | |
1da177e4 | 2553 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2554 | if (page == chip->pagebuf) |
2555 | chip->pagebuf = -1; | |
1da177e4 | 2556 | |
f722013e | 2557 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2558 | |
0612b9dd | 2559 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2560 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2561 | else | |
2562 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2563 | |
b0bb6903 HS |
2564 | chip->select_chip(mtd, -1); |
2565 | ||
7bc3312b TG |
2566 | if (status) |
2567 | return status; | |
1da177e4 | 2568 | |
7014568b | 2569 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2570 | |
7bc3312b | 2571 | return 0; |
8593fbc6 TG |
2572 | } |
2573 | ||
2574 | /** | |
2575 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2576 | * @mtd: MTD device structure |
2577 | * @to: offset to write to | |
2578 | * @ops: oob operation description structure | |
8593fbc6 TG |
2579 | */ |
2580 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2581 | struct mtd_oob_ops *ops) | |
2582 | { | |
8593fbc6 TG |
2583 | int ret = -ENOTSUPP; |
2584 | ||
2585 | ops->retlen = 0; | |
2586 | ||
2587 | /* Do not allow writes past end of device */ | |
7014568b | 2588 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2589 | pr_debug("%s: attempt to write beyond end of device\n", |
2590 | __func__); | |
8593fbc6 TG |
2591 | return -EINVAL; |
2592 | } | |
2593 | ||
6a8214aa | 2594 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2595 | |
f8ac0414 | 2596 | switch (ops->mode) { |
0612b9dd BN |
2597 | case MTD_OPS_PLACE_OOB: |
2598 | case MTD_OPS_AUTO_OOB: | |
2599 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2600 | break; |
2601 | ||
2602 | default: | |
2603 | goto out; | |
2604 | } | |
2605 | ||
2606 | if (!ops->datbuf) | |
2607 | ret = nand_do_write_oob(mtd, to, ops); | |
2608 | else | |
2609 | ret = nand_do_write_ops(mtd, to, ops); | |
2610 | ||
7351d3a5 | 2611 | out: |
1da177e4 | 2612 | nand_release_device(mtd); |
1da177e4 LT |
2613 | return ret; |
2614 | } | |
2615 | ||
1da177e4 | 2616 | /** |
7854d3f7 | 2617 | * single_erase_cmd - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2618 | * @mtd: MTD device structure |
2619 | * @page: the page address of the block which will be erased | |
1da177e4 | 2620 | * |
8b6e50c9 | 2621 | * Standard erase command for NAND chips. |
1da177e4 | 2622 | */ |
e0c7d767 | 2623 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2624 | { |
ace4dfee | 2625 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2626 | /* Send commands to erase a block */ |
ace4dfee TG |
2627 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2628 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2629 | } |
2630 | ||
1da177e4 LT |
2631 | /** |
2632 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2633 | * @mtd: MTD device structure |
2634 | * @instr: erase instruction | |
1da177e4 | 2635 | * |
8b6e50c9 | 2636 | * Erase one ore more blocks. |
1da177e4 | 2637 | */ |
e0c7d767 | 2638 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2639 | { |
e0c7d767 | 2640 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2641 | } |
61b03bd7 | 2642 | |
1da177e4 | 2643 | /** |
7854d3f7 | 2644 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2645 | * @mtd: MTD device structure |
2646 | * @instr: erase instruction | |
2647 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2648 | * |
8b6e50c9 | 2649 | * Erase one ore more blocks. |
1da177e4 | 2650 | */ |
ace4dfee TG |
2651 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2652 | int allowbbt) | |
1da177e4 | 2653 | { |
69423d99 | 2654 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2655 | struct nand_chip *chip = mtd->priv; |
69423d99 | 2656 | loff_t len; |
1da177e4 | 2657 | |
289c0522 BN |
2658 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2659 | __func__, (unsigned long long)instr->addr, | |
2660 | (unsigned long long)instr->len); | |
1da177e4 | 2661 | |
6fe5a6ac | 2662 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2663 | return -EINVAL; |
1da177e4 | 2664 | |
1da177e4 | 2665 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2666 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2667 | |
2668 | /* Shift to get first page */ | |
ace4dfee TG |
2669 | page = (int)(instr->addr >> chip->page_shift); |
2670 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2671 | |
2672 | /* Calculate pages in each block */ | |
ace4dfee | 2673 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2674 | |
2675 | /* Select the NAND device */ | |
ace4dfee | 2676 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2677 | |
1da177e4 LT |
2678 | /* Check, if it is write protected */ |
2679 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2680 | pr_debug("%s: device is write protected!\n", |
2681 | __func__); | |
1da177e4 LT |
2682 | instr->state = MTD_ERASE_FAILED; |
2683 | goto erase_exit; | |
2684 | } | |
2685 | ||
2686 | /* Loop through the pages */ | |
2687 | len = instr->len; | |
2688 | ||
2689 | instr->state = MTD_ERASING; | |
2690 | ||
2691 | while (len) { | |
12183a20 | 2692 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2693 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2694 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2695 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2696 | __func__, page); | |
1da177e4 LT |
2697 | instr->state = MTD_ERASE_FAILED; |
2698 | goto erase_exit; | |
2699 | } | |
61b03bd7 | 2700 | |
ace4dfee TG |
2701 | /* |
2702 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2703 | * contains the current cached page. |
ace4dfee TG |
2704 | */ |
2705 | if (page <= chip->pagebuf && chip->pagebuf < | |
2706 | (page + pages_per_block)) | |
2707 | chip->pagebuf = -1; | |
1da177e4 | 2708 | |
ace4dfee | 2709 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2710 | |
7bc3312b | 2711 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2712 | |
ace4dfee TG |
2713 | /* |
2714 | * See if operation failed and additional status checks are | |
2715 | * available | |
2716 | */ | |
2717 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2718 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2719 | status, page); | |
068e3c0a | 2720 | |
1da177e4 | 2721 | /* See if block erase succeeded */ |
a4ab4c5d | 2722 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2723 | pr_debug("%s: failed erase, page 0x%08x\n", |
2724 | __func__, page); | |
1da177e4 | 2725 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2726 | instr->fail_addr = |
2727 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2728 | goto erase_exit; |
2729 | } | |
30f464b7 | 2730 | |
1da177e4 | 2731 | /* Increment page address and decrement length */ |
daae74ca | 2732 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
2733 | page += pages_per_block; |
2734 | ||
2735 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2736 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2737 | chipnr++; |
ace4dfee TG |
2738 | chip->select_chip(mtd, -1); |
2739 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2740 | } |
2741 | } | |
2742 | instr->state = MTD_ERASE_DONE; | |
2743 | ||
7351d3a5 | 2744 | erase_exit: |
1da177e4 LT |
2745 | |
2746 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2747 | |
2748 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2749 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2750 | nand_release_device(mtd); |
2751 | ||
49defc01 DW |
2752 | /* Do call back function */ |
2753 | if (!ret) | |
2754 | mtd_erase_callback(instr); | |
2755 | ||
1da177e4 LT |
2756 | /* Return more or less happy */ |
2757 | return ret; | |
2758 | } | |
2759 | ||
2760 | /** | |
2761 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2762 | * @mtd: MTD device structure |
1da177e4 | 2763 | * |
8b6e50c9 | 2764 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2765 | */ |
e0c7d767 | 2766 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2767 | { |
289c0522 | 2768 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2769 | |
2770 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 2771 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 2772 | /* Release it and go back */ |
e0c7d767 | 2773 | nand_release_device(mtd); |
1da177e4 LT |
2774 | } |
2775 | ||
1da177e4 | 2776 | /** |
ace4dfee | 2777 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2778 | * @mtd: MTD device structure |
2779 | * @offs: offset relative to mtd start | |
1da177e4 | 2780 | */ |
ace4dfee | 2781 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 2782 | { |
ace4dfee | 2783 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2784 | } |
2785 | ||
2786 | /** | |
ace4dfee | 2787 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2788 | * @mtd: MTD device structure |
2789 | * @ofs: offset relative to mtd start | |
1da177e4 | 2790 | */ |
e0c7d767 | 2791 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2792 | { |
1da177e4 LT |
2793 | int ret; |
2794 | ||
f8ac0414 FF |
2795 | ret = nand_block_isbad(mtd, ofs); |
2796 | if (ret) { | |
8b6e50c9 | 2797 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
2798 | if (ret > 0) |
2799 | return 0; | |
e0c7d767 DW |
2800 | return ret; |
2801 | } | |
1da177e4 | 2802 | |
5a0edb25 | 2803 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
2804 | } |
2805 | ||
7db03ecc HS |
2806 | /** |
2807 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
2808 | * @mtd: MTD device structure | |
2809 | * @chip: nand chip info structure | |
2810 | * @addr: feature address. | |
2811 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2812 | */ | |
2813 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2814 | int addr, uint8_t *subfeature_param) | |
2815 | { | |
2816 | int status; | |
05f78359 | 2817 | int i; |
7db03ecc | 2818 | |
d914c932 DM |
2819 | if (!chip->onfi_version || |
2820 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
2821 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
2822 | return -EINVAL; |
2823 | ||
2824 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
2825 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
2826 | chip->write_byte(mtd, subfeature_param[i]); | |
2827 | ||
7db03ecc HS |
2828 | status = chip->waitfunc(mtd, chip); |
2829 | if (status & NAND_STATUS_FAIL) | |
2830 | return -EIO; | |
2831 | return 0; | |
2832 | } | |
2833 | ||
2834 | /** | |
2835 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
2836 | * @mtd: MTD device structure | |
2837 | * @chip: nand chip info structure | |
2838 | * @addr: feature address. | |
2839 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2840 | */ | |
2841 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2842 | int addr, uint8_t *subfeature_param) | |
2843 | { | |
05f78359 UKK |
2844 | int i; |
2845 | ||
d914c932 DM |
2846 | if (!chip->onfi_version || |
2847 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
2848 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
2849 | return -EINVAL; |
2850 | ||
2851 | /* clear the sub feature parameters */ | |
2852 | memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); | |
2853 | ||
2854 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); | |
05f78359 UKK |
2855 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
2856 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
2857 | return 0; |
2858 | } | |
2859 | ||
962034f4 VW |
2860 | /** |
2861 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 2862 | * @mtd: MTD device structure |
962034f4 VW |
2863 | */ |
2864 | static int nand_suspend(struct mtd_info *mtd) | |
2865 | { | |
6a8214aa | 2866 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2867 | } |
2868 | ||
2869 | /** | |
2870 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 2871 | * @mtd: MTD device structure |
962034f4 VW |
2872 | */ |
2873 | static void nand_resume(struct mtd_info *mtd) | |
2874 | { | |
ace4dfee | 2875 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2876 | |
ace4dfee | 2877 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2878 | nand_release_device(mtd); |
2879 | else | |
d0370219 BN |
2880 | pr_err("%s called for a chip which is not in suspended state\n", |
2881 | __func__); | |
962034f4 VW |
2882 | } |
2883 | ||
8b6e50c9 | 2884 | /* Set default functions */ |
ace4dfee | 2885 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2886 | { |
1da177e4 | 2887 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2888 | if (!chip->chip_delay) |
2889 | chip->chip_delay = 20; | |
1da177e4 LT |
2890 | |
2891 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2892 | if (chip->cmdfunc == NULL) |
2893 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2894 | |
2895 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2896 | if (chip->waitfunc == NULL) |
2897 | chip->waitfunc = nand_wait; | |
2898 | ||
2899 | if (!chip->select_chip) | |
2900 | chip->select_chip = nand_select_chip; | |
68e80780 | 2901 | |
4204cccd HS |
2902 | /* set for ONFI nand */ |
2903 | if (!chip->onfi_set_features) | |
2904 | chip->onfi_set_features = nand_onfi_set_features; | |
2905 | if (!chip->onfi_get_features) | |
2906 | chip->onfi_get_features = nand_onfi_get_features; | |
2907 | ||
68e80780 BN |
2908 | /* If called twice, pointers that depend on busw may need to be reset */ |
2909 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
2910 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
2911 | if (!chip->read_word) | |
2912 | chip->read_word = nand_read_word; | |
2913 | if (!chip->block_bad) | |
2914 | chip->block_bad = nand_block_bad; | |
2915 | if (!chip->block_markbad) | |
2916 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 2917 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 2918 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
2919 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
2920 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 2921 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 2922 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
2923 | if (!chip->scan_bbt) |
2924 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2925 | |
2926 | if (!chip->controller) { | |
2927 | chip->controller = &chip->hwcontrol; | |
2928 | spin_lock_init(&chip->controller->lock); | |
2929 | init_waitqueue_head(&chip->controller->wq); | |
2930 | } | |
2931 | ||
7aa65bfd TG |
2932 | } |
2933 | ||
8b6e50c9 | 2934 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
2935 | static void sanitize_string(uint8_t *s, size_t len) |
2936 | { | |
2937 | ssize_t i; | |
2938 | ||
8b6e50c9 | 2939 | /* Null terminate */ |
d1e1f4e4 FF |
2940 | s[len - 1] = 0; |
2941 | ||
8b6e50c9 | 2942 | /* Remove non printable chars */ |
d1e1f4e4 FF |
2943 | for (i = 0; i < len - 1; i++) { |
2944 | if (s[i] < ' ' || s[i] > 127) | |
2945 | s[i] = '?'; | |
2946 | } | |
2947 | ||
8b6e50c9 | 2948 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
2949 | strim(s); |
2950 | } | |
2951 | ||
2952 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
2953 | { | |
2954 | int i; | |
2955 | while (len--) { | |
2956 | crc ^= *p++ << 8; | |
2957 | for (i = 0; i < 8; i++) | |
2958 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
2959 | } | |
2960 | ||
2961 | return crc; | |
2962 | } | |
2963 | ||
6dcbe0cd HS |
2964 | /* Parse the Extended Parameter Page. */ |
2965 | static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, | |
2966 | struct nand_chip *chip, struct nand_onfi_params *p) | |
2967 | { | |
2968 | struct onfi_ext_param_page *ep; | |
2969 | struct onfi_ext_section *s; | |
2970 | struct onfi_ext_ecc_info *ecc; | |
2971 | uint8_t *cursor; | |
2972 | int ret = -EINVAL; | |
2973 | int len; | |
2974 | int i; | |
2975 | ||
2976 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
2977 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
2978 | if (!ep) |
2979 | return -ENOMEM; | |
6dcbe0cd HS |
2980 | |
2981 | /* Send our own NAND_CMD_PARAM. */ | |
2982 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
2983 | ||
2984 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
2985 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
2986 | sizeof(*p) * p->num_of_param_pages , -1); | |
2987 | ||
2988 | /* Read out the Extended Parameter Page. */ | |
2989 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
2990 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
2991 | != le16_to_cpu(ep->crc))) { | |
2992 | pr_debug("fail in the CRC.\n"); | |
2993 | goto ext_out; | |
2994 | } | |
2995 | ||
2996 | /* | |
2997 | * Check the signature. | |
2998 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
2999 | */ | |
3000 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3001 | pr_debug("The signature is invalid.\n"); | |
3002 | goto ext_out; | |
3003 | } | |
3004 | ||
3005 | /* find the ECC section. */ | |
3006 | cursor = (uint8_t *)(ep + 1); | |
3007 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3008 | s = ep->sections + i; | |
3009 | if (s->type == ONFI_SECTION_TYPE_2) | |
3010 | break; | |
3011 | cursor += s->length * 16; | |
3012 | } | |
3013 | if (i == ONFI_EXT_SECTION_MAX) { | |
3014 | pr_debug("We can not find the ECC section.\n"); | |
3015 | goto ext_out; | |
3016 | } | |
3017 | ||
3018 | /* get the info we want. */ | |
3019 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3020 | ||
4ae7d228 BN |
3021 | if (!ecc->codeword_size) { |
3022 | pr_debug("Invalid codeword size\n"); | |
3023 | goto ext_out; | |
6dcbe0cd HS |
3024 | } |
3025 | ||
4ae7d228 BN |
3026 | chip->ecc_strength_ds = ecc->ecc_bits; |
3027 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3028 | ret = 0; |
6dcbe0cd HS |
3029 | |
3030 | ext_out: | |
3031 | kfree(ep); | |
3032 | return ret; | |
3033 | } | |
3034 | ||
8429bb39 BN |
3035 | static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) |
3036 | { | |
3037 | struct nand_chip *chip = mtd->priv; | |
3038 | uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; | |
3039 | ||
3040 | return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, | |
3041 | feature); | |
3042 | } | |
3043 | ||
3044 | /* | |
3045 | * Configure chip properties from Micron vendor-specific ONFI table | |
3046 | */ | |
3047 | static void nand_onfi_detect_micron(struct nand_chip *chip, | |
3048 | struct nand_onfi_params *p) | |
3049 | { | |
3050 | struct nand_onfi_vendor_micron *micron = (void *)p->vendor; | |
3051 | ||
3052 | if (le16_to_cpu(p->vendor_revision) < 1) | |
3053 | return; | |
3054 | ||
3055 | chip->read_retries = micron->read_retry_options; | |
3056 | chip->setup_read_retry = nand_setup_read_retry_micron; | |
3057 | } | |
3058 | ||
6fb277ba | 3059 | /* |
8b6e50c9 | 3060 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
3061 | */ |
3062 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 3063 | int *busw) |
6fb277ba FF |
3064 | { |
3065 | struct nand_onfi_params *p = &chip->onfi_params; | |
3066 | int i; | |
3067 | int val; | |
3068 | ||
7854d3f7 | 3069 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3070 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3071 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3072 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3073 | return 0; | |
3074 | ||
c7f23a70 BN |
3075 | /* |
3076 | * ONFI must be probed in 8-bit mode or with NAND_BUSWIDTH_AUTO, not | |
3077 | * with NAND_BUSWIDTH_16 | |
3078 | */ | |
3079 | if (chip->options & NAND_BUSWIDTH_16) { | |
3080 | pr_err("ONFI cannot be probed in 16-bit mode; aborting\n"); | |
3081 | return 0; | |
3082 | } | |
3083 | ||
6fb277ba FF |
3084 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3085 | for (i = 0; i < 3; i++) { | |
3086 | chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); | |
3087 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == | |
3088 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3089 | break; |
3090 | } | |
3091 | } | |
3092 | ||
c7f23a70 BN |
3093 | if (i == 3) { |
3094 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3095 | return 0; |
c7f23a70 | 3096 | } |
6fb277ba | 3097 | |
8b6e50c9 | 3098 | /* Check version */ |
6fb277ba | 3099 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3100 | if (val & (1 << 5)) |
3101 | chip->onfi_version = 23; | |
3102 | else if (val & (1 << 4)) | |
6fb277ba FF |
3103 | chip->onfi_version = 22; |
3104 | else if (val & (1 << 3)) | |
3105 | chip->onfi_version = 21; | |
3106 | else if (val & (1 << 2)) | |
3107 | chip->onfi_version = 20; | |
b7b1a29d | 3108 | else if (val & (1 << 1)) |
6fb277ba | 3109 | chip->onfi_version = 10; |
b7b1a29d BN |
3110 | |
3111 | if (!chip->onfi_version) { | |
20171642 | 3112 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3113 | return 0; |
3114 | } | |
6fb277ba FF |
3115 | |
3116 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3117 | sanitize_string(p->model, sizeof(p->model)); | |
3118 | if (!mtd->name) | |
3119 | mtd->name = p->model; | |
4355b70c | 3120 | |
6fb277ba | 3121 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3122 | |
3123 | /* | |
3124 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3125 | * (don't ask me who thought of this...). MTD assumes that these | |
3126 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3127 | */ | |
3128 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3129 | mtd->erasesize *= mtd->writesize; | |
3130 | ||
6fb277ba | 3131 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3132 | |
3133 | /* See erasesize comment */ | |
3134 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3135 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3136 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 HS |
3137 | |
3138 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) | |
08c248fb | 3139 | *busw = NAND_BUSWIDTH_16; |
e2985fc1 HS |
3140 | else |
3141 | *busw = 0; | |
6fb277ba | 3142 | |
10c86bab HS |
3143 | if (p->ecc_bits != 0xff) { |
3144 | chip->ecc_strength_ds = p->ecc_bits; | |
3145 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3146 | } else if (chip->onfi_version >= 21 && |
3147 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3148 | ||
3149 | /* | |
3150 | * The nand_flash_detect_ext_param_page() uses the | |
3151 | * Change Read Column command which maybe not supported | |
3152 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3153 | * now. We do not replace user supplied command function. | |
3154 | */ | |
3155 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3156 | chip->cmdfunc = nand_command_lp; | |
3157 | ||
3158 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
3159 | if (nand_flash_detect_ext_param_page(mtd, chip, p)) | |
c7f23a70 BN |
3160 | pr_warn("Failed to detect ONFI extended param page\n"); |
3161 | } else { | |
3162 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3163 | } |
3164 | ||
8429bb39 BN |
3165 | if (p->jedec_id == NAND_MFR_MICRON) |
3166 | nand_onfi_detect_micron(chip, p); | |
3167 | ||
6fb277ba FF |
3168 | return 1; |
3169 | } | |
3170 | ||
e3b88bd6 BN |
3171 | /* |
3172 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3173 | * @id_data: the ID string | |
3174 | * @arrlen: the length of the @id_data array | |
3175 | * @period: the period of repitition | |
3176 | * | |
3177 | * Check if an ID string is repeated within a given sequence of bytes at | |
3178 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3179 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3180 | * if the repetition has a period of @period; otherwise, returns zero. |
3181 | */ | |
3182 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3183 | { | |
3184 | int i, j; | |
3185 | for (i = 0; i < period; i++) | |
3186 | for (j = i + period; j < arrlen; j += period) | |
3187 | if (id_data[i] != id_data[j]) | |
3188 | return 0; | |
3189 | return 1; | |
3190 | } | |
3191 | ||
3192 | /* | |
3193 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3194 | * @id_data: the ID string | |
3195 | * @arrlen: the length of the @id_data array | |
3196 | ||
3197 | * Returns the length of the ID string, according to known wraparound/trailing | |
3198 | * zero patterns. If no pattern exists, returns the length of the array. | |
3199 | */ | |
3200 | static int nand_id_len(u8 *id_data, int arrlen) | |
3201 | { | |
3202 | int last_nonzero, period; | |
3203 | ||
3204 | /* Find last non-zero byte */ | |
3205 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3206 | if (id_data[last_nonzero]) | |
3207 | break; | |
3208 | ||
3209 | /* All zeros */ | |
3210 | if (last_nonzero < 0) | |
3211 | return 0; | |
3212 | ||
3213 | /* Calculate wraparound period */ | |
3214 | for (period = 1; period < arrlen; period++) | |
3215 | if (nand_id_has_period(id_data, arrlen, period)) | |
3216 | break; | |
3217 | ||
3218 | /* There's a repeated pattern */ | |
3219 | if (period < arrlen) | |
3220 | return period; | |
3221 | ||
3222 | /* There are trailing zeros */ | |
3223 | if (last_nonzero < arrlen - 1) | |
3224 | return last_nonzero + 1; | |
3225 | ||
3226 | /* No pattern detected */ | |
3227 | return arrlen; | |
3228 | } | |
3229 | ||
7db906b7 HS |
3230 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3231 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3232 | { | |
3233 | int bits; | |
3234 | ||
3235 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3236 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3237 | return bits + 1; | |
3238 | } | |
3239 | ||
fc09bbc0 BN |
3240 | /* |
3241 | * Many new NAND share similar device ID codes, which represent the size of the | |
3242 | * chip. The rest of the parameters must be decoded according to generic or | |
3243 | * manufacturer-specific "extended ID" decoding patterns. | |
3244 | */ | |
3245 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3246 | u8 id_data[8], int *busw) | |
3247 | { | |
e3b88bd6 | 3248 | int extid, id_len; |
fc09bbc0 | 3249 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3250 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3251 | /* The 4th id byte is the important one */ |
3252 | extid = id_data[3]; | |
3253 | ||
e3b88bd6 BN |
3254 | id_len = nand_id_len(id_data, 8); |
3255 | ||
fc09bbc0 BN |
3256 | /* |
3257 | * Field definitions are in the following datasheets: | |
3258 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 3259 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 3260 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 3261 | * |
af451af4 BN |
3262 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3263 | * ID to decide what to do. | |
fc09bbc0 | 3264 | */ |
af451af4 | 3265 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
1d0ed69d | 3266 | !nand_is_slc(chip) && id_data[5] != 0x00) { |
fc09bbc0 BN |
3267 | /* Calc pagesize */ |
3268 | mtd->writesize = 2048 << (extid & 0x03); | |
3269 | extid >>= 2; | |
3270 | /* Calc oobsize */ | |
e2d3a35e | 3271 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3272 | case 1: |
3273 | mtd->oobsize = 128; | |
3274 | break; | |
3275 | case 2: | |
3276 | mtd->oobsize = 218; | |
3277 | break; | |
3278 | case 3: | |
3279 | mtd->oobsize = 400; | |
3280 | break; | |
e2d3a35e | 3281 | case 4: |
fc09bbc0 BN |
3282 | mtd->oobsize = 436; |
3283 | break; | |
e2d3a35e BN |
3284 | case 5: |
3285 | mtd->oobsize = 512; | |
3286 | break; | |
3287 | case 6: | |
3288 | default: /* Other cases are "reserved" (unknown) */ | |
3289 | mtd->oobsize = 640; | |
3290 | break; | |
fc09bbc0 BN |
3291 | } |
3292 | extid >>= 2; | |
3293 | /* Calc blocksize */ | |
3294 | mtd->erasesize = (128 * 1024) << | |
3295 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3296 | *busw = 0; | |
73ca392f | 3297 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
1d0ed69d | 3298 | !nand_is_slc(chip)) { |
73ca392f BN |
3299 | unsigned int tmp; |
3300 | ||
3301 | /* Calc pagesize */ | |
3302 | mtd->writesize = 2048 << (extid & 0x03); | |
3303 | extid >>= 2; | |
3304 | /* Calc oobsize */ | |
3305 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3306 | case 0: | |
3307 | mtd->oobsize = 128; | |
3308 | break; | |
3309 | case 1: | |
3310 | mtd->oobsize = 224; | |
3311 | break; | |
3312 | case 2: | |
3313 | mtd->oobsize = 448; | |
3314 | break; | |
3315 | case 3: | |
3316 | mtd->oobsize = 64; | |
3317 | break; | |
3318 | case 4: | |
3319 | mtd->oobsize = 32; | |
3320 | break; | |
3321 | case 5: | |
3322 | mtd->oobsize = 16; | |
3323 | break; | |
3324 | default: | |
3325 | mtd->oobsize = 640; | |
3326 | break; | |
3327 | } | |
3328 | extid >>= 2; | |
3329 | /* Calc blocksize */ | |
3330 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3331 | if (tmp < 0x03) | |
3332 | mtd->erasesize = (128 * 1024) << tmp; | |
3333 | else if (tmp == 0x03) | |
3334 | mtd->erasesize = 768 * 1024; | |
3335 | else | |
3336 | mtd->erasesize = (64 * 1024) << tmp; | |
3337 | *busw = 0; | |
fc09bbc0 BN |
3338 | } else { |
3339 | /* Calc pagesize */ | |
3340 | mtd->writesize = 1024 << (extid & 0x03); | |
3341 | extid >>= 2; | |
3342 | /* Calc oobsize */ | |
3343 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3344 | (mtd->writesize >> 9); | |
3345 | extid >>= 2; | |
3346 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3347 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3348 | extid >>= 2; | |
3349 | /* Get buswidth information */ | |
3350 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
60c67382 BN |
3351 | |
3352 | /* | |
3353 | * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per | |
3354 | * 512B page. For Toshiba SLC, we decode the 5th/6th byte as | |
3355 | * follows: | |
3356 | * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, | |
3357 | * 110b -> 24nm | |
3358 | * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC | |
3359 | */ | |
3360 | if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && | |
1d0ed69d | 3361 | nand_is_slc(chip) && |
60c67382 BN |
3362 | (id_data[5] & 0x7) == 0x6 /* 24nm */ && |
3363 | !(id_data[4] & 0x80) /* !BENAND */) { | |
3364 | mtd->oobsize = 32 * mtd->writesize >> 9; | |
3365 | } | |
3366 | ||
fc09bbc0 BN |
3367 | } |
3368 | } | |
3369 | ||
f23a481c BN |
3370 | /* |
3371 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3372 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3373 | * the chip. | |
3374 | */ | |
3375 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3376 | struct nand_flash_dev *type, u8 id_data[8], | |
3377 | int *busw) | |
3378 | { | |
3379 | int maf_id = id_data[0]; | |
3380 | ||
3381 | mtd->erasesize = type->erasesize; | |
3382 | mtd->writesize = type->pagesize; | |
3383 | mtd->oobsize = mtd->writesize / 32; | |
3384 | *busw = type->options & NAND_BUSWIDTH_16; | |
3385 | ||
1c195e90 HS |
3386 | /* All legacy ID NAND are small-page, SLC */ |
3387 | chip->bits_per_cell = 1; | |
3388 | ||
f23a481c BN |
3389 | /* |
3390 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3391 | * some Spansion chips have erasesize that conflicts with size | |
3392 | * listed in nand_ids table. | |
3393 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3394 | */ | |
3395 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3396 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3397 | && mtd->writesize == 512) { | |
3398 | mtd->erasesize = 128 * 1024; | |
3399 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3400 | } | |
3401 | } | |
3402 | ||
7e74c2d7 BN |
3403 | /* |
3404 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3405 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3406 | * page size, cell-type information). | |
3407 | */ | |
3408 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3409 | struct nand_chip *chip, u8 id_data[8]) | |
3410 | { | |
3411 | int maf_id = id_data[0]; | |
3412 | ||
3413 | /* Set the bad block position */ | |
3414 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3415 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3416 | else | |
3417 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3418 | ||
3419 | /* | |
3420 | * Bad block marker is stored in the last page of each block on Samsung | |
3421 | * and Hynix MLC devices; stored in first two pages of each block on | |
3422 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3423 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3424 | */ | |
1d0ed69d | 3425 | if (!nand_is_slc(chip) && |
7e74c2d7 BN |
3426 | (maf_id == NAND_MFR_SAMSUNG || |
3427 | maf_id == NAND_MFR_HYNIX)) | |
3428 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
1d0ed69d | 3429 | else if ((nand_is_slc(chip) && |
7e74c2d7 BN |
3430 | (maf_id == NAND_MFR_SAMSUNG || |
3431 | maf_id == NAND_MFR_HYNIX || | |
3432 | maf_id == NAND_MFR_TOSHIBA || | |
3433 | maf_id == NAND_MFR_AMD || | |
3434 | maf_id == NAND_MFR_MACRONIX)) || | |
3435 | (mtd->writesize == 2048 && | |
3436 | maf_id == NAND_MFR_MICRON)) | |
3437 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3438 | } | |
3439 | ||
ec6e87e3 HS |
3440 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3441 | { | |
3442 | return type->id_len; | |
3443 | } | |
3444 | ||
3445 | static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, | |
3446 | struct nand_flash_dev *type, u8 *id_data, int *busw) | |
3447 | { | |
3448 | if (!strncmp(type->id, id_data, type->id_len)) { | |
3449 | mtd->writesize = type->pagesize; | |
3450 | mtd->erasesize = type->erasesize; | |
3451 | mtd->oobsize = type->oobsize; | |
3452 | ||
7db906b7 | 3453 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3454 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3455 | chip->options |= type->options; | |
57219342 HS |
3456 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3457 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
ec6e87e3 HS |
3458 | |
3459 | *busw = type->options & NAND_BUSWIDTH_16; | |
3460 | ||
092b6a1d CZ |
3461 | if (!mtd->name) |
3462 | mtd->name = type->name; | |
3463 | ||
ec6e87e3 HS |
3464 | return true; |
3465 | } | |
3466 | return false; | |
3467 | } | |
3468 | ||
7aa65bfd | 3469 | /* |
8b6e50c9 | 3470 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3471 | */ |
3472 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3473 | struct nand_chip *chip, |
7351d3a5 FF |
3474 | int busw, |
3475 | int *maf_id, int *dev_id, | |
5e81e88a | 3476 | struct nand_flash_dev *type) |
7aa65bfd | 3477 | { |
d1e1f4e4 | 3478 | int i, maf_idx; |
426c457a | 3479 | u8 id_data[8]; |
1da177e4 LT |
3480 | |
3481 | /* Select the device */ | |
ace4dfee | 3482 | chip->select_chip(mtd, 0); |
1da177e4 | 3483 | |
ef89a880 KB |
3484 | /* |
3485 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3486 | * after power-up. |
ef89a880 KB |
3487 | */ |
3488 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3489 | ||
1da177e4 | 3490 | /* Send the command for reading device ID */ |
ace4dfee | 3491 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3492 | |
3493 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3494 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3495 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3496 | |
8b6e50c9 BN |
3497 | /* |
3498 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3499 | * interface concerns can cause random data which looks like a |
3500 | * possibly credible NAND flash to appear. If the two results do | |
3501 | * not match, ignore the device completely. | |
3502 | */ | |
3503 | ||
3504 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3505 | ||
4aef9b78 BN |
3506 | /* Read entire ID string */ |
3507 | for (i = 0; i < 8; i++) | |
426c457a | 3508 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3509 | |
d1e1f4e4 | 3510 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
20171642 | 3511 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
d0370219 | 3512 | *maf_id, *dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
3513 | return ERR_PTR(-ENODEV); |
3514 | } | |
3515 | ||
7aa65bfd | 3516 | if (!type) |
5e81e88a DW |
3517 | type = nand_flash_ids; |
3518 | ||
ec6e87e3 HS |
3519 | for (; type->name != NULL; type++) { |
3520 | if (is_full_id_nand(type)) { | |
3521 | if (find_full_id_nand(mtd, chip, type, id_data, &busw)) | |
3522 | goto ident_done; | |
3523 | } else if (*dev_id == type->dev_id) { | |
3524 | break; | |
3525 | } | |
3526 | } | |
5e81e88a | 3527 | |
d1e1f4e4 FF |
3528 | chip->onfi_version = 0; |
3529 | if (!type->name || !type->pagesize) { | |
6fb277ba | 3530 | /* Check is chip is ONFI compliant */ |
47450b35 | 3531 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3532 | goto ident_done; |
d1e1f4e4 FF |
3533 | } |
3534 | ||
5e81e88a | 3535 | if (!type->name) |
7aa65bfd TG |
3536 | return ERR_PTR(-ENODEV); |
3537 | ||
ba0251fe TG |
3538 | if (!mtd->name) |
3539 | mtd->name = type->name; | |
3540 | ||
69423d99 | 3541 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3542 | |
12a40a57 | 3543 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 3544 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
3545 | busw = chip->init_size(mtd, chip, id_data); |
3546 | } else if (!type->pagesize) { | |
fc09bbc0 BN |
3547 | /* Decode parameters from extended ID */ |
3548 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3549 | } else { |
f23a481c | 3550 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3551 | } |
bf7a01bf BN |
3552 | /* Get chip options */ |
3553 | chip->options |= type->options; | |
d1e1f4e4 | 3554 | |
8b6e50c9 BN |
3555 | /* |
3556 | * Check if chip is not a Samsung device. Do not clear the | |
3557 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3558 | */ |
3559 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3560 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3561 | ident_done: | |
3562 | ||
7aa65bfd | 3563 | /* Try to identify manufacturer */ |
9a909867 | 3564 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3565 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3566 | break; | |
3567 | } | |
0ea4a755 | 3568 | |
64b37b2a MC |
3569 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
3570 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
3571 | chip->options |= busw; | |
3572 | nand_set_defaults(chip, busw); | |
3573 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { | |
3574 | /* | |
3575 | * Check, if buswidth is correct. Hardware drivers should set | |
3576 | * chip correct! | |
3577 | */ | |
20171642 EG |
3578 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3579 | *maf_id, *dev_id); | |
3580 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); | |
3581 | pr_warn("bus width %d instead %d bit\n", | |
d0370219 BN |
3582 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3583 | busw ? 16 : 8); | |
7aa65bfd TG |
3584 | return ERR_PTR(-EINVAL); |
3585 | } | |
61b03bd7 | 3586 | |
7e74c2d7 BN |
3587 | nand_decode_bbm_options(mtd, chip, id_data); |
3588 | ||
7aa65bfd | 3589 | /* Calculate the address shift from the page size */ |
ace4dfee | 3590 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3591 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3592 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3593 | |
ace4dfee | 3594 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3595 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3596 | if (chip->chipsize & 0xffffffff) |
3597 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3598 | else { |
3599 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3600 | chip->chip_shift += 32 - 1; | |
3601 | } | |
1da177e4 | 3602 | |
26d9be11 | 3603 | chip->badblockbits = 8; |
14c65786 | 3604 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd | 3605 | |
8b6e50c9 | 3606 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3607 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3608 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3609 | |
20171642 EG |
3610 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3611 | *maf_id, *dev_id); | |
3612 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3723e93c | 3613 | chip->onfi_version ? chip->onfi_params.model : type->name); |
20171642 | 3614 | pr_info("%dMiB, %s, page size: %d, OOB size: %d\n", |
3723e93c HS |
3615 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3616 | mtd->writesize, mtd->oobsize); | |
7aa65bfd TG |
3617 | return type; |
3618 | } | |
3619 | ||
7aa65bfd | 3620 | /** |
3b85c321 | 3621 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3622 | * @mtd: MTD device structure |
3623 | * @maxchips: number of chips to scan for | |
3624 | * @table: alternative NAND ID table | |
7aa65bfd | 3625 | * |
8b6e50c9 BN |
3626 | * This is the first phase of the normal nand_scan() function. It reads the |
3627 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3628 | * |
3b85c321 | 3629 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3630 | */ |
5e81e88a DW |
3631 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3632 | struct nand_flash_dev *table) | |
7aa65bfd | 3633 | { |
d1e1f4e4 | 3634 | int i, busw, nand_maf_id, nand_dev_id; |
ace4dfee | 3635 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3636 | struct nand_flash_dev *type; |
3637 | ||
7aa65bfd | 3638 | /* Get buswidth to select the correct functions */ |
ace4dfee | 3639 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 3640 | /* Set the default functions */ |
ace4dfee | 3641 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
3642 | |
3643 | /* Read the flash type */ | |
7351d3a5 FF |
3644 | type = nand_get_flash_type(mtd, chip, busw, |
3645 | &nand_maf_id, &nand_dev_id, table); | |
7aa65bfd TG |
3646 | |
3647 | if (IS_ERR(type)) { | |
b1c6e6db | 3648 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3649 | pr_warn("No NAND device found\n"); |
ace4dfee | 3650 | chip->select_chip(mtd, -1); |
7aa65bfd | 3651 | return PTR_ERR(type); |
1da177e4 LT |
3652 | } |
3653 | ||
07300164 HS |
3654 | chip->select_chip(mtd, -1); |
3655 | ||
7aa65bfd | 3656 | /* Check for a chip array */ |
e0c7d767 | 3657 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3658 | chip->select_chip(mtd, i); |
ef89a880 KB |
3659 | /* See comment in nand_get_flash_type for reset */ |
3660 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3661 | /* Send the command for reading device ID */ |
ace4dfee | 3662 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3663 | /* Read manufacturer and device IDs */ |
ace4dfee | 3664 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
3665 | nand_dev_id != chip->read_byte(mtd)) { |
3666 | chip->select_chip(mtd, -1); | |
1da177e4 | 3667 | break; |
07300164 HS |
3668 | } |
3669 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
3670 | } |
3671 | if (i > 1) | |
20171642 | 3672 | pr_info("%d chips detected\n", i); |
61b03bd7 | 3673 | |
1da177e4 | 3674 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3675 | chip->numchips = i; |
3676 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3677 | |
3b85c321 DW |
3678 | return 0; |
3679 | } | |
7351d3a5 | 3680 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 DW |
3681 | |
3682 | ||
3683 | /** | |
3684 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 3685 | * @mtd: MTD device structure |
3b85c321 | 3686 | * |
8b6e50c9 BN |
3687 | * This is the second phase of the normal nand_scan() function. It fills out |
3688 | * all the uninitialized function pointers with the defaults and scans for a | |
3689 | * bad block table if appropriate. | |
3b85c321 DW |
3690 | */ |
3691 | int nand_scan_tail(struct mtd_info *mtd) | |
3692 | { | |
3693 | int i; | |
3694 | struct nand_chip *chip = mtd->priv; | |
97de79e0 | 3695 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
3b85c321 | 3696 | |
e2414f4c BN |
3697 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
3698 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
3699 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
3700 | ||
4bf63fcb DW |
3701 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3702 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
3703 | if (!chip->buffers) | |
3704 | return -ENOMEM; | |
3705 | ||
7dcdcbef | 3706 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3707 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3708 | |
7aa65bfd | 3709 | /* |
8b6e50c9 | 3710 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 3711 | */ |
97de79e0 | 3712 | if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3713 | switch (mtd->oobsize) { |
1da177e4 | 3714 | case 8: |
97de79e0 | 3715 | ecc->layout = &nand_oob_8; |
1da177e4 LT |
3716 | break; |
3717 | case 16: | |
97de79e0 | 3718 | ecc->layout = &nand_oob_16; |
1da177e4 LT |
3719 | break; |
3720 | case 64: | |
97de79e0 | 3721 | ecc->layout = &nand_oob_64; |
1da177e4 | 3722 | break; |
81ec5364 | 3723 | case 128: |
97de79e0 | 3724 | ecc->layout = &nand_oob_128; |
81ec5364 | 3725 | break; |
1da177e4 | 3726 | default: |
d0370219 BN |
3727 | pr_warn("No oob scheme defined for oobsize %d\n", |
3728 | mtd->oobsize); | |
1da177e4 LT |
3729 | BUG(); |
3730 | } | |
3731 | } | |
61b03bd7 | 3732 | |
956e944c DW |
3733 | if (!chip->write_page) |
3734 | chip->write_page = nand_write_page; | |
3735 | ||
61b03bd7 | 3736 | /* |
8b6e50c9 | 3737 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 3738 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 3739 | */ |
956e944c | 3740 | |
97de79e0 | 3741 | switch (ecc->mode) { |
6e0cb135 SN |
3742 | case NAND_ECC_HW_OOB_FIRST: |
3743 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 3744 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
9a4d4d69 | 3745 | pr_warn("No ECC functions supplied; " |
d0370219 | 3746 | "hardware ECC not possible\n"); |
6e0cb135 SN |
3747 | BUG(); |
3748 | } | |
97de79e0 HS |
3749 | if (!ecc->read_page) |
3750 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 3751 | |
6dfc6d25 | 3752 | case NAND_ECC_HW: |
8b6e50c9 | 3753 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
3754 | if (!ecc->read_page) |
3755 | ecc->read_page = nand_read_page_hwecc; | |
3756 | if (!ecc->write_page) | |
3757 | ecc->write_page = nand_write_page_hwecc; | |
3758 | if (!ecc->read_page_raw) | |
3759 | ecc->read_page_raw = nand_read_page_raw; | |
3760 | if (!ecc->write_page_raw) | |
3761 | ecc->write_page_raw = nand_write_page_raw; | |
3762 | if (!ecc->read_oob) | |
3763 | ecc->read_oob = nand_read_oob_std; | |
3764 | if (!ecc->write_oob) | |
3765 | ecc->write_oob = nand_write_oob_std; | |
3766 | if (!ecc->read_subpage) | |
3767 | ecc->read_subpage = nand_read_subpage; | |
3768 | if (!ecc->write_subpage) | |
3769 | ecc->write_subpage = nand_write_subpage_hwecc; | |
f5bbdacc | 3770 | |
6dfc6d25 | 3771 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
3772 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
3773 | (!ecc->read_page || | |
3774 | ecc->read_page == nand_read_page_hwecc || | |
3775 | !ecc->write_page || | |
3776 | ecc->write_page == nand_write_page_hwecc)) { | |
9a4d4d69 | 3777 | pr_warn("No ECC functions supplied; " |
d0370219 | 3778 | "hardware ECC not possible\n"); |
6dfc6d25 TG |
3779 | BUG(); |
3780 | } | |
8b6e50c9 | 3781 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
3782 | if (!ecc->read_page) |
3783 | ecc->read_page = nand_read_page_syndrome; | |
3784 | if (!ecc->write_page) | |
3785 | ecc->write_page = nand_write_page_syndrome; | |
3786 | if (!ecc->read_page_raw) | |
3787 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
3788 | if (!ecc->write_page_raw) | |
3789 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
3790 | if (!ecc->read_oob) | |
3791 | ecc->read_oob = nand_read_oob_syndrome; | |
3792 | if (!ecc->write_oob) | |
3793 | ecc->write_oob = nand_write_oob_syndrome; | |
3794 | ||
3795 | if (mtd->writesize >= ecc->size) { | |
3796 | if (!ecc->strength) { | |
e2788c98 MD |
3797 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); |
3798 | BUG(); | |
3799 | } | |
6dfc6d25 | 3800 | break; |
e2788c98 | 3801 | } |
9a4d4d69 | 3802 | pr_warn("%d byte HW ECC not possible on " |
d0370219 | 3803 | "%d byte page size, fallback to SW ECC\n", |
97de79e0 HS |
3804 | ecc->size, mtd->writesize); |
3805 | ecc->mode = NAND_ECC_SOFT; | |
61b03bd7 | 3806 | |
6dfc6d25 | 3807 | case NAND_ECC_SOFT: |
97de79e0 HS |
3808 | ecc->calculate = nand_calculate_ecc; |
3809 | ecc->correct = nand_correct_data; | |
3810 | ecc->read_page = nand_read_page_swecc; | |
3811 | ecc->read_subpage = nand_read_subpage; | |
3812 | ecc->write_page = nand_write_page_swecc; | |
3813 | ecc->read_page_raw = nand_read_page_raw; | |
3814 | ecc->write_page_raw = nand_write_page_raw; | |
3815 | ecc->read_oob = nand_read_oob_std; | |
3816 | ecc->write_oob = nand_write_oob_std; | |
3817 | if (!ecc->size) | |
3818 | ecc->size = 256; | |
3819 | ecc->bytes = 3; | |
3820 | ecc->strength = 1; | |
1da177e4 | 3821 | break; |
61b03bd7 | 3822 | |
193bd400 ID |
3823 | case NAND_ECC_SOFT_BCH: |
3824 | if (!mtd_nand_has_bch()) { | |
9a4d4d69 | 3825 | pr_warn("CONFIG_MTD_ECC_BCH not enabled\n"); |
193bd400 ID |
3826 | BUG(); |
3827 | } | |
97de79e0 HS |
3828 | ecc->calculate = nand_bch_calculate_ecc; |
3829 | ecc->correct = nand_bch_correct_data; | |
3830 | ecc->read_page = nand_read_page_swecc; | |
3831 | ecc->read_subpage = nand_read_subpage; | |
3832 | ecc->write_page = nand_write_page_swecc; | |
3833 | ecc->read_page_raw = nand_read_page_raw; | |
3834 | ecc->write_page_raw = nand_write_page_raw; | |
3835 | ecc->read_oob = nand_read_oob_std; | |
3836 | ecc->write_oob = nand_write_oob_std; | |
193bd400 ID |
3837 | /* |
3838 | * Board driver should supply ecc.size and ecc.bytes values to | |
3839 | * select how many bits are correctable; see nand_bch_init() | |
8b6e50c9 BN |
3840 | * for details. Otherwise, default to 4 bits for large page |
3841 | * devices. | |
193bd400 | 3842 | */ |
97de79e0 HS |
3843 | if (!ecc->size && (mtd->oobsize >= 64)) { |
3844 | ecc->size = 512; | |
3845 | ecc->bytes = 7; | |
193bd400 | 3846 | } |
97de79e0 HS |
3847 | ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, |
3848 | &ecc->layout); | |
3849 | if (!ecc->priv) { | |
9a4d4d69 | 3850 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
3851 | BUG(); |
3852 | } | |
97de79e0 | 3853 | ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size); |
193bd400 ID |
3854 | break; |
3855 | ||
61b03bd7 | 3856 | case NAND_ECC_NONE: |
9a4d4d69 | 3857 | pr_warn("NAND_ECC_NONE selected by board driver. " |
d0370219 | 3858 | "This is not recommended!\n"); |
97de79e0 HS |
3859 | ecc->read_page = nand_read_page_raw; |
3860 | ecc->write_page = nand_write_page_raw; | |
3861 | ecc->read_oob = nand_read_oob_std; | |
3862 | ecc->read_page_raw = nand_read_page_raw; | |
3863 | ecc->write_page_raw = nand_write_page_raw; | |
3864 | ecc->write_oob = nand_write_oob_std; | |
3865 | ecc->size = mtd->writesize; | |
3866 | ecc->bytes = 0; | |
3867 | ecc->strength = 0; | |
1da177e4 | 3868 | break; |
956e944c | 3869 | |
1da177e4 | 3870 | default: |
97de79e0 | 3871 | pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); |
61b03bd7 | 3872 | BUG(); |
1da177e4 | 3873 | } |
61b03bd7 | 3874 | |
9ce244b3 | 3875 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
3876 | if (!ecc->read_oob_raw) |
3877 | ecc->read_oob_raw = ecc->read_oob; | |
3878 | if (!ecc->write_oob_raw) | |
3879 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 3880 | |
5bd34c09 TG |
3881 | /* |
3882 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 3883 | * the out of band area. |
5bd34c09 | 3884 | */ |
97de79e0 HS |
3885 | ecc->layout->oobavail = 0; |
3886 | for (i = 0; ecc->layout->oobfree[i].length | |
3887 | && i < ARRAY_SIZE(ecc->layout->oobfree); i++) | |
3888 | ecc->layout->oobavail += ecc->layout->oobfree[i].length; | |
3889 | mtd->oobavail = ecc->layout->oobavail; | |
5bd34c09 | 3890 | |
7aa65bfd TG |
3891 | /* |
3892 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 3893 | * mode. |
7aa65bfd | 3894 | */ |
97de79e0 HS |
3895 | ecc->steps = mtd->writesize / ecc->size; |
3896 | if (ecc->steps * ecc->size != mtd->writesize) { | |
9a4d4d69 | 3897 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 3898 | BUG(); |
1da177e4 | 3899 | } |
97de79e0 | 3900 | ecc->total = ecc->steps * ecc->bytes; |
61b03bd7 | 3901 | |
8b6e50c9 | 3902 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 3903 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 3904 | switch (ecc->steps) { |
29072b96 TG |
3905 | case 2: |
3906 | mtd->subpage_sft = 1; | |
3907 | break; | |
3908 | case 4: | |
3909 | case 8: | |
81ec5364 | 3910 | case 16: |
29072b96 TG |
3911 | mtd->subpage_sft = 2; |
3912 | break; | |
3913 | } | |
3914 | } | |
3915 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
3916 | ||
04bbd0ea | 3917 | /* Initialize state */ |
ace4dfee | 3918 | chip->state = FL_READY; |
1da177e4 | 3919 | |
1da177e4 | 3920 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 3921 | chip->pagebuf = -1; |
1da177e4 | 3922 | |
a5ff4f10 | 3923 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
97de79e0 | 3924 | if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9)) |
a5ff4f10 JW |
3925 | chip->options |= NAND_SUBPAGE_READ; |
3926 | ||
1da177e4 | 3927 | /* Fill in remaining MTD driver data */ |
963d1c28 | 3928 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
3929 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
3930 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
3931 | mtd->_erase = nand_erase; |
3932 | mtd->_point = NULL; | |
3933 | mtd->_unpoint = NULL; | |
3934 | mtd->_read = nand_read; | |
3935 | mtd->_write = nand_write; | |
3936 | mtd->_panic_write = panic_nand_write; | |
3937 | mtd->_read_oob = nand_read_oob; | |
3938 | mtd->_write_oob = nand_write_oob; | |
3939 | mtd->_sync = nand_sync; | |
3940 | mtd->_lock = NULL; | |
3941 | mtd->_unlock = NULL; | |
3942 | mtd->_suspend = nand_suspend; | |
3943 | mtd->_resume = nand_resume; | |
3944 | mtd->_block_isbad = nand_block_isbad; | |
3945 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 3946 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 3947 | |
6a918bad | 3948 | /* propagate ecc info to mtd_info */ |
97de79e0 HS |
3949 | mtd->ecclayout = ecc->layout; |
3950 | mtd->ecc_strength = ecc->strength; | |
3951 | mtd->ecc_step_size = ecc->size; | |
ea3b2ea2 SL |
3952 | /* |
3953 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
3954 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
3955 | * properly set. | |
3956 | */ | |
3957 | if (!mtd->bitflip_threshold) | |
3958 | mtd->bitflip_threshold = mtd->ecc_strength; | |
1da177e4 | 3959 | |
0040bf38 | 3960 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 3961 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 3962 | return 0; |
1da177e4 LT |
3963 | |
3964 | /* Build bad block table */ | |
ace4dfee | 3965 | return chip->scan_bbt(mtd); |
1da177e4 | 3966 | } |
7351d3a5 | 3967 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 3968 | |
8b6e50c9 BN |
3969 | /* |
3970 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 3971 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
3972 | * to call us from in-kernel code if the core NAND support is modular. |
3973 | */ | |
3b85c321 DW |
3974 | #ifdef MODULE |
3975 | #define caller_is_module() (1) | |
3976 | #else | |
3977 | #define caller_is_module() \ | |
a6e6abd5 | 3978 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
3979 | #endif |
3980 | ||
3981 | /** | |
3982 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
3983 | * @mtd: MTD device structure |
3984 | * @maxchips: number of chips to scan for | |
3b85c321 | 3985 | * |
8b6e50c9 BN |
3986 | * This fills out all the uninitialized function pointers with the defaults. |
3987 | * The flash ID is read and the mtd/chip structures are filled with the | |
3988 | * appropriate values. The mtd->owner field must be set to the module of the | |
3989 | * caller. | |
3b85c321 DW |
3990 | */ |
3991 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
3992 | { | |
3993 | int ret; | |
3994 | ||
3995 | /* Many callers got this wrong, so check for it for a while... */ | |
3996 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 3997 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
3998 | BUG(); |
3999 | } | |
4000 | ||
5e81e88a | 4001 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
4002 | if (!ret) |
4003 | ret = nand_scan_tail(mtd); | |
4004 | return ret; | |
4005 | } | |
7351d3a5 | 4006 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 4007 | |
1da177e4 | 4008 | /** |
61b03bd7 | 4009 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
4010 | * @mtd: MTD device structure |
4011 | */ | |
e0c7d767 | 4012 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 4013 | { |
ace4dfee | 4014 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 4015 | |
193bd400 ID |
4016 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
4017 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
4018 | ||
5ffcaf3d | 4019 | mtd_device_unregister(mtd); |
1da177e4 | 4020 | |
fa671646 | 4021 | /* Free bad block table memory */ |
ace4dfee | 4022 | kfree(chip->bbt); |
4bf63fcb DW |
4023 | if (!(chip->options & NAND_OWN_BUFFERS)) |
4024 | kfree(chip->buffers); | |
58373ff0 BN |
4025 | |
4026 | /* Free bad block descriptor memory */ | |
4027 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
4028 | & NAND_BBT_DYNAMICSTRUCT) | |
4029 | kfree(chip->badblock_pattern); | |
1da177e4 | 4030 | } |
e0c7d767 | 4031 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
4032 | |
4033 | static int __init nand_base_init(void) | |
4034 | { | |
4035 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
4036 | return 0; | |
4037 | } | |
4038 | ||
4039 | static void __exit nand_base_exit(void) | |
4040 | { | |
4041 | led_trigger_unregister_simple(nand_led_trigger); | |
4042 | } | |
4043 | ||
4044 | module_init(nand_base_init); | |
4045 | module_exit(nand_base_exit); | |
4046 | ||
e0c7d767 | 4047 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
4048 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
4049 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 4050 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |