Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 7 | * |
1da177e4 | 8 | * Additional technical information is available on |
8b2b403c | 9 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 10 | * |
1da177e4 | 11 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 12 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 13 | * |
ace4dfee | 14 | * Credits: |
61b03bd7 TG |
15 | * David Woodhouse for adding multichip support |
16 | * | |
1da177e4 LT |
17 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
18 | * rework for 2K page size chips | |
19 | * | |
ace4dfee | 20 | * TODO: |
1da177e4 LT |
21 | * Enable cached programming for 2k page size chips |
22 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 23 | * if we have HW ECC support. |
c0b8ba7b | 24 | * BBT table is not serialized, has to be fixed |
1da177e4 | 25 | * |
1da177e4 LT |
26 | * This program is free software; you can redistribute it and/or modify |
27 | * it under the terms of the GNU General Public License version 2 as | |
28 | * published by the Free Software Foundation. | |
29 | * | |
30 | */ | |
31 | ||
20171642 EG |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
552d9205 | 34 | #include <linux/module.h> |
1da177e4 LT |
35 | #include <linux/delay.h> |
36 | #include <linux/errno.h> | |
7aa65bfd | 37 | #include <linux/err.h> |
1da177e4 LT |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
66507c7b | 40 | #include <linux/mm.h> |
1da177e4 LT |
41 | #include <linux/types.h> |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 45 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
46 | #include <linux/interrupt.h> |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
7351d3a5 | 49 | #include <linux/io.h> |
1da177e4 | 50 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
51 | |
52 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 53 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
54 | .eccbytes = 3, |
55 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
56 | .oobfree = { |
57 | {.offset = 3, | |
58 | .length = 2}, | |
59 | {.offset = 6, | |
f8ac0414 | 60 | .length = 2} } |
1da177e4 LT |
61 | }; |
62 | ||
5bd34c09 | 63 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
64 | .eccbytes = 6, |
65 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
66 | .oobfree = { |
67 | {.offset = 8, | |
f8ac0414 | 68 | . length = 8} } |
1da177e4 LT |
69 | }; |
70 | ||
5bd34c09 | 71 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
72 | .eccbytes = 24, |
73 | .eccpos = { | |
e0c7d767 DW |
74 | 40, 41, 42, 43, 44, 45, 46, 47, |
75 | 48, 49, 50, 51, 52, 53, 54, 55, | |
76 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
77 | .oobfree = { |
78 | {.offset = 2, | |
f8ac0414 | 79 | .length = 38} } |
1da177e4 LT |
80 | }; |
81 | ||
81ec5364 TG |
82 | static struct nand_ecclayout nand_oob_128 = { |
83 | .eccbytes = 48, | |
84 | .eccpos = { | |
85 | 80, 81, 82, 83, 84, 85, 86, 87, | |
86 | 88, 89, 90, 91, 92, 93, 94, 95, | |
87 | 96, 97, 98, 99, 100, 101, 102, 103, | |
88 | 104, 105, 106, 107, 108, 109, 110, 111, | |
89 | 112, 113, 114, 115, 116, 117, 118, 119, | |
90 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
91 | .oobfree = { | |
92 | {.offset = 2, | |
f8ac0414 | 93 | .length = 78} } |
81ec5364 TG |
94 | }; |
95 | ||
6a8214aa | 96 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
1da177e4 | 97 | |
8593fbc6 TG |
98 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
99 | struct mtd_oob_ops *ops); | |
100 | ||
d470a97c | 101 | /* |
8e87d782 | 102 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
103 | * compiled away when LED support is disabled. |
104 | */ | |
105 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
106 | ||
6fe5a6ac VS |
107 | static int check_offs_len(struct mtd_info *mtd, |
108 | loff_t ofs, uint64_t len) | |
109 | { | |
110 | struct nand_chip *chip = mtd->priv; | |
111 | int ret = 0; | |
112 | ||
113 | /* Start address must align on block boundary */ | |
daae74ca | 114 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 115 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
116 | ret = -EINVAL; |
117 | } | |
118 | ||
119 | /* Length must align on block boundary */ | |
daae74ca | 120 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 121 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
122 | ret = -EINVAL; |
123 | } | |
124 | ||
6fe5a6ac VS |
125 | return ret; |
126 | } | |
127 | ||
1da177e4 LT |
128 | /** |
129 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 130 | * @mtd: MTD device structure |
61b03bd7 | 131 | * |
b0bb6903 | 132 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 133 | */ |
e0c7d767 | 134 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 135 | { |
ace4dfee | 136 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 137 | |
a36ed299 | 138 | /* Release the controller and the chip */ |
ace4dfee TG |
139 | spin_lock(&chip->controller->lock); |
140 | chip->controller->active = NULL; | |
141 | chip->state = FL_READY; | |
142 | wake_up(&chip->controller->wq); | |
143 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
144 | } |
145 | ||
146 | /** | |
147 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 148 | * @mtd: MTD device structure |
1da177e4 | 149 | * |
7854d3f7 | 150 | * Default read function for 8bit buswidth |
1da177e4 | 151 | */ |
58dd8f2b | 152 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 153 | { |
ace4dfee TG |
154 | struct nand_chip *chip = mtd->priv; |
155 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
156 | } |
157 | ||
1da177e4 | 158 | /** |
7854d3f7 | 159 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 160 | * @mtd: MTD device structure |
1da177e4 | 161 | * |
7854d3f7 BN |
162 | * Default read function for 16bit buswidth with endianness conversion. |
163 | * | |
1da177e4 | 164 | */ |
58dd8f2b | 165 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 166 | { |
ace4dfee TG |
167 | struct nand_chip *chip = mtd->priv; |
168 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
169 | } |
170 | ||
1da177e4 LT |
171 | /** |
172 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 173 | * @mtd: MTD device structure |
1da177e4 | 174 | * |
7854d3f7 | 175 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
176 | */ |
177 | static u16 nand_read_word(struct mtd_info *mtd) | |
178 | { | |
ace4dfee TG |
179 | struct nand_chip *chip = mtd->priv; |
180 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
181 | } |
182 | ||
1da177e4 LT |
183 | /** |
184 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
185 | * @mtd: MTD device structure |
186 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
187 | * |
188 | * Default select function for 1 chip devices. | |
189 | */ | |
ace4dfee | 190 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 191 | { |
ace4dfee TG |
192 | struct nand_chip *chip = mtd->priv; |
193 | ||
194 | switch (chipnr) { | |
1da177e4 | 195 | case -1: |
ace4dfee | 196 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
197 | break; |
198 | case 0: | |
1da177e4 LT |
199 | break; |
200 | ||
201 | default: | |
202 | BUG(); | |
203 | } | |
204 | } | |
205 | ||
05f78359 UKK |
206 | /** |
207 | * nand_write_byte - [DEFAULT] write single byte to chip | |
208 | * @mtd: MTD device structure | |
209 | * @byte: value to write | |
210 | * | |
211 | * Default function to write a byte to I/O[7:0] | |
212 | */ | |
213 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
214 | { | |
215 | struct nand_chip *chip = mtd->priv; | |
216 | ||
217 | chip->write_buf(mtd, &byte, 1); | |
218 | } | |
219 | ||
220 | /** | |
221 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
222 | * @mtd: MTD device structure | |
223 | * @byte: value to write | |
224 | * | |
225 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
226 | */ | |
227 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
228 | { | |
229 | struct nand_chip *chip = mtd->priv; | |
230 | uint16_t word = byte; | |
231 | ||
232 | /* | |
233 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
234 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
235 | * | |
236 | * When the host supports a 16-bit bus width, only data is | |
237 | * transferred at the 16-bit width. All address and command line | |
238 | * transfers shall use only the lower 8-bits of the data bus. During | |
239 | * command transfers, the host may place any value on the upper | |
240 | * 8-bits of the data bus. During address transfers, the host shall | |
241 | * set the upper 8-bits of the data bus to 00h. | |
242 | * | |
243 | * One user of the write_byte callback is nand_onfi_set_features. The | |
244 | * four parameters are specified to be written to I/O[7:0], but this is | |
245 | * neither an address nor a command transfer. Let's assume a 0 on the | |
246 | * upper I/O lines is OK. | |
247 | */ | |
248 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
249 | } | |
250 | ||
1da177e4 LT |
251 | /** |
252 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
253 | * @mtd: MTD device structure |
254 | * @buf: data buffer | |
255 | * @len: number of bytes to write | |
1da177e4 | 256 | * |
7854d3f7 | 257 | * Default write function for 8bit buswidth. |
1da177e4 | 258 | */ |
58dd8f2b | 259 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 260 | { |
ace4dfee | 261 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 262 | |
76413839 | 263 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
264 | } |
265 | ||
266 | /** | |
61b03bd7 | 267 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
268 | * @mtd: MTD device structure |
269 | * @buf: buffer to store date | |
270 | * @len: number of bytes to read | |
1da177e4 | 271 | * |
7854d3f7 | 272 | * Default read function for 8bit buswidth. |
1da177e4 | 273 | */ |
58dd8f2b | 274 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 275 | { |
ace4dfee | 276 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 277 | |
76413839 | 278 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
279 | } |
280 | ||
1da177e4 LT |
281 | /** |
282 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
283 | * @mtd: MTD device structure |
284 | * @buf: data buffer | |
285 | * @len: number of bytes to write | |
1da177e4 | 286 | * |
7854d3f7 | 287 | * Default write function for 16bit buswidth. |
1da177e4 | 288 | */ |
58dd8f2b | 289 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 290 | { |
ace4dfee | 291 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 292 | u16 *p = (u16 *) buf; |
61b03bd7 | 293 | |
76413839 | 294 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
295 | } |
296 | ||
297 | /** | |
61b03bd7 | 298 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
299 | * @mtd: MTD device structure |
300 | * @buf: buffer to store date | |
301 | * @len: number of bytes to read | |
1da177e4 | 302 | * |
7854d3f7 | 303 | * Default read function for 16bit buswidth. |
1da177e4 | 304 | */ |
58dd8f2b | 305 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 306 | { |
ace4dfee | 307 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 308 | u16 *p = (u16 *) buf; |
1da177e4 | 309 | |
76413839 | 310 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
311 | } |
312 | ||
1da177e4 LT |
313 | /** |
314 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
315 | * @mtd: MTD device structure |
316 | * @ofs: offset from device start | |
317 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 318 | * |
61b03bd7 | 319 | * Check, if the block is bad. |
1da177e4 LT |
320 | */ |
321 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
322 | { | |
cdbec050 | 323 | int page, chipnr, res = 0, i = 0; |
ace4dfee | 324 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
325 | u16 bad; |
326 | ||
5fb1549d | 327 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
328 | ofs += mtd->erasesize - mtd->writesize; |
329 | ||
1a12f46a TK |
330 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
331 | ||
1da177e4 | 332 | if (getchip) { |
ace4dfee | 333 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 334 | |
6a8214aa | 335 | nand_get_device(mtd, FL_READING); |
1da177e4 LT |
336 | |
337 | /* Select the NAND device */ | |
ace4dfee | 338 | chip->select_chip(mtd, chipnr); |
1a12f46a | 339 | } |
1da177e4 | 340 | |
cdbec050 BN |
341 | do { |
342 | if (chip->options & NAND_BUSWIDTH_16) { | |
343 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
344 | chip->badblockpos & 0xFE, page); | |
345 | bad = cpu_to_le16(chip->read_word(mtd)); | |
346 | if (chip->badblockpos & 0x1) | |
347 | bad >>= 8; | |
348 | else | |
349 | bad &= 0xFF; | |
350 | } else { | |
351 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
352 | page); | |
353 | bad = chip->read_byte(mtd); | |
354 | } | |
355 | ||
356 | if (likely(chip->badblockbits == 8)) | |
357 | res = bad != 0xFF; | |
e0b58d0a | 358 | else |
cdbec050 BN |
359 | res = hweight8(bad) < chip->badblockbits; |
360 | ofs += mtd->writesize; | |
361 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
362 | i++; | |
363 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 364 | |
b0bb6903 HS |
365 | if (getchip) { |
366 | chip->select_chip(mtd, -1); | |
1da177e4 | 367 | nand_release_device(mtd); |
b0bb6903 | 368 | } |
61b03bd7 | 369 | |
1da177e4 LT |
370 | return res; |
371 | } | |
372 | ||
373 | /** | |
5a0edb25 | 374 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
375 | * @mtd: MTD device structure |
376 | * @ofs: offset from device start | |
1da177e4 | 377 | * |
8b6e50c9 | 378 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
379 | * specific driver. It provides the details for writing a bad block marker to a |
380 | * block. | |
381 | */ | |
382 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
383 | { | |
384 | struct nand_chip *chip = mtd->priv; | |
385 | struct mtd_oob_ops ops; | |
386 | uint8_t buf[2] = { 0, 0 }; | |
387 | int ret = 0, res, i = 0; | |
388 | ||
389 | ops.datbuf = NULL; | |
390 | ops.oobbuf = buf; | |
391 | ops.ooboffs = chip->badblockpos; | |
392 | if (chip->options & NAND_BUSWIDTH_16) { | |
393 | ops.ooboffs &= ~0x01; | |
394 | ops.len = ops.ooblen = 2; | |
395 | } else { | |
396 | ops.len = ops.ooblen = 1; | |
397 | } | |
398 | ops.mode = MTD_OPS_PLACE_OOB; | |
399 | ||
400 | /* Write to first/last page(s) if necessary */ | |
401 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
402 | ofs += mtd->erasesize - mtd->writesize; | |
403 | do { | |
404 | res = nand_do_write_oob(mtd, ofs, &ops); | |
405 | if (!ret) | |
406 | ret = res; | |
407 | ||
408 | i++; | |
409 | ofs += mtd->writesize; | |
410 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
411 | ||
412 | return ret; | |
413 | } | |
414 | ||
415 | /** | |
416 | * nand_block_markbad_lowlevel - mark a block bad | |
417 | * @mtd: MTD device structure | |
418 | * @ofs: offset from device start | |
419 | * | |
420 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
421 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
422 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
423 | * | |
b32843b7 | 424 | * We try operations in the following order: |
e2414f4c | 425 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
426 | * (2) write bad block marker to OOB area of affected block (unless flag |
427 | * NAND_BBT_NO_OOB_BBM is present) | |
428 | * (3) update the BBT | |
429 | * Note that we retain the first error encountered in (2) or (3), finish the | |
e2414f4c | 430 | * procedures, and dump the error in the end. |
1da177e4 | 431 | */ |
5a0edb25 | 432 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 433 | { |
ace4dfee | 434 | struct nand_chip *chip = mtd->priv; |
b32843b7 | 435 | int res, ret = 0; |
61b03bd7 | 436 | |
b32843b7 | 437 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
438 | struct erase_info einfo; |
439 | ||
440 | /* Attempt erase before marking OOB */ | |
441 | memset(&einfo, 0, sizeof(einfo)); | |
442 | einfo.mtd = mtd; | |
443 | einfo.addr = ofs; | |
daae74ca | 444 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 445 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 446 | |
b32843b7 | 447 | /* Write bad block marker to OOB */ |
6a8214aa | 448 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 449 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 450 | nand_release_device(mtd); |
f1a28c02 | 451 | } |
e2414f4c | 452 | |
b32843b7 BN |
453 | /* Mark block bad in BBT */ |
454 | if (chip->bbt) { | |
455 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
456 | if (!ret) |
457 | ret = res; | |
458 | } | |
459 | ||
f1a28c02 TG |
460 | if (!ret) |
461 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 462 | |
f1a28c02 | 463 | return ret; |
1da177e4 LT |
464 | } |
465 | ||
61b03bd7 | 466 | /** |
1da177e4 | 467 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 468 | * @mtd: MTD device structure |
1da177e4 | 469 | * |
8b6e50c9 BN |
470 | * Check, if the device is write protected. The function expects, that the |
471 | * device is already selected. | |
1da177e4 | 472 | */ |
e0c7d767 | 473 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 474 | { |
ace4dfee | 475 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 476 | |
8b6e50c9 | 477 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
478 | if (chip->options & NAND_BROKEN_XD) |
479 | return 0; | |
480 | ||
1da177e4 | 481 | /* Check the WP bit */ |
ace4dfee TG |
482 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
483 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
484 | } |
485 | ||
8471bb73 | 486 | /** |
c30e1f79 | 487 | * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. |
8471bb73 EG |
488 | * @mtd: MTD device structure |
489 | * @ofs: offset from device start | |
490 | * | |
c30e1f79 | 491 | * Check if the block is marked as reserved. |
8471bb73 EG |
492 | */ |
493 | static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) | |
494 | { | |
495 | struct nand_chip *chip = mtd->priv; | |
496 | ||
497 | if (!chip->bbt) | |
498 | return 0; | |
499 | /* Return info from the table */ | |
500 | return nand_isreserved_bbt(mtd, ofs); | |
501 | } | |
502 | ||
1da177e4 LT |
503 | /** |
504 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
505 | * @mtd: MTD device structure |
506 | * @ofs: offset from device start | |
507 | * @getchip: 0, if the chip is already selected | |
508 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
509 | * |
510 | * Check, if the block is bad. Either by reading the bad block table or | |
511 | * calling of the scan function. | |
512 | */ | |
2c0a2bed TG |
513 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
514 | int allowbbt) | |
1da177e4 | 515 | { |
ace4dfee | 516 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 517 | |
ace4dfee TG |
518 | if (!chip->bbt) |
519 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 520 | |
1da177e4 | 521 | /* Return info from the table */ |
e0c7d767 | 522 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
523 | } |
524 | ||
2af7c653 SK |
525 | /** |
526 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
527 | * @mtd: MTD device structure |
528 | * @timeo: Timeout | |
2af7c653 SK |
529 | * |
530 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
531 | * context. | |
532 | */ | |
533 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
534 | { | |
535 | struct nand_chip *chip = mtd->priv; | |
536 | int i; | |
537 | ||
538 | /* Wait for the device to get ready */ | |
539 | for (i = 0; i < timeo; i++) { | |
540 | if (chip->dev_ready(mtd)) | |
541 | break; | |
542 | touch_softlockup_watchdog(); | |
543 | mdelay(1); | |
544 | } | |
545 | } | |
546 | ||
7854d3f7 | 547 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 548 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 549 | { |
ace4dfee | 550 | struct nand_chip *chip = mtd->priv; |
ca6a2489 | 551 | unsigned long timeo = jiffies + msecs_to_jiffies(20); |
3b88775c | 552 | |
2af7c653 SK |
553 | /* 400ms timeout */ |
554 | if (in_interrupt() || oops_in_progress) | |
555 | return panic_nand_wait_ready(mtd, 400); | |
556 | ||
8fe833c1 | 557 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 558 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 559 | do { |
ace4dfee | 560 | if (chip->dev_ready(mtd)) |
8fe833c1 | 561 | break; |
8446f1d3 | 562 | touch_softlockup_watchdog(); |
61b03bd7 | 563 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 564 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 565 | } |
4b648b02 | 566 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 567 | |
1da177e4 LT |
568 | /** |
569 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
570 | * @mtd: MTD device structure |
571 | * @command: the command to be sent | |
572 | * @column: the column address for this command, -1 if none | |
573 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 574 | * |
8b6e50c9 | 575 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 576 | * (512 Bytes per page). |
1da177e4 | 577 | */ |
7abd3ef9 TG |
578 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
579 | int column, int page_addr) | |
1da177e4 | 580 | { |
ace4dfee | 581 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 582 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 583 | |
8b6e50c9 | 584 | /* Write out the command to the device */ |
1da177e4 LT |
585 | if (command == NAND_CMD_SEQIN) { |
586 | int readcmd; | |
587 | ||
28318776 | 588 | if (column >= mtd->writesize) { |
1da177e4 | 589 | /* OOB area */ |
28318776 | 590 | column -= mtd->writesize; |
1da177e4 LT |
591 | readcmd = NAND_CMD_READOOB; |
592 | } else if (column < 256) { | |
593 | /* First 256 bytes --> READ0 */ | |
594 | readcmd = NAND_CMD_READ0; | |
595 | } else { | |
596 | column -= 256; | |
597 | readcmd = NAND_CMD_READ1; | |
598 | } | |
ace4dfee | 599 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 600 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 601 | } |
ace4dfee | 602 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 603 | |
8b6e50c9 | 604 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
605 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
606 | /* Serially input address */ | |
607 | if (column != -1) { | |
608 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
609 | if (chip->options & NAND_BUSWIDTH_16 && |
610 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 611 | column >>= 1; |
ace4dfee | 612 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
613 | ctrl &= ~NAND_CTRL_CHANGE; |
614 | } | |
615 | if (page_addr != -1) { | |
ace4dfee | 616 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 617 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 618 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 619 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
620 | if (chip->chipsize > (32 << 20)) |
621 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 622 | } |
ace4dfee | 623 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
624 | |
625 | /* | |
8b6e50c9 BN |
626 | * Program and erase have their own busy handlers status and sequential |
627 | * in needs no delay | |
e0c7d767 | 628 | */ |
1da177e4 | 629 | switch (command) { |
61b03bd7 | 630 | |
1da177e4 LT |
631 | case NAND_CMD_PAGEPROG: |
632 | case NAND_CMD_ERASE1: | |
633 | case NAND_CMD_ERASE2: | |
634 | case NAND_CMD_SEQIN: | |
635 | case NAND_CMD_STATUS: | |
636 | return; | |
637 | ||
638 | case NAND_CMD_RESET: | |
ace4dfee | 639 | if (chip->dev_ready) |
1da177e4 | 640 | break; |
ace4dfee TG |
641 | udelay(chip->chip_delay); |
642 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 643 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
644 | chip->cmd_ctrl(mtd, |
645 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
646 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
647 | ; | |
1da177e4 LT |
648 | return; |
649 | ||
e0c7d767 | 650 | /* This applies to read commands */ |
1da177e4 | 651 | default: |
61b03bd7 | 652 | /* |
1da177e4 LT |
653 | * If we don't have access to the busy pin, we apply the given |
654 | * command delay | |
e0c7d767 | 655 | */ |
ace4dfee TG |
656 | if (!chip->dev_ready) { |
657 | udelay(chip->chip_delay); | |
1da177e4 | 658 | return; |
61b03bd7 | 659 | } |
1da177e4 | 660 | } |
8b6e50c9 BN |
661 | /* |
662 | * Apply this short delay always to ensure that we do wait tWB in | |
663 | * any case on any machine. | |
664 | */ | |
e0c7d767 | 665 | ndelay(100); |
3b88775c TG |
666 | |
667 | nand_wait_ready(mtd); | |
1da177e4 LT |
668 | } |
669 | ||
670 | /** | |
671 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
672 | * @mtd: MTD device structure |
673 | * @command: the command to be sent | |
674 | * @column: the column address for this command, -1 if none | |
675 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 676 | * |
7abd3ef9 | 677 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
678 | * devices. We don't have the separate regions as we have in the small page |
679 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 680 | */ |
7abd3ef9 TG |
681 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
682 | int column, int page_addr) | |
1da177e4 | 683 | { |
ace4dfee | 684 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
685 | |
686 | /* Emulate NAND_CMD_READOOB */ | |
687 | if (command == NAND_CMD_READOOB) { | |
28318776 | 688 | column += mtd->writesize; |
1da177e4 LT |
689 | command = NAND_CMD_READ0; |
690 | } | |
61b03bd7 | 691 | |
7abd3ef9 | 692 | /* Command latch cycle */ |
fb066ada | 693 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
694 | |
695 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 696 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
697 | |
698 | /* Serially input address */ | |
699 | if (column != -1) { | |
700 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
701 | if (chip->options & NAND_BUSWIDTH_16 && |
702 | !nand_opcode_8bits(command)) | |
1da177e4 | 703 | column >>= 1; |
ace4dfee | 704 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 705 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 706 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 707 | } |
1da177e4 | 708 | if (page_addr != -1) { |
ace4dfee TG |
709 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
710 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 711 | NAND_NCE | NAND_ALE); |
1da177e4 | 712 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
713 | if (chip->chipsize > (128 << 20)) |
714 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 715 | NAND_NCE | NAND_ALE); |
1da177e4 | 716 | } |
1da177e4 | 717 | } |
ace4dfee | 718 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
719 | |
720 | /* | |
8b6e50c9 | 721 | * Program and erase have their own busy handlers status, sequential |
7a442f17 | 722 | * in and status need no delay. |
30f464b7 | 723 | */ |
1da177e4 | 724 | switch (command) { |
61b03bd7 | 725 | |
1da177e4 LT |
726 | case NAND_CMD_CACHEDPROG: |
727 | case NAND_CMD_PAGEPROG: | |
728 | case NAND_CMD_ERASE1: | |
729 | case NAND_CMD_ERASE2: | |
730 | case NAND_CMD_SEQIN: | |
7bc3312b | 731 | case NAND_CMD_RNDIN: |
1da177e4 | 732 | case NAND_CMD_STATUS: |
30f464b7 | 733 | return; |
1da177e4 LT |
734 | |
735 | case NAND_CMD_RESET: | |
ace4dfee | 736 | if (chip->dev_ready) |
1da177e4 | 737 | break; |
ace4dfee | 738 | udelay(chip->chip_delay); |
12efdde3 TG |
739 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
740 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
741 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
742 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
743 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
744 | ; | |
1da177e4 LT |
745 | return; |
746 | ||
7bc3312b TG |
747 | case NAND_CMD_RNDOUT: |
748 | /* No ready / busy check necessary */ | |
749 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
750 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
751 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
752 | NAND_NCE | NAND_CTRL_CHANGE); | |
753 | return; | |
754 | ||
1da177e4 | 755 | case NAND_CMD_READ0: |
12efdde3 TG |
756 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
757 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
758 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
759 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 760 | |
e0c7d767 | 761 | /* This applies to read commands */ |
1da177e4 | 762 | default: |
61b03bd7 | 763 | /* |
1da177e4 | 764 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 765 | * command delay. |
e0c7d767 | 766 | */ |
ace4dfee TG |
767 | if (!chip->dev_ready) { |
768 | udelay(chip->chip_delay); | |
1da177e4 | 769 | return; |
61b03bd7 | 770 | } |
1da177e4 | 771 | } |
3b88775c | 772 | |
8b6e50c9 BN |
773 | /* |
774 | * Apply this short delay always to ensure that we do wait tWB in | |
775 | * any case on any machine. | |
776 | */ | |
e0c7d767 | 777 | ndelay(100); |
3b88775c TG |
778 | |
779 | nand_wait_ready(mtd); | |
1da177e4 LT |
780 | } |
781 | ||
2af7c653 SK |
782 | /** |
783 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
784 | * @chip: the nand chip descriptor |
785 | * @mtd: MTD device structure | |
786 | * @new_state: the state which is requested | |
2af7c653 SK |
787 | * |
788 | * Used when in panic, no locks are taken. | |
789 | */ | |
790 | static void panic_nand_get_device(struct nand_chip *chip, | |
791 | struct mtd_info *mtd, int new_state) | |
792 | { | |
7854d3f7 | 793 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
794 | chip->controller->active = chip; |
795 | chip->state = new_state; | |
796 | } | |
797 | ||
1da177e4 LT |
798 | /** |
799 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
800 | * @mtd: MTD device structure |
801 | * @new_state: the state which is requested | |
1da177e4 LT |
802 | * |
803 | * Get the device and lock it for exclusive access | |
804 | */ | |
2c0a2bed | 805 | static int |
6a8214aa | 806 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 807 | { |
6a8214aa | 808 | struct nand_chip *chip = mtd->priv; |
ace4dfee TG |
809 | spinlock_t *lock = &chip->controller->lock; |
810 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 811 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 812 | retry: |
0dfc6246 TG |
813 | spin_lock(lock); |
814 | ||
b8b3ee9a | 815 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
816 | if (!chip->controller->active) |
817 | chip->controller->active = chip; | |
a36ed299 | 818 | |
ace4dfee TG |
819 | if (chip->controller->active == chip && chip->state == FL_READY) { |
820 | chip->state = new_state; | |
0dfc6246 | 821 | spin_unlock(lock); |
962034f4 VW |
822 | return 0; |
823 | } | |
824 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
825 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
826 | chip->state = FL_PM_SUSPENDED; | |
827 | spin_unlock(lock); | |
828 | return 0; | |
6b0d9a84 | 829 | } |
0dfc6246 TG |
830 | } |
831 | set_current_state(TASK_UNINTERRUPTIBLE); | |
832 | add_wait_queue(wq, &wait); | |
833 | spin_unlock(lock); | |
834 | schedule(); | |
835 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
836 | goto retry; |
837 | } | |
838 | ||
2af7c653 | 839 | /** |
8b6e50c9 BN |
840 | * panic_nand_wait - [GENERIC] wait until the command is done |
841 | * @mtd: MTD device structure | |
842 | * @chip: NAND chip structure | |
843 | * @timeo: timeout | |
2af7c653 SK |
844 | * |
845 | * Wait for command done. This is a helper function for nand_wait used when | |
846 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 847 | * an oops through mtdoops. |
2af7c653 SK |
848 | */ |
849 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
850 | unsigned long timeo) | |
851 | { | |
852 | int i; | |
853 | for (i = 0; i < timeo; i++) { | |
854 | if (chip->dev_ready) { | |
855 | if (chip->dev_ready(mtd)) | |
856 | break; | |
857 | } else { | |
858 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
859 | break; | |
860 | } | |
861 | mdelay(1); | |
f8ac0414 | 862 | } |
2af7c653 SK |
863 | } |
864 | ||
1da177e4 | 865 | /** |
8b6e50c9 BN |
866 | * nand_wait - [DEFAULT] wait until the command is done |
867 | * @mtd: MTD device structure | |
868 | * @chip: NAND chip structure | |
1da177e4 | 869 | * |
8b6e50c9 BN |
870 | * Wait for command done. This applies to erase and program only. Erase can |
871 | * take up to 400ms and program up to 20ms according to general NAND and | |
872 | * SmartMedia specs. | |
844d3b42 | 873 | */ |
7bc3312b | 874 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
875 | { |
876 | ||
7bc3312b | 877 | int status, state = chip->state; |
6d2559f8 | 878 | unsigned long timeo = (state == FL_ERASING ? 400 : 20); |
1da177e4 | 879 | |
8fe833c1 RP |
880 | led_trigger_event(nand_led_trigger, LED_FULL); |
881 | ||
8b6e50c9 BN |
882 | /* |
883 | * Apply this short delay always to ensure that we do wait tWB in any | |
884 | * case on any machine. | |
885 | */ | |
e0c7d767 | 886 | ndelay(100); |
1da177e4 | 887 | |
14c65786 | 888 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 889 | |
2af7c653 SK |
890 | if (in_interrupt() || oops_in_progress) |
891 | panic_nand_wait(mtd, chip, timeo); | |
892 | else { | |
6d2559f8 | 893 | timeo = jiffies + msecs_to_jiffies(timeo); |
2af7c653 SK |
894 | while (time_before(jiffies, timeo)) { |
895 | if (chip->dev_ready) { | |
896 | if (chip->dev_ready(mtd)) | |
897 | break; | |
898 | } else { | |
899 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
900 | break; | |
901 | } | |
902 | cond_resched(); | |
1da177e4 | 903 | } |
1da177e4 | 904 | } |
8fe833c1 RP |
905 | led_trigger_event(nand_led_trigger, LED_OFF); |
906 | ||
ace4dfee | 907 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
908 | /* This can happen if in case of timeout or buggy dev_ready */ |
909 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
910 | return status; |
911 | } | |
912 | ||
7d70f334 | 913 | /** |
b6d676db | 914 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
915 | * @mtd: mtd info |
916 | * @ofs: offset to start unlock from | |
917 | * @len: length to unlock | |
8b6e50c9 BN |
918 | * @invert: when = 0, unlock the range of blocks within the lower and |
919 | * upper boundary address | |
920 | * when = 1, unlock the range of blocks outside the boundaries | |
921 | * of the lower and upper boundary address | |
7d70f334 | 922 | * |
8b6e50c9 | 923 | * Returs unlock status. |
7d70f334 VS |
924 | */ |
925 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
926 | uint64_t len, int invert) | |
927 | { | |
928 | int ret = 0; | |
929 | int status, page; | |
930 | struct nand_chip *chip = mtd->priv; | |
931 | ||
932 | /* Submit address of first page to unlock */ | |
933 | page = ofs >> chip->page_shift; | |
934 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
935 | ||
936 | /* Submit address of last page to unlock */ | |
937 | page = (ofs + len) >> chip->page_shift; | |
938 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
939 | (page | invert) & chip->pagemask); | |
940 | ||
941 | /* Call wait ready function */ | |
942 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 943 | /* See if device thinks it succeeded */ |
74830966 | 944 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 945 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
946 | __func__, status); |
947 | ret = -EIO; | |
948 | } | |
949 | ||
950 | return ret; | |
951 | } | |
952 | ||
953 | /** | |
b6d676db | 954 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
955 | * @mtd: mtd info |
956 | * @ofs: offset to start unlock from | |
957 | * @len: length to unlock | |
7d70f334 | 958 | * |
8b6e50c9 | 959 | * Returns unlock status. |
7d70f334 VS |
960 | */ |
961 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
962 | { | |
963 | int ret = 0; | |
964 | int chipnr; | |
965 | struct nand_chip *chip = mtd->priv; | |
966 | ||
289c0522 | 967 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
968 | __func__, (unsigned long long)ofs, len); |
969 | ||
970 | if (check_offs_len(mtd, ofs, len)) | |
971 | ret = -EINVAL; | |
972 | ||
973 | /* Align to last block address if size addresses end of the device */ | |
974 | if (ofs + len == mtd->size) | |
975 | len -= mtd->erasesize; | |
976 | ||
6a8214aa | 977 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
978 | |
979 | /* Shift to get chip number */ | |
980 | chipnr = ofs >> chip->chip_shift; | |
981 | ||
982 | chip->select_chip(mtd, chipnr); | |
983 | ||
57d3a9a8 WD |
984 | /* |
985 | * Reset the chip. | |
986 | * If we want to check the WP through READ STATUS and check the bit 7 | |
987 | * we must reset the chip | |
988 | * some operation can also clear the bit 7 of status register | |
989 | * eg. erase/program a locked block | |
990 | */ | |
991 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
992 | ||
7d70f334 VS |
993 | /* Check, if it is write protected */ |
994 | if (nand_check_wp(mtd)) { | |
289c0522 | 995 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
996 | __func__); |
997 | ret = -EIO; | |
998 | goto out; | |
999 | } | |
1000 | ||
1001 | ret = __nand_unlock(mtd, ofs, len, 0); | |
1002 | ||
1003 | out: | |
b0bb6903 | 1004 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1005 | nand_release_device(mtd); |
1006 | ||
1007 | return ret; | |
1008 | } | |
7351d3a5 | 1009 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
1010 | |
1011 | /** | |
b6d676db | 1012 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
1013 | * @mtd: mtd info |
1014 | * @ofs: offset to start unlock from | |
1015 | * @len: length to unlock | |
7d70f334 | 1016 | * |
8b6e50c9 BN |
1017 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
1018 | * have this feature, but it allows only to lock all blocks, not for specified | |
1019 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
1020 | * now. | |
7d70f334 | 1021 | * |
8b6e50c9 | 1022 | * Returns lock status. |
7d70f334 VS |
1023 | */ |
1024 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1025 | { | |
1026 | int ret = 0; | |
1027 | int chipnr, status, page; | |
1028 | struct nand_chip *chip = mtd->priv; | |
1029 | ||
289c0522 | 1030 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1031 | __func__, (unsigned long long)ofs, len); |
1032 | ||
1033 | if (check_offs_len(mtd, ofs, len)) | |
1034 | ret = -EINVAL; | |
1035 | ||
6a8214aa | 1036 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
1037 | |
1038 | /* Shift to get chip number */ | |
1039 | chipnr = ofs >> chip->chip_shift; | |
1040 | ||
1041 | chip->select_chip(mtd, chipnr); | |
1042 | ||
57d3a9a8 WD |
1043 | /* |
1044 | * Reset the chip. | |
1045 | * If we want to check the WP through READ STATUS and check the bit 7 | |
1046 | * we must reset the chip | |
1047 | * some operation can also clear the bit 7 of status register | |
1048 | * eg. erase/program a locked block | |
1049 | */ | |
1050 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1051 | ||
7d70f334 VS |
1052 | /* Check, if it is write protected */ |
1053 | if (nand_check_wp(mtd)) { | |
289c0522 | 1054 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1055 | __func__); |
1056 | status = MTD_ERASE_FAILED; | |
1057 | ret = -EIO; | |
1058 | goto out; | |
1059 | } | |
1060 | ||
1061 | /* Submit address of first page to lock */ | |
1062 | page = ofs >> chip->page_shift; | |
1063 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1064 | ||
1065 | /* Call wait ready function */ | |
1066 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1067 | /* See if device thinks it succeeded */ |
74830966 | 1068 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1069 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1070 | __func__, status); |
1071 | ret = -EIO; | |
1072 | goto out; | |
1073 | } | |
1074 | ||
1075 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1076 | ||
1077 | out: | |
b0bb6903 | 1078 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1079 | nand_release_device(mtd); |
1080 | ||
1081 | return ret; | |
1082 | } | |
7351d3a5 | 1083 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1084 | |
8593fbc6 | 1085 | /** |
7854d3f7 | 1086 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1087 | * @mtd: mtd info structure |
1088 | * @chip: nand chip info structure | |
1089 | * @buf: buffer to store read data | |
1fbb938d | 1090 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1091 | * @page: page number to read |
52ff49df | 1092 | * |
7854d3f7 | 1093 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1094 | */ |
1095 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1096 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1097 | { |
1098 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1099 | if (oob_required) |
1100 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1101 | return 0; |
1102 | } | |
1103 | ||
52ff49df | 1104 | /** |
7854d3f7 | 1105 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1106 | * @mtd: mtd info structure |
1107 | * @chip: nand chip info structure | |
1108 | * @buf: buffer to store read data | |
1fbb938d | 1109 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1110 | * @page: page number to read |
52ff49df DB |
1111 | * |
1112 | * We need a special oob layout and handling even when OOB isn't used. | |
1113 | */ | |
7351d3a5 | 1114 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1115 | struct nand_chip *chip, uint8_t *buf, |
1116 | int oob_required, int page) | |
52ff49df DB |
1117 | { |
1118 | int eccsize = chip->ecc.size; | |
1119 | int eccbytes = chip->ecc.bytes; | |
1120 | uint8_t *oob = chip->oob_poi; | |
1121 | int steps, size; | |
1122 | ||
1123 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1124 | chip->read_buf(mtd, buf, eccsize); | |
1125 | buf += eccsize; | |
1126 | ||
1127 | if (chip->ecc.prepad) { | |
1128 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1129 | oob += chip->ecc.prepad; | |
1130 | } | |
1131 | ||
1132 | chip->read_buf(mtd, oob, eccbytes); | |
1133 | oob += eccbytes; | |
1134 | ||
1135 | if (chip->ecc.postpad) { | |
1136 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1137 | oob += chip->ecc.postpad; | |
1138 | } | |
1139 | } | |
1140 | ||
1141 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1142 | if (size) | |
1143 | chip->read_buf(mtd, oob, size); | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
1da177e4 | 1148 | /** |
7854d3f7 | 1149 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1150 | * @mtd: mtd info structure |
1151 | * @chip: nand chip info structure | |
1152 | * @buf: buffer to store read data | |
1fbb938d | 1153 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1154 | * @page: page number to read |
068e3c0a | 1155 | */ |
f5bbdacc | 1156 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1157 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1158 | { |
f5bbdacc TG |
1159 | int i, eccsize = chip->ecc.size; |
1160 | int eccbytes = chip->ecc.bytes; | |
1161 | int eccsteps = chip->ecc.steps; | |
1162 | uint8_t *p = buf; | |
4bf63fcb DW |
1163 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1164 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1165 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1166 | unsigned int max_bitflips = 0; |
f5bbdacc | 1167 | |
1fbb938d | 1168 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1169 | |
1170 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1171 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1172 | ||
1173 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1174 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1175 | |
1176 | eccsteps = chip->ecc.steps; | |
1177 | p = buf; | |
1178 | ||
1179 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1180 | int stat; | |
1181 | ||
1182 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1183 | if (stat < 0) { |
f5bbdacc | 1184 | mtd->ecc_stats.failed++; |
3f91e94f | 1185 | } else { |
f5bbdacc | 1186 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1187 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1188 | } | |
f5bbdacc | 1189 | } |
3f91e94f | 1190 | return max_bitflips; |
22c60f5f | 1191 | } |
1da177e4 | 1192 | |
3d459559 | 1193 | /** |
837a6ba4 | 1194 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1195 | * @mtd: mtd info structure |
1196 | * @chip: nand chip info structure | |
1197 | * @data_offs: offset of requested data within the page | |
1198 | * @readlen: data length | |
1199 | * @bufpoi: buffer to store read data | |
e004debd | 1200 | * @page: page number to read |
3d459559 | 1201 | */ |
7351d3a5 | 1202 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
1203 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
1204 | int page) | |
3d459559 AK |
1205 | { |
1206 | int start_step, end_step, num_steps; | |
1207 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1208 | uint8_t *p; | |
1209 | int data_col_addr, i, gaps = 0; | |
1210 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1211 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
4a4163ca | 1212 | int index; |
3f91e94f | 1213 | unsigned int max_bitflips = 0; |
3d459559 | 1214 | |
7854d3f7 | 1215 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1216 | start_step = data_offs / chip->ecc.size; |
1217 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1218 | num_steps = end_step - start_step + 1; | |
4a4163ca | 1219 | index = start_step * chip->ecc.bytes; |
3d459559 | 1220 | |
8b6e50c9 | 1221 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1222 | datafrag_len = num_steps * chip->ecc.size; |
1223 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1224 | ||
1225 | data_col_addr = start_step * chip->ecc.size; | |
1226 | /* If we read not a page aligned data */ | |
1227 | if (data_col_addr != 0) | |
1228 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1229 | ||
1230 | p = bufpoi + data_col_addr; | |
1231 | chip->read_buf(mtd, p, datafrag_len); | |
1232 | ||
8b6e50c9 | 1233 | /* Calculate ECC */ |
3d459559 AK |
1234 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1235 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1236 | ||
8b6e50c9 BN |
1237 | /* |
1238 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1239 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1240 | */ |
3d459559 | 1241 | for (i = 0; i < eccfrag_len - 1; i++) { |
47570bb1 | 1242 | if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { |
3d459559 AK |
1243 | gaps = 1; |
1244 | break; | |
1245 | } | |
1246 | } | |
1247 | if (gaps) { | |
1248 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1249 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1250 | } else { | |
8b6e50c9 | 1251 | /* |
7854d3f7 | 1252 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1253 | * about buswidth alignment in read_buf. |
1254 | */ | |
7351d3a5 | 1255 | aligned_pos = eccpos[index] & ~(busw - 1); |
3d459559 | 1256 | aligned_len = eccfrag_len; |
7351d3a5 | 1257 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1258 | aligned_len++; |
7351d3a5 | 1259 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1260 | aligned_len++; |
1261 | ||
7351d3a5 FF |
1262 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1263 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1264 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1265 | } | |
1266 | ||
1267 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1268 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1269 | |
1270 | p = bufpoi + data_col_addr; | |
1271 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1272 | int stat; | |
1273 | ||
7351d3a5 FF |
1274 | stat = chip->ecc.correct(mtd, p, |
1275 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
3f91e94f | 1276 | if (stat < 0) { |
3d459559 | 1277 | mtd->ecc_stats.failed++; |
3f91e94f | 1278 | } else { |
3d459559 | 1279 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1280 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1281 | } | |
3d459559 | 1282 | } |
3f91e94f | 1283 | return max_bitflips; |
3d459559 AK |
1284 | } |
1285 | ||
068e3c0a | 1286 | /** |
7854d3f7 | 1287 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1288 | * @mtd: mtd info structure |
1289 | * @chip: nand chip info structure | |
1290 | * @buf: buffer to store read data | |
1fbb938d | 1291 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1292 | * @page: page number to read |
068e3c0a | 1293 | * |
7854d3f7 | 1294 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1295 | */ |
f5bbdacc | 1296 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1297 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1298 | { |
f5bbdacc TG |
1299 | int i, eccsize = chip->ecc.size; |
1300 | int eccbytes = chip->ecc.bytes; | |
1301 | int eccsteps = chip->ecc.steps; | |
1302 | uint8_t *p = buf; | |
4bf63fcb DW |
1303 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1304 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1305 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1306 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1307 | |
1308 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1309 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1310 | chip->read_buf(mtd, p, eccsize); | |
1311 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1312 | } |
f75e5097 | 1313 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1314 | |
f5bbdacc | 1315 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1316 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1317 | |
f5bbdacc TG |
1318 | eccsteps = chip->ecc.steps; |
1319 | p = buf; | |
61b03bd7 | 1320 | |
f5bbdacc TG |
1321 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1322 | int stat; | |
1da177e4 | 1323 | |
f5bbdacc | 1324 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
3f91e94f | 1325 | if (stat < 0) { |
f5bbdacc | 1326 | mtd->ecc_stats.failed++; |
3f91e94f | 1327 | } else { |
f5bbdacc | 1328 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1329 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1330 | } | |
f5bbdacc | 1331 | } |
3f91e94f | 1332 | return max_bitflips; |
f5bbdacc | 1333 | } |
1da177e4 | 1334 | |
6e0cb135 | 1335 | /** |
7854d3f7 | 1336 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1337 | * @mtd: mtd info structure |
1338 | * @chip: nand chip info structure | |
1339 | * @buf: buffer to store read data | |
1fbb938d | 1340 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1341 | * @page: page number to read |
6e0cb135 | 1342 | * |
8b6e50c9 BN |
1343 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1344 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1345 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1346 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1347 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1348 | */ |
1349 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1350 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1351 | { |
1352 | int i, eccsize = chip->ecc.size; | |
1353 | int eccbytes = chip->ecc.bytes; | |
1354 | int eccsteps = chip->ecc.steps; | |
1355 | uint8_t *p = buf; | |
1356 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1357 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1358 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1359 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1360 | |
1361 | /* Read the OOB area first */ | |
1362 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1363 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1364 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1365 | ||
1366 | for (i = 0; i < chip->ecc.total; i++) | |
1367 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1368 | ||
1369 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1370 | int stat; | |
1371 | ||
1372 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1373 | chip->read_buf(mtd, p, eccsize); | |
1374 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1375 | ||
1376 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
3f91e94f | 1377 | if (stat < 0) { |
6e0cb135 | 1378 | mtd->ecc_stats.failed++; |
3f91e94f | 1379 | } else { |
6e0cb135 | 1380 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1381 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1382 | } | |
6e0cb135 | 1383 | } |
3f91e94f | 1384 | return max_bitflips; |
6e0cb135 SN |
1385 | } |
1386 | ||
f5bbdacc | 1387 | /** |
7854d3f7 | 1388 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1389 | * @mtd: mtd info structure |
1390 | * @chip: nand chip info structure | |
1391 | * @buf: buffer to store read data | |
1fbb938d | 1392 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1393 | * @page: page number to read |
f5bbdacc | 1394 | * |
8b6e50c9 BN |
1395 | * The hw generator calculates the error syndrome automatically. Therefore we |
1396 | * need a special oob layout and handling. | |
f5bbdacc TG |
1397 | */ |
1398 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1399 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1400 | { |
1401 | int i, eccsize = chip->ecc.size; | |
1402 | int eccbytes = chip->ecc.bytes; | |
1403 | int eccsteps = chip->ecc.steps; | |
1404 | uint8_t *p = buf; | |
f75e5097 | 1405 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1406 | unsigned int max_bitflips = 0; |
1da177e4 | 1407 | |
f5bbdacc TG |
1408 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1409 | int stat; | |
61b03bd7 | 1410 | |
f5bbdacc TG |
1411 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1412 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1413 | |
f5bbdacc TG |
1414 | if (chip->ecc.prepad) { |
1415 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1416 | oob += chip->ecc.prepad; | |
1417 | } | |
1da177e4 | 1418 | |
f5bbdacc TG |
1419 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1420 | chip->read_buf(mtd, oob, eccbytes); | |
1421 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1422 | |
3f91e94f | 1423 | if (stat < 0) { |
f5bbdacc | 1424 | mtd->ecc_stats.failed++; |
3f91e94f | 1425 | } else { |
f5bbdacc | 1426 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1427 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1428 | } | |
61b03bd7 | 1429 | |
f5bbdacc | 1430 | oob += eccbytes; |
1da177e4 | 1431 | |
f5bbdacc TG |
1432 | if (chip->ecc.postpad) { |
1433 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1434 | oob += chip->ecc.postpad; | |
61b03bd7 | 1435 | } |
f5bbdacc | 1436 | } |
1da177e4 | 1437 | |
f5bbdacc | 1438 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1439 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1440 | if (i) |
1441 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1442 | |
3f91e94f | 1443 | return max_bitflips; |
f5bbdacc | 1444 | } |
1da177e4 | 1445 | |
f5bbdacc | 1446 | /** |
7854d3f7 | 1447 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1448 | * @chip: nand chip structure |
1449 | * @oob: oob destination address | |
1450 | * @ops: oob ops structure | |
1451 | * @len: size of oob to transfer | |
8593fbc6 TG |
1452 | */ |
1453 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1454 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1455 | { |
f8ac0414 | 1456 | switch (ops->mode) { |
8593fbc6 | 1457 | |
0612b9dd BN |
1458 | case MTD_OPS_PLACE_OOB: |
1459 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1460 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1461 | return oob + len; | |
1462 | ||
0612b9dd | 1463 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1464 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1465 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1466 | size_t bytes = 0; | |
8593fbc6 | 1467 | |
f8ac0414 | 1468 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1469 | /* Read request not from offset 0? */ |
7bc3312b TG |
1470 | if (unlikely(roffs)) { |
1471 | if (roffs >= free->length) { | |
1472 | roffs -= free->length; | |
1473 | continue; | |
1474 | } | |
1475 | boffs = free->offset + roffs; | |
1476 | bytes = min_t(size_t, len, | |
1477 | (free->length - roffs)); | |
1478 | roffs = 0; | |
1479 | } else { | |
1480 | bytes = min_t(size_t, len, free->length); | |
1481 | boffs = free->offset; | |
1482 | } | |
1483 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1484 | oob += bytes; |
1485 | } | |
1486 | return oob; | |
1487 | } | |
1488 | default: | |
1489 | BUG(); | |
1490 | } | |
1491 | return NULL; | |
1492 | } | |
1493 | ||
ba84fb59 BN |
1494 | /** |
1495 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1496 | * @mtd: MTD device structure | |
1497 | * @retry_mode: the retry mode to use | |
1498 | * | |
1499 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
1500 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
1501 | * a new threshold, the host should retry reading the page. | |
1502 | */ | |
1503 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
1504 | { | |
1505 | struct nand_chip *chip = mtd->priv; | |
1506 | ||
1507 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
1508 | ||
1509 | if (retry_mode >= chip->read_retries) | |
1510 | return -EINVAL; | |
1511 | ||
1512 | if (!chip->setup_read_retry) | |
1513 | return -EOPNOTSUPP; | |
1514 | ||
1515 | return chip->setup_read_retry(mtd, retry_mode); | |
1516 | } | |
1517 | ||
8593fbc6 | 1518 | /** |
7854d3f7 | 1519 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1520 | * @mtd: MTD device structure |
1521 | * @from: offset to read from | |
1522 | * @ops: oob ops structure | |
f5bbdacc TG |
1523 | * |
1524 | * Internal function. Called with chip held. | |
1525 | */ | |
8593fbc6 TG |
1526 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1527 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1528 | { |
e47f3db4 | 1529 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
f5bbdacc | 1530 | struct nand_chip *chip = mtd->priv; |
f5bbdacc | 1531 | int ret = 0; |
8593fbc6 | 1532 | uint32_t readlen = ops->len; |
7014568b | 1533 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1534 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1535 | mtd->oobavail : mtd->oobsize; |
1536 | ||
8593fbc6 | 1537 | uint8_t *bufpoi, *oob, *buf; |
66507c7b | 1538 | int use_bufpoi; |
edbc4540 | 1539 | unsigned int max_bitflips = 0; |
ba84fb59 | 1540 | int retry_mode = 0; |
b72f3dfb | 1541 | bool ecc_fail = false; |
1da177e4 | 1542 | |
f5bbdacc TG |
1543 | chipnr = (int)(from >> chip->chip_shift); |
1544 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1545 | |
f5bbdacc TG |
1546 | realpage = (int)(from >> chip->page_shift); |
1547 | page = realpage & chip->pagemask; | |
1da177e4 | 1548 | |
f5bbdacc | 1549 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1550 | |
8593fbc6 TG |
1551 | buf = ops->datbuf; |
1552 | oob = ops->oobbuf; | |
e47f3db4 | 1553 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1554 | |
f8ac0414 | 1555 | while (1) { |
b72f3dfb BN |
1556 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
1557 | ||
f5bbdacc TG |
1558 | bytes = min(mtd->writesize - col, readlen); |
1559 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1560 | |
66507c7b KD |
1561 | if (!aligned) |
1562 | use_bufpoi = 1; | |
1563 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
1564 | use_bufpoi = !virt_addr_valid(buf); | |
1565 | else | |
1566 | use_bufpoi = 0; | |
1567 | ||
8b6e50c9 | 1568 | /* Is the current page in the buffer? */ |
8593fbc6 | 1569 | if (realpage != chip->pagebuf || oob) { |
66507c7b KD |
1570 | bufpoi = use_bufpoi ? chip->buffers->databuf : buf; |
1571 | ||
1572 | if (use_bufpoi && aligned) | |
1573 | pr_debug("%s: using read bounce buffer for buf@%p\n", | |
1574 | __func__, buf); | |
61b03bd7 | 1575 | |
ba84fb59 | 1576 | read_retry: |
c00a0991 | 1577 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1578 | |
edbc4540 MD |
1579 | /* |
1580 | * Now read the page into the buffer. Absent an error, | |
1581 | * the read methods return max bitflips per ecc step. | |
1582 | */ | |
0612b9dd | 1583 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1584 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1585 | oob_required, |
1586 | page); | |
a5ff4f10 JW |
1587 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1588 | !oob) | |
7351d3a5 | 1589 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
1590 | col, bytes, bufpoi, |
1591 | page); | |
956e944c | 1592 | else |
46a8cf2d | 1593 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1594 | oob_required, page); |
6d77b9d0 | 1595 | if (ret < 0) { |
66507c7b | 1596 | if (use_bufpoi) |
6d77b9d0 BN |
1597 | /* Invalidate page cache */ |
1598 | chip->pagebuf = -1; | |
1da177e4 | 1599 | break; |
6d77b9d0 | 1600 | } |
f5bbdacc | 1601 | |
edbc4540 MD |
1602 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1603 | ||
f5bbdacc | 1604 | /* Transfer not aligned data */ |
66507c7b | 1605 | if (use_bufpoi) { |
a5ff4f10 | 1606 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 1607 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 1608 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1609 | chip->pagebuf = realpage; |
edbc4540 MD |
1610 | chip->pagebuf_bitflips = ret; |
1611 | } else { | |
6d77b9d0 BN |
1612 | /* Invalidate page cache */ |
1613 | chip->pagebuf = -1; | |
edbc4540 | 1614 | } |
4bf63fcb | 1615 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1616 | } |
1617 | ||
8593fbc6 | 1618 | if (unlikely(oob)) { |
b64d39d8 ML |
1619 | int toread = min(oobreadlen, max_oobsize); |
1620 | ||
1621 | if (toread) { | |
1622 | oob = nand_transfer_oob(chip, | |
1623 | oob, ops, toread); | |
1624 | oobreadlen -= toread; | |
1625 | } | |
8593fbc6 | 1626 | } |
5bc7c33c BN |
1627 | |
1628 | if (chip->options & NAND_NEED_READRDY) { | |
1629 | /* Apply delay or wait for ready/busy pin */ | |
1630 | if (!chip->dev_ready) | |
1631 | udelay(chip->chip_delay); | |
1632 | else | |
1633 | nand_wait_ready(mtd); | |
1634 | } | |
b72f3dfb | 1635 | |
ba84fb59 | 1636 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 1637 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
1638 | retry_mode++; |
1639 | ret = nand_setup_read_retry(mtd, | |
1640 | retry_mode); | |
1641 | if (ret < 0) | |
1642 | break; | |
1643 | ||
1644 | /* Reset failures; retry */ | |
1645 | mtd->ecc_stats.failed = ecc_failures; | |
1646 | goto read_retry; | |
1647 | } else { | |
1648 | /* No more retry modes; real failure */ | |
1649 | ecc_fail = true; | |
1650 | } | |
1651 | } | |
1652 | ||
1653 | buf += bytes; | |
8593fbc6 | 1654 | } else { |
4bf63fcb | 1655 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1656 | buf += bytes; |
edbc4540 MD |
1657 | max_bitflips = max_t(unsigned int, max_bitflips, |
1658 | chip->pagebuf_bitflips); | |
8593fbc6 | 1659 | } |
1da177e4 | 1660 | |
f5bbdacc | 1661 | readlen -= bytes; |
61b03bd7 | 1662 | |
ba84fb59 BN |
1663 | /* Reset to retry mode 0 */ |
1664 | if (retry_mode) { | |
1665 | ret = nand_setup_read_retry(mtd, 0); | |
1666 | if (ret < 0) | |
1667 | break; | |
1668 | retry_mode = 0; | |
1669 | } | |
1670 | ||
f5bbdacc | 1671 | if (!readlen) |
61b03bd7 | 1672 | break; |
1da177e4 | 1673 | |
8b6e50c9 | 1674 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1675 | col = 0; |
1676 | /* Increment page address */ | |
1677 | realpage++; | |
1678 | ||
ace4dfee | 1679 | page = realpage & chip->pagemask; |
1da177e4 LT |
1680 | /* Check, if we cross a chip boundary */ |
1681 | if (!page) { | |
1682 | chipnr++; | |
ace4dfee TG |
1683 | chip->select_chip(mtd, -1); |
1684 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1685 | } |
1da177e4 | 1686 | } |
b0bb6903 | 1687 | chip->select_chip(mtd, -1); |
1da177e4 | 1688 | |
8593fbc6 | 1689 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1690 | if (oob) |
1691 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1692 | |
3f91e94f | 1693 | if (ret < 0) |
f5bbdacc TG |
1694 | return ret; |
1695 | ||
b72f3dfb | 1696 | if (ecc_fail) |
9a1fcdfd TG |
1697 | return -EBADMSG; |
1698 | ||
edbc4540 | 1699 | return max_bitflips; |
f5bbdacc TG |
1700 | } |
1701 | ||
1702 | /** | |
25985edc | 1703 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1704 | * @mtd: MTD device structure |
1705 | * @from: offset to read from | |
1706 | * @len: number of bytes to read | |
1707 | * @retlen: pointer to variable to store the number of read bytes | |
1708 | * @buf: the databuffer to put data | |
f5bbdacc | 1709 | * |
8b6e50c9 | 1710 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1711 | */ |
1712 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1713 | size_t *retlen, uint8_t *buf) | |
1714 | { | |
4a89ff88 | 1715 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1716 | int ret; |
1717 | ||
6a8214aa | 1718 | nand_get_device(mtd, FL_READING); |
4a89ff88 BN |
1719 | ops.len = len; |
1720 | ops.datbuf = buf; | |
1721 | ops.oobbuf = NULL; | |
11041ae6 | 1722 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1723 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1724 | *retlen = ops.retlen; |
f5bbdacc | 1725 | nand_release_device(mtd); |
f5bbdacc | 1726 | return ret; |
1da177e4 LT |
1727 | } |
1728 | ||
7bc3312b | 1729 | /** |
7854d3f7 | 1730 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1731 | * @mtd: mtd info structure |
1732 | * @chip: nand chip info structure | |
1733 | * @page: page number to read | |
7bc3312b TG |
1734 | */ |
1735 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1736 | int page) |
7bc3312b | 1737 | { |
5c2ffb11 | 1738 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1739 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1740 | return 0; |
7bc3312b TG |
1741 | } |
1742 | ||
1743 | /** | |
7854d3f7 | 1744 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1745 | * with syndromes |
8b6e50c9 BN |
1746 | * @mtd: mtd info structure |
1747 | * @chip: nand chip info structure | |
1748 | * @page: page number to read | |
7bc3312b TG |
1749 | */ |
1750 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1751 | int page) |
7bc3312b TG |
1752 | { |
1753 | uint8_t *buf = chip->oob_poi; | |
1754 | int length = mtd->oobsize; | |
1755 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1756 | int eccsize = chip->ecc.size; | |
1757 | uint8_t *bufpoi = buf; | |
1758 | int i, toread, sndrnd = 0, pos; | |
1759 | ||
1760 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1761 | for (i = 0; i < chip->ecc.steps; i++) { | |
1762 | if (sndrnd) { | |
1763 | pos = eccsize + i * (eccsize + chunk); | |
1764 | if (mtd->writesize > 512) | |
1765 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1766 | else | |
1767 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1768 | } else | |
1769 | sndrnd = 1; | |
1770 | toread = min_t(int, length, chunk); | |
1771 | chip->read_buf(mtd, bufpoi, toread); | |
1772 | bufpoi += toread; | |
1773 | length -= toread; | |
1774 | } | |
1775 | if (length > 0) | |
1776 | chip->read_buf(mtd, bufpoi, length); | |
1777 | ||
5c2ffb11 | 1778 | return 0; |
7bc3312b TG |
1779 | } |
1780 | ||
1781 | /** | |
7854d3f7 | 1782 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1783 | * @mtd: mtd info structure |
1784 | * @chip: nand chip info structure | |
1785 | * @page: page number to write | |
7bc3312b TG |
1786 | */ |
1787 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1788 | int page) | |
1789 | { | |
1790 | int status = 0; | |
1791 | const uint8_t *buf = chip->oob_poi; | |
1792 | int length = mtd->oobsize; | |
1793 | ||
1794 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1795 | chip->write_buf(mtd, buf, length); | |
1796 | /* Send command to program the OOB data */ | |
1797 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1798 | ||
1799 | status = chip->waitfunc(mtd, chip); | |
1800 | ||
0d420f9d | 1801 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1802 | } |
1803 | ||
1804 | /** | |
7854d3f7 | 1805 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1806 | * with syndrome - only for large page flash |
1807 | * @mtd: mtd info structure | |
1808 | * @chip: nand chip info structure | |
1809 | * @page: page number to write | |
7bc3312b TG |
1810 | */ |
1811 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1812 | struct nand_chip *chip, int page) | |
1813 | { | |
1814 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1815 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1816 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1817 | const uint8_t *bufpoi = chip->oob_poi; | |
1818 | ||
1819 | /* | |
1820 | * data-ecc-data-ecc ... ecc-oob | |
1821 | * or | |
1822 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1823 | */ | |
1824 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1825 | pos = steps * (eccsize + chunk); | |
1826 | steps = 0; | |
1827 | } else | |
8b0036ee | 1828 | pos = eccsize; |
7bc3312b TG |
1829 | |
1830 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1831 | for (i = 0; i < steps; i++) { | |
1832 | if (sndcmd) { | |
1833 | if (mtd->writesize <= 512) { | |
1834 | uint32_t fill = 0xFFFFFFFF; | |
1835 | ||
1836 | len = eccsize; | |
1837 | while (len > 0) { | |
1838 | int num = min_t(int, len, 4); | |
1839 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1840 | num); | |
1841 | len -= num; | |
1842 | } | |
1843 | } else { | |
1844 | pos = eccsize + i * (eccsize + chunk); | |
1845 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1846 | } | |
1847 | } else | |
1848 | sndcmd = 1; | |
1849 | len = min_t(int, length, chunk); | |
1850 | chip->write_buf(mtd, bufpoi, len); | |
1851 | bufpoi += len; | |
1852 | length -= len; | |
1853 | } | |
1854 | if (length > 0) | |
1855 | chip->write_buf(mtd, bufpoi, length); | |
1856 | ||
1857 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1858 | status = chip->waitfunc(mtd, chip); | |
1859 | ||
1860 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1861 | } | |
1862 | ||
1da177e4 | 1863 | /** |
7854d3f7 | 1864 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
1865 | * @mtd: MTD device structure |
1866 | * @from: offset to read from | |
1867 | * @ops: oob operations description structure | |
1da177e4 | 1868 | * |
8b6e50c9 | 1869 | * NAND read out-of-band data from the spare area. |
1da177e4 | 1870 | */ |
8593fbc6 TG |
1871 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1872 | struct mtd_oob_ops *ops) | |
1da177e4 | 1873 | { |
c00a0991 | 1874 | int page, realpage, chipnr; |
ace4dfee | 1875 | struct nand_chip *chip = mtd->priv; |
041e4575 | 1876 | struct mtd_ecc_stats stats; |
7014568b VW |
1877 | int readlen = ops->ooblen; |
1878 | int len; | |
7bc3312b | 1879 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 1880 | int ret = 0; |
61b03bd7 | 1881 | |
289c0522 | 1882 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 1883 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 1884 | |
041e4575 BN |
1885 | stats = mtd->ecc_stats; |
1886 | ||
0612b9dd | 1887 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 1888 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1889 | else |
1890 | len = mtd->oobsize; | |
1891 | ||
1892 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
1893 | pr_debug("%s: attempt to start read outside oob\n", |
1894 | __func__); | |
03736155 AH |
1895 | return -EINVAL; |
1896 | } | |
1897 | ||
1898 | /* Do not allow reads past end of device */ | |
1899 | if (unlikely(from >= mtd->size || | |
1900 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1901 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
1902 | pr_debug("%s: attempt to read beyond end of device\n", |
1903 | __func__); | |
03736155 AH |
1904 | return -EINVAL; |
1905 | } | |
7014568b | 1906 | |
7314e9e7 | 1907 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1908 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1909 | |
7314e9e7 TG |
1910 | /* Shift to get page */ |
1911 | realpage = (int)(from >> chip->page_shift); | |
1912 | page = realpage & chip->pagemask; | |
1da177e4 | 1913 | |
f8ac0414 | 1914 | while (1) { |
0612b9dd | 1915 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 1916 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 1917 | else |
1951f2f7 SL |
1918 | ret = chip->ecc.read_oob(mtd, chip, page); |
1919 | ||
1920 | if (ret < 0) | |
1921 | break; | |
7014568b VW |
1922 | |
1923 | len = min(len, readlen); | |
1924 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1925 | |
5bc7c33c BN |
1926 | if (chip->options & NAND_NEED_READRDY) { |
1927 | /* Apply delay or wait for ready/busy pin */ | |
1928 | if (!chip->dev_ready) | |
1929 | udelay(chip->chip_delay); | |
1930 | else | |
1931 | nand_wait_ready(mtd); | |
1932 | } | |
1933 | ||
7014568b | 1934 | readlen -= len; |
0d420f9d SZ |
1935 | if (!readlen) |
1936 | break; | |
1937 | ||
7314e9e7 TG |
1938 | /* Increment page address */ |
1939 | realpage++; | |
1940 | ||
1941 | page = realpage & chip->pagemask; | |
1942 | /* Check, if we cross a chip boundary */ | |
1943 | if (!page) { | |
1944 | chipnr++; | |
1945 | chip->select_chip(mtd, -1); | |
1946 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1947 | } |
1948 | } | |
b0bb6903 | 1949 | chip->select_chip(mtd, -1); |
1da177e4 | 1950 | |
1951f2f7 SL |
1951 | ops->oobretlen = ops->ooblen - readlen; |
1952 | ||
1953 | if (ret < 0) | |
1954 | return ret; | |
041e4575 BN |
1955 | |
1956 | if (mtd->ecc_stats.failed - stats.failed) | |
1957 | return -EBADMSG; | |
1958 | ||
1959 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
1960 | } |
1961 | ||
1962 | /** | |
8593fbc6 | 1963 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
1964 | * @mtd: MTD device structure |
1965 | * @from: offset to read from | |
1966 | * @ops: oob operation description structure | |
1da177e4 | 1967 | * |
8b6e50c9 | 1968 | * NAND read data and/or out-of-band data. |
1da177e4 | 1969 | */ |
8593fbc6 TG |
1970 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1971 | struct mtd_oob_ops *ops) | |
1da177e4 | 1972 | { |
8593fbc6 TG |
1973 | int ret = -ENOTSUPP; |
1974 | ||
1975 | ops->retlen = 0; | |
1da177e4 LT |
1976 | |
1977 | /* Do not allow reads past end of device */ | |
7014568b | 1978 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
1979 | pr_debug("%s: attempt to read beyond end of device\n", |
1980 | __func__); | |
1da177e4 LT |
1981 | return -EINVAL; |
1982 | } | |
1983 | ||
6a8214aa | 1984 | nand_get_device(mtd, FL_READING); |
1da177e4 | 1985 | |
f8ac0414 | 1986 | switch (ops->mode) { |
0612b9dd BN |
1987 | case MTD_OPS_PLACE_OOB: |
1988 | case MTD_OPS_AUTO_OOB: | |
1989 | case MTD_OPS_RAW: | |
8593fbc6 | 1990 | break; |
1da177e4 | 1991 | |
8593fbc6 TG |
1992 | default: |
1993 | goto out; | |
1994 | } | |
1da177e4 | 1995 | |
8593fbc6 TG |
1996 | if (!ops->datbuf) |
1997 | ret = nand_do_read_oob(mtd, from, ops); | |
1998 | else | |
1999 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 2000 | |
7351d3a5 | 2001 | out: |
8593fbc6 TG |
2002 | nand_release_device(mtd); |
2003 | return ret; | |
2004 | } | |
61b03bd7 | 2005 | |
1da177e4 | 2006 | |
8593fbc6 | 2007 | /** |
7854d3f7 | 2008 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
2009 | * @mtd: mtd info structure |
2010 | * @chip: nand chip info structure | |
2011 | * @buf: data buffer | |
1fbb938d | 2012 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df | 2013 | * |
7854d3f7 | 2014 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 2015 | */ |
fdbad98d | 2016 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2017 | const uint8_t *buf, int oob_required) |
8593fbc6 TG |
2018 | { |
2019 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
2020 | if (oob_required) |
2021 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2022 | |
2023 | return 0; | |
1da177e4 LT |
2024 | } |
2025 | ||
52ff49df | 2026 | /** |
7854d3f7 | 2027 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
2028 | * @mtd: mtd info structure |
2029 | * @chip: nand chip info structure | |
2030 | * @buf: data buffer | |
1fbb938d | 2031 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df DB |
2032 | * |
2033 | * We need a special oob layout and handling even when ECC isn't checked. | |
2034 | */ | |
fdbad98d | 2035 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 2036 | struct nand_chip *chip, |
1fbb938d | 2037 | const uint8_t *buf, int oob_required) |
52ff49df DB |
2038 | { |
2039 | int eccsize = chip->ecc.size; | |
2040 | int eccbytes = chip->ecc.bytes; | |
2041 | uint8_t *oob = chip->oob_poi; | |
2042 | int steps, size; | |
2043 | ||
2044 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
2045 | chip->write_buf(mtd, buf, eccsize); | |
2046 | buf += eccsize; | |
2047 | ||
2048 | if (chip->ecc.prepad) { | |
2049 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2050 | oob += chip->ecc.prepad; | |
2051 | } | |
2052 | ||
60c3bc1f | 2053 | chip->write_buf(mtd, oob, eccbytes); |
52ff49df DB |
2054 | oob += eccbytes; |
2055 | ||
2056 | if (chip->ecc.postpad) { | |
2057 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2058 | oob += chip->ecc.postpad; | |
2059 | } | |
2060 | } | |
2061 | ||
2062 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2063 | if (size) | |
2064 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2065 | |
2066 | return 0; | |
52ff49df | 2067 | } |
9223a456 | 2068 | /** |
7854d3f7 | 2069 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2070 | * @mtd: mtd info structure |
2071 | * @chip: nand chip info structure | |
2072 | * @buf: data buffer | |
1fbb938d | 2073 | * @oob_required: must write chip->oob_poi to OOB |
9223a456 | 2074 | */ |
fdbad98d | 2075 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2076 | const uint8_t *buf, int oob_required) |
9223a456 | 2077 | { |
f75e5097 TG |
2078 | int i, eccsize = chip->ecc.size; |
2079 | int eccbytes = chip->ecc.bytes; | |
2080 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2081 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2082 | const uint8_t *p = buf; |
8b099a39 | 2083 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2084 | |
7854d3f7 | 2085 | /* Software ECC calculation */ |
8593fbc6 TG |
2086 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2087 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2088 | |
8593fbc6 TG |
2089 | for (i = 0; i < chip->ecc.total; i++) |
2090 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 2091 | |
fdbad98d | 2092 | return chip->ecc.write_page_raw(mtd, chip, buf, 1); |
f75e5097 | 2093 | } |
9223a456 | 2094 | |
f75e5097 | 2095 | /** |
7854d3f7 | 2096 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2097 | * @mtd: mtd info structure |
2098 | * @chip: nand chip info structure | |
2099 | * @buf: data buffer | |
1fbb938d | 2100 | * @oob_required: must write chip->oob_poi to OOB |
f75e5097 | 2101 | */ |
fdbad98d | 2102 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2103 | const uint8_t *buf, int oob_required) |
f75e5097 TG |
2104 | { |
2105 | int i, eccsize = chip->ecc.size; | |
2106 | int eccbytes = chip->ecc.bytes; | |
2107 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2108 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2109 | const uint8_t *p = buf; |
8b099a39 | 2110 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2111 | |
f75e5097 TG |
2112 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2113 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2114 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2115 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2116 | } |
2117 | ||
f75e5097 TG |
2118 | for (i = 0; i < chip->ecc.total; i++) |
2119 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2120 | ||
2121 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2122 | |
2123 | return 0; | |
9223a456 TG |
2124 | } |
2125 | ||
837a6ba4 GP |
2126 | |
2127 | /** | |
2128 | * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write | |
2129 | * @mtd: mtd info structure | |
2130 | * @chip: nand chip info structure | |
d6a95080 | 2131 | * @offset: column address of subpage within the page |
837a6ba4 | 2132 | * @data_len: data length |
d6a95080 | 2133 | * @buf: data buffer |
837a6ba4 GP |
2134 | * @oob_required: must write chip->oob_poi to OOB |
2135 | */ | |
2136 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2137 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2138 | uint32_t data_len, const uint8_t *buf, |
837a6ba4 GP |
2139 | int oob_required) |
2140 | { | |
2141 | uint8_t *oob_buf = chip->oob_poi; | |
2142 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2143 | int ecc_size = chip->ecc.size; | |
2144 | int ecc_bytes = chip->ecc.bytes; | |
2145 | int ecc_steps = chip->ecc.steps; | |
2146 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
2147 | uint32_t start_step = offset / ecc_size; | |
2148 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2149 | int oob_bytes = mtd->oobsize / ecc_steps; | |
2150 | int step, i; | |
2151 | ||
2152 | for (step = 0; step < ecc_steps; step++) { | |
2153 | /* configure controller for WRITE access */ | |
2154 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2155 | ||
2156 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2157 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2158 | |
2159 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2160 | if ((step < start_step) || (step > end_step)) | |
2161 | memset(ecc_calc, 0xff, ecc_bytes); | |
2162 | else | |
d6a95080 | 2163 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2164 | |
2165 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2166 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2167 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2168 | memset(oob_buf, 0xff, oob_bytes); | |
2169 | ||
d6a95080 | 2170 | buf += ecc_size; |
837a6ba4 GP |
2171 | ecc_calc += ecc_bytes; |
2172 | oob_buf += oob_bytes; | |
2173 | } | |
2174 | ||
2175 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2176 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2177 | ecc_calc = chip->buffers->ecccalc; | |
2178 | for (i = 0; i < chip->ecc.total; i++) | |
2179 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2180 | ||
2181 | /* write OOB buffer to NAND device */ | |
2182 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2183 | ||
2184 | return 0; | |
2185 | } | |
2186 | ||
2187 | ||
61b03bd7 | 2188 | /** |
7854d3f7 | 2189 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2190 | * @mtd: mtd info structure |
2191 | * @chip: nand chip info structure | |
2192 | * @buf: data buffer | |
1fbb938d | 2193 | * @oob_required: must write chip->oob_poi to OOB |
1da177e4 | 2194 | * |
8b6e50c9 BN |
2195 | * The hw generator calculates the error syndrome automatically. Therefore we |
2196 | * need a special oob layout and handling. | |
f75e5097 | 2197 | */ |
fdbad98d | 2198 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
2199 | struct nand_chip *chip, |
2200 | const uint8_t *buf, int oob_required) | |
1da177e4 | 2201 | { |
f75e5097 TG |
2202 | int i, eccsize = chip->ecc.size; |
2203 | int eccbytes = chip->ecc.bytes; | |
2204 | int eccsteps = chip->ecc.steps; | |
2205 | const uint8_t *p = buf; | |
2206 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2207 | |
f75e5097 | 2208 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2209 | |
f75e5097 TG |
2210 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2211 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2212 | |
f75e5097 TG |
2213 | if (chip->ecc.prepad) { |
2214 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2215 | oob += chip->ecc.prepad; | |
2216 | } | |
2217 | ||
2218 | chip->ecc.calculate(mtd, p, oob); | |
2219 | chip->write_buf(mtd, oob, eccbytes); | |
2220 | oob += eccbytes; | |
2221 | ||
2222 | if (chip->ecc.postpad) { | |
2223 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2224 | oob += chip->ecc.postpad; | |
1da177e4 | 2225 | } |
1da177e4 | 2226 | } |
f75e5097 TG |
2227 | |
2228 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2229 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2230 | if (i) |
2231 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2232 | |
2233 | return 0; | |
f75e5097 TG |
2234 | } |
2235 | ||
2236 | /** | |
956e944c | 2237 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2238 | * @mtd: MTD device structure |
2239 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2240 | * @offset: address offset within the page |
2241 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2242 | * @buf: the data to write |
1fbb938d | 2243 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2244 | * @page: page number to write |
2245 | * @cached: cached programming | |
2246 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2247 | */ |
2248 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
2249 | uint32_t offset, int data_len, const uint8_t *buf, |
2250 | int oob_required, int page, int cached, int raw) | |
f75e5097 | 2251 | { |
837a6ba4 GP |
2252 | int status, subpage; |
2253 | ||
2254 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2255 | chip->ecc.write_subpage) | |
2256 | subpage = offset || (data_len < mtd->writesize); | |
2257 | else | |
2258 | subpage = 0; | |
f75e5097 TG |
2259 | |
2260 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2261 | ||
956e944c | 2262 | if (unlikely(raw)) |
837a6ba4 GP |
2263 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
2264 | oob_required); | |
2265 | else if (subpage) | |
2266 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
2267 | buf, oob_required); | |
956e944c | 2268 | else |
fdbad98d JW |
2269 | status = chip->ecc.write_page(mtd, chip, buf, oob_required); |
2270 | ||
2271 | if (status < 0) | |
2272 | return status; | |
f75e5097 TG |
2273 | |
2274 | /* | |
7854d3f7 | 2275 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2276 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2277 | */ |
2278 | cached = 0; | |
2279 | ||
3239a6cd | 2280 | if (!cached || !NAND_HAS_CACHEPROG(chip)) { |
f75e5097 TG |
2281 | |
2282 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2283 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2284 | /* |
2285 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2286 | * available. |
f75e5097 TG |
2287 | */ |
2288 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2289 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2290 | page); | |
2291 | ||
2292 | if (status & NAND_STATUS_FAIL) | |
2293 | return -EIO; | |
2294 | } else { | |
2295 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2296 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2297 | } |
2298 | ||
f75e5097 | 2299 | return 0; |
1da177e4 LT |
2300 | } |
2301 | ||
8593fbc6 | 2302 | /** |
7854d3f7 | 2303 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2304 | * @mtd: MTD device structure |
8b6e50c9 BN |
2305 | * @oob: oob data buffer |
2306 | * @len: oob data write length | |
2307 | * @ops: oob ops structure | |
8593fbc6 | 2308 | */ |
f722013e TAA |
2309 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2310 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2311 | { |
f722013e TAA |
2312 | struct nand_chip *chip = mtd->priv; |
2313 | ||
2314 | /* | |
2315 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2316 | * data from a previous OOB read. | |
2317 | */ | |
2318 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2319 | ||
f8ac0414 | 2320 | switch (ops->mode) { |
8593fbc6 | 2321 | |
0612b9dd BN |
2322 | case MTD_OPS_PLACE_OOB: |
2323 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2324 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2325 | return oob + len; | |
2326 | ||
0612b9dd | 2327 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2328 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2329 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2330 | size_t bytes = 0; | |
8593fbc6 | 2331 | |
f8ac0414 | 2332 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2333 | /* Write request not from offset 0? */ |
7bc3312b TG |
2334 | if (unlikely(woffs)) { |
2335 | if (woffs >= free->length) { | |
2336 | woffs -= free->length; | |
2337 | continue; | |
2338 | } | |
2339 | boffs = free->offset + woffs; | |
2340 | bytes = min_t(size_t, len, | |
2341 | (free->length - woffs)); | |
2342 | woffs = 0; | |
2343 | } else { | |
2344 | bytes = min_t(size_t, len, free->length); | |
2345 | boffs = free->offset; | |
2346 | } | |
8b0036ee | 2347 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2348 | oob += bytes; |
2349 | } | |
2350 | return oob; | |
2351 | } | |
2352 | default: | |
2353 | BUG(); | |
2354 | } | |
2355 | return NULL; | |
2356 | } | |
2357 | ||
f8ac0414 | 2358 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2359 | |
2360 | /** | |
7854d3f7 | 2361 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2362 | * @mtd: MTD device structure |
2363 | * @to: offset to write to | |
2364 | * @ops: oob operations description structure | |
1da177e4 | 2365 | * |
8b6e50c9 | 2366 | * NAND write with ECC. |
1da177e4 | 2367 | */ |
8593fbc6 TG |
2368 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2369 | struct mtd_oob_ops *ops) | |
1da177e4 | 2370 | { |
29072b96 | 2371 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2372 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2373 | uint32_t writelen = ops->len; |
782ce79a ML |
2374 | |
2375 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2376 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2377 | mtd->oobavail : mtd->oobsize; |
2378 | ||
8593fbc6 TG |
2379 | uint8_t *oob = ops->oobbuf; |
2380 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2381 | int ret; |
e47f3db4 | 2382 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2383 | |
8593fbc6 | 2384 | ops->retlen = 0; |
29072b96 TG |
2385 | if (!writelen) |
2386 | return 0; | |
1da177e4 | 2387 | |
8b6e50c9 | 2388 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2389 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2390 | pr_notice("%s: attempt to write non page aligned data\n", |
2391 | __func__); | |
1da177e4 LT |
2392 | return -EINVAL; |
2393 | } | |
2394 | ||
29072b96 | 2395 | column = to & (mtd->writesize - 1); |
1da177e4 | 2396 | |
6a930961 TG |
2397 | chipnr = (int)(to >> chip->chip_shift); |
2398 | chip->select_chip(mtd, chipnr); | |
2399 | ||
1da177e4 | 2400 | /* Check, if it is write protected */ |
b0bb6903 HS |
2401 | if (nand_check_wp(mtd)) { |
2402 | ret = -EIO; | |
2403 | goto err_out; | |
2404 | } | |
1da177e4 | 2405 | |
f75e5097 TG |
2406 | realpage = (int)(to >> chip->page_shift); |
2407 | page = realpage & chip->pagemask; | |
2408 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2409 | ||
2410 | /* Invalidate the page cache, when we write to the cached page */ | |
537ab1bd BN |
2411 | if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && |
2412 | ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) | |
ace4dfee | 2413 | chip->pagebuf = -1; |
61b03bd7 | 2414 | |
782ce79a | 2415 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2416 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2417 | ret = -EINVAL; | |
2418 | goto err_out; | |
2419 | } | |
782ce79a | 2420 | |
f8ac0414 | 2421 | while (1) { |
29072b96 | 2422 | int bytes = mtd->writesize; |
f75e5097 | 2423 | int cached = writelen > bytes && page != blockmask; |
29072b96 | 2424 | uint8_t *wbuf = buf; |
66507c7b KD |
2425 | int use_bufpoi; |
2426 | int part_pagewr = (column || writelen < (mtd->writesize - 1)); | |
2427 | ||
2428 | if (part_pagewr) | |
2429 | use_bufpoi = 1; | |
2430 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
2431 | use_bufpoi = !virt_addr_valid(buf); | |
2432 | else | |
2433 | use_bufpoi = 0; | |
29072b96 | 2434 | |
66507c7b KD |
2435 | /* Partial page write?, or need to use bounce buffer */ |
2436 | if (use_bufpoi) { | |
2437 | pr_debug("%s: using write bounce buffer for buf@%p\n", | |
2438 | __func__, buf); | |
29072b96 | 2439 | cached = 0; |
66507c7b KD |
2440 | if (part_pagewr) |
2441 | bytes = min_t(int, bytes - column, writelen); | |
29072b96 TG |
2442 | chip->pagebuf = -1; |
2443 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2444 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2445 | wbuf = chip->buffers->databuf; | |
2446 | } | |
1da177e4 | 2447 | |
782ce79a ML |
2448 | if (unlikely(oob)) { |
2449 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2450 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2451 | oobwritelen -= len; |
f722013e TAA |
2452 | } else { |
2453 | /* We still need to erase leftover OOB data */ | |
2454 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2455 | } |
837a6ba4 GP |
2456 | ret = chip->write_page(mtd, chip, column, bytes, wbuf, |
2457 | oob_required, page, cached, | |
2458 | (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2459 | if (ret) |
2460 | break; | |
2461 | ||
2462 | writelen -= bytes; | |
2463 | if (!writelen) | |
2464 | break; | |
2465 | ||
29072b96 | 2466 | column = 0; |
f75e5097 TG |
2467 | buf += bytes; |
2468 | realpage++; | |
2469 | ||
2470 | page = realpage & chip->pagemask; | |
2471 | /* Check, if we cross a chip boundary */ | |
2472 | if (!page) { | |
2473 | chipnr++; | |
2474 | chip->select_chip(mtd, -1); | |
2475 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2476 | } |
2477 | } | |
8593fbc6 | 2478 | |
8593fbc6 | 2479 | ops->retlen = ops->len - writelen; |
7014568b VW |
2480 | if (unlikely(oob)) |
2481 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2482 | |
2483 | err_out: | |
2484 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2485 | return ret; |
2486 | } | |
2487 | ||
2af7c653 SK |
2488 | /** |
2489 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2490 | * @mtd: MTD device structure |
2491 | * @to: offset to write to | |
2492 | * @len: number of bytes to write | |
2493 | * @retlen: pointer to variable to store the number of written bytes | |
2494 | * @buf: the data to write | |
2af7c653 SK |
2495 | * |
2496 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2497 | * may for example be called by mtdoops when writing an oops while in panic. | |
2498 | */ | |
2499 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2500 | size_t *retlen, const uint8_t *buf) | |
2501 | { | |
2502 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2503 | struct mtd_oob_ops ops; |
2af7c653 SK |
2504 | int ret; |
2505 | ||
8b6e50c9 | 2506 | /* Wait for the device to get ready */ |
2af7c653 SK |
2507 | panic_nand_wait(mtd, chip, 400); |
2508 | ||
8b6e50c9 | 2509 | /* Grab the device */ |
2af7c653 SK |
2510 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2511 | ||
4a89ff88 BN |
2512 | ops.len = len; |
2513 | ops.datbuf = (uint8_t *)buf; | |
2514 | ops.oobbuf = NULL; | |
11041ae6 | 2515 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2516 | |
4a89ff88 | 2517 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2518 | |
4a89ff88 | 2519 | *retlen = ops.retlen; |
2af7c653 SK |
2520 | return ret; |
2521 | } | |
2522 | ||
f75e5097 | 2523 | /** |
8593fbc6 | 2524 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2525 | * @mtd: MTD device structure |
2526 | * @to: offset to write to | |
2527 | * @len: number of bytes to write | |
2528 | * @retlen: pointer to variable to store the number of written bytes | |
2529 | * @buf: the data to write | |
f75e5097 | 2530 | * |
8b6e50c9 | 2531 | * NAND write with ECC. |
f75e5097 | 2532 | */ |
8593fbc6 TG |
2533 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2534 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2535 | { |
4a89ff88 | 2536 | struct mtd_oob_ops ops; |
f75e5097 TG |
2537 | int ret; |
2538 | ||
6a8214aa | 2539 | nand_get_device(mtd, FL_WRITING); |
4a89ff88 BN |
2540 | ops.len = len; |
2541 | ops.datbuf = (uint8_t *)buf; | |
2542 | ops.oobbuf = NULL; | |
11041ae6 | 2543 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2544 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2545 | *retlen = ops.retlen; |
f75e5097 | 2546 | nand_release_device(mtd); |
8593fbc6 | 2547 | return ret; |
f75e5097 | 2548 | } |
7314e9e7 | 2549 | |
1da177e4 | 2550 | /** |
8593fbc6 | 2551 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2552 | * @mtd: MTD device structure |
2553 | * @to: offset to write to | |
2554 | * @ops: oob operation description structure | |
1da177e4 | 2555 | * |
8b6e50c9 | 2556 | * NAND write out-of-band. |
1da177e4 | 2557 | */ |
8593fbc6 TG |
2558 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2559 | struct mtd_oob_ops *ops) | |
1da177e4 | 2560 | { |
03736155 | 2561 | int chipnr, page, status, len; |
ace4dfee | 2562 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2563 | |
289c0522 | 2564 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2565 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2566 | |
0612b9dd | 2567 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2568 | len = chip->ecc.layout->oobavail; |
2569 | else | |
2570 | len = mtd->oobsize; | |
2571 | ||
1da177e4 | 2572 | /* Do not allow write past end of page */ |
03736155 | 2573 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2574 | pr_debug("%s: attempt to write past end of page\n", |
2575 | __func__); | |
1da177e4 LT |
2576 | return -EINVAL; |
2577 | } | |
2578 | ||
03736155 | 2579 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2580 | pr_debug("%s: attempt to start write outside oob\n", |
2581 | __func__); | |
03736155 AH |
2582 | return -EINVAL; |
2583 | } | |
2584 | ||
775adc3d | 2585 | /* Do not allow write past end of device */ |
03736155 AH |
2586 | if (unlikely(to >= mtd->size || |
2587 | ops->ooboffs + ops->ooblen > | |
2588 | ((mtd->size >> chip->page_shift) - | |
2589 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2590 | pr_debug("%s: attempt to write beyond end of device\n", |
2591 | __func__); | |
03736155 AH |
2592 | return -EINVAL; |
2593 | } | |
2594 | ||
7314e9e7 | 2595 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2596 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2597 | |
7314e9e7 TG |
2598 | /* Shift to get page */ |
2599 | page = (int)(to >> chip->page_shift); | |
2600 | ||
2601 | /* | |
2602 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2603 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2604 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2605 | * it in the doc2000 driver in August 1999. dwmw2. | |
2606 | */ | |
ace4dfee | 2607 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2608 | |
2609 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2610 | if (nand_check_wp(mtd)) { |
2611 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2612 | return -EROFS; |
b0bb6903 | 2613 | } |
61b03bd7 | 2614 | |
1da177e4 | 2615 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2616 | if (page == chip->pagebuf) |
2617 | chip->pagebuf = -1; | |
1da177e4 | 2618 | |
f722013e | 2619 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2620 | |
0612b9dd | 2621 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2622 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2623 | else | |
2624 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2625 | |
b0bb6903 HS |
2626 | chip->select_chip(mtd, -1); |
2627 | ||
7bc3312b TG |
2628 | if (status) |
2629 | return status; | |
1da177e4 | 2630 | |
7014568b | 2631 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2632 | |
7bc3312b | 2633 | return 0; |
8593fbc6 TG |
2634 | } |
2635 | ||
2636 | /** | |
2637 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2638 | * @mtd: MTD device structure |
2639 | * @to: offset to write to | |
2640 | * @ops: oob operation description structure | |
8593fbc6 TG |
2641 | */ |
2642 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2643 | struct mtd_oob_ops *ops) | |
2644 | { | |
8593fbc6 TG |
2645 | int ret = -ENOTSUPP; |
2646 | ||
2647 | ops->retlen = 0; | |
2648 | ||
2649 | /* Do not allow writes past end of device */ | |
7014568b | 2650 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2651 | pr_debug("%s: attempt to write beyond end of device\n", |
2652 | __func__); | |
8593fbc6 TG |
2653 | return -EINVAL; |
2654 | } | |
2655 | ||
6a8214aa | 2656 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2657 | |
f8ac0414 | 2658 | switch (ops->mode) { |
0612b9dd BN |
2659 | case MTD_OPS_PLACE_OOB: |
2660 | case MTD_OPS_AUTO_OOB: | |
2661 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2662 | break; |
2663 | ||
2664 | default: | |
2665 | goto out; | |
2666 | } | |
2667 | ||
2668 | if (!ops->datbuf) | |
2669 | ret = nand_do_write_oob(mtd, to, ops); | |
2670 | else | |
2671 | ret = nand_do_write_ops(mtd, to, ops); | |
2672 | ||
7351d3a5 | 2673 | out: |
1da177e4 | 2674 | nand_release_device(mtd); |
1da177e4 LT |
2675 | return ret; |
2676 | } | |
2677 | ||
1da177e4 | 2678 | /** |
49c50b97 | 2679 | * single_erase - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2680 | * @mtd: MTD device structure |
2681 | * @page: the page address of the block which will be erased | |
1da177e4 | 2682 | * |
49c50b97 | 2683 | * Standard erase command for NAND chips. Returns NAND status. |
1da177e4 | 2684 | */ |
49c50b97 | 2685 | static int single_erase(struct mtd_info *mtd, int page) |
1da177e4 | 2686 | { |
ace4dfee | 2687 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2688 | /* Send commands to erase a block */ |
ace4dfee TG |
2689 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2690 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
49c50b97 BN |
2691 | |
2692 | return chip->waitfunc(mtd, chip); | |
1da177e4 LT |
2693 | } |
2694 | ||
1da177e4 LT |
2695 | /** |
2696 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2697 | * @mtd: MTD device structure |
2698 | * @instr: erase instruction | |
1da177e4 | 2699 | * |
8b6e50c9 | 2700 | * Erase one ore more blocks. |
1da177e4 | 2701 | */ |
e0c7d767 | 2702 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2703 | { |
e0c7d767 | 2704 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2705 | } |
61b03bd7 | 2706 | |
1da177e4 | 2707 | /** |
7854d3f7 | 2708 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2709 | * @mtd: MTD device structure |
2710 | * @instr: erase instruction | |
2711 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2712 | * |
8b6e50c9 | 2713 | * Erase one ore more blocks. |
1da177e4 | 2714 | */ |
ace4dfee TG |
2715 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2716 | int allowbbt) | |
1da177e4 | 2717 | { |
69423d99 | 2718 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2719 | struct nand_chip *chip = mtd->priv; |
69423d99 | 2720 | loff_t len; |
1da177e4 | 2721 | |
289c0522 BN |
2722 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2723 | __func__, (unsigned long long)instr->addr, | |
2724 | (unsigned long long)instr->len); | |
1da177e4 | 2725 | |
6fe5a6ac | 2726 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2727 | return -EINVAL; |
1da177e4 | 2728 | |
1da177e4 | 2729 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2730 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2731 | |
2732 | /* Shift to get first page */ | |
ace4dfee TG |
2733 | page = (int)(instr->addr >> chip->page_shift); |
2734 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2735 | |
2736 | /* Calculate pages in each block */ | |
ace4dfee | 2737 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2738 | |
2739 | /* Select the NAND device */ | |
ace4dfee | 2740 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2741 | |
1da177e4 LT |
2742 | /* Check, if it is write protected */ |
2743 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2744 | pr_debug("%s: device is write protected!\n", |
2745 | __func__); | |
1da177e4 LT |
2746 | instr->state = MTD_ERASE_FAILED; |
2747 | goto erase_exit; | |
2748 | } | |
2749 | ||
2750 | /* Loop through the pages */ | |
2751 | len = instr->len; | |
2752 | ||
2753 | instr->state = MTD_ERASING; | |
2754 | ||
2755 | while (len) { | |
12183a20 | 2756 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2757 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2758 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2759 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2760 | __func__, page); | |
1da177e4 LT |
2761 | instr->state = MTD_ERASE_FAILED; |
2762 | goto erase_exit; | |
2763 | } | |
61b03bd7 | 2764 | |
ace4dfee TG |
2765 | /* |
2766 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2767 | * contains the current cached page. |
ace4dfee TG |
2768 | */ |
2769 | if (page <= chip->pagebuf && chip->pagebuf < | |
2770 | (page + pages_per_block)) | |
2771 | chip->pagebuf = -1; | |
1da177e4 | 2772 | |
49c50b97 | 2773 | status = chip->erase(mtd, page & chip->pagemask); |
1da177e4 | 2774 | |
ace4dfee TG |
2775 | /* |
2776 | * See if operation failed and additional status checks are | |
2777 | * available | |
2778 | */ | |
2779 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2780 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2781 | status, page); | |
068e3c0a | 2782 | |
1da177e4 | 2783 | /* See if block erase succeeded */ |
a4ab4c5d | 2784 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2785 | pr_debug("%s: failed erase, page 0x%08x\n", |
2786 | __func__, page); | |
1da177e4 | 2787 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2788 | instr->fail_addr = |
2789 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2790 | goto erase_exit; |
2791 | } | |
30f464b7 | 2792 | |
1da177e4 | 2793 | /* Increment page address and decrement length */ |
daae74ca | 2794 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
2795 | page += pages_per_block; |
2796 | ||
2797 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2798 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2799 | chipnr++; |
ace4dfee TG |
2800 | chip->select_chip(mtd, -1); |
2801 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2802 | } |
2803 | } | |
2804 | instr->state = MTD_ERASE_DONE; | |
2805 | ||
7351d3a5 | 2806 | erase_exit: |
1da177e4 LT |
2807 | |
2808 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2809 | |
2810 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2811 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2812 | nand_release_device(mtd); |
2813 | ||
49defc01 DW |
2814 | /* Do call back function */ |
2815 | if (!ret) | |
2816 | mtd_erase_callback(instr); | |
2817 | ||
1da177e4 LT |
2818 | /* Return more or less happy */ |
2819 | return ret; | |
2820 | } | |
2821 | ||
2822 | /** | |
2823 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2824 | * @mtd: MTD device structure |
1da177e4 | 2825 | * |
8b6e50c9 | 2826 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2827 | */ |
e0c7d767 | 2828 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2829 | { |
289c0522 | 2830 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2831 | |
2832 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 2833 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 2834 | /* Release it and go back */ |
e0c7d767 | 2835 | nand_release_device(mtd); |
1da177e4 LT |
2836 | } |
2837 | ||
1da177e4 | 2838 | /** |
ace4dfee | 2839 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2840 | * @mtd: MTD device structure |
2841 | * @offs: offset relative to mtd start | |
1da177e4 | 2842 | */ |
ace4dfee | 2843 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 2844 | { |
ace4dfee | 2845 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2846 | } |
2847 | ||
2848 | /** | |
ace4dfee | 2849 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2850 | * @mtd: MTD device structure |
2851 | * @ofs: offset relative to mtd start | |
1da177e4 | 2852 | */ |
e0c7d767 | 2853 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2854 | { |
1da177e4 LT |
2855 | int ret; |
2856 | ||
f8ac0414 FF |
2857 | ret = nand_block_isbad(mtd, ofs); |
2858 | if (ret) { | |
8b6e50c9 | 2859 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
2860 | if (ret > 0) |
2861 | return 0; | |
e0c7d767 DW |
2862 | return ret; |
2863 | } | |
1da177e4 | 2864 | |
5a0edb25 | 2865 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
2866 | } |
2867 | ||
7db03ecc HS |
2868 | /** |
2869 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
2870 | * @mtd: MTD device structure | |
2871 | * @chip: nand chip info structure | |
2872 | * @addr: feature address. | |
2873 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2874 | */ | |
2875 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2876 | int addr, uint8_t *subfeature_param) | |
2877 | { | |
2878 | int status; | |
05f78359 | 2879 | int i; |
7db03ecc | 2880 | |
d914c932 DM |
2881 | if (!chip->onfi_version || |
2882 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
2883 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
2884 | return -EINVAL; |
2885 | ||
2886 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
2887 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
2888 | chip->write_byte(mtd, subfeature_param[i]); | |
2889 | ||
7db03ecc HS |
2890 | status = chip->waitfunc(mtd, chip); |
2891 | if (status & NAND_STATUS_FAIL) | |
2892 | return -EIO; | |
2893 | return 0; | |
2894 | } | |
2895 | ||
2896 | /** | |
2897 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
2898 | * @mtd: MTD device structure | |
2899 | * @chip: nand chip info structure | |
2900 | * @addr: feature address. | |
2901 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2902 | */ | |
2903 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2904 | int addr, uint8_t *subfeature_param) | |
2905 | { | |
05f78359 UKK |
2906 | int i; |
2907 | ||
d914c932 DM |
2908 | if (!chip->onfi_version || |
2909 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
2910 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
2911 | return -EINVAL; |
2912 | ||
2913 | /* clear the sub feature parameters */ | |
2914 | memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); | |
2915 | ||
2916 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); | |
05f78359 UKK |
2917 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
2918 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
2919 | return 0; |
2920 | } | |
2921 | ||
962034f4 VW |
2922 | /** |
2923 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 2924 | * @mtd: MTD device structure |
962034f4 VW |
2925 | */ |
2926 | static int nand_suspend(struct mtd_info *mtd) | |
2927 | { | |
6a8214aa | 2928 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2929 | } |
2930 | ||
2931 | /** | |
2932 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 2933 | * @mtd: MTD device structure |
962034f4 VW |
2934 | */ |
2935 | static void nand_resume(struct mtd_info *mtd) | |
2936 | { | |
ace4dfee | 2937 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2938 | |
ace4dfee | 2939 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2940 | nand_release_device(mtd); |
2941 | else | |
d0370219 BN |
2942 | pr_err("%s called for a chip which is not in suspended state\n", |
2943 | __func__); | |
962034f4 VW |
2944 | } |
2945 | ||
72ea4036 SB |
2946 | /** |
2947 | * nand_shutdown - [MTD Interface] Finish the current NAND operation and | |
2948 | * prevent further operations | |
2949 | * @mtd: MTD device structure | |
2950 | */ | |
2951 | static void nand_shutdown(struct mtd_info *mtd) | |
2952 | { | |
2953 | nand_get_device(mtd, FL_SHUTDOWN); | |
2954 | } | |
2955 | ||
8b6e50c9 | 2956 | /* Set default functions */ |
ace4dfee | 2957 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2958 | { |
1da177e4 | 2959 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2960 | if (!chip->chip_delay) |
2961 | chip->chip_delay = 20; | |
1da177e4 LT |
2962 | |
2963 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2964 | if (chip->cmdfunc == NULL) |
2965 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2966 | |
2967 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2968 | if (chip->waitfunc == NULL) |
2969 | chip->waitfunc = nand_wait; | |
2970 | ||
2971 | if (!chip->select_chip) | |
2972 | chip->select_chip = nand_select_chip; | |
68e80780 | 2973 | |
4204cccd HS |
2974 | /* set for ONFI nand */ |
2975 | if (!chip->onfi_set_features) | |
2976 | chip->onfi_set_features = nand_onfi_set_features; | |
2977 | if (!chip->onfi_get_features) | |
2978 | chip->onfi_get_features = nand_onfi_get_features; | |
2979 | ||
68e80780 BN |
2980 | /* If called twice, pointers that depend on busw may need to be reset */ |
2981 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
2982 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
2983 | if (!chip->read_word) | |
2984 | chip->read_word = nand_read_word; | |
2985 | if (!chip->block_bad) | |
2986 | chip->block_bad = nand_block_bad; | |
2987 | if (!chip->block_markbad) | |
2988 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 2989 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 2990 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
2991 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
2992 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 2993 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 2994 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
2995 | if (!chip->scan_bbt) |
2996 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2997 | |
2998 | if (!chip->controller) { | |
2999 | chip->controller = &chip->hwcontrol; | |
3000 | spin_lock_init(&chip->controller->lock); | |
3001 | init_waitqueue_head(&chip->controller->wq); | |
3002 | } | |
3003 | ||
7aa65bfd TG |
3004 | } |
3005 | ||
8b6e50c9 | 3006 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
3007 | static void sanitize_string(uint8_t *s, size_t len) |
3008 | { | |
3009 | ssize_t i; | |
3010 | ||
8b6e50c9 | 3011 | /* Null terminate */ |
d1e1f4e4 FF |
3012 | s[len - 1] = 0; |
3013 | ||
8b6e50c9 | 3014 | /* Remove non printable chars */ |
d1e1f4e4 FF |
3015 | for (i = 0; i < len - 1; i++) { |
3016 | if (s[i] < ' ' || s[i] > 127) | |
3017 | s[i] = '?'; | |
3018 | } | |
3019 | ||
8b6e50c9 | 3020 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
3021 | strim(s); |
3022 | } | |
3023 | ||
3024 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
3025 | { | |
3026 | int i; | |
3027 | while (len--) { | |
3028 | crc ^= *p++ << 8; | |
3029 | for (i = 0; i < 8; i++) | |
3030 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
3031 | } | |
3032 | ||
3033 | return crc; | |
3034 | } | |
3035 | ||
6dcbe0cd HS |
3036 | /* Parse the Extended Parameter Page. */ |
3037 | static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, | |
3038 | struct nand_chip *chip, struct nand_onfi_params *p) | |
3039 | { | |
3040 | struct onfi_ext_param_page *ep; | |
3041 | struct onfi_ext_section *s; | |
3042 | struct onfi_ext_ecc_info *ecc; | |
3043 | uint8_t *cursor; | |
3044 | int ret = -EINVAL; | |
3045 | int len; | |
3046 | int i; | |
3047 | ||
3048 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
3049 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
3050 | if (!ep) |
3051 | return -ENOMEM; | |
6dcbe0cd HS |
3052 | |
3053 | /* Send our own NAND_CMD_PARAM. */ | |
3054 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
3055 | ||
3056 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
3057 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
3058 | sizeof(*p) * p->num_of_param_pages , -1); | |
3059 | ||
3060 | /* Read out the Extended Parameter Page. */ | |
3061 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
3062 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
3063 | != le16_to_cpu(ep->crc))) { | |
3064 | pr_debug("fail in the CRC.\n"); | |
3065 | goto ext_out; | |
3066 | } | |
3067 | ||
3068 | /* | |
3069 | * Check the signature. | |
3070 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
3071 | */ | |
3072 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3073 | pr_debug("The signature is invalid.\n"); | |
3074 | goto ext_out; | |
3075 | } | |
3076 | ||
3077 | /* find the ECC section. */ | |
3078 | cursor = (uint8_t *)(ep + 1); | |
3079 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3080 | s = ep->sections + i; | |
3081 | if (s->type == ONFI_SECTION_TYPE_2) | |
3082 | break; | |
3083 | cursor += s->length * 16; | |
3084 | } | |
3085 | if (i == ONFI_EXT_SECTION_MAX) { | |
3086 | pr_debug("We can not find the ECC section.\n"); | |
3087 | goto ext_out; | |
3088 | } | |
3089 | ||
3090 | /* get the info we want. */ | |
3091 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3092 | ||
4ae7d228 BN |
3093 | if (!ecc->codeword_size) { |
3094 | pr_debug("Invalid codeword size\n"); | |
3095 | goto ext_out; | |
6dcbe0cd HS |
3096 | } |
3097 | ||
4ae7d228 BN |
3098 | chip->ecc_strength_ds = ecc->ecc_bits; |
3099 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3100 | ret = 0; |
6dcbe0cd HS |
3101 | |
3102 | ext_out: | |
3103 | kfree(ep); | |
3104 | return ret; | |
3105 | } | |
3106 | ||
8429bb39 BN |
3107 | static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) |
3108 | { | |
3109 | struct nand_chip *chip = mtd->priv; | |
3110 | uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; | |
3111 | ||
3112 | return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, | |
3113 | feature); | |
3114 | } | |
3115 | ||
3116 | /* | |
3117 | * Configure chip properties from Micron vendor-specific ONFI table | |
3118 | */ | |
3119 | static void nand_onfi_detect_micron(struct nand_chip *chip, | |
3120 | struct nand_onfi_params *p) | |
3121 | { | |
3122 | struct nand_onfi_vendor_micron *micron = (void *)p->vendor; | |
3123 | ||
3124 | if (le16_to_cpu(p->vendor_revision) < 1) | |
3125 | return; | |
3126 | ||
3127 | chip->read_retries = micron->read_retry_options; | |
3128 | chip->setup_read_retry = nand_setup_read_retry_micron; | |
3129 | } | |
3130 | ||
6fb277ba | 3131 | /* |
8b6e50c9 | 3132 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
3133 | */ |
3134 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 3135 | int *busw) |
6fb277ba FF |
3136 | { |
3137 | struct nand_onfi_params *p = &chip->onfi_params; | |
bd9c6e99 | 3138 | int i, j; |
6fb277ba FF |
3139 | int val; |
3140 | ||
7854d3f7 | 3141 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3142 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3143 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3144 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3145 | return 0; | |
3146 | ||
6fb277ba FF |
3147 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3148 | for (i = 0; i < 3; i++) { | |
bd9c6e99 BN |
3149 | for (j = 0; j < sizeof(*p); j++) |
3150 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
6fb277ba FF |
3151 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
3152 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3153 | break; |
3154 | } | |
3155 | } | |
3156 | ||
c7f23a70 BN |
3157 | if (i == 3) { |
3158 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3159 | return 0; |
c7f23a70 | 3160 | } |
6fb277ba | 3161 | |
8b6e50c9 | 3162 | /* Check version */ |
6fb277ba | 3163 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3164 | if (val & (1 << 5)) |
3165 | chip->onfi_version = 23; | |
3166 | else if (val & (1 << 4)) | |
6fb277ba FF |
3167 | chip->onfi_version = 22; |
3168 | else if (val & (1 << 3)) | |
3169 | chip->onfi_version = 21; | |
3170 | else if (val & (1 << 2)) | |
3171 | chip->onfi_version = 20; | |
b7b1a29d | 3172 | else if (val & (1 << 1)) |
6fb277ba | 3173 | chip->onfi_version = 10; |
b7b1a29d BN |
3174 | |
3175 | if (!chip->onfi_version) { | |
20171642 | 3176 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3177 | return 0; |
3178 | } | |
6fb277ba FF |
3179 | |
3180 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3181 | sanitize_string(p->model, sizeof(p->model)); | |
3182 | if (!mtd->name) | |
3183 | mtd->name = p->model; | |
4355b70c | 3184 | |
6fb277ba | 3185 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3186 | |
3187 | /* | |
3188 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3189 | * (don't ask me who thought of this...). MTD assumes that these | |
3190 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3191 | */ | |
3192 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3193 | mtd->erasesize *= mtd->writesize; | |
3194 | ||
6fb277ba | 3195 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3196 | |
3197 | /* See erasesize comment */ | |
3198 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3199 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3200 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 HS |
3201 | |
3202 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) | |
08c248fb | 3203 | *busw = NAND_BUSWIDTH_16; |
e2985fc1 HS |
3204 | else |
3205 | *busw = 0; | |
6fb277ba | 3206 | |
10c86bab HS |
3207 | if (p->ecc_bits != 0xff) { |
3208 | chip->ecc_strength_ds = p->ecc_bits; | |
3209 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3210 | } else if (chip->onfi_version >= 21 && |
3211 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3212 | ||
3213 | /* | |
3214 | * The nand_flash_detect_ext_param_page() uses the | |
3215 | * Change Read Column command which maybe not supported | |
3216 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3217 | * now. We do not replace user supplied command function. | |
3218 | */ | |
3219 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3220 | chip->cmdfunc = nand_command_lp; | |
3221 | ||
3222 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
3223 | if (nand_flash_detect_ext_param_page(mtd, chip, p)) | |
c7f23a70 BN |
3224 | pr_warn("Failed to detect ONFI extended param page\n"); |
3225 | } else { | |
3226 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3227 | } |
3228 | ||
8429bb39 BN |
3229 | if (p->jedec_id == NAND_MFR_MICRON) |
3230 | nand_onfi_detect_micron(chip, p); | |
3231 | ||
6fb277ba FF |
3232 | return 1; |
3233 | } | |
3234 | ||
91361818 HS |
3235 | /* |
3236 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
3237 | */ | |
3238 | static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, | |
3239 | int *busw) | |
3240 | { | |
3241 | struct nand_jedec_params *p = &chip->jedec_params; | |
3242 | struct jedec_ecc_info *ecc; | |
3243 | int val; | |
3244 | int i, j; | |
3245 | ||
3246 | /* Try JEDEC for unknown chip or LP */ | |
3247 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); | |
3248 | if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || | |
3249 | chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || | |
3250 | chip->read_byte(mtd) != 'C') | |
3251 | return 0; | |
3252 | ||
3253 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); | |
3254 | for (i = 0; i < 3; i++) { | |
3255 | for (j = 0; j < sizeof(*p); j++) | |
3256 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
3257 | ||
3258 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
3259 | le16_to_cpu(p->crc)) | |
3260 | break; | |
3261 | } | |
3262 | ||
3263 | if (i == 3) { | |
3264 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
3265 | return 0; | |
3266 | } | |
3267 | ||
3268 | /* Check version */ | |
3269 | val = le16_to_cpu(p->revision); | |
3270 | if (val & (1 << 2)) | |
3271 | chip->jedec_version = 10; | |
3272 | else if (val & (1 << 1)) | |
3273 | chip->jedec_version = 1; /* vendor specific version */ | |
3274 | ||
3275 | if (!chip->jedec_version) { | |
3276 | pr_info("unsupported JEDEC version: %d\n", val); | |
3277 | return 0; | |
3278 | } | |
3279 | ||
3280 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3281 | sanitize_string(p->model, sizeof(p->model)); | |
3282 | if (!mtd->name) | |
3283 | mtd->name = p->model; | |
3284 | ||
3285 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
3286 | ||
3287 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3288 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3289 | mtd->erasesize *= mtd->writesize; | |
3290 | ||
3291 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
3292 | ||
3293 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3294 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
3295 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
3296 | chip->bits_per_cell = p->bits_per_cell; | |
3297 | ||
3298 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
3299 | *busw = NAND_BUSWIDTH_16; | |
3300 | else | |
3301 | *busw = 0; | |
3302 | ||
3303 | /* ECC info */ | |
3304 | ecc = &p->ecc_info[0]; | |
3305 | ||
3306 | if (ecc->codeword_size >= 9) { | |
3307 | chip->ecc_strength_ds = ecc->ecc_bits; | |
3308 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
3309 | } else { | |
3310 | pr_warn("Invalid codeword size\n"); | |
3311 | } | |
3312 | ||
3313 | return 1; | |
3314 | } | |
3315 | ||
e3b88bd6 BN |
3316 | /* |
3317 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3318 | * @id_data: the ID string | |
3319 | * @arrlen: the length of the @id_data array | |
3320 | * @period: the period of repitition | |
3321 | * | |
3322 | * Check if an ID string is repeated within a given sequence of bytes at | |
3323 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3324 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3325 | * if the repetition has a period of @period; otherwise, returns zero. |
3326 | */ | |
3327 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3328 | { | |
3329 | int i, j; | |
3330 | for (i = 0; i < period; i++) | |
3331 | for (j = i + period; j < arrlen; j += period) | |
3332 | if (id_data[i] != id_data[j]) | |
3333 | return 0; | |
3334 | return 1; | |
3335 | } | |
3336 | ||
3337 | /* | |
3338 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3339 | * @id_data: the ID string | |
3340 | * @arrlen: the length of the @id_data array | |
3341 | ||
3342 | * Returns the length of the ID string, according to known wraparound/trailing | |
3343 | * zero patterns. If no pattern exists, returns the length of the array. | |
3344 | */ | |
3345 | static int nand_id_len(u8 *id_data, int arrlen) | |
3346 | { | |
3347 | int last_nonzero, period; | |
3348 | ||
3349 | /* Find last non-zero byte */ | |
3350 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3351 | if (id_data[last_nonzero]) | |
3352 | break; | |
3353 | ||
3354 | /* All zeros */ | |
3355 | if (last_nonzero < 0) | |
3356 | return 0; | |
3357 | ||
3358 | /* Calculate wraparound period */ | |
3359 | for (period = 1; period < arrlen; period++) | |
3360 | if (nand_id_has_period(id_data, arrlen, period)) | |
3361 | break; | |
3362 | ||
3363 | /* There's a repeated pattern */ | |
3364 | if (period < arrlen) | |
3365 | return period; | |
3366 | ||
3367 | /* There are trailing zeros */ | |
3368 | if (last_nonzero < arrlen - 1) | |
3369 | return last_nonzero + 1; | |
3370 | ||
3371 | /* No pattern detected */ | |
3372 | return arrlen; | |
3373 | } | |
3374 | ||
7db906b7 HS |
3375 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3376 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3377 | { | |
3378 | int bits; | |
3379 | ||
3380 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3381 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3382 | return bits + 1; | |
3383 | } | |
3384 | ||
fc09bbc0 BN |
3385 | /* |
3386 | * Many new NAND share similar device ID codes, which represent the size of the | |
3387 | * chip. The rest of the parameters must be decoded according to generic or | |
3388 | * manufacturer-specific "extended ID" decoding patterns. | |
3389 | */ | |
3390 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3391 | u8 id_data[8], int *busw) | |
3392 | { | |
e3b88bd6 | 3393 | int extid, id_len; |
fc09bbc0 | 3394 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3395 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3396 | /* The 4th id byte is the important one */ |
3397 | extid = id_data[3]; | |
3398 | ||
e3b88bd6 BN |
3399 | id_len = nand_id_len(id_data, 8); |
3400 | ||
fc09bbc0 BN |
3401 | /* |
3402 | * Field definitions are in the following datasheets: | |
3403 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 3404 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 3405 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 3406 | * |
af451af4 BN |
3407 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3408 | * ID to decide what to do. | |
fc09bbc0 | 3409 | */ |
af451af4 | 3410 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
1d0ed69d | 3411 | !nand_is_slc(chip) && id_data[5] != 0x00) { |
fc09bbc0 BN |
3412 | /* Calc pagesize */ |
3413 | mtd->writesize = 2048 << (extid & 0x03); | |
3414 | extid >>= 2; | |
3415 | /* Calc oobsize */ | |
e2d3a35e | 3416 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3417 | case 1: |
3418 | mtd->oobsize = 128; | |
3419 | break; | |
3420 | case 2: | |
3421 | mtd->oobsize = 218; | |
3422 | break; | |
3423 | case 3: | |
3424 | mtd->oobsize = 400; | |
3425 | break; | |
e2d3a35e | 3426 | case 4: |
fc09bbc0 BN |
3427 | mtd->oobsize = 436; |
3428 | break; | |
e2d3a35e BN |
3429 | case 5: |
3430 | mtd->oobsize = 512; | |
3431 | break; | |
3432 | case 6: | |
e2d3a35e BN |
3433 | mtd->oobsize = 640; |
3434 | break; | |
94d04e82 HS |
3435 | case 7: |
3436 | default: /* Other cases are "reserved" (unknown) */ | |
3437 | mtd->oobsize = 1024; | |
3438 | break; | |
fc09bbc0 BN |
3439 | } |
3440 | extid >>= 2; | |
3441 | /* Calc blocksize */ | |
3442 | mtd->erasesize = (128 * 1024) << | |
3443 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3444 | *busw = 0; | |
73ca392f | 3445 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
1d0ed69d | 3446 | !nand_is_slc(chip)) { |
73ca392f BN |
3447 | unsigned int tmp; |
3448 | ||
3449 | /* Calc pagesize */ | |
3450 | mtd->writesize = 2048 << (extid & 0x03); | |
3451 | extid >>= 2; | |
3452 | /* Calc oobsize */ | |
3453 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3454 | case 0: | |
3455 | mtd->oobsize = 128; | |
3456 | break; | |
3457 | case 1: | |
3458 | mtd->oobsize = 224; | |
3459 | break; | |
3460 | case 2: | |
3461 | mtd->oobsize = 448; | |
3462 | break; | |
3463 | case 3: | |
3464 | mtd->oobsize = 64; | |
3465 | break; | |
3466 | case 4: | |
3467 | mtd->oobsize = 32; | |
3468 | break; | |
3469 | case 5: | |
3470 | mtd->oobsize = 16; | |
3471 | break; | |
3472 | default: | |
3473 | mtd->oobsize = 640; | |
3474 | break; | |
3475 | } | |
3476 | extid >>= 2; | |
3477 | /* Calc blocksize */ | |
3478 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3479 | if (tmp < 0x03) | |
3480 | mtd->erasesize = (128 * 1024) << tmp; | |
3481 | else if (tmp == 0x03) | |
3482 | mtd->erasesize = 768 * 1024; | |
3483 | else | |
3484 | mtd->erasesize = (64 * 1024) << tmp; | |
3485 | *busw = 0; | |
fc09bbc0 BN |
3486 | } else { |
3487 | /* Calc pagesize */ | |
3488 | mtd->writesize = 1024 << (extid & 0x03); | |
3489 | extid >>= 2; | |
3490 | /* Calc oobsize */ | |
3491 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3492 | (mtd->writesize >> 9); | |
3493 | extid >>= 2; | |
3494 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3495 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3496 | extid >>= 2; | |
3497 | /* Get buswidth information */ | |
3498 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
60c67382 BN |
3499 | |
3500 | /* | |
3501 | * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per | |
3502 | * 512B page. For Toshiba SLC, we decode the 5th/6th byte as | |
3503 | * follows: | |
3504 | * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, | |
3505 | * 110b -> 24nm | |
3506 | * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC | |
3507 | */ | |
3508 | if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && | |
1d0ed69d | 3509 | nand_is_slc(chip) && |
60c67382 BN |
3510 | (id_data[5] & 0x7) == 0x6 /* 24nm */ && |
3511 | !(id_data[4] & 0x80) /* !BENAND */) { | |
3512 | mtd->oobsize = 32 * mtd->writesize >> 9; | |
3513 | } | |
3514 | ||
fc09bbc0 BN |
3515 | } |
3516 | } | |
3517 | ||
f23a481c BN |
3518 | /* |
3519 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3520 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3521 | * the chip. | |
3522 | */ | |
3523 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3524 | struct nand_flash_dev *type, u8 id_data[8], | |
3525 | int *busw) | |
3526 | { | |
3527 | int maf_id = id_data[0]; | |
3528 | ||
3529 | mtd->erasesize = type->erasesize; | |
3530 | mtd->writesize = type->pagesize; | |
3531 | mtd->oobsize = mtd->writesize / 32; | |
3532 | *busw = type->options & NAND_BUSWIDTH_16; | |
3533 | ||
1c195e90 HS |
3534 | /* All legacy ID NAND are small-page, SLC */ |
3535 | chip->bits_per_cell = 1; | |
3536 | ||
f23a481c BN |
3537 | /* |
3538 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3539 | * some Spansion chips have erasesize that conflicts with size | |
3540 | * listed in nand_ids table. | |
3541 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3542 | */ | |
3543 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3544 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3545 | && mtd->writesize == 512) { | |
3546 | mtd->erasesize = 128 * 1024; | |
3547 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3548 | } | |
3549 | } | |
3550 | ||
7e74c2d7 BN |
3551 | /* |
3552 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3553 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3554 | * page size, cell-type information). | |
3555 | */ | |
3556 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3557 | struct nand_chip *chip, u8 id_data[8]) | |
3558 | { | |
3559 | int maf_id = id_data[0]; | |
3560 | ||
3561 | /* Set the bad block position */ | |
3562 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3563 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3564 | else | |
3565 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3566 | ||
3567 | /* | |
3568 | * Bad block marker is stored in the last page of each block on Samsung | |
3569 | * and Hynix MLC devices; stored in first two pages of each block on | |
3570 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3571 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3572 | */ | |
1d0ed69d | 3573 | if (!nand_is_slc(chip) && |
7e74c2d7 BN |
3574 | (maf_id == NAND_MFR_SAMSUNG || |
3575 | maf_id == NAND_MFR_HYNIX)) | |
3576 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
1d0ed69d | 3577 | else if ((nand_is_slc(chip) && |
7e74c2d7 BN |
3578 | (maf_id == NAND_MFR_SAMSUNG || |
3579 | maf_id == NAND_MFR_HYNIX || | |
3580 | maf_id == NAND_MFR_TOSHIBA || | |
3581 | maf_id == NAND_MFR_AMD || | |
3582 | maf_id == NAND_MFR_MACRONIX)) || | |
3583 | (mtd->writesize == 2048 && | |
3584 | maf_id == NAND_MFR_MICRON)) | |
3585 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3586 | } | |
3587 | ||
ec6e87e3 HS |
3588 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3589 | { | |
3590 | return type->id_len; | |
3591 | } | |
3592 | ||
3593 | static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, | |
3594 | struct nand_flash_dev *type, u8 *id_data, int *busw) | |
3595 | { | |
3596 | if (!strncmp(type->id, id_data, type->id_len)) { | |
3597 | mtd->writesize = type->pagesize; | |
3598 | mtd->erasesize = type->erasesize; | |
3599 | mtd->oobsize = type->oobsize; | |
3600 | ||
7db906b7 | 3601 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3602 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3603 | chip->options |= type->options; | |
57219342 HS |
3604 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3605 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
57a94e24 BB |
3606 | chip->onfi_timing_mode_default = |
3607 | type->onfi_timing_mode_default; | |
ec6e87e3 HS |
3608 | |
3609 | *busw = type->options & NAND_BUSWIDTH_16; | |
3610 | ||
092b6a1d CZ |
3611 | if (!mtd->name) |
3612 | mtd->name = type->name; | |
3613 | ||
ec6e87e3 HS |
3614 | return true; |
3615 | } | |
3616 | return false; | |
3617 | } | |
3618 | ||
7aa65bfd | 3619 | /* |
8b6e50c9 | 3620 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3621 | */ |
3622 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3623 | struct nand_chip *chip, |
7351d3a5 | 3624 | int *maf_id, int *dev_id, |
5e81e88a | 3625 | struct nand_flash_dev *type) |
7aa65bfd | 3626 | { |
bb77082f | 3627 | int busw; |
d1e1f4e4 | 3628 | int i, maf_idx; |
426c457a | 3629 | u8 id_data[8]; |
1da177e4 LT |
3630 | |
3631 | /* Select the device */ | |
ace4dfee | 3632 | chip->select_chip(mtd, 0); |
1da177e4 | 3633 | |
ef89a880 KB |
3634 | /* |
3635 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3636 | * after power-up. |
ef89a880 KB |
3637 | */ |
3638 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3639 | ||
1da177e4 | 3640 | /* Send the command for reading device ID */ |
ace4dfee | 3641 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3642 | |
3643 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3644 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3645 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3646 | |
8b6e50c9 BN |
3647 | /* |
3648 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3649 | * interface concerns can cause random data which looks like a |
3650 | * possibly credible NAND flash to appear. If the two results do | |
3651 | * not match, ignore the device completely. | |
3652 | */ | |
3653 | ||
3654 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3655 | ||
4aef9b78 BN |
3656 | /* Read entire ID string */ |
3657 | for (i = 0; i < 8; i++) | |
426c457a | 3658 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3659 | |
d1e1f4e4 | 3660 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
20171642 | 3661 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
d0370219 | 3662 | *maf_id, *dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
3663 | return ERR_PTR(-ENODEV); |
3664 | } | |
3665 | ||
7aa65bfd | 3666 | if (!type) |
5e81e88a DW |
3667 | type = nand_flash_ids; |
3668 | ||
ec6e87e3 HS |
3669 | for (; type->name != NULL; type++) { |
3670 | if (is_full_id_nand(type)) { | |
3671 | if (find_full_id_nand(mtd, chip, type, id_data, &busw)) | |
3672 | goto ident_done; | |
3673 | } else if (*dev_id == type->dev_id) { | |
3674 | break; | |
3675 | } | |
3676 | } | |
5e81e88a | 3677 | |
d1e1f4e4 FF |
3678 | chip->onfi_version = 0; |
3679 | if (!type->name || !type->pagesize) { | |
35fc5195 | 3680 | /* Check if the chip is ONFI compliant */ |
47450b35 | 3681 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3682 | goto ident_done; |
91361818 HS |
3683 | |
3684 | /* Check if the chip is JEDEC compliant */ | |
3685 | if (nand_flash_detect_jedec(mtd, chip, &busw)) | |
3686 | goto ident_done; | |
d1e1f4e4 FF |
3687 | } |
3688 | ||
5e81e88a | 3689 | if (!type->name) |
7aa65bfd TG |
3690 | return ERR_PTR(-ENODEV); |
3691 | ||
ba0251fe TG |
3692 | if (!mtd->name) |
3693 | mtd->name = type->name; | |
3694 | ||
69423d99 | 3695 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3696 | |
12a40a57 | 3697 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 3698 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
3699 | busw = chip->init_size(mtd, chip, id_data); |
3700 | } else if (!type->pagesize) { | |
fc09bbc0 BN |
3701 | /* Decode parameters from extended ID */ |
3702 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3703 | } else { |
f23a481c | 3704 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3705 | } |
bf7a01bf BN |
3706 | /* Get chip options */ |
3707 | chip->options |= type->options; | |
d1e1f4e4 | 3708 | |
8b6e50c9 BN |
3709 | /* |
3710 | * Check if chip is not a Samsung device. Do not clear the | |
3711 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3712 | */ |
3713 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3714 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3715 | ident_done: | |
3716 | ||
7aa65bfd | 3717 | /* Try to identify manufacturer */ |
9a909867 | 3718 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3719 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3720 | break; | |
3721 | } | |
0ea4a755 | 3722 | |
64b37b2a MC |
3723 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
3724 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
3725 | chip->options |= busw; | |
3726 | nand_set_defaults(chip, busw); | |
3727 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { | |
3728 | /* | |
3729 | * Check, if buswidth is correct. Hardware drivers should set | |
3730 | * chip correct! | |
3731 | */ | |
20171642 EG |
3732 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3733 | *maf_id, *dev_id); | |
3734 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); | |
3735 | pr_warn("bus width %d instead %d bit\n", | |
d0370219 BN |
3736 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3737 | busw ? 16 : 8); | |
7aa65bfd TG |
3738 | return ERR_PTR(-EINVAL); |
3739 | } | |
61b03bd7 | 3740 | |
7e74c2d7 BN |
3741 | nand_decode_bbm_options(mtd, chip, id_data); |
3742 | ||
7aa65bfd | 3743 | /* Calculate the address shift from the page size */ |
ace4dfee | 3744 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3745 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3746 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3747 | |
ace4dfee | 3748 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3749 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3750 | if (chip->chipsize & 0xffffffff) |
3751 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3752 | else { |
3753 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3754 | chip->chip_shift += 32 - 1; | |
3755 | } | |
1da177e4 | 3756 | |
26d9be11 | 3757 | chip->badblockbits = 8; |
49c50b97 | 3758 | chip->erase = single_erase; |
7aa65bfd | 3759 | |
8b6e50c9 | 3760 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3761 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3762 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3763 | |
20171642 EG |
3764 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3765 | *maf_id, *dev_id); | |
ffdac6cd HS |
3766 | |
3767 | if (chip->onfi_version) | |
3768 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3769 | chip->onfi_params.model); | |
3770 | else if (chip->jedec_version) | |
3771 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3772 | chip->jedec_params.model); | |
3773 | else | |
3774 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3775 | type->name); | |
3776 | ||
3755a991 | 3777 | pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", |
3723e93c | 3778 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3755a991 | 3779 | mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); |
7aa65bfd TG |
3780 | return type; |
3781 | } | |
3782 | ||
7aa65bfd | 3783 | /** |
3b85c321 | 3784 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3785 | * @mtd: MTD device structure |
3786 | * @maxchips: number of chips to scan for | |
3787 | * @table: alternative NAND ID table | |
7aa65bfd | 3788 | * |
8b6e50c9 BN |
3789 | * This is the first phase of the normal nand_scan() function. It reads the |
3790 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3791 | * |
3b85c321 | 3792 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3793 | */ |
5e81e88a DW |
3794 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3795 | struct nand_flash_dev *table) | |
7aa65bfd | 3796 | { |
bb77082f | 3797 | int i, nand_maf_id, nand_dev_id; |
ace4dfee | 3798 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3799 | struct nand_flash_dev *type; |
3800 | ||
7aa65bfd | 3801 | /* Set the default functions */ |
bb77082f | 3802 | nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); |
7aa65bfd TG |
3803 | |
3804 | /* Read the flash type */ | |
bb77082f CZ |
3805 | type = nand_get_flash_type(mtd, chip, &nand_maf_id, |
3806 | &nand_dev_id, table); | |
7aa65bfd TG |
3807 | |
3808 | if (IS_ERR(type)) { | |
b1c6e6db | 3809 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3810 | pr_warn("No NAND device found\n"); |
ace4dfee | 3811 | chip->select_chip(mtd, -1); |
7aa65bfd | 3812 | return PTR_ERR(type); |
1da177e4 LT |
3813 | } |
3814 | ||
07300164 HS |
3815 | chip->select_chip(mtd, -1); |
3816 | ||
7aa65bfd | 3817 | /* Check for a chip array */ |
e0c7d767 | 3818 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3819 | chip->select_chip(mtd, i); |
ef89a880 KB |
3820 | /* See comment in nand_get_flash_type for reset */ |
3821 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3822 | /* Send the command for reading device ID */ |
ace4dfee | 3823 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3824 | /* Read manufacturer and device IDs */ |
ace4dfee | 3825 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
3826 | nand_dev_id != chip->read_byte(mtd)) { |
3827 | chip->select_chip(mtd, -1); | |
1da177e4 | 3828 | break; |
07300164 HS |
3829 | } |
3830 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
3831 | } |
3832 | if (i > 1) | |
20171642 | 3833 | pr_info("%d chips detected\n", i); |
61b03bd7 | 3834 | |
1da177e4 | 3835 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3836 | chip->numchips = i; |
3837 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3838 | |
3b85c321 DW |
3839 | return 0; |
3840 | } | |
7351d3a5 | 3841 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 | 3842 | |
67a9ad9b EG |
3843 | /* |
3844 | * Check if the chip configuration meet the datasheet requirements. | |
3845 | ||
3846 | * If our configuration corrects A bits per B bytes and the minimum | |
3847 | * required correction level is X bits per Y bytes, then we must ensure | |
3848 | * both of the following are true: | |
3849 | * | |
3850 | * (1) A / B >= X / Y | |
3851 | * (2) A >= X | |
3852 | * | |
3853 | * Requirement (1) ensures we can correct for the required bitflip density. | |
3854 | * Requirement (2) ensures we can correct even when all bitflips are clumped | |
3855 | * in the same sector. | |
3856 | */ | |
3857 | static bool nand_ecc_strength_good(struct mtd_info *mtd) | |
3858 | { | |
3859 | struct nand_chip *chip = mtd->priv; | |
3860 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
3861 | int corr, ds_corr; | |
3862 | ||
3863 | if (ecc->size == 0 || chip->ecc_step_ds == 0) | |
3864 | /* Not enough information */ | |
3865 | return true; | |
3866 | ||
3867 | /* | |
3868 | * We get the number of corrected bits per page to compare | |
3869 | * the correction density. | |
3870 | */ | |
3871 | corr = (mtd->writesize * ecc->strength) / ecc->size; | |
3872 | ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; | |
3873 | ||
3874 | return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; | |
3875 | } | |
3b85c321 DW |
3876 | |
3877 | /** | |
3878 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 3879 | * @mtd: MTD device structure |
3b85c321 | 3880 | * |
8b6e50c9 BN |
3881 | * This is the second phase of the normal nand_scan() function. It fills out |
3882 | * all the uninitialized function pointers with the defaults and scans for a | |
3883 | * bad block table if appropriate. | |
3b85c321 DW |
3884 | */ |
3885 | int nand_scan_tail(struct mtd_info *mtd) | |
3886 | { | |
3887 | int i; | |
3888 | struct nand_chip *chip = mtd->priv; | |
97de79e0 | 3889 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
f02ea4e6 | 3890 | struct nand_buffers *nbuf; |
3b85c321 | 3891 | |
e2414f4c BN |
3892 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
3893 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
3894 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
3895 | ||
f02ea4e6 HS |
3896 | if (!(chip->options & NAND_OWN_BUFFERS)) { |
3897 | nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize | |
3898 | + mtd->oobsize * 3, GFP_KERNEL); | |
3899 | if (!nbuf) | |
3900 | return -ENOMEM; | |
3901 | nbuf->ecccalc = (uint8_t *)(nbuf + 1); | |
3902 | nbuf->ecccode = nbuf->ecccalc + mtd->oobsize; | |
3903 | nbuf->databuf = nbuf->ecccode + mtd->oobsize; | |
3904 | ||
3905 | chip->buffers = nbuf; | |
3906 | } else { | |
3907 | if (!chip->buffers) | |
3908 | return -ENOMEM; | |
3909 | } | |
4bf63fcb | 3910 | |
7dcdcbef | 3911 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3912 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3913 | |
7aa65bfd | 3914 | /* |
8b6e50c9 | 3915 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 3916 | */ |
97de79e0 | 3917 | if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3918 | switch (mtd->oobsize) { |
1da177e4 | 3919 | case 8: |
97de79e0 | 3920 | ecc->layout = &nand_oob_8; |
1da177e4 LT |
3921 | break; |
3922 | case 16: | |
97de79e0 | 3923 | ecc->layout = &nand_oob_16; |
1da177e4 LT |
3924 | break; |
3925 | case 64: | |
97de79e0 | 3926 | ecc->layout = &nand_oob_64; |
1da177e4 | 3927 | break; |
81ec5364 | 3928 | case 128: |
97de79e0 | 3929 | ecc->layout = &nand_oob_128; |
81ec5364 | 3930 | break; |
1da177e4 | 3931 | default: |
d0370219 BN |
3932 | pr_warn("No oob scheme defined for oobsize %d\n", |
3933 | mtd->oobsize); | |
1da177e4 LT |
3934 | BUG(); |
3935 | } | |
3936 | } | |
61b03bd7 | 3937 | |
956e944c DW |
3938 | if (!chip->write_page) |
3939 | chip->write_page = nand_write_page; | |
3940 | ||
61b03bd7 | 3941 | /* |
8b6e50c9 | 3942 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 3943 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 3944 | */ |
956e944c | 3945 | |
97de79e0 | 3946 | switch (ecc->mode) { |
6e0cb135 SN |
3947 | case NAND_ECC_HW_OOB_FIRST: |
3948 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 3949 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
2ac63d90 | 3950 | pr_warn("No ECC functions supplied; hardware ECC not possible\n"); |
6e0cb135 SN |
3951 | BUG(); |
3952 | } | |
97de79e0 HS |
3953 | if (!ecc->read_page) |
3954 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 3955 | |
6dfc6d25 | 3956 | case NAND_ECC_HW: |
8b6e50c9 | 3957 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
3958 | if (!ecc->read_page) |
3959 | ecc->read_page = nand_read_page_hwecc; | |
3960 | if (!ecc->write_page) | |
3961 | ecc->write_page = nand_write_page_hwecc; | |
3962 | if (!ecc->read_page_raw) | |
3963 | ecc->read_page_raw = nand_read_page_raw; | |
3964 | if (!ecc->write_page_raw) | |
3965 | ecc->write_page_raw = nand_write_page_raw; | |
3966 | if (!ecc->read_oob) | |
3967 | ecc->read_oob = nand_read_oob_std; | |
3968 | if (!ecc->write_oob) | |
3969 | ecc->write_oob = nand_write_oob_std; | |
3970 | if (!ecc->read_subpage) | |
3971 | ecc->read_subpage = nand_read_subpage; | |
3972 | if (!ecc->write_subpage) | |
3973 | ecc->write_subpage = nand_write_subpage_hwecc; | |
f5bbdacc | 3974 | |
6dfc6d25 | 3975 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
3976 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
3977 | (!ecc->read_page || | |
3978 | ecc->read_page == nand_read_page_hwecc || | |
3979 | !ecc->write_page || | |
3980 | ecc->write_page == nand_write_page_hwecc)) { | |
2ac63d90 | 3981 | pr_warn("No ECC functions supplied; hardware ECC not possible\n"); |
6dfc6d25 TG |
3982 | BUG(); |
3983 | } | |
8b6e50c9 | 3984 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
3985 | if (!ecc->read_page) |
3986 | ecc->read_page = nand_read_page_syndrome; | |
3987 | if (!ecc->write_page) | |
3988 | ecc->write_page = nand_write_page_syndrome; | |
3989 | if (!ecc->read_page_raw) | |
3990 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
3991 | if (!ecc->write_page_raw) | |
3992 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
3993 | if (!ecc->read_oob) | |
3994 | ecc->read_oob = nand_read_oob_syndrome; | |
3995 | if (!ecc->write_oob) | |
3996 | ecc->write_oob = nand_write_oob_syndrome; | |
3997 | ||
3998 | if (mtd->writesize >= ecc->size) { | |
3999 | if (!ecc->strength) { | |
e2788c98 MD |
4000 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); |
4001 | BUG(); | |
4002 | } | |
6dfc6d25 | 4003 | break; |
e2788c98 | 4004 | } |
2ac63d90 RM |
4005 | pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", |
4006 | ecc->size, mtd->writesize); | |
97de79e0 | 4007 | ecc->mode = NAND_ECC_SOFT; |
61b03bd7 | 4008 | |
6dfc6d25 | 4009 | case NAND_ECC_SOFT: |
97de79e0 HS |
4010 | ecc->calculate = nand_calculate_ecc; |
4011 | ecc->correct = nand_correct_data; | |
4012 | ecc->read_page = nand_read_page_swecc; | |
4013 | ecc->read_subpage = nand_read_subpage; | |
4014 | ecc->write_page = nand_write_page_swecc; | |
4015 | ecc->read_page_raw = nand_read_page_raw; | |
4016 | ecc->write_page_raw = nand_write_page_raw; | |
4017 | ecc->read_oob = nand_read_oob_std; | |
4018 | ecc->write_oob = nand_write_oob_std; | |
4019 | if (!ecc->size) | |
4020 | ecc->size = 256; | |
4021 | ecc->bytes = 3; | |
4022 | ecc->strength = 1; | |
1da177e4 | 4023 | break; |
61b03bd7 | 4024 | |
193bd400 ID |
4025 | case NAND_ECC_SOFT_BCH: |
4026 | if (!mtd_nand_has_bch()) { | |
148256fa | 4027 | pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); |
193bd400 ID |
4028 | BUG(); |
4029 | } | |
97de79e0 HS |
4030 | ecc->calculate = nand_bch_calculate_ecc; |
4031 | ecc->correct = nand_bch_correct_data; | |
4032 | ecc->read_page = nand_read_page_swecc; | |
4033 | ecc->read_subpage = nand_read_subpage; | |
4034 | ecc->write_page = nand_write_page_swecc; | |
4035 | ecc->read_page_raw = nand_read_page_raw; | |
4036 | ecc->write_page_raw = nand_write_page_raw; | |
4037 | ecc->read_oob = nand_read_oob_std; | |
4038 | ecc->write_oob = nand_write_oob_std; | |
193bd400 | 4039 | /* |
e0377cde AS |
4040 | * Board driver should supply ecc.size and ecc.strength values |
4041 | * to select how many bits are correctable. Otherwise, default | |
4042 | * to 4 bits for large page devices. | |
193bd400 | 4043 | */ |
97de79e0 HS |
4044 | if (!ecc->size && (mtd->oobsize >= 64)) { |
4045 | ecc->size = 512; | |
e0377cde | 4046 | ecc->strength = 4; |
193bd400 | 4047 | } |
e0377cde AS |
4048 | |
4049 | /* See nand_bch_init() for details. */ | |
4050 | ecc->bytes = DIV_ROUND_UP( | |
4051 | ecc->strength * fls(8 * ecc->size), 8); | |
97de79e0 HS |
4052 | ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, |
4053 | &ecc->layout); | |
4054 | if (!ecc->priv) { | |
9a4d4d69 | 4055 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
4056 | BUG(); |
4057 | } | |
4058 | break; | |
4059 | ||
61b03bd7 | 4060 | case NAND_ECC_NONE: |
2ac63d90 | 4061 | pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); |
97de79e0 HS |
4062 | ecc->read_page = nand_read_page_raw; |
4063 | ecc->write_page = nand_write_page_raw; | |
4064 | ecc->read_oob = nand_read_oob_std; | |
4065 | ecc->read_page_raw = nand_read_page_raw; | |
4066 | ecc->write_page_raw = nand_write_page_raw; | |
4067 | ecc->write_oob = nand_write_oob_std; | |
4068 | ecc->size = mtd->writesize; | |
4069 | ecc->bytes = 0; | |
4070 | ecc->strength = 0; | |
1da177e4 | 4071 | break; |
956e944c | 4072 | |
1da177e4 | 4073 | default: |
97de79e0 | 4074 | pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); |
61b03bd7 | 4075 | BUG(); |
1da177e4 | 4076 | } |
61b03bd7 | 4077 | |
9ce244b3 | 4078 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
4079 | if (!ecc->read_oob_raw) |
4080 | ecc->read_oob_raw = ecc->read_oob; | |
4081 | if (!ecc->write_oob_raw) | |
4082 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 4083 | |
5bd34c09 TG |
4084 | /* |
4085 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 4086 | * the out of band area. |
5bd34c09 | 4087 | */ |
97de79e0 HS |
4088 | ecc->layout->oobavail = 0; |
4089 | for (i = 0; ecc->layout->oobfree[i].length | |
4090 | && i < ARRAY_SIZE(ecc->layout->oobfree); i++) | |
4091 | ecc->layout->oobavail += ecc->layout->oobfree[i].length; | |
4092 | mtd->oobavail = ecc->layout->oobavail; | |
5bd34c09 | 4093 | |
54c39e9b TP |
4094 | /* ECC sanity check: warn if it's too weak */ |
4095 | if (!nand_ecc_strength_good(mtd)) | |
4096 | pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", | |
4097 | mtd->name); | |
67a9ad9b | 4098 | |
7aa65bfd TG |
4099 | /* |
4100 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 4101 | * mode. |
7aa65bfd | 4102 | */ |
97de79e0 HS |
4103 | ecc->steps = mtd->writesize / ecc->size; |
4104 | if (ecc->steps * ecc->size != mtd->writesize) { | |
9a4d4d69 | 4105 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 4106 | BUG(); |
1da177e4 | 4107 | } |
97de79e0 | 4108 | ecc->total = ecc->steps * ecc->bytes; |
61b03bd7 | 4109 | |
8b6e50c9 | 4110 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 4111 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 4112 | switch (ecc->steps) { |
29072b96 TG |
4113 | case 2: |
4114 | mtd->subpage_sft = 1; | |
4115 | break; | |
4116 | case 4: | |
4117 | case 8: | |
81ec5364 | 4118 | case 16: |
29072b96 TG |
4119 | mtd->subpage_sft = 2; |
4120 | break; | |
4121 | } | |
4122 | } | |
4123 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
4124 | ||
04bbd0ea | 4125 | /* Initialize state */ |
ace4dfee | 4126 | chip->state = FL_READY; |
1da177e4 | 4127 | |
1da177e4 | 4128 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 4129 | chip->pagebuf = -1; |
1da177e4 | 4130 | |
a5ff4f10 | 4131 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
4007e2d1 RL |
4132 | switch (ecc->mode) { |
4133 | case NAND_ECC_SOFT: | |
4134 | case NAND_ECC_SOFT_BCH: | |
4135 | if (chip->page_shift > 9) | |
4136 | chip->options |= NAND_SUBPAGE_READ; | |
4137 | break; | |
4138 | ||
4139 | default: | |
4140 | break; | |
4141 | } | |
a5ff4f10 | 4142 | |
1da177e4 | 4143 | /* Fill in remaining MTD driver data */ |
963d1c28 | 4144 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
4145 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
4146 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
4147 | mtd->_erase = nand_erase; |
4148 | mtd->_point = NULL; | |
4149 | mtd->_unpoint = NULL; | |
4150 | mtd->_read = nand_read; | |
4151 | mtd->_write = nand_write; | |
4152 | mtd->_panic_write = panic_nand_write; | |
4153 | mtd->_read_oob = nand_read_oob; | |
4154 | mtd->_write_oob = nand_write_oob; | |
4155 | mtd->_sync = nand_sync; | |
4156 | mtd->_lock = NULL; | |
4157 | mtd->_unlock = NULL; | |
4158 | mtd->_suspend = nand_suspend; | |
4159 | mtd->_resume = nand_resume; | |
72ea4036 | 4160 | mtd->_reboot = nand_shutdown; |
8471bb73 | 4161 | mtd->_block_isreserved = nand_block_isreserved; |
3c3c10bb AB |
4162 | mtd->_block_isbad = nand_block_isbad; |
4163 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 4164 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 4165 | |
6a918bad | 4166 | /* propagate ecc info to mtd_info */ |
97de79e0 HS |
4167 | mtd->ecclayout = ecc->layout; |
4168 | mtd->ecc_strength = ecc->strength; | |
4169 | mtd->ecc_step_size = ecc->size; | |
ea3b2ea2 SL |
4170 | /* |
4171 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
4172 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
4173 | * properly set. | |
4174 | */ | |
4175 | if (!mtd->bitflip_threshold) | |
240181fd | 4176 | mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); |
1da177e4 | 4177 | |
0040bf38 | 4178 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 4179 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 4180 | return 0; |
1da177e4 LT |
4181 | |
4182 | /* Build bad block table */ | |
ace4dfee | 4183 | return chip->scan_bbt(mtd); |
1da177e4 | 4184 | } |
7351d3a5 | 4185 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 4186 | |
8b6e50c9 BN |
4187 | /* |
4188 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 4189 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
4190 | * to call us from in-kernel code if the core NAND support is modular. |
4191 | */ | |
3b85c321 DW |
4192 | #ifdef MODULE |
4193 | #define caller_is_module() (1) | |
4194 | #else | |
4195 | #define caller_is_module() \ | |
a6e6abd5 | 4196 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
4197 | #endif |
4198 | ||
4199 | /** | |
4200 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
4201 | * @mtd: MTD device structure |
4202 | * @maxchips: number of chips to scan for | |
3b85c321 | 4203 | * |
8b6e50c9 BN |
4204 | * This fills out all the uninitialized function pointers with the defaults. |
4205 | * The flash ID is read and the mtd/chip structures are filled with the | |
4206 | * appropriate values. The mtd->owner field must be set to the module of the | |
4207 | * caller. | |
3b85c321 DW |
4208 | */ |
4209 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
4210 | { | |
4211 | int ret; | |
4212 | ||
4213 | /* Many callers got this wrong, so check for it for a while... */ | |
4214 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 4215 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
4216 | BUG(); |
4217 | } | |
4218 | ||
5e81e88a | 4219 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
4220 | if (!ret) |
4221 | ret = nand_scan_tail(mtd); | |
4222 | return ret; | |
4223 | } | |
7351d3a5 | 4224 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 4225 | |
1da177e4 | 4226 | /** |
61b03bd7 | 4227 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
4228 | * @mtd: MTD device structure |
4229 | */ | |
e0c7d767 | 4230 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 4231 | { |
ace4dfee | 4232 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 4233 | |
193bd400 ID |
4234 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
4235 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
4236 | ||
5ffcaf3d | 4237 | mtd_device_unregister(mtd); |
1da177e4 | 4238 | |
fa671646 | 4239 | /* Free bad block table memory */ |
ace4dfee | 4240 | kfree(chip->bbt); |
4bf63fcb DW |
4241 | if (!(chip->options & NAND_OWN_BUFFERS)) |
4242 | kfree(chip->buffers); | |
58373ff0 BN |
4243 | |
4244 | /* Free bad block descriptor memory */ | |
4245 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
4246 | & NAND_BBT_DYNAMICSTRUCT) | |
4247 | kfree(chip->badblock_pattern); | |
1da177e4 | 4248 | } |
e0c7d767 | 4249 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
4250 | |
4251 | static int __init nand_base_init(void) | |
4252 | { | |
4253 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
4254 | return 0; | |
4255 | } | |
4256 | ||
4257 | static void __exit nand_base_exit(void) | |
4258 | { | |
4259 | led_trigger_unregister_simple(nand_led_trigger); | |
4260 | } | |
4261 | ||
4262 | module_init(nand_base_init); | |
4263 | module_exit(nand_base_exit); | |
4264 | ||
e0c7d767 | 4265 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
4266 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
4267 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 4268 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |