Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 LT |
9 | * Additional technical information is available on |
10 | * http://www.linux-mtd.infradead.org/tech/nand.html | |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
24 | * if we have HW ecc support. | |
25 | * The AG-AND chips have nice features for speed improvement, | |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
27 | * | |
1da177e4 LT |
28 | * This program is free software; you can redistribute it and/or modify |
29 | * it under the terms of the GNU General Public License version 2 as | |
30 | * published by the Free Software Foundation. | |
31 | * | |
32 | */ | |
33 | ||
552d9205 | 34 | #include <linux/module.h> |
1da177e4 LT |
35 | #include <linux/delay.h> |
36 | #include <linux/errno.h> | |
7aa65bfd | 37 | #include <linux/err.h> |
1da177e4 LT |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
40 | #include <linux/types.h> | |
41 | #include <linux/mtd/mtd.h> | |
42 | #include <linux/mtd/nand.h> | |
43 | #include <linux/mtd/nand_ecc.h> | |
44 | #include <linux/mtd/compatmac.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/bitops.h> | |
8fe833c1 | 47 | #include <linux/leds.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | ||
50 | #ifdef CONFIG_MTD_PARTITIONS | |
51 | #include <linux/mtd/partitions.h> | |
52 | #endif | |
53 | ||
54 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 55 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
56 | .eccbytes = 3, |
57 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
58 | .oobfree = { |
59 | {.offset = 3, | |
60 | .length = 2}, | |
61 | {.offset = 6, | |
62 | .length = 2}} | |
1da177e4 LT |
63 | }; |
64 | ||
5bd34c09 | 65 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
66 | .eccbytes = 6, |
67 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
68 | .oobfree = { |
69 | {.offset = 8, | |
70 | . length = 8}} | |
1da177e4 LT |
71 | }; |
72 | ||
5bd34c09 | 73 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
74 | .eccbytes = 24, |
75 | .eccpos = { | |
e0c7d767 DW |
76 | 40, 41, 42, 43, 44, 45, 46, 47, |
77 | 48, 49, 50, 51, 52, 53, 54, 55, | |
78 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
79 | .oobfree = { |
80 | {.offset = 2, | |
81 | .length = 38}} | |
1da177e4 LT |
82 | }; |
83 | ||
ace4dfee | 84 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 85 | int new_state); |
1da177e4 | 86 | |
8593fbc6 TG |
87 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
88 | struct mtd_oob_ops *ops); | |
89 | ||
d470a97c TG |
90 | /* |
91 | * For devices which display every fart in the system on a seperate LED. Is | |
92 | * compiled away when LED support is disabled. | |
93 | */ | |
94 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
95 | ||
1da177e4 LT |
96 | /** |
97 | * nand_release_device - [GENERIC] release chip | |
98 | * @mtd: MTD device structure | |
61b03bd7 TG |
99 | * |
100 | * Deselect, release chip lock and wake up anyone waiting on the device | |
1da177e4 | 101 | */ |
e0c7d767 | 102 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 103 | { |
ace4dfee | 104 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
105 | |
106 | /* De-select the NAND device */ | |
ace4dfee | 107 | chip->select_chip(mtd, -1); |
0dfc6246 | 108 | |
a36ed299 | 109 | /* Release the controller and the chip */ |
ace4dfee TG |
110 | spin_lock(&chip->controller->lock); |
111 | chip->controller->active = NULL; | |
112 | chip->state = FL_READY; | |
113 | wake_up(&chip->controller->wq); | |
114 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
115 | } |
116 | ||
117 | /** | |
118 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
119 | * @mtd: MTD device structure | |
120 | * | |
121 | * Default read function for 8bit buswith | |
122 | */ | |
58dd8f2b | 123 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 124 | { |
ace4dfee TG |
125 | struct nand_chip *chip = mtd->priv; |
126 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
127 | } |
128 | ||
1da177e4 LT |
129 | /** |
130 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip | |
131 | * @mtd: MTD device structure | |
132 | * | |
61b03bd7 | 133 | * Default read function for 16bit buswith with |
1da177e4 LT |
134 | * endianess conversion |
135 | */ | |
58dd8f2b | 136 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 137 | { |
ace4dfee TG |
138 | struct nand_chip *chip = mtd->priv; |
139 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
140 | } |
141 | ||
1da177e4 LT |
142 | /** |
143 | * nand_read_word - [DEFAULT] read one word from the chip | |
144 | * @mtd: MTD device structure | |
145 | * | |
61b03bd7 | 146 | * Default read function for 16bit buswith without |
1da177e4 LT |
147 | * endianess conversion |
148 | */ | |
149 | static u16 nand_read_word(struct mtd_info *mtd) | |
150 | { | |
ace4dfee TG |
151 | struct nand_chip *chip = mtd->priv; |
152 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
153 | } |
154 | ||
1da177e4 LT |
155 | /** |
156 | * nand_select_chip - [DEFAULT] control CE line | |
157 | * @mtd: MTD device structure | |
844d3b42 | 158 | * @chipnr: chipnumber to select, -1 for deselect |
1da177e4 LT |
159 | * |
160 | * Default select function for 1 chip devices. | |
161 | */ | |
ace4dfee | 162 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 163 | { |
ace4dfee TG |
164 | struct nand_chip *chip = mtd->priv; |
165 | ||
166 | switch (chipnr) { | |
1da177e4 | 167 | case -1: |
ace4dfee | 168 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
169 | break; |
170 | case 0: | |
1da177e4 LT |
171 | break; |
172 | ||
173 | default: | |
174 | BUG(); | |
175 | } | |
176 | } | |
177 | ||
178 | /** | |
179 | * nand_write_buf - [DEFAULT] write buffer to chip | |
180 | * @mtd: MTD device structure | |
181 | * @buf: data buffer | |
182 | * @len: number of bytes to write | |
183 | * | |
184 | * Default write function for 8bit buswith | |
185 | */ | |
58dd8f2b | 186 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
187 | { |
188 | int i; | |
ace4dfee | 189 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 190 | |
e0c7d767 | 191 | for (i = 0; i < len; i++) |
ace4dfee | 192 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
193 | } |
194 | ||
195 | /** | |
61b03bd7 | 196 | * nand_read_buf - [DEFAULT] read chip data into buffer |
1da177e4 LT |
197 | * @mtd: MTD device structure |
198 | * @buf: buffer to store date | |
199 | * @len: number of bytes to read | |
200 | * | |
201 | * Default read function for 8bit buswith | |
202 | */ | |
58dd8f2b | 203 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
204 | { |
205 | int i; | |
ace4dfee | 206 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 207 | |
e0c7d767 | 208 | for (i = 0; i < len; i++) |
ace4dfee | 209 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
210 | } |
211 | ||
212 | /** | |
61b03bd7 | 213 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
214 | * @mtd: MTD device structure |
215 | * @buf: buffer containing the data to compare | |
216 | * @len: number of bytes to compare | |
217 | * | |
218 | * Default verify function for 8bit buswith | |
219 | */ | |
58dd8f2b | 220 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
221 | { |
222 | int i; | |
ace4dfee | 223 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 224 | |
e0c7d767 | 225 | for (i = 0; i < len; i++) |
ace4dfee | 226 | if (buf[i] != readb(chip->IO_ADDR_R)) |
1da177e4 | 227 | return -EFAULT; |
1da177e4 LT |
228 | return 0; |
229 | } | |
230 | ||
231 | /** | |
232 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
233 | * @mtd: MTD device structure | |
234 | * @buf: data buffer | |
235 | * @len: number of bytes to write | |
236 | * | |
237 | * Default write function for 16bit buswith | |
238 | */ | |
58dd8f2b | 239 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
240 | { |
241 | int i; | |
ace4dfee | 242 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
243 | u16 *p = (u16 *) buf; |
244 | len >>= 1; | |
61b03bd7 | 245 | |
e0c7d767 | 246 | for (i = 0; i < len; i++) |
ace4dfee | 247 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 248 | |
1da177e4 LT |
249 | } |
250 | ||
251 | /** | |
61b03bd7 | 252 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
1da177e4 LT |
253 | * @mtd: MTD device structure |
254 | * @buf: buffer to store date | |
255 | * @len: number of bytes to read | |
256 | * | |
257 | * Default read function for 16bit buswith | |
258 | */ | |
58dd8f2b | 259 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
260 | { |
261 | int i; | |
ace4dfee | 262 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
263 | u16 *p = (u16 *) buf; |
264 | len >>= 1; | |
265 | ||
e0c7d767 | 266 | for (i = 0; i < len; i++) |
ace4dfee | 267 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
268 | } |
269 | ||
270 | /** | |
61b03bd7 | 271 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
272 | * @mtd: MTD device structure |
273 | * @buf: buffer containing the data to compare | |
274 | * @len: number of bytes to compare | |
275 | * | |
276 | * Default verify function for 16bit buswith | |
277 | */ | |
58dd8f2b | 278 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
279 | { |
280 | int i; | |
ace4dfee | 281 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
282 | u16 *p = (u16 *) buf; |
283 | len >>= 1; | |
284 | ||
e0c7d767 | 285 | for (i = 0; i < len; i++) |
ace4dfee | 286 | if (p[i] != readw(chip->IO_ADDR_R)) |
1da177e4 LT |
287 | return -EFAULT; |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | /** | |
293 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
294 | * @mtd: MTD device structure | |
295 | * @ofs: offset from device start | |
296 | * @getchip: 0, if the chip is already selected | |
297 | * | |
61b03bd7 | 298 | * Check, if the block is bad. |
1da177e4 LT |
299 | */ |
300 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
301 | { | |
302 | int page, chipnr, res = 0; | |
ace4dfee | 303 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
304 | u16 bad; |
305 | ||
306 | if (getchip) { | |
ace4dfee TG |
307 | page = (int)(ofs >> chip->page_shift); |
308 | chipnr = (int)(ofs >> chip->chip_shift); | |
1da177e4 | 309 | |
ace4dfee | 310 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
311 | |
312 | /* Select the NAND device */ | |
ace4dfee | 313 | chip->select_chip(mtd, chipnr); |
61b03bd7 | 314 | } else |
e0c7d767 | 315 | page = (int)ofs; |
1da177e4 | 316 | |
ace4dfee TG |
317 | if (chip->options & NAND_BUSWIDTH_16) { |
318 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, | |
319 | page & chip->pagemask); | |
320 | bad = cpu_to_le16(chip->read_word(mtd)); | |
321 | if (chip->badblockpos & 0x1) | |
49196f33 | 322 | bad >>= 8; |
1da177e4 LT |
323 | if ((bad & 0xFF) != 0xff) |
324 | res = 1; | |
325 | } else { | |
ace4dfee TG |
326 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, |
327 | page & chip->pagemask); | |
328 | if (chip->read_byte(mtd) != 0xff) | |
1da177e4 LT |
329 | res = 1; |
330 | } | |
61b03bd7 | 331 | |
ace4dfee | 332 | if (getchip) |
1da177e4 | 333 | nand_release_device(mtd); |
61b03bd7 | 334 | |
1da177e4 LT |
335 | return res; |
336 | } | |
337 | ||
338 | /** | |
339 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
340 | * @mtd: MTD device structure | |
341 | * @ofs: offset from device start | |
342 | * | |
343 | * This is the default implementation, which can be overridden by | |
344 | * a hardware specific driver. | |
345 | */ | |
346 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
347 | { | |
ace4dfee | 348 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 349 | uint8_t buf[2] = { 0, 0 }; |
f1a28c02 | 350 | int block, ret; |
61b03bd7 | 351 | |
1da177e4 | 352 | /* Get block number */ |
ace4dfee TG |
353 | block = ((int)ofs) >> chip->bbt_erase_shift; |
354 | if (chip->bbt) | |
355 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 LT |
356 | |
357 | /* Do we have a flash based bad block table ? */ | |
ace4dfee | 358 | if (chip->options & NAND_USE_FLASH_BBT) |
f1a28c02 TG |
359 | ret = nand_update_bbt(mtd, ofs); |
360 | else { | |
361 | /* We write two bytes, so we dont have to mess with 16 bit | |
362 | * access | |
363 | */ | |
364 | ofs += mtd->oobsize; | |
365 | chip->ops.len = 2; | |
366 | chip->ops.datbuf = NULL; | |
367 | chip->ops.oobbuf = buf; | |
368 | chip->ops.ooboffs = chip->badblockpos & ~0x01; | |
369 | ||
370 | ret = nand_do_write_oob(mtd, ofs, &chip->ops); | |
371 | } | |
372 | if (!ret) | |
373 | mtd->ecc_stats.badblocks++; | |
374 | return ret; | |
1da177e4 LT |
375 | } |
376 | ||
61b03bd7 | 377 | /** |
1da177e4 LT |
378 | * nand_check_wp - [GENERIC] check if the chip is write protected |
379 | * @mtd: MTD device structure | |
61b03bd7 | 380 | * Check, if the device is write protected |
1da177e4 | 381 | * |
61b03bd7 | 382 | * The function expects, that the device is already selected |
1da177e4 | 383 | */ |
e0c7d767 | 384 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 385 | { |
ace4dfee | 386 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 387 | /* Check the WP bit */ |
ace4dfee TG |
388 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
389 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
390 | } |
391 | ||
392 | /** | |
393 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
394 | * @mtd: MTD device structure | |
395 | * @ofs: offset from device start | |
396 | * @getchip: 0, if the chip is already selected | |
397 | * @allowbbt: 1, if its allowed to access the bbt area | |
398 | * | |
399 | * Check, if the block is bad. Either by reading the bad block table or | |
400 | * calling of the scan function. | |
401 | */ | |
2c0a2bed TG |
402 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
403 | int allowbbt) | |
1da177e4 | 404 | { |
ace4dfee | 405 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 406 | |
ace4dfee TG |
407 | if (!chip->bbt) |
408 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 409 | |
1da177e4 | 410 | /* Return info from the table */ |
e0c7d767 | 411 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
412 | } |
413 | ||
61b03bd7 | 414 | /* |
3b88775c TG |
415 | * Wait for the ready pin, after a command |
416 | * The timeout is catched later. | |
417 | */ | |
4b648b02 | 418 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 419 | { |
ace4dfee | 420 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 421 | unsigned long timeo = jiffies + 2; |
3b88775c | 422 | |
8fe833c1 | 423 | led_trigger_event(nand_led_trigger, LED_FULL); |
3b88775c TG |
424 | /* wait until command is processed or timeout occures */ |
425 | do { | |
ace4dfee | 426 | if (chip->dev_ready(mtd)) |
8fe833c1 | 427 | break; |
8446f1d3 | 428 | touch_softlockup_watchdog(); |
61b03bd7 | 429 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 430 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 431 | } |
4b648b02 | 432 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 433 | |
1da177e4 LT |
434 | /** |
435 | * nand_command - [DEFAULT] Send command to NAND device | |
436 | * @mtd: MTD device structure | |
437 | * @command: the command to be sent | |
438 | * @column: the column address for this command, -1 if none | |
439 | * @page_addr: the page address for this command, -1 if none | |
440 | * | |
441 | * Send command to NAND device. This function is used for small page | |
442 | * devices (256/512 Bytes per page) | |
443 | */ | |
7abd3ef9 TG |
444 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
445 | int column, int page_addr) | |
1da177e4 | 446 | { |
ace4dfee | 447 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 448 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 449 | |
1da177e4 LT |
450 | /* |
451 | * Write out the command to the device. | |
452 | */ | |
453 | if (command == NAND_CMD_SEQIN) { | |
454 | int readcmd; | |
455 | ||
28318776 | 456 | if (column >= mtd->writesize) { |
1da177e4 | 457 | /* OOB area */ |
28318776 | 458 | column -= mtd->writesize; |
1da177e4 LT |
459 | readcmd = NAND_CMD_READOOB; |
460 | } else if (column < 256) { | |
461 | /* First 256 bytes --> READ0 */ | |
462 | readcmd = NAND_CMD_READ0; | |
463 | } else { | |
464 | column -= 256; | |
465 | readcmd = NAND_CMD_READ1; | |
466 | } | |
ace4dfee | 467 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 468 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 469 | } |
ace4dfee | 470 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 471 | |
7abd3ef9 TG |
472 | /* |
473 | * Address cycle, when necessary | |
474 | */ | |
475 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; | |
476 | /* Serially input address */ | |
477 | if (column != -1) { | |
478 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 479 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 480 | column >>= 1; |
ace4dfee | 481 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
482 | ctrl &= ~NAND_CTRL_CHANGE; |
483 | } | |
484 | if (page_addr != -1) { | |
ace4dfee | 485 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 486 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 487 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 488 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
489 | if (chip->chipsize > (32 << 20)) |
490 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 491 | } |
ace4dfee | 492 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
493 | |
494 | /* | |
495 | * program and erase have their own busy handlers | |
1da177e4 | 496 | * status and sequential in needs no delay |
e0c7d767 | 497 | */ |
1da177e4 | 498 | switch (command) { |
61b03bd7 | 499 | |
1da177e4 LT |
500 | case NAND_CMD_PAGEPROG: |
501 | case NAND_CMD_ERASE1: | |
502 | case NAND_CMD_ERASE2: | |
503 | case NAND_CMD_SEQIN: | |
504 | case NAND_CMD_STATUS: | |
505 | return; | |
506 | ||
507 | case NAND_CMD_RESET: | |
ace4dfee | 508 | if (chip->dev_ready) |
1da177e4 | 509 | break; |
ace4dfee TG |
510 | udelay(chip->chip_delay); |
511 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 512 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
513 | chip->cmd_ctrl(mtd, |
514 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 515 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
516 | return; |
517 | ||
e0c7d767 | 518 | /* This applies to read commands */ |
1da177e4 | 519 | default: |
61b03bd7 | 520 | /* |
1da177e4 LT |
521 | * If we don't have access to the busy pin, we apply the given |
522 | * command delay | |
e0c7d767 | 523 | */ |
ace4dfee TG |
524 | if (!chip->dev_ready) { |
525 | udelay(chip->chip_delay); | |
1da177e4 | 526 | return; |
61b03bd7 | 527 | } |
1da177e4 | 528 | } |
1da177e4 LT |
529 | /* Apply this short delay always to ensure that we do wait tWB in |
530 | * any case on any machine. */ | |
e0c7d767 | 531 | ndelay(100); |
3b88775c TG |
532 | |
533 | nand_wait_ready(mtd); | |
1da177e4 LT |
534 | } |
535 | ||
536 | /** | |
537 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
538 | * @mtd: MTD device structure | |
539 | * @command: the command to be sent | |
540 | * @column: the column address for this command, -1 if none | |
541 | * @page_addr: the page address for this command, -1 if none | |
542 | * | |
7abd3ef9 TG |
543 | * Send command to NAND device. This is the version for the new large page |
544 | * devices We dont have the separate regions as we have in the small page | |
545 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 546 | */ |
7abd3ef9 TG |
547 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
548 | int column, int page_addr) | |
1da177e4 | 549 | { |
ace4dfee | 550 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
551 | |
552 | /* Emulate NAND_CMD_READOOB */ | |
553 | if (command == NAND_CMD_READOOB) { | |
28318776 | 554 | column += mtd->writesize; |
1da177e4 LT |
555 | command = NAND_CMD_READ0; |
556 | } | |
61b03bd7 | 557 | |
7abd3ef9 | 558 | /* Command latch cycle */ |
ace4dfee | 559 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 560 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
561 | |
562 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 563 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
564 | |
565 | /* Serially input address */ | |
566 | if (column != -1) { | |
567 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 568 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 569 | column >>= 1; |
ace4dfee | 570 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 571 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 572 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 573 | } |
1da177e4 | 574 | if (page_addr != -1) { |
ace4dfee TG |
575 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
576 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 577 | NAND_NCE | NAND_ALE); |
1da177e4 | 578 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
579 | if (chip->chipsize > (128 << 20)) |
580 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 581 | NAND_NCE | NAND_ALE); |
1da177e4 | 582 | } |
1da177e4 | 583 | } |
ace4dfee | 584 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
585 | |
586 | /* | |
587 | * program and erase have their own busy handlers | |
30f464b7 DM |
588 | * status, sequential in, and deplete1 need no delay |
589 | */ | |
1da177e4 | 590 | switch (command) { |
61b03bd7 | 591 | |
1da177e4 LT |
592 | case NAND_CMD_CACHEDPROG: |
593 | case NAND_CMD_PAGEPROG: | |
594 | case NAND_CMD_ERASE1: | |
595 | case NAND_CMD_ERASE2: | |
596 | case NAND_CMD_SEQIN: | |
7bc3312b | 597 | case NAND_CMD_RNDIN: |
1da177e4 | 598 | case NAND_CMD_STATUS: |
30f464b7 | 599 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
600 | return; |
601 | ||
e0c7d767 DW |
602 | /* |
603 | * read error status commands require only a short delay | |
604 | */ | |
30f464b7 DM |
605 | case NAND_CMD_STATUS_ERROR: |
606 | case NAND_CMD_STATUS_ERROR0: | |
607 | case NAND_CMD_STATUS_ERROR1: | |
608 | case NAND_CMD_STATUS_ERROR2: | |
609 | case NAND_CMD_STATUS_ERROR3: | |
ace4dfee | 610 | udelay(chip->chip_delay); |
30f464b7 | 611 | return; |
1da177e4 LT |
612 | |
613 | case NAND_CMD_RESET: | |
ace4dfee | 614 | if (chip->dev_ready) |
1da177e4 | 615 | break; |
ace4dfee | 616 | udelay(chip->chip_delay); |
12efdde3 TG |
617 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
618 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
619 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
620 | NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 621 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
622 | return; |
623 | ||
7bc3312b TG |
624 | case NAND_CMD_RNDOUT: |
625 | /* No ready / busy check necessary */ | |
626 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
627 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
628 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
629 | NAND_NCE | NAND_CTRL_CHANGE); | |
630 | return; | |
631 | ||
1da177e4 | 632 | case NAND_CMD_READ0: |
12efdde3 TG |
633 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
634 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
635 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
636 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 637 | |
e0c7d767 | 638 | /* This applies to read commands */ |
1da177e4 | 639 | default: |
61b03bd7 | 640 | /* |
1da177e4 LT |
641 | * If we don't have access to the busy pin, we apply the given |
642 | * command delay | |
e0c7d767 | 643 | */ |
ace4dfee TG |
644 | if (!chip->dev_ready) { |
645 | udelay(chip->chip_delay); | |
1da177e4 | 646 | return; |
61b03bd7 | 647 | } |
1da177e4 | 648 | } |
3b88775c | 649 | |
1da177e4 LT |
650 | /* Apply this short delay always to ensure that we do wait tWB in |
651 | * any case on any machine. */ | |
e0c7d767 | 652 | ndelay(100); |
3b88775c TG |
653 | |
654 | nand_wait_ready(mtd); | |
1da177e4 LT |
655 | } |
656 | ||
657 | /** | |
658 | * nand_get_device - [GENERIC] Get chip for selected access | |
844d3b42 | 659 | * @chip: the nand chip descriptor |
1da177e4 | 660 | * @mtd: MTD device structure |
61b03bd7 | 661 | * @new_state: the state which is requested |
1da177e4 LT |
662 | * |
663 | * Get the device and lock it for exclusive access | |
664 | */ | |
2c0a2bed | 665 | static int |
ace4dfee | 666 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 667 | { |
ace4dfee TG |
668 | spinlock_t *lock = &chip->controller->lock; |
669 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 670 | DECLARE_WAITQUEUE(wait, current); |
e0c7d767 | 671 | retry: |
0dfc6246 TG |
672 | spin_lock(lock); |
673 | ||
1da177e4 | 674 | /* Hardware controller shared among independend devices */ |
a36ed299 | 675 | /* Hardware controller shared among independend devices */ |
ace4dfee TG |
676 | if (!chip->controller->active) |
677 | chip->controller->active = chip; | |
a36ed299 | 678 | |
ace4dfee TG |
679 | if (chip->controller->active == chip && chip->state == FL_READY) { |
680 | chip->state = new_state; | |
0dfc6246 | 681 | spin_unlock(lock); |
962034f4 VW |
682 | return 0; |
683 | } | |
684 | if (new_state == FL_PM_SUSPENDED) { | |
685 | spin_unlock(lock); | |
ace4dfee | 686 | return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; |
0dfc6246 TG |
687 | } |
688 | set_current_state(TASK_UNINTERRUPTIBLE); | |
689 | add_wait_queue(wq, &wait); | |
690 | spin_unlock(lock); | |
691 | schedule(); | |
692 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
693 | goto retry; |
694 | } | |
695 | ||
696 | /** | |
697 | * nand_wait - [DEFAULT] wait until the command is done | |
698 | * @mtd: MTD device structure | |
844d3b42 | 699 | * @chip: NAND chip structure |
1da177e4 LT |
700 | * |
701 | * Wait for command done. This applies to erase and program only | |
61b03bd7 | 702 | * Erase can take up to 400ms and program up to 20ms according to |
1da177e4 | 703 | * general NAND and SmartMedia specs |
844d3b42 | 704 | */ |
7bc3312b | 705 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
706 | { |
707 | ||
e0c7d767 | 708 | unsigned long timeo = jiffies; |
7bc3312b | 709 | int status, state = chip->state; |
61b03bd7 | 710 | |
1da177e4 | 711 | if (state == FL_ERASING) |
e0c7d767 | 712 | timeo += (HZ * 400) / 1000; |
1da177e4 | 713 | else |
e0c7d767 | 714 | timeo += (HZ * 20) / 1000; |
1da177e4 | 715 | |
8fe833c1 RP |
716 | led_trigger_event(nand_led_trigger, LED_FULL); |
717 | ||
1da177e4 LT |
718 | /* Apply this short delay always to ensure that we do wait tWB in |
719 | * any case on any machine. */ | |
e0c7d767 | 720 | ndelay(100); |
1da177e4 | 721 | |
ace4dfee TG |
722 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
723 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 724 | else |
ace4dfee | 725 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 726 | |
61b03bd7 | 727 | while (time_before(jiffies, timeo)) { |
ace4dfee TG |
728 | if (chip->dev_ready) { |
729 | if (chip->dev_ready(mtd)) | |
61b03bd7 | 730 | break; |
1da177e4 | 731 | } else { |
ace4dfee | 732 | if (chip->read_byte(mtd) & NAND_STATUS_READY) |
1da177e4 LT |
733 | break; |
734 | } | |
20a6c211 | 735 | cond_resched(); |
1da177e4 | 736 | } |
8fe833c1 RP |
737 | led_trigger_event(nand_led_trigger, LED_OFF); |
738 | ||
ace4dfee | 739 | status = (int)chip->read_byte(mtd); |
1da177e4 LT |
740 | return status; |
741 | } | |
742 | ||
8593fbc6 TG |
743 | /** |
744 | * nand_read_page_raw - [Intern] read raw page data without ecc | |
745 | * @mtd: mtd info structure | |
746 | * @chip: nand chip info structure | |
747 | * @buf: buffer to store read data | |
748 | */ | |
749 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
750 | uint8_t *buf) | |
751 | { | |
752 | chip->read_buf(mtd, buf, mtd->writesize); | |
753 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
754 | return 0; | |
755 | } | |
756 | ||
1da177e4 | 757 | /** |
d29ebdbe | 758 | * nand_read_page_swecc - [REPLACABLE] software ecc based page read function |
f5bbdacc TG |
759 | * @mtd: mtd info structure |
760 | * @chip: nand chip info structure | |
761 | * @buf: buffer to store read data | |
068e3c0a | 762 | */ |
f5bbdacc TG |
763 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
764 | uint8_t *buf) | |
1da177e4 | 765 | { |
f5bbdacc TG |
766 | int i, eccsize = chip->ecc.size; |
767 | int eccbytes = chip->ecc.bytes; | |
768 | int eccsteps = chip->ecc.steps; | |
769 | uint8_t *p = buf; | |
4bf63fcb DW |
770 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
771 | uint8_t *ecc_code = chip->buffers->ecccode; | |
5bd34c09 | 772 | int *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc | 773 | |
8593fbc6 | 774 | nand_read_page_raw(mtd, chip, buf); |
f5bbdacc TG |
775 | |
776 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
777 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
778 | ||
779 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 780 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
781 | |
782 | eccsteps = chip->ecc.steps; | |
783 | p = buf; | |
784 | ||
785 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
786 | int stat; | |
787 | ||
788 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
789 | if (stat == -1) | |
790 | mtd->ecc_stats.failed++; | |
791 | else | |
792 | mtd->ecc_stats.corrected += stat; | |
793 | } | |
794 | return 0; | |
22c60f5f | 795 | } |
1da177e4 | 796 | |
068e3c0a | 797 | /** |
d29ebdbe | 798 | * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function |
f5bbdacc TG |
799 | * @mtd: mtd info structure |
800 | * @chip: nand chip info structure | |
801 | * @buf: buffer to store read data | |
068e3c0a | 802 | * |
f5bbdacc | 803 | * Not for syndrome calculating ecc controllers which need a special oob layout |
068e3c0a | 804 | */ |
f5bbdacc TG |
805 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
806 | uint8_t *buf) | |
1da177e4 | 807 | { |
f5bbdacc TG |
808 | int i, eccsize = chip->ecc.size; |
809 | int eccbytes = chip->ecc.bytes; | |
810 | int eccsteps = chip->ecc.steps; | |
811 | uint8_t *p = buf; | |
4bf63fcb DW |
812 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
813 | uint8_t *ecc_code = chip->buffers->ecccode; | |
5bd34c09 | 814 | int *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc TG |
815 | |
816 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
817 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
818 | chip->read_buf(mtd, p, eccsize); | |
819 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 820 | } |
f75e5097 | 821 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 822 | |
f5bbdacc | 823 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 824 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 825 | |
f5bbdacc TG |
826 | eccsteps = chip->ecc.steps; |
827 | p = buf; | |
61b03bd7 | 828 | |
f5bbdacc TG |
829 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
830 | int stat; | |
1da177e4 | 831 | |
f5bbdacc TG |
832 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
833 | if (stat == -1) | |
834 | mtd->ecc_stats.failed++; | |
835 | else | |
836 | mtd->ecc_stats.corrected += stat; | |
837 | } | |
838 | return 0; | |
839 | } | |
1da177e4 | 840 | |
f5bbdacc | 841 | /** |
d29ebdbe | 842 | * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read |
f5bbdacc TG |
843 | * @mtd: mtd info structure |
844 | * @chip: nand chip info structure | |
845 | * @buf: buffer to store read data | |
846 | * | |
847 | * The hw generator calculates the error syndrome automatically. Therefor | |
f75e5097 | 848 | * we need a special oob layout and handling. |
f5bbdacc TG |
849 | */ |
850 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
851 | uint8_t *buf) | |
852 | { | |
853 | int i, eccsize = chip->ecc.size; | |
854 | int eccbytes = chip->ecc.bytes; | |
855 | int eccsteps = chip->ecc.steps; | |
856 | uint8_t *p = buf; | |
f75e5097 | 857 | uint8_t *oob = chip->oob_poi; |
1da177e4 | 858 | |
f5bbdacc TG |
859 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
860 | int stat; | |
61b03bd7 | 861 | |
f5bbdacc TG |
862 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
863 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 864 | |
f5bbdacc TG |
865 | if (chip->ecc.prepad) { |
866 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
867 | oob += chip->ecc.prepad; | |
868 | } | |
1da177e4 | 869 | |
f5bbdacc TG |
870 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
871 | chip->read_buf(mtd, oob, eccbytes); | |
872 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 873 | |
f5bbdacc TG |
874 | if (stat == -1) |
875 | mtd->ecc_stats.failed++; | |
61b03bd7 | 876 | else |
f5bbdacc | 877 | mtd->ecc_stats.corrected += stat; |
61b03bd7 | 878 | |
f5bbdacc | 879 | oob += eccbytes; |
1da177e4 | 880 | |
f5bbdacc TG |
881 | if (chip->ecc.postpad) { |
882 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
883 | oob += chip->ecc.postpad; | |
61b03bd7 | 884 | } |
f5bbdacc | 885 | } |
1da177e4 | 886 | |
f5bbdacc | 887 | /* Calculate remaining oob bytes */ |
7e4178f9 | 888 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
889 | if (i) |
890 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 891 | |
f5bbdacc TG |
892 | return 0; |
893 | } | |
1da177e4 | 894 | |
f5bbdacc | 895 | /** |
8593fbc6 TG |
896 | * nand_transfer_oob - [Internal] Transfer oob to client buffer |
897 | * @chip: nand chip structure | |
844d3b42 | 898 | * @oob: oob destination address |
8593fbc6 TG |
899 | * @ops: oob ops structure |
900 | */ | |
901 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
902 | struct mtd_oob_ops *ops) | |
903 | { | |
904 | size_t len = ops->ooblen; | |
905 | ||
906 | switch(ops->mode) { | |
907 | ||
908 | case MTD_OOB_PLACE: | |
909 | case MTD_OOB_RAW: | |
910 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); | |
911 | return oob + len; | |
912 | ||
913 | case MTD_OOB_AUTO: { | |
914 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
915 | uint32_t boffs = 0, roffs = ops->ooboffs; |
916 | size_t bytes = 0; | |
8593fbc6 TG |
917 | |
918 | for(; free->length && len; free++, len -= bytes) { | |
7bc3312b TG |
919 | /* Read request not from offset 0 ? */ |
920 | if (unlikely(roffs)) { | |
921 | if (roffs >= free->length) { | |
922 | roffs -= free->length; | |
923 | continue; | |
924 | } | |
925 | boffs = free->offset + roffs; | |
926 | bytes = min_t(size_t, len, | |
927 | (free->length - roffs)); | |
928 | roffs = 0; | |
929 | } else { | |
930 | bytes = min_t(size_t, len, free->length); | |
931 | boffs = free->offset; | |
932 | } | |
933 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
934 | oob += bytes; |
935 | } | |
936 | return oob; | |
937 | } | |
938 | default: | |
939 | BUG(); | |
940 | } | |
941 | return NULL; | |
942 | } | |
943 | ||
944 | /** | |
945 | * nand_do_read_ops - [Internal] Read data with ECC | |
f5bbdacc TG |
946 | * |
947 | * @mtd: MTD device structure | |
948 | * @from: offset to read from | |
844d3b42 | 949 | * @ops: oob ops structure |
f5bbdacc TG |
950 | * |
951 | * Internal function. Called with chip held. | |
952 | */ | |
8593fbc6 TG |
953 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
954 | struct mtd_oob_ops *ops) | |
f5bbdacc TG |
955 | { |
956 | int chipnr, page, realpage, col, bytes, aligned; | |
957 | struct nand_chip *chip = mtd->priv; | |
958 | struct mtd_ecc_stats stats; | |
959 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
960 | int sndcmd = 1; | |
961 | int ret = 0; | |
8593fbc6 TG |
962 | uint32_t readlen = ops->len; |
963 | uint8_t *bufpoi, *oob, *buf; | |
1da177e4 | 964 | |
f5bbdacc | 965 | stats = mtd->ecc_stats; |
1da177e4 | 966 | |
f5bbdacc TG |
967 | chipnr = (int)(from >> chip->chip_shift); |
968 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 969 | |
f5bbdacc TG |
970 | realpage = (int)(from >> chip->page_shift); |
971 | page = realpage & chip->pagemask; | |
1da177e4 | 972 | |
f5bbdacc | 973 | col = (int)(from & (mtd->writesize - 1)); |
4bf63fcb | 974 | chip->oob_poi = chip->buffers->oobrbuf; |
61b03bd7 | 975 | |
8593fbc6 TG |
976 | buf = ops->datbuf; |
977 | oob = ops->oobbuf; | |
978 | ||
f5bbdacc TG |
979 | while(1) { |
980 | bytes = min(mtd->writesize - col, readlen); | |
981 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 982 | |
f5bbdacc | 983 | /* Is the current page in the buffer ? */ |
8593fbc6 | 984 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 985 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 986 | |
f5bbdacc TG |
987 | if (likely(sndcmd)) { |
988 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
989 | sndcmd = 0; | |
1da177e4 | 990 | } |
1da177e4 | 991 | |
f5bbdacc | 992 | /* Now read the page into the buffer */ |
956e944c DW |
993 | if (unlikely(ops->mode == MTD_OOB_RAW)) |
994 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi); | |
995 | else | |
996 | ret = chip->ecc.read_page(mtd, chip, bufpoi); | |
f5bbdacc | 997 | if (ret < 0) |
1da177e4 | 998 | break; |
f5bbdacc TG |
999 | |
1000 | /* Transfer not aligned data */ | |
1001 | if (!aligned) { | |
1002 | chip->pagebuf = realpage; | |
4bf63fcb | 1003 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1004 | } |
1005 | ||
8593fbc6 TG |
1006 | buf += bytes; |
1007 | ||
1008 | if (unlikely(oob)) { | |
1009 | /* Raw mode does data:oob:data:oob */ | |
1010 | if (ops->mode != MTD_OOB_RAW) | |
1011 | oob = nand_transfer_oob(chip, oob, ops); | |
1012 | else | |
1013 | buf = nand_transfer_oob(chip, buf, ops); | |
1014 | } | |
1015 | ||
f5bbdacc TG |
1016 | if (!(chip->options & NAND_NO_READRDY)) { |
1017 | /* | |
1018 | * Apply delay or wait for ready/busy pin. Do | |
1019 | * this before the AUTOINCR check, so no | |
1020 | * problems arise if a chip which does auto | |
1021 | * increment is marked as NOAUTOINCR by the | |
1022 | * board driver. | |
1023 | */ | |
1024 | if (!chip->dev_ready) | |
1025 | udelay(chip->chip_delay); | |
1026 | else | |
1027 | nand_wait_ready(mtd); | |
1da177e4 | 1028 | } |
8593fbc6 | 1029 | } else { |
4bf63fcb | 1030 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 TG |
1031 | buf += bytes; |
1032 | } | |
1da177e4 | 1033 | |
f5bbdacc | 1034 | readlen -= bytes; |
61b03bd7 | 1035 | |
f5bbdacc | 1036 | if (!readlen) |
61b03bd7 | 1037 | break; |
1da177e4 LT |
1038 | |
1039 | /* For subsequent reads align to page boundary. */ | |
1040 | col = 0; | |
1041 | /* Increment page address */ | |
1042 | realpage++; | |
1043 | ||
ace4dfee | 1044 | page = realpage & chip->pagemask; |
1da177e4 LT |
1045 | /* Check, if we cross a chip boundary */ |
1046 | if (!page) { | |
1047 | chipnr++; | |
ace4dfee TG |
1048 | chip->select_chip(mtd, -1); |
1049 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1050 | } |
f5bbdacc | 1051 | |
61b03bd7 TG |
1052 | /* Check, if the chip supports auto page increment |
1053 | * or if we have hit a block boundary. | |
e0c7d767 | 1054 | */ |
f5bbdacc | 1055 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
61b03bd7 | 1056 | sndcmd = 1; |
1da177e4 LT |
1057 | } |
1058 | ||
8593fbc6 | 1059 | ops->retlen = ops->len - (size_t) readlen; |
1da177e4 | 1060 | |
f5bbdacc TG |
1061 | if (ret) |
1062 | return ret; | |
1063 | ||
9a1fcdfd TG |
1064 | if (mtd->ecc_stats.failed - stats.failed) |
1065 | return -EBADMSG; | |
1066 | ||
1067 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
f5bbdacc TG |
1068 | } |
1069 | ||
1070 | /** | |
1071 | * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc | |
1072 | * @mtd: MTD device structure | |
1073 | * @from: offset to read from | |
1074 | * @len: number of bytes to read | |
1075 | * @retlen: pointer to variable to store the number of read bytes | |
1076 | * @buf: the databuffer to put data | |
1077 | * | |
1078 | * Get hold of the chip and call nand_do_read | |
1079 | */ | |
1080 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1081 | size_t *retlen, uint8_t *buf) | |
1082 | { | |
8593fbc6 | 1083 | struct nand_chip *chip = mtd->priv; |
f5bbdacc TG |
1084 | int ret; |
1085 | ||
f5bbdacc TG |
1086 | /* Do not allow reads past end of device */ |
1087 | if ((from + len) > mtd->size) | |
1088 | return -EINVAL; | |
1089 | if (!len) | |
1090 | return 0; | |
1091 | ||
8593fbc6 | 1092 | nand_get_device(chip, mtd, FL_READING); |
f5bbdacc | 1093 | |
8593fbc6 TG |
1094 | chip->ops.len = len; |
1095 | chip->ops.datbuf = buf; | |
1096 | chip->ops.oobbuf = NULL; | |
1097 | ||
1098 | ret = nand_do_read_ops(mtd, from, &chip->ops); | |
f5bbdacc | 1099 | |
7fd5aecc RP |
1100 | *retlen = chip->ops.retlen; |
1101 | ||
f5bbdacc TG |
1102 | nand_release_device(mtd); |
1103 | ||
1104 | return ret; | |
1da177e4 LT |
1105 | } |
1106 | ||
7bc3312b TG |
1107 | /** |
1108 | * nand_read_oob_std - [REPLACABLE] the most common OOB data read function | |
1109 | * @mtd: mtd info structure | |
1110 | * @chip: nand chip info structure | |
1111 | * @page: page number to read | |
1112 | * @sndcmd: flag whether to issue read command or not | |
1113 | */ | |
1114 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1115 | int page, int sndcmd) | |
1116 | { | |
1117 | if (sndcmd) { | |
1118 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1119 | sndcmd = 0; | |
1120 | } | |
1121 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1122 | return sndcmd; | |
1123 | } | |
1124 | ||
1125 | /** | |
1126 | * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC | |
1127 | * with syndromes | |
1128 | * @mtd: mtd info structure | |
1129 | * @chip: nand chip info structure | |
1130 | * @page: page number to read | |
1131 | * @sndcmd: flag whether to issue read command or not | |
1132 | */ | |
1133 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1134 | int page, int sndcmd) | |
1135 | { | |
1136 | uint8_t *buf = chip->oob_poi; | |
1137 | int length = mtd->oobsize; | |
1138 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1139 | int eccsize = chip->ecc.size; | |
1140 | uint8_t *bufpoi = buf; | |
1141 | int i, toread, sndrnd = 0, pos; | |
1142 | ||
1143 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1144 | for (i = 0; i < chip->ecc.steps; i++) { | |
1145 | if (sndrnd) { | |
1146 | pos = eccsize + i * (eccsize + chunk); | |
1147 | if (mtd->writesize > 512) | |
1148 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1149 | else | |
1150 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1151 | } else | |
1152 | sndrnd = 1; | |
1153 | toread = min_t(int, length, chunk); | |
1154 | chip->read_buf(mtd, bufpoi, toread); | |
1155 | bufpoi += toread; | |
1156 | length -= toread; | |
1157 | } | |
1158 | if (length > 0) | |
1159 | chip->read_buf(mtd, bufpoi, length); | |
1160 | ||
1161 | return 1; | |
1162 | } | |
1163 | ||
1164 | /** | |
1165 | * nand_write_oob_std - [REPLACABLE] the most common OOB data write function | |
1166 | * @mtd: mtd info structure | |
1167 | * @chip: nand chip info structure | |
1168 | * @page: page number to write | |
1169 | */ | |
1170 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1171 | int page) | |
1172 | { | |
1173 | int status = 0; | |
1174 | const uint8_t *buf = chip->oob_poi; | |
1175 | int length = mtd->oobsize; | |
1176 | ||
1177 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1178 | chip->write_buf(mtd, buf, length); | |
1179 | /* Send command to program the OOB data */ | |
1180 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1181 | ||
1182 | status = chip->waitfunc(mtd, chip); | |
1183 | ||
0d420f9d | 1184 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1185 | } |
1186 | ||
1187 | /** | |
1188 | * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC | |
1189 | * with syndrome - only for large page flash ! | |
1190 | * @mtd: mtd info structure | |
1191 | * @chip: nand chip info structure | |
1192 | * @page: page number to write | |
1193 | */ | |
1194 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1195 | struct nand_chip *chip, int page) | |
1196 | { | |
1197 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1198 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1199 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1200 | const uint8_t *bufpoi = chip->oob_poi; | |
1201 | ||
1202 | /* | |
1203 | * data-ecc-data-ecc ... ecc-oob | |
1204 | * or | |
1205 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1206 | */ | |
1207 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1208 | pos = steps * (eccsize + chunk); | |
1209 | steps = 0; | |
1210 | } else | |
8b0036ee | 1211 | pos = eccsize; |
7bc3312b TG |
1212 | |
1213 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1214 | for (i = 0; i < steps; i++) { | |
1215 | if (sndcmd) { | |
1216 | if (mtd->writesize <= 512) { | |
1217 | uint32_t fill = 0xFFFFFFFF; | |
1218 | ||
1219 | len = eccsize; | |
1220 | while (len > 0) { | |
1221 | int num = min_t(int, len, 4); | |
1222 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1223 | num); | |
1224 | len -= num; | |
1225 | } | |
1226 | } else { | |
1227 | pos = eccsize + i * (eccsize + chunk); | |
1228 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1229 | } | |
1230 | } else | |
1231 | sndcmd = 1; | |
1232 | len = min_t(int, length, chunk); | |
1233 | chip->write_buf(mtd, bufpoi, len); | |
1234 | bufpoi += len; | |
1235 | length -= len; | |
1236 | } | |
1237 | if (length > 0) | |
1238 | chip->write_buf(mtd, bufpoi, length); | |
1239 | ||
1240 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1241 | status = chip->waitfunc(mtd, chip); | |
1242 | ||
1243 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1244 | } | |
1245 | ||
1da177e4 | 1246 | /** |
8593fbc6 | 1247 | * nand_do_read_oob - [Intern] NAND read out-of-band |
1da177e4 LT |
1248 | * @mtd: MTD device structure |
1249 | * @from: offset to read from | |
8593fbc6 | 1250 | * @ops: oob operations description structure |
1da177e4 LT |
1251 | * |
1252 | * NAND read out-of-band data from the spare area | |
1253 | */ | |
8593fbc6 TG |
1254 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1255 | struct mtd_oob_ops *ops) | |
1da177e4 | 1256 | { |
7bc3312b | 1257 | int page, realpage, chipnr, sndcmd = 1; |
ace4dfee | 1258 | struct nand_chip *chip = mtd->priv; |
7314e9e7 | 1259 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
7bc3312b TG |
1260 | int readlen = ops->len; |
1261 | uint8_t *buf = ops->oobbuf; | |
61b03bd7 | 1262 | |
7e9a0bb0 AM |
1263 | DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n", |
1264 | (unsigned long long)from, readlen); | |
1da177e4 | 1265 | |
7314e9e7 | 1266 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1267 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1268 | |
7314e9e7 TG |
1269 | /* Shift to get page */ |
1270 | realpage = (int)(from >> chip->page_shift); | |
1271 | page = realpage & chip->pagemask; | |
1da177e4 | 1272 | |
4bf63fcb | 1273 | chip->oob_poi = chip->buffers->oobrbuf; |
7314e9e7 TG |
1274 | |
1275 | while(1) { | |
7bc3312b TG |
1276 | sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); |
1277 | buf = nand_transfer_oob(chip, buf, ops); | |
8593fbc6 | 1278 | |
7314e9e7 TG |
1279 | if (!(chip->options & NAND_NO_READRDY)) { |
1280 | /* | |
1281 | * Apply delay or wait for ready/busy pin. Do this | |
1282 | * before the AUTOINCR check, so no problems arise if a | |
1283 | * chip which does auto increment is marked as | |
1284 | * NOAUTOINCR by the board driver. | |
19870da7 | 1285 | */ |
ace4dfee TG |
1286 | if (!chip->dev_ready) |
1287 | udelay(chip->chip_delay); | |
19870da7 TG |
1288 | else |
1289 | nand_wait_ready(mtd); | |
7314e9e7 | 1290 | } |
19870da7 | 1291 | |
0d420f9d SZ |
1292 | readlen -= ops->ooblen; |
1293 | if (!readlen) | |
1294 | break; | |
1295 | ||
7314e9e7 TG |
1296 | /* Increment page address */ |
1297 | realpage++; | |
1298 | ||
1299 | page = realpage & chip->pagemask; | |
1300 | /* Check, if we cross a chip boundary */ | |
1301 | if (!page) { | |
1302 | chipnr++; | |
1303 | chip->select_chip(mtd, -1); | |
1304 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1305 | } |
7314e9e7 TG |
1306 | |
1307 | /* Check, if the chip supports auto page increment | |
1308 | * or if we have hit a block boundary. | |
1309 | */ | |
1310 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) | |
1311 | sndcmd = 1; | |
1da177e4 LT |
1312 | } |
1313 | ||
8593fbc6 | 1314 | ops->retlen = ops->len; |
1da177e4 LT |
1315 | return 0; |
1316 | } | |
1317 | ||
1318 | /** | |
8593fbc6 | 1319 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
1da177e4 | 1320 | * @mtd: MTD device structure |
1da177e4 | 1321 | * @from: offset to read from |
8593fbc6 | 1322 | * @ops: oob operation description structure |
1da177e4 | 1323 | * |
8593fbc6 | 1324 | * NAND read data and/or out-of-band data |
1da177e4 | 1325 | */ |
8593fbc6 TG |
1326 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1327 | struct mtd_oob_ops *ops) | |
1da177e4 | 1328 | { |
ace4dfee | 1329 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1330 | int ret = -ENOTSUPP; |
1331 | ||
1332 | ops->retlen = 0; | |
1da177e4 LT |
1333 | |
1334 | /* Do not allow reads past end of device */ | |
8593fbc6 TG |
1335 | if ((from + ops->len) > mtd->size) { |
1336 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " | |
ace4dfee | 1337 | "Attempt read beyond end of device\n"); |
1da177e4 LT |
1338 | return -EINVAL; |
1339 | } | |
1340 | ||
ace4dfee | 1341 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1342 | |
8593fbc6 TG |
1343 | switch(ops->mode) { |
1344 | case MTD_OOB_PLACE: | |
1345 | case MTD_OOB_AUTO: | |
8593fbc6 | 1346 | case MTD_OOB_RAW: |
8593fbc6 | 1347 | break; |
1da177e4 | 1348 | |
8593fbc6 TG |
1349 | default: |
1350 | goto out; | |
1351 | } | |
1da177e4 | 1352 | |
8593fbc6 TG |
1353 | if (!ops->datbuf) |
1354 | ret = nand_do_read_oob(mtd, from, ops); | |
1355 | else | |
1356 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1357 | |
8593fbc6 TG |
1358 | out: |
1359 | nand_release_device(mtd); | |
1360 | return ret; | |
1361 | } | |
61b03bd7 | 1362 | |
1da177e4 | 1363 | |
8593fbc6 TG |
1364 | /** |
1365 | * nand_write_page_raw - [Intern] raw page write function | |
1366 | * @mtd: mtd info structure | |
1367 | * @chip: nand chip info structure | |
1368 | * @buf: data buffer | |
1369 | */ | |
1370 | static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1371 | const uint8_t *buf) | |
1372 | { | |
1373 | chip->write_buf(mtd, buf, mtd->writesize); | |
1374 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1da177e4 LT |
1375 | } |
1376 | ||
9223a456 | 1377 | /** |
d29ebdbe | 1378 | * nand_write_page_swecc - [REPLACABLE] software ecc based page write function |
f75e5097 TG |
1379 | * @mtd: mtd info structure |
1380 | * @chip: nand chip info structure | |
1381 | * @buf: data buffer | |
9223a456 | 1382 | */ |
f75e5097 TG |
1383 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1384 | const uint8_t *buf) | |
9223a456 | 1385 | { |
f75e5097 TG |
1386 | int i, eccsize = chip->ecc.size; |
1387 | int eccbytes = chip->ecc.bytes; | |
1388 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1389 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1390 | const uint8_t *p = buf; |
5bd34c09 | 1391 | int *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1392 | |
8593fbc6 TG |
1393 | /* Software ecc calculation */ |
1394 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1395 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1396 | |
8593fbc6 TG |
1397 | for (i = 0; i < chip->ecc.total; i++) |
1398 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1399 | |
8593fbc6 | 1400 | nand_write_page_raw(mtd, chip, buf); |
f75e5097 | 1401 | } |
9223a456 | 1402 | |
f75e5097 | 1403 | /** |
d29ebdbe | 1404 | * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function |
f75e5097 TG |
1405 | * @mtd: mtd info structure |
1406 | * @chip: nand chip info structure | |
1407 | * @buf: data buffer | |
1408 | */ | |
1409 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1410 | const uint8_t *buf) | |
1411 | { | |
1412 | int i, eccsize = chip->ecc.size; | |
1413 | int eccbytes = chip->ecc.bytes; | |
1414 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1415 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1416 | const uint8_t *p = buf; |
5bd34c09 | 1417 | int *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1418 | |
f75e5097 TG |
1419 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1420 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 1421 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 1422 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
1423 | } |
1424 | ||
f75e5097 TG |
1425 | for (i = 0; i < chip->ecc.total; i++) |
1426 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1427 | ||
1428 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
9223a456 TG |
1429 | } |
1430 | ||
61b03bd7 | 1431 | /** |
d29ebdbe | 1432 | * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write |
f75e5097 TG |
1433 | * @mtd: mtd info structure |
1434 | * @chip: nand chip info structure | |
1435 | * @buf: data buffer | |
1da177e4 | 1436 | * |
f75e5097 TG |
1437 | * The hw generator calculates the error syndrome automatically. Therefor |
1438 | * we need a special oob layout and handling. | |
1439 | */ | |
1440 | static void nand_write_page_syndrome(struct mtd_info *mtd, | |
1441 | struct nand_chip *chip, const uint8_t *buf) | |
1da177e4 | 1442 | { |
f75e5097 TG |
1443 | int i, eccsize = chip->ecc.size; |
1444 | int eccbytes = chip->ecc.bytes; | |
1445 | int eccsteps = chip->ecc.steps; | |
1446 | const uint8_t *p = buf; | |
1447 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 1448 | |
f75e5097 | 1449 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 1450 | |
f75e5097 TG |
1451 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
1452 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 1453 | |
f75e5097 TG |
1454 | if (chip->ecc.prepad) { |
1455 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1456 | oob += chip->ecc.prepad; | |
1457 | } | |
1458 | ||
1459 | chip->ecc.calculate(mtd, p, oob); | |
1460 | chip->write_buf(mtd, oob, eccbytes); | |
1461 | oob += eccbytes; | |
1462 | ||
1463 | if (chip->ecc.postpad) { | |
1464 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1465 | oob += chip->ecc.postpad; | |
1da177e4 | 1466 | } |
1da177e4 | 1467 | } |
f75e5097 TG |
1468 | |
1469 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 1470 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
1471 | if (i) |
1472 | chip->write_buf(mtd, oob, i); | |
1473 | } | |
1474 | ||
1475 | /** | |
956e944c | 1476 | * nand_write_page - [REPLACEABLE] write one page |
f75e5097 TG |
1477 | * @mtd: MTD device structure |
1478 | * @chip: NAND chip descriptor | |
1479 | * @buf: the data to write | |
1480 | * @page: page number to write | |
1481 | * @cached: cached programming | |
1482 | */ | |
1483 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
956e944c | 1484 | const uint8_t *buf, int page, int cached, int raw) |
f75e5097 TG |
1485 | { |
1486 | int status; | |
1487 | ||
1488 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
1489 | ||
956e944c DW |
1490 | if (unlikely(raw)) |
1491 | chip->ecc.write_page_raw(mtd, chip, buf); | |
1492 | else | |
1493 | chip->ecc.write_page(mtd, chip, buf); | |
f75e5097 TG |
1494 | |
1495 | /* | |
1496 | * Cached progamming disabled for now, Not sure if its worth the | |
1497 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
1498 | */ | |
1499 | cached = 0; | |
1500 | ||
1501 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
1502 | ||
1503 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 1504 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
1505 | /* |
1506 | * See if operation failed and additional status checks are | |
1507 | * available | |
1508 | */ | |
1509 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
1510 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
1511 | page); | |
1512 | ||
1513 | if (status & NAND_STATUS_FAIL) | |
1514 | return -EIO; | |
1515 | } else { | |
1516 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 1517 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
1518 | } |
1519 | ||
1520 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
1521 | /* Send command to read back the data */ | |
1522 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1523 | ||
1524 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
1525 | return -EIO; | |
1526 | #endif | |
1527 | return 0; | |
1da177e4 LT |
1528 | } |
1529 | ||
8593fbc6 TG |
1530 | /** |
1531 | * nand_fill_oob - [Internal] Transfer client buffer to oob | |
1532 | * @chip: nand chip structure | |
1533 | * @oob: oob data buffer | |
1534 | * @ops: oob ops structure | |
1535 | */ | |
1536 | static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, | |
1537 | struct mtd_oob_ops *ops) | |
1538 | { | |
1539 | size_t len = ops->ooblen; | |
1540 | ||
1541 | switch(ops->mode) { | |
1542 | ||
1543 | case MTD_OOB_PLACE: | |
1544 | case MTD_OOB_RAW: | |
1545 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); | |
1546 | return oob + len; | |
1547 | ||
1548 | case MTD_OOB_AUTO: { | |
1549 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
1550 | uint32_t boffs = 0, woffs = ops->ooboffs; |
1551 | size_t bytes = 0; | |
8593fbc6 TG |
1552 | |
1553 | for(; free->length && len; free++, len -= bytes) { | |
7bc3312b TG |
1554 | /* Write request not from offset 0 ? */ |
1555 | if (unlikely(woffs)) { | |
1556 | if (woffs >= free->length) { | |
1557 | woffs -= free->length; | |
1558 | continue; | |
1559 | } | |
1560 | boffs = free->offset + woffs; | |
1561 | bytes = min_t(size_t, len, | |
1562 | (free->length - woffs)); | |
1563 | woffs = 0; | |
1564 | } else { | |
1565 | bytes = min_t(size_t, len, free->length); | |
1566 | boffs = free->offset; | |
1567 | } | |
8b0036ee | 1568 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
1569 | oob += bytes; |
1570 | } | |
1571 | return oob; | |
1572 | } | |
1573 | default: | |
1574 | BUG(); | |
1575 | } | |
1576 | return NULL; | |
1577 | } | |
1578 | ||
28318776 | 1579 | #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0 |
1da177e4 LT |
1580 | |
1581 | /** | |
8593fbc6 | 1582 | * nand_do_write_ops - [Internal] NAND write with ECC |
1da177e4 LT |
1583 | * @mtd: MTD device structure |
1584 | * @to: offset to write to | |
8593fbc6 | 1585 | * @ops: oob operations description structure |
1da177e4 LT |
1586 | * |
1587 | * NAND write with ECC | |
1588 | */ | |
8593fbc6 TG |
1589 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
1590 | struct mtd_oob_ops *ops) | |
1da177e4 | 1591 | { |
f75e5097 | 1592 | int chipnr, realpage, page, blockmask; |
ace4dfee | 1593 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1594 | uint32_t writelen = ops->len; |
1595 | uint8_t *oob = ops->oobbuf; | |
1596 | uint8_t *buf = ops->datbuf; | |
f75e5097 | 1597 | int bytes = mtd->writesize; |
8593fbc6 | 1598 | int ret; |
1da177e4 | 1599 | |
8593fbc6 | 1600 | ops->retlen = 0; |
1da177e4 | 1601 | |
61b03bd7 | 1602 | /* reject writes, which are not page aligned */ |
8593fbc6 | 1603 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
f75e5097 TG |
1604 | printk(KERN_NOTICE "nand_write: " |
1605 | "Attempt to write not page aligned data\n"); | |
1da177e4 LT |
1606 | return -EINVAL; |
1607 | } | |
1608 | ||
8593fbc6 | 1609 | if (!writelen) |
f75e5097 | 1610 | return 0; |
1da177e4 | 1611 | |
6a930961 TG |
1612 | chipnr = (int)(to >> chip->chip_shift); |
1613 | chip->select_chip(mtd, chipnr); | |
1614 | ||
1da177e4 LT |
1615 | /* Check, if it is write protected */ |
1616 | if (nand_check_wp(mtd)) | |
8593fbc6 | 1617 | return -EIO; |
1da177e4 | 1618 | |
f75e5097 TG |
1619 | realpage = (int)(to >> chip->page_shift); |
1620 | page = realpage & chip->pagemask; | |
1621 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
1622 | ||
1623 | /* Invalidate the page cache, when we write to the cached page */ | |
1624 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 1625 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 1626 | chip->pagebuf = -1; |
61b03bd7 | 1627 | |
4bf63fcb | 1628 | chip->oob_poi = chip->buffers->oobwbuf; |
61b03bd7 | 1629 | |
f75e5097 TG |
1630 | while(1) { |
1631 | int cached = writelen > bytes && page != blockmask; | |
1da177e4 | 1632 | |
8593fbc6 TG |
1633 | if (unlikely(oob)) |
1634 | oob = nand_fill_oob(chip, oob, ops); | |
1635 | ||
956e944c DW |
1636 | ret = chip->write_page(mtd, chip, buf, page, cached, |
1637 | (ops->mode == MTD_OOB_RAW)); | |
f75e5097 TG |
1638 | if (ret) |
1639 | break; | |
1640 | ||
1641 | writelen -= bytes; | |
1642 | if (!writelen) | |
1643 | break; | |
1644 | ||
1645 | buf += bytes; | |
1646 | realpage++; | |
1647 | ||
1648 | page = realpage & chip->pagemask; | |
1649 | /* Check, if we cross a chip boundary */ | |
1650 | if (!page) { | |
1651 | chipnr++; | |
1652 | chip->select_chip(mtd, -1); | |
1653 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1654 | } |
1655 | } | |
8593fbc6 TG |
1656 | |
1657 | if (unlikely(oob)) | |
1658 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
1659 | ||
1660 | ops->retlen = ops->len - writelen; | |
1da177e4 LT |
1661 | return ret; |
1662 | } | |
1663 | ||
f75e5097 | 1664 | /** |
8593fbc6 | 1665 | * nand_write - [MTD Interface] NAND write with ECC |
f75e5097 | 1666 | * @mtd: MTD device structure |
f75e5097 TG |
1667 | * @to: offset to write to |
1668 | * @len: number of bytes to write | |
8593fbc6 TG |
1669 | * @retlen: pointer to variable to store the number of written bytes |
1670 | * @buf: the data to write | |
f75e5097 | 1671 | * |
8593fbc6 | 1672 | * NAND write with ECC |
f75e5097 | 1673 | */ |
8593fbc6 TG |
1674 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
1675 | size_t *retlen, const uint8_t *buf) | |
f75e5097 TG |
1676 | { |
1677 | struct nand_chip *chip = mtd->priv; | |
f75e5097 TG |
1678 | int ret; |
1679 | ||
8593fbc6 TG |
1680 | /* Do not allow reads past end of device */ |
1681 | if ((to + len) > mtd->size) | |
f75e5097 | 1682 | return -EINVAL; |
8593fbc6 TG |
1683 | if (!len) |
1684 | return 0; | |
f75e5097 | 1685 | |
7bc3312b | 1686 | nand_get_device(chip, mtd, FL_WRITING); |
f75e5097 | 1687 | |
8593fbc6 TG |
1688 | chip->ops.len = len; |
1689 | chip->ops.datbuf = (uint8_t *)buf; | |
1690 | chip->ops.oobbuf = NULL; | |
f75e5097 | 1691 | |
8593fbc6 | 1692 | ret = nand_do_write_ops(mtd, to, &chip->ops); |
f75e5097 | 1693 | |
7fd5aecc RP |
1694 | *retlen = chip->ops.retlen; |
1695 | ||
f75e5097 | 1696 | nand_release_device(mtd); |
8593fbc6 | 1697 | |
8593fbc6 | 1698 | return ret; |
f75e5097 | 1699 | } |
7314e9e7 | 1700 | |
1da177e4 | 1701 | /** |
8593fbc6 | 1702 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
1da177e4 LT |
1703 | * @mtd: MTD device structure |
1704 | * @to: offset to write to | |
8593fbc6 | 1705 | * @ops: oob operation description structure |
1da177e4 LT |
1706 | * |
1707 | * NAND write out-of-band | |
1708 | */ | |
8593fbc6 TG |
1709 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
1710 | struct mtd_oob_ops *ops) | |
1da177e4 | 1711 | { |
8593fbc6 | 1712 | int chipnr, page, status; |
ace4dfee | 1713 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1714 | |
7314e9e7 | 1715 | DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", |
8593fbc6 | 1716 | (unsigned int)to, (int)ops->len); |
1da177e4 LT |
1717 | |
1718 | /* Do not allow write past end of page */ | |
8593fbc6 | 1719 | if ((ops->ooboffs + ops->len) > mtd->oobsize) { |
7314e9e7 TG |
1720 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " |
1721 | "Attempt to write past end of page\n"); | |
1da177e4 LT |
1722 | return -EINVAL; |
1723 | } | |
1724 | ||
7314e9e7 | 1725 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 1726 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1727 | |
7314e9e7 TG |
1728 | /* Shift to get page */ |
1729 | page = (int)(to >> chip->page_shift); | |
1730 | ||
1731 | /* | |
1732 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
1733 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
1734 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
1735 | * it in the doc2000 driver in August 1999. dwmw2. | |
1736 | */ | |
ace4dfee | 1737 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
1738 | |
1739 | /* Check, if it is write protected */ | |
1740 | if (nand_check_wp(mtd)) | |
8593fbc6 | 1741 | return -EROFS; |
61b03bd7 | 1742 | |
1da177e4 | 1743 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
1744 | if (page == chip->pagebuf) |
1745 | chip->pagebuf = -1; | |
1da177e4 | 1746 | |
4bf63fcb | 1747 | chip->oob_poi = chip->buffers->oobwbuf; |
7bc3312b TG |
1748 | memset(chip->oob_poi, 0xff, mtd->oobsize); |
1749 | nand_fill_oob(chip, ops->oobbuf, ops); | |
1750 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1751 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
1da177e4 | 1752 | |
7bc3312b TG |
1753 | if (status) |
1754 | return status; | |
1da177e4 | 1755 | |
8593fbc6 | 1756 | ops->retlen = ops->len; |
1da177e4 | 1757 | |
7bc3312b | 1758 | return 0; |
8593fbc6 TG |
1759 | } |
1760 | ||
1761 | /** | |
1762 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
1763 | * @mtd: MTD device structure | |
844d3b42 | 1764 | * @to: offset to write to |
8593fbc6 TG |
1765 | * @ops: oob operation description structure |
1766 | */ | |
1767 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
1768 | struct mtd_oob_ops *ops) | |
1769 | { | |
8593fbc6 TG |
1770 | struct nand_chip *chip = mtd->priv; |
1771 | int ret = -ENOTSUPP; | |
1772 | ||
1773 | ops->retlen = 0; | |
1774 | ||
1775 | /* Do not allow writes past end of device */ | |
1776 | if ((to + ops->len) > mtd->size) { | |
1777 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " | |
1778 | "Attempt read beyond end of device\n"); | |
1779 | return -EINVAL; | |
1780 | } | |
1781 | ||
7bc3312b | 1782 | nand_get_device(chip, mtd, FL_WRITING); |
8593fbc6 TG |
1783 | |
1784 | switch(ops->mode) { | |
1785 | case MTD_OOB_PLACE: | |
1786 | case MTD_OOB_AUTO: | |
8593fbc6 | 1787 | case MTD_OOB_RAW: |
8593fbc6 TG |
1788 | break; |
1789 | ||
1790 | default: | |
1791 | goto out; | |
1792 | } | |
1793 | ||
1794 | if (!ops->datbuf) | |
1795 | ret = nand_do_write_oob(mtd, to, ops); | |
1796 | else | |
1797 | ret = nand_do_write_ops(mtd, to, ops); | |
1798 | ||
e0c7d767 | 1799 | out: |
1da177e4 | 1800 | nand_release_device(mtd); |
1da177e4 LT |
1801 | return ret; |
1802 | } | |
1803 | ||
1da177e4 LT |
1804 | /** |
1805 | * single_erease_cmd - [GENERIC] NAND standard block erase command function | |
1806 | * @mtd: MTD device structure | |
1807 | * @page: the page address of the block which will be erased | |
1808 | * | |
1809 | * Standard erase command for NAND chips | |
1810 | */ | |
e0c7d767 | 1811 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 1812 | { |
ace4dfee | 1813 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1814 | /* Send commands to erase a block */ |
ace4dfee TG |
1815 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
1816 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
1817 | } |
1818 | ||
1819 | /** | |
1820 | * multi_erease_cmd - [GENERIC] AND specific block erase command function | |
1821 | * @mtd: MTD device structure | |
1822 | * @page: the page address of the block which will be erased | |
1823 | * | |
1824 | * AND multi block erase command function | |
1825 | * Erase 4 consecutive blocks | |
1826 | */ | |
e0c7d767 | 1827 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 1828 | { |
ace4dfee | 1829 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1830 | /* Send commands to erase a block */ |
ace4dfee TG |
1831 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
1832 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
1833 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
1834 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
1835 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
1836 | } |
1837 | ||
1838 | /** | |
1839 | * nand_erase - [MTD Interface] erase block(s) | |
1840 | * @mtd: MTD device structure | |
1841 | * @instr: erase instruction | |
1842 | * | |
1843 | * Erase one ore more blocks | |
1844 | */ | |
e0c7d767 | 1845 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 1846 | { |
e0c7d767 | 1847 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 1848 | } |
61b03bd7 | 1849 | |
30f464b7 | 1850 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 1851 | /** |
ace4dfee | 1852 | * nand_erase_nand - [Internal] erase block(s) |
1da177e4 LT |
1853 | * @mtd: MTD device structure |
1854 | * @instr: erase instruction | |
1855 | * @allowbbt: allow erasing the bbt area | |
1856 | * | |
1857 | * Erase one ore more blocks | |
1858 | */ | |
ace4dfee TG |
1859 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
1860 | int allowbbt) | |
1da177e4 LT |
1861 | { |
1862 | int page, len, status, pages_per_block, ret, chipnr; | |
ace4dfee TG |
1863 | struct nand_chip *chip = mtd->priv; |
1864 | int rewrite_bbt[NAND_MAX_CHIPS]={0}; | |
1865 | unsigned int bbt_masked_page = 0xffffffff; | |
1da177e4 | 1866 | |
ace4dfee TG |
1867 | DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", |
1868 | (unsigned int)instr->addr, (unsigned int)instr->len); | |
1da177e4 LT |
1869 | |
1870 | /* Start address must align on block boundary */ | |
ace4dfee | 1871 | if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) { |
e0c7d767 | 1872 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); |
1da177e4 LT |
1873 | return -EINVAL; |
1874 | } | |
1875 | ||
1876 | /* Length must align on block boundary */ | |
ace4dfee TG |
1877 | if (instr->len & ((1 << chip->phys_erase_shift) - 1)) { |
1878 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " | |
1879 | "Length not block aligned\n"); | |
1da177e4 LT |
1880 | return -EINVAL; |
1881 | } | |
1882 | ||
1883 | /* Do not allow erase past end of device */ | |
1884 | if ((instr->len + instr->addr) > mtd->size) { | |
ace4dfee TG |
1885 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1886 | "Erase past end of device\n"); | |
1da177e4 LT |
1887 | return -EINVAL; |
1888 | } | |
1889 | ||
1890 | instr->fail_addr = 0xffffffff; | |
1891 | ||
1892 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 1893 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
1894 | |
1895 | /* Shift to get first page */ | |
ace4dfee TG |
1896 | page = (int)(instr->addr >> chip->page_shift); |
1897 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
1898 | |
1899 | /* Calculate pages in each block */ | |
ace4dfee | 1900 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
1901 | |
1902 | /* Select the NAND device */ | |
ace4dfee | 1903 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1904 | |
1da177e4 LT |
1905 | /* Check, if it is write protected */ |
1906 | if (nand_check_wp(mtd)) { | |
ace4dfee TG |
1907 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1908 | "Device is write protected!!!\n"); | |
1da177e4 LT |
1909 | instr->state = MTD_ERASE_FAILED; |
1910 | goto erase_exit; | |
1911 | } | |
1912 | ||
ace4dfee TG |
1913 | /* |
1914 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
1915 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
1916 | * can not be matched. This is also done when the bbt is actually | |
1917 | * erased to avoid recusrsive updates | |
1918 | */ | |
1919 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
1920 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 1921 | |
1da177e4 LT |
1922 | /* Loop through the pages */ |
1923 | len = instr->len; | |
1924 | ||
1925 | instr->state = MTD_ERASING; | |
1926 | ||
1927 | while (len) { | |
ace4dfee TG |
1928 | /* |
1929 | * heck if we have a bad block, we do not erase bad blocks ! | |
1930 | */ | |
1931 | if (nand_block_checkbad(mtd, ((loff_t) page) << | |
1932 | chip->page_shift, 0, allowbbt)) { | |
1933 | printk(KERN_WARNING "nand_erase: attempt to erase a " | |
1934 | "bad block at page 0x%08x\n", page); | |
1da177e4 LT |
1935 | instr->state = MTD_ERASE_FAILED; |
1936 | goto erase_exit; | |
1937 | } | |
61b03bd7 | 1938 | |
ace4dfee TG |
1939 | /* |
1940 | * Invalidate the page cache, if we erase the block which | |
1941 | * contains the current cached page | |
1942 | */ | |
1943 | if (page <= chip->pagebuf && chip->pagebuf < | |
1944 | (page + pages_per_block)) | |
1945 | chip->pagebuf = -1; | |
1da177e4 | 1946 | |
ace4dfee | 1947 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 1948 | |
7bc3312b | 1949 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 1950 | |
ace4dfee TG |
1951 | /* |
1952 | * See if operation failed and additional status checks are | |
1953 | * available | |
1954 | */ | |
1955 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
1956 | status = chip->errstat(mtd, chip, FL_ERASING, | |
1957 | status, page); | |
068e3c0a | 1958 | |
1da177e4 | 1959 | /* See if block erase succeeded */ |
a4ab4c5d | 1960 | if (status & NAND_STATUS_FAIL) { |
ace4dfee TG |
1961 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1962 | "Failed erase, page 0x%08x\n", page); | |
1da177e4 | 1963 | instr->state = MTD_ERASE_FAILED; |
ace4dfee | 1964 | instr->fail_addr = (page << chip->page_shift); |
1da177e4 LT |
1965 | goto erase_exit; |
1966 | } | |
30f464b7 | 1967 | |
ace4dfee TG |
1968 | /* |
1969 | * If BBT requires refresh, set the BBT rewrite flag to the | |
1970 | * page being erased | |
1971 | */ | |
1972 | if (bbt_masked_page != 0xffffffff && | |
1973 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
1974 | rewrite_bbt[chipnr] = (page << chip->page_shift); | |
61b03bd7 | 1975 | |
1da177e4 | 1976 | /* Increment page address and decrement length */ |
ace4dfee | 1977 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
1978 | page += pages_per_block; |
1979 | ||
1980 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 1981 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 1982 | chipnr++; |
ace4dfee TG |
1983 | chip->select_chip(mtd, -1); |
1984 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 1985 | |
ace4dfee TG |
1986 | /* |
1987 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
1988 | * page mask to see if this BBT should be rewritten | |
1989 | */ | |
1990 | if (bbt_masked_page != 0xffffffff && | |
1991 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
1992 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
1993 | BBT_PAGE_MASK; | |
1da177e4 LT |
1994 | } |
1995 | } | |
1996 | instr->state = MTD_ERASE_DONE; | |
1997 | ||
e0c7d767 | 1998 | erase_exit: |
1da177e4 LT |
1999 | |
2000 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
2001 | /* Do call back function */ | |
2002 | if (!ret) | |
2003 | mtd_erase_callback(instr); | |
2004 | ||
2005 | /* Deselect and wake up anyone waiting on the device */ | |
2006 | nand_release_device(mtd); | |
2007 | ||
ace4dfee TG |
2008 | /* |
2009 | * If BBT requires refresh and erase was successful, rewrite any | |
2010 | * selected bad block tables | |
2011 | */ | |
2012 | if (bbt_masked_page == 0xffffffff || ret) | |
2013 | return ret; | |
2014 | ||
2015 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2016 | if (!rewrite_bbt[chipnr]) | |
2017 | continue; | |
2018 | /* update the BBT for chip */ | |
2019 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt " | |
2020 | "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr], | |
2021 | chip->bbt_td->pages[chipnr]); | |
2022 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); | |
30f464b7 DM |
2023 | } |
2024 | ||
1da177e4 LT |
2025 | /* Return more or less happy */ |
2026 | return ret; | |
2027 | } | |
2028 | ||
2029 | /** | |
2030 | * nand_sync - [MTD Interface] sync | |
2031 | * @mtd: MTD device structure | |
2032 | * | |
2033 | * Sync is actually a wait for chip ready function | |
2034 | */ | |
e0c7d767 | 2035 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2036 | { |
ace4dfee | 2037 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2038 | |
e0c7d767 | 2039 | DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n"); |
1da177e4 LT |
2040 | |
2041 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2042 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 2043 | /* Release it and go back */ |
e0c7d767 | 2044 | nand_release_device(mtd); |
1da177e4 LT |
2045 | } |
2046 | ||
1da177e4 | 2047 | /** |
ace4dfee | 2048 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
1da177e4 | 2049 | * @mtd: MTD device structure |
844d3b42 | 2050 | * @offs: offset relative to mtd start |
1da177e4 | 2051 | */ |
ace4dfee | 2052 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 LT |
2053 | { |
2054 | /* Check for invalid offset */ | |
ace4dfee | 2055 | if (offs > mtd->size) |
1da177e4 | 2056 | return -EINVAL; |
61b03bd7 | 2057 | |
ace4dfee | 2058 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2059 | } |
2060 | ||
2061 | /** | |
ace4dfee | 2062 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
1da177e4 LT |
2063 | * @mtd: MTD device structure |
2064 | * @ofs: offset relative to mtd start | |
2065 | */ | |
e0c7d767 | 2066 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2067 | { |
ace4dfee | 2068 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2069 | int ret; |
2070 | ||
e0c7d767 DW |
2071 | if ((ret = nand_block_isbad(mtd, ofs))) { |
2072 | /* If it was bad already, return success and do nothing. */ | |
1da177e4 LT |
2073 | if (ret > 0) |
2074 | return 0; | |
e0c7d767 DW |
2075 | return ret; |
2076 | } | |
1da177e4 | 2077 | |
ace4dfee | 2078 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2079 | } |
2080 | ||
962034f4 VW |
2081 | /** |
2082 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
2083 | * @mtd: MTD device structure | |
2084 | */ | |
2085 | static int nand_suspend(struct mtd_info *mtd) | |
2086 | { | |
ace4dfee | 2087 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2088 | |
ace4dfee | 2089 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2090 | } |
2091 | ||
2092 | /** | |
2093 | * nand_resume - [MTD Interface] Resume the NAND flash | |
2094 | * @mtd: MTD device structure | |
2095 | */ | |
2096 | static void nand_resume(struct mtd_info *mtd) | |
2097 | { | |
ace4dfee | 2098 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2099 | |
ace4dfee | 2100 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2101 | nand_release_device(mtd); |
2102 | else | |
2c0a2bed TG |
2103 | printk(KERN_ERR "nand_resume() called for a chip which is not " |
2104 | "in suspended state\n"); | |
962034f4 VW |
2105 | } |
2106 | ||
7aa65bfd TG |
2107 | /* |
2108 | * Set default functions | |
2109 | */ | |
ace4dfee | 2110 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2111 | { |
1da177e4 | 2112 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2113 | if (!chip->chip_delay) |
2114 | chip->chip_delay = 20; | |
1da177e4 LT |
2115 | |
2116 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2117 | if (chip->cmdfunc == NULL) |
2118 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2119 | |
2120 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2121 | if (chip->waitfunc == NULL) |
2122 | chip->waitfunc = nand_wait; | |
2123 | ||
2124 | if (!chip->select_chip) | |
2125 | chip->select_chip = nand_select_chip; | |
2126 | if (!chip->read_byte) | |
2127 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2128 | if (!chip->read_word) | |
2129 | chip->read_word = nand_read_word; | |
2130 | if (!chip->block_bad) | |
2131 | chip->block_bad = nand_block_bad; | |
2132 | if (!chip->block_markbad) | |
2133 | chip->block_markbad = nand_default_block_markbad; | |
2134 | if (!chip->write_buf) | |
2135 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2136 | if (!chip->read_buf) | |
2137 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
2138 | if (!chip->verify_buf) | |
2139 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; | |
2140 | if (!chip->scan_bbt) | |
2141 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2142 | |
2143 | if (!chip->controller) { | |
2144 | chip->controller = &chip->hwcontrol; | |
2145 | spin_lock_init(&chip->controller->lock); | |
2146 | init_waitqueue_head(&chip->controller->wq); | |
2147 | } | |
2148 | ||
7aa65bfd TG |
2149 | } |
2150 | ||
2151 | /* | |
ace4dfee | 2152 | * Get the flash and manufacturer id and lookup if the type is supported |
7aa65bfd TG |
2153 | */ |
2154 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 2155 | struct nand_chip *chip, |
7aa65bfd TG |
2156 | int busw, int *maf_id) |
2157 | { | |
2158 | struct nand_flash_dev *type = NULL; | |
2159 | int i, dev_id, maf_idx; | |
1da177e4 LT |
2160 | |
2161 | /* Select the device */ | |
ace4dfee | 2162 | chip->select_chip(mtd, 0); |
1da177e4 LT |
2163 | |
2164 | /* Send the command for reading device ID */ | |
ace4dfee | 2165 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
2166 | |
2167 | /* Read manufacturer and device IDs */ | |
ace4dfee TG |
2168 | *maf_id = chip->read_byte(mtd); |
2169 | dev_id = chip->read_byte(mtd); | |
1da177e4 | 2170 | |
7aa65bfd | 2171 | /* Lookup the flash id */ |
1da177e4 | 2172 | for (i = 0; nand_flash_ids[i].name != NULL; i++) { |
7aa65bfd TG |
2173 | if (dev_id == nand_flash_ids[i].id) { |
2174 | type = &nand_flash_ids[i]; | |
2175 | break; | |
2176 | } | |
2177 | } | |
61b03bd7 | 2178 | |
7aa65bfd TG |
2179 | if (!type) |
2180 | return ERR_PTR(-ENODEV); | |
2181 | ||
ba0251fe TG |
2182 | if (!mtd->name) |
2183 | mtd->name = type->name; | |
2184 | ||
2185 | chip->chipsize = type->chipsize << 20; | |
7aa65bfd TG |
2186 | |
2187 | /* Newer devices have all the information in additional id bytes */ | |
ba0251fe | 2188 | if (!type->pagesize) { |
7aa65bfd TG |
2189 | int extid; |
2190 | /* The 3rd id byte contains non relevant data ATM */ | |
ace4dfee | 2191 | extid = chip->read_byte(mtd); |
7aa65bfd | 2192 | /* The 4th id byte is the important one */ |
ace4dfee | 2193 | extid = chip->read_byte(mtd); |
7aa65bfd | 2194 | /* Calc pagesize */ |
4cbb9b80 | 2195 | mtd->writesize = 1024 << (extid & 0x3); |
7aa65bfd TG |
2196 | extid >>= 2; |
2197 | /* Calc oobsize */ | |
4cbb9b80 | 2198 | mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); |
7aa65bfd TG |
2199 | extid >>= 2; |
2200 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
2201 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
2202 | extid >>= 2; | |
2203 | /* Get buswidth information */ | |
2204 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
61b03bd7 | 2205 | |
7aa65bfd TG |
2206 | } else { |
2207 | /* | |
ace4dfee | 2208 | * Old devices have chip data hardcoded in the device id table |
7aa65bfd | 2209 | */ |
ba0251fe TG |
2210 | mtd->erasesize = type->erasesize; |
2211 | mtd->writesize = type->pagesize; | |
4cbb9b80 | 2212 | mtd->oobsize = mtd->writesize / 32; |
ba0251fe | 2213 | busw = type->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2214 | } |
1da177e4 | 2215 | |
7aa65bfd | 2216 | /* Try to identify manufacturer */ |
9a909867 | 2217 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
2218 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
2219 | break; | |
2220 | } | |
0ea4a755 | 2221 | |
7aa65bfd TG |
2222 | /* |
2223 | * Check, if buswidth is correct. Hardware drivers should set | |
ace4dfee | 2224 | * chip correct ! |
7aa65bfd | 2225 | */ |
ace4dfee | 2226 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
7aa65bfd TG |
2227 | printk(KERN_INFO "NAND device: Manufacturer ID:" |
2228 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, | |
2229 | dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
2230 | printk(KERN_WARNING "NAND bus width %d instead %d bit\n", | |
ace4dfee | 2231 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
7aa65bfd TG |
2232 | busw ? 16 : 8); |
2233 | return ERR_PTR(-EINVAL); | |
2234 | } | |
61b03bd7 | 2235 | |
7aa65bfd | 2236 | /* Calculate the address shift from the page size */ |
ace4dfee | 2237 | chip->page_shift = ffs(mtd->writesize) - 1; |
7aa65bfd | 2238 | /* Convert chipsize to number of pages per chip -1. */ |
ace4dfee | 2239 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 2240 | |
ace4dfee | 2241 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 2242 | ffs(mtd->erasesize) - 1; |
ace4dfee | 2243 | chip->chip_shift = ffs(chip->chipsize) - 1; |
1da177e4 | 2244 | |
7aa65bfd | 2245 | /* Set the bad block position */ |
ace4dfee | 2246 | chip->badblockpos = mtd->writesize > 512 ? |
7aa65bfd | 2247 | NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; |
61b03bd7 | 2248 | |
7aa65bfd | 2249 | /* Get chip options, preserve non chip based options */ |
ace4dfee | 2250 | chip->options &= ~NAND_CHIPOPTIONS_MSK; |
ba0251fe | 2251 | chip->options |= type->options & NAND_CHIPOPTIONS_MSK; |
7aa65bfd TG |
2252 | |
2253 | /* | |
ace4dfee | 2254 | * Set chip as a default. Board drivers can override it, if necessary |
7aa65bfd | 2255 | */ |
ace4dfee | 2256 | chip->options |= NAND_NO_AUTOINCR; |
7aa65bfd | 2257 | |
ace4dfee | 2258 | /* Check if chip is a not a samsung device. Do not clear the |
7aa65bfd TG |
2259 | * options for chips which are not having an extended id. |
2260 | */ | |
ba0251fe | 2261 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) |
ace4dfee | 2262 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; |
7aa65bfd TG |
2263 | |
2264 | /* Check for AND chips with 4 page planes */ | |
ace4dfee TG |
2265 | if (chip->options & NAND_4PAGE_ARRAY) |
2266 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 2267 | else |
ace4dfee | 2268 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd TG |
2269 | |
2270 | /* Do not replace user supplied command function ! */ | |
ace4dfee TG |
2271 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
2272 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd TG |
2273 | |
2274 | printk(KERN_INFO "NAND device: Manufacturer ID:" | |
2275 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, | |
2276 | nand_manuf_ids[maf_idx].name, type->name); | |
2277 | ||
2278 | return type; | |
2279 | } | |
2280 | ||
7aa65bfd | 2281 | /** |
3b85c321 DW |
2282 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
2283 | * @mtd: MTD device structure | |
2284 | * @maxchips: Number of chips to scan for | |
7aa65bfd | 2285 | * |
3b85c321 DW |
2286 | * This is the first phase of the normal nand_scan() function. It |
2287 | * reads the flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 2288 | * |
3b85c321 | 2289 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 2290 | */ |
3b85c321 | 2291 | int nand_scan_ident(struct mtd_info *mtd, int maxchips) |
7aa65bfd TG |
2292 | { |
2293 | int i, busw, nand_maf_id; | |
ace4dfee | 2294 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
2295 | struct nand_flash_dev *type; |
2296 | ||
7aa65bfd | 2297 | /* Get buswidth to select the correct functions */ |
ace4dfee | 2298 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2299 | /* Set the default functions */ |
ace4dfee | 2300 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
2301 | |
2302 | /* Read the flash type */ | |
ace4dfee | 2303 | type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id); |
7aa65bfd TG |
2304 | |
2305 | if (IS_ERR(type)) { | |
e0c7d767 | 2306 | printk(KERN_WARNING "No NAND device found!!!\n"); |
ace4dfee | 2307 | chip->select_chip(mtd, -1); |
7aa65bfd | 2308 | return PTR_ERR(type); |
1da177e4 LT |
2309 | } |
2310 | ||
7aa65bfd | 2311 | /* Check for a chip array */ |
e0c7d767 | 2312 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 2313 | chip->select_chip(mtd, i); |
1da177e4 | 2314 | /* Send the command for reading device ID */ |
ace4dfee | 2315 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 2316 | /* Read manufacturer and device IDs */ |
ace4dfee TG |
2317 | if (nand_maf_id != chip->read_byte(mtd) || |
2318 | type->id != chip->read_byte(mtd)) | |
1da177e4 LT |
2319 | break; |
2320 | } | |
2321 | if (i > 1) | |
2322 | printk(KERN_INFO "%d NAND chips detected\n", i); | |
61b03bd7 | 2323 | |
1da177e4 | 2324 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
2325 | chip->numchips = i; |
2326 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 2327 | |
3b85c321 DW |
2328 | return 0; |
2329 | } | |
2330 | ||
2331 | ||
2332 | /** | |
2333 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
2334 | * @mtd: MTD device structure | |
2335 | * @maxchips: Number of chips to scan for | |
2336 | * | |
2337 | * This is the second phase of the normal nand_scan() function. It | |
2338 | * fills out all the uninitialized function pointers with the defaults | |
2339 | * and scans for a bad block table if appropriate. | |
2340 | */ | |
2341 | int nand_scan_tail(struct mtd_info *mtd) | |
2342 | { | |
2343 | int i; | |
2344 | struct nand_chip *chip = mtd->priv; | |
2345 | ||
4bf63fcb DW |
2346 | if (!(chip->options & NAND_OWN_BUFFERS)) |
2347 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
2348 | if (!chip->buffers) | |
2349 | return -ENOMEM; | |
2350 | ||
f75e5097 | 2351 | /* Preset the internal oob write buffer */ |
4bf63fcb | 2352 | memset(chip->buffers->oobwbuf, 0xff, mtd->oobsize); |
1da177e4 | 2353 | |
7aa65bfd TG |
2354 | /* |
2355 | * If no default placement scheme is given, select an appropriate one | |
2356 | */ | |
5bd34c09 | 2357 | if (!chip->ecc.layout) { |
61b03bd7 | 2358 | switch (mtd->oobsize) { |
1da177e4 | 2359 | case 8: |
5bd34c09 | 2360 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
2361 | break; |
2362 | case 16: | |
5bd34c09 | 2363 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
2364 | break; |
2365 | case 64: | |
5bd34c09 | 2366 | chip->ecc.layout = &nand_oob_64; |
1da177e4 LT |
2367 | break; |
2368 | default: | |
7aa65bfd TG |
2369 | printk(KERN_WARNING "No oob scheme defined for " |
2370 | "oobsize %d\n", mtd->oobsize); | |
1da177e4 LT |
2371 | BUG(); |
2372 | } | |
2373 | } | |
61b03bd7 | 2374 | |
956e944c DW |
2375 | if (!chip->write_page) |
2376 | chip->write_page = nand_write_page; | |
2377 | ||
61b03bd7 | 2378 | /* |
7aa65bfd TG |
2379 | * check ECC mode, default to software if 3byte/512byte hardware ECC is |
2380 | * selected and we have 256 byte pagesize fallback to software ECC | |
e0c7d767 | 2381 | */ |
956e944c DW |
2382 | if (!chip->ecc.read_page_raw) |
2383 | chip->ecc.read_page_raw = nand_read_page_raw; | |
2384 | if (!chip->ecc.write_page_raw) | |
2385 | chip->ecc.write_page_raw = nand_write_page_raw; | |
2386 | ||
ace4dfee | 2387 | switch (chip->ecc.mode) { |
6dfc6d25 | 2388 | case NAND_ECC_HW: |
f5bbdacc TG |
2389 | /* Use standard hwecc read page function ? */ |
2390 | if (!chip->ecc.read_page) | |
2391 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
2392 | if (!chip->ecc.write_page) |
2393 | chip->ecc.write_page = nand_write_page_hwecc; | |
7bc3312b TG |
2394 | if (!chip->ecc.read_oob) |
2395 | chip->ecc.read_oob = nand_read_oob_std; | |
2396 | if (!chip->ecc.write_oob) | |
2397 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 2398 | |
6dfc6d25 | 2399 | case NAND_ECC_HW_SYNDROME: |
ace4dfee TG |
2400 | if (!chip->ecc.calculate || !chip->ecc.correct || |
2401 | !chip->ecc.hwctl) { | |
6dfc6d25 TG |
2402 | printk(KERN_WARNING "No ECC functions supplied, " |
2403 | "Hardware ECC not possible\n"); | |
2404 | BUG(); | |
2405 | } | |
f75e5097 | 2406 | /* Use standard syndrome read/write page function ? */ |
f5bbdacc TG |
2407 | if (!chip->ecc.read_page) |
2408 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
2409 | if (!chip->ecc.write_page) |
2410 | chip->ecc.write_page = nand_write_page_syndrome; | |
7bc3312b TG |
2411 | if (!chip->ecc.read_oob) |
2412 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
2413 | if (!chip->ecc.write_oob) | |
2414 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 2415 | |
ace4dfee | 2416 | if (mtd->writesize >= chip->ecc.size) |
6dfc6d25 TG |
2417 | break; |
2418 | printk(KERN_WARNING "%d byte HW ECC not possible on " | |
2419 | "%d byte page size, fallback to SW ECC\n", | |
ace4dfee TG |
2420 | chip->ecc.size, mtd->writesize); |
2421 | chip->ecc.mode = NAND_ECC_SOFT; | |
61b03bd7 | 2422 | |
6dfc6d25 | 2423 | case NAND_ECC_SOFT: |
ace4dfee TG |
2424 | chip->ecc.calculate = nand_calculate_ecc; |
2425 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 2426 | chip->ecc.read_page = nand_read_page_swecc; |
f75e5097 | 2427 | chip->ecc.write_page = nand_write_page_swecc; |
7bc3312b TG |
2428 | chip->ecc.read_oob = nand_read_oob_std; |
2429 | chip->ecc.write_oob = nand_write_oob_std; | |
ace4dfee TG |
2430 | chip->ecc.size = 256; |
2431 | chip->ecc.bytes = 3; | |
1da177e4 | 2432 | break; |
61b03bd7 TG |
2433 | |
2434 | case NAND_ECC_NONE: | |
7aa65bfd TG |
2435 | printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " |
2436 | "This is not recommended !!\n"); | |
8593fbc6 TG |
2437 | chip->ecc.read_page = nand_read_page_raw; |
2438 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b TG |
2439 | chip->ecc.read_oob = nand_read_oob_std; |
2440 | chip->ecc.write_oob = nand_write_oob_std; | |
ace4dfee TG |
2441 | chip->ecc.size = mtd->writesize; |
2442 | chip->ecc.bytes = 0; | |
1da177e4 | 2443 | break; |
956e944c | 2444 | |
1da177e4 | 2445 | default: |
7aa65bfd | 2446 | printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", |
ace4dfee | 2447 | chip->ecc.mode); |
61b03bd7 | 2448 | BUG(); |
1da177e4 | 2449 | } |
61b03bd7 | 2450 | |
5bd34c09 TG |
2451 | /* |
2452 | * The number of bytes available for a client to place data into | |
2453 | * the out of band area | |
2454 | */ | |
2455 | chip->ecc.layout->oobavail = 0; | |
2456 | for (i = 0; chip->ecc.layout->oobfree[i].length; i++) | |
2457 | chip->ecc.layout->oobavail += | |
2458 | chip->ecc.layout->oobfree[i].length; | |
2459 | ||
7aa65bfd TG |
2460 | /* |
2461 | * Set the number of read / write steps for one page depending on ECC | |
2462 | * mode | |
2463 | */ | |
ace4dfee TG |
2464 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
2465 | if(chip->ecc.steps * chip->ecc.size != mtd->writesize) { | |
6dfc6d25 TG |
2466 | printk(KERN_WARNING "Invalid ecc parameters\n"); |
2467 | BUG(); | |
1da177e4 | 2468 | } |
f5bbdacc | 2469 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 2470 | |
04bbd0ea | 2471 | /* Initialize state */ |
ace4dfee | 2472 | chip->state = FL_READY; |
1da177e4 LT |
2473 | |
2474 | /* De-select the device */ | |
ace4dfee | 2475 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2476 | |
2477 | /* Invalidate the pagebuffer reference */ | |
ace4dfee | 2478 | chip->pagebuf = -1; |
1da177e4 LT |
2479 | |
2480 | /* Fill in remaining MTD driver data */ | |
2481 | mtd->type = MTD_NANDFLASH; | |
5fa43394 | 2482 | mtd->flags = MTD_CAP_NANDFLASH; |
1da177e4 LT |
2483 | mtd->ecctype = MTD_ECC_SW; |
2484 | mtd->erase = nand_erase; | |
2485 | mtd->point = NULL; | |
2486 | mtd->unpoint = NULL; | |
2487 | mtd->read = nand_read; | |
2488 | mtd->write = nand_write; | |
1da177e4 LT |
2489 | mtd->read_oob = nand_read_oob; |
2490 | mtd->write_oob = nand_write_oob; | |
1da177e4 LT |
2491 | mtd->sync = nand_sync; |
2492 | mtd->lock = NULL; | |
2493 | mtd->unlock = NULL; | |
962034f4 VW |
2494 | mtd->suspend = nand_suspend; |
2495 | mtd->resume = nand_resume; | |
1da177e4 LT |
2496 | mtd->block_isbad = nand_block_isbad; |
2497 | mtd->block_markbad = nand_block_markbad; | |
2498 | ||
5bd34c09 TG |
2499 | /* propagate ecc.layout to mtd_info */ |
2500 | mtd->ecclayout = chip->ecc.layout; | |
1da177e4 | 2501 | |
0040bf38 | 2502 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 2503 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 2504 | return 0; |
1da177e4 LT |
2505 | |
2506 | /* Build bad block table */ | |
ace4dfee | 2507 | return chip->scan_bbt(mtd); |
1da177e4 LT |
2508 | } |
2509 | ||
3b85c321 DW |
2510 | /* module_text_address() isn't exported, and it's mostly a pointless |
2511 | test if this is a module _anyway_ -- they'd have to try _really_ hard | |
2512 | to call us from in-kernel code if the core NAND support is modular. */ | |
2513 | #ifdef MODULE | |
2514 | #define caller_is_module() (1) | |
2515 | #else | |
2516 | #define caller_is_module() \ | |
2517 | module_text_address((unsigned long)__builtin_return_address(0)) | |
2518 | #endif | |
2519 | ||
2520 | /** | |
2521 | * nand_scan - [NAND Interface] Scan for the NAND device | |
2522 | * @mtd: MTD device structure | |
2523 | * @maxchips: Number of chips to scan for | |
2524 | * | |
2525 | * This fills out all the uninitialized function pointers | |
2526 | * with the defaults. | |
2527 | * The flash ID is read and the mtd/chip structures are | |
2528 | * filled with the appropriate values. | |
2529 | * The mtd->owner field must be set to the module of the caller | |
2530 | * | |
2531 | */ | |
2532 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
2533 | { | |
2534 | int ret; | |
2535 | ||
2536 | /* Many callers got this wrong, so check for it for a while... */ | |
2537 | if (!mtd->owner && caller_is_module()) { | |
2538 | printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n"); | |
2539 | BUG(); | |
2540 | } | |
2541 | ||
2542 | ret = nand_scan_ident(mtd, maxchips); | |
2543 | if (!ret) | |
2544 | ret = nand_scan_tail(mtd); | |
2545 | return ret; | |
2546 | } | |
2547 | ||
1da177e4 | 2548 | /** |
61b03bd7 | 2549 | * nand_release - [NAND Interface] Free resources held by the NAND device |
1da177e4 LT |
2550 | * @mtd: MTD device structure |
2551 | */ | |
e0c7d767 | 2552 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 2553 | { |
ace4dfee | 2554 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2555 | |
2556 | #ifdef CONFIG_MTD_PARTITIONS | |
2557 | /* Deregister partitions */ | |
e0c7d767 | 2558 | del_mtd_partitions(mtd); |
1da177e4 LT |
2559 | #endif |
2560 | /* Deregister the device */ | |
e0c7d767 | 2561 | del_mtd_device(mtd); |
1da177e4 | 2562 | |
fa671646 | 2563 | /* Free bad block table memory */ |
ace4dfee | 2564 | kfree(chip->bbt); |
4bf63fcb DW |
2565 | if (!(chip->options & NAND_OWN_BUFFERS)) |
2566 | kfree(chip->buffers); | |
1da177e4 LT |
2567 | } |
2568 | ||
e0c7d767 | 2569 | EXPORT_SYMBOL_GPL(nand_scan); |
3b85c321 DW |
2570 | EXPORT_SYMBOL_GPL(nand_scan_ident); |
2571 | EXPORT_SYMBOL_GPL(nand_scan_tail); | |
e0c7d767 | 2572 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
2573 | |
2574 | static int __init nand_base_init(void) | |
2575 | { | |
2576 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
2577 | return 0; | |
2578 | } | |
2579 | ||
2580 | static void __exit nand_base_exit(void) | |
2581 | { | |
2582 | led_trigger_unregister_simple(nand_led_trigger); | |
2583 | } | |
2584 | ||
2585 | module_init(nand_base_init); | |
2586 | module_exit(nand_base_exit); | |
2587 | ||
e0c7d767 DW |
2588 | MODULE_LICENSE("GPL"); |
2589 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); | |
2590 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |