Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Additional technical information is available on |
8b2b403c | 10 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
24 | * if we have HW ecc support. | |
25 | * The AG-AND chips have nice features for speed improvement, | |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
c0b8ba7b | 27 | * BBT table is not serialized, has to be fixed |
1da177e4 | 28 | * |
1da177e4 LT |
29 | * This program is free software; you can redistribute it and/or modify |
30 | * it under the terms of the GNU General Public License version 2 as | |
31 | * published by the Free Software Foundation. | |
32 | * | |
33 | */ | |
34 | ||
552d9205 | 35 | #include <linux/module.h> |
1da177e4 LT |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
7aa65bfd | 38 | #include <linux/err.h> |
1da177e4 LT |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
45 | #include <linux/mtd/compatmac.h> | |
46 | #include <linux/interrupt.h> | |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
1da177e4 LT |
49 | #include <asm/io.h> |
50 | ||
51 | #ifdef CONFIG_MTD_PARTITIONS | |
52 | #include <linux/mtd/partitions.h> | |
53 | #endif | |
54 | ||
55 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 56 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
57 | .eccbytes = 3, |
58 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
59 | .oobfree = { |
60 | {.offset = 3, | |
61 | .length = 2}, | |
62 | {.offset = 6, | |
63 | .length = 2}} | |
1da177e4 LT |
64 | }; |
65 | ||
5bd34c09 | 66 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
67 | .eccbytes = 6, |
68 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
69 | .oobfree = { |
70 | {.offset = 8, | |
71 | . length = 8}} | |
1da177e4 LT |
72 | }; |
73 | ||
5bd34c09 | 74 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
75 | .eccbytes = 24, |
76 | .eccpos = { | |
e0c7d767 DW |
77 | 40, 41, 42, 43, 44, 45, 46, 47, |
78 | 48, 49, 50, 51, 52, 53, 54, 55, | |
79 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
80 | .oobfree = { |
81 | {.offset = 2, | |
82 | .length = 38}} | |
1da177e4 LT |
83 | }; |
84 | ||
81ec5364 TG |
85 | static struct nand_ecclayout nand_oob_128 = { |
86 | .eccbytes = 48, | |
87 | .eccpos = { | |
88 | 80, 81, 82, 83, 84, 85, 86, 87, | |
89 | 88, 89, 90, 91, 92, 93, 94, 95, | |
90 | 96, 97, 98, 99, 100, 101, 102, 103, | |
91 | 104, 105, 106, 107, 108, 109, 110, 111, | |
92 | 112, 113, 114, 115, 116, 117, 118, 119, | |
93 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
94 | .oobfree = { | |
95 | {.offset = 2, | |
96 | .length = 78}} | |
97 | }; | |
98 | ||
ace4dfee | 99 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 100 | int new_state); |
1da177e4 | 101 | |
8593fbc6 TG |
102 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
103 | struct mtd_oob_ops *ops); | |
104 | ||
d470a97c | 105 | /* |
8e87d782 | 106 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
107 | * compiled away when LED support is disabled. |
108 | */ | |
109 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
110 | ||
6fe5a6ac VS |
111 | static int check_offs_len(struct mtd_info *mtd, |
112 | loff_t ofs, uint64_t len) | |
113 | { | |
114 | struct nand_chip *chip = mtd->priv; | |
115 | int ret = 0; | |
116 | ||
117 | /* Start address must align on block boundary */ | |
118 | if (ofs & ((1 << chip->phys_erase_shift) - 1)) { | |
119 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__); | |
120 | ret = -EINVAL; | |
121 | } | |
122 | ||
123 | /* Length must align on block boundary */ | |
124 | if (len & ((1 << chip->phys_erase_shift) - 1)) { | |
125 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n", | |
126 | __func__); | |
127 | ret = -EINVAL; | |
128 | } | |
129 | ||
130 | /* Do not allow past end of device */ | |
131 | if (ofs + len > mtd->size) { | |
132 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n", | |
133 | __func__); | |
134 | ret = -EINVAL; | |
135 | } | |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
1da177e4 LT |
140 | /** |
141 | * nand_release_device - [GENERIC] release chip | |
142 | * @mtd: MTD device structure | |
61b03bd7 TG |
143 | * |
144 | * Deselect, release chip lock and wake up anyone waiting on the device | |
1da177e4 | 145 | */ |
e0c7d767 | 146 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 147 | { |
ace4dfee | 148 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
149 | |
150 | /* De-select the NAND device */ | |
ace4dfee | 151 | chip->select_chip(mtd, -1); |
0dfc6246 | 152 | |
a36ed299 | 153 | /* Release the controller and the chip */ |
ace4dfee TG |
154 | spin_lock(&chip->controller->lock); |
155 | chip->controller->active = NULL; | |
156 | chip->state = FL_READY; | |
157 | wake_up(&chip->controller->wq); | |
158 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
159 | } |
160 | ||
161 | /** | |
162 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
163 | * @mtd: MTD device structure | |
164 | * | |
165 | * Default read function for 8bit buswith | |
166 | */ | |
58dd8f2b | 167 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 168 | { |
ace4dfee TG |
169 | struct nand_chip *chip = mtd->priv; |
170 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
171 | } |
172 | ||
1da177e4 LT |
173 | /** |
174 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip | |
175 | * @mtd: MTD device structure | |
176 | * | |
61b03bd7 | 177 | * Default read function for 16bit buswith with |
1da177e4 LT |
178 | * endianess conversion |
179 | */ | |
58dd8f2b | 180 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 181 | { |
ace4dfee TG |
182 | struct nand_chip *chip = mtd->priv; |
183 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
184 | } |
185 | ||
1da177e4 LT |
186 | /** |
187 | * nand_read_word - [DEFAULT] read one word from the chip | |
188 | * @mtd: MTD device structure | |
189 | * | |
61b03bd7 | 190 | * Default read function for 16bit buswith without |
1da177e4 LT |
191 | * endianess conversion |
192 | */ | |
193 | static u16 nand_read_word(struct mtd_info *mtd) | |
194 | { | |
ace4dfee TG |
195 | struct nand_chip *chip = mtd->priv; |
196 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
197 | } |
198 | ||
1da177e4 LT |
199 | /** |
200 | * nand_select_chip - [DEFAULT] control CE line | |
201 | * @mtd: MTD device structure | |
844d3b42 | 202 | * @chipnr: chipnumber to select, -1 for deselect |
1da177e4 LT |
203 | * |
204 | * Default select function for 1 chip devices. | |
205 | */ | |
ace4dfee | 206 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 207 | { |
ace4dfee TG |
208 | struct nand_chip *chip = mtd->priv; |
209 | ||
210 | switch (chipnr) { | |
1da177e4 | 211 | case -1: |
ace4dfee | 212 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
213 | break; |
214 | case 0: | |
1da177e4 LT |
215 | break; |
216 | ||
217 | default: | |
218 | BUG(); | |
219 | } | |
220 | } | |
221 | ||
222 | /** | |
223 | * nand_write_buf - [DEFAULT] write buffer to chip | |
224 | * @mtd: MTD device structure | |
225 | * @buf: data buffer | |
226 | * @len: number of bytes to write | |
227 | * | |
228 | * Default write function for 8bit buswith | |
229 | */ | |
58dd8f2b | 230 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
231 | { |
232 | int i; | |
ace4dfee | 233 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 234 | |
e0c7d767 | 235 | for (i = 0; i < len; i++) |
ace4dfee | 236 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
237 | } |
238 | ||
239 | /** | |
61b03bd7 | 240 | * nand_read_buf - [DEFAULT] read chip data into buffer |
1da177e4 LT |
241 | * @mtd: MTD device structure |
242 | * @buf: buffer to store date | |
243 | * @len: number of bytes to read | |
244 | * | |
245 | * Default read function for 8bit buswith | |
246 | */ | |
58dd8f2b | 247 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
248 | { |
249 | int i; | |
ace4dfee | 250 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 251 | |
e0c7d767 | 252 | for (i = 0; i < len; i++) |
ace4dfee | 253 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
254 | } |
255 | ||
256 | /** | |
61b03bd7 | 257 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
258 | * @mtd: MTD device structure |
259 | * @buf: buffer containing the data to compare | |
260 | * @len: number of bytes to compare | |
261 | * | |
262 | * Default verify function for 8bit buswith | |
263 | */ | |
58dd8f2b | 264 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
265 | { |
266 | int i; | |
ace4dfee | 267 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 268 | |
e0c7d767 | 269 | for (i = 0; i < len; i++) |
ace4dfee | 270 | if (buf[i] != readb(chip->IO_ADDR_R)) |
1da177e4 | 271 | return -EFAULT; |
1da177e4 LT |
272 | return 0; |
273 | } | |
274 | ||
275 | /** | |
276 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
277 | * @mtd: MTD device structure | |
278 | * @buf: data buffer | |
279 | * @len: number of bytes to write | |
280 | * | |
281 | * Default write function for 16bit buswith | |
282 | */ | |
58dd8f2b | 283 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
284 | { |
285 | int i; | |
ace4dfee | 286 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
287 | u16 *p = (u16 *) buf; |
288 | len >>= 1; | |
61b03bd7 | 289 | |
e0c7d767 | 290 | for (i = 0; i < len; i++) |
ace4dfee | 291 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 292 | |
1da177e4 LT |
293 | } |
294 | ||
295 | /** | |
61b03bd7 | 296 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
1da177e4 LT |
297 | * @mtd: MTD device structure |
298 | * @buf: buffer to store date | |
299 | * @len: number of bytes to read | |
300 | * | |
301 | * Default read function for 16bit buswith | |
302 | */ | |
58dd8f2b | 303 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
304 | { |
305 | int i; | |
ace4dfee | 306 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
307 | u16 *p = (u16 *) buf; |
308 | len >>= 1; | |
309 | ||
e0c7d767 | 310 | for (i = 0; i < len; i++) |
ace4dfee | 311 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
312 | } |
313 | ||
314 | /** | |
61b03bd7 | 315 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
316 | * @mtd: MTD device structure |
317 | * @buf: buffer containing the data to compare | |
318 | * @len: number of bytes to compare | |
319 | * | |
320 | * Default verify function for 16bit buswith | |
321 | */ | |
58dd8f2b | 322 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
323 | { |
324 | int i; | |
ace4dfee | 325 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
326 | u16 *p = (u16 *) buf; |
327 | len >>= 1; | |
328 | ||
e0c7d767 | 329 | for (i = 0; i < len; i++) |
ace4dfee | 330 | if (p[i] != readw(chip->IO_ADDR_R)) |
1da177e4 LT |
331 | return -EFAULT; |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
336 | /** | |
337 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
338 | * @mtd: MTD device structure | |
339 | * @ofs: offset from device start | |
340 | * @getchip: 0, if the chip is already selected | |
341 | * | |
61b03bd7 | 342 | * Check, if the block is bad. |
1da177e4 LT |
343 | */ |
344 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
345 | { | |
346 | int page, chipnr, res = 0; | |
ace4dfee | 347 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
348 | u16 bad; |
349 | ||
30fe8115 | 350 | if (chip->options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
351 | ofs += mtd->erasesize - mtd->writesize; |
352 | ||
1a12f46a TK |
353 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
354 | ||
1da177e4 | 355 | if (getchip) { |
ace4dfee | 356 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 357 | |
ace4dfee | 358 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
359 | |
360 | /* Select the NAND device */ | |
ace4dfee | 361 | chip->select_chip(mtd, chipnr); |
1a12f46a | 362 | } |
1da177e4 | 363 | |
ace4dfee TG |
364 | if (chip->options & NAND_BUSWIDTH_16) { |
365 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, | |
1a12f46a | 366 | page); |
ace4dfee TG |
367 | bad = cpu_to_le16(chip->read_word(mtd)); |
368 | if (chip->badblockpos & 0x1) | |
49196f33 | 369 | bad >>= 8; |
e0b58d0a ML |
370 | else |
371 | bad &= 0xFF; | |
1da177e4 | 372 | } else { |
1a12f46a | 373 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); |
e0b58d0a | 374 | bad = chip->read_byte(mtd); |
1da177e4 | 375 | } |
61b03bd7 | 376 | |
e0b58d0a ML |
377 | if (likely(chip->badblockbits == 8)) |
378 | res = bad != 0xFF; | |
379 | else | |
380 | res = hweight8(bad) < chip->badblockbits; | |
381 | ||
ace4dfee | 382 | if (getchip) |
1da177e4 | 383 | nand_release_device(mtd); |
61b03bd7 | 384 | |
1da177e4 LT |
385 | return res; |
386 | } | |
387 | ||
388 | /** | |
389 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
390 | * @mtd: MTD device structure | |
391 | * @ofs: offset from device start | |
392 | * | |
393 | * This is the default implementation, which can be overridden by | |
394 | * a hardware specific driver. | |
395 | */ | |
396 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
397 | { | |
ace4dfee | 398 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 399 | uint8_t buf[2] = { 0, 0 }; |
f1a28c02 | 400 | int block, ret; |
61b03bd7 | 401 | |
30fe8115 | 402 | if (chip->options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
403 | ofs += mtd->erasesize - mtd->writesize; |
404 | ||
1da177e4 | 405 | /* Get block number */ |
4226b510 | 406 | block = (int)(ofs >> chip->bbt_erase_shift); |
ace4dfee TG |
407 | if (chip->bbt) |
408 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 LT |
409 | |
410 | /* Do we have a flash based bad block table ? */ | |
ace4dfee | 411 | if (chip->options & NAND_USE_FLASH_BBT) |
f1a28c02 TG |
412 | ret = nand_update_bbt(mtd, ofs); |
413 | else { | |
414 | /* We write two bytes, so we dont have to mess with 16 bit | |
415 | * access | |
416 | */ | |
c0b8ba7b | 417 | nand_get_device(chip, mtd, FL_WRITING); |
f1a28c02 | 418 | ofs += mtd->oobsize; |
ff0dab64 | 419 | chip->ops.len = chip->ops.ooblen = 2; |
f1a28c02 TG |
420 | chip->ops.datbuf = NULL; |
421 | chip->ops.oobbuf = buf; | |
422 | chip->ops.ooboffs = chip->badblockpos & ~0x01; | |
423 | ||
424 | ret = nand_do_write_oob(mtd, ofs, &chip->ops); | |
c0b8ba7b | 425 | nand_release_device(mtd); |
f1a28c02 TG |
426 | } |
427 | if (!ret) | |
428 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 429 | |
f1a28c02 | 430 | return ret; |
1da177e4 LT |
431 | } |
432 | ||
61b03bd7 | 433 | /** |
1da177e4 LT |
434 | * nand_check_wp - [GENERIC] check if the chip is write protected |
435 | * @mtd: MTD device structure | |
61b03bd7 | 436 | * Check, if the device is write protected |
1da177e4 | 437 | * |
61b03bd7 | 438 | * The function expects, that the device is already selected |
1da177e4 | 439 | */ |
e0c7d767 | 440 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 441 | { |
ace4dfee | 442 | struct nand_chip *chip = mtd->priv; |
93edbad6 ML |
443 | |
444 | /* broken xD cards report WP despite being writable */ | |
445 | if (chip->options & NAND_BROKEN_XD) | |
446 | return 0; | |
447 | ||
1da177e4 | 448 | /* Check the WP bit */ |
ace4dfee TG |
449 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
450 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
451 | } |
452 | ||
453 | /** | |
454 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
455 | * @mtd: MTD device structure | |
456 | * @ofs: offset from device start | |
457 | * @getchip: 0, if the chip is already selected | |
458 | * @allowbbt: 1, if its allowed to access the bbt area | |
459 | * | |
460 | * Check, if the block is bad. Either by reading the bad block table or | |
461 | * calling of the scan function. | |
462 | */ | |
2c0a2bed TG |
463 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
464 | int allowbbt) | |
1da177e4 | 465 | { |
ace4dfee | 466 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 467 | |
ace4dfee TG |
468 | if (!chip->bbt) |
469 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 470 | |
1da177e4 | 471 | /* Return info from the table */ |
e0c7d767 | 472 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
473 | } |
474 | ||
2af7c653 SK |
475 | /** |
476 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
477 | * @mtd: MTD device structure | |
478 | * @timeo: Timeout | |
479 | * | |
480 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
481 | * context. | |
482 | */ | |
483 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
484 | { | |
485 | struct nand_chip *chip = mtd->priv; | |
486 | int i; | |
487 | ||
488 | /* Wait for the device to get ready */ | |
489 | for (i = 0; i < timeo; i++) { | |
490 | if (chip->dev_ready(mtd)) | |
491 | break; | |
492 | touch_softlockup_watchdog(); | |
493 | mdelay(1); | |
494 | } | |
495 | } | |
496 | ||
61b03bd7 | 497 | /* |
3b88775c TG |
498 | * Wait for the ready pin, after a command |
499 | * The timeout is catched later. | |
500 | */ | |
4b648b02 | 501 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 502 | { |
ace4dfee | 503 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 504 | unsigned long timeo = jiffies + 2; |
3b88775c | 505 | |
2af7c653 SK |
506 | /* 400ms timeout */ |
507 | if (in_interrupt() || oops_in_progress) | |
508 | return panic_nand_wait_ready(mtd, 400); | |
509 | ||
8fe833c1 | 510 | led_trigger_event(nand_led_trigger, LED_FULL); |
3b88775c TG |
511 | /* wait until command is processed or timeout occures */ |
512 | do { | |
ace4dfee | 513 | if (chip->dev_ready(mtd)) |
8fe833c1 | 514 | break; |
8446f1d3 | 515 | touch_softlockup_watchdog(); |
61b03bd7 | 516 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 517 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 518 | } |
4b648b02 | 519 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 520 | |
1da177e4 LT |
521 | /** |
522 | * nand_command - [DEFAULT] Send command to NAND device | |
523 | * @mtd: MTD device structure | |
524 | * @command: the command to be sent | |
525 | * @column: the column address for this command, -1 if none | |
526 | * @page_addr: the page address for this command, -1 if none | |
527 | * | |
528 | * Send command to NAND device. This function is used for small page | |
529 | * devices (256/512 Bytes per page) | |
530 | */ | |
7abd3ef9 TG |
531 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
532 | int column, int page_addr) | |
1da177e4 | 533 | { |
ace4dfee | 534 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 535 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 536 | |
1da177e4 LT |
537 | /* |
538 | * Write out the command to the device. | |
539 | */ | |
540 | if (command == NAND_CMD_SEQIN) { | |
541 | int readcmd; | |
542 | ||
28318776 | 543 | if (column >= mtd->writesize) { |
1da177e4 | 544 | /* OOB area */ |
28318776 | 545 | column -= mtd->writesize; |
1da177e4 LT |
546 | readcmd = NAND_CMD_READOOB; |
547 | } else if (column < 256) { | |
548 | /* First 256 bytes --> READ0 */ | |
549 | readcmd = NAND_CMD_READ0; | |
550 | } else { | |
551 | column -= 256; | |
552 | readcmd = NAND_CMD_READ1; | |
553 | } | |
ace4dfee | 554 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 555 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 556 | } |
ace4dfee | 557 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 558 | |
7abd3ef9 TG |
559 | /* |
560 | * Address cycle, when necessary | |
561 | */ | |
562 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; | |
563 | /* Serially input address */ | |
564 | if (column != -1) { | |
565 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 566 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 567 | column >>= 1; |
ace4dfee | 568 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
569 | ctrl &= ~NAND_CTRL_CHANGE; |
570 | } | |
571 | if (page_addr != -1) { | |
ace4dfee | 572 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 573 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 574 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 575 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
576 | if (chip->chipsize > (32 << 20)) |
577 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 578 | } |
ace4dfee | 579 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
580 | |
581 | /* | |
582 | * program and erase have their own busy handlers | |
1da177e4 | 583 | * status and sequential in needs no delay |
e0c7d767 | 584 | */ |
1da177e4 | 585 | switch (command) { |
61b03bd7 | 586 | |
1da177e4 LT |
587 | case NAND_CMD_PAGEPROG: |
588 | case NAND_CMD_ERASE1: | |
589 | case NAND_CMD_ERASE2: | |
590 | case NAND_CMD_SEQIN: | |
591 | case NAND_CMD_STATUS: | |
592 | return; | |
593 | ||
594 | case NAND_CMD_RESET: | |
ace4dfee | 595 | if (chip->dev_ready) |
1da177e4 | 596 | break; |
ace4dfee TG |
597 | udelay(chip->chip_delay); |
598 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 599 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
600 | chip->cmd_ctrl(mtd, |
601 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 602 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
603 | return; |
604 | ||
e0c7d767 | 605 | /* This applies to read commands */ |
1da177e4 | 606 | default: |
61b03bd7 | 607 | /* |
1da177e4 LT |
608 | * If we don't have access to the busy pin, we apply the given |
609 | * command delay | |
e0c7d767 | 610 | */ |
ace4dfee TG |
611 | if (!chip->dev_ready) { |
612 | udelay(chip->chip_delay); | |
1da177e4 | 613 | return; |
61b03bd7 | 614 | } |
1da177e4 | 615 | } |
1da177e4 LT |
616 | /* Apply this short delay always to ensure that we do wait tWB in |
617 | * any case on any machine. */ | |
e0c7d767 | 618 | ndelay(100); |
3b88775c TG |
619 | |
620 | nand_wait_ready(mtd); | |
1da177e4 LT |
621 | } |
622 | ||
623 | /** | |
624 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
625 | * @mtd: MTD device structure | |
626 | * @command: the command to be sent | |
627 | * @column: the column address for this command, -1 if none | |
628 | * @page_addr: the page address for this command, -1 if none | |
629 | * | |
7abd3ef9 TG |
630 | * Send command to NAND device. This is the version for the new large page |
631 | * devices We dont have the separate regions as we have in the small page | |
632 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 633 | */ |
7abd3ef9 TG |
634 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
635 | int column, int page_addr) | |
1da177e4 | 636 | { |
ace4dfee | 637 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
638 | |
639 | /* Emulate NAND_CMD_READOOB */ | |
640 | if (command == NAND_CMD_READOOB) { | |
28318776 | 641 | column += mtd->writesize; |
1da177e4 LT |
642 | command = NAND_CMD_READ0; |
643 | } | |
61b03bd7 | 644 | |
7abd3ef9 | 645 | /* Command latch cycle */ |
ace4dfee | 646 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 647 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
648 | |
649 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 650 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
651 | |
652 | /* Serially input address */ | |
653 | if (column != -1) { | |
654 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 655 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 656 | column >>= 1; |
ace4dfee | 657 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 658 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 659 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 660 | } |
1da177e4 | 661 | if (page_addr != -1) { |
ace4dfee TG |
662 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
663 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 664 | NAND_NCE | NAND_ALE); |
1da177e4 | 665 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
666 | if (chip->chipsize > (128 << 20)) |
667 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 668 | NAND_NCE | NAND_ALE); |
1da177e4 | 669 | } |
1da177e4 | 670 | } |
ace4dfee | 671 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
672 | |
673 | /* | |
674 | * program and erase have their own busy handlers | |
30f464b7 DM |
675 | * status, sequential in, and deplete1 need no delay |
676 | */ | |
1da177e4 | 677 | switch (command) { |
61b03bd7 | 678 | |
1da177e4 LT |
679 | case NAND_CMD_CACHEDPROG: |
680 | case NAND_CMD_PAGEPROG: | |
681 | case NAND_CMD_ERASE1: | |
682 | case NAND_CMD_ERASE2: | |
683 | case NAND_CMD_SEQIN: | |
7bc3312b | 684 | case NAND_CMD_RNDIN: |
1da177e4 | 685 | case NAND_CMD_STATUS: |
30f464b7 | 686 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
687 | return; |
688 | ||
e0c7d767 DW |
689 | /* |
690 | * read error status commands require only a short delay | |
691 | */ | |
30f464b7 DM |
692 | case NAND_CMD_STATUS_ERROR: |
693 | case NAND_CMD_STATUS_ERROR0: | |
694 | case NAND_CMD_STATUS_ERROR1: | |
695 | case NAND_CMD_STATUS_ERROR2: | |
696 | case NAND_CMD_STATUS_ERROR3: | |
ace4dfee | 697 | udelay(chip->chip_delay); |
30f464b7 | 698 | return; |
1da177e4 LT |
699 | |
700 | case NAND_CMD_RESET: | |
ace4dfee | 701 | if (chip->dev_ready) |
1da177e4 | 702 | break; |
ace4dfee | 703 | udelay(chip->chip_delay); |
12efdde3 TG |
704 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
705 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
706 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
707 | NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 708 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
709 | return; |
710 | ||
7bc3312b TG |
711 | case NAND_CMD_RNDOUT: |
712 | /* No ready / busy check necessary */ | |
713 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
714 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
715 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
716 | NAND_NCE | NAND_CTRL_CHANGE); | |
717 | return; | |
718 | ||
1da177e4 | 719 | case NAND_CMD_READ0: |
12efdde3 TG |
720 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
721 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
722 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
723 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 724 | |
e0c7d767 | 725 | /* This applies to read commands */ |
1da177e4 | 726 | default: |
61b03bd7 | 727 | /* |
1da177e4 LT |
728 | * If we don't have access to the busy pin, we apply the given |
729 | * command delay | |
e0c7d767 | 730 | */ |
ace4dfee TG |
731 | if (!chip->dev_ready) { |
732 | udelay(chip->chip_delay); | |
1da177e4 | 733 | return; |
61b03bd7 | 734 | } |
1da177e4 | 735 | } |
3b88775c | 736 | |
1da177e4 LT |
737 | /* Apply this short delay always to ensure that we do wait tWB in |
738 | * any case on any machine. */ | |
e0c7d767 | 739 | ndelay(100); |
3b88775c TG |
740 | |
741 | nand_wait_ready(mtd); | |
1da177e4 LT |
742 | } |
743 | ||
2af7c653 SK |
744 | /** |
745 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
746 | * @chip: the nand chip descriptor | |
747 | * @mtd: MTD device structure | |
748 | * @new_state: the state which is requested | |
749 | * | |
750 | * Used when in panic, no locks are taken. | |
751 | */ | |
752 | static void panic_nand_get_device(struct nand_chip *chip, | |
753 | struct mtd_info *mtd, int new_state) | |
754 | { | |
755 | /* Hardware controller shared among independend devices */ | |
756 | chip->controller->active = chip; | |
757 | chip->state = new_state; | |
758 | } | |
759 | ||
1da177e4 LT |
760 | /** |
761 | * nand_get_device - [GENERIC] Get chip for selected access | |
844d3b42 | 762 | * @chip: the nand chip descriptor |
1da177e4 | 763 | * @mtd: MTD device structure |
61b03bd7 | 764 | * @new_state: the state which is requested |
1da177e4 LT |
765 | * |
766 | * Get the device and lock it for exclusive access | |
767 | */ | |
2c0a2bed | 768 | static int |
ace4dfee | 769 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 770 | { |
ace4dfee TG |
771 | spinlock_t *lock = &chip->controller->lock; |
772 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 773 | DECLARE_WAITQUEUE(wait, current); |
e0c7d767 | 774 | retry: |
0dfc6246 TG |
775 | spin_lock(lock); |
776 | ||
b8b3ee9a | 777 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
778 | if (!chip->controller->active) |
779 | chip->controller->active = chip; | |
a36ed299 | 780 | |
ace4dfee TG |
781 | if (chip->controller->active == chip && chip->state == FL_READY) { |
782 | chip->state = new_state; | |
0dfc6246 | 783 | spin_unlock(lock); |
962034f4 VW |
784 | return 0; |
785 | } | |
786 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
787 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
788 | chip->state = FL_PM_SUSPENDED; | |
789 | spin_unlock(lock); | |
790 | return 0; | |
6b0d9a84 | 791 | } |
0dfc6246 TG |
792 | } |
793 | set_current_state(TASK_UNINTERRUPTIBLE); | |
794 | add_wait_queue(wq, &wait); | |
795 | spin_unlock(lock); | |
796 | schedule(); | |
797 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
798 | goto retry; |
799 | } | |
800 | ||
2af7c653 SK |
801 | /** |
802 | * panic_nand_wait - [GENERIC] wait until the command is done | |
803 | * @mtd: MTD device structure | |
804 | * @chip: NAND chip structure | |
805 | * @timeo: Timeout | |
806 | * | |
807 | * Wait for command done. This is a helper function for nand_wait used when | |
808 | * we are in interrupt context. May happen when in panic and trying to write | |
809 | * an oops trough mtdoops. | |
810 | */ | |
811 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
812 | unsigned long timeo) | |
813 | { | |
814 | int i; | |
815 | for (i = 0; i < timeo; i++) { | |
816 | if (chip->dev_ready) { | |
817 | if (chip->dev_ready(mtd)) | |
818 | break; | |
819 | } else { | |
820 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
821 | break; | |
822 | } | |
823 | mdelay(1); | |
824 | } | |
825 | } | |
826 | ||
1da177e4 LT |
827 | /** |
828 | * nand_wait - [DEFAULT] wait until the command is done | |
829 | * @mtd: MTD device structure | |
844d3b42 | 830 | * @chip: NAND chip structure |
1da177e4 LT |
831 | * |
832 | * Wait for command done. This applies to erase and program only | |
61b03bd7 | 833 | * Erase can take up to 400ms and program up to 20ms according to |
1da177e4 | 834 | * general NAND and SmartMedia specs |
844d3b42 | 835 | */ |
7bc3312b | 836 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
837 | { |
838 | ||
e0c7d767 | 839 | unsigned long timeo = jiffies; |
7bc3312b | 840 | int status, state = chip->state; |
61b03bd7 | 841 | |
1da177e4 | 842 | if (state == FL_ERASING) |
e0c7d767 | 843 | timeo += (HZ * 400) / 1000; |
1da177e4 | 844 | else |
e0c7d767 | 845 | timeo += (HZ * 20) / 1000; |
1da177e4 | 846 | |
8fe833c1 RP |
847 | led_trigger_event(nand_led_trigger, LED_FULL); |
848 | ||
1da177e4 LT |
849 | /* Apply this short delay always to ensure that we do wait tWB in |
850 | * any case on any machine. */ | |
e0c7d767 | 851 | ndelay(100); |
1da177e4 | 852 | |
ace4dfee TG |
853 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
854 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 855 | else |
ace4dfee | 856 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 857 | |
2af7c653 SK |
858 | if (in_interrupt() || oops_in_progress) |
859 | panic_nand_wait(mtd, chip, timeo); | |
860 | else { | |
861 | while (time_before(jiffies, timeo)) { | |
862 | if (chip->dev_ready) { | |
863 | if (chip->dev_ready(mtd)) | |
864 | break; | |
865 | } else { | |
866 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
867 | break; | |
868 | } | |
869 | cond_resched(); | |
1da177e4 | 870 | } |
1da177e4 | 871 | } |
8fe833c1 RP |
872 | led_trigger_event(nand_led_trigger, LED_OFF); |
873 | ||
ace4dfee | 874 | status = (int)chip->read_byte(mtd); |
1da177e4 LT |
875 | return status; |
876 | } | |
877 | ||
7d70f334 VS |
878 | /** |
879 | * __nand_unlock - [REPLACABLE] unlocks specified locked blockes | |
880 | * | |
881 | * @param mtd - mtd info | |
882 | * @param ofs - offset to start unlock from | |
883 | * @param len - length to unlock | |
884 | * @invert - when = 0, unlock the range of blocks within the lower and | |
885 | * upper boundary address | |
886 | * whne = 1, unlock the range of blocks outside the boundaries | |
887 | * of the lower and upper boundary address | |
888 | * | |
889 | * @return - unlock status | |
890 | */ | |
891 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
892 | uint64_t len, int invert) | |
893 | { | |
894 | int ret = 0; | |
895 | int status, page; | |
896 | struct nand_chip *chip = mtd->priv; | |
897 | ||
898 | /* Submit address of first page to unlock */ | |
899 | page = ofs >> chip->page_shift; | |
900 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
901 | ||
902 | /* Submit address of last page to unlock */ | |
903 | page = (ofs + len) >> chip->page_shift; | |
904 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
905 | (page | invert) & chip->pagemask); | |
906 | ||
907 | /* Call wait ready function */ | |
908 | status = chip->waitfunc(mtd, chip); | |
909 | udelay(1000); | |
910 | /* See if device thinks it succeeded */ | |
911 | if (status & 0x01) { | |
912 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n", | |
913 | __func__, status); | |
914 | ret = -EIO; | |
915 | } | |
916 | ||
917 | return ret; | |
918 | } | |
919 | ||
920 | /** | |
921 | * nand_unlock - [REPLACABLE] unlocks specified locked blockes | |
922 | * | |
923 | * @param mtd - mtd info | |
924 | * @param ofs - offset to start unlock from | |
925 | * @param len - length to unlock | |
926 | * | |
927 | * @return - unlock status | |
928 | */ | |
929 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
930 | { | |
931 | int ret = 0; | |
932 | int chipnr; | |
933 | struct nand_chip *chip = mtd->priv; | |
934 | ||
935 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", | |
936 | __func__, (unsigned long long)ofs, len); | |
937 | ||
938 | if (check_offs_len(mtd, ofs, len)) | |
939 | ret = -EINVAL; | |
940 | ||
941 | /* Align to last block address if size addresses end of the device */ | |
942 | if (ofs + len == mtd->size) | |
943 | len -= mtd->erasesize; | |
944 | ||
945 | nand_get_device(chip, mtd, FL_UNLOCKING); | |
946 | ||
947 | /* Shift to get chip number */ | |
948 | chipnr = ofs >> chip->chip_shift; | |
949 | ||
950 | chip->select_chip(mtd, chipnr); | |
951 | ||
952 | /* Check, if it is write protected */ | |
953 | if (nand_check_wp(mtd)) { | |
954 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", | |
955 | __func__); | |
956 | ret = -EIO; | |
957 | goto out; | |
958 | } | |
959 | ||
960 | ret = __nand_unlock(mtd, ofs, len, 0); | |
961 | ||
962 | out: | |
963 | /* de-select the NAND device */ | |
964 | chip->select_chip(mtd, -1); | |
965 | ||
966 | nand_release_device(mtd); | |
967 | ||
968 | return ret; | |
969 | } | |
970 | ||
971 | /** | |
972 | * nand_lock - [REPLACABLE] locks all blockes present in the device | |
973 | * | |
974 | * @param mtd - mtd info | |
975 | * @param ofs - offset to start unlock from | |
976 | * @param len - length to unlock | |
977 | * | |
978 | * @return - lock status | |
979 | * | |
980 | * This feature is not support in many NAND parts. 'Micron' NAND parts | |
981 | * do have this feature, but it allows only to lock all blocks not for | |
982 | * specified range for block. | |
983 | * | |
984 | * Implementing 'lock' feature by making use of 'unlock', for now. | |
985 | */ | |
986 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
987 | { | |
988 | int ret = 0; | |
989 | int chipnr, status, page; | |
990 | struct nand_chip *chip = mtd->priv; | |
991 | ||
992 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", | |
993 | __func__, (unsigned long long)ofs, len); | |
994 | ||
995 | if (check_offs_len(mtd, ofs, len)) | |
996 | ret = -EINVAL; | |
997 | ||
998 | nand_get_device(chip, mtd, FL_LOCKING); | |
999 | ||
1000 | /* Shift to get chip number */ | |
1001 | chipnr = ofs >> chip->chip_shift; | |
1002 | ||
1003 | chip->select_chip(mtd, chipnr); | |
1004 | ||
1005 | /* Check, if it is write protected */ | |
1006 | if (nand_check_wp(mtd)) { | |
1007 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", | |
1008 | __func__); | |
1009 | status = MTD_ERASE_FAILED; | |
1010 | ret = -EIO; | |
1011 | goto out; | |
1012 | } | |
1013 | ||
1014 | /* Submit address of first page to lock */ | |
1015 | page = ofs >> chip->page_shift; | |
1016 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1017 | ||
1018 | /* Call wait ready function */ | |
1019 | status = chip->waitfunc(mtd, chip); | |
1020 | udelay(1000); | |
1021 | /* See if device thinks it succeeded */ | |
1022 | if (status & 0x01) { | |
1023 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n", | |
1024 | __func__, status); | |
1025 | ret = -EIO; | |
1026 | goto out; | |
1027 | } | |
1028 | ||
1029 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1030 | ||
1031 | out: | |
1032 | /* de-select the NAND device */ | |
1033 | chip->select_chip(mtd, -1); | |
1034 | ||
1035 | nand_release_device(mtd); | |
1036 | ||
1037 | return ret; | |
1038 | } | |
1039 | ||
8593fbc6 TG |
1040 | /** |
1041 | * nand_read_page_raw - [Intern] read raw page data without ecc | |
1042 | * @mtd: mtd info structure | |
1043 | * @chip: nand chip info structure | |
1044 | * @buf: buffer to store read data | |
58475fb9 | 1045 | * @page: page number to read |
52ff49df DB |
1046 | * |
1047 | * Not for syndrome calculating ecc controllers, which use a special oob layout | |
8593fbc6 TG |
1048 | */ |
1049 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1050 | uint8_t *buf, int page) |
8593fbc6 TG |
1051 | { |
1052 | chip->read_buf(mtd, buf, mtd->writesize); | |
1053 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1054 | return 0; | |
1055 | } | |
1056 | ||
52ff49df DB |
1057 | /** |
1058 | * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc | |
1059 | * @mtd: mtd info structure | |
1060 | * @chip: nand chip info structure | |
1061 | * @buf: buffer to store read data | |
58475fb9 | 1062 | * @page: page number to read |
52ff49df DB |
1063 | * |
1064 | * We need a special oob layout and handling even when OOB isn't used. | |
1065 | */ | |
1066 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1067 | uint8_t *buf, int page) |
52ff49df DB |
1068 | { |
1069 | int eccsize = chip->ecc.size; | |
1070 | int eccbytes = chip->ecc.bytes; | |
1071 | uint8_t *oob = chip->oob_poi; | |
1072 | int steps, size; | |
1073 | ||
1074 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1075 | chip->read_buf(mtd, buf, eccsize); | |
1076 | buf += eccsize; | |
1077 | ||
1078 | if (chip->ecc.prepad) { | |
1079 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1080 | oob += chip->ecc.prepad; | |
1081 | } | |
1082 | ||
1083 | chip->read_buf(mtd, oob, eccbytes); | |
1084 | oob += eccbytes; | |
1085 | ||
1086 | if (chip->ecc.postpad) { | |
1087 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1088 | oob += chip->ecc.postpad; | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1093 | if (size) | |
1094 | chip->read_buf(mtd, oob, size); | |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
1da177e4 | 1099 | /** |
d29ebdbe | 1100 | * nand_read_page_swecc - [REPLACABLE] software ecc based page read function |
f5bbdacc TG |
1101 | * @mtd: mtd info structure |
1102 | * @chip: nand chip info structure | |
1103 | * @buf: buffer to store read data | |
58475fb9 | 1104 | * @page: page number to read |
068e3c0a | 1105 | */ |
f5bbdacc | 1106 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1107 | uint8_t *buf, int page) |
1da177e4 | 1108 | { |
f5bbdacc TG |
1109 | int i, eccsize = chip->ecc.size; |
1110 | int eccbytes = chip->ecc.bytes; | |
1111 | int eccsteps = chip->ecc.steps; | |
1112 | uint8_t *p = buf; | |
4bf63fcb DW |
1113 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1114 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1115 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc | 1116 | |
46a8cf2d | 1117 | chip->ecc.read_page_raw(mtd, chip, buf, page); |
f5bbdacc TG |
1118 | |
1119 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1120 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1121 | ||
1122 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1123 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1124 | |
1125 | eccsteps = chip->ecc.steps; | |
1126 | p = buf; | |
1127 | ||
1128 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1129 | int stat; | |
1130 | ||
1131 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
c32b8dcc | 1132 | if (stat < 0) |
f5bbdacc TG |
1133 | mtd->ecc_stats.failed++; |
1134 | else | |
1135 | mtd->ecc_stats.corrected += stat; | |
1136 | } | |
1137 | return 0; | |
22c60f5f | 1138 | } |
1da177e4 | 1139 | |
3d459559 AK |
1140 | /** |
1141 | * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function | |
1142 | * @mtd: mtd info structure | |
1143 | * @chip: nand chip info structure | |
17c1d2be AK |
1144 | * @data_offs: offset of requested data within the page |
1145 | * @readlen: data length | |
1146 | * @bufpoi: buffer to store read data | |
3d459559 AK |
1147 | */ |
1148 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) | |
1149 | { | |
1150 | int start_step, end_step, num_steps; | |
1151 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1152 | uint8_t *p; | |
1153 | int data_col_addr, i, gaps = 0; | |
1154 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1155 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
1156 | ||
1157 | /* Column address wihin the page aligned to ECC size (256bytes). */ | |
1158 | start_step = data_offs / chip->ecc.size; | |
1159 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1160 | num_steps = end_step - start_step + 1; | |
1161 | ||
1162 | /* Data size aligned to ECC ecc.size*/ | |
1163 | datafrag_len = num_steps * chip->ecc.size; | |
1164 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1165 | ||
1166 | data_col_addr = start_step * chip->ecc.size; | |
1167 | /* If we read not a page aligned data */ | |
1168 | if (data_col_addr != 0) | |
1169 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1170 | ||
1171 | p = bufpoi + data_col_addr; | |
1172 | chip->read_buf(mtd, p, datafrag_len); | |
1173 | ||
1174 | /* Calculate ECC */ | |
1175 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) | |
1176 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1177 | ||
1178 | /* The performance is faster if to position offsets | |
1179 | according to ecc.pos. Let make sure here that | |
1180 | there are no gaps in ecc positions */ | |
1181 | for (i = 0; i < eccfrag_len - 1; i++) { | |
1182 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1183 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1184 | gaps = 1; | |
1185 | break; | |
1186 | } | |
1187 | } | |
1188 | if (gaps) { | |
1189 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1190 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1191 | } else { | |
1192 | /* send the command to read the particular ecc bytes */ | |
1193 | /* take care about buswidth alignment in read_buf */ | |
1194 | aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1); | |
1195 | aligned_len = eccfrag_len; | |
1196 | if (eccpos[start_step * chip->ecc.bytes] & (busw - 1)) | |
1197 | aligned_len++; | |
1198 | if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1)) | |
1199 | aligned_len++; | |
1200 | ||
1201 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1); | |
1202 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); | |
1203 | } | |
1204 | ||
1205 | for (i = 0; i < eccfrag_len; i++) | |
1206 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]]; | |
1207 | ||
1208 | p = bufpoi + data_col_addr; | |
1209 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1210 | int stat; | |
1211 | ||
1212 | stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
1213 | if (stat == -1) | |
1214 | mtd->ecc_stats.failed++; | |
1215 | else | |
1216 | mtd->ecc_stats.corrected += stat; | |
1217 | } | |
1218 | return 0; | |
1219 | } | |
1220 | ||
068e3c0a | 1221 | /** |
d29ebdbe | 1222 | * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function |
f5bbdacc TG |
1223 | * @mtd: mtd info structure |
1224 | * @chip: nand chip info structure | |
1225 | * @buf: buffer to store read data | |
58475fb9 | 1226 | * @page: page number to read |
068e3c0a | 1227 | * |
f5bbdacc | 1228 | * Not for syndrome calculating ecc controllers which need a special oob layout |
068e3c0a | 1229 | */ |
f5bbdacc | 1230 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1231 | uint8_t *buf, int page) |
1da177e4 | 1232 | { |
f5bbdacc TG |
1233 | int i, eccsize = chip->ecc.size; |
1234 | int eccbytes = chip->ecc.bytes; | |
1235 | int eccsteps = chip->ecc.steps; | |
1236 | uint8_t *p = buf; | |
4bf63fcb DW |
1237 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1238 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1239 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc TG |
1240 | |
1241 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1242 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1243 | chip->read_buf(mtd, p, eccsize); | |
1244 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1245 | } |
f75e5097 | 1246 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1247 | |
f5bbdacc | 1248 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1249 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1250 | |
f5bbdacc TG |
1251 | eccsteps = chip->ecc.steps; |
1252 | p = buf; | |
61b03bd7 | 1253 | |
f5bbdacc TG |
1254 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1255 | int stat; | |
1da177e4 | 1256 | |
f5bbdacc | 1257 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
c32b8dcc | 1258 | if (stat < 0) |
f5bbdacc TG |
1259 | mtd->ecc_stats.failed++; |
1260 | else | |
1261 | mtd->ecc_stats.corrected += stat; | |
1262 | } | |
1263 | return 0; | |
1264 | } | |
1da177e4 | 1265 | |
6e0cb135 SN |
1266 | /** |
1267 | * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first | |
1268 | * @mtd: mtd info structure | |
1269 | * @chip: nand chip info structure | |
1270 | * @buf: buffer to store read data | |
58475fb9 | 1271 | * @page: page number to read |
6e0cb135 SN |
1272 | * |
1273 | * Hardware ECC for large page chips, require OOB to be read first. | |
1274 | * For this ECC mode, the write_page method is re-used from ECC_HW. | |
1275 | * These methods read/write ECC from the OOB area, unlike the | |
1276 | * ECC_HW_SYNDROME support with multiple ECC steps, follows the | |
1277 | * "infix ECC" scheme and reads/writes ECC from the data area, by | |
1278 | * overwriting the NAND manufacturer bad block markings. | |
1279 | */ | |
1280 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1281 | struct nand_chip *chip, uint8_t *buf, int page) | |
1282 | { | |
1283 | int i, eccsize = chip->ecc.size; | |
1284 | int eccbytes = chip->ecc.bytes; | |
1285 | int eccsteps = chip->ecc.steps; | |
1286 | uint8_t *p = buf; | |
1287 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1288 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1289 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1290 | ||
1291 | /* Read the OOB area first */ | |
1292 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1293 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1294 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1295 | ||
1296 | for (i = 0; i < chip->ecc.total; i++) | |
1297 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1298 | ||
1299 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1300 | int stat; | |
1301 | ||
1302 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1303 | chip->read_buf(mtd, p, eccsize); | |
1304 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1305 | ||
1306 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
1307 | if (stat < 0) | |
1308 | mtd->ecc_stats.failed++; | |
1309 | else | |
1310 | mtd->ecc_stats.corrected += stat; | |
1311 | } | |
1312 | return 0; | |
1313 | } | |
1314 | ||
f5bbdacc | 1315 | /** |
d29ebdbe | 1316 | * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read |
f5bbdacc TG |
1317 | * @mtd: mtd info structure |
1318 | * @chip: nand chip info structure | |
1319 | * @buf: buffer to store read data | |
58475fb9 | 1320 | * @page: page number to read |
f5bbdacc TG |
1321 | * |
1322 | * The hw generator calculates the error syndrome automatically. Therefor | |
f75e5097 | 1323 | * we need a special oob layout and handling. |
f5bbdacc TG |
1324 | */ |
1325 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1326 | uint8_t *buf, int page) |
f5bbdacc TG |
1327 | { |
1328 | int i, eccsize = chip->ecc.size; | |
1329 | int eccbytes = chip->ecc.bytes; | |
1330 | int eccsteps = chip->ecc.steps; | |
1331 | uint8_t *p = buf; | |
f75e5097 | 1332 | uint8_t *oob = chip->oob_poi; |
1da177e4 | 1333 | |
f5bbdacc TG |
1334 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1335 | int stat; | |
61b03bd7 | 1336 | |
f5bbdacc TG |
1337 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1338 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1339 | |
f5bbdacc TG |
1340 | if (chip->ecc.prepad) { |
1341 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1342 | oob += chip->ecc.prepad; | |
1343 | } | |
1da177e4 | 1344 | |
f5bbdacc TG |
1345 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1346 | chip->read_buf(mtd, oob, eccbytes); | |
1347 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1348 | |
c32b8dcc | 1349 | if (stat < 0) |
f5bbdacc | 1350 | mtd->ecc_stats.failed++; |
61b03bd7 | 1351 | else |
f5bbdacc | 1352 | mtd->ecc_stats.corrected += stat; |
61b03bd7 | 1353 | |
f5bbdacc | 1354 | oob += eccbytes; |
1da177e4 | 1355 | |
f5bbdacc TG |
1356 | if (chip->ecc.postpad) { |
1357 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1358 | oob += chip->ecc.postpad; | |
61b03bd7 | 1359 | } |
f5bbdacc | 1360 | } |
1da177e4 | 1361 | |
f5bbdacc | 1362 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1363 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1364 | if (i) |
1365 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1366 | |
f5bbdacc TG |
1367 | return 0; |
1368 | } | |
1da177e4 | 1369 | |
f5bbdacc | 1370 | /** |
8593fbc6 TG |
1371 | * nand_transfer_oob - [Internal] Transfer oob to client buffer |
1372 | * @chip: nand chip structure | |
844d3b42 | 1373 | * @oob: oob destination address |
8593fbc6 | 1374 | * @ops: oob ops structure |
7014568b | 1375 | * @len: size of oob to transfer |
8593fbc6 TG |
1376 | */ |
1377 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1378 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1379 | { |
8593fbc6 TG |
1380 | switch(ops->mode) { |
1381 | ||
1382 | case MTD_OOB_PLACE: | |
1383 | case MTD_OOB_RAW: | |
1384 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); | |
1385 | return oob + len; | |
1386 | ||
1387 | case MTD_OOB_AUTO: { | |
1388 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
1389 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1390 | size_t bytes = 0; | |
8593fbc6 TG |
1391 | |
1392 | for(; free->length && len; free++, len -= bytes) { | |
7bc3312b TG |
1393 | /* Read request not from offset 0 ? */ |
1394 | if (unlikely(roffs)) { | |
1395 | if (roffs >= free->length) { | |
1396 | roffs -= free->length; | |
1397 | continue; | |
1398 | } | |
1399 | boffs = free->offset + roffs; | |
1400 | bytes = min_t(size_t, len, | |
1401 | (free->length - roffs)); | |
1402 | roffs = 0; | |
1403 | } else { | |
1404 | bytes = min_t(size_t, len, free->length); | |
1405 | boffs = free->offset; | |
1406 | } | |
1407 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1408 | oob += bytes; |
1409 | } | |
1410 | return oob; | |
1411 | } | |
1412 | default: | |
1413 | BUG(); | |
1414 | } | |
1415 | return NULL; | |
1416 | } | |
1417 | ||
1418 | /** | |
1419 | * nand_do_read_ops - [Internal] Read data with ECC | |
f5bbdacc TG |
1420 | * |
1421 | * @mtd: MTD device structure | |
1422 | * @from: offset to read from | |
844d3b42 | 1423 | * @ops: oob ops structure |
f5bbdacc TG |
1424 | * |
1425 | * Internal function. Called with chip held. | |
1426 | */ | |
8593fbc6 TG |
1427 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1428 | struct mtd_oob_ops *ops) | |
f5bbdacc TG |
1429 | { |
1430 | int chipnr, page, realpage, col, bytes, aligned; | |
1431 | struct nand_chip *chip = mtd->priv; | |
1432 | struct mtd_ecc_stats stats; | |
1433 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
1434 | int sndcmd = 1; | |
1435 | int ret = 0; | |
8593fbc6 | 1436 | uint32_t readlen = ops->len; |
7014568b | 1437 | uint32_t oobreadlen = ops->ooblen; |
9aca334e ML |
1438 | uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ? |
1439 | mtd->oobavail : mtd->oobsize; | |
1440 | ||
8593fbc6 | 1441 | uint8_t *bufpoi, *oob, *buf; |
1da177e4 | 1442 | |
f5bbdacc | 1443 | stats = mtd->ecc_stats; |
1da177e4 | 1444 | |
f5bbdacc TG |
1445 | chipnr = (int)(from >> chip->chip_shift); |
1446 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1447 | |
f5bbdacc TG |
1448 | realpage = (int)(from >> chip->page_shift); |
1449 | page = realpage & chip->pagemask; | |
1da177e4 | 1450 | |
f5bbdacc | 1451 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1452 | |
8593fbc6 TG |
1453 | buf = ops->datbuf; |
1454 | oob = ops->oobbuf; | |
1455 | ||
f5bbdacc TG |
1456 | while(1) { |
1457 | bytes = min(mtd->writesize - col, readlen); | |
1458 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1459 | |
f5bbdacc | 1460 | /* Is the current page in the buffer ? */ |
8593fbc6 | 1461 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1462 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1463 | |
f5bbdacc TG |
1464 | if (likely(sndcmd)) { |
1465 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
1466 | sndcmd = 0; | |
1da177e4 | 1467 | } |
1da177e4 | 1468 | |
f5bbdacc | 1469 | /* Now read the page into the buffer */ |
956e944c | 1470 | if (unlikely(ops->mode == MTD_OOB_RAW)) |
46a8cf2d SN |
1471 | ret = chip->ecc.read_page_raw(mtd, chip, |
1472 | bufpoi, page); | |
3d459559 AK |
1473 | else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) |
1474 | ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); | |
956e944c | 1475 | else |
46a8cf2d SN |
1476 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
1477 | page); | |
f5bbdacc | 1478 | if (ret < 0) |
1da177e4 | 1479 | break; |
f5bbdacc TG |
1480 | |
1481 | /* Transfer not aligned data */ | |
1482 | if (!aligned) { | |
3d459559 AK |
1483 | if (!NAND_SUBPAGE_READ(chip) && !oob) |
1484 | chip->pagebuf = realpage; | |
4bf63fcb | 1485 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1486 | } |
1487 | ||
8593fbc6 TG |
1488 | buf += bytes; |
1489 | ||
1490 | if (unlikely(oob)) { | |
9aca334e | 1491 | |
b64d39d8 ML |
1492 | int toread = min(oobreadlen, max_oobsize); |
1493 | ||
1494 | if (toread) { | |
1495 | oob = nand_transfer_oob(chip, | |
1496 | oob, ops, toread); | |
1497 | oobreadlen -= toread; | |
1498 | } | |
8593fbc6 TG |
1499 | } |
1500 | ||
f5bbdacc TG |
1501 | if (!(chip->options & NAND_NO_READRDY)) { |
1502 | /* | |
1503 | * Apply delay or wait for ready/busy pin. Do | |
1504 | * this before the AUTOINCR check, so no | |
1505 | * problems arise if a chip which does auto | |
1506 | * increment is marked as NOAUTOINCR by the | |
1507 | * board driver. | |
1508 | */ | |
1509 | if (!chip->dev_ready) | |
1510 | udelay(chip->chip_delay); | |
1511 | else | |
1512 | nand_wait_ready(mtd); | |
1da177e4 | 1513 | } |
8593fbc6 | 1514 | } else { |
4bf63fcb | 1515 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 TG |
1516 | buf += bytes; |
1517 | } | |
1da177e4 | 1518 | |
f5bbdacc | 1519 | readlen -= bytes; |
61b03bd7 | 1520 | |
f5bbdacc | 1521 | if (!readlen) |
61b03bd7 | 1522 | break; |
1da177e4 LT |
1523 | |
1524 | /* For subsequent reads align to page boundary. */ | |
1525 | col = 0; | |
1526 | /* Increment page address */ | |
1527 | realpage++; | |
1528 | ||
ace4dfee | 1529 | page = realpage & chip->pagemask; |
1da177e4 LT |
1530 | /* Check, if we cross a chip boundary */ |
1531 | if (!page) { | |
1532 | chipnr++; | |
ace4dfee TG |
1533 | chip->select_chip(mtd, -1); |
1534 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1535 | } |
f5bbdacc | 1536 | |
61b03bd7 TG |
1537 | /* Check, if the chip supports auto page increment |
1538 | * or if we have hit a block boundary. | |
e0c7d767 | 1539 | */ |
f5bbdacc | 1540 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
61b03bd7 | 1541 | sndcmd = 1; |
1da177e4 LT |
1542 | } |
1543 | ||
8593fbc6 | 1544 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1545 | if (oob) |
1546 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1547 | |
f5bbdacc TG |
1548 | if (ret) |
1549 | return ret; | |
1550 | ||
9a1fcdfd TG |
1551 | if (mtd->ecc_stats.failed - stats.failed) |
1552 | return -EBADMSG; | |
1553 | ||
1554 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
f5bbdacc TG |
1555 | } |
1556 | ||
1557 | /** | |
1558 | * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc | |
1559 | * @mtd: MTD device structure | |
1560 | * @from: offset to read from | |
1561 | * @len: number of bytes to read | |
1562 | * @retlen: pointer to variable to store the number of read bytes | |
1563 | * @buf: the databuffer to put data | |
1564 | * | |
1565 | * Get hold of the chip and call nand_do_read | |
1566 | */ | |
1567 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1568 | size_t *retlen, uint8_t *buf) | |
1569 | { | |
8593fbc6 | 1570 | struct nand_chip *chip = mtd->priv; |
f5bbdacc TG |
1571 | int ret; |
1572 | ||
f5bbdacc TG |
1573 | /* Do not allow reads past end of device */ |
1574 | if ((from + len) > mtd->size) | |
1575 | return -EINVAL; | |
1576 | if (!len) | |
1577 | return 0; | |
1578 | ||
8593fbc6 | 1579 | nand_get_device(chip, mtd, FL_READING); |
f5bbdacc | 1580 | |
8593fbc6 TG |
1581 | chip->ops.len = len; |
1582 | chip->ops.datbuf = buf; | |
1583 | chip->ops.oobbuf = NULL; | |
1584 | ||
1585 | ret = nand_do_read_ops(mtd, from, &chip->ops); | |
f5bbdacc | 1586 | |
7fd5aecc RP |
1587 | *retlen = chip->ops.retlen; |
1588 | ||
f5bbdacc TG |
1589 | nand_release_device(mtd); |
1590 | ||
1591 | return ret; | |
1da177e4 LT |
1592 | } |
1593 | ||
7bc3312b TG |
1594 | /** |
1595 | * nand_read_oob_std - [REPLACABLE] the most common OOB data read function | |
1596 | * @mtd: mtd info structure | |
1597 | * @chip: nand chip info structure | |
1598 | * @page: page number to read | |
1599 | * @sndcmd: flag whether to issue read command or not | |
1600 | */ | |
1601 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1602 | int page, int sndcmd) | |
1603 | { | |
1604 | if (sndcmd) { | |
1605 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1606 | sndcmd = 0; | |
1607 | } | |
1608 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1609 | return sndcmd; | |
1610 | } | |
1611 | ||
1612 | /** | |
1613 | * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC | |
1614 | * with syndromes | |
1615 | * @mtd: mtd info structure | |
1616 | * @chip: nand chip info structure | |
1617 | * @page: page number to read | |
1618 | * @sndcmd: flag whether to issue read command or not | |
1619 | */ | |
1620 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1621 | int page, int sndcmd) | |
1622 | { | |
1623 | uint8_t *buf = chip->oob_poi; | |
1624 | int length = mtd->oobsize; | |
1625 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1626 | int eccsize = chip->ecc.size; | |
1627 | uint8_t *bufpoi = buf; | |
1628 | int i, toread, sndrnd = 0, pos; | |
1629 | ||
1630 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1631 | for (i = 0; i < chip->ecc.steps; i++) { | |
1632 | if (sndrnd) { | |
1633 | pos = eccsize + i * (eccsize + chunk); | |
1634 | if (mtd->writesize > 512) | |
1635 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1636 | else | |
1637 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1638 | } else | |
1639 | sndrnd = 1; | |
1640 | toread = min_t(int, length, chunk); | |
1641 | chip->read_buf(mtd, bufpoi, toread); | |
1642 | bufpoi += toread; | |
1643 | length -= toread; | |
1644 | } | |
1645 | if (length > 0) | |
1646 | chip->read_buf(mtd, bufpoi, length); | |
1647 | ||
1648 | return 1; | |
1649 | } | |
1650 | ||
1651 | /** | |
1652 | * nand_write_oob_std - [REPLACABLE] the most common OOB data write function | |
1653 | * @mtd: mtd info structure | |
1654 | * @chip: nand chip info structure | |
1655 | * @page: page number to write | |
1656 | */ | |
1657 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1658 | int page) | |
1659 | { | |
1660 | int status = 0; | |
1661 | const uint8_t *buf = chip->oob_poi; | |
1662 | int length = mtd->oobsize; | |
1663 | ||
1664 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1665 | chip->write_buf(mtd, buf, length); | |
1666 | /* Send command to program the OOB data */ | |
1667 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1668 | ||
1669 | status = chip->waitfunc(mtd, chip); | |
1670 | ||
0d420f9d | 1671 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1672 | } |
1673 | ||
1674 | /** | |
1675 | * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC | |
1676 | * with syndrome - only for large page flash ! | |
1677 | * @mtd: mtd info structure | |
1678 | * @chip: nand chip info structure | |
1679 | * @page: page number to write | |
1680 | */ | |
1681 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1682 | struct nand_chip *chip, int page) | |
1683 | { | |
1684 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1685 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1686 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1687 | const uint8_t *bufpoi = chip->oob_poi; | |
1688 | ||
1689 | /* | |
1690 | * data-ecc-data-ecc ... ecc-oob | |
1691 | * or | |
1692 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1693 | */ | |
1694 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1695 | pos = steps * (eccsize + chunk); | |
1696 | steps = 0; | |
1697 | } else | |
8b0036ee | 1698 | pos = eccsize; |
7bc3312b TG |
1699 | |
1700 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1701 | for (i = 0; i < steps; i++) { | |
1702 | if (sndcmd) { | |
1703 | if (mtd->writesize <= 512) { | |
1704 | uint32_t fill = 0xFFFFFFFF; | |
1705 | ||
1706 | len = eccsize; | |
1707 | while (len > 0) { | |
1708 | int num = min_t(int, len, 4); | |
1709 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1710 | num); | |
1711 | len -= num; | |
1712 | } | |
1713 | } else { | |
1714 | pos = eccsize + i * (eccsize + chunk); | |
1715 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1716 | } | |
1717 | } else | |
1718 | sndcmd = 1; | |
1719 | len = min_t(int, length, chunk); | |
1720 | chip->write_buf(mtd, bufpoi, len); | |
1721 | bufpoi += len; | |
1722 | length -= len; | |
1723 | } | |
1724 | if (length > 0) | |
1725 | chip->write_buf(mtd, bufpoi, length); | |
1726 | ||
1727 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1728 | status = chip->waitfunc(mtd, chip); | |
1729 | ||
1730 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1731 | } | |
1732 | ||
1da177e4 | 1733 | /** |
8593fbc6 | 1734 | * nand_do_read_oob - [Intern] NAND read out-of-band |
1da177e4 LT |
1735 | * @mtd: MTD device structure |
1736 | * @from: offset to read from | |
8593fbc6 | 1737 | * @ops: oob operations description structure |
1da177e4 LT |
1738 | * |
1739 | * NAND read out-of-band data from the spare area | |
1740 | */ | |
8593fbc6 TG |
1741 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1742 | struct mtd_oob_ops *ops) | |
1da177e4 | 1743 | { |
7bc3312b | 1744 | int page, realpage, chipnr, sndcmd = 1; |
ace4dfee | 1745 | struct nand_chip *chip = mtd->priv; |
7314e9e7 | 1746 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
7014568b VW |
1747 | int readlen = ops->ooblen; |
1748 | int len; | |
7bc3312b | 1749 | uint8_t *buf = ops->oobbuf; |
61b03bd7 | 1750 | |
20d8e248 | 1751 | DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n", |
1752 | __func__, (unsigned long long)from, readlen); | |
1da177e4 | 1753 | |
03736155 | 1754 | if (ops->mode == MTD_OOB_AUTO) |
7014568b | 1755 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1756 | else |
1757 | len = mtd->oobsize; | |
1758 | ||
1759 | if (unlikely(ops->ooboffs >= len)) { | |
20d8e248 | 1760 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read " |
1761 | "outside oob\n", __func__); | |
03736155 AH |
1762 | return -EINVAL; |
1763 | } | |
1764 | ||
1765 | /* Do not allow reads past end of device */ | |
1766 | if (unlikely(from >= mtd->size || | |
1767 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1768 | (from >> chip->page_shift)) * len)) { | |
20d8e248 | 1769 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end " |
1770 | "of device\n", __func__); | |
03736155 AH |
1771 | return -EINVAL; |
1772 | } | |
7014568b | 1773 | |
7314e9e7 | 1774 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1775 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1776 | |
7314e9e7 TG |
1777 | /* Shift to get page */ |
1778 | realpage = (int)(from >> chip->page_shift); | |
1779 | page = realpage & chip->pagemask; | |
1da177e4 | 1780 | |
7314e9e7 | 1781 | while(1) { |
7bc3312b | 1782 | sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); |
7014568b VW |
1783 | |
1784 | len = min(len, readlen); | |
1785 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1786 | |
7314e9e7 TG |
1787 | if (!(chip->options & NAND_NO_READRDY)) { |
1788 | /* | |
1789 | * Apply delay or wait for ready/busy pin. Do this | |
1790 | * before the AUTOINCR check, so no problems arise if a | |
1791 | * chip which does auto increment is marked as | |
1792 | * NOAUTOINCR by the board driver. | |
19870da7 | 1793 | */ |
ace4dfee TG |
1794 | if (!chip->dev_ready) |
1795 | udelay(chip->chip_delay); | |
19870da7 TG |
1796 | else |
1797 | nand_wait_ready(mtd); | |
7314e9e7 | 1798 | } |
19870da7 | 1799 | |
7014568b | 1800 | readlen -= len; |
0d420f9d SZ |
1801 | if (!readlen) |
1802 | break; | |
1803 | ||
7314e9e7 TG |
1804 | /* Increment page address */ |
1805 | realpage++; | |
1806 | ||
1807 | page = realpage & chip->pagemask; | |
1808 | /* Check, if we cross a chip boundary */ | |
1809 | if (!page) { | |
1810 | chipnr++; | |
1811 | chip->select_chip(mtd, -1); | |
1812 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1813 | } |
7314e9e7 TG |
1814 | |
1815 | /* Check, if the chip supports auto page increment | |
1816 | * or if we have hit a block boundary. | |
1817 | */ | |
1818 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) | |
1819 | sndcmd = 1; | |
1da177e4 LT |
1820 | } |
1821 | ||
7014568b | 1822 | ops->oobretlen = ops->ooblen; |
1da177e4 LT |
1823 | return 0; |
1824 | } | |
1825 | ||
1826 | /** | |
8593fbc6 | 1827 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
1da177e4 | 1828 | * @mtd: MTD device structure |
1da177e4 | 1829 | * @from: offset to read from |
8593fbc6 | 1830 | * @ops: oob operation description structure |
1da177e4 | 1831 | * |
8593fbc6 | 1832 | * NAND read data and/or out-of-band data |
1da177e4 | 1833 | */ |
8593fbc6 TG |
1834 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1835 | struct mtd_oob_ops *ops) | |
1da177e4 | 1836 | { |
ace4dfee | 1837 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1838 | int ret = -ENOTSUPP; |
1839 | ||
1840 | ops->retlen = 0; | |
1da177e4 LT |
1841 | |
1842 | /* Do not allow reads past end of device */ | |
7014568b | 1843 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
20d8e248 | 1844 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read " |
1845 | "beyond end of device\n", __func__); | |
1da177e4 LT |
1846 | return -EINVAL; |
1847 | } | |
1848 | ||
ace4dfee | 1849 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1850 | |
8593fbc6 TG |
1851 | switch(ops->mode) { |
1852 | case MTD_OOB_PLACE: | |
1853 | case MTD_OOB_AUTO: | |
8593fbc6 | 1854 | case MTD_OOB_RAW: |
8593fbc6 | 1855 | break; |
1da177e4 | 1856 | |
8593fbc6 TG |
1857 | default: |
1858 | goto out; | |
1859 | } | |
1da177e4 | 1860 | |
8593fbc6 TG |
1861 | if (!ops->datbuf) |
1862 | ret = nand_do_read_oob(mtd, from, ops); | |
1863 | else | |
1864 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1865 | |
8593fbc6 TG |
1866 | out: |
1867 | nand_release_device(mtd); | |
1868 | return ret; | |
1869 | } | |
61b03bd7 | 1870 | |
1da177e4 | 1871 | |
8593fbc6 TG |
1872 | /** |
1873 | * nand_write_page_raw - [Intern] raw page write function | |
1874 | * @mtd: mtd info structure | |
1875 | * @chip: nand chip info structure | |
1876 | * @buf: data buffer | |
52ff49df DB |
1877 | * |
1878 | * Not for syndrome calculating ecc controllers, which use a special oob layout | |
8593fbc6 TG |
1879 | */ |
1880 | static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1881 | const uint8_t *buf) | |
1882 | { | |
1883 | chip->write_buf(mtd, buf, mtd->writesize); | |
1884 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1da177e4 LT |
1885 | } |
1886 | ||
52ff49df DB |
1887 | /** |
1888 | * nand_write_page_raw_syndrome - [Intern] raw page write function | |
1889 | * @mtd: mtd info structure | |
1890 | * @chip: nand chip info structure | |
1891 | * @buf: data buffer | |
1892 | * | |
1893 | * We need a special oob layout and handling even when ECC isn't checked. | |
1894 | */ | |
1895 | static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1896 | const uint8_t *buf) | |
1897 | { | |
1898 | int eccsize = chip->ecc.size; | |
1899 | int eccbytes = chip->ecc.bytes; | |
1900 | uint8_t *oob = chip->oob_poi; | |
1901 | int steps, size; | |
1902 | ||
1903 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1904 | chip->write_buf(mtd, buf, eccsize); | |
1905 | buf += eccsize; | |
1906 | ||
1907 | if (chip->ecc.prepad) { | |
1908 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1909 | oob += chip->ecc.prepad; | |
1910 | } | |
1911 | ||
1912 | chip->read_buf(mtd, oob, eccbytes); | |
1913 | oob += eccbytes; | |
1914 | ||
1915 | if (chip->ecc.postpad) { | |
1916 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1917 | oob += chip->ecc.postpad; | |
1918 | } | |
1919 | } | |
1920 | ||
1921 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1922 | if (size) | |
1923 | chip->write_buf(mtd, oob, size); | |
1924 | } | |
9223a456 | 1925 | /** |
d29ebdbe | 1926 | * nand_write_page_swecc - [REPLACABLE] software ecc based page write function |
f75e5097 TG |
1927 | * @mtd: mtd info structure |
1928 | * @chip: nand chip info structure | |
1929 | * @buf: data buffer | |
9223a456 | 1930 | */ |
f75e5097 TG |
1931 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1932 | const uint8_t *buf) | |
9223a456 | 1933 | { |
f75e5097 TG |
1934 | int i, eccsize = chip->ecc.size; |
1935 | int eccbytes = chip->ecc.bytes; | |
1936 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1937 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1938 | const uint8_t *p = buf; |
8b099a39 | 1939 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1940 | |
8593fbc6 TG |
1941 | /* Software ecc calculation */ |
1942 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1943 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1944 | |
8593fbc6 TG |
1945 | for (i = 0; i < chip->ecc.total; i++) |
1946 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1947 | |
90424de8 | 1948 | chip->ecc.write_page_raw(mtd, chip, buf); |
f75e5097 | 1949 | } |
9223a456 | 1950 | |
f75e5097 | 1951 | /** |
d29ebdbe | 1952 | * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function |
f75e5097 TG |
1953 | * @mtd: mtd info structure |
1954 | * @chip: nand chip info structure | |
1955 | * @buf: data buffer | |
1956 | */ | |
1957 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1958 | const uint8_t *buf) | |
1959 | { | |
1960 | int i, eccsize = chip->ecc.size; | |
1961 | int eccbytes = chip->ecc.bytes; | |
1962 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1963 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1964 | const uint8_t *p = buf; |
8b099a39 | 1965 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1966 | |
f75e5097 TG |
1967 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1968 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 1969 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 1970 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
1971 | } |
1972 | ||
f75e5097 TG |
1973 | for (i = 0; i < chip->ecc.total; i++) |
1974 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1975 | ||
1976 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
9223a456 TG |
1977 | } |
1978 | ||
61b03bd7 | 1979 | /** |
d29ebdbe | 1980 | * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write |
f75e5097 TG |
1981 | * @mtd: mtd info structure |
1982 | * @chip: nand chip info structure | |
1983 | * @buf: data buffer | |
1da177e4 | 1984 | * |
f75e5097 TG |
1985 | * The hw generator calculates the error syndrome automatically. Therefor |
1986 | * we need a special oob layout and handling. | |
1987 | */ | |
1988 | static void nand_write_page_syndrome(struct mtd_info *mtd, | |
1989 | struct nand_chip *chip, const uint8_t *buf) | |
1da177e4 | 1990 | { |
f75e5097 TG |
1991 | int i, eccsize = chip->ecc.size; |
1992 | int eccbytes = chip->ecc.bytes; | |
1993 | int eccsteps = chip->ecc.steps; | |
1994 | const uint8_t *p = buf; | |
1995 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 1996 | |
f75e5097 | 1997 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 1998 | |
f75e5097 TG |
1999 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2000 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2001 | |
f75e5097 TG |
2002 | if (chip->ecc.prepad) { |
2003 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2004 | oob += chip->ecc.prepad; | |
2005 | } | |
2006 | ||
2007 | chip->ecc.calculate(mtd, p, oob); | |
2008 | chip->write_buf(mtd, oob, eccbytes); | |
2009 | oob += eccbytes; | |
2010 | ||
2011 | if (chip->ecc.postpad) { | |
2012 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2013 | oob += chip->ecc.postpad; | |
1da177e4 | 2014 | } |
1da177e4 | 2015 | } |
f75e5097 TG |
2016 | |
2017 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2018 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2019 | if (i) |
2020 | chip->write_buf(mtd, oob, i); | |
2021 | } | |
2022 | ||
2023 | /** | |
956e944c | 2024 | * nand_write_page - [REPLACEABLE] write one page |
f75e5097 TG |
2025 | * @mtd: MTD device structure |
2026 | * @chip: NAND chip descriptor | |
2027 | * @buf: the data to write | |
2028 | * @page: page number to write | |
2029 | * @cached: cached programming | |
efbfe96c | 2030 | * @raw: use _raw version of write_page |
f75e5097 TG |
2031 | */ |
2032 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
956e944c | 2033 | const uint8_t *buf, int page, int cached, int raw) |
f75e5097 TG |
2034 | { |
2035 | int status; | |
2036 | ||
2037 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2038 | ||
956e944c DW |
2039 | if (unlikely(raw)) |
2040 | chip->ecc.write_page_raw(mtd, chip, buf); | |
2041 | else | |
2042 | chip->ecc.write_page(mtd, chip, buf); | |
f75e5097 TG |
2043 | |
2044 | /* | |
2045 | * Cached progamming disabled for now, Not sure if its worth the | |
2046 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
2047 | */ | |
2048 | cached = 0; | |
2049 | ||
2050 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
2051 | ||
2052 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2053 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2054 | /* |
2055 | * See if operation failed and additional status checks are | |
2056 | * available | |
2057 | */ | |
2058 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2059 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2060 | page); | |
2061 | ||
2062 | if (status & NAND_STATUS_FAIL) | |
2063 | return -EIO; | |
2064 | } else { | |
2065 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2066 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2067 | } |
2068 | ||
2069 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
2070 | /* Send command to read back the data */ | |
2071 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
2072 | ||
2073 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
2074 | return -EIO; | |
2075 | #endif | |
2076 | return 0; | |
1da177e4 LT |
2077 | } |
2078 | ||
8593fbc6 TG |
2079 | /** |
2080 | * nand_fill_oob - [Internal] Transfer client buffer to oob | |
2081 | * @chip: nand chip structure | |
2082 | * @oob: oob data buffer | |
2083 | * @ops: oob ops structure | |
2084 | */ | |
782ce79a ML |
2085 | static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len, |
2086 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2087 | { |
8593fbc6 TG |
2088 | switch(ops->mode) { |
2089 | ||
2090 | case MTD_OOB_PLACE: | |
2091 | case MTD_OOB_RAW: | |
2092 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); | |
2093 | return oob + len; | |
2094 | ||
2095 | case MTD_OOB_AUTO: { | |
2096 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
2097 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2098 | size_t bytes = 0; | |
8593fbc6 TG |
2099 | |
2100 | for(; free->length && len; free++, len -= bytes) { | |
7bc3312b TG |
2101 | /* Write request not from offset 0 ? */ |
2102 | if (unlikely(woffs)) { | |
2103 | if (woffs >= free->length) { | |
2104 | woffs -= free->length; | |
2105 | continue; | |
2106 | } | |
2107 | boffs = free->offset + woffs; | |
2108 | bytes = min_t(size_t, len, | |
2109 | (free->length - woffs)); | |
2110 | woffs = 0; | |
2111 | } else { | |
2112 | bytes = min_t(size_t, len, free->length); | |
2113 | boffs = free->offset; | |
2114 | } | |
8b0036ee | 2115 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2116 | oob += bytes; |
2117 | } | |
2118 | return oob; | |
2119 | } | |
2120 | default: | |
2121 | BUG(); | |
2122 | } | |
2123 | return NULL; | |
2124 | } | |
2125 | ||
29072b96 | 2126 | #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0 |
1da177e4 LT |
2127 | |
2128 | /** | |
8593fbc6 | 2129 | * nand_do_write_ops - [Internal] NAND write with ECC |
1da177e4 LT |
2130 | * @mtd: MTD device structure |
2131 | * @to: offset to write to | |
8593fbc6 | 2132 | * @ops: oob operations description structure |
1da177e4 LT |
2133 | * |
2134 | * NAND write with ECC | |
2135 | */ | |
8593fbc6 TG |
2136 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2137 | struct mtd_oob_ops *ops) | |
1da177e4 | 2138 | { |
29072b96 | 2139 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2140 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2141 | uint32_t writelen = ops->len; |
782ce79a ML |
2142 | |
2143 | uint32_t oobwritelen = ops->ooblen; | |
2144 | uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ? | |
2145 | mtd->oobavail : mtd->oobsize; | |
2146 | ||
8593fbc6 TG |
2147 | uint8_t *oob = ops->oobbuf; |
2148 | uint8_t *buf = ops->datbuf; | |
29072b96 | 2149 | int ret, subpage; |
1da177e4 | 2150 | |
8593fbc6 | 2151 | ops->retlen = 0; |
29072b96 TG |
2152 | if (!writelen) |
2153 | return 0; | |
1da177e4 | 2154 | |
61b03bd7 | 2155 | /* reject writes, which are not page aligned */ |
8593fbc6 | 2156 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
20d8e248 | 2157 | printk(KERN_NOTICE "%s: Attempt to write not " |
2158 | "page aligned data\n", __func__); | |
1da177e4 LT |
2159 | return -EINVAL; |
2160 | } | |
2161 | ||
29072b96 TG |
2162 | column = to & (mtd->writesize - 1); |
2163 | subpage = column || (writelen & (mtd->writesize - 1)); | |
2164 | ||
2165 | if (subpage && oob) | |
2166 | return -EINVAL; | |
1da177e4 | 2167 | |
6a930961 TG |
2168 | chipnr = (int)(to >> chip->chip_shift); |
2169 | chip->select_chip(mtd, chipnr); | |
2170 | ||
1da177e4 LT |
2171 | /* Check, if it is write protected */ |
2172 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2173 | return -EIO; |
1da177e4 | 2174 | |
f75e5097 TG |
2175 | realpage = (int)(to >> chip->page_shift); |
2176 | page = realpage & chip->pagemask; | |
2177 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2178 | ||
2179 | /* Invalidate the page cache, when we write to the cached page */ | |
2180 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2181 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2182 | chip->pagebuf = -1; |
61b03bd7 | 2183 | |
7dcdcbef DW |
2184 | /* If we're not given explicit OOB data, let it be 0xFF */ |
2185 | if (likely(!oob)) | |
2186 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
61b03bd7 | 2187 | |
782ce79a ML |
2188 | /* Don't allow multipage oob writes with offset */ |
2189 | if (ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) | |
2190 | return -EINVAL; | |
2191 | ||
f75e5097 | 2192 | while(1) { |
29072b96 | 2193 | int bytes = mtd->writesize; |
f75e5097 | 2194 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2195 | uint8_t *wbuf = buf; |
2196 | ||
2197 | /* Partial page write ? */ | |
2198 | if (unlikely(column || writelen < (mtd->writesize - 1))) { | |
2199 | cached = 0; | |
2200 | bytes = min_t(int, bytes - column, (int) writelen); | |
2201 | chip->pagebuf = -1; | |
2202 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2203 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2204 | wbuf = chip->buffers->databuf; | |
2205 | } | |
1da177e4 | 2206 | |
782ce79a ML |
2207 | if (unlikely(oob)) { |
2208 | size_t len = min(oobwritelen, oobmaxlen); | |
2209 | oob = nand_fill_oob(chip, oob, len, ops); | |
2210 | oobwritelen -= len; | |
2211 | } | |
8593fbc6 | 2212 | |
29072b96 | 2213 | ret = chip->write_page(mtd, chip, wbuf, page, cached, |
956e944c | 2214 | (ops->mode == MTD_OOB_RAW)); |
f75e5097 TG |
2215 | if (ret) |
2216 | break; | |
2217 | ||
2218 | writelen -= bytes; | |
2219 | if (!writelen) | |
2220 | break; | |
2221 | ||
29072b96 | 2222 | column = 0; |
f75e5097 TG |
2223 | buf += bytes; |
2224 | realpage++; | |
2225 | ||
2226 | page = realpage & chip->pagemask; | |
2227 | /* Check, if we cross a chip boundary */ | |
2228 | if (!page) { | |
2229 | chipnr++; | |
2230 | chip->select_chip(mtd, -1); | |
2231 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2232 | } |
2233 | } | |
8593fbc6 | 2234 | |
8593fbc6 | 2235 | ops->retlen = ops->len - writelen; |
7014568b VW |
2236 | if (unlikely(oob)) |
2237 | ops->oobretlen = ops->ooblen; | |
1da177e4 LT |
2238 | return ret; |
2239 | } | |
2240 | ||
2af7c653 SK |
2241 | /** |
2242 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
2243 | * @mtd: MTD device structure | |
2244 | * @to: offset to write to | |
2245 | * @len: number of bytes to write | |
2246 | * @retlen: pointer to variable to store the number of written bytes | |
2247 | * @buf: the data to write | |
2248 | * | |
2249 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2250 | * may for example be called by mtdoops when writing an oops while in panic. | |
2251 | */ | |
2252 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2253 | size_t *retlen, const uint8_t *buf) | |
2254 | { | |
2255 | struct nand_chip *chip = mtd->priv; | |
2256 | int ret; | |
2257 | ||
2258 | /* Do not allow reads past end of device */ | |
2259 | if ((to + len) > mtd->size) | |
2260 | return -EINVAL; | |
2261 | if (!len) | |
2262 | return 0; | |
2263 | ||
2264 | /* Wait for the device to get ready. */ | |
2265 | panic_nand_wait(mtd, chip, 400); | |
2266 | ||
2267 | /* Grab the device. */ | |
2268 | panic_nand_get_device(chip, mtd, FL_WRITING); | |
2269 | ||
2270 | chip->ops.len = len; | |
2271 | chip->ops.datbuf = (uint8_t *)buf; | |
2272 | chip->ops.oobbuf = NULL; | |
2273 | ||
2274 | ret = nand_do_write_ops(mtd, to, &chip->ops); | |
2275 | ||
2276 | *retlen = chip->ops.retlen; | |
2277 | return ret; | |
2278 | } | |
2279 | ||
f75e5097 | 2280 | /** |
8593fbc6 | 2281 | * nand_write - [MTD Interface] NAND write with ECC |
f75e5097 | 2282 | * @mtd: MTD device structure |
f75e5097 TG |
2283 | * @to: offset to write to |
2284 | * @len: number of bytes to write | |
8593fbc6 TG |
2285 | * @retlen: pointer to variable to store the number of written bytes |
2286 | * @buf: the data to write | |
f75e5097 | 2287 | * |
8593fbc6 | 2288 | * NAND write with ECC |
f75e5097 | 2289 | */ |
8593fbc6 TG |
2290 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2291 | size_t *retlen, const uint8_t *buf) | |
f75e5097 TG |
2292 | { |
2293 | struct nand_chip *chip = mtd->priv; | |
f75e5097 TG |
2294 | int ret; |
2295 | ||
8593fbc6 TG |
2296 | /* Do not allow reads past end of device */ |
2297 | if ((to + len) > mtd->size) | |
f75e5097 | 2298 | return -EINVAL; |
8593fbc6 TG |
2299 | if (!len) |
2300 | return 0; | |
f75e5097 | 2301 | |
7bc3312b | 2302 | nand_get_device(chip, mtd, FL_WRITING); |
f75e5097 | 2303 | |
8593fbc6 TG |
2304 | chip->ops.len = len; |
2305 | chip->ops.datbuf = (uint8_t *)buf; | |
2306 | chip->ops.oobbuf = NULL; | |
f75e5097 | 2307 | |
8593fbc6 | 2308 | ret = nand_do_write_ops(mtd, to, &chip->ops); |
f75e5097 | 2309 | |
7fd5aecc RP |
2310 | *retlen = chip->ops.retlen; |
2311 | ||
f75e5097 | 2312 | nand_release_device(mtd); |
8593fbc6 | 2313 | |
8593fbc6 | 2314 | return ret; |
f75e5097 | 2315 | } |
7314e9e7 | 2316 | |
1da177e4 | 2317 | /** |
8593fbc6 | 2318 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
1da177e4 LT |
2319 | * @mtd: MTD device structure |
2320 | * @to: offset to write to | |
8593fbc6 | 2321 | * @ops: oob operation description structure |
1da177e4 LT |
2322 | * |
2323 | * NAND write out-of-band | |
2324 | */ | |
8593fbc6 TG |
2325 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2326 | struct mtd_oob_ops *ops) | |
1da177e4 | 2327 | { |
03736155 | 2328 | int chipnr, page, status, len; |
ace4dfee | 2329 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2330 | |
20d8e248 | 2331 | DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n", |
2332 | __func__, (unsigned int)to, (int)ops->ooblen); | |
1da177e4 | 2333 | |
03736155 AH |
2334 | if (ops->mode == MTD_OOB_AUTO) |
2335 | len = chip->ecc.layout->oobavail; | |
2336 | else | |
2337 | len = mtd->oobsize; | |
2338 | ||
1da177e4 | 2339 | /* Do not allow write past end of page */ |
03736155 | 2340 | if ((ops->ooboffs + ops->ooblen) > len) { |
20d8e248 | 2341 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write " |
2342 | "past end of page\n", __func__); | |
1da177e4 LT |
2343 | return -EINVAL; |
2344 | } | |
2345 | ||
03736155 | 2346 | if (unlikely(ops->ooboffs >= len)) { |
20d8e248 | 2347 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start " |
2348 | "write outside oob\n", __func__); | |
03736155 AH |
2349 | return -EINVAL; |
2350 | } | |
2351 | ||
2352 | /* Do not allow reads past end of device */ | |
2353 | if (unlikely(to >= mtd->size || | |
2354 | ops->ooboffs + ops->ooblen > | |
2355 | ((mtd->size >> chip->page_shift) - | |
2356 | (to >> chip->page_shift)) * len)) { | |
20d8e248 | 2357 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " |
2358 | "end of device\n", __func__); | |
03736155 AH |
2359 | return -EINVAL; |
2360 | } | |
2361 | ||
7314e9e7 | 2362 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2363 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2364 | |
7314e9e7 TG |
2365 | /* Shift to get page */ |
2366 | page = (int)(to >> chip->page_shift); | |
2367 | ||
2368 | /* | |
2369 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2370 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2371 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2372 | * it in the doc2000 driver in August 1999. dwmw2. | |
2373 | */ | |
ace4dfee | 2374 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2375 | |
2376 | /* Check, if it is write protected */ | |
2377 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2378 | return -EROFS; |
61b03bd7 | 2379 | |
1da177e4 | 2380 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2381 | if (page == chip->pagebuf) |
2382 | chip->pagebuf = -1; | |
1da177e4 | 2383 | |
7bc3312b | 2384 | memset(chip->oob_poi, 0xff, mtd->oobsize); |
782ce79a | 2385 | nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops); |
7bc3312b TG |
2386 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); |
2387 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
1da177e4 | 2388 | |
7bc3312b TG |
2389 | if (status) |
2390 | return status; | |
1da177e4 | 2391 | |
7014568b | 2392 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2393 | |
7bc3312b | 2394 | return 0; |
8593fbc6 TG |
2395 | } |
2396 | ||
2397 | /** | |
2398 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
2399 | * @mtd: MTD device structure | |
844d3b42 | 2400 | * @to: offset to write to |
8593fbc6 TG |
2401 | * @ops: oob operation description structure |
2402 | */ | |
2403 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2404 | struct mtd_oob_ops *ops) | |
2405 | { | |
8593fbc6 TG |
2406 | struct nand_chip *chip = mtd->priv; |
2407 | int ret = -ENOTSUPP; | |
2408 | ||
2409 | ops->retlen = 0; | |
2410 | ||
2411 | /* Do not allow writes past end of device */ | |
7014568b | 2412 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
20d8e248 | 2413 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " |
2414 | "end of device\n", __func__); | |
8593fbc6 TG |
2415 | return -EINVAL; |
2416 | } | |
2417 | ||
7bc3312b | 2418 | nand_get_device(chip, mtd, FL_WRITING); |
8593fbc6 TG |
2419 | |
2420 | switch(ops->mode) { | |
2421 | case MTD_OOB_PLACE: | |
2422 | case MTD_OOB_AUTO: | |
8593fbc6 | 2423 | case MTD_OOB_RAW: |
8593fbc6 TG |
2424 | break; |
2425 | ||
2426 | default: | |
2427 | goto out; | |
2428 | } | |
2429 | ||
2430 | if (!ops->datbuf) | |
2431 | ret = nand_do_write_oob(mtd, to, ops); | |
2432 | else | |
2433 | ret = nand_do_write_ops(mtd, to, ops); | |
2434 | ||
e0c7d767 | 2435 | out: |
1da177e4 | 2436 | nand_release_device(mtd); |
1da177e4 LT |
2437 | return ret; |
2438 | } | |
2439 | ||
1da177e4 LT |
2440 | /** |
2441 | * single_erease_cmd - [GENERIC] NAND standard block erase command function | |
2442 | * @mtd: MTD device structure | |
2443 | * @page: the page address of the block which will be erased | |
2444 | * | |
2445 | * Standard erase command for NAND chips | |
2446 | */ | |
e0c7d767 | 2447 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2448 | { |
ace4dfee | 2449 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2450 | /* Send commands to erase a block */ |
ace4dfee TG |
2451 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2452 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2453 | } |
2454 | ||
2455 | /** | |
2456 | * multi_erease_cmd - [GENERIC] AND specific block erase command function | |
2457 | * @mtd: MTD device structure | |
2458 | * @page: the page address of the block which will be erased | |
2459 | * | |
2460 | * AND multi block erase command function | |
2461 | * Erase 4 consecutive blocks | |
2462 | */ | |
e0c7d767 | 2463 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2464 | { |
ace4dfee | 2465 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2466 | /* Send commands to erase a block */ |
ace4dfee TG |
2467 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2468 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2469 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2470 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
2471 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2472 | } |
2473 | ||
2474 | /** | |
2475 | * nand_erase - [MTD Interface] erase block(s) | |
2476 | * @mtd: MTD device structure | |
2477 | * @instr: erase instruction | |
2478 | * | |
2479 | * Erase one ore more blocks | |
2480 | */ | |
e0c7d767 | 2481 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2482 | { |
e0c7d767 | 2483 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2484 | } |
61b03bd7 | 2485 | |
30f464b7 | 2486 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 2487 | /** |
ace4dfee | 2488 | * nand_erase_nand - [Internal] erase block(s) |
1da177e4 LT |
2489 | * @mtd: MTD device structure |
2490 | * @instr: erase instruction | |
2491 | * @allowbbt: allow erasing the bbt area | |
2492 | * | |
2493 | * Erase one ore more blocks | |
2494 | */ | |
ace4dfee TG |
2495 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2496 | int allowbbt) | |
1da177e4 | 2497 | { |
69423d99 | 2498 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2499 | struct nand_chip *chip = mtd->priv; |
69423d99 | 2500 | loff_t rewrite_bbt[NAND_MAX_CHIPS]={0}; |
ace4dfee | 2501 | unsigned int bbt_masked_page = 0xffffffff; |
69423d99 | 2502 | loff_t len; |
1da177e4 | 2503 | |
20d8e248 | 2504 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", |
2505 | __func__, (unsigned long long)instr->addr, | |
2506 | (unsigned long long)instr->len); | |
1da177e4 | 2507 | |
6fe5a6ac | 2508 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2509 | return -EINVAL; |
1da177e4 | 2510 | |
bb0eb217 | 2511 | instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; |
1da177e4 LT |
2512 | |
2513 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2514 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
2515 | |
2516 | /* Shift to get first page */ | |
ace4dfee TG |
2517 | page = (int)(instr->addr >> chip->page_shift); |
2518 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2519 | |
2520 | /* Calculate pages in each block */ | |
ace4dfee | 2521 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2522 | |
2523 | /* Select the NAND device */ | |
ace4dfee | 2524 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2525 | |
1da177e4 LT |
2526 | /* Check, if it is write protected */ |
2527 | if (nand_check_wp(mtd)) { | |
20d8e248 | 2528 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", |
2529 | __func__); | |
1da177e4 LT |
2530 | instr->state = MTD_ERASE_FAILED; |
2531 | goto erase_exit; | |
2532 | } | |
2533 | ||
ace4dfee TG |
2534 | /* |
2535 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
2536 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
2537 | * can not be matched. This is also done when the bbt is actually | |
2538 | * erased to avoid recusrsive updates | |
2539 | */ | |
2540 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
2541 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 2542 | |
1da177e4 LT |
2543 | /* Loop through the pages */ |
2544 | len = instr->len; | |
2545 | ||
2546 | instr->state = MTD_ERASING; | |
2547 | ||
2548 | while (len) { | |
ace4dfee TG |
2549 | /* |
2550 | * heck if we have a bad block, we do not erase bad blocks ! | |
2551 | */ | |
2552 | if (nand_block_checkbad(mtd, ((loff_t) page) << | |
2553 | chip->page_shift, 0, allowbbt)) { | |
20d8e248 | 2554 | printk(KERN_WARNING "%s: attempt to erase a bad block " |
2555 | "at page 0x%08x\n", __func__, page); | |
1da177e4 LT |
2556 | instr->state = MTD_ERASE_FAILED; |
2557 | goto erase_exit; | |
2558 | } | |
61b03bd7 | 2559 | |
ace4dfee TG |
2560 | /* |
2561 | * Invalidate the page cache, if we erase the block which | |
2562 | * contains the current cached page | |
2563 | */ | |
2564 | if (page <= chip->pagebuf && chip->pagebuf < | |
2565 | (page + pages_per_block)) | |
2566 | chip->pagebuf = -1; | |
1da177e4 | 2567 | |
ace4dfee | 2568 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2569 | |
7bc3312b | 2570 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2571 | |
ace4dfee TG |
2572 | /* |
2573 | * See if operation failed and additional status checks are | |
2574 | * available | |
2575 | */ | |
2576 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2577 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2578 | status, page); | |
068e3c0a | 2579 | |
1da177e4 | 2580 | /* See if block erase succeeded */ |
a4ab4c5d | 2581 | if (status & NAND_STATUS_FAIL) { |
20d8e248 | 2582 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, " |
2583 | "page 0x%08x\n", __func__, page); | |
1da177e4 | 2584 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2585 | instr->fail_addr = |
2586 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2587 | goto erase_exit; |
2588 | } | |
30f464b7 | 2589 | |
ace4dfee TG |
2590 | /* |
2591 | * If BBT requires refresh, set the BBT rewrite flag to the | |
2592 | * page being erased | |
2593 | */ | |
2594 | if (bbt_masked_page != 0xffffffff && | |
2595 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
69423d99 AH |
2596 | rewrite_bbt[chipnr] = |
2597 | ((loff_t)page << chip->page_shift); | |
61b03bd7 | 2598 | |
1da177e4 | 2599 | /* Increment page address and decrement length */ |
ace4dfee | 2600 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
2601 | page += pages_per_block; |
2602 | ||
2603 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2604 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2605 | chipnr++; |
ace4dfee TG |
2606 | chip->select_chip(mtd, -1); |
2607 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 2608 | |
ace4dfee TG |
2609 | /* |
2610 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
2611 | * page mask to see if this BBT should be rewritten | |
2612 | */ | |
2613 | if (bbt_masked_page != 0xffffffff && | |
2614 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
2615 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
2616 | BBT_PAGE_MASK; | |
1da177e4 LT |
2617 | } |
2618 | } | |
2619 | instr->state = MTD_ERASE_DONE; | |
2620 | ||
e0c7d767 | 2621 | erase_exit: |
1da177e4 LT |
2622 | |
2623 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2624 | |
2625 | /* Deselect and wake up anyone waiting on the device */ | |
2626 | nand_release_device(mtd); | |
2627 | ||
49defc01 DW |
2628 | /* Do call back function */ |
2629 | if (!ret) | |
2630 | mtd_erase_callback(instr); | |
2631 | ||
ace4dfee TG |
2632 | /* |
2633 | * If BBT requires refresh and erase was successful, rewrite any | |
2634 | * selected bad block tables | |
2635 | */ | |
2636 | if (bbt_masked_page == 0xffffffff || ret) | |
2637 | return ret; | |
2638 | ||
2639 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2640 | if (!rewrite_bbt[chipnr]) | |
2641 | continue; | |
2642 | /* update the BBT for chip */ | |
20d8e248 | 2643 | DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt " |
2644 | "(%d:0x%0llx 0x%0x)\n", __func__, chipnr, | |
2645 | rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]); | |
ace4dfee | 2646 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); |
30f464b7 DM |
2647 | } |
2648 | ||
1da177e4 LT |
2649 | /* Return more or less happy */ |
2650 | return ret; | |
2651 | } | |
2652 | ||
2653 | /** | |
2654 | * nand_sync - [MTD Interface] sync | |
2655 | * @mtd: MTD device structure | |
2656 | * | |
2657 | * Sync is actually a wait for chip ready function | |
2658 | */ | |
e0c7d767 | 2659 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2660 | { |
ace4dfee | 2661 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2662 | |
20d8e248 | 2663 | DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__); |
1da177e4 LT |
2664 | |
2665 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2666 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 2667 | /* Release it and go back */ |
e0c7d767 | 2668 | nand_release_device(mtd); |
1da177e4 LT |
2669 | } |
2670 | ||
1da177e4 | 2671 | /** |
ace4dfee | 2672 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
1da177e4 | 2673 | * @mtd: MTD device structure |
844d3b42 | 2674 | * @offs: offset relative to mtd start |
1da177e4 | 2675 | */ |
ace4dfee | 2676 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 LT |
2677 | { |
2678 | /* Check for invalid offset */ | |
ace4dfee | 2679 | if (offs > mtd->size) |
1da177e4 | 2680 | return -EINVAL; |
61b03bd7 | 2681 | |
ace4dfee | 2682 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2683 | } |
2684 | ||
2685 | /** | |
ace4dfee | 2686 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
1da177e4 LT |
2687 | * @mtd: MTD device structure |
2688 | * @ofs: offset relative to mtd start | |
2689 | */ | |
e0c7d767 | 2690 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2691 | { |
ace4dfee | 2692 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2693 | int ret; |
2694 | ||
e0c7d767 DW |
2695 | if ((ret = nand_block_isbad(mtd, ofs))) { |
2696 | /* If it was bad already, return success and do nothing. */ | |
1da177e4 LT |
2697 | if (ret > 0) |
2698 | return 0; | |
e0c7d767 DW |
2699 | return ret; |
2700 | } | |
1da177e4 | 2701 | |
ace4dfee | 2702 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2703 | } |
2704 | ||
962034f4 VW |
2705 | /** |
2706 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
2707 | * @mtd: MTD device structure | |
2708 | */ | |
2709 | static int nand_suspend(struct mtd_info *mtd) | |
2710 | { | |
ace4dfee | 2711 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2712 | |
ace4dfee | 2713 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2714 | } |
2715 | ||
2716 | /** | |
2717 | * nand_resume - [MTD Interface] Resume the NAND flash | |
2718 | * @mtd: MTD device structure | |
2719 | */ | |
2720 | static void nand_resume(struct mtd_info *mtd) | |
2721 | { | |
ace4dfee | 2722 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2723 | |
ace4dfee | 2724 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2725 | nand_release_device(mtd); |
2726 | else | |
20d8e248 | 2727 | printk(KERN_ERR "%s called for a chip which is not " |
2728 | "in suspended state\n", __func__); | |
962034f4 VW |
2729 | } |
2730 | ||
7aa65bfd TG |
2731 | /* |
2732 | * Set default functions | |
2733 | */ | |
ace4dfee | 2734 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2735 | { |
1da177e4 | 2736 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2737 | if (!chip->chip_delay) |
2738 | chip->chip_delay = 20; | |
1da177e4 LT |
2739 | |
2740 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2741 | if (chip->cmdfunc == NULL) |
2742 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2743 | |
2744 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2745 | if (chip->waitfunc == NULL) |
2746 | chip->waitfunc = nand_wait; | |
2747 | ||
2748 | if (!chip->select_chip) | |
2749 | chip->select_chip = nand_select_chip; | |
2750 | if (!chip->read_byte) | |
2751 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2752 | if (!chip->read_word) | |
2753 | chip->read_word = nand_read_word; | |
2754 | if (!chip->block_bad) | |
2755 | chip->block_bad = nand_block_bad; | |
2756 | if (!chip->block_markbad) | |
2757 | chip->block_markbad = nand_default_block_markbad; | |
2758 | if (!chip->write_buf) | |
2759 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2760 | if (!chip->read_buf) | |
2761 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
2762 | if (!chip->verify_buf) | |
2763 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; | |
2764 | if (!chip->scan_bbt) | |
2765 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2766 | |
2767 | if (!chip->controller) { | |
2768 | chip->controller = &chip->hwcontrol; | |
2769 | spin_lock_init(&chip->controller->lock); | |
2770 | init_waitqueue_head(&chip->controller->wq); | |
2771 | } | |
2772 | ||
7aa65bfd TG |
2773 | } |
2774 | ||
2775 | /* | |
ace4dfee | 2776 | * Get the flash and manufacturer id and lookup if the type is supported |
7aa65bfd TG |
2777 | */ |
2778 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 2779 | struct nand_chip *chip, |
5e81e88a DW |
2780 | int busw, int *maf_id, |
2781 | struct nand_flash_dev *type) | |
7aa65bfd | 2782 | { |
426c457a KC |
2783 | int i, dev_id, maf_idx; |
2784 | u8 id_data[8]; | |
1da177e4 LT |
2785 | |
2786 | /* Select the device */ | |
ace4dfee | 2787 | chip->select_chip(mtd, 0); |
1da177e4 | 2788 | |
ef89a880 KB |
2789 | /* |
2790 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
2791 | * after power-up | |
2792 | */ | |
2793 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
2794 | ||
1da177e4 | 2795 | /* Send the command for reading device ID */ |
ace4dfee | 2796 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
2797 | |
2798 | /* Read manufacturer and device IDs */ | |
ace4dfee TG |
2799 | *maf_id = chip->read_byte(mtd); |
2800 | dev_id = chip->read_byte(mtd); | |
1da177e4 | 2801 | |
ed8165c7 BD |
2802 | /* Try again to make sure, as some systems the bus-hold or other |
2803 | * interface concerns can cause random data which looks like a | |
2804 | * possibly credible NAND flash to appear. If the two results do | |
2805 | * not match, ignore the device completely. | |
2806 | */ | |
2807 | ||
2808 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
2809 | ||
426c457a | 2810 | /* Read entire ID string */ |
ed8165c7 | 2811 | |
426c457a KC |
2812 | for (i = 0; i < 8; i++) |
2813 | id_data[i] = chip->read_byte(mtd); | |
ed8165c7 | 2814 | |
426c457a | 2815 | if (id_data[0] != *maf_id || id_data[1] != dev_id) { |
ed8165c7 BD |
2816 | printk(KERN_INFO "%s: second ID read did not match " |
2817 | "%02x,%02x against %02x,%02x\n", __func__, | |
426c457a | 2818 | *maf_id, dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
2819 | return ERR_PTR(-ENODEV); |
2820 | } | |
2821 | ||
7aa65bfd | 2822 | if (!type) |
5e81e88a DW |
2823 | type = nand_flash_ids; |
2824 | ||
2825 | for (; type->name != NULL; type++) | |
2826 | if (dev_id == type->id) | |
2827 | break; | |
2828 | ||
2829 | if (!type->name) | |
7aa65bfd TG |
2830 | return ERR_PTR(-ENODEV); |
2831 | ||
ba0251fe TG |
2832 | if (!mtd->name) |
2833 | mtd->name = type->name; | |
2834 | ||
69423d99 | 2835 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd TG |
2836 | |
2837 | /* Newer devices have all the information in additional id bytes */ | |
ba0251fe | 2838 | if (!type->pagesize) { |
7aa65bfd | 2839 | int extid; |
29072b96 | 2840 | /* The 3rd id byte holds MLC / multichip data */ |
426c457a | 2841 | chip->cellinfo = id_data[2]; |
7aa65bfd | 2842 | /* The 4th id byte is the important one */ |
426c457a | 2843 | extid = id_data[3]; |
61b03bd7 | 2844 | |
426c457a KC |
2845 | /* |
2846 | * Field definitions are in the following datasheets: | |
2847 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
2848 | * New style (6 byte ID): Samsung K9GAG08U0D (p.40) | |
2849 | * | |
2850 | * Check for wraparound + Samsung ID + nonzero 6th byte | |
2851 | * to decide what to do. | |
2852 | */ | |
2853 | if (id_data[0] == id_data[6] && id_data[1] == id_data[7] && | |
2854 | id_data[0] == NAND_MFR_SAMSUNG && | |
2855 | id_data[5] != 0x00) { | |
2856 | /* Calc pagesize */ | |
2857 | mtd->writesize = 2048 << (extid & 0x03); | |
2858 | extid >>= 2; | |
2859 | /* Calc oobsize */ | |
2860 | mtd->oobsize = (extid & 0x03) == 0x01 ? 128 : 218; | |
2861 | extid >>= 2; | |
2862 | /* Calc blocksize */ | |
2863 | mtd->erasesize = (128 * 1024) << | |
2864 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
2865 | busw = 0; | |
2866 | } else { | |
2867 | /* Calc pagesize */ | |
2868 | mtd->writesize = 1024 << (extid & 0x03); | |
2869 | extid >>= 2; | |
2870 | /* Calc oobsize */ | |
2871 | mtd->oobsize = (8 << (extid & 0x01)) * | |
2872 | (mtd->writesize >> 9); | |
2873 | extid >>= 2; | |
2874 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
2875 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
2876 | extid >>= 2; | |
2877 | /* Get buswidth information */ | |
2878 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
2879 | } | |
7aa65bfd TG |
2880 | } else { |
2881 | /* | |
ace4dfee | 2882 | * Old devices have chip data hardcoded in the device id table |
7aa65bfd | 2883 | */ |
ba0251fe TG |
2884 | mtd->erasesize = type->erasesize; |
2885 | mtd->writesize = type->pagesize; | |
4cbb9b80 | 2886 | mtd->oobsize = mtd->writesize / 32; |
ba0251fe | 2887 | busw = type->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2888 | } |
1da177e4 | 2889 | |
7aa65bfd | 2890 | /* Try to identify manufacturer */ |
9a909867 | 2891 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
2892 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
2893 | break; | |
2894 | } | |
0ea4a755 | 2895 | |
7aa65bfd TG |
2896 | /* |
2897 | * Check, if buswidth is correct. Hardware drivers should set | |
ace4dfee | 2898 | * chip correct ! |
7aa65bfd | 2899 | */ |
ace4dfee | 2900 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
7aa65bfd TG |
2901 | printk(KERN_INFO "NAND device: Manufacturer ID:" |
2902 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, | |
2903 | dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
2904 | printk(KERN_WARNING "NAND bus width %d instead %d bit\n", | |
ace4dfee | 2905 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
7aa65bfd TG |
2906 | busw ? 16 : 8); |
2907 | return ERR_PTR(-EINVAL); | |
2908 | } | |
61b03bd7 | 2909 | |
7aa65bfd | 2910 | /* Calculate the address shift from the page size */ |
ace4dfee | 2911 | chip->page_shift = ffs(mtd->writesize) - 1; |
7aa65bfd | 2912 | /* Convert chipsize to number of pages per chip -1. */ |
ace4dfee | 2913 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 2914 | |
ace4dfee | 2915 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 2916 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
2917 | if (chip->chipsize & 0xffffffff) |
2918 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
2919 | else | |
2920 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1; | |
1da177e4 | 2921 | |
7aa65bfd | 2922 | /* Set the bad block position */ |
c7b28e25 BN |
2923 | if (!(busw & NAND_BUSWIDTH_16) && (*maf_id == NAND_MFR_STMICRO || |
2924 | (*maf_id == NAND_MFR_SAMSUNG && | |
2925 | mtd->writesize == 512) || | |
2926 | *maf_id == NAND_MFR_AMD)) | |
2927 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
2928 | else | |
2929 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
2930 | ||
61b03bd7 | 2931 | |
7aa65bfd | 2932 | /* Get chip options, preserve non chip based options */ |
ace4dfee | 2933 | chip->options &= ~NAND_CHIPOPTIONS_MSK; |
ba0251fe | 2934 | chip->options |= type->options & NAND_CHIPOPTIONS_MSK; |
7aa65bfd TG |
2935 | |
2936 | /* | |
ace4dfee | 2937 | * Set chip as a default. Board drivers can override it, if necessary |
7aa65bfd | 2938 | */ |
ace4dfee | 2939 | chip->options |= NAND_NO_AUTOINCR; |
7aa65bfd | 2940 | |
ace4dfee | 2941 | /* Check if chip is a not a samsung device. Do not clear the |
7aa65bfd TG |
2942 | * options for chips which are not having an extended id. |
2943 | */ | |
ba0251fe | 2944 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) |
ace4dfee | 2945 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; |
7aa65bfd | 2946 | |
b60b08b0 KC |
2947 | /* |
2948 | * Bad block marker is stored in the last page of each block | |
c7b28e25 BN |
2949 | * on Samsung and Hynix MLC devices; stored in first two pages |
2950 | * of each block on Micron devices with 2KiB pages and on | |
2951 | * SLC Samsung, Hynix, and AMD/Spansion. All others scan only | |
2952 | * the first page. | |
b60b08b0 KC |
2953 | */ |
2954 | if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && | |
2955 | (*maf_id == NAND_MFR_SAMSUNG || | |
2956 | *maf_id == NAND_MFR_HYNIX)) | |
30fe8115 | 2957 | chip->options |= NAND_BBT_SCANLASTPAGE; |
c7b28e25 BN |
2958 | else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && |
2959 | (*maf_id == NAND_MFR_SAMSUNG || | |
2960 | *maf_id == NAND_MFR_HYNIX || | |
2961 | *maf_id == NAND_MFR_AMD)) || | |
2962 | (mtd->writesize == 2048 && | |
2963 | *maf_id == NAND_MFR_MICRON)) | |
2964 | chip->options |= NAND_BBT_SCAN2NDPAGE; | |
2965 | ||
58373ff0 BN |
2966 | /* |
2967 | * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6 | |
2968 | */ | |
2969 | if (!(busw & NAND_BUSWIDTH_16) && | |
2970 | *maf_id == NAND_MFR_STMICRO && | |
2971 | mtd->writesize == 2048) { | |
2972 | chip->options |= NAND_BBT_SCANBYTE1AND6; | |
2973 | chip->badblockpos = 0; | |
2974 | } | |
b60b08b0 | 2975 | |
7aa65bfd | 2976 | /* Check for AND chips with 4 page planes */ |
ace4dfee TG |
2977 | if (chip->options & NAND_4PAGE_ARRAY) |
2978 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 2979 | else |
ace4dfee | 2980 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd TG |
2981 | |
2982 | /* Do not replace user supplied command function ! */ | |
ace4dfee TG |
2983 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
2984 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd TG |
2985 | |
2986 | printk(KERN_INFO "NAND device: Manufacturer ID:" | |
2987 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, | |
2988 | nand_manuf_ids[maf_idx].name, type->name); | |
2989 | ||
2990 | return type; | |
2991 | } | |
2992 | ||
7aa65bfd | 2993 | /** |
3b85c321 DW |
2994 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
2995 | * @mtd: MTD device structure | |
2996 | * @maxchips: Number of chips to scan for | |
5e81e88a | 2997 | * @table: Alternative NAND ID table |
7aa65bfd | 2998 | * |
3b85c321 DW |
2999 | * This is the first phase of the normal nand_scan() function. It |
3000 | * reads the flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3001 | * |
3b85c321 | 3002 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3003 | */ |
5e81e88a DW |
3004 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3005 | struct nand_flash_dev *table) | |
7aa65bfd TG |
3006 | { |
3007 | int i, busw, nand_maf_id; | |
ace4dfee | 3008 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3009 | struct nand_flash_dev *type; |
3010 | ||
7aa65bfd | 3011 | /* Get buswidth to select the correct functions */ |
ace4dfee | 3012 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 3013 | /* Set the default functions */ |
ace4dfee | 3014 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
3015 | |
3016 | /* Read the flash type */ | |
5e81e88a | 3017 | type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, table); |
7aa65bfd TG |
3018 | |
3019 | if (IS_ERR(type)) { | |
b1c6e6db BD |
3020 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
3021 | printk(KERN_WARNING "No NAND device found.\n"); | |
ace4dfee | 3022 | chip->select_chip(mtd, -1); |
7aa65bfd | 3023 | return PTR_ERR(type); |
1da177e4 LT |
3024 | } |
3025 | ||
7aa65bfd | 3026 | /* Check for a chip array */ |
e0c7d767 | 3027 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3028 | chip->select_chip(mtd, i); |
ef89a880 KB |
3029 | /* See comment in nand_get_flash_type for reset */ |
3030 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3031 | /* Send the command for reading device ID */ |
ace4dfee | 3032 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3033 | /* Read manufacturer and device IDs */ |
ace4dfee TG |
3034 | if (nand_maf_id != chip->read_byte(mtd) || |
3035 | type->id != chip->read_byte(mtd)) | |
1da177e4 LT |
3036 | break; |
3037 | } | |
3038 | if (i > 1) | |
3039 | printk(KERN_INFO "%d NAND chips detected\n", i); | |
61b03bd7 | 3040 | |
1da177e4 | 3041 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3042 | chip->numchips = i; |
3043 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3044 | |
3b85c321 DW |
3045 | return 0; |
3046 | } | |
3047 | ||
3048 | ||
3049 | /** | |
3050 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
3051 | * @mtd: MTD device structure | |
3b85c321 DW |
3052 | * |
3053 | * This is the second phase of the normal nand_scan() function. It | |
3054 | * fills out all the uninitialized function pointers with the defaults | |
3055 | * and scans for a bad block table if appropriate. | |
3056 | */ | |
3057 | int nand_scan_tail(struct mtd_info *mtd) | |
3058 | { | |
3059 | int i; | |
3060 | struct nand_chip *chip = mtd->priv; | |
3061 | ||
4bf63fcb DW |
3062 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3063 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
3064 | if (!chip->buffers) | |
3065 | return -ENOMEM; | |
3066 | ||
7dcdcbef | 3067 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3068 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3069 | |
7aa65bfd TG |
3070 | /* |
3071 | * If no default placement scheme is given, select an appropriate one | |
3072 | */ | |
5bd34c09 | 3073 | if (!chip->ecc.layout) { |
61b03bd7 | 3074 | switch (mtd->oobsize) { |
1da177e4 | 3075 | case 8: |
5bd34c09 | 3076 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
3077 | break; |
3078 | case 16: | |
5bd34c09 | 3079 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
3080 | break; |
3081 | case 64: | |
5bd34c09 | 3082 | chip->ecc.layout = &nand_oob_64; |
1da177e4 | 3083 | break; |
81ec5364 TG |
3084 | case 128: |
3085 | chip->ecc.layout = &nand_oob_128; | |
3086 | break; | |
1da177e4 | 3087 | default: |
7aa65bfd TG |
3088 | printk(KERN_WARNING "No oob scheme defined for " |
3089 | "oobsize %d\n", mtd->oobsize); | |
1da177e4 LT |
3090 | BUG(); |
3091 | } | |
3092 | } | |
61b03bd7 | 3093 | |
956e944c DW |
3094 | if (!chip->write_page) |
3095 | chip->write_page = nand_write_page; | |
3096 | ||
61b03bd7 | 3097 | /* |
7aa65bfd TG |
3098 | * check ECC mode, default to software if 3byte/512byte hardware ECC is |
3099 | * selected and we have 256 byte pagesize fallback to software ECC | |
e0c7d767 | 3100 | */ |
956e944c | 3101 | |
ace4dfee | 3102 | switch (chip->ecc.mode) { |
6e0cb135 SN |
3103 | case NAND_ECC_HW_OOB_FIRST: |
3104 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
3105 | if (!chip->ecc.calculate || !chip->ecc.correct || | |
3106 | !chip->ecc.hwctl) { | |
3107 | printk(KERN_WARNING "No ECC functions supplied; " | |
3108 | "Hardware ECC not possible\n"); | |
3109 | BUG(); | |
3110 | } | |
3111 | if (!chip->ecc.read_page) | |
3112 | chip->ecc.read_page = nand_read_page_hwecc_oob_first; | |
3113 | ||
6dfc6d25 | 3114 | case NAND_ECC_HW: |
f5bbdacc TG |
3115 | /* Use standard hwecc read page function ? */ |
3116 | if (!chip->ecc.read_page) | |
3117 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
3118 | if (!chip->ecc.write_page) |
3119 | chip->ecc.write_page = nand_write_page_hwecc; | |
52ff49df DB |
3120 | if (!chip->ecc.read_page_raw) |
3121 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3122 | if (!chip->ecc.write_page_raw) | |
3123 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3124 | if (!chip->ecc.read_oob) |
3125 | chip->ecc.read_oob = nand_read_oob_std; | |
3126 | if (!chip->ecc.write_oob) | |
3127 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 3128 | |
6dfc6d25 | 3129 | case NAND_ECC_HW_SYNDROME: |
78b65179 SW |
3130 | if ((!chip->ecc.calculate || !chip->ecc.correct || |
3131 | !chip->ecc.hwctl) && | |
3132 | (!chip->ecc.read_page || | |
1c45f604 | 3133 | chip->ecc.read_page == nand_read_page_hwecc || |
78b65179 | 3134 | !chip->ecc.write_page || |
1c45f604 | 3135 | chip->ecc.write_page == nand_write_page_hwecc)) { |
6e0cb135 | 3136 | printk(KERN_WARNING "No ECC functions supplied; " |
6dfc6d25 TG |
3137 | "Hardware ECC not possible\n"); |
3138 | BUG(); | |
3139 | } | |
f75e5097 | 3140 | /* Use standard syndrome read/write page function ? */ |
f5bbdacc TG |
3141 | if (!chip->ecc.read_page) |
3142 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
3143 | if (!chip->ecc.write_page) |
3144 | chip->ecc.write_page = nand_write_page_syndrome; | |
52ff49df DB |
3145 | if (!chip->ecc.read_page_raw) |
3146 | chip->ecc.read_page_raw = nand_read_page_raw_syndrome; | |
3147 | if (!chip->ecc.write_page_raw) | |
3148 | chip->ecc.write_page_raw = nand_write_page_raw_syndrome; | |
7bc3312b TG |
3149 | if (!chip->ecc.read_oob) |
3150 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
3151 | if (!chip->ecc.write_oob) | |
3152 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 3153 | |
ace4dfee | 3154 | if (mtd->writesize >= chip->ecc.size) |
6dfc6d25 TG |
3155 | break; |
3156 | printk(KERN_WARNING "%d byte HW ECC not possible on " | |
3157 | "%d byte page size, fallback to SW ECC\n", | |
ace4dfee TG |
3158 | chip->ecc.size, mtd->writesize); |
3159 | chip->ecc.mode = NAND_ECC_SOFT; | |
61b03bd7 | 3160 | |
6dfc6d25 | 3161 | case NAND_ECC_SOFT: |
ace4dfee TG |
3162 | chip->ecc.calculate = nand_calculate_ecc; |
3163 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 3164 | chip->ecc.read_page = nand_read_page_swecc; |
3d459559 | 3165 | chip->ecc.read_subpage = nand_read_subpage; |
f75e5097 | 3166 | chip->ecc.write_page = nand_write_page_swecc; |
52ff49df DB |
3167 | chip->ecc.read_page_raw = nand_read_page_raw; |
3168 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3169 | chip->ecc.read_oob = nand_read_oob_std; |
3170 | chip->ecc.write_oob = nand_write_oob_std; | |
9a73290d SV |
3171 | if (!chip->ecc.size) |
3172 | chip->ecc.size = 256; | |
ace4dfee | 3173 | chip->ecc.bytes = 3; |
1da177e4 | 3174 | break; |
61b03bd7 TG |
3175 | |
3176 | case NAND_ECC_NONE: | |
7aa65bfd TG |
3177 | printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " |
3178 | "This is not recommended !!\n"); | |
8593fbc6 TG |
3179 | chip->ecc.read_page = nand_read_page_raw; |
3180 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b | 3181 | chip->ecc.read_oob = nand_read_oob_std; |
52ff49df DB |
3182 | chip->ecc.read_page_raw = nand_read_page_raw; |
3183 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b | 3184 | chip->ecc.write_oob = nand_write_oob_std; |
ace4dfee TG |
3185 | chip->ecc.size = mtd->writesize; |
3186 | chip->ecc.bytes = 0; | |
1da177e4 | 3187 | break; |
956e944c | 3188 | |
1da177e4 | 3189 | default: |
7aa65bfd | 3190 | printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", |
ace4dfee | 3191 | chip->ecc.mode); |
61b03bd7 | 3192 | BUG(); |
1da177e4 | 3193 | } |
61b03bd7 | 3194 | |
5bd34c09 TG |
3195 | /* |
3196 | * The number of bytes available for a client to place data into | |
3197 | * the out of band area | |
3198 | */ | |
3199 | chip->ecc.layout->oobavail = 0; | |
81d19b04 DB |
3200 | for (i = 0; chip->ecc.layout->oobfree[i].length |
3201 | && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) | |
5bd34c09 TG |
3202 | chip->ecc.layout->oobavail += |
3203 | chip->ecc.layout->oobfree[i].length; | |
1f92267c | 3204 | mtd->oobavail = chip->ecc.layout->oobavail; |
5bd34c09 | 3205 | |
7aa65bfd TG |
3206 | /* |
3207 | * Set the number of read / write steps for one page depending on ECC | |
3208 | * mode | |
3209 | */ | |
ace4dfee TG |
3210 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
3211 | if(chip->ecc.steps * chip->ecc.size != mtd->writesize) { | |
6dfc6d25 TG |
3212 | printk(KERN_WARNING "Invalid ecc parameters\n"); |
3213 | BUG(); | |
1da177e4 | 3214 | } |
f5bbdacc | 3215 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 3216 | |
29072b96 TG |
3217 | /* |
3218 | * Allow subpage writes up to ecc.steps. Not possible for MLC | |
3219 | * FLASH. | |
3220 | */ | |
3221 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
3222 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
3223 | switch(chip->ecc.steps) { | |
3224 | case 2: | |
3225 | mtd->subpage_sft = 1; | |
3226 | break; | |
3227 | case 4: | |
3228 | case 8: | |
81ec5364 | 3229 | case 16: |
29072b96 TG |
3230 | mtd->subpage_sft = 2; |
3231 | break; | |
3232 | } | |
3233 | } | |
3234 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
3235 | ||
04bbd0ea | 3236 | /* Initialize state */ |
ace4dfee | 3237 | chip->state = FL_READY; |
1da177e4 LT |
3238 | |
3239 | /* De-select the device */ | |
ace4dfee | 3240 | chip->select_chip(mtd, -1); |
1da177e4 LT |
3241 | |
3242 | /* Invalidate the pagebuffer reference */ | |
ace4dfee | 3243 | chip->pagebuf = -1; |
1da177e4 LT |
3244 | |
3245 | /* Fill in remaining MTD driver data */ | |
3246 | mtd->type = MTD_NANDFLASH; | |
93edbad6 ML |
3247 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
3248 | MTD_CAP_NANDFLASH; | |
1da177e4 LT |
3249 | mtd->erase = nand_erase; |
3250 | mtd->point = NULL; | |
3251 | mtd->unpoint = NULL; | |
3252 | mtd->read = nand_read; | |
3253 | mtd->write = nand_write; | |
2af7c653 | 3254 | mtd->panic_write = panic_nand_write; |
1da177e4 LT |
3255 | mtd->read_oob = nand_read_oob; |
3256 | mtd->write_oob = nand_write_oob; | |
1da177e4 LT |
3257 | mtd->sync = nand_sync; |
3258 | mtd->lock = NULL; | |
3259 | mtd->unlock = NULL; | |
962034f4 VW |
3260 | mtd->suspend = nand_suspend; |
3261 | mtd->resume = nand_resume; | |
1da177e4 LT |
3262 | mtd->block_isbad = nand_block_isbad; |
3263 | mtd->block_markbad = nand_block_markbad; | |
3264 | ||
5bd34c09 TG |
3265 | /* propagate ecc.layout to mtd_info */ |
3266 | mtd->ecclayout = chip->ecc.layout; | |
1da177e4 | 3267 | |
0040bf38 | 3268 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 3269 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 3270 | return 0; |
1da177e4 LT |
3271 | |
3272 | /* Build bad block table */ | |
ace4dfee | 3273 | return chip->scan_bbt(mtd); |
1da177e4 LT |
3274 | } |
3275 | ||
a6e6abd5 | 3276 | /* is_module_text_address() isn't exported, and it's mostly a pointless |
3b85c321 DW |
3277 | test if this is a module _anyway_ -- they'd have to try _really_ hard |
3278 | to call us from in-kernel code if the core NAND support is modular. */ | |
3279 | #ifdef MODULE | |
3280 | #define caller_is_module() (1) | |
3281 | #else | |
3282 | #define caller_is_module() \ | |
a6e6abd5 | 3283 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
3284 | #endif |
3285 | ||
3286 | /** | |
3287 | * nand_scan - [NAND Interface] Scan for the NAND device | |
3288 | * @mtd: MTD device structure | |
3289 | * @maxchips: Number of chips to scan for | |
3290 | * | |
3291 | * This fills out all the uninitialized function pointers | |
3292 | * with the defaults. | |
3293 | * The flash ID is read and the mtd/chip structures are | |
3294 | * filled with the appropriate values. | |
3295 | * The mtd->owner field must be set to the module of the caller | |
3296 | * | |
3297 | */ | |
3298 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
3299 | { | |
3300 | int ret; | |
3301 | ||
3302 | /* Many callers got this wrong, so check for it for a while... */ | |
3303 | if (!mtd->owner && caller_is_module()) { | |
20d8e248 | 3304 | printk(KERN_CRIT "%s called with NULL mtd->owner!\n", |
3305 | __func__); | |
3b85c321 DW |
3306 | BUG(); |
3307 | } | |
3308 | ||
5e81e88a | 3309 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
3310 | if (!ret) |
3311 | ret = nand_scan_tail(mtd); | |
3312 | return ret; | |
3313 | } | |
3314 | ||
1da177e4 | 3315 | /** |
61b03bd7 | 3316 | * nand_release - [NAND Interface] Free resources held by the NAND device |
1da177e4 LT |
3317 | * @mtd: MTD device structure |
3318 | */ | |
e0c7d767 | 3319 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 3320 | { |
ace4dfee | 3321 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
3322 | |
3323 | #ifdef CONFIG_MTD_PARTITIONS | |
3324 | /* Deregister partitions */ | |
e0c7d767 | 3325 | del_mtd_partitions(mtd); |
1da177e4 LT |
3326 | #endif |
3327 | /* Deregister the device */ | |
e0c7d767 | 3328 | del_mtd_device(mtd); |
1da177e4 | 3329 | |
fa671646 | 3330 | /* Free bad block table memory */ |
ace4dfee | 3331 | kfree(chip->bbt); |
4bf63fcb DW |
3332 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3333 | kfree(chip->buffers); | |
58373ff0 BN |
3334 | |
3335 | /* Free bad block descriptor memory */ | |
3336 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
3337 | & NAND_BBT_DYNAMICSTRUCT) | |
3338 | kfree(chip->badblock_pattern); | |
1da177e4 LT |
3339 | } |
3340 | ||
7d70f334 VS |
3341 | EXPORT_SYMBOL_GPL(nand_lock); |
3342 | EXPORT_SYMBOL_GPL(nand_unlock); | |
e0c7d767 | 3343 | EXPORT_SYMBOL_GPL(nand_scan); |
3b85c321 DW |
3344 | EXPORT_SYMBOL_GPL(nand_scan_ident); |
3345 | EXPORT_SYMBOL_GPL(nand_scan_tail); | |
e0c7d767 | 3346 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
3347 | |
3348 | static int __init nand_base_init(void) | |
3349 | { | |
3350 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
3351 | return 0; | |
3352 | } | |
3353 | ||
3354 | static void __exit nand_base_exit(void) | |
3355 | { | |
3356 | led_trigger_unregister_simple(nand_led_trigger); | |
3357 | } | |
3358 | ||
3359 | module_init(nand_base_init); | |
3360 | module_exit(nand_base_exit); | |
3361 | ||
e0c7d767 DW |
3362 | MODULE_LICENSE("GPL"); |
3363 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); | |
3364 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |