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mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
45#include <linux/mtd/compatmac.h>
46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
1da177e4
LT		 49#include <asm/io.h>
50
51#ifdef CONFIG_MTD_PARTITIONS
52#include <linux/mtd/partitions.h>
53#endif
54
55/* Define default oob placement schemes for large and small page devices */
5bd34c09 56static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 57 .eccbytes = 3,
58 .eccpos = {0, 1, 2},
5bd34c09
TG		 59 .oobfree = {
60 {.offset = 3,
61 .length = 2},
62 {.offset = 6,
63 .length = 2}}
1da177e4
LT		 64};
65
5bd34c09 66static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 67 .eccbytes = 6,
68 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 69 .oobfree = {
70 {.offset = 8,
71 . length = 8}}
1da177e4
LT		 72};
73
5bd34c09 74static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 75 .eccbytes = 24,
76 .eccpos = {
e0c7d767
DW		 77 40, 41, 42, 43, 44, 45, 46, 47,
78 48, 49, 50, 51, 52, 53, 54, 55,
79 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 80 .oobfree = {
81 {.offset = 2,
82 .length = 38}}
1da177e4
LT		 83};
84
81ec5364
TG		 85static struct nand_ecclayout nand_oob_128 = {
86 .eccbytes = 48,
87 .eccpos = {
88 80, 81, 82, 83, 84, 85, 86, 87,
89 88, 89, 90, 91, 92, 93, 94, 95,
90 96, 97, 98, 99, 100, 101, 102, 103,
91 104, 105, 106, 107, 108, 109, 110, 111,
92 112, 113, 114, 115, 116, 117, 118, 119,
93 120, 121, 122, 123, 124, 125, 126, 127},
94 .oobfree = {
95 {.offset = 2,
96 .length = 78}}
97};
98
ace4dfee 99static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 100 int new_state);
1da177e4 101
8593fbc6
TG		 102static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
103 struct mtd_oob_ops *ops);
104
d470a97c 105/*
8e87d782 106 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 107 * compiled away when LED support is disabled.
108 */
109DEFINE_LED_TRIGGER(nand_led_trigger);
110
6fe5a6ac
VS		 111static int check_offs_len(struct mtd_info *mtd,
112 loff_t ofs, uint64_t len)
113{
114 struct nand_chip *chip = mtd->priv;
115 int ret = 0;
116
117 /* Start address must align on block boundary */
118 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
119 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
120 ret = -EINVAL;
121 }
122
123 /* Length must align on block boundary */
124 if (len & ((1 << chip->phys_erase_shift) - 1)) {
125 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
126 __func__);
127 ret = -EINVAL;
128 }
129
130 /* Do not allow past end of device */
131 if (ofs + len > mtd->size) {
132 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
133 __func__);
134 ret = -EINVAL;
135 }
136
137 return ret;
138}
139
1da177e4
LT		 140/**
141 * nand_release_device - [GENERIC] release chip
142 * @mtd: MTD device structure
61b03bd7
TG		 143 *
144 * Deselect, release chip lock and wake up anyone waiting on the device
1da177e4 145 */
e0c7d767 146static void nand_release_device(struct mtd_info *mtd)
1da177e4 147{
ace4dfee 148 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 149
150 /* De-select the NAND device */
ace4dfee 151 chip->select_chip(mtd, -1);
0dfc6246 152
a36ed299 153 /* Release the controller and the chip */
ace4dfee
TG		 154 spin_lock(&chip->controller->lock);
155 chip->controller->active = NULL;
156 chip->state = FL_READY;
157 wake_up(&chip->controller->wq);
158 spin_unlock(&chip->controller->lock);
1da177e4
LT		 159}
160
161/**
162 * nand_read_byte - [DEFAULT] read one byte from the chip
163 * @mtd: MTD device structure
164 *
165 * Default read function for 8bit buswith
166 */
58dd8f2b 167static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 168{
ace4dfee
TG		 169 struct nand_chip *chip = mtd->priv;
170 return readb(chip->IO_ADDR_R);
1da177e4
LT		 171}
172
1da177e4
LT		 173/**
174 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
175 * @mtd: MTD device structure
176 *
61b03bd7 177 * Default read function for 16bit buswith with
1da177e4
LT		 178 * endianess conversion
179 */
58dd8f2b 180static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 181{
ace4dfee
TG		 182 struct nand_chip *chip = mtd->priv;
183 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 184}
185
1da177e4
LT		 186/**
187 * nand_read_word - [DEFAULT] read one word from the chip
188 * @mtd: MTD device structure
189 *
61b03bd7 190 * Default read function for 16bit buswith without
1da177e4
LT		 191 * endianess conversion
192 */
193static u16 nand_read_word(struct mtd_info *mtd)
194{
ace4dfee
TG		 195 struct nand_chip *chip = mtd->priv;
196 return readw(chip->IO_ADDR_R);
1da177e4
LT		 197}
198
1da177e4
LT		 199/**
200 * nand_select_chip - [DEFAULT] control CE line
201 * @mtd: MTD device structure
844d3b42 202 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 203 *
204 * Default select function for 1 chip devices.
205 */
ace4dfee 206static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 207{
ace4dfee
TG		 208 struct nand_chip *chip = mtd->priv;
209
210 switch (chipnr) {
1da177e4 211 case -1:
ace4dfee 212 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 213 break;
214 case 0:
1da177e4
LT		 215 break;
216
217 default:
218 BUG();
219 }
220}
221
222/**
223 * nand_write_buf - [DEFAULT] write buffer to chip
224 * @mtd: MTD device structure
225 * @buf: data buffer
226 * @len: number of bytes to write
227 *
228 * Default write function for 8bit buswith
229 */
58dd8f2b 230static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 231{
232 int i;
ace4dfee 233 struct nand_chip *chip = mtd->priv;
1da177e4 234
e0c7d767 235 for (i = 0; i < len; i++)
ace4dfee 236 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 237}
238
239/**
61b03bd7 240 * nand_read_buf - [DEFAULT] read chip data into buffer
1da177e4
LT		 241 * @mtd: MTD device structure
242 * @buf: buffer to store date
243 * @len: number of bytes to read
244 *
245 * Default read function for 8bit buswith
246 */
58dd8f2b 247static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 248{
249 int i;
ace4dfee 250 struct nand_chip *chip = mtd->priv;
1da177e4 251
e0c7d767 252 for (i = 0; i < len; i++)
ace4dfee 253 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 254}
255
256/**
61b03bd7 257 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 258 * @mtd: MTD device structure
259 * @buf: buffer containing the data to compare
260 * @len: number of bytes to compare
261 *
262 * Default verify function for 8bit buswith
263 */
58dd8f2b 264static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 265{
266 int i;
ace4dfee 267 struct nand_chip *chip = mtd->priv;
1da177e4 268
e0c7d767 269 for (i = 0; i < len; i++)
ace4dfee 270 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 271 return -EFAULT;
1da177e4
LT		 272 return 0;
273}
274
275/**
276 * nand_write_buf16 - [DEFAULT] write buffer to chip
277 * @mtd: MTD device structure
278 * @buf: data buffer
279 * @len: number of bytes to write
280 *
281 * Default write function for 16bit buswith
282 */
58dd8f2b 283static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 284{
285 int i;
ace4dfee 286 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 287 u16 *p = (u16 *) buf;
288 len >>= 1;
61b03bd7 289
e0c7d767 290 for (i = 0; i < len; i++)
ace4dfee 291 writew(p[i], chip->IO_ADDR_W);
61b03bd7 292
1da177e4
LT		 293}
294
295/**
61b03bd7 296 * nand_read_buf16 - [DEFAULT] read chip data into buffer
1da177e4
LT		 297 * @mtd: MTD device structure
298 * @buf: buffer to store date
299 * @len: number of bytes to read
300 *
301 * Default read function for 16bit buswith
302 */
58dd8f2b 303static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 304{
305 int i;
ace4dfee 306 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 307 u16 *p = (u16 *) buf;
308 len >>= 1;
309
e0c7d767 310 for (i = 0; i < len; i++)
ace4dfee 311 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 312}
313
314/**
61b03bd7 315 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 316 * @mtd: MTD device structure
317 * @buf: buffer containing the data to compare
318 * @len: number of bytes to compare
319 *
320 * Default verify function for 16bit buswith
321 */
58dd8f2b 322static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 323{
324 int i;
ace4dfee 325 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 326 u16 *p = (u16 *) buf;
327 len >>= 1;
328
e0c7d767 329 for (i = 0; i < len; i++)
ace4dfee 330 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 331 return -EFAULT;
332
333 return 0;
334}
335
336/**
337 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
338 * @mtd: MTD device structure
339 * @ofs: offset from device start
340 * @getchip: 0, if the chip is already selected
341 *
61b03bd7 342 * Check, if the block is bad.
1da177e4
LT		 343 */
344static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
345{
346 int page, chipnr, res = 0;
ace4dfee 347 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 348 u16 bad;
349
1a12f46a
TK		 350 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
351
1da177e4 352 if (getchip) {
ace4dfee 353 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 354
ace4dfee 355 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 356
357 /* Select the NAND device */
ace4dfee 358 chip->select_chip(mtd, chipnr);
1a12f46a 359 }
1da177e4 360
ace4dfee
TG		 361 if (chip->options & NAND_BUSWIDTH_16) {
362 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 363 page);
ace4dfee
TG		 364 bad = cpu_to_le16(chip->read_word(mtd));
365 if (chip->badblockpos & 0x1)
49196f33 366 bad >>= 8;
e0b58d0a
ML		 367 else
368 bad &= 0xFF;
1da177e4 369 } else {
1a12f46a 370 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
e0b58d0a 371 bad = chip->read_byte(mtd);
1da177e4 372 }
61b03bd7 373
e0b58d0a
ML		 374 if (likely(chip->badblockbits == 8))
375 res = bad != 0xFF;
376 else
377 res = hweight8(bad) < chip->badblockbits;
378
ace4dfee 379 if (getchip)
1da177e4 380 nand_release_device(mtd);
61b03bd7 381
1da177e4
LT		 382 return res;
383}
384
385/**
386 * nand_default_block_markbad - [DEFAULT] mark a block bad
387 * @mtd: MTD device structure
388 * @ofs: offset from device start
389 *
390 * This is the default implementation, which can be overridden by
391 * a hardware specific driver.
392*/
393static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
394{
ace4dfee 395 struct nand_chip *chip = mtd->priv;
58dd8f2b 396 uint8_t buf[2] = { 0, 0 };
f1a28c02 397 int block, ret;
61b03bd7 398
1da177e4 399 /* Get block number */
4226b510 400 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 401 if (chip->bbt)
402 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4
LT		 403
404 /* Do we have a flash based bad block table ? */
ace4dfee 405 if (chip->options & NAND_USE_FLASH_BBT)
f1a28c02
TG		 406 ret = nand_update_bbt(mtd, ofs);
407 else {
408 /* We write two bytes, so we dont have to mess with 16 bit
409 * access
410 */
c0b8ba7b 411 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 412 ofs += mtd->oobsize;
ff0dab64 413 chip->ops.len = chip->ops.ooblen = 2;
f1a28c02
TG		 414 chip->ops.datbuf = NULL;
415 chip->ops.oobbuf = buf;
416 chip->ops.ooboffs = chip->badblockpos & ~0x01;
417
418 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
c0b8ba7b 419 nand_release_device(mtd);
f1a28c02
TG		 420 }
421 if (!ret)
422 mtd->ecc_stats.badblocks++;
c0b8ba7b 423
f1a28c02 424 return ret;
1da177e4
LT		 425}
426
61b03bd7 427/**
1da177e4
LT		 428 * nand_check_wp - [GENERIC] check if the chip is write protected
429 * @mtd: MTD device structure
61b03bd7 430 * Check, if the device is write protected
1da177e4 431 *
61b03bd7 432 * The function expects, that the device is already selected
1da177e4 433 */
e0c7d767 434static int nand_check_wp(struct mtd_info *mtd)
1da177e4 435{
ace4dfee 436 struct nand_chip *chip = mtd->priv;
1da177e4 437 /* Check the WP bit */
ace4dfee
TG		 438 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
439 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 440}
441
442/**
443 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
444 * @mtd: MTD device structure
445 * @ofs: offset from device start
446 * @getchip: 0, if the chip is already selected
447 * @allowbbt: 1, if its allowed to access the bbt area
448 *
449 * Check, if the block is bad. Either by reading the bad block table or
450 * calling of the scan function.
451 */
2c0a2bed
TG		 452static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
453 int allowbbt)
1da177e4 454{
ace4dfee 455 struct nand_chip *chip = mtd->priv;
61b03bd7 456
ace4dfee
TG		 457 if (!chip->bbt)
458 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 459
1da177e4 460 /* Return info from the table */
e0c7d767 461 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 462}
463
2af7c653
SK		 464/**
465 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
466 * @mtd: MTD device structure
467 * @timeo: Timeout
468 *
469 * Helper function for nand_wait_ready used when needing to wait in interrupt
470 * context.
471 */
472static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
473{
474 struct nand_chip *chip = mtd->priv;
475 int i;
476
477 /* Wait for the device to get ready */
478 for (i = 0; i < timeo; i++) {
479 if (chip->dev_ready(mtd))
480 break;
481 touch_softlockup_watchdog();
482 mdelay(1);
483 }
484}
485
61b03bd7 486/*
3b88775c
TG		 487 * Wait for the ready pin, after a command
488 * The timeout is catched later.
489 */
4b648b02 490void nand_wait_ready(struct mtd_info *mtd)
3b88775c 491{
ace4dfee 492 struct nand_chip *chip = mtd->priv;
e0c7d767 493 unsigned long timeo = jiffies + 2;
3b88775c 494
2af7c653
SK		 495 /* 400ms timeout */
496 if (in_interrupt() || oops_in_progress)
497 return panic_nand_wait_ready(mtd, 400);
498
8fe833c1 499 led_trigger_event(nand_led_trigger, LED_FULL);
3b88775c
TG		 500 /* wait until command is processed or timeout occures */
501 do {
ace4dfee 502 if (chip->dev_ready(mtd))
8fe833c1 503 break;
8446f1d3 504 touch_softlockup_watchdog();
61b03bd7 505 } while (time_before(jiffies, timeo));
8fe833c1 506 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 507}
4b648b02 508EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 509
1da177e4
LT		 510/**
511 * nand_command - [DEFAULT] Send command to NAND device
512 * @mtd: MTD device structure
513 * @command: the command to be sent
514 * @column: the column address for this command, -1 if none
515 * @page_addr: the page address for this command, -1 if none
516 *
517 * Send command to NAND device. This function is used for small page
518 * devices (256/512 Bytes per page)
519 */
7abd3ef9
TG		 520static void nand_command(struct mtd_info *mtd, unsigned int command,
521 int column, int page_addr)
1da177e4 522{
ace4dfee 523 register struct nand_chip *chip = mtd->priv;
7abd3ef9 524 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 525
1da177e4
LT		 526 /*
527 * Write out the command to the device.
528 */
529 if (command == NAND_CMD_SEQIN) {
530 int readcmd;
531
28318776 532 if (column >= mtd->writesize) {
1da177e4 533 /* OOB area */
28318776 534 column -= mtd->writesize;
1da177e4
LT		 535 readcmd = NAND_CMD_READOOB;
536 } else if (column < 256) {
537 /* First 256 bytes --> READ0 */
538 readcmd = NAND_CMD_READ0;
539 } else {
540 column -= 256;
541 readcmd = NAND_CMD_READ1;
542 }
ace4dfee 543 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 544 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 545 }
ace4dfee 546 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 547
7abd3ef9
TG		 548 /*
549 * Address cycle, when necessary
550 */
551 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
552 /* Serially input address */
553 if (column != -1) {
554 /* Adjust columns for 16 bit buswidth */
ace4dfee 555 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 556 column >>= 1;
ace4dfee 557 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 558 ctrl &= ~NAND_CTRL_CHANGE;
559 }
560 if (page_addr != -1) {
ace4dfee 561 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 562 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 563 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 564 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 565 if (chip->chipsize > (32 << 20))
566 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 567 }
ace4dfee 568 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 569
570 /*
571 * program and erase have their own busy handlers
1da177e4 572 * status and sequential in needs no delay
e0c7d767 573 */
1da177e4 574 switch (command) {
61b03bd7 575
1da177e4
LT		 576 case NAND_CMD_PAGEPROG:
577 case NAND_CMD_ERASE1:
578 case NAND_CMD_ERASE2:
579 case NAND_CMD_SEQIN:
580 case NAND_CMD_STATUS:
581 return;
582
583 case NAND_CMD_RESET:
ace4dfee 584 if (chip->dev_ready)
1da177e4 585 break;
ace4dfee
TG		 586 udelay(chip->chip_delay);
587 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 588 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 589 chip->cmd_ctrl(mtd,
590 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
ace4dfee 591 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
1da177e4
LT		 592 return;
593
e0c7d767 594 /* This applies to read commands */
1da177e4 595 default:
61b03bd7 596 /*
1da177e4
LT		 597 * If we don't have access to the busy pin, we apply the given
598 * command delay
e0c7d767 599 */
ace4dfee
TG		 600 if (!chip->dev_ready) {
601 udelay(chip->chip_delay);
1da177e4 602 return;
61b03bd7 603 }
1da177e4 604 }
1da177e4
LT		 605 /* Apply this short delay always to ensure that we do wait tWB in
606 * any case on any machine. */
e0c7d767 607 ndelay(100);
3b88775c
TG		 608
609 nand_wait_ready(mtd);
1da177e4
LT		 610}
611
612/**
613 * nand_command_lp - [DEFAULT] Send command to NAND large page device
614 * @mtd: MTD device structure
615 * @command: the command to be sent
616 * @column: the column address for this command, -1 if none
617 * @page_addr: the page address for this command, -1 if none
618 *
7abd3ef9
TG		 619 * Send command to NAND device. This is the version for the new large page
620 * devices We dont have the separate regions as we have in the small page
621 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 622 */
7abd3ef9
TG		 623static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
624 int column, int page_addr)
1da177e4 625{
ace4dfee 626 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 627
628 /* Emulate NAND_CMD_READOOB */
629 if (command == NAND_CMD_READOOB) {
28318776 630 column += mtd->writesize;
1da177e4
LT		 631 command = NAND_CMD_READ0;
632 }
61b03bd7 633
7abd3ef9 634 /* Command latch cycle */
ace4dfee 635 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 636 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 637
638 if (column != -1 || page_addr != -1) {
7abd3ef9 639 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 640
641 /* Serially input address */
642 if (column != -1) {
643 /* Adjust columns for 16 bit buswidth */
ace4dfee 644 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 645 column >>= 1;
ace4dfee 646 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 647 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 648 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 649 }
1da177e4 650 if (page_addr != -1) {
ace4dfee
TG		 651 chip->cmd_ctrl(mtd, page_addr, ctrl);
652 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 653 NAND_NCE | NAND_ALE);
1da177e4 654 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 655 if (chip->chipsize > (128 << 20))
656 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 657 NAND_NCE | NAND_ALE);
1da177e4 658 }
1da177e4 659 }
ace4dfee 660 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 661
662 /*
663 * program and erase have their own busy handlers
30f464b7
DM		 664 * status, sequential in, and deplete1 need no delay
665 */
1da177e4 666 switch (command) {
61b03bd7 667
1da177e4
LT		 668 case NAND_CMD_CACHEDPROG:
669 case NAND_CMD_PAGEPROG:
670 case NAND_CMD_ERASE1:
671 case NAND_CMD_ERASE2:
672 case NAND_CMD_SEQIN:
7bc3312b 673 case NAND_CMD_RNDIN:
1da177e4 674 case NAND_CMD_STATUS:
30f464b7 675 case NAND_CMD_DEPLETE1:
1da177e4
LT		 676 return;
677
e0c7d767
DW		 678 /*
679 * read error status commands require only a short delay
680 */
30f464b7
DM		 681 case NAND_CMD_STATUS_ERROR:
682 case NAND_CMD_STATUS_ERROR0:
683 case NAND_CMD_STATUS_ERROR1:
684 case NAND_CMD_STATUS_ERROR2:
685 case NAND_CMD_STATUS_ERROR3:
ace4dfee 686 udelay(chip->chip_delay);
30f464b7 687 return;
1da177e4
LT		 688
689 case NAND_CMD_RESET:
ace4dfee 690 if (chip->dev_ready)
1da177e4 691 break;
ace4dfee 692 udelay(chip->chip_delay);
12efdde3
TG		 693 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
694 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
695 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
696 NAND_NCE | NAND_CTRL_CHANGE);
ace4dfee 697 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
1da177e4
LT		 698 return;
699
7bc3312b
TG		 700 case NAND_CMD_RNDOUT:
701 /* No ready / busy check necessary */
702 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
703 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
704 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
705 NAND_NCE | NAND_CTRL_CHANGE);
706 return;
707
1da177e4 708 case NAND_CMD_READ0:
12efdde3
TG		 709 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
710 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
711 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
712 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 713
e0c7d767 714 /* This applies to read commands */
1da177e4 715 default:
61b03bd7 716 /*
1da177e4
LT		 717 * If we don't have access to the busy pin, we apply the given
718 * command delay
e0c7d767 719 */
ace4dfee
TG		 720 if (!chip->dev_ready) {
721 udelay(chip->chip_delay);
1da177e4 722 return;
61b03bd7 723 }
1da177e4 724 }
3b88775c 725
1da177e4
LT		 726 /* Apply this short delay always to ensure that we do wait tWB in
727 * any case on any machine. */
e0c7d767 728 ndelay(100);
3b88775c
TG		 729
730 nand_wait_ready(mtd);
1da177e4
LT		 731}
732
2af7c653
SK		 733/**
734 * panic_nand_get_device - [GENERIC] Get chip for selected access
735 * @chip: the nand chip descriptor
736 * @mtd: MTD device structure
737 * @new_state: the state which is requested
738 *
739 * Used when in panic, no locks are taken.
740 */
741static void panic_nand_get_device(struct nand_chip *chip,
742 struct mtd_info *mtd, int new_state)
743{
744 /* Hardware controller shared among independend devices */
745 chip->controller->active = chip;
746 chip->state = new_state;
747}
748
1da177e4
LT		 749/**
750 * nand_get_device - [GENERIC] Get chip for selected access
844d3b42 751 * @chip: the nand chip descriptor
1da177e4 752 * @mtd: MTD device structure
61b03bd7 753 * @new_state: the state which is requested
1da177e4
LT		 754 *
755 * Get the device and lock it for exclusive access
756 */
2c0a2bed 757static int
ace4dfee 758nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 759{
ace4dfee
TG		 760 spinlock_t *lock = &chip->controller->lock;
761 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 762 DECLARE_WAITQUEUE(wait, current);
e0c7d767 763 retry:
0dfc6246
TG		 764 spin_lock(lock);
765
b8b3ee9a 766 /* Hardware controller shared among independent devices */
ace4dfee
TG		 767 if (!chip->controller->active)
768 chip->controller->active = chip;
a36ed299 769
ace4dfee
TG		 770 if (chip->controller->active == chip && chip->state == FL_READY) {
771 chip->state = new_state;
0dfc6246 772 spin_unlock(lock);
962034f4
VW		 773 return 0;
774 }
775 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 776 if (chip->controller->active->state == FL_PM_SUSPENDED) {
777 chip->state = FL_PM_SUSPENDED;
778 spin_unlock(lock);
779 return 0;
6b0d9a84 780 }
0dfc6246
TG		 781 }
782 set_current_state(TASK_UNINTERRUPTIBLE);
783 add_wait_queue(wq, &wait);
784 spin_unlock(lock);
785 schedule();
786 remove_wait_queue(wq, &wait);
1da177e4
LT		 787 goto retry;
788}
789
2af7c653
SK		 790/**
791 * panic_nand_wait - [GENERIC] wait until the command is done
792 * @mtd: MTD device structure
793 * @chip: NAND chip structure
794 * @timeo: Timeout
795 *
796 * Wait for command done. This is a helper function for nand_wait used when
797 * we are in interrupt context. May happen when in panic and trying to write
798 * an oops trough mtdoops.
799 */
800static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
801 unsigned long timeo)
802{
803 int i;
804 for (i = 0; i < timeo; i++) {
805 if (chip->dev_ready) {
806 if (chip->dev_ready(mtd))
807 break;
808 } else {
809 if (chip->read_byte(mtd) & NAND_STATUS_READY)
810 break;
811 }
812 mdelay(1);
813 }
814}
815
1da177e4
LT		 816/**
817 * nand_wait - [DEFAULT] wait until the command is done
818 * @mtd: MTD device structure
844d3b42 819 * @chip: NAND chip structure
1da177e4
LT		 820 *
821 * Wait for command done. This applies to erase and program only
61b03bd7 822 * Erase can take up to 400ms and program up to 20ms according to
1da177e4 823 * general NAND and SmartMedia specs
844d3b42 824 */
7bc3312b 825static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 826{
827
e0c7d767 828 unsigned long timeo = jiffies;
7bc3312b 829 int status, state = chip->state;
61b03bd7 830
1da177e4 831 if (state == FL_ERASING)
e0c7d767 832 timeo += (HZ * 400) / 1000;
1da177e4 833 else
e0c7d767 834 timeo += (HZ * 20) / 1000;
1da177e4 835
8fe833c1
RP		 836 led_trigger_event(nand_led_trigger, LED_FULL);
837
1da177e4
LT		 838 /* Apply this short delay always to ensure that we do wait tWB in
839 * any case on any machine. */
e0c7d767 840 ndelay(100);
1da177e4 841
ace4dfee
TG		 842 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
843 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 844 else
ace4dfee 845 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 846
2af7c653
SK		 847 if (in_interrupt() || oops_in_progress)
848 panic_nand_wait(mtd, chip, timeo);
849 else {
850 while (time_before(jiffies, timeo)) {
851 if (chip->dev_ready) {
852 if (chip->dev_ready(mtd))
853 break;
854 } else {
855 if (chip->read_byte(mtd) & NAND_STATUS_READY)
856 break;
857 }
858 cond_resched();
1da177e4 859 }
1da177e4 860 }
8fe833c1
RP		 861 led_trigger_event(nand_led_trigger, LED_OFF);
862
ace4dfee 863 status = (int)chip->read_byte(mtd);
1da177e4
LT		 864 return status;
865}
866
7d70f334
VS		 867/**
868 * __nand_unlock - [REPLACABLE] unlocks specified locked blockes
869 *
870 * @param mtd - mtd info
871 * @param ofs - offset to start unlock from
872 * @param len - length to unlock
873 * @invert - when = 0, unlock the range of blocks within the lower and
874 * upper boundary address
875 * whne = 1, unlock the range of blocks outside the boundaries
876 * of the lower and upper boundary address
877 *
878 * @return - unlock status
879 */
880static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
881 uint64_t len, int invert)
882{
883 int ret = 0;
884 int status, page;
885 struct nand_chip *chip = mtd->priv;
886
887 /* Submit address of first page to unlock */
888 page = ofs >> chip->page_shift;
889 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
890
891 /* Submit address of last page to unlock */
892 page = (ofs + len) >> chip->page_shift;
893 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
894 (page | invert) & chip->pagemask);
895
896 /* Call wait ready function */
897 status = chip->waitfunc(mtd, chip);
898 udelay(1000);
899 /* See if device thinks it succeeded */
900 if (status & 0x01) {
901 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
902 __func__, status);
903 ret = -EIO;
904 }
905
906 return ret;
907}
908
909/**
910 * nand_unlock - [REPLACABLE] unlocks specified locked blockes
911 *
912 * @param mtd - mtd info
913 * @param ofs - offset to start unlock from
914 * @param len - length to unlock
915 *
916 * @return - unlock status
917 */
918int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
919{
920 int ret = 0;
921 int chipnr;
922 struct nand_chip *chip = mtd->priv;
923
924 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
925 __func__, (unsigned long long)ofs, len);
926
927 if (check_offs_len(mtd, ofs, len))
928 ret = -EINVAL;
929
930 /* Align to last block address if size addresses end of the device */
931 if (ofs + len == mtd->size)
932 len -= mtd->erasesize;
933
934 nand_get_device(chip, mtd, FL_UNLOCKING);
935
936 /* Shift to get chip number */
937 chipnr = ofs >> chip->chip_shift;
938
939 chip->select_chip(mtd, chipnr);
940
941 /* Check, if it is write protected */
942 if (nand_check_wp(mtd)) {
943 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
944 __func__);
945 ret = -EIO;
946 goto out;
947 }
948
949 ret = __nand_unlock(mtd, ofs, len, 0);
950
951out:
952 /* de-select the NAND device */
953 chip->select_chip(mtd, -1);
954
955 nand_release_device(mtd);
956
957 return ret;
958}
959
960/**
961 * nand_lock - [REPLACABLE] locks all blockes present in the device
962 *
963 * @param mtd - mtd info
964 * @param ofs - offset to start unlock from
965 * @param len - length to unlock
966 *
967 * @return - lock status
968 *
969 * This feature is not support in many NAND parts. 'Micron' NAND parts
970 * do have this feature, but it allows only to lock all blocks not for
971 * specified range for block.
972 *
973 * Implementing 'lock' feature by making use of 'unlock', for now.
974 */
975int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
976{
977 int ret = 0;
978 int chipnr, status, page;
979 struct nand_chip *chip = mtd->priv;
980
981 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
982 __func__, (unsigned long long)ofs, len);
983
984 if (check_offs_len(mtd, ofs, len))
985 ret = -EINVAL;
986
987 nand_get_device(chip, mtd, FL_LOCKING);
988
989 /* Shift to get chip number */
990 chipnr = ofs >> chip->chip_shift;
991
992 chip->select_chip(mtd, chipnr);
993
994 /* Check, if it is write protected */
995 if (nand_check_wp(mtd)) {
996 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
997 __func__);
998 status = MTD_ERASE_FAILED;
999 ret = -EIO;
1000 goto out;
1001 }
1002
1003 /* Submit address of first page to lock */
1004 page = ofs >> chip->page_shift;
1005 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1006
1007 /* Call wait ready function */
1008 status = chip->waitfunc(mtd, chip);
1009 udelay(1000);
1010 /* See if device thinks it succeeded */
1011 if (status & 0x01) {
1012 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1013 __func__, status);
1014 ret = -EIO;
1015 goto out;
1016 }
1017
1018 ret = __nand_unlock(mtd, ofs, len, 0x1);
1019
1020out:
1021 /* de-select the NAND device */
1022 chip->select_chip(mtd, -1);
1023
1024 nand_release_device(mtd);
1025
1026 return ret;
1027}
1028
8593fbc6
TG		 1029/**
1030 * nand_read_page_raw - [Intern] read raw page data without ecc
1031 * @mtd: mtd info structure
1032 * @chip: nand chip info structure
1033 * @buf: buffer to store read data
58475fb9 1034 * @page: page number to read
52ff49df
DB		 1035 *
1036 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1037 */
1038static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1039 uint8_t *buf, int page)
8593fbc6
TG		 1040{
1041 chip->read_buf(mtd, buf, mtd->writesize);
1042 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1043 return 0;
1044}
1045
52ff49df
DB		 1046/**
1047 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1048 * @mtd: mtd info structure
1049 * @chip: nand chip info structure
1050 * @buf: buffer to store read data
58475fb9 1051 * @page: page number to read
52ff49df
DB		 1052 *
1053 * We need a special oob layout and handling even when OOB isn't used.
1054 */
1055static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1056 uint8_t *buf, int page)
52ff49df
DB		 1057{
1058 int eccsize = chip->ecc.size;
1059 int eccbytes = chip->ecc.bytes;
1060 uint8_t *oob = chip->oob_poi;
1061 int steps, size;
1062
1063 for (steps = chip->ecc.steps; steps > 0; steps--) {
1064 chip->read_buf(mtd, buf, eccsize);
1065 buf += eccsize;
1066
1067 if (chip->ecc.prepad) {
1068 chip->read_buf(mtd, oob, chip->ecc.prepad);
1069 oob += chip->ecc.prepad;
1070 }
1071
1072 chip->read_buf(mtd, oob, eccbytes);
1073 oob += eccbytes;
1074
1075 if (chip->ecc.postpad) {
1076 chip->read_buf(mtd, oob, chip->ecc.postpad);
1077 oob += chip->ecc.postpad;
1078 }
1079 }
1080
1081 size = mtd->oobsize - (oob - chip->oob_poi);
1082 if (size)
1083 chip->read_buf(mtd, oob, size);
1084
1085 return 0;
1086}
1087
1da177e4 1088/**
d29ebdbe 1089 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
f5bbdacc
TG		 1090 * @mtd: mtd info structure
1091 * @chip: nand chip info structure
1092 * @buf: buffer to store read data
58475fb9 1093 * @page: page number to read
068e3c0a 1094 */
f5bbdacc 1095static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1096 uint8_t *buf, int page)
1da177e4 1097{
f5bbdacc
TG		 1098 int i, eccsize = chip->ecc.size;
1099 int eccbytes = chip->ecc.bytes;
1100 int eccsteps = chip->ecc.steps;
1101 uint8_t *p = buf;
4bf63fcb
DW		 1102 uint8_t *ecc_calc = chip->buffers->ecccalc;
1103 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1104 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 1105
46a8cf2d 1106 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 1107
1108 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1109 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1110
1111 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1112 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1113
1114 eccsteps = chip->ecc.steps;
1115 p = buf;
1116
1117 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1118 int stat;
1119
1120 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1121 if (stat < 0)
f5bbdacc
TG		 1122 mtd->ecc_stats.failed++;
1123 else
1124 mtd->ecc_stats.corrected += stat;
1125 }
1126 return 0;
22c60f5f 1127}
1da177e4 1128
3d459559
AK		 1129/**
1130 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1131 * @mtd: mtd info structure
1132 * @chip: nand chip info structure
17c1d2be
AK		 1133 * @data_offs: offset of requested data within the page
1134 * @readlen: data length
1135 * @bufpoi: buffer to store read data
3d459559
AK		 1136 */
1137static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1138{
1139 int start_step, end_step, num_steps;
1140 uint32_t *eccpos = chip->ecc.layout->eccpos;
1141 uint8_t *p;
1142 int data_col_addr, i, gaps = 0;
1143 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1144 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1145
1146 /* Column address wihin the page aligned to ECC size (256bytes). */
1147 start_step = data_offs / chip->ecc.size;
1148 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1149 num_steps = end_step - start_step + 1;
1150
1151 /* Data size aligned to ECC ecc.size*/
1152 datafrag_len = num_steps * chip->ecc.size;
1153 eccfrag_len = num_steps * chip->ecc.bytes;
1154
1155 data_col_addr = start_step * chip->ecc.size;
1156 /* If we read not a page aligned data */
1157 if (data_col_addr != 0)
1158 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1159
1160 p = bufpoi + data_col_addr;
1161 chip->read_buf(mtd, p, datafrag_len);
1162
1163 /* Calculate ECC */
1164 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1165 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1166
1167 /* The performance is faster if to position offsets
1168 according to ecc.pos. Let make sure here that
1169 there are no gaps in ecc positions */
1170 for (i = 0; i < eccfrag_len - 1; i++) {
1171 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1172 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1173 gaps = 1;
1174 break;
1175 }
1176 }
1177 if (gaps) {
1178 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1179 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1180 } else {
1181 /* send the command to read the particular ecc bytes */
1182 /* take care about buswidth alignment in read_buf */
1183 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1184 aligned_len = eccfrag_len;
1185 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1186 aligned_len++;
1187 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1188 aligned_len++;
1189
1190 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1191 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1192 }
1193
1194 for (i = 0; i < eccfrag_len; i++)
1195 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1196
1197 p = bufpoi + data_col_addr;
1198 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1199 int stat;
1200
1201 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1202 if (stat == -1)
1203 mtd->ecc_stats.failed++;
1204 else
1205 mtd->ecc_stats.corrected += stat;
1206 }
1207 return 0;
1208}
1209
068e3c0a 1210/**
d29ebdbe 1211 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
f5bbdacc
TG		 1212 * @mtd: mtd info structure
1213 * @chip: nand chip info structure
1214 * @buf: buffer to store read data
58475fb9 1215 * @page: page number to read
068e3c0a 1216 *
f5bbdacc 1217 * Not for syndrome calculating ecc controllers which need a special oob layout
068e3c0a 1218 */
f5bbdacc 1219static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1220 uint8_t *buf, int page)
1da177e4 1221{
f5bbdacc
TG		 1222 int i, eccsize = chip->ecc.size;
1223 int eccbytes = chip->ecc.bytes;
1224 int eccsteps = chip->ecc.steps;
1225 uint8_t *p = buf;
4bf63fcb
DW		 1226 uint8_t *ecc_calc = chip->buffers->ecccalc;
1227 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1228 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1229
1230 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1231 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1232 chip->read_buf(mtd, p, eccsize);
1233 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1234 }
f75e5097 1235 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1236
f5bbdacc 1237 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1238 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1239
f5bbdacc
TG		 1240 eccsteps = chip->ecc.steps;
1241 p = buf;
61b03bd7 1242
f5bbdacc
TG		 1243 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1244 int stat;
1da177e4 1245
f5bbdacc 1246 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1247 if (stat < 0)
f5bbdacc
TG		 1248 mtd->ecc_stats.failed++;
1249 else
1250 mtd->ecc_stats.corrected += stat;
1251 }
1252 return 0;
1253}
1da177e4 1254
6e0cb135
SN		 1255/**
1256 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1257 * @mtd: mtd info structure
1258 * @chip: nand chip info structure
1259 * @buf: buffer to store read data
58475fb9 1260 * @page: page number to read
6e0cb135
SN		 1261 *
1262 * Hardware ECC for large page chips, require OOB to be read first.
1263 * For this ECC mode, the write_page method is re-used from ECC_HW.
1264 * These methods read/write ECC from the OOB area, unlike the
1265 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1266 * "infix ECC" scheme and reads/writes ECC from the data area, by
1267 * overwriting the NAND manufacturer bad block markings.
1268 */
1269static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1270 struct nand_chip *chip, uint8_t *buf, int page)
1271{
1272 int i, eccsize = chip->ecc.size;
1273 int eccbytes = chip->ecc.bytes;
1274 int eccsteps = chip->ecc.steps;
1275 uint8_t *p = buf;
1276 uint8_t *ecc_code = chip->buffers->ecccode;
1277 uint32_t *eccpos = chip->ecc.layout->eccpos;
1278 uint8_t *ecc_calc = chip->buffers->ecccalc;
1279
1280 /* Read the OOB area first */
1281 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1282 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1283 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1284
1285 for (i = 0; i < chip->ecc.total; i++)
1286 ecc_code[i] = chip->oob_poi[eccpos[i]];
1287
1288 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1289 int stat;
1290
1291 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1292 chip->read_buf(mtd, p, eccsize);
1293 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1294
1295 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1296 if (stat < 0)
1297 mtd->ecc_stats.failed++;
1298 else
1299 mtd->ecc_stats.corrected += stat;
1300 }
1301 return 0;
1302}
1303
f5bbdacc 1304/**
d29ebdbe 1305 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
f5bbdacc
TG		 1306 * @mtd: mtd info structure
1307 * @chip: nand chip info structure
1308 * @buf: buffer to store read data
58475fb9 1309 * @page: page number to read
f5bbdacc
TG		 1310 *
1311 * The hw generator calculates the error syndrome automatically. Therefor
f75e5097 1312 * we need a special oob layout and handling.
f5bbdacc
TG		 1313 */
1314static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1315 uint8_t *buf, int page)
f5bbdacc
TG		 1316{
1317 int i, eccsize = chip->ecc.size;
1318 int eccbytes = chip->ecc.bytes;
1319 int eccsteps = chip->ecc.steps;
1320 uint8_t *p = buf;
f75e5097 1321 uint8_t *oob = chip->oob_poi;
1da177e4 1322
f5bbdacc
TG		 1323 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1324 int stat;
61b03bd7 1325
f5bbdacc
TG		 1326 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1327 chip->read_buf(mtd, p, eccsize);
1da177e4 1328
f5bbdacc
TG		 1329 if (chip->ecc.prepad) {
1330 chip->read_buf(mtd, oob, chip->ecc.prepad);
1331 oob += chip->ecc.prepad;
1332 }
1da177e4 1333
f5bbdacc
TG		 1334 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1335 chip->read_buf(mtd, oob, eccbytes);
1336 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1337
c32b8dcc 1338 if (stat < 0)
f5bbdacc 1339 mtd->ecc_stats.failed++;
61b03bd7 1340 else
f5bbdacc 1341 mtd->ecc_stats.corrected += stat;
61b03bd7 1342
f5bbdacc 1343 oob += eccbytes;
1da177e4 1344
f5bbdacc
TG		 1345 if (chip->ecc.postpad) {
1346 chip->read_buf(mtd, oob, chip->ecc.postpad);
1347 oob += chip->ecc.postpad;
61b03bd7 1348 }
f5bbdacc 1349 }
1da177e4 1350
f5bbdacc 1351 /* Calculate remaining oob bytes */
7e4178f9 1352 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1353 if (i)
1354 chip->read_buf(mtd, oob, i);
61b03bd7 1355
f5bbdacc
TG		 1356 return 0;
1357}
1da177e4 1358
f5bbdacc 1359/**
8593fbc6
TG		 1360 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1361 * @chip: nand chip structure
844d3b42 1362 * @oob: oob destination address
8593fbc6 1363 * @ops: oob ops structure
7014568b 1364 * @len: size of oob to transfer
8593fbc6
TG		 1365 */
1366static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1367 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1368{
8593fbc6
TG		 1369 switch(ops->mode) {
1370
1371 case MTD_OOB_PLACE:
1372 case MTD_OOB_RAW:
1373 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1374 return oob + len;
1375
1376 case MTD_OOB_AUTO: {
1377 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1378 uint32_t boffs = 0, roffs = ops->ooboffs;
1379 size_t bytes = 0;
8593fbc6
TG		 1380
1381 for(; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1382 /* Read request not from offset 0 ? */
1383 if (unlikely(roffs)) {
1384 if (roffs >= free->length) {
1385 roffs -= free->length;
1386 continue;
1387 }
1388 boffs = free->offset + roffs;
1389 bytes = min_t(size_t, len,
1390 (free->length - roffs));
1391 roffs = 0;
1392 } else {
1393 bytes = min_t(size_t, len, free->length);
1394 boffs = free->offset;
1395 }
1396 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1397 oob += bytes;
1398 }
1399 return oob;
1400 }
1401 default:
1402 BUG();
1403 }
1404 return NULL;
1405}
1406
1407/**
1408 * nand_do_read_ops - [Internal] Read data with ECC
f5bbdacc
TG		 1409 *
1410 * @mtd: MTD device structure
1411 * @from: offset to read from
844d3b42 1412 * @ops: oob ops structure
f5bbdacc
TG		 1413 *
1414 * Internal function. Called with chip held.
1415 */
8593fbc6
TG		 1416static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1417 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1418{
1419 int chipnr, page, realpage, col, bytes, aligned;
1420 struct nand_chip *chip = mtd->priv;
1421 struct mtd_ecc_stats stats;
1422 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1423 int sndcmd = 1;
1424 int ret = 0;
8593fbc6 1425 uint32_t readlen = ops->len;
7014568b 1426 uint32_t oobreadlen = ops->ooblen;
9aca334e
ML		 1427 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1428 mtd->oobavail : mtd->oobsize;
1429
8593fbc6 1430 uint8_t *bufpoi, *oob, *buf;
1da177e4 1431
f5bbdacc 1432 stats = mtd->ecc_stats;
1da177e4 1433
f5bbdacc
TG		 1434 chipnr = (int)(from >> chip->chip_shift);
1435 chip->select_chip(mtd, chipnr);
61b03bd7 1436
f5bbdacc
TG		 1437 realpage = (int)(from >> chip->page_shift);
1438 page = realpage & chip->pagemask;
1da177e4 1439
f5bbdacc 1440 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1441
8593fbc6
TG		 1442 buf = ops->datbuf;
1443 oob = ops->oobbuf;
1444
f5bbdacc
TG		 1445 while(1) {
1446 bytes = min(mtd->writesize - col, readlen);
1447 aligned = (bytes == mtd->writesize);
61b03bd7 1448
f5bbdacc 1449 /* Is the current page in the buffer ? */
8593fbc6 1450 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1451 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1452
f5bbdacc
TG		 1453 if (likely(sndcmd)) {
1454 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1455 sndcmd = 0;
1da177e4 1456 }
1da177e4 1457
f5bbdacc 1458 /* Now read the page into the buffer */
956e944c 1459 if (unlikely(ops->mode == MTD_OOB_RAW))
46a8cf2d
SN		 1460 ret = chip->ecc.read_page_raw(mtd, chip,
1461 bufpoi, page);
3d459559
AK		 1462 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1463 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
956e944c 1464 else
46a8cf2d
SN		 1465 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1466 page);
f5bbdacc 1467 if (ret < 0)
1da177e4 1468 break;
f5bbdacc
TG		 1469
1470 /* Transfer not aligned data */
1471 if (!aligned) {
3d459559
AK		 1472 if (!NAND_SUBPAGE_READ(chip) && !oob)
1473 chip->pagebuf = realpage;
4bf63fcb 1474 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1475 }
1476
8593fbc6
TG		 1477 buf += bytes;
1478
1479 if (unlikely(oob)) {
9aca334e 1480
b64d39d8
ML		 1481 int toread = min(oobreadlen, max_oobsize);
1482
1483 if (toread) {
1484 oob = nand_transfer_oob(chip,
1485 oob, ops, toread);
1486 oobreadlen -= toread;
1487 }
8593fbc6
TG		 1488 }
1489
f5bbdacc
TG		 1490 if (!(chip->options & NAND_NO_READRDY)) {
1491 /*
1492 * Apply delay or wait for ready/busy pin. Do
1493 * this before the AUTOINCR check, so no
1494 * problems arise if a chip which does auto
1495 * increment is marked as NOAUTOINCR by the
1496 * board driver.
1497 */
1498 if (!chip->dev_ready)
1499 udelay(chip->chip_delay);
1500 else
1501 nand_wait_ready(mtd);
1da177e4 1502 }
8593fbc6 1503 } else {
4bf63fcb 1504 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1505 buf += bytes;
1506 }
1da177e4 1507
f5bbdacc 1508 readlen -= bytes;
61b03bd7 1509
f5bbdacc 1510 if (!readlen)
61b03bd7 1511 break;
1da177e4
LT		 1512
1513 /* For subsequent reads align to page boundary. */
1514 col = 0;
1515 /* Increment page address */
1516 realpage++;
1517
ace4dfee 1518 page = realpage & chip->pagemask;
1da177e4
LT		 1519 /* Check, if we cross a chip boundary */
1520 if (!page) {
1521 chipnr++;
ace4dfee
TG		 1522 chip->select_chip(mtd, -1);
1523 chip->select_chip(mtd, chipnr);
1da177e4 1524 }
f5bbdacc 1525
61b03bd7
TG		 1526 /* Check, if the chip supports auto page increment
1527 * or if we have hit a block boundary.
e0c7d767 1528 */
f5bbdacc 1529 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1530 sndcmd = 1;
1da177e4
LT		 1531 }
1532
8593fbc6 1533 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1534 if (oob)
1535 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1536
f5bbdacc
TG		 1537 if (ret)
1538 return ret;
1539
9a1fcdfd
TG		 1540 if (mtd->ecc_stats.failed - stats.failed)
1541 return -EBADMSG;
1542
1543 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1544}
1545
1546/**
1547 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1548 * @mtd: MTD device structure
1549 * @from: offset to read from
1550 * @len: number of bytes to read
1551 * @retlen: pointer to variable to store the number of read bytes
1552 * @buf: the databuffer to put data
1553 *
1554 * Get hold of the chip and call nand_do_read
1555 */
1556static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1557 size_t *retlen, uint8_t *buf)
1558{
8593fbc6 1559 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1560 int ret;
1561
f5bbdacc
TG		 1562 /* Do not allow reads past end of device */
1563 if ((from + len) > mtd->size)
1564 return -EINVAL;
1565 if (!len)
1566 return 0;
1567
8593fbc6 1568 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1569
8593fbc6
TG		 1570 chip->ops.len = len;
1571 chip->ops.datbuf = buf;
1572 chip->ops.oobbuf = NULL;
1573
1574 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1575
7fd5aecc
RP		 1576 *retlen = chip->ops.retlen;
1577
f5bbdacc
TG		 1578 nand_release_device(mtd);
1579
1580 return ret;
1da177e4
LT		 1581}
1582
7bc3312b
TG		 1583/**
1584 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1585 * @mtd: mtd info structure
1586 * @chip: nand chip info structure
1587 * @page: page number to read
1588 * @sndcmd: flag whether to issue read command or not
1589 */
1590static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1591 int page, int sndcmd)
1592{
1593 if (sndcmd) {
1594 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1595 sndcmd = 0;
1596 }
1597 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1598 return sndcmd;
1599}
1600
1601/**
1602 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1603 * with syndromes
1604 * @mtd: mtd info structure
1605 * @chip: nand chip info structure
1606 * @page: page number to read
1607 * @sndcmd: flag whether to issue read command or not
1608 */
1609static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1610 int page, int sndcmd)
1611{
1612 uint8_t *buf = chip->oob_poi;
1613 int length = mtd->oobsize;
1614 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1615 int eccsize = chip->ecc.size;
1616 uint8_t *bufpoi = buf;
1617 int i, toread, sndrnd = 0, pos;
1618
1619 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1620 for (i = 0; i < chip->ecc.steps; i++) {
1621 if (sndrnd) {
1622 pos = eccsize + i * (eccsize + chunk);
1623 if (mtd->writesize > 512)
1624 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1625 else
1626 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1627 } else
1628 sndrnd = 1;
1629 toread = min_t(int, length, chunk);
1630 chip->read_buf(mtd, bufpoi, toread);
1631 bufpoi += toread;
1632 length -= toread;
1633 }
1634 if (length > 0)
1635 chip->read_buf(mtd, bufpoi, length);
1636
1637 return 1;
1638}
1639
1640/**
1641 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1642 * @mtd: mtd info structure
1643 * @chip: nand chip info structure
1644 * @page: page number to write
1645 */
1646static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1647 int page)
1648{
1649 int status = 0;
1650 const uint8_t *buf = chip->oob_poi;
1651 int length = mtd->oobsize;
1652
1653 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1654 chip->write_buf(mtd, buf, length);
1655 /* Send command to program the OOB data */
1656 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1657
1658 status = chip->waitfunc(mtd, chip);
1659
0d420f9d 1660 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1661}
1662
1663/**
1664 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1665 * with syndrome - only for large page flash !
1666 * @mtd: mtd info structure
1667 * @chip: nand chip info structure
1668 * @page: page number to write
1669 */
1670static int nand_write_oob_syndrome(struct mtd_info *mtd,
1671 struct nand_chip *chip, int page)
1672{
1673 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1674 int eccsize = chip->ecc.size, length = mtd->oobsize;
1675 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1676 const uint8_t *bufpoi = chip->oob_poi;
1677
1678 /*
1679 * data-ecc-data-ecc ... ecc-oob
1680 * or
1681 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1682 */
1683 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1684 pos = steps * (eccsize + chunk);
1685 steps = 0;
1686 } else
8b0036ee 1687 pos = eccsize;
7bc3312b
TG		 1688
1689 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1690 for (i = 0; i < steps; i++) {
1691 if (sndcmd) {
1692 if (mtd->writesize <= 512) {
1693 uint32_t fill = 0xFFFFFFFF;
1694
1695 len = eccsize;
1696 while (len > 0) {
1697 int num = min_t(int, len, 4);
1698 chip->write_buf(mtd, (uint8_t *)&fill,
1699 num);
1700 len -= num;
1701 }
1702 } else {
1703 pos = eccsize + i * (eccsize + chunk);
1704 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1705 }
1706 } else
1707 sndcmd = 1;
1708 len = min_t(int, length, chunk);
1709 chip->write_buf(mtd, bufpoi, len);
1710 bufpoi += len;
1711 length -= len;
1712 }
1713 if (length > 0)
1714 chip->write_buf(mtd, bufpoi, length);
1715
1716 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1717 status = chip->waitfunc(mtd, chip);
1718
1719 return status & NAND_STATUS_FAIL ? -EIO : 0;
1720}
1721
1da177e4 1722/**
8593fbc6 1723 * nand_do_read_oob - [Intern] NAND read out-of-band
1da177e4
LT		 1724 * @mtd: MTD device structure
1725 * @from: offset to read from
8593fbc6 1726 * @ops: oob operations description structure
1da177e4
LT		 1727 *
1728 * NAND read out-of-band data from the spare area
1729 */
8593fbc6
TG		 1730static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1731 struct mtd_oob_ops *ops)
1da177e4 1732{
7bc3312b 1733 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1734 struct nand_chip *chip = mtd->priv;
7314e9e7 1735 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1736 int readlen = ops->ooblen;
1737 int len;
7bc3312b 1738 uint8_t *buf = ops->oobbuf;
61b03bd7 1739
20d8e248 1740 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1741 __func__, (unsigned long long)from, readlen);
1da177e4 1742
03736155 1743 if (ops->mode == MTD_OOB_AUTO)
7014568b 1744 len = chip->ecc.layout->oobavail;
03736155
AH		 1745 else
1746 len = mtd->oobsize;
1747
1748 if (unlikely(ops->ooboffs >= len)) {
20d8e248 1749 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1750 "outside oob\n", __func__);
03736155
AH		 1751 return -EINVAL;
1752 }
1753
1754 /* Do not allow reads past end of device */
1755 if (unlikely(from >= mtd->size ||
1756 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1757 (from >> chip->page_shift)) * len)) {
20d8e248 1758 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1759 "of device\n", __func__);
03736155
AH		 1760 return -EINVAL;
1761 }
7014568b 1762
7314e9e7 1763 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1764 chip->select_chip(mtd, chipnr);
1da177e4 1765
7314e9e7
TG		 1766 /* Shift to get page */
1767 realpage = (int)(from >> chip->page_shift);
1768 page = realpage & chip->pagemask;
1da177e4 1769
7314e9e7 1770 while(1) {
7bc3312b 1771 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1772
1773 len = min(len, readlen);
1774 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1775
7314e9e7
TG		 1776 if (!(chip->options & NAND_NO_READRDY)) {
1777 /*
1778 * Apply delay or wait for ready/busy pin. Do this
1779 * before the AUTOINCR check, so no problems arise if a
1780 * chip which does auto increment is marked as
1781 * NOAUTOINCR by the board driver.
19870da7 1782 */
ace4dfee
TG		 1783 if (!chip->dev_ready)
1784 udelay(chip->chip_delay);
19870da7
TG		 1785 else
1786 nand_wait_ready(mtd);
7314e9e7 1787 }
19870da7 1788
7014568b 1789 readlen -= len;
0d420f9d
SZ		 1790 if (!readlen)
1791 break;
1792
7314e9e7
TG		 1793 /* Increment page address */
1794 realpage++;
1795
1796 page = realpage & chip->pagemask;
1797 /* Check, if we cross a chip boundary */
1798 if (!page) {
1799 chipnr++;
1800 chip->select_chip(mtd, -1);
1801 chip->select_chip(mtd, chipnr);
1da177e4 1802 }
7314e9e7
TG		 1803
1804 /* Check, if the chip supports auto page increment
1805 * or if we have hit a block boundary.
1806 */
1807 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1808 sndcmd = 1;
1da177e4
LT		 1809 }
1810
7014568b 1811 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1812 return 0;
1813}
1814
1815/**
8593fbc6 1816 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1da177e4 1817 * @mtd: MTD device structure
1da177e4 1818 * @from: offset to read from
8593fbc6 1819 * @ops: oob operation description structure
1da177e4 1820 *
8593fbc6 1821 * NAND read data and/or out-of-band data
1da177e4 1822 */
8593fbc6
TG		 1823static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1824 struct mtd_oob_ops *ops)
1da177e4 1825{
ace4dfee 1826 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1827 int ret = -ENOTSUPP;
1828
1829 ops->retlen = 0;
1da177e4
LT		 1830
1831 /* Do not allow reads past end of device */
7014568b 1832 if (ops->datbuf && (from + ops->len) > mtd->size) {
20d8e248 1833 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1834 "beyond end of device\n", __func__);
1da177e4
LT		 1835 return -EINVAL;
1836 }
1837
ace4dfee 1838 nand_get_device(chip, mtd, FL_READING);
1da177e4 1839
8593fbc6
TG		 1840 switch(ops->mode) {
1841 case MTD_OOB_PLACE:
1842 case MTD_OOB_AUTO:
8593fbc6 1843 case MTD_OOB_RAW:
8593fbc6 1844 break;
1da177e4 1845
8593fbc6
TG		 1846 default:
1847 goto out;
1848 }
1da177e4 1849
8593fbc6
TG		 1850 if (!ops->datbuf)
1851 ret = nand_do_read_oob(mtd, from, ops);
1852 else
1853 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1854
8593fbc6
TG		 1855 out:
1856 nand_release_device(mtd);
1857 return ret;
1858}
61b03bd7 1859
1da177e4 1860
8593fbc6
TG		 1861/**
1862 * nand_write_page_raw - [Intern] raw page write function
1863 * @mtd: mtd info structure
1864 * @chip: nand chip info structure
1865 * @buf: data buffer
52ff49df
DB		 1866 *
1867 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1868 */
1869static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1870 const uint8_t *buf)
1871{
1872 chip->write_buf(mtd, buf, mtd->writesize);
1873 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1874}
1875
52ff49df
DB		 1876/**
1877 * nand_write_page_raw_syndrome - [Intern] raw page write function
1878 * @mtd: mtd info structure
1879 * @chip: nand chip info structure
1880 * @buf: data buffer
1881 *
1882 * We need a special oob layout and handling even when ECC isn't checked.
1883 */
1884static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1885 const uint8_t *buf)
1886{
1887 int eccsize = chip->ecc.size;
1888 int eccbytes = chip->ecc.bytes;
1889 uint8_t *oob = chip->oob_poi;
1890 int steps, size;
1891
1892 for (steps = chip->ecc.steps; steps > 0; steps--) {
1893 chip->write_buf(mtd, buf, eccsize);
1894 buf += eccsize;
1895
1896 if (chip->ecc.prepad) {
1897 chip->write_buf(mtd, oob, chip->ecc.prepad);
1898 oob += chip->ecc.prepad;
1899 }
1900
1901 chip->read_buf(mtd, oob, eccbytes);
1902 oob += eccbytes;
1903
1904 if (chip->ecc.postpad) {
1905 chip->write_buf(mtd, oob, chip->ecc.postpad);
1906 oob += chip->ecc.postpad;
1907 }
1908 }
1909
1910 size = mtd->oobsize - (oob - chip->oob_poi);
1911 if (size)
1912 chip->write_buf(mtd, oob, size);
1913}
9223a456 1914/**
d29ebdbe 1915 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
f75e5097
TG		 1916 * @mtd: mtd info structure
1917 * @chip: nand chip info structure
1918 * @buf: data buffer
9223a456 1919 */
f75e5097
TG		 1920static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1921 const uint8_t *buf)
9223a456 1922{
f75e5097
TG		 1923 int i, eccsize = chip->ecc.size;
1924 int eccbytes = chip->ecc.bytes;
1925 int eccsteps = chip->ecc.steps;
4bf63fcb 1926 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1927 const uint8_t *p = buf;
8b099a39 1928 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1929
8593fbc6
TG		 1930 /* Software ecc calculation */
1931 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1932 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1933
8593fbc6
TG		 1934 for (i = 0; i < chip->ecc.total; i++)
1935 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1936
90424de8 1937 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1938}
9223a456 1939
f75e5097 1940/**
d29ebdbe 1941 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
f75e5097
TG		 1942 * @mtd: mtd info structure
1943 * @chip: nand chip info structure
1944 * @buf: data buffer
1945 */
1946static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1947 const uint8_t *buf)
1948{
1949 int i, eccsize = chip->ecc.size;
1950 int eccbytes = chip->ecc.bytes;
1951 int eccsteps = chip->ecc.steps;
4bf63fcb 1952 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1953 const uint8_t *p = buf;
8b099a39 1954 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1955
f75e5097
TG		 1956 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1957 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1958 chip->write_buf(mtd, p, eccsize);
f75e5097 1959 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1960 }
1961
f75e5097
TG		 1962 for (i = 0; i < chip->ecc.total; i++)
1963 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1964
1965 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 1966}
1967
61b03bd7 1968/**
d29ebdbe 1969 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
f75e5097
TG		 1970 * @mtd: mtd info structure
1971 * @chip: nand chip info structure
1972 * @buf: data buffer
1da177e4 1973 *
f75e5097
TG		 1974 * The hw generator calculates the error syndrome automatically. Therefor
1975 * we need a special oob layout and handling.
1976 */
1977static void nand_write_page_syndrome(struct mtd_info *mtd,
1978 struct nand_chip *chip, const uint8_t *buf)
1da177e4 1979{
f75e5097
TG		 1980 int i, eccsize = chip->ecc.size;
1981 int eccbytes = chip->ecc.bytes;
1982 int eccsteps = chip->ecc.steps;
1983 const uint8_t *p = buf;
1984 uint8_t *oob = chip->oob_poi;
1da177e4 1985
f75e5097 1986 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 1987
f75e5097
TG		 1988 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1989 chip->write_buf(mtd, p, eccsize);
61b03bd7 1990
f75e5097
TG		 1991 if (chip->ecc.prepad) {
1992 chip->write_buf(mtd, oob, chip->ecc.prepad);
1993 oob += chip->ecc.prepad;
1994 }
1995
1996 chip->ecc.calculate(mtd, p, oob);
1997 chip->write_buf(mtd, oob, eccbytes);
1998 oob += eccbytes;
1999
2000 if (chip->ecc.postpad) {
2001 chip->write_buf(mtd, oob, chip->ecc.postpad);
2002 oob += chip->ecc.postpad;
1da177e4 2003 }
1da177e4 2004 }
f75e5097
TG		 2005
2006 /* Calculate remaining oob bytes */
7e4178f9 2007 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2008 if (i)
2009 chip->write_buf(mtd, oob, i);
2010}
2011
2012/**
956e944c 2013 * nand_write_page - [REPLACEABLE] write one page
f75e5097
TG		 2014 * @mtd: MTD device structure
2015 * @chip: NAND chip descriptor
2016 * @buf: the data to write
2017 * @page: page number to write
2018 * @cached: cached programming
efbfe96c 2019 * @raw: use _raw version of write_page
f75e5097
TG		 2020 */
2021static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 2022 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 2023{
2024 int status;
2025
2026 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2027
956e944c
DW		 2028 if (unlikely(raw))
2029 chip->ecc.write_page_raw(mtd, chip, buf);
2030 else
2031 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 2032
2033 /*
2034 * Cached progamming disabled for now, Not sure if its worth the
2035 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2036 */
2037 cached = 0;
2038
2039 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2040
2041 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2042 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2043 /*
2044 * See if operation failed and additional status checks are
2045 * available
2046 */
2047 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2048 status = chip->errstat(mtd, chip, FL_WRITING, status,
2049 page);
2050
2051 if (status & NAND_STATUS_FAIL)
2052 return -EIO;
2053 } else {
2054 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2055 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2056 }
2057
2058#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2059 /* Send command to read back the data */
2060 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2061
2062 if (chip->verify_buf(mtd, buf, mtd->writesize))
2063 return -EIO;
2064#endif
2065 return 0;
1da177e4
LT		 2066}
2067
8593fbc6
TG		 2068/**
2069 * nand_fill_oob - [Internal] Transfer client buffer to oob
2070 * @chip: nand chip structure
2071 * @oob: oob data buffer
2072 * @ops: oob ops structure
2073 */
782ce79a
ML		 2074static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2075 struct mtd_oob_ops *ops)
8593fbc6 2076{
8593fbc6
TG		 2077 switch(ops->mode) {
2078
2079 case MTD_OOB_PLACE:
2080 case MTD_OOB_RAW:
2081 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2082 return oob + len;
2083
2084 case MTD_OOB_AUTO: {
2085 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2086 uint32_t boffs = 0, woffs = ops->ooboffs;
2087 size_t bytes = 0;
8593fbc6
TG		 2088
2089 for(; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 2090 /* Write request not from offset 0 ? */
2091 if (unlikely(woffs)) {
2092 if (woffs >= free->length) {
2093 woffs -= free->length;
2094 continue;
2095 }
2096 boffs = free->offset + woffs;
2097 bytes = min_t(size_t, len,
2098 (free->length - woffs));
2099 woffs = 0;
2100 } else {
2101 bytes = min_t(size_t, len, free->length);
2102 boffs = free->offset;
2103 }
8b0036ee 2104 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2105 oob += bytes;
2106 }
2107 return oob;
2108 }
2109 default:
2110 BUG();
2111 }
2112 return NULL;
2113}
2114
29072b96 2115#define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1da177e4
LT		 2116
2117/**
8593fbc6 2118 * nand_do_write_ops - [Internal] NAND write with ECC
1da177e4
LT		 2119 * @mtd: MTD device structure
2120 * @to: offset to write to
8593fbc6 2121 * @ops: oob operations description structure
1da177e4
LT		 2122 *
2123 * NAND write with ECC
2124 */
8593fbc6
TG		 2125static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2126 struct mtd_oob_ops *ops)
1da177e4 2127{
29072b96 2128 int chipnr, realpage, page, blockmask, column;
ace4dfee 2129 struct nand_chip *chip = mtd->priv;
8593fbc6 2130 uint32_t writelen = ops->len;
782ce79a
ML		 2131
2132 uint32_t oobwritelen = ops->ooblen;
2133 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2134 mtd->oobavail : mtd->oobsize;
2135
8593fbc6
TG		 2136 uint8_t *oob = ops->oobbuf;
2137 uint8_t *buf = ops->datbuf;
29072b96 2138 int ret, subpage;
1da177e4 2139
8593fbc6 2140 ops->retlen = 0;
29072b96
TG		 2141 if (!writelen)
2142 return 0;
1da177e4 2143
61b03bd7 2144 /* reject writes, which are not page aligned */
8593fbc6 2145 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
20d8e248 2146 printk(KERN_NOTICE "%s: Attempt to write not "
2147 "page aligned data\n", __func__);
1da177e4
LT		 2148 return -EINVAL;
2149 }
2150
29072b96
TG		 2151 column = to & (mtd->writesize - 1);
2152 subpage = column || (writelen & (mtd->writesize - 1));
2153
2154 if (subpage && oob)
2155 return -EINVAL;
1da177e4 2156
6a930961
TG		 2157 chipnr = (int)(to >> chip->chip_shift);
2158 chip->select_chip(mtd, chipnr);
2159
1da177e4
LT		 2160 /* Check, if it is write protected */
2161 if (nand_check_wp(mtd))
8593fbc6 2162 return -EIO;
1da177e4 2163
f75e5097
TG		 2164 realpage = (int)(to >> chip->page_shift);
2165 page = realpage & chip->pagemask;
2166 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2167
2168 /* Invalidate the page cache, when we write to the cached page */
2169 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2170 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2171 chip->pagebuf = -1;
61b03bd7 2172
7dcdcbef
DW		 2173 /* If we're not given explicit OOB data, let it be 0xFF */
2174 if (likely(!oob))
2175 memset(chip->oob_poi, 0xff, mtd->oobsize);
61b03bd7 2176
782ce79a
ML		 2177 /* Don't allow multipage oob writes with offset */
2178 if (ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2179 return -EINVAL;
2180
f75e5097 2181 while(1) {
29072b96 2182 int bytes = mtd->writesize;
f75e5097 2183 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2184 uint8_t *wbuf = buf;
2185
2186 /* Partial page write ? */
2187 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2188 cached = 0;
2189 bytes = min_t(int, bytes - column, (int) writelen);
2190 chip->pagebuf = -1;
2191 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2192 memcpy(&chip->buffers->databuf[column], buf, bytes);
2193 wbuf = chip->buffers->databuf;
2194 }
1da177e4 2195
782ce79a
ML		 2196 if (unlikely(oob)) {
2197 size_t len = min(oobwritelen, oobmaxlen);
2198 oob = nand_fill_oob(chip, oob, len, ops);
2199 oobwritelen -= len;
2200 }
8593fbc6 2201
29072b96 2202 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 2203 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 2204 if (ret)
2205 break;
2206
2207 writelen -= bytes;
2208 if (!writelen)
2209 break;
2210
29072b96 2211 column = 0;
f75e5097
TG		 2212 buf += bytes;
2213 realpage++;
2214
2215 page = realpage & chip->pagemask;
2216 /* Check, if we cross a chip boundary */
2217 if (!page) {
2218 chipnr++;
2219 chip->select_chip(mtd, -1);
2220 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2221 }
2222 }
8593fbc6 2223
8593fbc6 2224 ops->retlen = ops->len - writelen;
7014568b
VW		 2225 if (unlikely(oob))
2226 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2227 return ret;
2228}
2229
2af7c653
SK		 2230/**
2231 * panic_nand_write - [MTD Interface] NAND write with ECC
2232 * @mtd: MTD device structure
2233 * @to: offset to write to
2234 * @len: number of bytes to write
2235 * @retlen: pointer to variable to store the number of written bytes
2236 * @buf: the data to write
2237 *
2238 * NAND write with ECC. Used when performing writes in interrupt context, this
2239 * may for example be called by mtdoops when writing an oops while in panic.
2240 */
2241static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2242 size_t *retlen, const uint8_t *buf)
2243{
2244 struct nand_chip *chip = mtd->priv;
2245 int ret;
2246
2247 /* Do not allow reads past end of device */
2248 if ((to + len) > mtd->size)
2249 return -EINVAL;
2250 if (!len)
2251 return 0;
2252
2253 /* Wait for the device to get ready. */
2254 panic_nand_wait(mtd, chip, 400);
2255
2256 /* Grab the device. */
2257 panic_nand_get_device(chip, mtd, FL_WRITING);
2258
2259 chip->ops.len = len;
2260 chip->ops.datbuf = (uint8_t *)buf;
2261 chip->ops.oobbuf = NULL;
2262
2263 ret = nand_do_write_ops(mtd, to, &chip->ops);
2264
2265 *retlen = chip->ops.retlen;
2266 return ret;
2267}
2268
f75e5097 2269/**
8593fbc6 2270 * nand_write - [MTD Interface] NAND write with ECC
f75e5097 2271 * @mtd: MTD device structure
f75e5097
TG		 2272 * @to: offset to write to
2273 * @len: number of bytes to write
8593fbc6
TG		 2274 * @retlen: pointer to variable to store the number of written bytes
2275 * @buf: the data to write
f75e5097 2276 *
8593fbc6 2277 * NAND write with ECC
f75e5097 2278 */
8593fbc6
TG		 2279static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2280 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2281{
2282 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 2283 int ret;
2284
8593fbc6
TG		 2285 /* Do not allow reads past end of device */
2286 if ((to + len) > mtd->size)
f75e5097 2287 return -EINVAL;
8593fbc6
TG		 2288 if (!len)
2289 return 0;
f75e5097 2290
7bc3312b 2291 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 2292
8593fbc6
TG		 2293 chip->ops.len = len;
2294 chip->ops.datbuf = (uint8_t *)buf;
2295 chip->ops.oobbuf = NULL;
f75e5097 2296
8593fbc6 2297 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 2298
7fd5aecc
RP		 2299 *retlen = chip->ops.retlen;
2300
f75e5097 2301 nand_release_device(mtd);
8593fbc6 2302
8593fbc6 2303 return ret;
f75e5097 2304}
7314e9e7 2305
1da177e4 2306/**
8593fbc6 2307 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1da177e4
LT		 2308 * @mtd: MTD device structure
2309 * @to: offset to write to
8593fbc6 2310 * @ops: oob operation description structure
1da177e4
LT		 2311 *
2312 * NAND write out-of-band
2313 */
8593fbc6
TG		 2314static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2315 struct mtd_oob_ops *ops)
1da177e4 2316{
03736155 2317 int chipnr, page, status, len;
ace4dfee 2318 struct nand_chip *chip = mtd->priv;
1da177e4 2319
20d8e248 2320 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2321 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2322
03736155
AH		 2323 if (ops->mode == MTD_OOB_AUTO)
2324 len = chip->ecc.layout->oobavail;
2325 else
2326 len = mtd->oobsize;
2327
1da177e4 2328 /* Do not allow write past end of page */
03736155 2329 if ((ops->ooboffs + ops->ooblen) > len) {
20d8e248 2330 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2331 "past end of page\n", __func__);
1da177e4
LT		 2332 return -EINVAL;
2333 }
2334
03736155 2335 if (unlikely(ops->ooboffs >= len)) {
20d8e248 2336 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2337 "write outside oob\n", __func__);
03736155
AH		 2338 return -EINVAL;
2339 }
2340
2341 /* Do not allow reads past end of device */
2342 if (unlikely(to >= mtd->size ||
2343 ops->ooboffs + ops->ooblen >
2344 ((mtd->size >> chip->page_shift) -
2345 (to >> chip->page_shift)) * len)) {
20d8e248 2346 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2347 "end of device\n", __func__);
03736155
AH		 2348 return -EINVAL;
2349 }
2350
7314e9e7 2351 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2352 chip->select_chip(mtd, chipnr);
1da177e4 2353
7314e9e7
TG		 2354 /* Shift to get page */
2355 page = (int)(to >> chip->page_shift);
2356
2357 /*
2358 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2359 * of my DiskOnChip 2000 test units) will clear the whole data page too
2360 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2361 * it in the doc2000 driver in August 1999. dwmw2.
2362 */
ace4dfee 2363 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2364
2365 /* Check, if it is write protected */
2366 if (nand_check_wp(mtd))
8593fbc6 2367 return -EROFS;
61b03bd7 2368
1da177e4 2369 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2370 if (page == chip->pagebuf)
2371 chip->pagebuf = -1;
1da177e4 2372
7bc3312b 2373 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2374 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
7bc3312b
TG		 2375 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2376 memset(chip->oob_poi, 0xff, mtd->oobsize);
1da177e4 2377
7bc3312b
TG		 2378 if (status)
2379 return status;
1da177e4 2380
7014568b 2381 ops->oobretlen = ops->ooblen;
1da177e4 2382
7bc3312b 2383 return 0;
8593fbc6
TG		 2384}
2385
2386/**
2387 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2388 * @mtd: MTD device structure
844d3b42 2389 * @to: offset to write to
8593fbc6
TG		 2390 * @ops: oob operation description structure
2391 */
2392static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2393 struct mtd_oob_ops *ops)
2394{
8593fbc6
TG		 2395 struct nand_chip *chip = mtd->priv;
2396 int ret = -ENOTSUPP;
2397
2398 ops->retlen = 0;
2399
2400 /* Do not allow writes past end of device */
7014568b 2401 if (ops->datbuf && (to + ops->len) > mtd->size) {
20d8e248 2402 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2403 "end of device\n", __func__);
8593fbc6
TG		 2404 return -EINVAL;
2405 }
2406
7bc3312b 2407 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6
TG		 2408
2409 switch(ops->mode) {
2410 case MTD_OOB_PLACE:
2411 case MTD_OOB_AUTO:
8593fbc6 2412 case MTD_OOB_RAW:
8593fbc6
TG		 2413 break;
2414
2415 default:
2416 goto out;
2417 }
2418
2419 if (!ops->datbuf)
2420 ret = nand_do_write_oob(mtd, to, ops);
2421 else
2422 ret = nand_do_write_ops(mtd, to, ops);
2423
e0c7d767 2424 out:
1da177e4 2425 nand_release_device(mtd);
1da177e4
LT		 2426 return ret;
2427}
2428
1da177e4
LT		 2429/**
2430 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2431 * @mtd: MTD device structure
2432 * @page: the page address of the block which will be erased
2433 *
2434 * Standard erase command for NAND chips
2435 */
e0c7d767 2436static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2437{
ace4dfee 2438 struct nand_chip *chip = mtd->priv;
1da177e4 2439 /* Send commands to erase a block */
ace4dfee
TG		 2440 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2441 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2442}
2443
2444/**
2445 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2446 * @mtd: MTD device structure
2447 * @page: the page address of the block which will be erased
2448 *
2449 * AND multi block erase command function
2450 * Erase 4 consecutive blocks
2451 */
e0c7d767 2452static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2453{
ace4dfee 2454 struct nand_chip *chip = mtd->priv;
1da177e4 2455 /* Send commands to erase a block */
ace4dfee
TG		 2456 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2457 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2458 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2459 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2460 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2461}
2462
2463/**
2464 * nand_erase - [MTD Interface] erase block(s)
2465 * @mtd: MTD device structure
2466 * @instr: erase instruction
2467 *
2468 * Erase one ore more blocks
2469 */
e0c7d767 2470static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2471{
e0c7d767 2472 return nand_erase_nand(mtd, instr, 0);
1da177e4 2473}
61b03bd7 2474
30f464b7 2475#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2476/**
ace4dfee 2477 * nand_erase_nand - [Internal] erase block(s)
1da177e4
LT		 2478 * @mtd: MTD device structure
2479 * @instr: erase instruction
2480 * @allowbbt: allow erasing the bbt area
2481 *
2482 * Erase one ore more blocks
2483 */
ace4dfee
TG		 2484int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2485 int allowbbt)
1da177e4 2486{
69423d99 2487 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2488 struct nand_chip *chip = mtd->priv;
69423d99 2489 loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
ace4dfee 2490 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2491 loff_t len;
1da177e4 2492
20d8e248 2493 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2494 __func__, (unsigned long long)instr->addr,
2495 (unsigned long long)instr->len);
1da177e4 2496
6fe5a6ac 2497 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2498 return -EINVAL;
1da177e4 2499
bb0eb217 2500 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2501
2502 /* Grab the lock and see if the device is available */
ace4dfee 2503 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2504
2505 /* Shift to get first page */
ace4dfee
TG		 2506 page = (int)(instr->addr >> chip->page_shift);
2507 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2508
2509 /* Calculate pages in each block */
ace4dfee 2510 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2511
2512 /* Select the NAND device */
ace4dfee 2513 chip->select_chip(mtd, chipnr);
1da177e4 2514
1da177e4
LT		 2515 /* Check, if it is write protected */
2516 if (nand_check_wp(mtd)) {
20d8e248 2517 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2518 __func__);
1da177e4
LT		 2519 instr->state = MTD_ERASE_FAILED;
2520 goto erase_exit;
2521 }
2522
ace4dfee
TG		 2523 /*
2524 * If BBT requires refresh, set the BBT page mask to see if the BBT
2525 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2526 * can not be matched. This is also done when the bbt is actually
2527 * erased to avoid recusrsive updates
2528 */
2529 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2530 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2531
1da177e4
LT		 2532 /* Loop through the pages */
2533 len = instr->len;
2534
2535 instr->state = MTD_ERASING;
2536
2537 while (len) {
ace4dfee
TG		 2538 /*
2539 * heck if we have a bad block, we do not erase bad blocks !
2540 */
2541 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2542 chip->page_shift, 0, allowbbt)) {
20d8e248 2543 printk(KERN_WARNING "%s: attempt to erase a bad block "
2544 "at page 0x%08x\n", __func__, page);
1da177e4
LT		 2545 instr->state = MTD_ERASE_FAILED;
2546 goto erase_exit;
2547 }
61b03bd7 2548
ace4dfee
TG		 2549 /*
2550 * Invalidate the page cache, if we erase the block which
2551 * contains the current cached page
2552 */
2553 if (page <= chip->pagebuf && chip->pagebuf <
2554 (page + pages_per_block))
2555 chip->pagebuf = -1;
1da177e4 2556
ace4dfee 2557 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2558
7bc3312b 2559 status = chip->waitfunc(mtd, chip);
1da177e4 2560
ace4dfee
TG		 2561 /*
2562 * See if operation failed and additional status checks are
2563 * available
2564 */
2565 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2566 status = chip->errstat(mtd, chip, FL_ERASING,
2567 status, page);
068e3c0a 2568
1da177e4 2569 /* See if block erase succeeded */
a4ab4c5d 2570 if (status & NAND_STATUS_FAIL) {
20d8e248 2571 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2572 "page 0x%08x\n", __func__, page);
1da177e4 2573 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2574 instr->fail_addr =
2575 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2576 goto erase_exit;
2577 }
30f464b7 2578
ace4dfee
TG		 2579 /*
2580 * If BBT requires refresh, set the BBT rewrite flag to the
2581 * page being erased
2582 */
2583 if (bbt_masked_page != 0xffffffff &&
2584 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2585 rewrite_bbt[chipnr] =
2586 ((loff_t)page << chip->page_shift);
61b03bd7 2587
1da177e4 2588 /* Increment page address and decrement length */
ace4dfee 2589 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2590 page += pages_per_block;
2591
2592 /* Check, if we cross a chip boundary */
ace4dfee 2593 if (len && !(page & chip->pagemask)) {
1da177e4 2594 chipnr++;
ace4dfee
TG		 2595 chip->select_chip(mtd, -1);
2596 chip->select_chip(mtd, chipnr);
30f464b7 2597
ace4dfee
TG		 2598 /*
2599 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2600 * page mask to see if this BBT should be rewritten
2601 */
2602 if (bbt_masked_page != 0xffffffff &&
2603 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2604 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2605 BBT_PAGE_MASK;
1da177e4
LT		 2606 }
2607 }
2608 instr->state = MTD_ERASE_DONE;
2609
e0c7d767 2610 erase_exit:
1da177e4
LT		 2611
2612 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2613
2614 /* Deselect and wake up anyone waiting on the device */
2615 nand_release_device(mtd);
2616
49defc01
DW		 2617 /* Do call back function */
2618 if (!ret)
2619 mtd_erase_callback(instr);
2620
ace4dfee
TG		 2621 /*
2622 * If BBT requires refresh and erase was successful, rewrite any
2623 * selected bad block tables
2624 */
2625 if (bbt_masked_page == 0xffffffff || ret)
2626 return ret;
2627
2628 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2629 if (!rewrite_bbt[chipnr])
2630 continue;
2631 /* update the BBT for chip */
20d8e248 2632 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2633 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2634 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
ace4dfee 2635 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2636 }
2637
1da177e4
LT		 2638 /* Return more or less happy */
2639 return ret;
2640}
2641
2642/**
2643 * nand_sync - [MTD Interface] sync
2644 * @mtd: MTD device structure
2645 *
2646 * Sync is actually a wait for chip ready function
2647 */
e0c7d767 2648static void nand_sync(struct mtd_info *mtd)
1da177e4 2649{
ace4dfee 2650 struct nand_chip *chip = mtd->priv;
1da177e4 2651
20d8e248 2652 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
1da177e4
LT		 2653
2654 /* Grab the lock and see if the device is available */
ace4dfee 2655 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2656 /* Release it and go back */
e0c7d767 2657 nand_release_device(mtd);
1da177e4
LT		 2658}
2659
1da177e4 2660/**
ace4dfee 2661 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1da177e4 2662 * @mtd: MTD device structure
844d3b42 2663 * @offs: offset relative to mtd start
1da177e4 2664 */
ace4dfee 2665static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2666{
2667 /* Check for invalid offset */
ace4dfee 2668 if (offs > mtd->size)
1da177e4 2669 return -EINVAL;
61b03bd7 2670
ace4dfee 2671 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2672}
2673
2674/**
ace4dfee 2675 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1da177e4
LT		 2676 * @mtd: MTD device structure
2677 * @ofs: offset relative to mtd start
2678 */
e0c7d767 2679static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2680{
ace4dfee 2681 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2682 int ret;
2683
e0c7d767
DW		 2684 if ((ret = nand_block_isbad(mtd, ofs))) {
2685 /* If it was bad already, return success and do nothing. */
1da177e4
LT		 2686 if (ret > 0)
2687 return 0;
e0c7d767
DW		 2688 return ret;
2689 }
1da177e4 2690
ace4dfee 2691 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2692}
2693
962034f4
VW		 2694/**
2695 * nand_suspend - [MTD Interface] Suspend the NAND flash
2696 * @mtd: MTD device structure
2697 */
2698static int nand_suspend(struct mtd_info *mtd)
2699{
ace4dfee 2700 struct nand_chip *chip = mtd->priv;
962034f4 2701
ace4dfee 2702 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2703}
2704
2705/**
2706 * nand_resume - [MTD Interface] Resume the NAND flash
2707 * @mtd: MTD device structure
2708 */
2709static void nand_resume(struct mtd_info *mtd)
2710{
ace4dfee 2711 struct nand_chip *chip = mtd->priv;
962034f4 2712
ace4dfee 2713 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2714 nand_release_device(mtd);
2715 else
20d8e248 2716 printk(KERN_ERR "%s called for a chip which is not "
2717 "in suspended state\n", __func__);
962034f4
VW		 2718}
2719
7aa65bfd
TG		 2720/*
2721 * Set default functions
2722 */
ace4dfee 2723static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2724{
1da177e4 2725 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2726 if (!chip->chip_delay)
2727 chip->chip_delay = 20;
1da177e4
LT		 2728
2729 /* check, if a user supplied command function given */
ace4dfee
TG		 2730 if (chip->cmdfunc == NULL)
2731 chip->cmdfunc = nand_command;
1da177e4
LT		 2732
2733 /* check, if a user supplied wait function given */
ace4dfee
TG		 2734 if (chip->waitfunc == NULL)
2735 chip->waitfunc = nand_wait;
2736
2737 if (!chip->select_chip)
2738 chip->select_chip = nand_select_chip;
2739 if (!chip->read_byte)
2740 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2741 if (!chip->read_word)
2742 chip->read_word = nand_read_word;
2743 if (!chip->block_bad)
2744 chip->block_bad = nand_block_bad;
2745 if (!chip->block_markbad)
2746 chip->block_markbad = nand_default_block_markbad;
2747 if (!chip->write_buf)
2748 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2749 if (!chip->read_buf)
2750 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2751 if (!chip->verify_buf)
2752 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2753 if (!chip->scan_bbt)
2754 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2755
2756 if (!chip->controller) {
2757 chip->controller = &chip->hwcontrol;
2758 spin_lock_init(&chip->controller->lock);
2759 init_waitqueue_head(&chip->controller->wq);
2760 }
2761
7aa65bfd
TG		 2762}
2763
2764/*
ace4dfee 2765 * Get the flash and manufacturer id and lookup if the type is supported
7aa65bfd
TG		 2766 */
2767static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2768 struct nand_chip *chip,
5e81e88a
DW		 2769 int busw, int *maf_id,
2770 struct nand_flash_dev *type)
7aa65bfd 2771{
5e81e88a 2772 int dev_id, maf_idx;
ed8165c7 2773 int tmp_id, tmp_manf;
1da177e4
LT		 2774
2775 /* Select the device */
ace4dfee 2776 chip->select_chip(mtd, 0);
1da177e4 2777
ef89a880
KB		 2778 /*
2779 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2780 * after power-up
2781 */
2782 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2783
1da177e4 2784 /* Send the command for reading device ID */
ace4dfee 2785 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2786
2787 /* Read manufacturer and device IDs */
ace4dfee
TG		 2788 *maf_id = chip->read_byte(mtd);
2789 dev_id = chip->read_byte(mtd);
1da177e4 2790
ed8165c7
BD		 2791 /* Try again to make sure, as some systems the bus-hold or other
2792 * interface concerns can cause random data which looks like a
2793 * possibly credible NAND flash to appear. If the two results do
2794 * not match, ignore the device completely.
2795 */
2796
2797 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2798
2799 /* Read manufacturer and device IDs */
2800
2801 tmp_manf = chip->read_byte(mtd);
2802 tmp_id = chip->read_byte(mtd);
2803
2804 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2805 printk(KERN_INFO "%s: second ID read did not match "
2806 "%02x,%02x against %02x,%02x\n", __func__,
2807 *maf_id, dev_id, tmp_manf, tmp_id);
2808 return ERR_PTR(-ENODEV);
2809 }
2810
7aa65bfd 2811 if (!type)
5e81e88a
DW		 2812 type = nand_flash_ids;
2813
2814 for (; type->name != NULL; type++)
2815 if (dev_id == type->id)
2816 break;
2817
2818 if (!type->name)
7aa65bfd
TG		 2819 return ERR_PTR(-ENODEV);
2820
ba0251fe
TG		 2821 if (!mtd->name)
2822 mtd->name = type->name;
2823
69423d99 2824 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd
TG		 2825
2826 /* Newer devices have all the information in additional id bytes */
ba0251fe 2827 if (!type->pagesize) {
7aa65bfd 2828 int extid;
29072b96
TG		 2829 /* The 3rd id byte holds MLC / multichip data */
2830 chip->cellinfo = chip->read_byte(mtd);
7aa65bfd 2831 /* The 4th id byte is the important one */
ace4dfee 2832 extid = chip->read_byte(mtd);
7aa65bfd 2833 /* Calc pagesize */
4cbb9b80 2834 mtd->writesize = 1024 << (extid & 0x3);
7aa65bfd
TG		 2835 extid >>= 2;
2836 /* Calc oobsize */
4cbb9b80 2837 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
7aa65bfd
TG		 2838 extid >>= 2;
2839 /* Calc blocksize. Blocksize is multiples of 64KiB */
2840 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2841 extid >>= 2;
2842 /* Get buswidth information */
2843 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
61b03bd7 2844
7aa65bfd
TG		 2845 } else {
2846 /*
ace4dfee 2847 * Old devices have chip data hardcoded in the device id table
7aa65bfd 2848 */
ba0251fe
TG		 2849 mtd->erasesize = type->erasesize;
2850 mtd->writesize = type->pagesize;
4cbb9b80 2851 mtd->oobsize = mtd->writesize / 32;
ba0251fe 2852 busw = type->options & NAND_BUSWIDTH_16;
7aa65bfd 2853 }
1da177e4 2854
7aa65bfd 2855 /* Try to identify manufacturer */
9a909867 2856 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 2857 if (nand_manuf_ids[maf_idx].id == *maf_id)
2858 break;
2859 }
0ea4a755 2860
7aa65bfd
TG		 2861 /*
2862 * Check, if buswidth is correct. Hardware drivers should set
ace4dfee 2863 * chip correct !
7aa65bfd 2864 */
ace4dfee 2865 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
7aa65bfd
TG		 2866 printk(KERN_INFO "NAND device: Manufacturer ID:"
2867 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2868 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2869 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
ace4dfee 2870 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
7aa65bfd
TG		 2871 busw ? 16 : 8);
2872 return ERR_PTR(-EINVAL);
2873 }
61b03bd7 2874
7aa65bfd 2875 /* Calculate the address shift from the page size */
ace4dfee 2876 chip->page_shift = ffs(mtd->writesize) - 1;
7aa65bfd 2877 /* Convert chipsize to number of pages per chip -1. */
ace4dfee 2878 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 2879
ace4dfee 2880 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 2881 ffs(mtd->erasesize) - 1;
69423d99
AH		 2882 if (chip->chipsize & 0xffffffff)
2883 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2884 else
2885 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
1da177e4 2886
7aa65bfd 2887 /* Set the bad block position */
ace4dfee 2888 chip->badblockpos = mtd->writesize > 512 ?
7aa65bfd 2889 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
e0b58d0a 2890 chip->badblockbits = 8;
61b03bd7 2891
7aa65bfd 2892 /* Get chip options, preserve non chip based options */
ace4dfee 2893 chip->options &= ~NAND_CHIPOPTIONS_MSK;
ba0251fe 2894 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
7aa65bfd
TG		 2895
2896 /*
ace4dfee 2897 * Set chip as a default. Board drivers can override it, if necessary
7aa65bfd 2898 */
ace4dfee 2899 chip->options |= NAND_NO_AUTOINCR;
7aa65bfd 2900
ace4dfee 2901 /* Check if chip is a not a samsung device. Do not clear the
7aa65bfd
TG		 2902 * options for chips which are not having an extended id.
2903 */
ba0251fe 2904 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
ace4dfee 2905 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
7aa65bfd
TG		 2906
2907 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 2908 if (chip->options & NAND_4PAGE_ARRAY)
2909 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 2910 else
ace4dfee 2911 chip->erase_cmd = single_erase_cmd;
7aa65bfd
TG		 2912
2913 /* Do not replace user supplied command function ! */
ace4dfee
TG		 2914 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2915 chip->cmdfunc = nand_command_lp;
7aa65bfd
TG		 2916
2917 printk(KERN_INFO "NAND device: Manufacturer ID:"
2918 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2919 nand_manuf_ids[maf_idx].name, type->name);
2920
2921 return type;
2922}
2923
7aa65bfd 2924/**
3b85c321
DW		 2925 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2926 * @mtd: MTD device structure
2927 * @maxchips: Number of chips to scan for
5e81e88a 2928 * @table: Alternative NAND ID table
7aa65bfd 2929 *
3b85c321
DW		 2930 * This is the first phase of the normal nand_scan() function. It
2931 * reads the flash ID and sets up MTD fields accordingly.
7aa65bfd 2932 *
3b85c321 2933 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 2934 */
5e81e88a
DW		 2935int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2936 struct nand_flash_dev *table)
7aa65bfd
TG		 2937{
2938 int i, busw, nand_maf_id;
ace4dfee 2939 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 2940 struct nand_flash_dev *type;
2941
7aa65bfd 2942 /* Get buswidth to select the correct functions */
ace4dfee 2943 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 2944 /* Set the default functions */
ace4dfee 2945 nand_set_defaults(chip, busw);
7aa65bfd
TG		 2946
2947 /* Read the flash type */
5e81e88a 2948 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, table);
7aa65bfd
TG		 2949
2950 if (IS_ERR(type)) {
b1c6e6db
BD		 2951 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
2952 printk(KERN_WARNING "No NAND device found.\n");
ace4dfee 2953 chip->select_chip(mtd, -1);
7aa65bfd 2954 return PTR_ERR(type);
1da177e4
LT		 2955 }
2956
7aa65bfd 2957 /* Check for a chip array */
e0c7d767 2958 for (i = 1; i < maxchips; i++) {
ace4dfee 2959 chip->select_chip(mtd, i);
ef89a880
KB		 2960 /* See comment in nand_get_flash_type for reset */
2961 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 2962 /* Send the command for reading device ID */
ace4dfee 2963 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 2964 /* Read manufacturer and device IDs */
ace4dfee
TG		 2965 if (nand_maf_id != chip->read_byte(mtd) ||
2966 type->id != chip->read_byte(mtd))
1da177e4
LT		 2967 break;
2968 }
2969 if (i > 1)
2970 printk(KERN_INFO "%d NAND chips detected\n", i);
61b03bd7 2971
1da177e4 2972 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 2973 chip->numchips = i;
2974 mtd->size = i * chip->chipsize;
7aa65bfd 2975
3b85c321
DW		 2976 return 0;
2977}
2978
2979
2980/**
2981 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2982 * @mtd: MTD device structure
3b85c321
DW		 2983 *
2984 * This is the second phase of the normal nand_scan() function. It
2985 * fills out all the uninitialized function pointers with the defaults
2986 * and scans for a bad block table if appropriate.
2987 */
2988int nand_scan_tail(struct mtd_info *mtd)
2989{
2990 int i;
2991 struct nand_chip *chip = mtd->priv;
2992
4bf63fcb
DW		 2993 if (!(chip->options & NAND_OWN_BUFFERS))
2994 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2995 if (!chip->buffers)
2996 return -ENOMEM;
2997
7dcdcbef 2998 /* Set the internal oob buffer location, just after the page data */
784f4d5e 2999 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3000
7aa65bfd
TG		 3001 /*
3002 * If no default placement scheme is given, select an appropriate one
3003 */
5bd34c09 3004 if (!chip->ecc.layout) {
61b03bd7 3005 switch (mtd->oobsize) {
1da177e4 3006 case 8:
5bd34c09 3007 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3008 break;
3009 case 16:
5bd34c09 3010 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3011 break;
3012 case 64:
5bd34c09 3013 chip->ecc.layout = &nand_oob_64;
1da177e4 3014 break;
81ec5364
TG		 3015 case 128:
3016 chip->ecc.layout = &nand_oob_128;
3017 break;
1da177e4 3018 default:
7aa65bfd
TG		 3019 printk(KERN_WARNING "No oob scheme defined for "
3020 "oobsize %d\n", mtd->oobsize);
1da177e4
LT		 3021 BUG();
3022 }
3023 }
61b03bd7 3024
956e944c
DW		 3025 if (!chip->write_page)
3026 chip->write_page = nand_write_page;
3027
61b03bd7 3028 /*
7aa65bfd
TG		 3029 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3030 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3031 */
956e944c 3032
ace4dfee 3033 switch (chip->ecc.mode) {
6e0cb135
SN		 3034 case NAND_ECC_HW_OOB_FIRST:
3035 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3036 if (!chip->ecc.calculate || !chip->ecc.correct ||
3037 !chip->ecc.hwctl) {
3038 printk(KERN_WARNING "No ECC functions supplied; "
3039 "Hardware ECC not possible\n");
3040 BUG();
3041 }
3042 if (!chip->ecc.read_page)
3043 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3044
6dfc6d25 3045 case NAND_ECC_HW:
f5bbdacc
TG		 3046 /* Use standard hwecc read page function ? */
3047 if (!chip->ecc.read_page)
3048 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3049 if (!chip->ecc.write_page)
3050 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3051 if (!chip->ecc.read_page_raw)
3052 chip->ecc.read_page_raw = nand_read_page_raw;
3053 if (!chip->ecc.write_page_raw)
3054 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3055 if (!chip->ecc.read_oob)
3056 chip->ecc.read_oob = nand_read_oob_std;
3057 if (!chip->ecc.write_oob)
3058 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3059
6dfc6d25 3060 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3061 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3062 !chip->ecc.hwctl) &&
3063 (!chip->ecc.read_page ||
1c45f604 3064 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3065 !chip->ecc.write_page ||
1c45f604 3066 chip->ecc.write_page == nand_write_page_hwecc)) {
6e0cb135 3067 printk(KERN_WARNING "No ECC functions supplied; "
6dfc6d25
TG		 3068 "Hardware ECC not possible\n");
3069 BUG();
3070 }
f75e5097 3071 /* Use standard syndrome read/write page function ? */
f5bbdacc
TG		 3072 if (!chip->ecc.read_page)
3073 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3074 if (!chip->ecc.write_page)
3075 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3076 if (!chip->ecc.read_page_raw)
3077 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3078 if (!chip->ecc.write_page_raw)
3079 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3080 if (!chip->ecc.read_oob)
3081 chip->ecc.read_oob = nand_read_oob_syndrome;
3082 if (!chip->ecc.write_oob)
3083 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3084
ace4dfee 3085 if (mtd->writesize >= chip->ecc.size)
6dfc6d25
TG		 3086 break;
3087 printk(KERN_WARNING "%d byte HW ECC not possible on "
3088 "%d byte page size, fallback to SW ECC\n",
ace4dfee
TG		 3089 chip->ecc.size, mtd->writesize);
3090 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3091
6dfc6d25 3092 case NAND_ECC_SOFT:
ace4dfee
TG		 3093 chip->ecc.calculate = nand_calculate_ecc;
3094 chip->ecc.correct = nand_correct_data;
f5bbdacc 3095 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3096 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3097 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3098 chip->ecc.read_page_raw = nand_read_page_raw;
3099 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3100 chip->ecc.read_oob = nand_read_oob_std;
3101 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3102 if (!chip->ecc.size)
3103 chip->ecc.size = 256;
ace4dfee 3104 chip->ecc.bytes = 3;
1da177e4 3105 break;
61b03bd7
TG		 3106
3107 case NAND_ECC_NONE:
7aa65bfd
TG		 3108 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3109 "This is not recommended !!\n");
8593fbc6
TG		 3110 chip->ecc.read_page = nand_read_page_raw;
3111 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3112 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3113 chip->ecc.read_page_raw = nand_read_page_raw;
3114 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3115 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3116 chip->ecc.size = mtd->writesize;
3117 chip->ecc.bytes = 0;
1da177e4 3118 break;
956e944c 3119
1da177e4 3120 default:
7aa65bfd 3121 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
ace4dfee 3122 chip->ecc.mode);
61b03bd7 3123 BUG();
1da177e4 3124 }
61b03bd7 3125
5bd34c09
TG		 3126 /*
3127 * The number of bytes available for a client to place data into
3128 * the out of band area
3129 */
3130 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3131 for (i = 0; chip->ecc.layout->oobfree[i].length
3132 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3133 chip->ecc.layout->oobavail +=
3134 chip->ecc.layout->oobfree[i].length;
1f92267c 3135 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3136
7aa65bfd
TG		 3137 /*
3138 * Set the number of read / write steps for one page depending on ECC
3139 * mode
3140 */
ace4dfee
TG		 3141 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3142 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
6dfc6d25
TG		 3143 printk(KERN_WARNING "Invalid ecc parameters\n");
3144 BUG();
1da177e4 3145 }
f5bbdacc 3146 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3147
29072b96
TG		 3148 /*
3149 * Allow subpage writes up to ecc.steps. Not possible for MLC
3150 * FLASH.
3151 */
3152 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3153 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3154 switch(chip->ecc.steps) {
3155 case 2:
3156 mtd->subpage_sft = 1;
3157 break;
3158 case 4:
3159 case 8:
81ec5364 3160 case 16:
29072b96
TG		 3161 mtd->subpage_sft = 2;
3162 break;
3163 }
3164 }
3165 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3166
04bbd0ea 3167 /* Initialize state */
ace4dfee 3168 chip->state = FL_READY;
1da177e4
LT		 3169
3170 /* De-select the device */
ace4dfee 3171 chip->select_chip(mtd, -1);
1da177e4
LT		 3172
3173 /* Invalidate the pagebuffer reference */
ace4dfee 3174 chip->pagebuf = -1;
1da177e4
LT		 3175
3176 /* Fill in remaining MTD driver data */
3177 mtd->type = MTD_NANDFLASH;
5fa43394 3178 mtd->flags = MTD_CAP_NANDFLASH;
1da177e4
LT		 3179 mtd->erase = nand_erase;
3180 mtd->point = NULL;
3181 mtd->unpoint = NULL;
3182 mtd->read = nand_read;
3183 mtd->write = nand_write;
2af7c653 3184 mtd->panic_write = panic_nand_write;
1da177e4
LT		 3185 mtd->read_oob = nand_read_oob;
3186 mtd->write_oob = nand_write_oob;
1da177e4
LT		 3187 mtd->sync = nand_sync;
3188 mtd->lock = NULL;
3189 mtd->unlock = NULL;
962034f4
VW		 3190 mtd->suspend = nand_suspend;
3191 mtd->resume = nand_resume;
1da177e4
LT		 3192 mtd->block_isbad = nand_block_isbad;
3193 mtd->block_markbad = nand_block_markbad;
3194
5bd34c09
TG		 3195 /* propagate ecc.layout to mtd_info */
3196 mtd->ecclayout = chip->ecc.layout;
1da177e4 3197
0040bf38 3198 /* Check, if we should skip the bad block table scan */
ace4dfee 3199 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3200 return 0;
1da177e4
LT		 3201
3202 /* Build bad block table */
ace4dfee 3203 return chip->scan_bbt(mtd);
1da177e4
LT		 3204}
3205
a6e6abd5 3206/* is_module_text_address() isn't exported, and it's mostly a pointless
3b85c321
DW		 3207 test if this is a module _anyway_ -- they'd have to try _really_ hard
3208 to call us from in-kernel code if the core NAND support is modular. */
3209#ifdef MODULE
3210#define caller_is_module() (1)
3211#else
3212#define caller_is_module() \
a6e6abd5 3213 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3214#endif
3215
3216/**
3217 * nand_scan - [NAND Interface] Scan for the NAND device
3218 * @mtd: MTD device structure
3219 * @maxchips: Number of chips to scan for
3220 *
3221 * This fills out all the uninitialized function pointers
3222 * with the defaults.
3223 * The flash ID is read and the mtd/chip structures are
3224 * filled with the appropriate values.
3225 * The mtd->owner field must be set to the module of the caller
3226 *
3227 */
3228int nand_scan(struct mtd_info *mtd, int maxchips)
3229{
3230 int ret;
3231
3232 /* Many callers got this wrong, so check for it for a while... */
3233 if (!mtd->owner && caller_is_module()) {
20d8e248 3234 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3235 __func__);
3b85c321
DW		 3236 BUG();
3237 }
3238
5e81e88a 3239 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3240 if (!ret)
3241 ret = nand_scan_tail(mtd);
3242 return ret;
3243}
3244
1da177e4 3245/**
61b03bd7 3246 * nand_release - [NAND Interface] Free resources held by the NAND device
1da177e4
LT		 3247 * @mtd: MTD device structure
3248*/
e0c7d767 3249void nand_release(struct mtd_info *mtd)
1da177e4 3250{
ace4dfee 3251 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 3252
3253#ifdef CONFIG_MTD_PARTITIONS
3254 /* Deregister partitions */
e0c7d767 3255 del_mtd_partitions(mtd);
1da177e4
LT		 3256#endif
3257 /* Deregister the device */
e0c7d767 3258 del_mtd_device(mtd);
1da177e4 3259
fa671646 3260 /* Free bad block table memory */
ace4dfee 3261 kfree(chip->bbt);
4bf63fcb
DW		 3262 if (!(chip->options & NAND_OWN_BUFFERS))
3263 kfree(chip->buffers);
1da177e4
LT		 3264}
3265
7d70f334
VS		 3266EXPORT_SYMBOL_GPL(nand_lock);
3267EXPORT_SYMBOL_GPL(nand_unlock);
e0c7d767 3268EXPORT_SYMBOL_GPL(nand_scan);
3b85c321
DW		 3269EXPORT_SYMBOL_GPL(nand_scan_ident);
3270EXPORT_SYMBOL_GPL(nand_scan_tail);
e0c7d767 3271EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3272
3273static int __init nand_base_init(void)
3274{
3275 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3276 return 0;
3277}
3278
3279static void __exit nand_base_exit(void)
3280{
3281 led_trigger_unregister_simple(nand_led_trigger);
3282}
3283
3284module_init(nand_base_init);
3285module_exit(nand_base_exit);
3286
e0c7d767
DW		 3287MODULE_LICENSE("GPL");
3288MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3289MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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