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Documentation: mtd: update the document for m25p80
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
61b03bd7 7 *
1da177e4 8 * Additional technical information is available on
8b2b403c 9 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 10 *
1da177e4 11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 13 *
ace4dfee 14 * Credits:
61b03bd7
TG		 15 * David Woodhouse for adding multichip support
16 *
1da177e4
LT		 17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
19 *
ace4dfee 20 * TODO:
1da177e4
LT		 21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 23 * if we have HW ECC support.
c0b8ba7b 24 * BBT table is not serialized, has to be fixed
1da177e4 25 *
1da177e4
LT		 26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
29 *
30 */
31
20171642
EG		 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
552d9205 34#include <linux/module.h>
1da177e4
LT		 35#include <linux/delay.h>
36#include <linux/errno.h>
7aa65bfd 37#include <linux/err.h>
1da177e4
LT		 38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/types.h>
41#include <linux/mtd/mtd.h>
42#include <linux/mtd/nand.h>
43#include <linux/mtd/nand_ecc.h>
193bd400 44#include <linux/mtd/nand_bch.h>
1da177e4
LT		 45#include <linux/interrupt.h>
46#include <linux/bitops.h>
8fe833c1 47#include <linux/leds.h>
7351d3a5 48#include <linux/io.h>
1da177e4 49#include <linux/mtd/partitions.h>
1da177e4
LT		 50
51/* Define default oob placement schemes for large and small page devices */
5bd34c09 52static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 53 .eccbytes = 3,
54 .eccpos = {0, 1, 2},
5bd34c09
TG		 55 .oobfree = {
56 {.offset = 3,
57 .length = 2},
58 {.offset = 6,
f8ac0414 59 .length = 2} }
1da177e4
LT		 60};
61
5bd34c09 62static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 63 .eccbytes = 6,
64 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 65 .oobfree = {
66 {.offset = 8,
f8ac0414 67 . length = 8} }
1da177e4
LT		 68};
69
5bd34c09 70static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 71 .eccbytes = 24,
72 .eccpos = {
e0c7d767
DW		 73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 76 .oobfree = {
77 {.offset = 2,
f8ac0414 78 .length = 38} }
1da177e4
LT		 79};
80
81ec5364
TG		 81static struct nand_ecclayout nand_oob_128 = {
82 .eccbytes = 48,
83 .eccpos = {
84 80, 81, 82, 83, 84, 85, 86, 87,
85 88, 89, 90, 91, 92, 93, 94, 95,
86 96, 97, 98, 99, 100, 101, 102, 103,
87 104, 105, 106, 107, 108, 109, 110, 111,
88 112, 113, 114, 115, 116, 117, 118, 119,
89 120, 121, 122, 123, 124, 125, 126, 127},
90 .oobfree = {
91 {.offset = 2,
f8ac0414 92 .length = 78} }
81ec5364
TG		 93};
94
6a8214aa 95static int nand_get_device(struct mtd_info *mtd, int new_state);
1da177e4 96
8593fbc6
TG		 97static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
98 struct mtd_oob_ops *ops);
99
d470a97c 100/*
8e87d782 101 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 102 * compiled away when LED support is disabled.
103 */
104DEFINE_LED_TRIGGER(nand_led_trigger);
105
6fe5a6ac
VS		 106static int check_offs_len(struct mtd_info *mtd,
107 loff_t ofs, uint64_t len)
108{
109 struct nand_chip *chip = mtd->priv;
110 int ret = 0;
111
112 /* Start address must align on block boundary */
daae74ca 113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 114 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 115 ret = -EINVAL;
116 }
117
118 /* Length must align on block boundary */
daae74ca 119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 120 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 121 ret = -EINVAL;
122 }
123
6fe5a6ac
VS		 124 return ret;
125}
126
1da177e4
LT		 127/**
128 * nand_release_device - [GENERIC] release chip
8b6e50c9 129 * @mtd: MTD device structure
61b03bd7 130 *
b0bb6903 131 * Release chip lock and wake up anyone waiting on the device.
1da177e4 132 */
e0c7d767 133static void nand_release_device(struct mtd_info *mtd)
1da177e4 134{
ace4dfee 135 struct nand_chip *chip = mtd->priv;
1da177e4 136
a36ed299 137 /* Release the controller and the chip */
ace4dfee
TG		 138 spin_lock(&chip->controller->lock);
139 chip->controller->active = NULL;
140 chip->state = FL_READY;
141 wake_up(&chip->controller->wq);
142 spin_unlock(&chip->controller->lock);
1da177e4
LT		 143}
144
145/**
146 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 147 * @mtd: MTD device structure
1da177e4 148 *
7854d3f7 149 * Default read function for 8bit buswidth
1da177e4 150 */
58dd8f2b 151static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 152{
ace4dfee
TG		 153 struct nand_chip *chip = mtd->priv;
154 return readb(chip->IO_ADDR_R);
1da177e4
LT		 155}
156
1da177e4 157/**
064a7694 158 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
7854d3f7 159 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 160 * @mtd: MTD device structure
1da177e4 161 *
7854d3f7
BN		 162 * Default read function for 16bit buswidth with endianness conversion.
163 *
1da177e4 164 */
58dd8f2b 165static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 166{
ace4dfee
TG		 167 struct nand_chip *chip = mtd->priv;
168 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 169}
170
1da177e4
LT		 171/**
172 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 173 * @mtd: MTD device structure
1da177e4 174 *
7854d3f7 175 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 176 */
177static u16 nand_read_word(struct mtd_info *mtd)
178{
ace4dfee
TG		 179 struct nand_chip *chip = mtd->priv;
180 return readw(chip->IO_ADDR_R);
1da177e4
LT		 181}
182
1da177e4
LT		 183/**
184 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 185 * @mtd: MTD device structure
186 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 187 *
188 * Default select function for 1 chip devices.
189 */
ace4dfee 190static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 191{
ace4dfee
TG		 192 struct nand_chip *chip = mtd->priv;
193
194 switch (chipnr) {
1da177e4 195 case -1:
ace4dfee 196 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 197 break;
198 case 0:
1da177e4
LT		 199 break;
200
201 default:
202 BUG();
203 }
204}
205
05f78359
UKK		 206/**
207 * nand_write_byte - [DEFAULT] write single byte to chip
208 * @mtd: MTD device structure
209 * @byte: value to write
210 *
211 * Default function to write a byte to I/O[7:0]
212 */
213static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
214{
215 struct nand_chip *chip = mtd->priv;
216
217 chip->write_buf(mtd, &byte, 1);
218}
219
220/**
221 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
222 * @mtd: MTD device structure
223 * @byte: value to write
224 *
225 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
226 */
227static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
228{
229 struct nand_chip *chip = mtd->priv;
230 uint16_t word = byte;
231
232 /*
233 * It's not entirely clear what should happen to I/O[15:8] when writing
234 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
235 *
236 * When the host supports a 16-bit bus width, only data is
237 * transferred at the 16-bit width. All address and command line
238 * transfers shall use only the lower 8-bits of the data bus. During
239 * command transfers, the host may place any value on the upper
240 * 8-bits of the data bus. During address transfers, the host shall
241 * set the upper 8-bits of the data bus to 00h.
242 *
243 * One user of the write_byte callback is nand_onfi_set_features. The
244 * four parameters are specified to be written to I/O[7:0], but this is
245 * neither an address nor a command transfer. Let's assume a 0 on the
246 * upper I/O lines is OK.
247 */
248 chip->write_buf(mtd, (uint8_t *)&word, 2);
249}
250
1da177e4
LT		 251/**
252 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 253 * @mtd: MTD device structure
254 * @buf: data buffer
255 * @len: number of bytes to write
1da177e4 256 *
7854d3f7 257 * Default write function for 8bit buswidth.
1da177e4 258 */
58dd8f2b 259static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 260{
ace4dfee 261 struct nand_chip *chip = mtd->priv;
1da177e4 262
76413839 263 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 264}
265
266/**
61b03bd7 267 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 268 * @mtd: MTD device structure
269 * @buf: buffer to store date
270 * @len: number of bytes to read
1da177e4 271 *
7854d3f7 272 * Default read function for 8bit buswidth.
1da177e4 273 */
58dd8f2b 274static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 275{
ace4dfee 276 struct nand_chip *chip = mtd->priv;
1da177e4 277
76413839 278 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 279}
280
1da177e4
LT		 281/**
282 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 283 * @mtd: MTD device structure
284 * @buf: data buffer
285 * @len: number of bytes to write
1da177e4 286 *
7854d3f7 287 * Default write function for 16bit buswidth.
1da177e4 288 */
58dd8f2b 289static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 290{
ace4dfee 291 struct nand_chip *chip = mtd->priv;
1da177e4 292 u16 *p = (u16 *) buf;
61b03bd7 293
76413839 294 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 295}
296
297/**
61b03bd7 298 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 299 * @mtd: MTD device structure
300 * @buf: buffer to store date
301 * @len: number of bytes to read
1da177e4 302 *
7854d3f7 303 * Default read function for 16bit buswidth.
1da177e4 304 */
58dd8f2b 305static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 306{
ace4dfee 307 struct nand_chip *chip = mtd->priv;
1da177e4 308 u16 *p = (u16 *) buf;
1da177e4 309
76413839 310 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 311}
312
1da177e4
LT		 313/**
314 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 315 * @mtd: MTD device structure
316 * @ofs: offset from device start
317 * @getchip: 0, if the chip is already selected
1da177e4 318 *
61b03bd7 319 * Check, if the block is bad.
1da177e4
LT		 320 */
321static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
322{
cdbec050 323 int page, chipnr, res = 0, i = 0;
ace4dfee 324 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 325 u16 bad;
326
5fb1549d 327 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 328 ofs += mtd->erasesize - mtd->writesize;
329
1a12f46a
TK		 330 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
331
1da177e4 332 if (getchip) {
ace4dfee 333 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 334
6a8214aa 335 nand_get_device(mtd, FL_READING);
1da177e4
LT		 336
337 /* Select the NAND device */
ace4dfee 338 chip->select_chip(mtd, chipnr);
1a12f46a 339 }
1da177e4 340
cdbec050
BN		 341 do {
342 if (chip->options & NAND_BUSWIDTH_16) {
343 chip->cmdfunc(mtd, NAND_CMD_READOOB,
344 chip->badblockpos & 0xFE, page);
345 bad = cpu_to_le16(chip->read_word(mtd));
346 if (chip->badblockpos & 0x1)
347 bad >>= 8;
348 else
349 bad &= 0xFF;
350 } else {
351 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
352 page);
353 bad = chip->read_byte(mtd);
354 }
355
356 if (likely(chip->badblockbits == 8))
357 res = bad != 0xFF;
e0b58d0a 358 else
cdbec050
BN		 359 res = hweight8(bad) < chip->badblockbits;
360 ofs += mtd->writesize;
361 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
362 i++;
363 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 364
b0bb6903
HS		 365 if (getchip) {
366 chip->select_chip(mtd, -1);
1da177e4 367 nand_release_device(mtd);
b0bb6903 368 }
61b03bd7 369
1da177e4
LT		 370 return res;
371}
372
373/**
5a0edb25 374 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
8b6e50c9
BN		 375 * @mtd: MTD device structure
376 * @ofs: offset from device start
1da177e4 377 *
8b6e50c9 378 * This is the default implementation, which can be overridden by a hardware
5a0edb25
BN		 379 * specific driver. It provides the details for writing a bad block marker to a
380 * block.
381 */
382static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
383{
384 struct nand_chip *chip = mtd->priv;
385 struct mtd_oob_ops ops;
386 uint8_t buf[2] = { 0, 0 };
387 int ret = 0, res, i = 0;
388
389 ops.datbuf = NULL;
390 ops.oobbuf = buf;
391 ops.ooboffs = chip->badblockpos;
392 if (chip->options & NAND_BUSWIDTH_16) {
393 ops.ooboffs &= ~0x01;
394 ops.len = ops.ooblen = 2;
395 } else {
396 ops.len = ops.ooblen = 1;
397 }
398 ops.mode = MTD_OPS_PLACE_OOB;
399
400 /* Write to first/last page(s) if necessary */
401 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
402 ofs += mtd->erasesize - mtd->writesize;
403 do {
404 res = nand_do_write_oob(mtd, ofs, &ops);
405 if (!ret)
406 ret = res;
407
408 i++;
409 ofs += mtd->writesize;
410 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
411
412 return ret;
413}
414
415/**
416 * nand_block_markbad_lowlevel - mark a block bad
417 * @mtd: MTD device structure
418 * @ofs: offset from device start
419 *
420 * This function performs the generic NAND bad block marking steps (i.e., bad
421 * block table(s) and/or marker(s)). We only allow the hardware driver to
422 * specify how to write bad block markers to OOB (chip->block_markbad).
423 *
b32843b7 424 * We try operations in the following order:
e2414f4c 425 * (1) erase the affected block, to allow OOB marker to be written cleanly
b32843b7
BN		 426 * (2) write bad block marker to OOB area of affected block (unless flag
427 * NAND_BBT_NO_OOB_BBM is present)
428 * (3) update the BBT
429 * Note that we retain the first error encountered in (2) or (3), finish the
e2414f4c 430 * procedures, and dump the error in the end.
1da177e4 431*/
5a0edb25 432static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
1da177e4 433{
ace4dfee 434 struct nand_chip *chip = mtd->priv;
b32843b7 435 int res, ret = 0;
61b03bd7 436
b32843b7 437 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
00918429
BN		 438 struct erase_info einfo;
439
440 /* Attempt erase before marking OOB */
441 memset(&einfo, 0, sizeof(einfo));
442 einfo.mtd = mtd;
443 einfo.addr = ofs;
daae74ca 444 einfo.len = 1ULL << chip->phys_erase_shift;
00918429 445 nand_erase_nand(mtd, &einfo, 0);
1da177e4 446
b32843b7 447 /* Write bad block marker to OOB */
6a8214aa 448 nand_get_device(mtd, FL_WRITING);
5a0edb25 449 ret = chip->block_markbad(mtd, ofs);
c0b8ba7b 450 nand_release_device(mtd);
f1a28c02 451 }
e2414f4c 452
b32843b7
BN		 453 /* Mark block bad in BBT */
454 if (chip->bbt) {
455 res = nand_markbad_bbt(mtd, ofs);
e2414f4c
BN		 456 if (!ret)
457 ret = res;
458 }
459
f1a28c02
TG		 460 if (!ret)
461 mtd->ecc_stats.badblocks++;
c0b8ba7b 462
f1a28c02 463 return ret;
1da177e4
LT		 464}
465
61b03bd7 466/**
1da177e4 467 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 468 * @mtd: MTD device structure
1da177e4 469 *
8b6e50c9
BN		 470 * Check, if the device is write protected. The function expects, that the
471 * device is already selected.
1da177e4 472 */
e0c7d767 473static int nand_check_wp(struct mtd_info *mtd)
1da177e4 474{
ace4dfee 475 struct nand_chip *chip = mtd->priv;
93edbad6 476
8b6e50c9 477 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 478 if (chip->options & NAND_BROKEN_XD)
479 return 0;
480
1da177e4 481 /* Check the WP bit */
ace4dfee
TG		 482 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
483 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 484}
485
486/**
487 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 488 * @mtd: MTD device structure
489 * @ofs: offset from device start
490 * @getchip: 0, if the chip is already selected
491 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 492 *
493 * Check, if the block is bad. Either by reading the bad block table or
494 * calling of the scan function.
495 */
2c0a2bed
TG		 496static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
497 int allowbbt)
1da177e4 498{
ace4dfee 499 struct nand_chip *chip = mtd->priv;
61b03bd7 500
ace4dfee
TG		 501 if (!chip->bbt)
502 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 503
1da177e4 504 /* Return info from the table */
e0c7d767 505 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 506}
507
2af7c653
SK		 508/**
509 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 510 * @mtd: MTD device structure
511 * @timeo: Timeout
2af7c653
SK		 512 *
513 * Helper function for nand_wait_ready used when needing to wait in interrupt
514 * context.
515 */
516static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
517{
518 struct nand_chip *chip = mtd->priv;
519 int i;
520
521 /* Wait for the device to get ready */
522 for (i = 0; i < timeo; i++) {
523 if (chip->dev_ready(mtd))
524 break;
525 touch_softlockup_watchdog();
526 mdelay(1);
527 }
528}
529
7854d3f7 530/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 531void nand_wait_ready(struct mtd_info *mtd)
3b88775c 532{
ace4dfee 533 struct nand_chip *chip = mtd->priv;
ca6a2489 534 unsigned long timeo = jiffies + msecs_to_jiffies(20);
3b88775c 535
2af7c653
SK		 536 /* 400ms timeout */
537 if (in_interrupt() || oops_in_progress)
538 return panic_nand_wait_ready(mtd, 400);
539
8fe833c1 540 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 541 /* Wait until command is processed or timeout occurs */
3b88775c 542 do {
ace4dfee 543 if (chip->dev_ready(mtd))
8fe833c1 544 break;
8446f1d3 545 touch_softlockup_watchdog();
61b03bd7 546 } while (time_before(jiffies, timeo));
8fe833c1 547 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 548}
4b648b02 549EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 550
1da177e4
LT		 551/**
552 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 553 * @mtd: MTD device structure
554 * @command: the command to be sent
555 * @column: the column address for this command, -1 if none
556 * @page_addr: the page address for this command, -1 if none
1da177e4 557 *
8b6e50c9 558 * Send command to NAND device. This function is used for small page devices
51148f1f 559 * (512 Bytes per page).
1da177e4 560 */
7abd3ef9
TG		 561static void nand_command(struct mtd_info *mtd, unsigned int command,
562 int column, int page_addr)
1da177e4 563{
ace4dfee 564 register struct nand_chip *chip = mtd->priv;
7abd3ef9 565 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 566
8b6e50c9 567 /* Write out the command to the device */
1da177e4
LT		 568 if (command == NAND_CMD_SEQIN) {
569 int readcmd;
570
28318776 571 if (column >= mtd->writesize) {
1da177e4 572 /* OOB area */
28318776 573 column -= mtd->writesize;
1da177e4
LT		 574 readcmd = NAND_CMD_READOOB;
575 } else if (column < 256) {
576 /* First 256 bytes --> READ0 */
577 readcmd = NAND_CMD_READ0;
578 } else {
579 column -= 256;
580 readcmd = NAND_CMD_READ1;
581 }
ace4dfee 582 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 583 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 584 }
ace4dfee 585 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 586
8b6e50c9 587 /* Address cycle, when necessary */
7abd3ef9
TG		 588 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
589 /* Serially input address */
590 if (column != -1) {
591 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 592 if (chip->options & NAND_BUSWIDTH_16 &&
593 !nand_opcode_8bits(command))
7abd3ef9 594 column >>= 1;
ace4dfee 595 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 596 ctrl &= ~NAND_CTRL_CHANGE;
597 }
598 if (page_addr != -1) {
ace4dfee 599 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 600 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 601 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 602 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 603 if (chip->chipsize > (32 << 20))
604 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 605 }
ace4dfee 606 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 607
608 /*
8b6e50c9
BN		 609 * Program and erase have their own busy handlers status and sequential
610 * in needs no delay
e0c7d767 611 */
1da177e4 612 switch (command) {
61b03bd7 613
1da177e4
LT		 614 case NAND_CMD_PAGEPROG:
615 case NAND_CMD_ERASE1:
616 case NAND_CMD_ERASE2:
617 case NAND_CMD_SEQIN:
618 case NAND_CMD_STATUS:
619 return;
620
621 case NAND_CMD_RESET:
ace4dfee 622 if (chip->dev_ready)
1da177e4 623 break;
ace4dfee
TG		 624 udelay(chip->chip_delay);
625 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 626 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 627 chip->cmd_ctrl(mtd,
628 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 629 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
630 ;
1da177e4
LT		 631 return;
632
e0c7d767 633 /* This applies to read commands */
1da177e4 634 default:
61b03bd7 635 /*
1da177e4
LT		 636 * If we don't have access to the busy pin, we apply the given
637 * command delay
e0c7d767 638 */
ace4dfee
TG		 639 if (!chip->dev_ready) {
640 udelay(chip->chip_delay);
1da177e4 641 return;
61b03bd7 642 }
1da177e4 643 }
8b6e50c9
BN		 644 /*
645 * Apply this short delay always to ensure that we do wait tWB in
646 * any case on any machine.
647 */
e0c7d767 648 ndelay(100);
3b88775c
TG		 649
650 nand_wait_ready(mtd);
1da177e4
LT		 651}
652
653/**
654 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 655 * @mtd: MTD device structure
656 * @command: the command to be sent
657 * @column: the column address for this command, -1 if none
658 * @page_addr: the page address for this command, -1 if none
1da177e4 659 *
7abd3ef9 660 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 661 * devices. We don't have the separate regions as we have in the small page
662 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 663 */
7abd3ef9
TG		 664static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
665 int column, int page_addr)
1da177e4 666{
ace4dfee 667 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 668
669 /* Emulate NAND_CMD_READOOB */
670 if (command == NAND_CMD_READOOB) {
28318776 671 column += mtd->writesize;
1da177e4
LT		 672 command = NAND_CMD_READ0;
673 }
61b03bd7 674
7abd3ef9 675 /* Command latch cycle */
fb066ada 676 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 677
678 if (column != -1 || page_addr != -1) {
7abd3ef9 679 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 680
681 /* Serially input address */
682 if (column != -1) {
683 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 684 if (chip->options & NAND_BUSWIDTH_16 &&
685 !nand_opcode_8bits(command))
1da177e4 686 column >>= 1;
ace4dfee 687 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 688 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 689 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 690 }
1da177e4 691 if (page_addr != -1) {
ace4dfee
TG		 692 chip->cmd_ctrl(mtd, page_addr, ctrl);
693 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 694 NAND_NCE | NAND_ALE);
1da177e4 695 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 696 if (chip->chipsize > (128 << 20))
697 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 698 NAND_NCE | NAND_ALE);
1da177e4 699 }
1da177e4 700 }
ace4dfee 701 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 702
703 /*
8b6e50c9
BN		 704 * Program and erase have their own busy handlers status, sequential
705 * in, and deplete1 need no delay.
30f464b7 706 */
1da177e4 707 switch (command) {
61b03bd7 708
1da177e4
LT		 709 case NAND_CMD_CACHEDPROG:
710 case NAND_CMD_PAGEPROG:
711 case NAND_CMD_ERASE1:
712 case NAND_CMD_ERASE2:
713 case NAND_CMD_SEQIN:
7bc3312b 714 case NAND_CMD_RNDIN:
1da177e4 715 case NAND_CMD_STATUS:
30f464b7 716 return;
1da177e4
LT		 717
718 case NAND_CMD_RESET:
ace4dfee 719 if (chip->dev_ready)
1da177e4 720 break;
ace4dfee 721 udelay(chip->chip_delay);
12efdde3
TG		 722 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
723 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
724 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
725 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 726 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
727 ;
1da177e4
LT		 728 return;
729
7bc3312b
TG		 730 case NAND_CMD_RNDOUT:
731 /* No ready / busy check necessary */
732 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
733 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
734 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
735 NAND_NCE | NAND_CTRL_CHANGE);
736 return;
737
1da177e4 738 case NAND_CMD_READ0:
12efdde3
TG		 739 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
740 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
741 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
742 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 743
e0c7d767 744 /* This applies to read commands */
1da177e4 745 default:
61b03bd7 746 /*
1da177e4 747 * If we don't have access to the busy pin, we apply the given
8b6e50c9 748 * command delay.
e0c7d767 749 */
ace4dfee
TG		 750 if (!chip->dev_ready) {
751 udelay(chip->chip_delay);
1da177e4 752 return;
61b03bd7 753 }
1da177e4 754 }
3b88775c 755
8b6e50c9
BN		 756 /*
757 * Apply this short delay always to ensure that we do wait tWB in
758 * any case on any machine.
759 */
e0c7d767 760 ndelay(100);
3b88775c
TG		 761
762 nand_wait_ready(mtd);
1da177e4
LT		 763}
764
2af7c653
SK		 765/**
766 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 767 * @chip: the nand chip descriptor
768 * @mtd: MTD device structure
769 * @new_state: the state which is requested
2af7c653
SK		 770 *
771 * Used when in panic, no locks are taken.
772 */
773static void panic_nand_get_device(struct nand_chip *chip,
774 struct mtd_info *mtd, int new_state)
775{
7854d3f7 776 /* Hardware controller shared among independent devices */
2af7c653
SK		 777 chip->controller->active = chip;
778 chip->state = new_state;
779}
780
1da177e4
LT		 781/**
782 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 783 * @mtd: MTD device structure
784 * @new_state: the state which is requested
1da177e4
LT		 785 *
786 * Get the device and lock it for exclusive access
787 */
2c0a2bed 788static int
6a8214aa 789nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 790{
6a8214aa 791 struct nand_chip *chip = mtd->priv;
ace4dfee
TG		 792 spinlock_t *lock = &chip->controller->lock;
793 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 794 DECLARE_WAITQUEUE(wait, current);
7351d3a5 795retry:
0dfc6246
TG		 796 spin_lock(lock);
797
b8b3ee9a 798 /* Hardware controller shared among independent devices */
ace4dfee
TG		 799 if (!chip->controller->active)
800 chip->controller->active = chip;
a36ed299 801
ace4dfee
TG		 802 if (chip->controller->active == chip && chip->state == FL_READY) {
803 chip->state = new_state;
0dfc6246 804 spin_unlock(lock);
962034f4
VW		 805 return 0;
806 }
807 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 808 if (chip->controller->active->state == FL_PM_SUSPENDED) {
809 chip->state = FL_PM_SUSPENDED;
810 spin_unlock(lock);
811 return 0;
6b0d9a84 812 }
0dfc6246
TG		 813 }
814 set_current_state(TASK_UNINTERRUPTIBLE);
815 add_wait_queue(wq, &wait);
816 spin_unlock(lock);
817 schedule();
818 remove_wait_queue(wq, &wait);
1da177e4
LT		 819 goto retry;
820}
821
2af7c653 822/**
8b6e50c9
BN		 823 * panic_nand_wait - [GENERIC] wait until the command is done
824 * @mtd: MTD device structure
825 * @chip: NAND chip structure
826 * @timeo: timeout
2af7c653
SK		 827 *
828 * Wait for command done. This is a helper function for nand_wait used when
829 * we are in interrupt context. May happen when in panic and trying to write
b595076a 830 * an oops through mtdoops.
2af7c653
SK		 831 */
832static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
833 unsigned long timeo)
834{
835 int i;
836 for (i = 0; i < timeo; i++) {
837 if (chip->dev_ready) {
838 if (chip->dev_ready(mtd))
839 break;
840 } else {
841 if (chip->read_byte(mtd) & NAND_STATUS_READY)
842 break;
843 }
844 mdelay(1);
f8ac0414 845 }
2af7c653
SK		 846}
847
1da177e4 848/**
8b6e50c9
BN		 849 * nand_wait - [DEFAULT] wait until the command is done
850 * @mtd: MTD device structure
851 * @chip: NAND chip structure
1da177e4 852 *
8b6e50c9
BN		 853 * Wait for command done. This applies to erase and program only. Erase can
854 * take up to 400ms and program up to 20ms according to general NAND and
855 * SmartMedia specs.
844d3b42 856 */
7bc3312b 857static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 858{
859
7bc3312b 860 int status, state = chip->state;
6d2559f8 861 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1da177e4 862
8fe833c1
RP		 863 led_trigger_event(nand_led_trigger, LED_FULL);
864
8b6e50c9
BN		 865 /*
866 * Apply this short delay always to ensure that we do wait tWB in any
867 * case on any machine.
868 */
e0c7d767 869 ndelay(100);
1da177e4 870
14c65786 871 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 872
2af7c653
SK		 873 if (in_interrupt() || oops_in_progress)
874 panic_nand_wait(mtd, chip, timeo);
875 else {
6d2559f8 876 timeo = jiffies + msecs_to_jiffies(timeo);
2af7c653
SK		 877 while (time_before(jiffies, timeo)) {
878 if (chip->dev_ready) {
879 if (chip->dev_ready(mtd))
880 break;
881 } else {
882 if (chip->read_byte(mtd) & NAND_STATUS_READY)
883 break;
884 }
885 cond_resched();
1da177e4 886 }
1da177e4 887 }
8fe833c1
RP		 888 led_trigger_event(nand_led_trigger, LED_OFF);
889
ace4dfee 890 status = (int)chip->read_byte(mtd);
f251b8df
MC		 891 /* This can happen if in case of timeout or buggy dev_ready */
892 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 893 return status;
894}
895
7d70f334 896/**
b6d676db 897 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 898 * @mtd: mtd info
899 * @ofs: offset to start unlock from
900 * @len: length to unlock
8b6e50c9
BN		 901 * @invert: when = 0, unlock the range of blocks within the lower and
902 * upper boundary address
903 * when = 1, unlock the range of blocks outside the boundaries
904 * of the lower and upper boundary address
7d70f334 905 *
8b6e50c9 906 * Returs unlock status.
7d70f334
VS		 907 */
908static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
909 uint64_t len, int invert)
910{
911 int ret = 0;
912 int status, page;
913 struct nand_chip *chip = mtd->priv;
914
915 /* Submit address of first page to unlock */
916 page = ofs >> chip->page_shift;
917 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
918
919 /* Submit address of last page to unlock */
920 page = (ofs + len) >> chip->page_shift;
921 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
922 (page | invert) & chip->pagemask);
923
924 /* Call wait ready function */
925 status = chip->waitfunc(mtd, chip);
7d70f334 926 /* See if device thinks it succeeded */
74830966 927 if (status & NAND_STATUS_FAIL) {
289c0522 928 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 929 __func__, status);
930 ret = -EIO;
931 }
932
933 return ret;
934}
935
936/**
b6d676db 937 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 938 * @mtd: mtd info
939 * @ofs: offset to start unlock from
940 * @len: length to unlock
7d70f334 941 *
8b6e50c9 942 * Returns unlock status.
7d70f334
VS		 943 */
944int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
945{
946 int ret = 0;
947 int chipnr;
948 struct nand_chip *chip = mtd->priv;
949
289c0522 950 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 951 __func__, (unsigned long long)ofs, len);
952
953 if (check_offs_len(mtd, ofs, len))
954 ret = -EINVAL;
955
956 /* Align to last block address if size addresses end of the device */
957 if (ofs + len == mtd->size)
958 len -= mtd->erasesize;
959
6a8214aa 960 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 961
962 /* Shift to get chip number */
963 chipnr = ofs >> chip->chip_shift;
964
965 chip->select_chip(mtd, chipnr);
966
967 /* Check, if it is write protected */
968 if (nand_check_wp(mtd)) {
289c0522 969 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 970 __func__);
971 ret = -EIO;
972 goto out;
973 }
974
975 ret = __nand_unlock(mtd, ofs, len, 0);
976
977out:
b0bb6903 978 chip->select_chip(mtd, -1);
7d70f334
VS		 979 nand_release_device(mtd);
980
981 return ret;
982}
7351d3a5 983EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 984
985/**
b6d676db 986 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 987 * @mtd: mtd info
988 * @ofs: offset to start unlock from
989 * @len: length to unlock
7d70f334 990 *
8b6e50c9
BN		 991 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
992 * have this feature, but it allows only to lock all blocks, not for specified
993 * range for block. Implementing 'lock' feature by making use of 'unlock', for
994 * now.
7d70f334 995 *
8b6e50c9 996 * Returns lock status.
7d70f334
VS		 997 */
998int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
999{
1000 int ret = 0;
1001 int chipnr, status, page;
1002 struct nand_chip *chip = mtd->priv;
1003
289c0522 1004 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1005 __func__, (unsigned long long)ofs, len);
1006
1007 if (check_offs_len(mtd, ofs, len))
1008 ret = -EINVAL;
1009
6a8214aa 1010 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 1011
1012 /* Shift to get chip number */
1013 chipnr = ofs >> chip->chip_shift;
1014
1015 chip->select_chip(mtd, chipnr);
1016
1017 /* Check, if it is write protected */
1018 if (nand_check_wp(mtd)) {
289c0522 1019 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1020 __func__);
1021 status = MTD_ERASE_FAILED;
1022 ret = -EIO;
1023 goto out;
1024 }
1025
1026 /* Submit address of first page to lock */
1027 page = ofs >> chip->page_shift;
1028 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1029
1030 /* Call wait ready function */
1031 status = chip->waitfunc(mtd, chip);
7d70f334 1032 /* See if device thinks it succeeded */
74830966 1033 if (status & NAND_STATUS_FAIL) {
289c0522 1034 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1035 __func__, status);
1036 ret = -EIO;
1037 goto out;
1038 }
1039
1040 ret = __nand_unlock(mtd, ofs, len, 0x1);
1041
1042out:
b0bb6903 1043 chip->select_chip(mtd, -1);
7d70f334
VS		 1044 nand_release_device(mtd);
1045
1046 return ret;
1047}
7351d3a5 1048EXPORT_SYMBOL(nand_lock);
7d70f334 1049
8593fbc6 1050/**
7854d3f7 1051 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1052 * @mtd: mtd info structure
1053 * @chip: nand chip info structure
1054 * @buf: buffer to store read data
1fbb938d 1055 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1056 * @page: page number to read
52ff49df 1057 *
7854d3f7 1058 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1059 */
1060static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1061 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1062{
1063 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1064 if (oob_required)
1065 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1066 return 0;
1067}
1068
52ff49df 1069/**
7854d3f7 1070 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1071 * @mtd: mtd info structure
1072 * @chip: nand chip info structure
1073 * @buf: buffer to store read data
1fbb938d 1074 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1075 * @page: page number to read
52ff49df
DB		 1076 *
1077 * We need a special oob layout and handling even when OOB isn't used.
1078 */
7351d3a5 1079static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1080 struct nand_chip *chip, uint8_t *buf,
1081 int oob_required, int page)
52ff49df
DB		 1082{
1083 int eccsize = chip->ecc.size;
1084 int eccbytes = chip->ecc.bytes;
1085 uint8_t *oob = chip->oob_poi;
1086 int steps, size;
1087
1088 for (steps = chip->ecc.steps; steps > 0; steps--) {
1089 chip->read_buf(mtd, buf, eccsize);
1090 buf += eccsize;
1091
1092 if (chip->ecc.prepad) {
1093 chip->read_buf(mtd, oob, chip->ecc.prepad);
1094 oob += chip->ecc.prepad;
1095 }
1096
1097 chip->read_buf(mtd, oob, eccbytes);
1098 oob += eccbytes;
1099
1100 if (chip->ecc.postpad) {
1101 chip->read_buf(mtd, oob, chip->ecc.postpad);
1102 oob += chip->ecc.postpad;
1103 }
1104 }
1105
1106 size = mtd->oobsize - (oob - chip->oob_poi);
1107 if (size)
1108 chip->read_buf(mtd, oob, size);
1109
1110 return 0;
1111}
1112
1da177e4 1113/**
7854d3f7 1114 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1115 * @mtd: mtd info structure
1116 * @chip: nand chip info structure
1117 * @buf: buffer to store read data
1fbb938d 1118 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1119 * @page: page number to read
068e3c0a 1120 */
f5bbdacc 1121static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1122 uint8_t *buf, int oob_required, int page)
1da177e4 1123{
f5bbdacc
TG		 1124 int i, eccsize = chip->ecc.size;
1125 int eccbytes = chip->ecc.bytes;
1126 int eccsteps = chip->ecc.steps;
1127 uint8_t *p = buf;
4bf63fcb
DW		 1128 uint8_t *ecc_calc = chip->buffers->ecccalc;
1129 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1130 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1131 unsigned int max_bitflips = 0;
f5bbdacc 1132
1fbb938d 1133 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1134
1135 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1136 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1137
1138 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1139 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1140
1141 eccsteps = chip->ecc.steps;
1142 p = buf;
1143
1144 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1145 int stat;
1146
1147 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1148 if (stat < 0) {
f5bbdacc 1149 mtd->ecc_stats.failed++;
3f91e94f 1150 } else {
f5bbdacc 1151 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1152 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1153 }
f5bbdacc 1154 }
3f91e94f 1155 return max_bitflips;
22c60f5f 1156}
1da177e4 1157
3d459559 1158/**
837a6ba4 1159 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1160 * @mtd: mtd info structure
1161 * @chip: nand chip info structure
1162 * @data_offs: offset of requested data within the page
1163 * @readlen: data length
1164 * @bufpoi: buffer to store read data
e004debd 1165 * @page: page number to read
3d459559 1166 */
7351d3a5 1167static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
e004debd
HS		 1168 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1169 int page)
3d459559
AK		 1170{
1171 int start_step, end_step, num_steps;
1172 uint32_t *eccpos = chip->ecc.layout->eccpos;
1173 uint8_t *p;
1174 int data_col_addr, i, gaps = 0;
1175 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1176 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
4a4163ca 1177 int index;
3f91e94f 1178 unsigned int max_bitflips = 0;
3d459559 1179
7854d3f7 1180 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1181 start_step = data_offs / chip->ecc.size;
1182 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1183 num_steps = end_step - start_step + 1;
4a4163ca 1184 index = start_step * chip->ecc.bytes;
3d459559 1185
8b6e50c9 1186 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1187 datafrag_len = num_steps * chip->ecc.size;
1188 eccfrag_len = num_steps * chip->ecc.bytes;
1189
1190 data_col_addr = start_step * chip->ecc.size;
1191 /* If we read not a page aligned data */
1192 if (data_col_addr != 0)
1193 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1194
1195 p = bufpoi + data_col_addr;
1196 chip->read_buf(mtd, p, datafrag_len);
1197
8b6e50c9 1198 /* Calculate ECC */
3d459559
AK		 1199 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1200 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1201
8b6e50c9
BN		 1202 /*
1203 * The performance is faster if we position offsets according to
7854d3f7 1204 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1205 */
3d459559 1206 for (i = 0; i < eccfrag_len - 1; i++) {
47570bb1 1207 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
3d459559
AK		 1208 gaps = 1;
1209 break;
1210 }
1211 }
1212 if (gaps) {
1213 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1214 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1215 } else {
8b6e50c9 1216 /*
7854d3f7 1217 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1218 * about buswidth alignment in read_buf.
1219 */
7351d3a5 1220 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1221 aligned_len = eccfrag_len;
7351d3a5 1222 if (eccpos[index] & (busw - 1))
3d459559 1223 aligned_len++;
7351d3a5 1224 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1225 aligned_len++;
1226
7351d3a5
FF		 1227 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1228 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1229 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1230 }
1231
1232 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1233 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1234
1235 p = bufpoi + data_col_addr;
1236 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1237 int stat;
1238
7351d3a5
FF		 1239 stat = chip->ecc.correct(mtd, p,
1240 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1241 if (stat < 0) {
3d459559 1242 mtd->ecc_stats.failed++;
3f91e94f 1243 } else {
3d459559 1244 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1245 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1246 }
3d459559 1247 }
3f91e94f 1248 return max_bitflips;
3d459559
AK		 1249}
1250
068e3c0a 1251/**
7854d3f7 1252 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1253 * @mtd: mtd info structure
1254 * @chip: nand chip info structure
1255 * @buf: buffer to store read data
1fbb938d 1256 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1257 * @page: page number to read
068e3c0a 1258 *
7854d3f7 1259 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1260 */
f5bbdacc 1261static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1262 uint8_t *buf, int oob_required, int page)
1da177e4 1263{
f5bbdacc
TG		 1264 int i, eccsize = chip->ecc.size;
1265 int eccbytes = chip->ecc.bytes;
1266 int eccsteps = chip->ecc.steps;
1267 uint8_t *p = buf;
4bf63fcb
DW		 1268 uint8_t *ecc_calc = chip->buffers->ecccalc;
1269 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1270 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1271 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1272
1273 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1274 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1275 chip->read_buf(mtd, p, eccsize);
1276 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1277 }
f75e5097 1278 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1279
f5bbdacc 1280 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1281 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1282
f5bbdacc
TG		 1283 eccsteps = chip->ecc.steps;
1284 p = buf;
61b03bd7 1285
f5bbdacc
TG		 1286 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1287 int stat;
1da177e4 1288
f5bbdacc 1289 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1290 if (stat < 0) {
f5bbdacc 1291 mtd->ecc_stats.failed++;
3f91e94f 1292 } else {
f5bbdacc 1293 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1294 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1295 }
f5bbdacc 1296 }
3f91e94f 1297 return max_bitflips;
f5bbdacc 1298}
1da177e4 1299
6e0cb135 1300/**
7854d3f7 1301 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1302 * @mtd: mtd info structure
1303 * @chip: nand chip info structure
1304 * @buf: buffer to store read data
1fbb938d 1305 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1306 * @page: page number to read
6e0cb135 1307 *
8b6e50c9
BN		 1308 * Hardware ECC for large page chips, require OOB to be read first. For this
1309 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1310 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1311 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1312 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1313 */
1314static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1315 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1316{
1317 int i, eccsize = chip->ecc.size;
1318 int eccbytes = chip->ecc.bytes;
1319 int eccsteps = chip->ecc.steps;
1320 uint8_t *p = buf;
1321 uint8_t *ecc_code = chip->buffers->ecccode;
1322 uint32_t *eccpos = chip->ecc.layout->eccpos;
1323 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1324 unsigned int max_bitflips = 0;
6e0cb135
SN		 1325
1326 /* Read the OOB area first */
1327 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1328 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1329 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1330
1331 for (i = 0; i < chip->ecc.total; i++)
1332 ecc_code[i] = chip->oob_poi[eccpos[i]];
1333
1334 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1335 int stat;
1336
1337 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1338 chip->read_buf(mtd, p, eccsize);
1339 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1340
1341 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1342 if (stat < 0) {
6e0cb135 1343 mtd->ecc_stats.failed++;
3f91e94f 1344 } else {
6e0cb135 1345 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1346 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1347 }
6e0cb135 1348 }
3f91e94f 1349 return max_bitflips;
6e0cb135
SN		 1350}
1351
f5bbdacc 1352/**
7854d3f7 1353 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1354 * @mtd: mtd info structure
1355 * @chip: nand chip info structure
1356 * @buf: buffer to store read data
1fbb938d 1357 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1358 * @page: page number to read
f5bbdacc 1359 *
8b6e50c9
BN		 1360 * The hw generator calculates the error syndrome automatically. Therefore we
1361 * need a special oob layout and handling.
f5bbdacc
TG		 1362 */
1363static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1364 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1365{
1366 int i, eccsize = chip->ecc.size;
1367 int eccbytes = chip->ecc.bytes;
1368 int eccsteps = chip->ecc.steps;
1369 uint8_t *p = buf;
f75e5097 1370 uint8_t *oob = chip->oob_poi;
3f91e94f 1371 unsigned int max_bitflips = 0;
1da177e4 1372
f5bbdacc
TG		 1373 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1374 int stat;
61b03bd7 1375
f5bbdacc
TG		 1376 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1377 chip->read_buf(mtd, p, eccsize);
1da177e4 1378
f5bbdacc
TG		 1379 if (chip->ecc.prepad) {
1380 chip->read_buf(mtd, oob, chip->ecc.prepad);
1381 oob += chip->ecc.prepad;
1382 }
1da177e4 1383
f5bbdacc
TG		 1384 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1385 chip->read_buf(mtd, oob, eccbytes);
1386 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1387
3f91e94f 1388 if (stat < 0) {
f5bbdacc 1389 mtd->ecc_stats.failed++;
3f91e94f 1390 } else {
f5bbdacc 1391 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1392 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1393 }
61b03bd7 1394
f5bbdacc 1395 oob += eccbytes;
1da177e4 1396
f5bbdacc
TG		 1397 if (chip->ecc.postpad) {
1398 chip->read_buf(mtd, oob, chip->ecc.postpad);
1399 oob += chip->ecc.postpad;
61b03bd7 1400 }
f5bbdacc 1401 }
1da177e4 1402
f5bbdacc 1403 /* Calculate remaining oob bytes */
7e4178f9 1404 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1405 if (i)
1406 chip->read_buf(mtd, oob, i);
61b03bd7 1407
3f91e94f 1408 return max_bitflips;
f5bbdacc 1409}
1da177e4 1410
f5bbdacc 1411/**
7854d3f7 1412 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1413 * @chip: nand chip structure
1414 * @oob: oob destination address
1415 * @ops: oob ops structure
1416 * @len: size of oob to transfer
8593fbc6
TG		 1417 */
1418static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1419 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1420{
f8ac0414 1421 switch (ops->mode) {
8593fbc6 1422
0612b9dd
BN		 1423 case MTD_OPS_PLACE_OOB:
1424 case MTD_OPS_RAW:
8593fbc6
TG		 1425 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1426 return oob + len;
1427
0612b9dd 1428 case MTD_OPS_AUTO_OOB: {
8593fbc6 1429 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1430 uint32_t boffs = 0, roffs = ops->ooboffs;
1431 size_t bytes = 0;
8593fbc6 1432
f8ac0414 1433 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1434 /* Read request not from offset 0? */
7bc3312b
TG		 1435 if (unlikely(roffs)) {
1436 if (roffs >= free->length) {
1437 roffs -= free->length;
1438 continue;
1439 }
1440 boffs = free->offset + roffs;
1441 bytes = min_t(size_t, len,
1442 (free->length - roffs));
1443 roffs = 0;
1444 } else {
1445 bytes = min_t(size_t, len, free->length);
1446 boffs = free->offset;
1447 }
1448 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1449 oob += bytes;
1450 }
1451 return oob;
1452 }
1453 default:
1454 BUG();
1455 }
1456 return NULL;
1457}
1458
ba84fb59
BN		 1459/**
1460 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1461 * @mtd: MTD device structure
1462 * @retry_mode: the retry mode to use
1463 *
1464 * Some vendors supply a special command to shift the Vt threshold, to be used
1465 * when there are too many bitflips in a page (i.e., ECC error). After setting
1466 * a new threshold, the host should retry reading the page.
1467 */
1468static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1469{
1470 struct nand_chip *chip = mtd->priv;
1471
1472 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1473
1474 if (retry_mode >= chip->read_retries)
1475 return -EINVAL;
1476
1477 if (!chip->setup_read_retry)
1478 return -EOPNOTSUPP;
1479
1480 return chip->setup_read_retry(mtd, retry_mode);
1481}
1482
8593fbc6 1483/**
7854d3f7 1484 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1485 * @mtd: MTD device structure
1486 * @from: offset to read from
1487 * @ops: oob ops structure
f5bbdacc
TG		 1488 *
1489 * Internal function. Called with chip held.
1490 */
8593fbc6
TG		 1491static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1492 struct mtd_oob_ops *ops)
f5bbdacc 1493{
e47f3db4 1494 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc 1495 struct nand_chip *chip = mtd->priv;
f5bbdacc 1496 int ret = 0;
8593fbc6 1497 uint32_t readlen = ops->len;
7014568b 1498 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1499 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1500 mtd->oobavail : mtd->oobsize;
1501
8593fbc6 1502 uint8_t *bufpoi, *oob, *buf;
edbc4540 1503 unsigned int max_bitflips = 0;
ba84fb59 1504 int retry_mode = 0;
b72f3dfb 1505 bool ecc_fail = false;
1da177e4 1506
f5bbdacc
TG		 1507 chipnr = (int)(from >> chip->chip_shift);
1508 chip->select_chip(mtd, chipnr);
61b03bd7 1509
f5bbdacc
TG		 1510 realpage = (int)(from >> chip->page_shift);
1511 page = realpage & chip->pagemask;
1da177e4 1512
f5bbdacc 1513 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1514
8593fbc6
TG		 1515 buf = ops->datbuf;
1516 oob = ops->oobbuf;
e47f3db4 1517 oob_required = oob ? 1 : 0;
8593fbc6 1518
f8ac0414 1519 while (1) {
b72f3dfb
BN		 1520 unsigned int ecc_failures = mtd->ecc_stats.failed;
1521
f5bbdacc
TG		 1522 bytes = min(mtd->writesize - col, readlen);
1523 aligned = (bytes == mtd->writesize);
61b03bd7 1524
8b6e50c9 1525 /* Is the current page in the buffer? */
8593fbc6 1526 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1527 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1528
ba84fb59 1529read_retry:
c00a0991 1530 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1531
edbc4540
MD		 1532 /*
1533 * Now read the page into the buffer. Absent an error,
1534 * the read methods return max bitflips per ecc step.
1535 */
0612b9dd 1536 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1537 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1538 oob_required,
1539 page);
a5ff4f10
JW		 1540 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1541 !oob)
7351d3a5 1542 ret = chip->ecc.read_subpage(mtd, chip,
e004debd
HS		 1543 col, bytes, bufpoi,
1544 page);
956e944c 1545 else
46a8cf2d 1546 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1547 oob_required, page);
6d77b9d0
BN		 1548 if (ret < 0) {
1549 if (!aligned)
1550 /* Invalidate page cache */
1551 chip->pagebuf = -1;
1da177e4 1552 break;
6d77b9d0 1553 }
f5bbdacc 1554
edbc4540
MD		 1555 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1556
f5bbdacc
TG		 1557 /* Transfer not aligned data */
1558 if (!aligned) {
a5ff4f10 1559 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
b72f3dfb 1560 !(mtd->ecc_stats.failed - ecc_failures) &&
edbc4540 1561 (ops->mode != MTD_OPS_RAW)) {
3d459559 1562 chip->pagebuf = realpage;
edbc4540
MD		 1563 chip->pagebuf_bitflips = ret;
1564 } else {
6d77b9d0
BN		 1565 /* Invalidate page cache */
1566 chip->pagebuf = -1;
edbc4540 1567 }
4bf63fcb 1568 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1569 }
1570
8593fbc6 1571 if (unlikely(oob)) {
b64d39d8
ML		 1572 int toread = min(oobreadlen, max_oobsize);
1573
1574 if (toread) {
1575 oob = nand_transfer_oob(chip,
1576 oob, ops, toread);
1577 oobreadlen -= toread;
1578 }
8593fbc6 1579 }
5bc7c33c
BN		 1580
1581 if (chip->options & NAND_NEED_READRDY) {
1582 /* Apply delay or wait for ready/busy pin */
1583 if (!chip->dev_ready)
1584 udelay(chip->chip_delay);
1585 else
1586 nand_wait_ready(mtd);
1587 }
b72f3dfb 1588
ba84fb59 1589 if (mtd->ecc_stats.failed - ecc_failures) {
28fa65e6 1590 if (retry_mode + 1 < chip->read_retries) {
ba84fb59
BN		 1591 retry_mode++;
1592 ret = nand_setup_read_retry(mtd,
1593 retry_mode);
1594 if (ret < 0)
1595 break;
1596
1597 /* Reset failures; retry */
1598 mtd->ecc_stats.failed = ecc_failures;
1599 goto read_retry;
1600 } else {
1601 /* No more retry modes; real failure */
1602 ecc_fail = true;
1603 }
1604 }
1605
1606 buf += bytes;
8593fbc6 1607 } else {
4bf63fcb 1608 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1609 buf += bytes;
edbc4540
MD		 1610 max_bitflips = max_t(unsigned int, max_bitflips,
1611 chip->pagebuf_bitflips);
8593fbc6 1612 }
1da177e4 1613
f5bbdacc 1614 readlen -= bytes;
61b03bd7 1615
ba84fb59
BN		 1616 /* Reset to retry mode 0 */
1617 if (retry_mode) {
1618 ret = nand_setup_read_retry(mtd, 0);
1619 if (ret < 0)
1620 break;
1621 retry_mode = 0;
1622 }
1623
f5bbdacc 1624 if (!readlen)
61b03bd7 1625 break;
1da177e4 1626
8b6e50c9 1627 /* For subsequent reads align to page boundary */
1da177e4
LT		 1628 col = 0;
1629 /* Increment page address */
1630 realpage++;
1631
ace4dfee 1632 page = realpage & chip->pagemask;
1da177e4
LT		 1633 /* Check, if we cross a chip boundary */
1634 if (!page) {
1635 chipnr++;
ace4dfee
TG		 1636 chip->select_chip(mtd, -1);
1637 chip->select_chip(mtd, chipnr);
1da177e4 1638 }
1da177e4 1639 }
b0bb6903 1640 chip->select_chip(mtd, -1);
1da177e4 1641
8593fbc6 1642 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1643 if (oob)
1644 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1645
3f91e94f 1646 if (ret < 0)
f5bbdacc
TG		 1647 return ret;
1648
b72f3dfb 1649 if (ecc_fail)
9a1fcdfd
TG		 1650 return -EBADMSG;
1651
edbc4540 1652 return max_bitflips;
f5bbdacc
TG		 1653}
1654
1655/**
25985edc 1656 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1657 * @mtd: MTD device structure
1658 * @from: offset to read from
1659 * @len: number of bytes to read
1660 * @retlen: pointer to variable to store the number of read bytes
1661 * @buf: the databuffer to put data
f5bbdacc 1662 *
8b6e50c9 1663 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1664 */
1665static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1666 size_t *retlen, uint8_t *buf)
1667{
4a89ff88 1668 struct mtd_oob_ops ops;
f5bbdacc
TG		 1669 int ret;
1670
6a8214aa 1671 nand_get_device(mtd, FL_READING);
4a89ff88
BN		 1672 ops.len = len;
1673 ops.datbuf = buf;
1674 ops.oobbuf = NULL;
11041ae6 1675 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1676 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1677 *retlen = ops.retlen;
f5bbdacc 1678 nand_release_device(mtd);
f5bbdacc 1679 return ret;
1da177e4
LT		 1680}
1681
7bc3312b 1682/**
7854d3f7 1683 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1684 * @mtd: mtd info structure
1685 * @chip: nand chip info structure
1686 * @page: page number to read
7bc3312b
TG		 1687 */
1688static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1689 int page)
7bc3312b 1690{
5c2ffb11 1691 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1692 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1693 return 0;
7bc3312b
TG		 1694}
1695
1696/**
7854d3f7 1697 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1698 * with syndromes
8b6e50c9
BN		 1699 * @mtd: mtd info structure
1700 * @chip: nand chip info structure
1701 * @page: page number to read
7bc3312b
TG		 1702 */
1703static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1704 int page)
7bc3312b
TG		 1705{
1706 uint8_t *buf = chip->oob_poi;
1707 int length = mtd->oobsize;
1708 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1709 int eccsize = chip->ecc.size;
1710 uint8_t *bufpoi = buf;
1711 int i, toread, sndrnd = 0, pos;
1712
1713 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1714 for (i = 0; i < chip->ecc.steps; i++) {
1715 if (sndrnd) {
1716 pos = eccsize + i * (eccsize + chunk);
1717 if (mtd->writesize > 512)
1718 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1719 else
1720 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1721 } else
1722 sndrnd = 1;
1723 toread = min_t(int, length, chunk);
1724 chip->read_buf(mtd, bufpoi, toread);
1725 bufpoi += toread;
1726 length -= toread;
1727 }
1728 if (length > 0)
1729 chip->read_buf(mtd, bufpoi, length);
1730
5c2ffb11 1731 return 0;
7bc3312b
TG		 1732}
1733
1734/**
7854d3f7 1735 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1736 * @mtd: mtd info structure
1737 * @chip: nand chip info structure
1738 * @page: page number to write
7bc3312b
TG		 1739 */
1740static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1741 int page)
1742{
1743 int status = 0;
1744 const uint8_t *buf = chip->oob_poi;
1745 int length = mtd->oobsize;
1746
1747 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1748 chip->write_buf(mtd, buf, length);
1749 /* Send command to program the OOB data */
1750 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1751
1752 status = chip->waitfunc(mtd, chip);
1753
0d420f9d 1754 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1755}
1756
1757/**
7854d3f7 1758 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1759 * with syndrome - only for large page flash
1760 * @mtd: mtd info structure
1761 * @chip: nand chip info structure
1762 * @page: page number to write
7bc3312b
TG		 1763 */
1764static int nand_write_oob_syndrome(struct mtd_info *mtd,
1765 struct nand_chip *chip, int page)
1766{
1767 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1768 int eccsize = chip->ecc.size, length = mtd->oobsize;
1769 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1770 const uint8_t *bufpoi = chip->oob_poi;
1771
1772 /*
1773 * data-ecc-data-ecc ... ecc-oob
1774 * or
1775 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1776 */
1777 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1778 pos = steps * (eccsize + chunk);
1779 steps = 0;
1780 } else
8b0036ee 1781 pos = eccsize;
7bc3312b
TG		 1782
1783 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1784 for (i = 0; i < steps; i++) {
1785 if (sndcmd) {
1786 if (mtd->writesize <= 512) {
1787 uint32_t fill = 0xFFFFFFFF;
1788
1789 len = eccsize;
1790 while (len > 0) {
1791 int num = min_t(int, len, 4);
1792 chip->write_buf(mtd, (uint8_t *)&fill,
1793 num);
1794 len -= num;
1795 }
1796 } else {
1797 pos = eccsize + i * (eccsize + chunk);
1798 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1799 }
1800 } else
1801 sndcmd = 1;
1802 len = min_t(int, length, chunk);
1803 chip->write_buf(mtd, bufpoi, len);
1804 bufpoi += len;
1805 length -= len;
1806 }
1807 if (length > 0)
1808 chip->write_buf(mtd, bufpoi, length);
1809
1810 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1811 status = chip->waitfunc(mtd, chip);
1812
1813 return status & NAND_STATUS_FAIL ? -EIO : 0;
1814}
1815
1da177e4 1816/**
7854d3f7 1817 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1818 * @mtd: MTD device structure
1819 * @from: offset to read from
1820 * @ops: oob operations description structure
1da177e4 1821 *
8b6e50c9 1822 * NAND read out-of-band data from the spare area.
1da177e4 1823 */
8593fbc6
TG		 1824static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1825 struct mtd_oob_ops *ops)
1da177e4 1826{
c00a0991 1827 int page, realpage, chipnr;
ace4dfee 1828 struct nand_chip *chip = mtd->priv;
041e4575 1829 struct mtd_ecc_stats stats;
7014568b
VW		 1830 int readlen = ops->ooblen;
1831 int len;
7bc3312b 1832 uint8_t *buf = ops->oobbuf;
1951f2f7 1833 int ret = 0;
61b03bd7 1834
289c0522 1835 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1836 __func__, (unsigned long long)from, readlen);
1da177e4 1837
041e4575
BN		 1838 stats = mtd->ecc_stats;
1839
0612b9dd 1840 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1841 len = chip->ecc.layout->oobavail;
03736155
AH		 1842 else
1843 len = mtd->oobsize;
1844
1845 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1846 pr_debug("%s: attempt to start read outside oob\n",
1847 __func__);
03736155
AH		 1848 return -EINVAL;
1849 }
1850
1851 /* Do not allow reads past end of device */
1852 if (unlikely(from >= mtd->size ||
1853 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1854 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1855 pr_debug("%s: attempt to read beyond end of device\n",
1856 __func__);
03736155
AH		 1857 return -EINVAL;
1858 }
7014568b 1859
7314e9e7 1860 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1861 chip->select_chip(mtd, chipnr);
1da177e4 1862
7314e9e7
TG		 1863 /* Shift to get page */
1864 realpage = (int)(from >> chip->page_shift);
1865 page = realpage & chip->pagemask;
1da177e4 1866
f8ac0414 1867 while (1) {
0612b9dd 1868 if (ops->mode == MTD_OPS_RAW)
1951f2f7 1869 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 1870 else
1951f2f7
SL		 1871 ret = chip->ecc.read_oob(mtd, chip, page);
1872
1873 if (ret < 0)
1874 break;
7014568b
VW		 1875
1876 len = min(len, readlen);
1877 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1878
5bc7c33c
BN		 1879 if (chip->options & NAND_NEED_READRDY) {
1880 /* Apply delay or wait for ready/busy pin */
1881 if (!chip->dev_ready)
1882 udelay(chip->chip_delay);
1883 else
1884 nand_wait_ready(mtd);
1885 }
1886
7014568b 1887 readlen -= len;
0d420f9d
SZ		 1888 if (!readlen)
1889 break;
1890
7314e9e7
TG		 1891 /* Increment page address */
1892 realpage++;
1893
1894 page = realpage & chip->pagemask;
1895 /* Check, if we cross a chip boundary */
1896 if (!page) {
1897 chipnr++;
1898 chip->select_chip(mtd, -1);
1899 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1900 }
1901 }
b0bb6903 1902 chip->select_chip(mtd, -1);
1da177e4 1903
1951f2f7
SL		 1904 ops->oobretlen = ops->ooblen - readlen;
1905
1906 if (ret < 0)
1907 return ret;
041e4575
BN		 1908
1909 if (mtd->ecc_stats.failed - stats.failed)
1910 return -EBADMSG;
1911
1912 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1913}
1914
1915/**
8593fbc6 1916 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1917 * @mtd: MTD device structure
1918 * @from: offset to read from
1919 * @ops: oob operation description structure
1da177e4 1920 *
8b6e50c9 1921 * NAND read data and/or out-of-band data.
1da177e4 1922 */
8593fbc6
TG		 1923static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1924 struct mtd_oob_ops *ops)
1da177e4 1925{
8593fbc6
TG		 1926 int ret = -ENOTSUPP;
1927
1928 ops->retlen = 0;
1da177e4
LT		 1929
1930 /* Do not allow reads past end of device */
7014568b 1931 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1932 pr_debug("%s: attempt to read beyond end of device\n",
1933 __func__);
1da177e4
LT		 1934 return -EINVAL;
1935 }
1936
6a8214aa 1937 nand_get_device(mtd, FL_READING);
1da177e4 1938
f8ac0414 1939 switch (ops->mode) {
0612b9dd
BN		 1940 case MTD_OPS_PLACE_OOB:
1941 case MTD_OPS_AUTO_OOB:
1942 case MTD_OPS_RAW:
8593fbc6 1943 break;
1da177e4 1944
8593fbc6
TG		 1945 default:
1946 goto out;
1947 }
1da177e4 1948
8593fbc6
TG		 1949 if (!ops->datbuf)
1950 ret = nand_do_read_oob(mtd, from, ops);
1951 else
1952 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1953
7351d3a5 1954out:
8593fbc6
TG		 1955 nand_release_device(mtd);
1956 return ret;
1957}
61b03bd7 1958
1da177e4 1959
8593fbc6 1960/**
7854d3f7 1961 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1962 * @mtd: mtd info structure
1963 * @chip: nand chip info structure
1964 * @buf: data buffer
1fbb938d 1965 * @oob_required: must write chip->oob_poi to OOB
52ff49df 1966 *
7854d3f7 1967 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 1968 */
fdbad98d 1969static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1970 const uint8_t *buf, int oob_required)
8593fbc6
TG		 1971{
1972 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1973 if (oob_required)
1974 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1975
1976 return 0;
1da177e4
LT		 1977}
1978
52ff49df 1979/**
7854d3f7 1980 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1981 * @mtd: mtd info structure
1982 * @chip: nand chip info structure
1983 * @buf: data buffer
1fbb938d 1984 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 1985 *
1986 * We need a special oob layout and handling even when ECC isn't checked.
1987 */
fdbad98d 1988static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 1989 struct nand_chip *chip,
1fbb938d 1990 const uint8_t *buf, int oob_required)
52ff49df
DB		 1991{
1992 int eccsize = chip->ecc.size;
1993 int eccbytes = chip->ecc.bytes;
1994 uint8_t *oob = chip->oob_poi;
1995 int steps, size;
1996
1997 for (steps = chip->ecc.steps; steps > 0; steps--) {
1998 chip->write_buf(mtd, buf, eccsize);
1999 buf += eccsize;
2000
2001 if (chip->ecc.prepad) {
2002 chip->write_buf(mtd, oob, chip->ecc.prepad);
2003 oob += chip->ecc.prepad;
2004 }
2005
60c3bc1f 2006 chip->write_buf(mtd, oob, eccbytes);
52ff49df
DB		 2007 oob += eccbytes;
2008
2009 if (chip->ecc.postpad) {
2010 chip->write_buf(mtd, oob, chip->ecc.postpad);
2011 oob += chip->ecc.postpad;
2012 }
2013 }
2014
2015 size = mtd->oobsize - (oob - chip->oob_poi);
2016 if (size)
2017 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 2018
2019 return 0;
52ff49df 2020}
9223a456 2021/**
7854d3f7 2022 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 2023 * @mtd: mtd info structure
2024 * @chip: nand chip info structure
2025 * @buf: data buffer
1fbb938d 2026 * @oob_required: must write chip->oob_poi to OOB
9223a456 2027 */
fdbad98d 2028static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2029 const uint8_t *buf, int oob_required)
9223a456 2030{
f75e5097
TG		 2031 int i, eccsize = chip->ecc.size;
2032 int eccbytes = chip->ecc.bytes;
2033 int eccsteps = chip->ecc.steps;
4bf63fcb 2034 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2035 const uint8_t *p = buf;
8b099a39 2036 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2037
7854d3f7 2038 /* Software ECC calculation */
8593fbc6
TG		 2039 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2040 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 2041
8593fbc6
TG		 2042 for (i = 0; i < chip->ecc.total; i++)
2043 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 2044
fdbad98d 2045 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 2046}
9223a456 2047
f75e5097 2048/**
7854d3f7 2049 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2050 * @mtd: mtd info structure
2051 * @chip: nand chip info structure
2052 * @buf: data buffer
1fbb938d 2053 * @oob_required: must write chip->oob_poi to OOB
f75e5097 2054 */
fdbad98d 2055static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2056 const uint8_t *buf, int oob_required)
f75e5097
TG		 2057{
2058 int i, eccsize = chip->ecc.size;
2059 int eccbytes = chip->ecc.bytes;
2060 int eccsteps = chip->ecc.steps;
4bf63fcb 2061 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2062 const uint8_t *p = buf;
8b099a39 2063 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2064
f75e5097
TG		 2065 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2066 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2067 chip->write_buf(mtd, p, eccsize);
f75e5097 2068 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2069 }
2070
f75e5097
TG		 2071 for (i = 0; i < chip->ecc.total; i++)
2072 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2073
2074 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2075
2076 return 0;
9223a456
TG		 2077}
2078
837a6ba4
GP		 2079
2080/**
2081 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2082 * @mtd: mtd info structure
2083 * @chip: nand chip info structure
d6a95080 2084 * @offset: column address of subpage within the page
837a6ba4 2085 * @data_len: data length
d6a95080 2086 * @buf: data buffer
837a6ba4
GP		 2087 * @oob_required: must write chip->oob_poi to OOB
2088 */
2089static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2090 struct nand_chip *chip, uint32_t offset,
d6a95080 2091 uint32_t data_len, const uint8_t *buf,
837a6ba4
GP		 2092 int oob_required)
2093{
2094 uint8_t *oob_buf = chip->oob_poi;
2095 uint8_t *ecc_calc = chip->buffers->ecccalc;
2096 int ecc_size = chip->ecc.size;
2097 int ecc_bytes = chip->ecc.bytes;
2098 int ecc_steps = chip->ecc.steps;
2099 uint32_t *eccpos = chip->ecc.layout->eccpos;
2100 uint32_t start_step = offset / ecc_size;
2101 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2102 int oob_bytes = mtd->oobsize / ecc_steps;
2103 int step, i;
2104
2105 for (step = 0; step < ecc_steps; step++) {
2106 /* configure controller for WRITE access */
2107 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2108
2109 /* write data (untouched subpages already masked by 0xFF) */
d6a95080 2110 chip->write_buf(mtd, buf, ecc_size);
837a6ba4
GP		 2111
2112 /* mask ECC of un-touched subpages by padding 0xFF */
2113 if ((step < start_step) || (step > end_step))
2114 memset(ecc_calc, 0xff, ecc_bytes);
2115 else
d6a95080 2116 chip->ecc.calculate(mtd, buf, ecc_calc);
837a6ba4
GP		 2117
2118 /* mask OOB of un-touched subpages by padding 0xFF */
2119 /* if oob_required, preserve OOB metadata of written subpage */
2120 if (!oob_required || (step < start_step) || (step > end_step))
2121 memset(oob_buf, 0xff, oob_bytes);
2122
d6a95080 2123 buf += ecc_size;
837a6ba4
GP		 2124 ecc_calc += ecc_bytes;
2125 oob_buf += oob_bytes;
2126 }
2127
2128 /* copy calculated ECC for whole page to chip->buffer->oob */
2129 /* this include masked-value(0xFF) for unwritten subpages */
2130 ecc_calc = chip->buffers->ecccalc;
2131 for (i = 0; i < chip->ecc.total; i++)
2132 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2133
2134 /* write OOB buffer to NAND device */
2135 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2136
2137 return 0;
2138}
2139
2140
61b03bd7 2141/**
7854d3f7 2142 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2143 * @mtd: mtd info structure
2144 * @chip: nand chip info structure
2145 * @buf: data buffer
1fbb938d 2146 * @oob_required: must write chip->oob_poi to OOB
1da177e4 2147 *
8b6e50c9
BN		 2148 * The hw generator calculates the error syndrome automatically. Therefore we
2149 * need a special oob layout and handling.
f75e5097 2150 */
fdbad98d 2151static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 2152 struct nand_chip *chip,
2153 const uint8_t *buf, int oob_required)
1da177e4 2154{
f75e5097
TG		 2155 int i, eccsize = chip->ecc.size;
2156 int eccbytes = chip->ecc.bytes;
2157 int eccsteps = chip->ecc.steps;
2158 const uint8_t *p = buf;
2159 uint8_t *oob = chip->oob_poi;
1da177e4 2160
f75e5097 2161 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2162
f75e5097
TG		 2163 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2164 chip->write_buf(mtd, p, eccsize);
61b03bd7 2165
f75e5097
TG		 2166 if (chip->ecc.prepad) {
2167 chip->write_buf(mtd, oob, chip->ecc.prepad);
2168 oob += chip->ecc.prepad;
2169 }
2170
2171 chip->ecc.calculate(mtd, p, oob);
2172 chip->write_buf(mtd, oob, eccbytes);
2173 oob += eccbytes;
2174
2175 if (chip->ecc.postpad) {
2176 chip->write_buf(mtd, oob, chip->ecc.postpad);
2177 oob += chip->ecc.postpad;
1da177e4 2178 }
1da177e4 2179 }
f75e5097
TG		 2180
2181 /* Calculate remaining oob bytes */
7e4178f9 2182 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2183 if (i)
2184 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2185
2186 return 0;
f75e5097
TG		 2187}
2188
2189/**
956e944c 2190 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2191 * @mtd: MTD device structure
2192 * @chip: NAND chip descriptor
837a6ba4
GP		 2193 * @offset: address offset within the page
2194 * @data_len: length of actual data to be written
8b6e50c9 2195 * @buf: the data to write
1fbb938d 2196 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2197 * @page: page number to write
2198 * @cached: cached programming
2199 * @raw: use _raw version of write_page
f75e5097
TG		 2200 */
2201static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4
GP		 2202 uint32_t offset, int data_len, const uint8_t *buf,
2203 int oob_required, int page, int cached, int raw)
f75e5097 2204{
837a6ba4
GP		 2205 int status, subpage;
2206
2207 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2208 chip->ecc.write_subpage)
2209 subpage = offset || (data_len < mtd->writesize);
2210 else
2211 subpage = 0;
f75e5097
TG		 2212
2213 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2214
956e944c 2215 if (unlikely(raw))
837a6ba4
GP		 2216 status = chip->ecc.write_page_raw(mtd, chip, buf,
2217 oob_required);
2218 else if (subpage)
2219 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2220 buf, oob_required);
956e944c 2221 else
fdbad98d
JW		 2222 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2223
2224 if (status < 0)
2225 return status;
f75e5097
TG		 2226
2227 /*
7854d3f7 2228 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2229 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2230 */
2231 cached = 0;
2232
3239a6cd 2233 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2234
2235 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2236 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2237 /*
2238 * See if operation failed and additional status checks are
8b6e50c9 2239 * available.
f75e5097
TG		 2240 */
2241 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2242 status = chip->errstat(mtd, chip, FL_WRITING, status,
2243 page);
2244
2245 if (status & NAND_STATUS_FAIL)
2246 return -EIO;
2247 } else {
2248 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2249 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2250 }
2251
f75e5097 2252 return 0;
1da177e4
LT		 2253}
2254
8593fbc6 2255/**
7854d3f7 2256 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2257 * @mtd: MTD device structure
8b6e50c9
BN		 2258 * @oob: oob data buffer
2259 * @len: oob data write length
2260 * @ops: oob ops structure
8593fbc6 2261 */
f722013e
TAA		 2262static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2263 struct mtd_oob_ops *ops)
8593fbc6 2264{
f722013e
TAA		 2265 struct nand_chip *chip = mtd->priv;
2266
2267 /*
2268 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2269 * data from a previous OOB read.
2270 */
2271 memset(chip->oob_poi, 0xff, mtd->oobsize);
2272
f8ac0414 2273 switch (ops->mode) {
8593fbc6 2274
0612b9dd
BN		 2275 case MTD_OPS_PLACE_OOB:
2276 case MTD_OPS_RAW:
8593fbc6
TG		 2277 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2278 return oob + len;
2279
0612b9dd 2280 case MTD_OPS_AUTO_OOB: {
8593fbc6 2281 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2282 uint32_t boffs = 0, woffs = ops->ooboffs;
2283 size_t bytes = 0;
8593fbc6 2284
f8ac0414 2285 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2286 /* Write request not from offset 0? */
7bc3312b
TG		 2287 if (unlikely(woffs)) {
2288 if (woffs >= free->length) {
2289 woffs -= free->length;
2290 continue;
2291 }
2292 boffs = free->offset + woffs;
2293 bytes = min_t(size_t, len,
2294 (free->length - woffs));
2295 woffs = 0;
2296 } else {
2297 bytes = min_t(size_t, len, free->length);
2298 boffs = free->offset;
2299 }
8b0036ee 2300 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2301 oob += bytes;
2302 }
2303 return oob;
2304 }
2305 default:
2306 BUG();
2307 }
2308 return NULL;
2309}
2310
f8ac0414 2311#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2312
2313/**
7854d3f7 2314 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2315 * @mtd: MTD device structure
2316 * @to: offset to write to
2317 * @ops: oob operations description structure
1da177e4 2318 *
8b6e50c9 2319 * NAND write with ECC.
1da177e4 2320 */
8593fbc6
TG		 2321static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2322 struct mtd_oob_ops *ops)
1da177e4 2323{
29072b96 2324 int chipnr, realpage, page, blockmask, column;
ace4dfee 2325 struct nand_chip *chip = mtd->priv;
8593fbc6 2326 uint32_t writelen = ops->len;
782ce79a
ML		 2327
2328 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2329 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2330 mtd->oobavail : mtd->oobsize;
2331
8593fbc6
TG		 2332 uint8_t *oob = ops->oobbuf;
2333 uint8_t *buf = ops->datbuf;
837a6ba4 2334 int ret;
e47f3db4 2335 int oob_required = oob ? 1 : 0;
1da177e4 2336
8593fbc6 2337 ops->retlen = 0;
29072b96
TG		 2338 if (!writelen)
2339 return 0;
1da177e4 2340
8b6e50c9 2341 /* Reject writes, which are not page aligned */
8593fbc6 2342 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2343 pr_notice("%s: attempt to write non page aligned data\n",
2344 __func__);
1da177e4
LT		 2345 return -EINVAL;
2346 }
2347
29072b96 2348 column = to & (mtd->writesize - 1);
1da177e4 2349
6a930961
TG		 2350 chipnr = (int)(to >> chip->chip_shift);
2351 chip->select_chip(mtd, chipnr);
2352
1da177e4 2353 /* Check, if it is write protected */
b0bb6903
HS		 2354 if (nand_check_wp(mtd)) {
2355 ret = -EIO;
2356 goto err_out;
2357 }
1da177e4 2358
f75e5097
TG		 2359 realpage = (int)(to >> chip->page_shift);
2360 page = realpage & chip->pagemask;
2361 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2362
2363 /* Invalidate the page cache, when we write to the cached page */
2364 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2365 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2366 chip->pagebuf = -1;
61b03bd7 2367
782ce79a 2368 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2369 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2370 ret = -EINVAL;
2371 goto err_out;
2372 }
782ce79a 2373
f8ac0414 2374 while (1) {
29072b96 2375 int bytes = mtd->writesize;
f75e5097 2376 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2377 uint8_t *wbuf = buf;
2378
8b6e50c9 2379 /* Partial page write? */
29072b96
TG		 2380 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2381 cached = 0;
2382 bytes = min_t(int, bytes - column, (int) writelen);
2383 chip->pagebuf = -1;
2384 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2385 memcpy(&chip->buffers->databuf[column], buf, bytes);
2386 wbuf = chip->buffers->databuf;
2387 }
1da177e4 2388
782ce79a
ML		 2389 if (unlikely(oob)) {
2390 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2391 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2392 oobwritelen -= len;
f722013e
TAA		 2393 } else {
2394 /* We still need to erase leftover OOB data */
2395 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2396 }
837a6ba4
GP		 2397 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2398 oob_required, page, cached,
2399 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2400 if (ret)
2401 break;
2402
2403 writelen -= bytes;
2404 if (!writelen)
2405 break;
2406
29072b96 2407 column = 0;
f75e5097
TG		 2408 buf += bytes;
2409 realpage++;
2410
2411 page = realpage & chip->pagemask;
2412 /* Check, if we cross a chip boundary */
2413 if (!page) {
2414 chipnr++;
2415 chip->select_chip(mtd, -1);
2416 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2417 }
2418 }
8593fbc6 2419
8593fbc6 2420 ops->retlen = ops->len - writelen;
7014568b
VW		 2421 if (unlikely(oob))
2422 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2423
2424err_out:
2425 chip->select_chip(mtd, -1);
1da177e4
LT		 2426 return ret;
2427}
2428
2af7c653
SK		 2429/**
2430 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2431 * @mtd: MTD device structure
2432 * @to: offset to write to
2433 * @len: number of bytes to write
2434 * @retlen: pointer to variable to store the number of written bytes
2435 * @buf: the data to write
2af7c653
SK		 2436 *
2437 * NAND write with ECC. Used when performing writes in interrupt context, this
2438 * may for example be called by mtdoops when writing an oops while in panic.
2439 */
2440static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2441 size_t *retlen, const uint8_t *buf)
2442{
2443 struct nand_chip *chip = mtd->priv;
4a89ff88 2444 struct mtd_oob_ops ops;
2af7c653
SK		 2445 int ret;
2446
8b6e50c9 2447 /* Wait for the device to get ready */
2af7c653
SK		 2448 panic_nand_wait(mtd, chip, 400);
2449
8b6e50c9 2450 /* Grab the device */
2af7c653
SK		 2451 panic_nand_get_device(chip, mtd, FL_WRITING);
2452
4a89ff88
BN		 2453 ops.len = len;
2454 ops.datbuf = (uint8_t *)buf;
2455 ops.oobbuf = NULL;
11041ae6 2456 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2457
4a89ff88 2458 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2459
4a89ff88 2460 *retlen = ops.retlen;
2af7c653
SK		 2461 return ret;
2462}
2463
f75e5097 2464/**
8593fbc6 2465 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2466 * @mtd: MTD device structure
2467 * @to: offset to write to
2468 * @len: number of bytes to write
2469 * @retlen: pointer to variable to store the number of written bytes
2470 * @buf: the data to write
f75e5097 2471 *
8b6e50c9 2472 * NAND write with ECC.
f75e5097 2473 */
8593fbc6
TG		 2474static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2475 size_t *retlen, const uint8_t *buf)
f75e5097 2476{
4a89ff88 2477 struct mtd_oob_ops ops;
f75e5097
TG		 2478 int ret;
2479
6a8214aa 2480 nand_get_device(mtd, FL_WRITING);
4a89ff88
BN		 2481 ops.len = len;
2482 ops.datbuf = (uint8_t *)buf;
2483 ops.oobbuf = NULL;
11041ae6 2484 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2485 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2486 *retlen = ops.retlen;
f75e5097 2487 nand_release_device(mtd);
8593fbc6 2488 return ret;
f75e5097 2489}
7314e9e7 2490
1da177e4 2491/**
8593fbc6 2492 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2493 * @mtd: MTD device structure
2494 * @to: offset to write to
2495 * @ops: oob operation description structure
1da177e4 2496 *
8b6e50c9 2497 * NAND write out-of-band.
1da177e4 2498 */
8593fbc6
TG		 2499static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2500 struct mtd_oob_ops *ops)
1da177e4 2501{
03736155 2502 int chipnr, page, status, len;
ace4dfee 2503 struct nand_chip *chip = mtd->priv;
1da177e4 2504
289c0522 2505 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2506 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2507
0612b9dd 2508 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2509 len = chip->ecc.layout->oobavail;
2510 else
2511 len = mtd->oobsize;
2512
1da177e4 2513 /* Do not allow write past end of page */
03736155 2514 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2515 pr_debug("%s: attempt to write past end of page\n",
2516 __func__);
1da177e4
LT		 2517 return -EINVAL;
2518 }
2519
03736155 2520 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2521 pr_debug("%s: attempt to start write outside oob\n",
2522 __func__);
03736155
AH		 2523 return -EINVAL;
2524 }
2525
775adc3d 2526 /* Do not allow write past end of device */
03736155
AH		 2527 if (unlikely(to >= mtd->size ||
2528 ops->ooboffs + ops->ooblen >
2529 ((mtd->size >> chip->page_shift) -
2530 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2531 pr_debug("%s: attempt to write beyond end of device\n",
2532 __func__);
03736155
AH		 2533 return -EINVAL;
2534 }
2535
7314e9e7 2536 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2537 chip->select_chip(mtd, chipnr);
1da177e4 2538
7314e9e7
TG		 2539 /* Shift to get page */
2540 page = (int)(to >> chip->page_shift);
2541
2542 /*
2543 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2544 * of my DiskOnChip 2000 test units) will clear the whole data page too
2545 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2546 * it in the doc2000 driver in August 1999. dwmw2.
2547 */
ace4dfee 2548 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2549
2550 /* Check, if it is write protected */
b0bb6903
HS		 2551 if (nand_check_wp(mtd)) {
2552 chip->select_chip(mtd, -1);
8593fbc6 2553 return -EROFS;
b0bb6903 2554 }
61b03bd7 2555
1da177e4 2556 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2557 if (page == chip->pagebuf)
2558 chip->pagebuf = -1;
1da177e4 2559
f722013e 2560 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2561
0612b9dd 2562 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2563 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2564 else
2565 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2566
b0bb6903
HS		 2567 chip->select_chip(mtd, -1);
2568
7bc3312b
TG		 2569 if (status)
2570 return status;
1da177e4 2571
7014568b 2572 ops->oobretlen = ops->ooblen;
1da177e4 2573
7bc3312b 2574 return 0;
8593fbc6
TG		 2575}
2576
2577/**
2578 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2579 * @mtd: MTD device structure
2580 * @to: offset to write to
2581 * @ops: oob operation description structure
8593fbc6
TG		 2582 */
2583static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2584 struct mtd_oob_ops *ops)
2585{
8593fbc6
TG		 2586 int ret = -ENOTSUPP;
2587
2588 ops->retlen = 0;
2589
2590 /* Do not allow writes past end of device */
7014568b 2591 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2592 pr_debug("%s: attempt to write beyond end of device\n",
2593 __func__);
8593fbc6
TG		 2594 return -EINVAL;
2595 }
2596
6a8214aa 2597 nand_get_device(mtd, FL_WRITING);
8593fbc6 2598
f8ac0414 2599 switch (ops->mode) {
0612b9dd
BN		 2600 case MTD_OPS_PLACE_OOB:
2601 case MTD_OPS_AUTO_OOB:
2602 case MTD_OPS_RAW:
8593fbc6
TG		 2603 break;
2604
2605 default:
2606 goto out;
2607 }
2608
2609 if (!ops->datbuf)
2610 ret = nand_do_write_oob(mtd, to, ops);
2611 else
2612 ret = nand_do_write_ops(mtd, to, ops);
2613
7351d3a5 2614out:
1da177e4 2615 nand_release_device(mtd);
1da177e4
LT		 2616 return ret;
2617}
2618
1da177e4 2619/**
49c50b97 2620 * single_erase - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2621 * @mtd: MTD device structure
2622 * @page: the page address of the block which will be erased
1da177e4 2623 *
49c50b97 2624 * Standard erase command for NAND chips. Returns NAND status.
1da177e4 2625 */
49c50b97 2626static int single_erase(struct mtd_info *mtd, int page)
1da177e4 2627{
ace4dfee 2628 struct nand_chip *chip = mtd->priv;
1da177e4 2629 /* Send commands to erase a block */
ace4dfee
TG		 2630 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2631 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
49c50b97
BN		 2632
2633 return chip->waitfunc(mtd, chip);
1da177e4
LT		 2634}
2635
1da177e4
LT		 2636/**
2637 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2638 * @mtd: MTD device structure
2639 * @instr: erase instruction
1da177e4 2640 *
8b6e50c9 2641 * Erase one ore more blocks.
1da177e4 2642 */
e0c7d767 2643static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2644{
e0c7d767 2645 return nand_erase_nand(mtd, instr, 0);
1da177e4 2646}
61b03bd7 2647
1da177e4 2648/**
7854d3f7 2649 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2650 * @mtd: MTD device structure
2651 * @instr: erase instruction
2652 * @allowbbt: allow erasing the bbt area
1da177e4 2653 *
8b6e50c9 2654 * Erase one ore more blocks.
1da177e4 2655 */
ace4dfee
TG		 2656int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2657 int allowbbt)
1da177e4 2658{
69423d99 2659 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2660 struct nand_chip *chip = mtd->priv;
69423d99 2661 loff_t len;
1da177e4 2662
289c0522
BN		 2663 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2664 __func__, (unsigned long long)instr->addr,
2665 (unsigned long long)instr->len);
1da177e4 2666
6fe5a6ac 2667 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2668 return -EINVAL;
1da177e4 2669
1da177e4 2670 /* Grab the lock and see if the device is available */
6a8214aa 2671 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 2672
2673 /* Shift to get first page */
ace4dfee
TG		 2674 page = (int)(instr->addr >> chip->page_shift);
2675 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2676
2677 /* Calculate pages in each block */
ace4dfee 2678 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2679
2680 /* Select the NAND device */
ace4dfee 2681 chip->select_chip(mtd, chipnr);
1da177e4 2682
1da177e4
LT		 2683 /* Check, if it is write protected */
2684 if (nand_check_wp(mtd)) {
289c0522
BN		 2685 pr_debug("%s: device is write protected!\n",
2686 __func__);
1da177e4
LT		 2687 instr->state = MTD_ERASE_FAILED;
2688 goto erase_exit;
2689 }
2690
2691 /* Loop through the pages */
2692 len = instr->len;
2693
2694 instr->state = MTD_ERASING;
2695
2696 while (len) {
12183a20 2697 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2698 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2699 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2700 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2701 __func__, page);
1da177e4
LT		 2702 instr->state = MTD_ERASE_FAILED;
2703 goto erase_exit;
2704 }
61b03bd7 2705
ace4dfee
TG		 2706 /*
2707 * Invalidate the page cache, if we erase the block which
8b6e50c9 2708 * contains the current cached page.
ace4dfee
TG		 2709 */
2710 if (page <= chip->pagebuf && chip->pagebuf <
2711 (page + pages_per_block))
2712 chip->pagebuf = -1;
1da177e4 2713
49c50b97 2714 status = chip->erase(mtd, page & chip->pagemask);
1da177e4 2715
ace4dfee
TG		 2716 /*
2717 * See if operation failed and additional status checks are
2718 * available
2719 */
2720 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2721 status = chip->errstat(mtd, chip, FL_ERASING,
2722 status, page);
068e3c0a 2723
1da177e4 2724 /* See if block erase succeeded */
a4ab4c5d 2725 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2726 pr_debug("%s: failed erase, page 0x%08x\n",
2727 __func__, page);
1da177e4 2728 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2729 instr->fail_addr =
2730 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2731 goto erase_exit;
2732 }
30f464b7 2733
1da177e4 2734 /* Increment page address and decrement length */
daae74ca 2735 len -= (1ULL << chip->phys_erase_shift);
1da177e4
LT		 2736 page += pages_per_block;
2737
2738 /* Check, if we cross a chip boundary */
ace4dfee 2739 if (len && !(page & chip->pagemask)) {
1da177e4 2740 chipnr++;
ace4dfee
TG		 2741 chip->select_chip(mtd, -1);
2742 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2743 }
2744 }
2745 instr->state = MTD_ERASE_DONE;
2746
7351d3a5 2747erase_exit:
1da177e4
LT		 2748
2749 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2750
2751 /* Deselect and wake up anyone waiting on the device */
b0bb6903 2752 chip->select_chip(mtd, -1);
1da177e4
LT		 2753 nand_release_device(mtd);
2754
49defc01
DW		 2755 /* Do call back function */
2756 if (!ret)
2757 mtd_erase_callback(instr);
2758
1da177e4
LT		 2759 /* Return more or less happy */
2760 return ret;
2761}
2762
2763/**
2764 * nand_sync - [MTD Interface] sync
8b6e50c9 2765 * @mtd: MTD device structure
1da177e4 2766 *
8b6e50c9 2767 * Sync is actually a wait for chip ready function.
1da177e4 2768 */
e0c7d767 2769static void nand_sync(struct mtd_info *mtd)
1da177e4 2770{
289c0522 2771 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2772
2773 /* Grab the lock and see if the device is available */
6a8214aa 2774 nand_get_device(mtd, FL_SYNCING);
1da177e4 2775 /* Release it and go back */
e0c7d767 2776 nand_release_device(mtd);
1da177e4
LT		 2777}
2778
1da177e4 2779/**
ace4dfee 2780 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2781 * @mtd: MTD device structure
2782 * @offs: offset relative to mtd start
1da177e4 2783 */
ace4dfee 2784static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2785{
ace4dfee 2786 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2787}
2788
2789/**
ace4dfee 2790 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2791 * @mtd: MTD device structure
2792 * @ofs: offset relative to mtd start
1da177e4 2793 */
e0c7d767 2794static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2795{
1da177e4
LT		 2796 int ret;
2797
f8ac0414
FF		 2798 ret = nand_block_isbad(mtd, ofs);
2799 if (ret) {
8b6e50c9 2800 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2801 if (ret > 0)
2802 return 0;
e0c7d767
DW		 2803 return ret;
2804 }
1da177e4 2805
5a0edb25 2806 return nand_block_markbad_lowlevel(mtd, ofs);
1da177e4
LT		 2807}
2808
7db03ecc
HS		 2809/**
2810 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2811 * @mtd: MTD device structure
2812 * @chip: nand chip info structure
2813 * @addr: feature address.
2814 * @subfeature_param: the subfeature parameters, a four bytes array.
2815 */
2816static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2817 int addr, uint8_t *subfeature_param)
2818{
2819 int status;
05f78359 2820 int i;
7db03ecc 2821
d914c932
DM		 2822 if (!chip->onfi_version ||
2823 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2824 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 2825 return -EINVAL;
2826
2827 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
05f78359
UKK		 2828 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2829 chip->write_byte(mtd, subfeature_param[i]);
2830
7db03ecc
HS		 2831 status = chip->waitfunc(mtd, chip);
2832 if (status & NAND_STATUS_FAIL)
2833 return -EIO;
2834 return 0;
2835}
2836
2837/**
2838 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2839 * @mtd: MTD device structure
2840 * @chip: nand chip info structure
2841 * @addr: feature address.
2842 * @subfeature_param: the subfeature parameters, a four bytes array.
2843 */
2844static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2845 int addr, uint8_t *subfeature_param)
2846{
05f78359
UKK		 2847 int i;
2848
d914c932
DM		 2849 if (!chip->onfi_version ||
2850 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2851 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 2852 return -EINVAL;
2853
2854 /* clear the sub feature parameters */
2855 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2856
2857 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
05f78359
UKK		 2858 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2859 *subfeature_param++ = chip->read_byte(mtd);
7db03ecc
HS		 2860 return 0;
2861}
2862
962034f4
VW		 2863/**
2864 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2865 * @mtd: MTD device structure
962034f4
VW		 2866 */
2867static int nand_suspend(struct mtd_info *mtd)
2868{
6a8214aa 2869 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 2870}
2871
2872/**
2873 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2874 * @mtd: MTD device structure
962034f4
VW		 2875 */
2876static void nand_resume(struct mtd_info *mtd)
2877{
ace4dfee 2878 struct nand_chip *chip = mtd->priv;
962034f4 2879
ace4dfee 2880 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2881 nand_release_device(mtd);
2882 else
d0370219
BN		 2883 pr_err("%s called for a chip which is not in suspended state\n",
2884 __func__);
962034f4
VW		 2885}
2886
8b6e50c9 2887/* Set default functions */
ace4dfee 2888static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2889{
1da177e4 2890 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2891 if (!chip->chip_delay)
2892 chip->chip_delay = 20;
1da177e4
LT		 2893
2894 /* check, if a user supplied command function given */
ace4dfee
TG		 2895 if (chip->cmdfunc == NULL)
2896 chip->cmdfunc = nand_command;
1da177e4
LT		 2897
2898 /* check, if a user supplied wait function given */
ace4dfee
TG		 2899 if (chip->waitfunc == NULL)
2900 chip->waitfunc = nand_wait;
2901
2902 if (!chip->select_chip)
2903 chip->select_chip = nand_select_chip;
68e80780 2904
4204cccd
HS		 2905 /* set for ONFI nand */
2906 if (!chip->onfi_set_features)
2907 chip->onfi_set_features = nand_onfi_set_features;
2908 if (!chip->onfi_get_features)
2909 chip->onfi_get_features = nand_onfi_get_features;
2910
68e80780
BN		 2911 /* If called twice, pointers that depend on busw may need to be reset */
2912 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 2913 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2914 if (!chip->read_word)
2915 chip->read_word = nand_read_word;
2916 if (!chip->block_bad)
2917 chip->block_bad = nand_block_bad;
2918 if (!chip->block_markbad)
2919 chip->block_markbad = nand_default_block_markbad;
68e80780 2920 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 2921 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
05f78359
UKK		 2922 if (!chip->write_byte || chip->write_byte == nand_write_byte)
2923 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
68e80780 2924 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 2925 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 2926 if (!chip->scan_bbt)
2927 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2928
2929 if (!chip->controller) {
2930 chip->controller = &chip->hwcontrol;
2931 spin_lock_init(&chip->controller->lock);
2932 init_waitqueue_head(&chip->controller->wq);
2933 }
2934
7aa65bfd
TG		 2935}
2936
8b6e50c9 2937/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2938static void sanitize_string(uint8_t *s, size_t len)
2939{
2940 ssize_t i;
2941
8b6e50c9 2942 /* Null terminate */
d1e1f4e4
FF		 2943 s[len - 1] = 0;
2944
8b6e50c9 2945 /* Remove non printable chars */
d1e1f4e4
FF		 2946 for (i = 0; i < len - 1; i++) {
2947 if (s[i] < ' ' || s[i] > 127)
2948 s[i] = '?';
2949 }
2950
8b6e50c9 2951 /* Remove trailing spaces */
d1e1f4e4
FF		 2952 strim(s);
2953}
2954
2955static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2956{
2957 int i;
2958 while (len--) {
2959 crc ^= *p++ << 8;
2960 for (i = 0; i < 8; i++)
2961 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2962 }
2963
2964 return crc;
2965}
2966
6dcbe0cd
HS		 2967/* Parse the Extended Parameter Page. */
2968static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
2969 struct nand_chip *chip, struct nand_onfi_params *p)
2970{
2971 struct onfi_ext_param_page *ep;
2972 struct onfi_ext_section *s;
2973 struct onfi_ext_ecc_info *ecc;
2974 uint8_t *cursor;
2975 int ret = -EINVAL;
2976 int len;
2977 int i;
2978
2979 len = le16_to_cpu(p->ext_param_page_length) * 16;
2980 ep = kmalloc(len, GFP_KERNEL);
5cb13271
BN		 2981 if (!ep)
2982 return -ENOMEM;
6dcbe0cd
HS		 2983
2984 /* Send our own NAND_CMD_PARAM. */
2985 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2986
2987 /* Use the Change Read Column command to skip the ONFI param pages. */
2988 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
2989 sizeof(*p) * p->num_of_param_pages , -1);
2990
2991 /* Read out the Extended Parameter Page. */
2992 chip->read_buf(mtd, (uint8_t *)ep, len);
2993 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
2994 != le16_to_cpu(ep->crc))) {
2995 pr_debug("fail in the CRC.\n");
2996 goto ext_out;
2997 }
2998
2999 /*
3000 * Check the signature.
3001 * Do not strictly follow the ONFI spec, maybe changed in future.
3002 */
3003 if (strncmp(ep->sig, "EPPS", 4)) {
3004 pr_debug("The signature is invalid.\n");
3005 goto ext_out;
3006 }
3007
3008 /* find the ECC section. */
3009 cursor = (uint8_t *)(ep + 1);
3010 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3011 s = ep->sections + i;
3012 if (s->type == ONFI_SECTION_TYPE_2)
3013 break;
3014 cursor += s->length * 16;
3015 }
3016 if (i == ONFI_EXT_SECTION_MAX) {
3017 pr_debug("We can not find the ECC section.\n");
3018 goto ext_out;
3019 }
3020
3021 /* get the info we want. */
3022 ecc = (struct onfi_ext_ecc_info *)cursor;
3023
4ae7d228
BN		 3024 if (!ecc->codeword_size) {
3025 pr_debug("Invalid codeword size\n");
3026 goto ext_out;
6dcbe0cd
HS		 3027 }
3028
4ae7d228
BN		 3029 chip->ecc_strength_ds = ecc->ecc_bits;
3030 chip->ecc_step_ds = 1 << ecc->codeword_size;
5cb13271 3031 ret = 0;
6dcbe0cd
HS		 3032
3033ext_out:
3034 kfree(ep);
3035 return ret;
3036}
3037
8429bb39
BN		 3038static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3039{
3040 struct nand_chip *chip = mtd->priv;
3041 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3042
3043 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3044 feature);
3045}
3046
3047/*
3048 * Configure chip properties from Micron vendor-specific ONFI table
3049 */
3050static void nand_onfi_detect_micron(struct nand_chip *chip,
3051 struct nand_onfi_params *p)
3052{
3053 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3054
3055 if (le16_to_cpu(p->vendor_revision) < 1)
3056 return;
3057
3058 chip->read_retries = micron->read_retry_options;
3059 chip->setup_read_retry = nand_setup_read_retry_micron;
3060}
3061
6fb277ba 3062/*
8b6e50c9 3063 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 3064 */
3065static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 3066 int *busw)
6fb277ba
FF		 3067{
3068 struct nand_onfi_params *p = &chip->onfi_params;
bd9c6e99 3069 int i, j;
6fb277ba
FF		 3070 int val;
3071
7854d3f7 3072 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 3073 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3074 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3075 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3076 return 0;
3077
6fb277ba
FF		 3078 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3079 for (i = 0; i < 3; i++) {
bd9c6e99
BN		 3080 for (j = 0; j < sizeof(*p); j++)
3081 ((uint8_t *)p)[j] = chip->read_byte(mtd);
6fb277ba
FF		 3082 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3083 le16_to_cpu(p->crc)) {
6fb277ba
FF		 3084 break;
3085 }
3086 }
3087
c7f23a70
BN		 3088 if (i == 3) {
3089 pr_err("Could not find valid ONFI parameter page; aborting\n");
6fb277ba 3090 return 0;
c7f23a70 3091 }
6fb277ba 3092
8b6e50c9 3093 /* Check version */
6fb277ba 3094 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 3095 if (val & (1 << 5))
3096 chip->onfi_version = 23;
3097 else if (val & (1 << 4))
6fb277ba
FF		 3098 chip->onfi_version = 22;
3099 else if (val & (1 << 3))
3100 chip->onfi_version = 21;
3101 else if (val & (1 << 2))
3102 chip->onfi_version = 20;
b7b1a29d 3103 else if (val & (1 << 1))
6fb277ba 3104 chip->onfi_version = 10;
b7b1a29d
BN		 3105
3106 if (!chip->onfi_version) {
20171642 3107 pr_info("unsupported ONFI version: %d\n", val);
b7b1a29d
BN		 3108 return 0;
3109 }
6fb277ba
FF		 3110
3111 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3112 sanitize_string(p->model, sizeof(p->model));
3113 if (!mtd->name)
3114 mtd->name = p->model;
4355b70c 3115
6fb277ba 3116 mtd->writesize = le32_to_cpu(p->byte_per_page);
4355b70c
BN		 3117
3118 /*
3119 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3120 * (don't ask me who thought of this...). MTD assumes that these
3121 * dimensions will be power-of-2, so just truncate the remaining area.
3122 */
3123 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3124 mtd->erasesize *= mtd->writesize;
3125
6fb277ba 3126 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4355b70c
BN		 3127
3128 /* See erasesize comment */
3129 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3130 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
13fbd179 3131 chip->bits_per_cell = p->bits_per_cell;
e2985fc1
HS		 3132
3133 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
08c248fb 3134 *busw = NAND_BUSWIDTH_16;
e2985fc1
HS		 3135 else
3136 *busw = 0;
6fb277ba 3137
10c86bab
HS		 3138 if (p->ecc_bits != 0xff) {
3139 chip->ecc_strength_ds = p->ecc_bits;
3140 chip->ecc_step_ds = 512;
6dcbe0cd
HS		 3141 } else if (chip->onfi_version >= 21 &&
3142 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3143
3144 /*
3145 * The nand_flash_detect_ext_param_page() uses the
3146 * Change Read Column command which maybe not supported
3147 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3148 * now. We do not replace user supplied command function.
3149 */
3150 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3151 chip->cmdfunc = nand_command_lp;
3152
3153 /* The Extended Parameter Page is supported since ONFI 2.1. */
3154 if (nand_flash_detect_ext_param_page(mtd, chip, p))
c7f23a70
BN		 3155 pr_warn("Failed to detect ONFI extended param page\n");
3156 } else {
3157 pr_warn("Could not retrieve ONFI ECC requirements\n");
10c86bab
HS		 3158 }
3159
8429bb39
BN		 3160 if (p->jedec_id == NAND_MFR_MICRON)
3161 nand_onfi_detect_micron(chip, p);
3162
6fb277ba
FF		 3163 return 1;
3164}
3165
91361818
HS		 3166/*
3167 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3168 */
3169static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3170 int *busw)
3171{
3172 struct nand_jedec_params *p = &chip->jedec_params;
3173 struct jedec_ecc_info *ecc;
3174 int val;
3175 int i, j;
3176
3177 /* Try JEDEC for unknown chip or LP */
3178 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3179 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3180 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3181 chip->read_byte(mtd) != 'C')
3182 return 0;
3183
3184 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3185 for (i = 0; i < 3; i++) {
3186 for (j = 0; j < sizeof(*p); j++)
3187 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3188
3189 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3190 le16_to_cpu(p->crc))
3191 break;
3192 }
3193
3194 if (i == 3) {
3195 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3196 return 0;
3197 }
3198
3199 /* Check version */
3200 val = le16_to_cpu(p->revision);
3201 if (val & (1 << 2))
3202 chip->jedec_version = 10;
3203 else if (val & (1 << 1))
3204 chip->jedec_version = 1; /* vendor specific version */
3205
3206 if (!chip->jedec_version) {
3207 pr_info("unsupported JEDEC version: %d\n", val);
3208 return 0;
3209 }
3210
3211 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3212 sanitize_string(p->model, sizeof(p->model));
3213 if (!mtd->name)
3214 mtd->name = p->model;
3215
3216 mtd->writesize = le32_to_cpu(p->byte_per_page);
3217
3218 /* Please reference to the comment for nand_flash_detect_onfi. */
3219 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3220 mtd->erasesize *= mtd->writesize;
3221
3222 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3223
3224 /* Please reference to the comment for nand_flash_detect_onfi. */
3225 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3226 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3227 chip->bits_per_cell = p->bits_per_cell;
3228
3229 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3230 *busw = NAND_BUSWIDTH_16;
3231 else
3232 *busw = 0;
3233
3234 /* ECC info */
3235 ecc = &p->ecc_info[0];
3236
3237 if (ecc->codeword_size >= 9) {
3238 chip->ecc_strength_ds = ecc->ecc_bits;
3239 chip->ecc_step_ds = 1 << ecc->codeword_size;
3240 } else {
3241 pr_warn("Invalid codeword size\n");
3242 }
3243
3244 return 1;
3245}
3246
e3b88bd6
BN		 3247/*
3248 * nand_id_has_period - Check if an ID string has a given wraparound period
3249 * @id_data: the ID string
3250 * @arrlen: the length of the @id_data array
3251 * @period: the period of repitition
3252 *
3253 * Check if an ID string is repeated within a given sequence of bytes at
3254 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3255 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3256 * if the repetition has a period of @period; otherwise, returns zero.
3257 */
3258static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3259{
3260 int i, j;
3261 for (i = 0; i < period; i++)
3262 for (j = i + period; j < arrlen; j += period)
3263 if (id_data[i] != id_data[j])
3264 return 0;
3265 return 1;
3266}
3267
3268/*
3269 * nand_id_len - Get the length of an ID string returned by CMD_READID
3270 * @id_data: the ID string
3271 * @arrlen: the length of the @id_data array
3272
3273 * Returns the length of the ID string, according to known wraparound/trailing
3274 * zero patterns. If no pattern exists, returns the length of the array.
3275 */
3276static int nand_id_len(u8 *id_data, int arrlen)
3277{
3278 int last_nonzero, period;
3279
3280 /* Find last non-zero byte */
3281 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3282 if (id_data[last_nonzero])
3283 break;
3284
3285 /* All zeros */
3286 if (last_nonzero < 0)
3287 return 0;
3288
3289 /* Calculate wraparound period */
3290 for (period = 1; period < arrlen; period++)
3291 if (nand_id_has_period(id_data, arrlen, period))
3292 break;
3293
3294 /* There's a repeated pattern */
3295 if (period < arrlen)
3296 return period;
3297
3298 /* There are trailing zeros */
3299 if (last_nonzero < arrlen - 1)
3300 return last_nonzero + 1;
3301
3302 /* No pattern detected */
3303 return arrlen;
3304}
3305
7db906b7
HS		 3306/* Extract the bits of per cell from the 3rd byte of the extended ID */
3307static int nand_get_bits_per_cell(u8 cellinfo)
3308{
3309 int bits;
3310
3311 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3312 bits >>= NAND_CI_CELLTYPE_SHIFT;
3313 return bits + 1;
3314}
3315
fc09bbc0
BN		 3316/*
3317 * Many new NAND share similar device ID codes, which represent the size of the
3318 * chip. The rest of the parameters must be decoded according to generic or
3319 * manufacturer-specific "extended ID" decoding patterns.
3320 */
3321static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3322 u8 id_data[8], int *busw)
3323{
e3b88bd6 3324 int extid, id_len;
fc09bbc0 3325 /* The 3rd id byte holds MLC / multichip data */
7db906b7 3326 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
fc09bbc0
BN		 3327 /* The 4th id byte is the important one */
3328 extid = id_data[3];
3329
e3b88bd6
BN		 3330 id_len = nand_id_len(id_data, 8);
3331
fc09bbc0
BN		 3332 /*
3333 * Field definitions are in the following datasheets:
3334 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 3335 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 3336 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 3337 *
af451af4
BN		 3338 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3339 * ID to decide what to do.
fc09bbc0 3340 */
af451af4 3341 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
1d0ed69d 3342 !nand_is_slc(chip) && id_data[5] != 0x00) {
fc09bbc0
BN		 3343 /* Calc pagesize */
3344 mtd->writesize = 2048 << (extid & 0x03);
3345 extid >>= 2;
3346 /* Calc oobsize */
e2d3a35e 3347 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 3348 case 1:
3349 mtd->oobsize = 128;
3350 break;
3351 case 2:
3352 mtd->oobsize = 218;
3353 break;
3354 case 3:
3355 mtd->oobsize = 400;
3356 break;
e2d3a35e 3357 case 4:
fc09bbc0
BN		 3358 mtd->oobsize = 436;
3359 break;
e2d3a35e
BN		 3360 case 5:
3361 mtd->oobsize = 512;
3362 break;
3363 case 6:
e2d3a35e
BN		 3364 mtd->oobsize = 640;
3365 break;
94d04e82
HS		 3366 case 7:
3367 default: /* Other cases are "reserved" (unknown) */
3368 mtd->oobsize = 1024;
3369 break;
fc09bbc0
BN		 3370 }
3371 extid >>= 2;
3372 /* Calc blocksize */
3373 mtd->erasesize = (128 * 1024) <<
3374 (((extid >> 1) & 0x04) | (extid & 0x03));
3375 *busw = 0;
73ca392f 3376 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
1d0ed69d 3377 !nand_is_slc(chip)) {
73ca392f
BN		 3378 unsigned int tmp;
3379
3380 /* Calc pagesize */
3381 mtd->writesize = 2048 << (extid & 0x03);
3382 extid >>= 2;
3383 /* Calc oobsize */
3384 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3385 case 0:
3386 mtd->oobsize = 128;
3387 break;
3388 case 1:
3389 mtd->oobsize = 224;
3390 break;
3391 case 2:
3392 mtd->oobsize = 448;
3393 break;
3394 case 3:
3395 mtd->oobsize = 64;
3396 break;
3397 case 4:
3398 mtd->oobsize = 32;
3399 break;
3400 case 5:
3401 mtd->oobsize = 16;
3402 break;
3403 default:
3404 mtd->oobsize = 640;
3405 break;
3406 }
3407 extid >>= 2;
3408 /* Calc blocksize */
3409 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3410 if (tmp < 0x03)
3411 mtd->erasesize = (128 * 1024) << tmp;
3412 else if (tmp == 0x03)
3413 mtd->erasesize = 768 * 1024;
3414 else
3415 mtd->erasesize = (64 * 1024) << tmp;
3416 *busw = 0;
fc09bbc0
BN		 3417 } else {
3418 /* Calc pagesize */
3419 mtd->writesize = 1024 << (extid & 0x03);
3420 extid >>= 2;
3421 /* Calc oobsize */
3422 mtd->oobsize = (8 << (extid & 0x01)) *
3423 (mtd->writesize >> 9);
3424 extid >>= 2;
3425 /* Calc blocksize. Blocksize is multiples of 64KiB */
3426 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3427 extid >>= 2;
3428 /* Get buswidth information */
3429 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
60c67382
BN		 3430
3431 /*
3432 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3433 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3434 * follows:
3435 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3436 * 110b -> 24nm
3437 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3438 */
3439 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
1d0ed69d 3440 nand_is_slc(chip) &&
60c67382
BN		 3441 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3442 !(id_data[4] & 0x80) /* !BENAND */) {
3443 mtd->oobsize = 32 * mtd->writesize >> 9;
3444 }
3445
fc09bbc0
BN		 3446 }
3447}
3448
f23a481c
BN		 3449/*
3450 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3451 * decodes a matching ID table entry and assigns the MTD size parameters for
3452 * the chip.
3453 */
3454static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3455 struct nand_flash_dev *type, u8 id_data[8],
3456 int *busw)
3457{
3458 int maf_id = id_data[0];
3459
3460 mtd->erasesize = type->erasesize;
3461 mtd->writesize = type->pagesize;
3462 mtd->oobsize = mtd->writesize / 32;
3463 *busw = type->options & NAND_BUSWIDTH_16;
3464
1c195e90
HS		 3465 /* All legacy ID NAND are small-page, SLC */
3466 chip->bits_per_cell = 1;
3467
f23a481c
BN		 3468 /*
3469 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3470 * some Spansion chips have erasesize that conflicts with size
3471 * listed in nand_ids table.
3472 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3473 */
3474 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3475 && id_data[6] == 0x00 && id_data[7] == 0x00
3476 && mtd->writesize == 512) {
3477 mtd->erasesize = 128 * 1024;
3478 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3479 }
3480}
3481
7e74c2d7
BN		 3482/*
3483 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3484 * heuristic patterns using various detected parameters (e.g., manufacturer,
3485 * page size, cell-type information).
3486 */
3487static void nand_decode_bbm_options(struct mtd_info *mtd,
3488 struct nand_chip *chip, u8 id_data[8])
3489{
3490 int maf_id = id_data[0];
3491
3492 /* Set the bad block position */
3493 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3494 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3495 else
3496 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3497
3498 /*
3499 * Bad block marker is stored in the last page of each block on Samsung
3500 * and Hynix MLC devices; stored in first two pages of each block on
3501 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3502 * AMD/Spansion, and Macronix. All others scan only the first page.
3503 */
1d0ed69d 3504 if (!nand_is_slc(chip) &&
7e74c2d7
BN		 3505 (maf_id == NAND_MFR_SAMSUNG ||
3506 maf_id == NAND_MFR_HYNIX))
3507 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
1d0ed69d 3508 else if ((nand_is_slc(chip) &&
7e74c2d7
BN		 3509 (maf_id == NAND_MFR_SAMSUNG ||
3510 maf_id == NAND_MFR_HYNIX ||
3511 maf_id == NAND_MFR_TOSHIBA ||
3512 maf_id == NAND_MFR_AMD ||
3513 maf_id == NAND_MFR_MACRONIX)) ||
3514 (mtd->writesize == 2048 &&
3515 maf_id == NAND_MFR_MICRON))
3516 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3517}
3518
ec6e87e3
HS		 3519static inline bool is_full_id_nand(struct nand_flash_dev *type)
3520{
3521 return type->id_len;
3522}
3523
3524static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3525 struct nand_flash_dev *type, u8 *id_data, int *busw)
3526{
3527 if (!strncmp(type->id, id_data, type->id_len)) {
3528 mtd->writesize = type->pagesize;
3529 mtd->erasesize = type->erasesize;
3530 mtd->oobsize = type->oobsize;
3531
7db906b7 3532 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
ec6e87e3
HS		 3533 chip->chipsize = (uint64_t)type->chipsize << 20;
3534 chip->options |= type->options;
57219342
HS		 3535 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3536 chip->ecc_step_ds = NAND_ECC_STEP(type);
ec6e87e3
HS		 3537
3538 *busw = type->options & NAND_BUSWIDTH_16;
3539
092b6a1d
CZ		 3540 if (!mtd->name)
3541 mtd->name = type->name;
3542
ec6e87e3
HS		 3543 return true;
3544 }
3545 return false;
3546}
3547
7aa65bfd 3548/*
8b6e50c9 3549 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3550 */
3551static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3552 struct nand_chip *chip,
7351d3a5 3553 int *maf_id, int *dev_id,
5e81e88a 3554 struct nand_flash_dev *type)
7aa65bfd 3555{
bb77082f 3556 int busw;
d1e1f4e4 3557 int i, maf_idx;
426c457a 3558 u8 id_data[8];
1da177e4
LT		 3559
3560 /* Select the device */
ace4dfee 3561 chip->select_chip(mtd, 0);
1da177e4 3562
ef89a880
KB		 3563 /*
3564 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3565 * after power-up.
ef89a880
KB		 3566 */
3567 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3568
1da177e4 3569 /* Send the command for reading device ID */
ace4dfee 3570 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3571
3572 /* Read manufacturer and device IDs */
ace4dfee 3573 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3574 *dev_id = chip->read_byte(mtd);
1da177e4 3575
8b6e50c9
BN		 3576 /*
3577 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3578 * interface concerns can cause random data which looks like a
3579 * possibly credible NAND flash to appear. If the two results do
3580 * not match, ignore the device completely.
3581 */
3582
3583 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3584
4aef9b78
BN		 3585 /* Read entire ID string */
3586 for (i = 0; i < 8; i++)
426c457a 3587 id_data[i] = chip->read_byte(mtd);
ed8165c7 3588
d1e1f4e4 3589 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
20171642 3590 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
d0370219 3591 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3592 return ERR_PTR(-ENODEV);
3593 }
3594
7aa65bfd 3595 if (!type)
5e81e88a
DW		 3596 type = nand_flash_ids;
3597
ec6e87e3
HS		 3598 for (; type->name != NULL; type++) {
3599 if (is_full_id_nand(type)) {
3600 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3601 goto ident_done;
3602 } else if (*dev_id == type->dev_id) {
3603 break;
3604 }
3605 }
5e81e88a 3606
d1e1f4e4
FF		 3607 chip->onfi_version = 0;
3608 if (!type->name || !type->pagesize) {
35fc5195 3609 /* Check if the chip is ONFI compliant */
47450b35 3610 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3611 goto ident_done;
91361818
HS		 3612
3613 /* Check if the chip is JEDEC compliant */
3614 if (nand_flash_detect_jedec(mtd, chip, &busw))
3615 goto ident_done;
d1e1f4e4
FF		 3616 }
3617
5e81e88a 3618 if (!type->name)
7aa65bfd
TG		 3619 return ERR_PTR(-ENODEV);
3620
ba0251fe
TG		 3621 if (!mtd->name)
3622 mtd->name = type->name;
3623
69423d99 3624 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3625
12a40a57 3626 if (!type->pagesize && chip->init_size) {
8b6e50c9 3627 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3628 busw = chip->init_size(mtd, chip, id_data);
3629 } else if (!type->pagesize) {
fc09bbc0
BN		 3630 /* Decode parameters from extended ID */
3631 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3632 } else {
f23a481c 3633 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3634 }
bf7a01bf
BN		 3635 /* Get chip options */
3636 chip->options |= type->options;
d1e1f4e4 3637
8b6e50c9
BN		 3638 /*
3639 * Check if chip is not a Samsung device. Do not clear the
3640 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3641 */
3642 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3643 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3644ident_done:
3645
7aa65bfd 3646 /* Try to identify manufacturer */
9a909867 3647 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3648 if (nand_manuf_ids[maf_idx].id == *maf_id)
3649 break;
3650 }
0ea4a755 3651
64b37b2a
MC		 3652 if (chip->options & NAND_BUSWIDTH_AUTO) {
3653 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3654 chip->options |= busw;
3655 nand_set_defaults(chip, busw);
3656 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3657 /*
3658 * Check, if buswidth is correct. Hardware drivers should set
3659 * chip correct!
3660 */
20171642
EG		 3661 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3662 *maf_id, *dev_id);
3663 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3664 pr_warn("bus width %d instead %d bit\n",
d0370219
BN		 3665 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3666 busw ? 16 : 8);
7aa65bfd
TG		 3667 return ERR_PTR(-EINVAL);
3668 }
61b03bd7 3669
7e74c2d7
BN		 3670 nand_decode_bbm_options(mtd, chip, id_data);
3671
7aa65bfd 3672 /* Calculate the address shift from the page size */
ace4dfee 3673 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3674 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3675 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3676
ace4dfee 3677 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3678 ffs(mtd->erasesize) - 1;
69423d99
AH		 3679 if (chip->chipsize & 0xffffffff)
3680 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3681 else {
3682 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3683 chip->chip_shift += 32 - 1;
3684 }
1da177e4 3685
26d9be11 3686 chip->badblockbits = 8;
49c50b97 3687 chip->erase = single_erase;
7aa65bfd 3688
8b6e50c9 3689 /* Do not replace user supplied command function! */
ace4dfee
TG		 3690 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3691 chip->cmdfunc = nand_command_lp;
7aa65bfd 3692
20171642
EG		 3693 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3694 *maf_id, *dev_id);
ffdac6cd
HS		 3695
3696 if (chip->onfi_version)
3697 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3698 chip->onfi_params.model);
3699 else if (chip->jedec_version)
3700 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3701 chip->jedec_params.model);
3702 else
3703 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3704 type->name);
3705
20171642 3706 pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3723e93c
HS		 3707 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3708 mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3709 return type;
3710}
3711
7aa65bfd 3712/**
3b85c321 3713 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3714 * @mtd: MTD device structure
3715 * @maxchips: number of chips to scan for
3716 * @table: alternative NAND ID table
7aa65bfd 3717 *
8b6e50c9
BN		 3718 * This is the first phase of the normal nand_scan() function. It reads the
3719 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3720 *
3b85c321 3721 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3722 */
5e81e88a
DW		 3723int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3724 struct nand_flash_dev *table)
7aa65bfd 3725{
bb77082f 3726 int i, nand_maf_id, nand_dev_id;
ace4dfee 3727 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3728 struct nand_flash_dev *type;
3729
7aa65bfd 3730 /* Set the default functions */
bb77082f 3731 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
7aa65bfd
TG		 3732
3733 /* Read the flash type */
bb77082f
CZ		 3734 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3735 &nand_dev_id, table);
7aa65bfd
TG		 3736
3737 if (IS_ERR(type)) {
b1c6e6db 3738 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3739 pr_warn("No NAND device found\n");
ace4dfee 3740 chip->select_chip(mtd, -1);
7aa65bfd 3741 return PTR_ERR(type);
1da177e4
LT		 3742 }
3743
07300164
HS		 3744 chip->select_chip(mtd, -1);
3745
7aa65bfd 3746 /* Check for a chip array */
e0c7d767 3747 for (i = 1; i < maxchips; i++) {
ace4dfee 3748 chip->select_chip(mtd, i);
ef89a880
KB		 3749 /* See comment in nand_get_flash_type for reset */
3750 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3751 /* Send the command for reading device ID */
ace4dfee 3752 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3753 /* Read manufacturer and device IDs */
ace4dfee 3754 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 3755 nand_dev_id != chip->read_byte(mtd)) {
3756 chip->select_chip(mtd, -1);
1da177e4 3757 break;
07300164
HS		 3758 }
3759 chip->select_chip(mtd, -1);
1da177e4
LT		 3760 }
3761 if (i > 1)
20171642 3762 pr_info("%d chips detected\n", i);
61b03bd7 3763
1da177e4 3764 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3765 chip->numchips = i;
3766 mtd->size = i * chip->chipsize;
7aa65bfd 3767
3b85c321
DW		 3768 return 0;
3769}
7351d3a5 3770EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3771
3772
3773/**
3774 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3775 * @mtd: MTD device structure
3b85c321 3776 *
8b6e50c9
BN		 3777 * This is the second phase of the normal nand_scan() function. It fills out
3778 * all the uninitialized function pointers with the defaults and scans for a
3779 * bad block table if appropriate.
3b85c321
DW		 3780 */
3781int nand_scan_tail(struct mtd_info *mtd)
3782{
3783 int i;
3784 struct nand_chip *chip = mtd->priv;
97de79e0 3785 struct nand_ecc_ctrl *ecc = &chip->ecc;
f02ea4e6 3786 struct nand_buffers *nbuf;
3b85c321 3787
e2414f4c
BN		 3788 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3789 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3790 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3791
f02ea4e6
HS		 3792 if (!(chip->options & NAND_OWN_BUFFERS)) {
3793 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
3794 + mtd->oobsize * 3, GFP_KERNEL);
3795 if (!nbuf)
3796 return -ENOMEM;
3797 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
3798 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
3799 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
3800
3801 chip->buffers = nbuf;
3802 } else {
3803 if (!chip->buffers)
3804 return -ENOMEM;
3805 }
4bf63fcb 3806
7dcdcbef 3807 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3808 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3809
7aa65bfd 3810 /*
8b6e50c9 3811 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3812 */
97de79e0 3813 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3814 switch (mtd->oobsize) {
1da177e4 3815 case 8:
97de79e0 3816 ecc->layout = &nand_oob_8;
1da177e4
LT		 3817 break;
3818 case 16:
97de79e0 3819 ecc->layout = &nand_oob_16;
1da177e4
LT		 3820 break;
3821 case 64:
97de79e0 3822 ecc->layout = &nand_oob_64;
1da177e4 3823 break;
81ec5364 3824 case 128:
97de79e0 3825 ecc->layout = &nand_oob_128;
81ec5364 3826 break;
1da177e4 3827 default:
d0370219
BN		 3828 pr_warn("No oob scheme defined for oobsize %d\n",
3829 mtd->oobsize);
1da177e4
LT		 3830 BUG();
3831 }
3832 }
61b03bd7 3833
956e944c
DW		 3834 if (!chip->write_page)
3835 chip->write_page = nand_write_page;
3836
61b03bd7 3837 /*
8b6e50c9 3838 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3839 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3840 */
956e944c 3841
97de79e0 3842 switch (ecc->mode) {
6e0cb135
SN		 3843 case NAND_ECC_HW_OOB_FIRST:
3844 /* Similar to NAND_ECC_HW, but a separate read_page handle */
97de79e0 3845 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
9a4d4d69 3846 pr_warn("No ECC functions supplied; "
d0370219 3847 "hardware ECC not possible\n");
6e0cb135
SN		 3848 BUG();
3849 }
97de79e0
HS		 3850 if (!ecc->read_page)
3851 ecc->read_page = nand_read_page_hwecc_oob_first;
6e0cb135 3852
6dfc6d25 3853 case NAND_ECC_HW:
8b6e50c9 3854 /* Use standard hwecc read page function? */
97de79e0
HS		 3855 if (!ecc->read_page)
3856 ecc->read_page = nand_read_page_hwecc;
3857 if (!ecc->write_page)
3858 ecc->write_page = nand_write_page_hwecc;
3859 if (!ecc->read_page_raw)
3860 ecc->read_page_raw = nand_read_page_raw;
3861 if (!ecc->write_page_raw)
3862 ecc->write_page_raw = nand_write_page_raw;
3863 if (!ecc->read_oob)
3864 ecc->read_oob = nand_read_oob_std;
3865 if (!ecc->write_oob)
3866 ecc->write_oob = nand_write_oob_std;
3867 if (!ecc->read_subpage)
3868 ecc->read_subpage = nand_read_subpage;
3869 if (!ecc->write_subpage)
3870 ecc->write_subpage = nand_write_subpage_hwecc;
f5bbdacc 3871
6dfc6d25 3872 case NAND_ECC_HW_SYNDROME:
97de79e0
HS		 3873 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
3874 (!ecc->read_page ||
3875 ecc->read_page == nand_read_page_hwecc ||
3876 !ecc->write_page ||
3877 ecc->write_page == nand_write_page_hwecc)) {
9a4d4d69 3878 pr_warn("No ECC functions supplied; "
d0370219 3879 "hardware ECC not possible\n");
6dfc6d25
TG		 3880 BUG();
3881 }
8b6e50c9 3882 /* Use standard syndrome read/write page function? */
97de79e0
HS		 3883 if (!ecc->read_page)
3884 ecc->read_page = nand_read_page_syndrome;
3885 if (!ecc->write_page)
3886 ecc->write_page = nand_write_page_syndrome;
3887 if (!ecc->read_page_raw)
3888 ecc->read_page_raw = nand_read_page_raw_syndrome;
3889 if (!ecc->write_page_raw)
3890 ecc->write_page_raw = nand_write_page_raw_syndrome;
3891 if (!ecc->read_oob)
3892 ecc->read_oob = nand_read_oob_syndrome;
3893 if (!ecc->write_oob)
3894 ecc->write_oob = nand_write_oob_syndrome;
3895
3896 if (mtd->writesize >= ecc->size) {
3897 if (!ecc->strength) {
e2788c98
MD		 3898 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3899 BUG();
3900 }
6dfc6d25 3901 break;
e2788c98 3902 }
9a4d4d69 3903 pr_warn("%d byte HW ECC not possible on "
d0370219 3904 "%d byte page size, fallback to SW ECC\n",
97de79e0
HS		 3905 ecc->size, mtd->writesize);
3906 ecc->mode = NAND_ECC_SOFT;
61b03bd7 3907
6dfc6d25 3908 case NAND_ECC_SOFT:
97de79e0
HS		 3909 ecc->calculate = nand_calculate_ecc;
3910 ecc->correct = nand_correct_data;
3911 ecc->read_page = nand_read_page_swecc;
3912 ecc->read_subpage = nand_read_subpage;
3913 ecc->write_page = nand_write_page_swecc;
3914 ecc->read_page_raw = nand_read_page_raw;
3915 ecc->write_page_raw = nand_write_page_raw;
3916 ecc->read_oob = nand_read_oob_std;
3917 ecc->write_oob = nand_write_oob_std;
3918 if (!ecc->size)
3919 ecc->size = 256;
3920 ecc->bytes = 3;
3921 ecc->strength = 1;
1da177e4 3922 break;
61b03bd7 3923
193bd400
ID		 3924 case NAND_ECC_SOFT_BCH:
3925 if (!mtd_nand_has_bch()) {
148256fa 3926 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
193bd400
ID		 3927 BUG();
3928 }
97de79e0
HS		 3929 ecc->calculate = nand_bch_calculate_ecc;
3930 ecc->correct = nand_bch_correct_data;
3931 ecc->read_page = nand_read_page_swecc;
3932 ecc->read_subpage = nand_read_subpage;
3933 ecc->write_page = nand_write_page_swecc;
3934 ecc->read_page_raw = nand_read_page_raw;
3935 ecc->write_page_raw = nand_write_page_raw;
3936 ecc->read_oob = nand_read_oob_std;
3937 ecc->write_oob = nand_write_oob_std;
193bd400
ID		 3938 /*
3939 * Board driver should supply ecc.size and ecc.bytes values to
3940 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3941 * for details. Otherwise, default to 4 bits for large page
3942 * devices.
193bd400 3943 */
97de79e0
HS		 3944 if (!ecc->size && (mtd->oobsize >= 64)) {
3945 ecc->size = 512;
3946 ecc->bytes = 7;
193bd400 3947 }
97de79e0
HS		 3948 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
3949 &ecc->layout);
3950 if (!ecc->priv) {
9a4d4d69 3951 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3952 BUG();
3953 }
97de79e0 3954 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
193bd400
ID		 3955 break;
3956
61b03bd7 3957 case NAND_ECC_NONE:
9a4d4d69 3958 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3959 "This is not recommended!\n");
97de79e0
HS		 3960 ecc->read_page = nand_read_page_raw;
3961 ecc->write_page = nand_write_page_raw;
3962 ecc->read_oob = nand_read_oob_std;
3963 ecc->read_page_raw = nand_read_page_raw;
3964 ecc->write_page_raw = nand_write_page_raw;
3965 ecc->write_oob = nand_write_oob_std;
3966 ecc->size = mtd->writesize;
3967 ecc->bytes = 0;
3968 ecc->strength = 0;
1da177e4 3969 break;
956e944c 3970
1da177e4 3971 default:
97de79e0 3972 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
61b03bd7 3973 BUG();
1da177e4 3974 }
61b03bd7 3975
9ce244b3 3976 /* For many systems, the standard OOB write also works for raw */
97de79e0
HS		 3977 if (!ecc->read_oob_raw)
3978 ecc->read_oob_raw = ecc->read_oob;
3979 if (!ecc->write_oob_raw)
3980 ecc->write_oob_raw = ecc->write_oob;
9ce244b3 3981
5bd34c09
TG		 3982 /*
3983 * The number of bytes available for a client to place data into
8b6e50c9 3984 * the out of band area.
5bd34c09 3985 */
97de79e0
HS		 3986 ecc->layout->oobavail = 0;
3987 for (i = 0; ecc->layout->oobfree[i].length
3988 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
3989 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
3990 mtd->oobavail = ecc->layout->oobavail;
5bd34c09 3991
7aa65bfd
TG		 3992 /*
3993 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3994 * mode.
7aa65bfd 3995 */
97de79e0
HS		 3996 ecc->steps = mtd->writesize / ecc->size;
3997 if (ecc->steps * ecc->size != mtd->writesize) {
9a4d4d69 3998 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3999 BUG();
1da177e4 4000 }
97de79e0 4001 ecc->total = ecc->steps * ecc->bytes;
61b03bd7 4002
8b6e50c9 4003 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
1d0ed69d 4004 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
97de79e0 4005 switch (ecc->steps) {
29072b96
TG		 4006 case 2:
4007 mtd->subpage_sft = 1;
4008 break;
4009 case 4:
4010 case 8:
81ec5364 4011 case 16:
29072b96
TG		 4012 mtd->subpage_sft = 2;
4013 break;
4014 }
4015 }
4016 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4017
04bbd0ea 4018 /* Initialize state */
ace4dfee 4019 chip->state = FL_READY;
1da177e4 4020
1da177e4 4021 /* Invalidate the pagebuffer reference */
ace4dfee 4022 chip->pagebuf = -1;
1da177e4 4023
a5ff4f10 4024 /* Large page NAND with SOFT_ECC should support subpage reads */
97de79e0 4025 if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
a5ff4f10
JW		 4026 chip->options |= NAND_SUBPAGE_READ;
4027
1da177e4 4028 /* Fill in remaining MTD driver data */
963d1c28 4029 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
93edbad6
ML		 4030 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4031 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 4032 mtd->_erase = nand_erase;
4033 mtd->_point = NULL;
4034 mtd->_unpoint = NULL;
4035 mtd->_read = nand_read;
4036 mtd->_write = nand_write;
4037 mtd->_panic_write = panic_nand_write;
4038 mtd->_read_oob = nand_read_oob;
4039 mtd->_write_oob = nand_write_oob;
4040 mtd->_sync = nand_sync;
4041 mtd->_lock = NULL;
4042 mtd->_unlock = NULL;
4043 mtd->_suspend = nand_suspend;
4044 mtd->_resume = nand_resume;
4045 mtd->_block_isbad = nand_block_isbad;
4046 mtd->_block_markbad = nand_block_markbad;
cbcab65a 4047 mtd->writebufsize = mtd->writesize;
1da177e4 4048
6a918bad 4049 /* propagate ecc info to mtd_info */
97de79e0
HS		 4050 mtd->ecclayout = ecc->layout;
4051 mtd->ecc_strength = ecc->strength;
4052 mtd->ecc_step_size = ecc->size;
ea3b2ea2
SL		 4053 /*
4054 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4055 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4056 * properly set.
4057 */
4058 if (!mtd->bitflip_threshold)
4059 mtd->bitflip_threshold = mtd->ecc_strength;
1da177e4 4060
0040bf38 4061 /* Check, if we should skip the bad block table scan */
ace4dfee 4062 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 4063 return 0;
1da177e4
LT		 4064
4065 /* Build bad block table */
ace4dfee 4066 return chip->scan_bbt(mtd);
1da177e4 4067}
7351d3a5 4068EXPORT_SYMBOL(nand_scan_tail);
1da177e4 4069
8b6e50c9
BN		 4070/*
4071 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 4072 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 4073 * to call us from in-kernel code if the core NAND support is modular.
4074 */
3b85c321
DW		 4075#ifdef MODULE
4076#define caller_is_module() (1)
4077#else
4078#define caller_is_module() \
a6e6abd5 4079 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 4080#endif
4081
4082/**
4083 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4084 * @mtd: MTD device structure
4085 * @maxchips: number of chips to scan for
3b85c321 4086 *
8b6e50c9
BN		 4087 * This fills out all the uninitialized function pointers with the defaults.
4088 * The flash ID is read and the mtd/chip structures are filled with the
4089 * appropriate values. The mtd->owner field must be set to the module of the
4090 * caller.
3b85c321
DW		 4091 */
4092int nand_scan(struct mtd_info *mtd, int maxchips)
4093{
4094 int ret;
4095
4096 /* Many callers got this wrong, so check for it for a while... */
4097 if (!mtd->owner && caller_is_module()) {
d0370219 4098 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 4099 BUG();
4100 }
4101
5e81e88a 4102 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 4103 if (!ret)
4104 ret = nand_scan_tail(mtd);
4105 return ret;
4106}
7351d3a5 4107EXPORT_SYMBOL(nand_scan);
3b85c321 4108
1da177e4 4109/**
61b03bd7 4110 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 4111 * @mtd: MTD device structure
4112 */
e0c7d767 4113void nand_release(struct mtd_info *mtd)
1da177e4 4114{
ace4dfee 4115 struct nand_chip *chip = mtd->priv;
1da177e4 4116
193bd400
ID		 4117 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4118 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4119
5ffcaf3d 4120 mtd_device_unregister(mtd);
1da177e4 4121
fa671646 4122 /* Free bad block table memory */
ace4dfee 4123 kfree(chip->bbt);
4bf63fcb
DW		 4124 if (!(chip->options & NAND_OWN_BUFFERS))
4125 kfree(chip->buffers);
58373ff0
BN		 4126
4127 /* Free bad block descriptor memory */
4128 if (chip->badblock_pattern && chip->badblock_pattern->options
4129 & NAND_BBT_DYNAMICSTRUCT)
4130 kfree(chip->badblock_pattern);
1da177e4 4131}
e0c7d767 4132EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 4133
4134static int __init nand_base_init(void)
4135{
4136 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4137 return 0;
4138}
4139
4140static void __exit nand_base_exit(void)
4141{
4142 led_trigger_unregister_simple(nand_led_trigger);
4143}
4144
4145module_init(nand_base_init);
4146module_exit(nand_base_exit);
4147
e0c7d767 4148MODULE_LICENSE("GPL");
7351d3a5
FF		 4149MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4150MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 4151MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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