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mtd: txx9ndfmc: Use nand_release to free resources
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
45#include <linux/mtd/compatmac.h>
46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
1da177e4
LT		 49#include <asm/io.h>
50
51#ifdef CONFIG_MTD_PARTITIONS
52#include <linux/mtd/partitions.h>
53#endif
54
55/* Define default oob placement schemes for large and small page devices */
5bd34c09 56static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 57 .eccbytes = 3,
58 .eccpos = {0, 1, 2},
5bd34c09
TG		 59 .oobfree = {
60 {.offset = 3,
61 .length = 2},
62 {.offset = 6,
63 .length = 2}}
1da177e4
LT		 64};
65
5bd34c09 66static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 67 .eccbytes = 6,
68 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 69 .oobfree = {
70 {.offset = 8,
71 . length = 8}}
1da177e4
LT		 72};
73
5bd34c09 74static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 75 .eccbytes = 24,
76 .eccpos = {
e0c7d767
DW		 77 40, 41, 42, 43, 44, 45, 46, 47,
78 48, 49, 50, 51, 52, 53, 54, 55,
79 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 80 .oobfree = {
81 {.offset = 2,
82 .length = 38}}
1da177e4
LT		 83};
84
81ec5364
TG		 85static struct nand_ecclayout nand_oob_128 = {
86 .eccbytes = 48,
87 .eccpos = {
88 80, 81, 82, 83, 84, 85, 86, 87,
89 88, 89, 90, 91, 92, 93, 94, 95,
90 96, 97, 98, 99, 100, 101, 102, 103,
91 104, 105, 106, 107, 108, 109, 110, 111,
92 112, 113, 114, 115, 116, 117, 118, 119,
93 120, 121, 122, 123, 124, 125, 126, 127},
94 .oobfree = {
95 {.offset = 2,
96 .length = 78}}
97};
98
ace4dfee 99static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 100 int new_state);
1da177e4 101
8593fbc6
TG		 102static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
103 struct mtd_oob_ops *ops);
104
d470a97c 105/*
8e87d782 106 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 107 * compiled away when LED support is disabled.
108 */
109DEFINE_LED_TRIGGER(nand_led_trigger);
110
1da177e4
LT		 111/**
112 * nand_release_device - [GENERIC] release chip
113 * @mtd: MTD device structure
61b03bd7
TG		 114 *
115 * Deselect, release chip lock and wake up anyone waiting on the device
1da177e4 116 */
e0c7d767 117static void nand_release_device(struct mtd_info *mtd)
1da177e4 118{
ace4dfee 119 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 120
121 /* De-select the NAND device */
ace4dfee 122 chip->select_chip(mtd, -1);
0dfc6246 123
a36ed299 124 /* Release the controller and the chip */
ace4dfee
TG		 125 spin_lock(&chip->controller->lock);
126 chip->controller->active = NULL;
127 chip->state = FL_READY;
128 wake_up(&chip->controller->wq);
129 spin_unlock(&chip->controller->lock);
1da177e4
LT		 130}
131
132/**
133 * nand_read_byte - [DEFAULT] read one byte from the chip
134 * @mtd: MTD device structure
135 *
136 * Default read function for 8bit buswith
137 */
58dd8f2b 138static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 139{
ace4dfee
TG		 140 struct nand_chip *chip = mtd->priv;
141 return readb(chip->IO_ADDR_R);
1da177e4
LT		 142}
143
1da177e4
LT		 144/**
145 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
146 * @mtd: MTD device structure
147 *
61b03bd7 148 * Default read function for 16bit buswith with
1da177e4
LT		 149 * endianess conversion
150 */
58dd8f2b 151static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 152{
ace4dfee
TG		 153 struct nand_chip *chip = mtd->priv;
154 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 155}
156
1da177e4
LT		 157/**
158 * nand_read_word - [DEFAULT] read one word from the chip
159 * @mtd: MTD device structure
160 *
61b03bd7 161 * Default read function for 16bit buswith without
1da177e4
LT		 162 * endianess conversion
163 */
164static u16 nand_read_word(struct mtd_info *mtd)
165{
ace4dfee
TG		 166 struct nand_chip *chip = mtd->priv;
167 return readw(chip->IO_ADDR_R);
1da177e4
LT		 168}
169
1da177e4
LT		 170/**
171 * nand_select_chip - [DEFAULT] control CE line
172 * @mtd: MTD device structure
844d3b42 173 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 174 *
175 * Default select function for 1 chip devices.
176 */
ace4dfee 177static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 178{
ace4dfee
TG		 179 struct nand_chip *chip = mtd->priv;
180
181 switch (chipnr) {
1da177e4 182 case -1:
ace4dfee 183 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 184 break;
185 case 0:
1da177e4
LT		 186 break;
187
188 default:
189 BUG();
190 }
191}
192
193/**
194 * nand_write_buf - [DEFAULT] write buffer to chip
195 * @mtd: MTD device structure
196 * @buf: data buffer
197 * @len: number of bytes to write
198 *
199 * Default write function for 8bit buswith
200 */
58dd8f2b 201static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 202{
203 int i;
ace4dfee 204 struct nand_chip *chip = mtd->priv;
1da177e4 205
e0c7d767 206 for (i = 0; i < len; i++)
ace4dfee 207 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 208}
209
210/**
61b03bd7 211 * nand_read_buf - [DEFAULT] read chip data into buffer
1da177e4
LT		 212 * @mtd: MTD device structure
213 * @buf: buffer to store date
214 * @len: number of bytes to read
215 *
216 * Default read function for 8bit buswith
217 */
58dd8f2b 218static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 219{
220 int i;
ace4dfee 221 struct nand_chip *chip = mtd->priv;
1da177e4 222
e0c7d767 223 for (i = 0; i < len; i++)
ace4dfee 224 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 225}
226
227/**
61b03bd7 228 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 229 * @mtd: MTD device structure
230 * @buf: buffer containing the data to compare
231 * @len: number of bytes to compare
232 *
233 * Default verify function for 8bit buswith
234 */
58dd8f2b 235static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 236{
237 int i;
ace4dfee 238 struct nand_chip *chip = mtd->priv;
1da177e4 239
e0c7d767 240 for (i = 0; i < len; i++)
ace4dfee 241 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 242 return -EFAULT;
1da177e4
LT		 243 return 0;
244}
245
246/**
247 * nand_write_buf16 - [DEFAULT] write buffer to chip
248 * @mtd: MTD device structure
249 * @buf: data buffer
250 * @len: number of bytes to write
251 *
252 * Default write function for 16bit buswith
253 */
58dd8f2b 254static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 255{
256 int i;
ace4dfee 257 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 258 u16 *p = (u16 *) buf;
259 len >>= 1;
61b03bd7 260
e0c7d767 261 for (i = 0; i < len; i++)
ace4dfee 262 writew(p[i], chip->IO_ADDR_W);
61b03bd7 263
1da177e4
LT		 264}
265
266/**
61b03bd7 267 * nand_read_buf16 - [DEFAULT] read chip data into buffer
1da177e4
LT		 268 * @mtd: MTD device structure
269 * @buf: buffer to store date
270 * @len: number of bytes to read
271 *
272 * Default read function for 16bit buswith
273 */
58dd8f2b 274static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 275{
276 int i;
ace4dfee 277 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 278 u16 *p = (u16 *) buf;
279 len >>= 1;
280
e0c7d767 281 for (i = 0; i < len; i++)
ace4dfee 282 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 283}
284
285/**
61b03bd7 286 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 287 * @mtd: MTD device structure
288 * @buf: buffer containing the data to compare
289 * @len: number of bytes to compare
290 *
291 * Default verify function for 16bit buswith
292 */
58dd8f2b 293static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 294{
295 int i;
ace4dfee 296 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 297 u16 *p = (u16 *) buf;
298 len >>= 1;
299
e0c7d767 300 for (i = 0; i < len; i++)
ace4dfee 301 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 302 return -EFAULT;
303
304 return 0;
305}
306
307/**
308 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
309 * @mtd: MTD device structure
310 * @ofs: offset from device start
311 * @getchip: 0, if the chip is already selected
312 *
61b03bd7 313 * Check, if the block is bad.
1da177e4
LT		 314 */
315static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
316{
317 int page, chipnr, res = 0;
ace4dfee 318 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 319 u16 bad;
320
1a12f46a
TK		 321 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
322
1da177e4 323 if (getchip) {
ace4dfee 324 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 325
ace4dfee 326 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 327
328 /* Select the NAND device */
ace4dfee 329 chip->select_chip(mtd, chipnr);
1a12f46a 330 }
1da177e4 331
ace4dfee
TG		 332 if (chip->options & NAND_BUSWIDTH_16) {
333 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 334 page);
ace4dfee
TG		 335 bad = cpu_to_le16(chip->read_word(mtd));
336 if (chip->badblockpos & 0x1)
49196f33 337 bad >>= 8;
1da177e4
LT		 338 if ((bad & 0xFF) != 0xff)
339 res = 1;
340 } else {
1a12f46a 341 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
ace4dfee 342 if (chip->read_byte(mtd) != 0xff)
1da177e4
LT		 343 res = 1;
344 }
61b03bd7 345
ace4dfee 346 if (getchip)
1da177e4 347 nand_release_device(mtd);
61b03bd7 348
1da177e4
LT		 349 return res;
350}
351
352/**
353 * nand_default_block_markbad - [DEFAULT] mark a block bad
354 * @mtd: MTD device structure
355 * @ofs: offset from device start
356 *
357 * This is the default implementation, which can be overridden by
358 * a hardware specific driver.
359*/
360static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
361{
ace4dfee 362 struct nand_chip *chip = mtd->priv;
58dd8f2b 363 uint8_t buf[2] = { 0, 0 };
f1a28c02 364 int block, ret;
61b03bd7 365
1da177e4 366 /* Get block number */
4226b510 367 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 368 if (chip->bbt)
369 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4
LT		 370
371 /* Do we have a flash based bad block table ? */
ace4dfee 372 if (chip->options & NAND_USE_FLASH_BBT)
f1a28c02
TG		 373 ret = nand_update_bbt(mtd, ofs);
374 else {
375 /* We write two bytes, so we dont have to mess with 16 bit
376 * access
377 */
c0b8ba7b 378 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 379 ofs += mtd->oobsize;
ff0dab64 380 chip->ops.len = chip->ops.ooblen = 2;
f1a28c02
TG		 381 chip->ops.datbuf = NULL;
382 chip->ops.oobbuf = buf;
383 chip->ops.ooboffs = chip->badblockpos & ~0x01;
384
385 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
c0b8ba7b 386 nand_release_device(mtd);
f1a28c02
TG		 387 }
388 if (!ret)
389 mtd->ecc_stats.badblocks++;
c0b8ba7b 390
f1a28c02 391 return ret;
1da177e4
LT		 392}
393
61b03bd7 394/**
1da177e4
LT		 395 * nand_check_wp - [GENERIC] check if the chip is write protected
396 * @mtd: MTD device structure
61b03bd7 397 * Check, if the device is write protected
1da177e4 398 *
61b03bd7 399 * The function expects, that the device is already selected
1da177e4 400 */
e0c7d767 401static int nand_check_wp(struct mtd_info *mtd)
1da177e4 402{
ace4dfee 403 struct nand_chip *chip = mtd->priv;
1da177e4 404 /* Check the WP bit */
ace4dfee
TG		 405 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
406 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 407}
408
409/**
410 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
411 * @mtd: MTD device structure
412 * @ofs: offset from device start
413 * @getchip: 0, if the chip is already selected
414 * @allowbbt: 1, if its allowed to access the bbt area
415 *
416 * Check, if the block is bad. Either by reading the bad block table or
417 * calling of the scan function.
418 */
2c0a2bed
TG		 419static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
420 int allowbbt)
1da177e4 421{
ace4dfee 422 struct nand_chip *chip = mtd->priv;
61b03bd7 423
ace4dfee
TG		 424 if (!chip->bbt)
425 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 426
1da177e4 427 /* Return info from the table */
e0c7d767 428 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 429}
430
2af7c653
SK		 431/**
432 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
433 * @mtd: MTD device structure
434 * @timeo: Timeout
435 *
436 * Helper function for nand_wait_ready used when needing to wait in interrupt
437 * context.
438 */
439static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
440{
441 struct nand_chip *chip = mtd->priv;
442 int i;
443
444 /* Wait for the device to get ready */
445 for (i = 0; i < timeo; i++) {
446 if (chip->dev_ready(mtd))
447 break;
448 touch_softlockup_watchdog();
449 mdelay(1);
450 }
451}
452
61b03bd7 453/*
3b88775c
TG		 454 * Wait for the ready pin, after a command
455 * The timeout is catched later.
456 */
4b648b02 457void nand_wait_ready(struct mtd_info *mtd)
3b88775c 458{
ace4dfee 459 struct nand_chip *chip = mtd->priv;
e0c7d767 460 unsigned long timeo = jiffies + 2;
3b88775c 461
2af7c653
SK		 462 /* 400ms timeout */
463 if (in_interrupt() || oops_in_progress)
464 return panic_nand_wait_ready(mtd, 400);
465
8fe833c1 466 led_trigger_event(nand_led_trigger, LED_FULL);
3b88775c
TG		 467 /* wait until command is processed or timeout occures */
468 do {
ace4dfee 469 if (chip->dev_ready(mtd))
8fe833c1 470 break;
8446f1d3 471 touch_softlockup_watchdog();
61b03bd7 472 } while (time_before(jiffies, timeo));
8fe833c1 473 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 474}
4b648b02 475EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 476
1da177e4
LT		 477/**
478 * nand_command - [DEFAULT] Send command to NAND device
479 * @mtd: MTD device structure
480 * @command: the command to be sent
481 * @column: the column address for this command, -1 if none
482 * @page_addr: the page address for this command, -1 if none
483 *
484 * Send command to NAND device. This function is used for small page
485 * devices (256/512 Bytes per page)
486 */
7abd3ef9
TG		 487static void nand_command(struct mtd_info *mtd, unsigned int command,
488 int column, int page_addr)
1da177e4 489{
ace4dfee 490 register struct nand_chip *chip = mtd->priv;
7abd3ef9 491 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 492
1da177e4
LT		 493 /*
494 * Write out the command to the device.
495 */
496 if (command == NAND_CMD_SEQIN) {
497 int readcmd;
498
28318776 499 if (column >= mtd->writesize) {
1da177e4 500 /* OOB area */
28318776 501 column -= mtd->writesize;
1da177e4
LT		 502 readcmd = NAND_CMD_READOOB;
503 } else if (column < 256) {
504 /* First 256 bytes --> READ0 */
505 readcmd = NAND_CMD_READ0;
506 } else {
507 column -= 256;
508 readcmd = NAND_CMD_READ1;
509 }
ace4dfee 510 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 511 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 512 }
ace4dfee 513 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 514
7abd3ef9
TG		 515 /*
516 * Address cycle, when necessary
517 */
518 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
519 /* Serially input address */
520 if (column != -1) {
521 /* Adjust columns for 16 bit buswidth */
ace4dfee 522 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 523 column >>= 1;
ace4dfee 524 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 525 ctrl &= ~NAND_CTRL_CHANGE;
526 }
527 if (page_addr != -1) {
ace4dfee 528 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 529 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 530 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 531 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 532 if (chip->chipsize > (32 << 20))
533 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 534 }
ace4dfee 535 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 536
537 /*
538 * program and erase have their own busy handlers
1da177e4 539 * status and sequential in needs no delay
e0c7d767 540 */
1da177e4 541 switch (command) {
61b03bd7 542
1da177e4
LT		 543 case NAND_CMD_PAGEPROG:
544 case NAND_CMD_ERASE1:
545 case NAND_CMD_ERASE2:
546 case NAND_CMD_SEQIN:
547 case NAND_CMD_STATUS:
548 return;
549
550 case NAND_CMD_RESET:
ace4dfee 551 if (chip->dev_ready)
1da177e4 552 break;
ace4dfee
TG		 553 udelay(chip->chip_delay);
554 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 555 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 556 chip->cmd_ctrl(mtd,
557 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
ace4dfee 558 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
1da177e4
LT		 559 return;
560
e0c7d767 561 /* This applies to read commands */
1da177e4 562 default:
61b03bd7 563 /*
1da177e4
LT		 564 * If we don't have access to the busy pin, we apply the given
565 * command delay
e0c7d767 566 */
ace4dfee
TG		 567 if (!chip->dev_ready) {
568 udelay(chip->chip_delay);
1da177e4 569 return;
61b03bd7 570 }
1da177e4 571 }
1da177e4
LT		 572 /* Apply this short delay always to ensure that we do wait tWB in
573 * any case on any machine. */
e0c7d767 574 ndelay(100);
3b88775c
TG		 575
576 nand_wait_ready(mtd);
1da177e4
LT		 577}
578
579/**
580 * nand_command_lp - [DEFAULT] Send command to NAND large page device
581 * @mtd: MTD device structure
582 * @command: the command to be sent
583 * @column: the column address for this command, -1 if none
584 * @page_addr: the page address for this command, -1 if none
585 *
7abd3ef9
TG		 586 * Send command to NAND device. This is the version for the new large page
587 * devices We dont have the separate regions as we have in the small page
588 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 589 */
7abd3ef9
TG		 590static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
591 int column, int page_addr)
1da177e4 592{
ace4dfee 593 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 594
595 /* Emulate NAND_CMD_READOOB */
596 if (command == NAND_CMD_READOOB) {
28318776 597 column += mtd->writesize;
1da177e4
LT		 598 command = NAND_CMD_READ0;
599 }
61b03bd7 600
7abd3ef9 601 /* Command latch cycle */
ace4dfee 602 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 603 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 604
605 if (column != -1 || page_addr != -1) {
7abd3ef9 606 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 607
608 /* Serially input address */
609 if (column != -1) {
610 /* Adjust columns for 16 bit buswidth */
ace4dfee 611 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 612 column >>= 1;
ace4dfee 613 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 614 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 615 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 616 }
1da177e4 617 if (page_addr != -1) {
ace4dfee
TG		 618 chip->cmd_ctrl(mtd, page_addr, ctrl);
619 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 620 NAND_NCE | NAND_ALE);
1da177e4 621 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 622 if (chip->chipsize > (128 << 20))
623 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 624 NAND_NCE | NAND_ALE);
1da177e4 625 }
1da177e4 626 }
ace4dfee 627 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 628
629 /*
630 * program and erase have their own busy handlers
30f464b7
DM		 631 * status, sequential in, and deplete1 need no delay
632 */
1da177e4 633 switch (command) {
61b03bd7 634
1da177e4
LT		 635 case NAND_CMD_CACHEDPROG:
636 case NAND_CMD_PAGEPROG:
637 case NAND_CMD_ERASE1:
638 case NAND_CMD_ERASE2:
639 case NAND_CMD_SEQIN:
7bc3312b 640 case NAND_CMD_RNDIN:
1da177e4 641 case NAND_CMD_STATUS:
30f464b7 642 case NAND_CMD_DEPLETE1:
1da177e4
LT		 643 return;
644
e0c7d767
DW		 645 /*
646 * read error status commands require only a short delay
647 */
30f464b7
DM		 648 case NAND_CMD_STATUS_ERROR:
649 case NAND_CMD_STATUS_ERROR0:
650 case NAND_CMD_STATUS_ERROR1:
651 case NAND_CMD_STATUS_ERROR2:
652 case NAND_CMD_STATUS_ERROR3:
ace4dfee 653 udelay(chip->chip_delay);
30f464b7 654 return;
1da177e4
LT		 655
656 case NAND_CMD_RESET:
ace4dfee 657 if (chip->dev_ready)
1da177e4 658 break;
ace4dfee 659 udelay(chip->chip_delay);
12efdde3
TG		 660 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
661 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
662 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
663 NAND_NCE | NAND_CTRL_CHANGE);
ace4dfee 664 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
1da177e4
LT		 665 return;
666
7bc3312b
TG		 667 case NAND_CMD_RNDOUT:
668 /* No ready / busy check necessary */
669 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
670 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
671 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
672 NAND_NCE | NAND_CTRL_CHANGE);
673 return;
674
1da177e4 675 case NAND_CMD_READ0:
12efdde3
TG		 676 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
677 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
678 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
679 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 680
e0c7d767 681 /* This applies to read commands */
1da177e4 682 default:
61b03bd7 683 /*
1da177e4
LT		 684 * If we don't have access to the busy pin, we apply the given
685 * command delay
e0c7d767 686 */
ace4dfee
TG		 687 if (!chip->dev_ready) {
688 udelay(chip->chip_delay);
1da177e4 689 return;
61b03bd7 690 }
1da177e4 691 }
3b88775c 692
1da177e4
LT		 693 /* Apply this short delay always to ensure that we do wait tWB in
694 * any case on any machine. */
e0c7d767 695 ndelay(100);
3b88775c
TG		 696
697 nand_wait_ready(mtd);
1da177e4
LT		 698}
699
2af7c653
SK		 700/**
701 * panic_nand_get_device - [GENERIC] Get chip for selected access
702 * @chip: the nand chip descriptor
703 * @mtd: MTD device structure
704 * @new_state: the state which is requested
705 *
706 * Used when in panic, no locks are taken.
707 */
708static void panic_nand_get_device(struct nand_chip *chip,
709 struct mtd_info *mtd, int new_state)
710{
711 /* Hardware controller shared among independend devices */
712 chip->controller->active = chip;
713 chip->state = new_state;
714}
715
1da177e4
LT		 716/**
717 * nand_get_device - [GENERIC] Get chip for selected access
844d3b42 718 * @chip: the nand chip descriptor
1da177e4 719 * @mtd: MTD device structure
61b03bd7 720 * @new_state: the state which is requested
1da177e4
LT		 721 *
722 * Get the device and lock it for exclusive access
723 */
2c0a2bed 724static int
ace4dfee 725nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 726{
ace4dfee
TG		 727 spinlock_t *lock = &chip->controller->lock;
728 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 729 DECLARE_WAITQUEUE(wait, current);
e0c7d767 730 retry:
0dfc6246
TG		 731 spin_lock(lock);
732
b8b3ee9a 733 /* Hardware controller shared among independent devices */
ace4dfee
TG		 734 if (!chip->controller->active)
735 chip->controller->active = chip;
a36ed299 736
ace4dfee
TG		 737 if (chip->controller->active == chip && chip->state == FL_READY) {
738 chip->state = new_state;
0dfc6246 739 spin_unlock(lock);
962034f4
VW		 740 return 0;
741 }
742 if (new_state == FL_PM_SUSPENDED) {
743 spin_unlock(lock);
ace4dfee 744 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
0dfc6246
TG		 745 }
746 set_current_state(TASK_UNINTERRUPTIBLE);
747 add_wait_queue(wq, &wait);
748 spin_unlock(lock);
749 schedule();
750 remove_wait_queue(wq, &wait);
1da177e4
LT		 751 goto retry;
752}
753
2af7c653
SK		 754/**
755 * panic_nand_wait - [GENERIC] wait until the command is done
756 * @mtd: MTD device structure
757 * @chip: NAND chip structure
758 * @timeo: Timeout
759 *
760 * Wait for command done. This is a helper function for nand_wait used when
761 * we are in interrupt context. May happen when in panic and trying to write
762 * an oops trough mtdoops.
763 */
764static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
765 unsigned long timeo)
766{
767 int i;
768 for (i = 0; i < timeo; i++) {
769 if (chip->dev_ready) {
770 if (chip->dev_ready(mtd))
771 break;
772 } else {
773 if (chip->read_byte(mtd) & NAND_STATUS_READY)
774 break;
775 }
776 mdelay(1);
777 }
778}
779
1da177e4
LT		 780/**
781 * nand_wait - [DEFAULT] wait until the command is done
782 * @mtd: MTD device structure
844d3b42 783 * @chip: NAND chip structure
1da177e4
LT		 784 *
785 * Wait for command done. This applies to erase and program only
61b03bd7 786 * Erase can take up to 400ms and program up to 20ms according to
1da177e4 787 * general NAND and SmartMedia specs
844d3b42 788 */
7bc3312b 789static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 790{
791
e0c7d767 792 unsigned long timeo = jiffies;
7bc3312b 793 int status, state = chip->state;
61b03bd7 794
1da177e4 795 if (state == FL_ERASING)
e0c7d767 796 timeo += (HZ * 400) / 1000;
1da177e4 797 else
e0c7d767 798 timeo += (HZ * 20) / 1000;
1da177e4 799
8fe833c1
RP		 800 led_trigger_event(nand_led_trigger, LED_FULL);
801
1da177e4
LT		 802 /* Apply this short delay always to ensure that we do wait tWB in
803 * any case on any machine. */
e0c7d767 804 ndelay(100);
1da177e4 805
ace4dfee
TG		 806 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
807 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 808 else
ace4dfee 809 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 810
2af7c653
SK		 811 if (in_interrupt() || oops_in_progress)
812 panic_nand_wait(mtd, chip, timeo);
813 else {
814 while (time_before(jiffies, timeo)) {
815 if (chip->dev_ready) {
816 if (chip->dev_ready(mtd))
817 break;
818 } else {
819 if (chip->read_byte(mtd) & NAND_STATUS_READY)
820 break;
821 }
822 cond_resched();
1da177e4 823 }
1da177e4 824 }
8fe833c1
RP		 825 led_trigger_event(nand_led_trigger, LED_OFF);
826
ace4dfee 827 status = (int)chip->read_byte(mtd);
1da177e4
LT		 828 return status;
829}
830
8593fbc6
TG		 831/**
832 * nand_read_page_raw - [Intern] read raw page data without ecc
833 * @mtd: mtd info structure
834 * @chip: nand chip info structure
835 * @buf: buffer to store read data
58475fb9 836 * @page: page number to read
52ff49df
DB		 837 *
838 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 839 */
840static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 841 uint8_t *buf, int page)
8593fbc6
TG		 842{
843 chip->read_buf(mtd, buf, mtd->writesize);
844 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
845 return 0;
846}
847
52ff49df
DB		 848/**
849 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
850 * @mtd: mtd info structure
851 * @chip: nand chip info structure
852 * @buf: buffer to store read data
58475fb9 853 * @page: page number to read
52ff49df
DB		 854 *
855 * We need a special oob layout and handling even when OOB isn't used.
856 */
857static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 858 uint8_t *buf, int page)
52ff49df
DB		 859{
860 int eccsize = chip->ecc.size;
861 int eccbytes = chip->ecc.bytes;
862 uint8_t *oob = chip->oob_poi;
863 int steps, size;
864
865 for (steps = chip->ecc.steps; steps > 0; steps--) {
866 chip->read_buf(mtd, buf, eccsize);
867 buf += eccsize;
868
869 if (chip->ecc.prepad) {
870 chip->read_buf(mtd, oob, chip->ecc.prepad);
871 oob += chip->ecc.prepad;
872 }
873
874 chip->read_buf(mtd, oob, eccbytes);
875 oob += eccbytes;
876
877 if (chip->ecc.postpad) {
878 chip->read_buf(mtd, oob, chip->ecc.postpad);
879 oob += chip->ecc.postpad;
880 }
881 }
882
883 size = mtd->oobsize - (oob - chip->oob_poi);
884 if (size)
885 chip->read_buf(mtd, oob, size);
886
887 return 0;
888}
889
1da177e4 890/**
d29ebdbe 891 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
f5bbdacc
TG		 892 * @mtd: mtd info structure
893 * @chip: nand chip info structure
894 * @buf: buffer to store read data
58475fb9 895 * @page: page number to read
068e3c0a 896 */
f5bbdacc 897static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 898 uint8_t *buf, int page)
1da177e4 899{
f5bbdacc
TG		 900 int i, eccsize = chip->ecc.size;
901 int eccbytes = chip->ecc.bytes;
902 int eccsteps = chip->ecc.steps;
903 uint8_t *p = buf;
4bf63fcb
DW		 904 uint8_t *ecc_calc = chip->buffers->ecccalc;
905 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 906 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 907
46a8cf2d 908 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 909
910 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
911 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
912
913 for (i = 0; i < chip->ecc.total; i++)
f75e5097 914 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 915
916 eccsteps = chip->ecc.steps;
917 p = buf;
918
919 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
920 int stat;
921
922 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 923 if (stat < 0)
f5bbdacc
TG		 924 mtd->ecc_stats.failed++;
925 else
926 mtd->ecc_stats.corrected += stat;
927 }
928 return 0;
22c60f5f 929}
1da177e4 930
3d459559
AK		 931/**
932 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
933 * @mtd: mtd info structure
934 * @chip: nand chip info structure
17c1d2be
AK		 935 * @data_offs: offset of requested data within the page
936 * @readlen: data length
937 * @bufpoi: buffer to store read data
3d459559
AK		 938 */
939static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
940{
941 int start_step, end_step, num_steps;
942 uint32_t *eccpos = chip->ecc.layout->eccpos;
943 uint8_t *p;
944 int data_col_addr, i, gaps = 0;
945 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
946 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
947
948 /* Column address wihin the page aligned to ECC size (256bytes). */
949 start_step = data_offs / chip->ecc.size;
950 end_step = (data_offs + readlen - 1) / chip->ecc.size;
951 num_steps = end_step - start_step + 1;
952
953 /* Data size aligned to ECC ecc.size*/
954 datafrag_len = num_steps * chip->ecc.size;
955 eccfrag_len = num_steps * chip->ecc.bytes;
956
957 data_col_addr = start_step * chip->ecc.size;
958 /* If we read not a page aligned data */
959 if (data_col_addr != 0)
960 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
961
962 p = bufpoi + data_col_addr;
963 chip->read_buf(mtd, p, datafrag_len);
964
965 /* Calculate ECC */
966 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
967 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
968
969 /* The performance is faster if to position offsets
970 according to ecc.pos. Let make sure here that
971 there are no gaps in ecc positions */
972 for (i = 0; i < eccfrag_len - 1; i++) {
973 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
974 eccpos[i + start_step * chip->ecc.bytes + 1]) {
975 gaps = 1;
976 break;
977 }
978 }
979 if (gaps) {
980 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
981 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
982 } else {
983 /* send the command to read the particular ecc bytes */
984 /* take care about buswidth alignment in read_buf */
985 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
986 aligned_len = eccfrag_len;
987 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
988 aligned_len++;
989 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
990 aligned_len++;
991
992 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
993 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
994 }
995
996 for (i = 0; i < eccfrag_len; i++)
997 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
998
999 p = bufpoi + data_col_addr;
1000 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1001 int stat;
1002
1003 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1004 if (stat == -1)
1005 mtd->ecc_stats.failed++;
1006 else
1007 mtd->ecc_stats.corrected += stat;
1008 }
1009 return 0;
1010}
1011
068e3c0a 1012/**
d29ebdbe 1013 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
f5bbdacc
TG		 1014 * @mtd: mtd info structure
1015 * @chip: nand chip info structure
1016 * @buf: buffer to store read data
58475fb9 1017 * @page: page number to read
068e3c0a 1018 *
f5bbdacc 1019 * Not for syndrome calculating ecc controllers which need a special oob layout
068e3c0a 1020 */
f5bbdacc 1021static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1022 uint8_t *buf, int page)
1da177e4 1023{
f5bbdacc
TG		 1024 int i, eccsize = chip->ecc.size;
1025 int eccbytes = chip->ecc.bytes;
1026 int eccsteps = chip->ecc.steps;
1027 uint8_t *p = buf;
4bf63fcb
DW		 1028 uint8_t *ecc_calc = chip->buffers->ecccalc;
1029 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1030 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1031
1032 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1033 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1034 chip->read_buf(mtd, p, eccsize);
1035 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1036 }
f75e5097 1037 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1038
f5bbdacc 1039 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1040 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1041
f5bbdacc
TG		 1042 eccsteps = chip->ecc.steps;
1043 p = buf;
61b03bd7 1044
f5bbdacc
TG		 1045 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1046 int stat;
1da177e4 1047
f5bbdacc 1048 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1049 if (stat < 0)
f5bbdacc
TG		 1050 mtd->ecc_stats.failed++;
1051 else
1052 mtd->ecc_stats.corrected += stat;
1053 }
1054 return 0;
1055}
1da177e4 1056
6e0cb135
SN		 1057/**
1058 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1059 * @mtd: mtd info structure
1060 * @chip: nand chip info structure
1061 * @buf: buffer to store read data
58475fb9 1062 * @page: page number to read
6e0cb135
SN		 1063 *
1064 * Hardware ECC for large page chips, require OOB to be read first.
1065 * For this ECC mode, the write_page method is re-used from ECC_HW.
1066 * These methods read/write ECC from the OOB area, unlike the
1067 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1068 * "infix ECC" scheme and reads/writes ECC from the data area, by
1069 * overwriting the NAND manufacturer bad block markings.
1070 */
1071static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1072 struct nand_chip *chip, uint8_t *buf, int page)
1073{
1074 int i, eccsize = chip->ecc.size;
1075 int eccbytes = chip->ecc.bytes;
1076 int eccsteps = chip->ecc.steps;
1077 uint8_t *p = buf;
1078 uint8_t *ecc_code = chip->buffers->ecccode;
1079 uint32_t *eccpos = chip->ecc.layout->eccpos;
1080 uint8_t *ecc_calc = chip->buffers->ecccalc;
1081
1082 /* Read the OOB area first */
1083 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1084 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1085 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1086
1087 for (i = 0; i < chip->ecc.total; i++)
1088 ecc_code[i] = chip->oob_poi[eccpos[i]];
1089
1090 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1091 int stat;
1092
1093 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1094 chip->read_buf(mtd, p, eccsize);
1095 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1096
1097 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1098 if (stat < 0)
1099 mtd->ecc_stats.failed++;
1100 else
1101 mtd->ecc_stats.corrected += stat;
1102 }
1103 return 0;
1104}
1105
f5bbdacc 1106/**
d29ebdbe 1107 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
f5bbdacc
TG		 1108 * @mtd: mtd info structure
1109 * @chip: nand chip info structure
1110 * @buf: buffer to store read data
58475fb9 1111 * @page: page number to read
f5bbdacc
TG		 1112 *
1113 * The hw generator calculates the error syndrome automatically. Therefor
f75e5097 1114 * we need a special oob layout and handling.
f5bbdacc
TG		 1115 */
1116static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1117 uint8_t *buf, int page)
f5bbdacc
TG		 1118{
1119 int i, eccsize = chip->ecc.size;
1120 int eccbytes = chip->ecc.bytes;
1121 int eccsteps = chip->ecc.steps;
1122 uint8_t *p = buf;
f75e5097 1123 uint8_t *oob = chip->oob_poi;
1da177e4 1124
f5bbdacc
TG		 1125 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1126 int stat;
61b03bd7 1127
f5bbdacc
TG		 1128 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1129 chip->read_buf(mtd, p, eccsize);
1da177e4 1130
f5bbdacc
TG		 1131 if (chip->ecc.prepad) {
1132 chip->read_buf(mtd, oob, chip->ecc.prepad);
1133 oob += chip->ecc.prepad;
1134 }
1da177e4 1135
f5bbdacc
TG		 1136 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1137 chip->read_buf(mtd, oob, eccbytes);
1138 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1139
c32b8dcc 1140 if (stat < 0)
f5bbdacc 1141 mtd->ecc_stats.failed++;
61b03bd7 1142 else
f5bbdacc 1143 mtd->ecc_stats.corrected += stat;
61b03bd7 1144
f5bbdacc 1145 oob += eccbytes;
1da177e4 1146
f5bbdacc
TG		 1147 if (chip->ecc.postpad) {
1148 chip->read_buf(mtd, oob, chip->ecc.postpad);
1149 oob += chip->ecc.postpad;
61b03bd7 1150 }
f5bbdacc 1151 }
1da177e4 1152
f5bbdacc 1153 /* Calculate remaining oob bytes */
7e4178f9 1154 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1155 if (i)
1156 chip->read_buf(mtd, oob, i);
61b03bd7 1157
f5bbdacc
TG		 1158 return 0;
1159}
1da177e4 1160
f5bbdacc 1161/**
8593fbc6
TG		 1162 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1163 * @chip: nand chip structure
844d3b42 1164 * @oob: oob destination address
8593fbc6 1165 * @ops: oob ops structure
7014568b 1166 * @len: size of oob to transfer
8593fbc6
TG		 1167 */
1168static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1169 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1170{
8593fbc6
TG		 1171 switch(ops->mode) {
1172
1173 case MTD_OOB_PLACE:
1174 case MTD_OOB_RAW:
1175 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1176 return oob + len;
1177
1178 case MTD_OOB_AUTO: {
1179 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1180 uint32_t boffs = 0, roffs = ops->ooboffs;
1181 size_t bytes = 0;
8593fbc6
TG		 1182
1183 for(; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1184 /* Read request not from offset 0 ? */
1185 if (unlikely(roffs)) {
1186 if (roffs >= free->length) {
1187 roffs -= free->length;
1188 continue;
1189 }
1190 boffs = free->offset + roffs;
1191 bytes = min_t(size_t, len,
1192 (free->length - roffs));
1193 roffs = 0;
1194 } else {
1195 bytes = min_t(size_t, len, free->length);
1196 boffs = free->offset;
1197 }
1198 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1199 oob += bytes;
1200 }
1201 return oob;
1202 }
1203 default:
1204 BUG();
1205 }
1206 return NULL;
1207}
1208
1209/**
1210 * nand_do_read_ops - [Internal] Read data with ECC
f5bbdacc
TG		 1211 *
1212 * @mtd: MTD device structure
1213 * @from: offset to read from
844d3b42 1214 * @ops: oob ops structure
f5bbdacc
TG		 1215 *
1216 * Internal function. Called with chip held.
1217 */
8593fbc6
TG		 1218static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1219 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1220{
1221 int chipnr, page, realpage, col, bytes, aligned;
1222 struct nand_chip *chip = mtd->priv;
1223 struct mtd_ecc_stats stats;
1224 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1225 int sndcmd = 1;
1226 int ret = 0;
8593fbc6 1227 uint32_t readlen = ops->len;
7014568b 1228 uint32_t oobreadlen = ops->ooblen;
8593fbc6 1229 uint8_t *bufpoi, *oob, *buf;
1da177e4 1230
f5bbdacc 1231 stats = mtd->ecc_stats;
1da177e4 1232
f5bbdacc
TG		 1233 chipnr = (int)(from >> chip->chip_shift);
1234 chip->select_chip(mtd, chipnr);
61b03bd7 1235
f5bbdacc
TG		 1236 realpage = (int)(from >> chip->page_shift);
1237 page = realpage & chip->pagemask;
1da177e4 1238
f5bbdacc 1239 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1240
8593fbc6
TG		 1241 buf = ops->datbuf;
1242 oob = ops->oobbuf;
1243
f5bbdacc
TG		 1244 while(1) {
1245 bytes = min(mtd->writesize - col, readlen);
1246 aligned = (bytes == mtd->writesize);
61b03bd7 1247
f5bbdacc 1248 /* Is the current page in the buffer ? */
8593fbc6 1249 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1250 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1251
f5bbdacc
TG		 1252 if (likely(sndcmd)) {
1253 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1254 sndcmd = 0;
1da177e4 1255 }
1da177e4 1256
f5bbdacc 1257 /* Now read the page into the buffer */
956e944c 1258 if (unlikely(ops->mode == MTD_OOB_RAW))
46a8cf2d
SN		 1259 ret = chip->ecc.read_page_raw(mtd, chip,
1260 bufpoi, page);
3d459559
AK		 1261 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1262 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
956e944c 1263 else
46a8cf2d
SN		 1264 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1265 page);
f5bbdacc 1266 if (ret < 0)
1da177e4 1267 break;
f5bbdacc
TG		 1268
1269 /* Transfer not aligned data */
1270 if (!aligned) {
3d459559
AK		 1271 if (!NAND_SUBPAGE_READ(chip) && !oob)
1272 chip->pagebuf = realpage;
4bf63fcb 1273 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1274 }
1275
8593fbc6
TG		 1276 buf += bytes;
1277
1278 if (unlikely(oob)) {
1279 /* Raw mode does data:oob:data:oob */
7014568b
VW		 1280 if (ops->mode != MTD_OOB_RAW) {
1281 int toread = min(oobreadlen,
1282 chip->ecc.layout->oobavail);
1283 if (toread) {
1284 oob = nand_transfer_oob(chip,
1285 oob, ops, toread);
1286 oobreadlen -= toread;
1287 }
1288 } else
1289 buf = nand_transfer_oob(chip,
1290 buf, ops, mtd->oobsize);
8593fbc6
TG		 1291 }
1292
f5bbdacc
TG		 1293 if (!(chip->options & NAND_NO_READRDY)) {
1294 /*
1295 * Apply delay or wait for ready/busy pin. Do
1296 * this before the AUTOINCR check, so no
1297 * problems arise if a chip which does auto
1298 * increment is marked as NOAUTOINCR by the
1299 * board driver.
1300 */
1301 if (!chip->dev_ready)
1302 udelay(chip->chip_delay);
1303 else
1304 nand_wait_ready(mtd);
1da177e4 1305 }
8593fbc6 1306 } else {
4bf63fcb 1307 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1308 buf += bytes;
1309 }
1da177e4 1310
f5bbdacc 1311 readlen -= bytes;
61b03bd7 1312
f5bbdacc 1313 if (!readlen)
61b03bd7 1314 break;
1da177e4
LT		 1315
1316 /* For subsequent reads align to page boundary. */
1317 col = 0;
1318 /* Increment page address */
1319 realpage++;
1320
ace4dfee 1321 page = realpage & chip->pagemask;
1da177e4
LT		 1322 /* Check, if we cross a chip boundary */
1323 if (!page) {
1324 chipnr++;
ace4dfee
TG		 1325 chip->select_chip(mtd, -1);
1326 chip->select_chip(mtd, chipnr);
1da177e4 1327 }
f5bbdacc 1328
61b03bd7
TG		 1329 /* Check, if the chip supports auto page increment
1330 * or if we have hit a block boundary.
e0c7d767 1331 */
f5bbdacc 1332 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1333 sndcmd = 1;
1da177e4
LT		 1334 }
1335
8593fbc6 1336 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1337 if (oob)
1338 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1339
f5bbdacc
TG		 1340 if (ret)
1341 return ret;
1342
9a1fcdfd
TG		 1343 if (mtd->ecc_stats.failed - stats.failed)
1344 return -EBADMSG;
1345
1346 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1347}
1348
1349/**
1350 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1351 * @mtd: MTD device structure
1352 * @from: offset to read from
1353 * @len: number of bytes to read
1354 * @retlen: pointer to variable to store the number of read bytes
1355 * @buf: the databuffer to put data
1356 *
1357 * Get hold of the chip and call nand_do_read
1358 */
1359static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1360 size_t *retlen, uint8_t *buf)
1361{
8593fbc6 1362 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1363 int ret;
1364
f5bbdacc
TG		 1365 /* Do not allow reads past end of device */
1366 if ((from + len) > mtd->size)
1367 return -EINVAL;
1368 if (!len)
1369 return 0;
1370
8593fbc6 1371 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1372
8593fbc6
TG		 1373 chip->ops.len = len;
1374 chip->ops.datbuf = buf;
1375 chip->ops.oobbuf = NULL;
1376
1377 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1378
7fd5aecc
RP		 1379 *retlen = chip->ops.retlen;
1380
f5bbdacc
TG		 1381 nand_release_device(mtd);
1382
1383 return ret;
1da177e4
LT		 1384}
1385
7bc3312b
TG		 1386/**
1387 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1388 * @mtd: mtd info structure
1389 * @chip: nand chip info structure
1390 * @page: page number to read
1391 * @sndcmd: flag whether to issue read command or not
1392 */
1393static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1394 int page, int sndcmd)
1395{
1396 if (sndcmd) {
1397 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1398 sndcmd = 0;
1399 }
1400 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1401 return sndcmd;
1402}
1403
1404/**
1405 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1406 * with syndromes
1407 * @mtd: mtd info structure
1408 * @chip: nand chip info structure
1409 * @page: page number to read
1410 * @sndcmd: flag whether to issue read command or not
1411 */
1412static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1413 int page, int sndcmd)
1414{
1415 uint8_t *buf = chip->oob_poi;
1416 int length = mtd->oobsize;
1417 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1418 int eccsize = chip->ecc.size;
1419 uint8_t *bufpoi = buf;
1420 int i, toread, sndrnd = 0, pos;
1421
1422 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1423 for (i = 0; i < chip->ecc.steps; i++) {
1424 if (sndrnd) {
1425 pos = eccsize + i * (eccsize + chunk);
1426 if (mtd->writesize > 512)
1427 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1428 else
1429 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1430 } else
1431 sndrnd = 1;
1432 toread = min_t(int, length, chunk);
1433 chip->read_buf(mtd, bufpoi, toread);
1434 bufpoi += toread;
1435 length -= toread;
1436 }
1437 if (length > 0)
1438 chip->read_buf(mtd, bufpoi, length);
1439
1440 return 1;
1441}
1442
1443/**
1444 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1445 * @mtd: mtd info structure
1446 * @chip: nand chip info structure
1447 * @page: page number to write
1448 */
1449static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1450 int page)
1451{
1452 int status = 0;
1453 const uint8_t *buf = chip->oob_poi;
1454 int length = mtd->oobsize;
1455
1456 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1457 chip->write_buf(mtd, buf, length);
1458 /* Send command to program the OOB data */
1459 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1460
1461 status = chip->waitfunc(mtd, chip);
1462
0d420f9d 1463 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1464}
1465
1466/**
1467 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1468 * with syndrome - only for large page flash !
1469 * @mtd: mtd info structure
1470 * @chip: nand chip info structure
1471 * @page: page number to write
1472 */
1473static int nand_write_oob_syndrome(struct mtd_info *mtd,
1474 struct nand_chip *chip, int page)
1475{
1476 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1477 int eccsize = chip->ecc.size, length = mtd->oobsize;
1478 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1479 const uint8_t *bufpoi = chip->oob_poi;
1480
1481 /*
1482 * data-ecc-data-ecc ... ecc-oob
1483 * or
1484 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1485 */
1486 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1487 pos = steps * (eccsize + chunk);
1488 steps = 0;
1489 } else
8b0036ee 1490 pos = eccsize;
7bc3312b
TG		 1491
1492 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1493 for (i = 0; i < steps; i++) {
1494 if (sndcmd) {
1495 if (mtd->writesize <= 512) {
1496 uint32_t fill = 0xFFFFFFFF;
1497
1498 len = eccsize;
1499 while (len > 0) {
1500 int num = min_t(int, len, 4);
1501 chip->write_buf(mtd, (uint8_t *)&fill,
1502 num);
1503 len -= num;
1504 }
1505 } else {
1506 pos = eccsize + i * (eccsize + chunk);
1507 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1508 }
1509 } else
1510 sndcmd = 1;
1511 len = min_t(int, length, chunk);
1512 chip->write_buf(mtd, bufpoi, len);
1513 bufpoi += len;
1514 length -= len;
1515 }
1516 if (length > 0)
1517 chip->write_buf(mtd, bufpoi, length);
1518
1519 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1520 status = chip->waitfunc(mtd, chip);
1521
1522 return status & NAND_STATUS_FAIL ? -EIO : 0;
1523}
1524
1da177e4 1525/**
8593fbc6 1526 * nand_do_read_oob - [Intern] NAND read out-of-band
1da177e4
LT		 1527 * @mtd: MTD device structure
1528 * @from: offset to read from
8593fbc6 1529 * @ops: oob operations description structure
1da177e4
LT		 1530 *
1531 * NAND read out-of-band data from the spare area
1532 */
8593fbc6
TG		 1533static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1534 struct mtd_oob_ops *ops)
1da177e4 1535{
7bc3312b 1536 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1537 struct nand_chip *chip = mtd->priv;
7314e9e7 1538 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1539 int readlen = ops->ooblen;
1540 int len;
7bc3312b 1541 uint8_t *buf = ops->oobbuf;
61b03bd7 1542
20d8e248 1543 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1544 __func__, (unsigned long long)from, readlen);
1da177e4 1545
03736155 1546 if (ops->mode == MTD_OOB_AUTO)
7014568b 1547 len = chip->ecc.layout->oobavail;
03736155
AH		 1548 else
1549 len = mtd->oobsize;
1550
1551 if (unlikely(ops->ooboffs >= len)) {
20d8e248 1552 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1553 "outside oob\n", __func__);
03736155
AH		 1554 return -EINVAL;
1555 }
1556
1557 /* Do not allow reads past end of device */
1558 if (unlikely(from >= mtd->size ||
1559 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1560 (from >> chip->page_shift)) * len)) {
20d8e248 1561 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1562 "of device\n", __func__);
03736155
AH		 1563 return -EINVAL;
1564 }
7014568b 1565
7314e9e7 1566 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1567 chip->select_chip(mtd, chipnr);
1da177e4 1568
7314e9e7
TG		 1569 /* Shift to get page */
1570 realpage = (int)(from >> chip->page_shift);
1571 page = realpage & chip->pagemask;
1da177e4 1572
7314e9e7 1573 while(1) {
7bc3312b 1574 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1575
1576 len = min(len, readlen);
1577 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1578
7314e9e7
TG		 1579 if (!(chip->options & NAND_NO_READRDY)) {
1580 /*
1581 * Apply delay or wait for ready/busy pin. Do this
1582 * before the AUTOINCR check, so no problems arise if a
1583 * chip which does auto increment is marked as
1584 * NOAUTOINCR by the board driver.
19870da7 1585 */
ace4dfee
TG		 1586 if (!chip->dev_ready)
1587 udelay(chip->chip_delay);
19870da7
TG		 1588 else
1589 nand_wait_ready(mtd);
7314e9e7 1590 }
19870da7 1591
7014568b 1592 readlen -= len;
0d420f9d
SZ		 1593 if (!readlen)
1594 break;
1595
7314e9e7
TG		 1596 /* Increment page address */
1597 realpage++;
1598
1599 page = realpage & chip->pagemask;
1600 /* Check, if we cross a chip boundary */
1601 if (!page) {
1602 chipnr++;
1603 chip->select_chip(mtd, -1);
1604 chip->select_chip(mtd, chipnr);
1da177e4 1605 }
7314e9e7
TG		 1606
1607 /* Check, if the chip supports auto page increment
1608 * or if we have hit a block boundary.
1609 */
1610 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1611 sndcmd = 1;
1da177e4
LT		 1612 }
1613
7014568b 1614 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1615 return 0;
1616}
1617
1618/**
8593fbc6 1619 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1da177e4 1620 * @mtd: MTD device structure
1da177e4 1621 * @from: offset to read from
8593fbc6 1622 * @ops: oob operation description structure
1da177e4 1623 *
8593fbc6 1624 * NAND read data and/or out-of-band data
1da177e4 1625 */
8593fbc6
TG		 1626static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1627 struct mtd_oob_ops *ops)
1da177e4 1628{
ace4dfee 1629 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1630 int ret = -ENOTSUPP;
1631
1632 ops->retlen = 0;
1da177e4
LT		 1633
1634 /* Do not allow reads past end of device */
7014568b 1635 if (ops->datbuf && (from + ops->len) > mtd->size) {
20d8e248 1636 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1637 "beyond end of device\n", __func__);
1da177e4
LT		 1638 return -EINVAL;
1639 }
1640
ace4dfee 1641 nand_get_device(chip, mtd, FL_READING);
1da177e4 1642
8593fbc6
TG		 1643 switch(ops->mode) {
1644 case MTD_OOB_PLACE:
1645 case MTD_OOB_AUTO:
8593fbc6 1646 case MTD_OOB_RAW:
8593fbc6 1647 break;
1da177e4 1648
8593fbc6
TG		 1649 default:
1650 goto out;
1651 }
1da177e4 1652
8593fbc6
TG		 1653 if (!ops->datbuf)
1654 ret = nand_do_read_oob(mtd, from, ops);
1655 else
1656 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1657
8593fbc6
TG		 1658 out:
1659 nand_release_device(mtd);
1660 return ret;
1661}
61b03bd7 1662
1da177e4 1663
8593fbc6
TG		 1664/**
1665 * nand_write_page_raw - [Intern] raw page write function
1666 * @mtd: mtd info structure
1667 * @chip: nand chip info structure
1668 * @buf: data buffer
52ff49df
DB		 1669 *
1670 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1671 */
1672static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1673 const uint8_t *buf)
1674{
1675 chip->write_buf(mtd, buf, mtd->writesize);
1676 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1677}
1678
52ff49df
DB		 1679/**
1680 * nand_write_page_raw_syndrome - [Intern] raw page write function
1681 * @mtd: mtd info structure
1682 * @chip: nand chip info structure
1683 * @buf: data buffer
1684 *
1685 * We need a special oob layout and handling even when ECC isn't checked.
1686 */
1687static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1688 const uint8_t *buf)
1689{
1690 int eccsize = chip->ecc.size;
1691 int eccbytes = chip->ecc.bytes;
1692 uint8_t *oob = chip->oob_poi;
1693 int steps, size;
1694
1695 for (steps = chip->ecc.steps; steps > 0; steps--) {
1696 chip->write_buf(mtd, buf, eccsize);
1697 buf += eccsize;
1698
1699 if (chip->ecc.prepad) {
1700 chip->write_buf(mtd, oob, chip->ecc.prepad);
1701 oob += chip->ecc.prepad;
1702 }
1703
1704 chip->read_buf(mtd, oob, eccbytes);
1705 oob += eccbytes;
1706
1707 if (chip->ecc.postpad) {
1708 chip->write_buf(mtd, oob, chip->ecc.postpad);
1709 oob += chip->ecc.postpad;
1710 }
1711 }
1712
1713 size = mtd->oobsize - (oob - chip->oob_poi);
1714 if (size)
1715 chip->write_buf(mtd, oob, size);
1716}
9223a456 1717/**
d29ebdbe 1718 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
f75e5097
TG		 1719 * @mtd: mtd info structure
1720 * @chip: nand chip info structure
1721 * @buf: data buffer
9223a456 1722 */
f75e5097
TG		 1723static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1724 const uint8_t *buf)
9223a456 1725{
f75e5097
TG		 1726 int i, eccsize = chip->ecc.size;
1727 int eccbytes = chip->ecc.bytes;
1728 int eccsteps = chip->ecc.steps;
4bf63fcb 1729 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1730 const uint8_t *p = buf;
8b099a39 1731 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1732
8593fbc6
TG		 1733 /* Software ecc calculation */
1734 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1735 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1736
8593fbc6
TG		 1737 for (i = 0; i < chip->ecc.total; i++)
1738 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1739
90424de8 1740 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1741}
9223a456 1742
f75e5097 1743/**
d29ebdbe 1744 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
f75e5097
TG		 1745 * @mtd: mtd info structure
1746 * @chip: nand chip info structure
1747 * @buf: data buffer
1748 */
1749static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1750 const uint8_t *buf)
1751{
1752 int i, eccsize = chip->ecc.size;
1753 int eccbytes = chip->ecc.bytes;
1754 int eccsteps = chip->ecc.steps;
4bf63fcb 1755 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1756 const uint8_t *p = buf;
8b099a39 1757 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1758
f75e5097
TG		 1759 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1760 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1761 chip->write_buf(mtd, p, eccsize);
f75e5097 1762 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1763 }
1764
f75e5097
TG		 1765 for (i = 0; i < chip->ecc.total; i++)
1766 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1767
1768 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 1769}
1770
61b03bd7 1771/**
d29ebdbe 1772 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
f75e5097
TG		 1773 * @mtd: mtd info structure
1774 * @chip: nand chip info structure
1775 * @buf: data buffer
1da177e4 1776 *
f75e5097
TG		 1777 * The hw generator calculates the error syndrome automatically. Therefor
1778 * we need a special oob layout and handling.
1779 */
1780static void nand_write_page_syndrome(struct mtd_info *mtd,
1781 struct nand_chip *chip, const uint8_t *buf)
1da177e4 1782{
f75e5097
TG		 1783 int i, eccsize = chip->ecc.size;
1784 int eccbytes = chip->ecc.bytes;
1785 int eccsteps = chip->ecc.steps;
1786 const uint8_t *p = buf;
1787 uint8_t *oob = chip->oob_poi;
1da177e4 1788
f75e5097 1789 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 1790
f75e5097
TG		 1791 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1792 chip->write_buf(mtd, p, eccsize);
61b03bd7 1793
f75e5097
TG		 1794 if (chip->ecc.prepad) {
1795 chip->write_buf(mtd, oob, chip->ecc.prepad);
1796 oob += chip->ecc.prepad;
1797 }
1798
1799 chip->ecc.calculate(mtd, p, oob);
1800 chip->write_buf(mtd, oob, eccbytes);
1801 oob += eccbytes;
1802
1803 if (chip->ecc.postpad) {
1804 chip->write_buf(mtd, oob, chip->ecc.postpad);
1805 oob += chip->ecc.postpad;
1da177e4 1806 }
1da177e4 1807 }
f75e5097
TG		 1808
1809 /* Calculate remaining oob bytes */
7e4178f9 1810 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 1811 if (i)
1812 chip->write_buf(mtd, oob, i);
1813}
1814
1815/**
956e944c 1816 * nand_write_page - [REPLACEABLE] write one page
f75e5097
TG		 1817 * @mtd: MTD device structure
1818 * @chip: NAND chip descriptor
1819 * @buf: the data to write
1820 * @page: page number to write
1821 * @cached: cached programming
efbfe96c 1822 * @raw: use _raw version of write_page
f75e5097
TG		 1823 */
1824static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 1825 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 1826{
1827 int status;
1828
1829 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1830
956e944c
DW		 1831 if (unlikely(raw))
1832 chip->ecc.write_page_raw(mtd, chip, buf);
1833 else
1834 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 1835
1836 /*
1837 * Cached progamming disabled for now, Not sure if its worth the
1838 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1839 */
1840 cached = 0;
1841
1842 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1843
1844 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 1845 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 1846 /*
1847 * See if operation failed and additional status checks are
1848 * available
1849 */
1850 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1851 status = chip->errstat(mtd, chip, FL_WRITING, status,
1852 page);
1853
1854 if (status & NAND_STATUS_FAIL)
1855 return -EIO;
1856 } else {
1857 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 1858 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 1859 }
1860
1861#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1862 /* Send command to read back the data */
1863 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1864
1865 if (chip->verify_buf(mtd, buf, mtd->writesize))
1866 return -EIO;
1867#endif
1868 return 0;
1da177e4
LT		 1869}
1870
8593fbc6
TG		 1871/**
1872 * nand_fill_oob - [Internal] Transfer client buffer to oob
1873 * @chip: nand chip structure
1874 * @oob: oob data buffer
1875 * @ops: oob ops structure
1876 */
1877static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1878 struct mtd_oob_ops *ops)
1879{
1880 size_t len = ops->ooblen;
1881
1882 switch(ops->mode) {
1883
1884 case MTD_OOB_PLACE:
1885 case MTD_OOB_RAW:
1886 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1887 return oob + len;
1888
1889 case MTD_OOB_AUTO: {
1890 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1891 uint32_t boffs = 0, woffs = ops->ooboffs;
1892 size_t bytes = 0;
8593fbc6
TG		 1893
1894 for(; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1895 /* Write request not from offset 0 ? */
1896 if (unlikely(woffs)) {
1897 if (woffs >= free->length) {
1898 woffs -= free->length;
1899 continue;
1900 }
1901 boffs = free->offset + woffs;
1902 bytes = min_t(size_t, len,
1903 (free->length - woffs));
1904 woffs = 0;
1905 } else {
1906 bytes = min_t(size_t, len, free->length);
1907 boffs = free->offset;
1908 }
8b0036ee 1909 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 1910 oob += bytes;
1911 }
1912 return oob;
1913 }
1914 default:
1915 BUG();
1916 }
1917 return NULL;
1918}
1919
29072b96 1920#define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1da177e4
LT		 1921
1922/**
8593fbc6 1923 * nand_do_write_ops - [Internal] NAND write with ECC
1da177e4
LT		 1924 * @mtd: MTD device structure
1925 * @to: offset to write to
8593fbc6 1926 * @ops: oob operations description structure
1da177e4
LT		 1927 *
1928 * NAND write with ECC
1929 */
8593fbc6
TG		 1930static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1931 struct mtd_oob_ops *ops)
1da177e4 1932{
29072b96 1933 int chipnr, realpage, page, blockmask, column;
ace4dfee 1934 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1935 uint32_t writelen = ops->len;
1936 uint8_t *oob = ops->oobbuf;
1937 uint8_t *buf = ops->datbuf;
29072b96 1938 int ret, subpage;
1da177e4 1939
8593fbc6 1940 ops->retlen = 0;
29072b96
TG		 1941 if (!writelen)
1942 return 0;
1da177e4 1943
61b03bd7 1944 /* reject writes, which are not page aligned */
8593fbc6 1945 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
20d8e248 1946 printk(KERN_NOTICE "%s: Attempt to write not "
1947 "page aligned data\n", __func__);
1da177e4
LT		 1948 return -EINVAL;
1949 }
1950
29072b96
TG		 1951 column = to & (mtd->writesize - 1);
1952 subpage = column || (writelen & (mtd->writesize - 1));
1953
1954 if (subpage && oob)
1955 return -EINVAL;
1da177e4 1956
6a930961
TG		 1957 chipnr = (int)(to >> chip->chip_shift);
1958 chip->select_chip(mtd, chipnr);
1959
1da177e4
LT		 1960 /* Check, if it is write protected */
1961 if (nand_check_wp(mtd))
8593fbc6 1962 return -EIO;
1da177e4 1963
f75e5097
TG		 1964 realpage = (int)(to >> chip->page_shift);
1965 page = realpage & chip->pagemask;
1966 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1967
1968 /* Invalidate the page cache, when we write to the cached page */
1969 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 1970 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 1971 chip->pagebuf = -1;
61b03bd7 1972
7dcdcbef
DW		 1973 /* If we're not given explicit OOB data, let it be 0xFF */
1974 if (likely(!oob))
1975 memset(chip->oob_poi, 0xff, mtd->oobsize);
61b03bd7 1976
f75e5097 1977 while(1) {
29072b96 1978 int bytes = mtd->writesize;
f75e5097 1979 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 1980 uint8_t *wbuf = buf;
1981
1982 /* Partial page write ? */
1983 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1984 cached = 0;
1985 bytes = min_t(int, bytes - column, (int) writelen);
1986 chip->pagebuf = -1;
1987 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1988 memcpy(&chip->buffers->databuf[column], buf, bytes);
1989 wbuf = chip->buffers->databuf;
1990 }
1da177e4 1991
8593fbc6
TG		 1992 if (unlikely(oob))
1993 oob = nand_fill_oob(chip, oob, ops);
1994
29072b96 1995 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 1996 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 1997 if (ret)
1998 break;
1999
2000 writelen -= bytes;
2001 if (!writelen)
2002 break;
2003
29072b96 2004 column = 0;
f75e5097
TG		 2005 buf += bytes;
2006 realpage++;
2007
2008 page = realpage & chip->pagemask;
2009 /* Check, if we cross a chip boundary */
2010 if (!page) {
2011 chipnr++;
2012 chip->select_chip(mtd, -1);
2013 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2014 }
2015 }
8593fbc6 2016
8593fbc6 2017 ops->retlen = ops->len - writelen;
7014568b
VW		 2018 if (unlikely(oob))
2019 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2020 return ret;
2021}
2022
2af7c653
SK		 2023/**
2024 * panic_nand_write - [MTD Interface] NAND write with ECC
2025 * @mtd: MTD device structure
2026 * @to: offset to write to
2027 * @len: number of bytes to write
2028 * @retlen: pointer to variable to store the number of written bytes
2029 * @buf: the data to write
2030 *
2031 * NAND write with ECC. Used when performing writes in interrupt context, this
2032 * may for example be called by mtdoops when writing an oops while in panic.
2033 */
2034static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2035 size_t *retlen, const uint8_t *buf)
2036{
2037 struct nand_chip *chip = mtd->priv;
2038 int ret;
2039
2040 /* Do not allow reads past end of device */
2041 if ((to + len) > mtd->size)
2042 return -EINVAL;
2043 if (!len)
2044 return 0;
2045
2046 /* Wait for the device to get ready. */
2047 panic_nand_wait(mtd, chip, 400);
2048
2049 /* Grab the device. */
2050 panic_nand_get_device(chip, mtd, FL_WRITING);
2051
2052 chip->ops.len = len;
2053 chip->ops.datbuf = (uint8_t *)buf;
2054 chip->ops.oobbuf = NULL;
2055
2056 ret = nand_do_write_ops(mtd, to, &chip->ops);
2057
2058 *retlen = chip->ops.retlen;
2059 return ret;
2060}
2061
f75e5097 2062/**
8593fbc6 2063 * nand_write - [MTD Interface] NAND write with ECC
f75e5097 2064 * @mtd: MTD device structure
f75e5097
TG		 2065 * @to: offset to write to
2066 * @len: number of bytes to write
8593fbc6
TG		 2067 * @retlen: pointer to variable to store the number of written bytes
2068 * @buf: the data to write
f75e5097 2069 *
8593fbc6 2070 * NAND write with ECC
f75e5097 2071 */
8593fbc6
TG		 2072static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2073 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2074{
2075 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 2076 int ret;
2077
8593fbc6
TG		 2078 /* Do not allow reads past end of device */
2079 if ((to + len) > mtd->size)
f75e5097 2080 return -EINVAL;
8593fbc6
TG		 2081 if (!len)
2082 return 0;
f75e5097 2083
7bc3312b 2084 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 2085
8593fbc6
TG		 2086 chip->ops.len = len;
2087 chip->ops.datbuf = (uint8_t *)buf;
2088 chip->ops.oobbuf = NULL;
f75e5097 2089
8593fbc6 2090 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 2091
7fd5aecc
RP		 2092 *retlen = chip->ops.retlen;
2093
f75e5097 2094 nand_release_device(mtd);
8593fbc6 2095
8593fbc6 2096 return ret;
f75e5097 2097}
7314e9e7 2098
1da177e4 2099/**
8593fbc6 2100 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1da177e4
LT		 2101 * @mtd: MTD device structure
2102 * @to: offset to write to
8593fbc6 2103 * @ops: oob operation description structure
1da177e4
LT		 2104 *
2105 * NAND write out-of-band
2106 */
8593fbc6
TG		 2107static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2108 struct mtd_oob_ops *ops)
1da177e4 2109{
03736155 2110 int chipnr, page, status, len;
ace4dfee 2111 struct nand_chip *chip = mtd->priv;
1da177e4 2112
20d8e248 2113 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2114 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2115
03736155
AH		 2116 if (ops->mode == MTD_OOB_AUTO)
2117 len = chip->ecc.layout->oobavail;
2118 else
2119 len = mtd->oobsize;
2120
1da177e4 2121 /* Do not allow write past end of page */
03736155 2122 if ((ops->ooboffs + ops->ooblen) > len) {
20d8e248 2123 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2124 "past end of page\n", __func__);
1da177e4
LT		 2125 return -EINVAL;
2126 }
2127
03736155 2128 if (unlikely(ops->ooboffs >= len)) {
20d8e248 2129 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2130 "write outside oob\n", __func__);
03736155
AH		 2131 return -EINVAL;
2132 }
2133
2134 /* Do not allow reads past end of device */
2135 if (unlikely(to >= mtd->size ||
2136 ops->ooboffs + ops->ooblen >
2137 ((mtd->size >> chip->page_shift) -
2138 (to >> chip->page_shift)) * len)) {
20d8e248 2139 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2140 "end of device\n", __func__);
03736155
AH		 2141 return -EINVAL;
2142 }
2143
7314e9e7 2144 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2145 chip->select_chip(mtd, chipnr);
1da177e4 2146
7314e9e7
TG		 2147 /* Shift to get page */
2148 page = (int)(to >> chip->page_shift);
2149
2150 /*
2151 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2152 * of my DiskOnChip 2000 test units) will clear the whole data page too
2153 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2154 * it in the doc2000 driver in August 1999. dwmw2.
2155 */
ace4dfee 2156 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2157
2158 /* Check, if it is write protected */
2159 if (nand_check_wp(mtd))
8593fbc6 2160 return -EROFS;
61b03bd7 2161
1da177e4 2162 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2163 if (page == chip->pagebuf)
2164 chip->pagebuf = -1;
1da177e4 2165
7bc3312b
TG		 2166 memset(chip->oob_poi, 0xff, mtd->oobsize);
2167 nand_fill_oob(chip, ops->oobbuf, ops);
2168 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2169 memset(chip->oob_poi, 0xff, mtd->oobsize);
1da177e4 2170
7bc3312b
TG		 2171 if (status)
2172 return status;
1da177e4 2173
7014568b 2174 ops->oobretlen = ops->ooblen;
1da177e4 2175
7bc3312b 2176 return 0;
8593fbc6
TG		 2177}
2178
2179/**
2180 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2181 * @mtd: MTD device structure
844d3b42 2182 * @to: offset to write to
8593fbc6
TG		 2183 * @ops: oob operation description structure
2184 */
2185static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2186 struct mtd_oob_ops *ops)
2187{
8593fbc6
TG		 2188 struct nand_chip *chip = mtd->priv;
2189 int ret = -ENOTSUPP;
2190
2191 ops->retlen = 0;
2192
2193 /* Do not allow writes past end of device */
7014568b 2194 if (ops->datbuf && (to + ops->len) > mtd->size) {
20d8e248 2195 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2196 "end of device\n", __func__);
8593fbc6
TG		 2197 return -EINVAL;
2198 }
2199
7bc3312b 2200 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6
TG		 2201
2202 switch(ops->mode) {
2203 case MTD_OOB_PLACE:
2204 case MTD_OOB_AUTO:
8593fbc6 2205 case MTD_OOB_RAW:
8593fbc6
TG		 2206 break;
2207
2208 default:
2209 goto out;
2210 }
2211
2212 if (!ops->datbuf)
2213 ret = nand_do_write_oob(mtd, to, ops);
2214 else
2215 ret = nand_do_write_ops(mtd, to, ops);
2216
e0c7d767 2217 out:
1da177e4 2218 nand_release_device(mtd);
1da177e4
LT		 2219 return ret;
2220}
2221
1da177e4
LT		 2222/**
2223 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2224 * @mtd: MTD device structure
2225 * @page: the page address of the block which will be erased
2226 *
2227 * Standard erase command for NAND chips
2228 */
e0c7d767 2229static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2230{
ace4dfee 2231 struct nand_chip *chip = mtd->priv;
1da177e4 2232 /* Send commands to erase a block */
ace4dfee
TG		 2233 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2234 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2235}
2236
2237/**
2238 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2239 * @mtd: MTD device structure
2240 * @page: the page address of the block which will be erased
2241 *
2242 * AND multi block erase command function
2243 * Erase 4 consecutive blocks
2244 */
e0c7d767 2245static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2246{
ace4dfee 2247 struct nand_chip *chip = mtd->priv;
1da177e4 2248 /* Send commands to erase a block */
ace4dfee
TG		 2249 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2250 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2251 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2252 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2253 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2254}
2255
2256/**
2257 * nand_erase - [MTD Interface] erase block(s)
2258 * @mtd: MTD device structure
2259 * @instr: erase instruction
2260 *
2261 * Erase one ore more blocks
2262 */
e0c7d767 2263static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2264{
e0c7d767 2265 return nand_erase_nand(mtd, instr, 0);
1da177e4 2266}
61b03bd7 2267
30f464b7 2268#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2269/**
ace4dfee 2270 * nand_erase_nand - [Internal] erase block(s)
1da177e4
LT		 2271 * @mtd: MTD device structure
2272 * @instr: erase instruction
2273 * @allowbbt: allow erasing the bbt area
2274 *
2275 * Erase one ore more blocks
2276 */
ace4dfee
TG		 2277int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2278 int allowbbt)
1da177e4 2279{
69423d99 2280 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2281 struct nand_chip *chip = mtd->priv;
69423d99 2282 loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
ace4dfee 2283 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2284 loff_t len;
1da177e4 2285
20d8e248 2286 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2287 __func__, (unsigned long long)instr->addr,
2288 (unsigned long long)instr->len);
1da177e4
LT		 2289
2290 /* Start address must align on block boundary */
ace4dfee 2291 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
20d8e248 2292 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
1da177e4
LT		 2293 return -EINVAL;
2294 }
2295
2296 /* Length must align on block boundary */
ace4dfee 2297 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
20d8e248 2298 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
2299 __func__);
1da177e4
LT		 2300 return -EINVAL;
2301 }
2302
2303 /* Do not allow erase past end of device */
2304 if ((instr->len + instr->addr) > mtd->size) {
20d8e248 2305 DEBUG(MTD_DEBUG_LEVEL0, "%s: Erase past end of device\n",
2306 __func__);
1da177e4
LT		 2307 return -EINVAL;
2308 }
2309
bb0eb217 2310 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2311
2312 /* Grab the lock and see if the device is available */
ace4dfee 2313 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2314
2315 /* Shift to get first page */
ace4dfee
TG		 2316 page = (int)(instr->addr >> chip->page_shift);
2317 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2318
2319 /* Calculate pages in each block */
ace4dfee 2320 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2321
2322 /* Select the NAND device */
ace4dfee 2323 chip->select_chip(mtd, chipnr);
1da177e4 2324
1da177e4
LT		 2325 /* Check, if it is write protected */
2326 if (nand_check_wp(mtd)) {
20d8e248 2327 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2328 __func__);
1da177e4
LT		 2329 instr->state = MTD_ERASE_FAILED;
2330 goto erase_exit;
2331 }
2332
ace4dfee
TG		 2333 /*
2334 * If BBT requires refresh, set the BBT page mask to see if the BBT
2335 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2336 * can not be matched. This is also done when the bbt is actually
2337 * erased to avoid recusrsive updates
2338 */
2339 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2340 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2341
1da177e4
LT		 2342 /* Loop through the pages */
2343 len = instr->len;
2344
2345 instr->state = MTD_ERASING;
2346
2347 while (len) {
ace4dfee
TG		 2348 /*
2349 * heck if we have a bad block, we do not erase bad blocks !
2350 */
2351 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2352 chip->page_shift, 0, allowbbt)) {
20d8e248 2353 printk(KERN_WARNING "%s: attempt to erase a bad block "
2354 "at page 0x%08x\n", __func__, page);
1da177e4
LT		 2355 instr->state = MTD_ERASE_FAILED;
2356 goto erase_exit;
2357 }
61b03bd7 2358
ace4dfee
TG		 2359 /*
2360 * Invalidate the page cache, if we erase the block which
2361 * contains the current cached page
2362 */
2363 if (page <= chip->pagebuf && chip->pagebuf <
2364 (page + pages_per_block))
2365 chip->pagebuf = -1;
1da177e4 2366
ace4dfee 2367 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2368
7bc3312b 2369 status = chip->waitfunc(mtd, chip);
1da177e4 2370
ace4dfee
TG		 2371 /*
2372 * See if operation failed and additional status checks are
2373 * available
2374 */
2375 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2376 status = chip->errstat(mtd, chip, FL_ERASING,
2377 status, page);
068e3c0a 2378
1da177e4 2379 /* See if block erase succeeded */
a4ab4c5d 2380 if (status & NAND_STATUS_FAIL) {
20d8e248 2381 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2382 "page 0x%08x\n", __func__, page);
1da177e4 2383 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2384 instr->fail_addr =
2385 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2386 goto erase_exit;
2387 }
30f464b7 2388
ace4dfee
TG		 2389 /*
2390 * If BBT requires refresh, set the BBT rewrite flag to the
2391 * page being erased
2392 */
2393 if (bbt_masked_page != 0xffffffff &&
2394 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2395 rewrite_bbt[chipnr] =
2396 ((loff_t)page << chip->page_shift);
61b03bd7 2397
1da177e4 2398 /* Increment page address and decrement length */
ace4dfee 2399 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2400 page += pages_per_block;
2401
2402 /* Check, if we cross a chip boundary */
ace4dfee 2403 if (len && !(page & chip->pagemask)) {
1da177e4 2404 chipnr++;
ace4dfee
TG		 2405 chip->select_chip(mtd, -1);
2406 chip->select_chip(mtd, chipnr);
30f464b7 2407
ace4dfee
TG		 2408 /*
2409 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2410 * page mask to see if this BBT should be rewritten
2411 */
2412 if (bbt_masked_page != 0xffffffff &&
2413 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2414 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2415 BBT_PAGE_MASK;
1da177e4
LT		 2416 }
2417 }
2418 instr->state = MTD_ERASE_DONE;
2419
e0c7d767 2420 erase_exit:
1da177e4
LT		 2421
2422 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2423
2424 /* Deselect and wake up anyone waiting on the device */
2425 nand_release_device(mtd);
2426
49defc01
DW		 2427 /* Do call back function */
2428 if (!ret)
2429 mtd_erase_callback(instr);
2430
ace4dfee
TG		 2431 /*
2432 * If BBT requires refresh and erase was successful, rewrite any
2433 * selected bad block tables
2434 */
2435 if (bbt_masked_page == 0xffffffff || ret)
2436 return ret;
2437
2438 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2439 if (!rewrite_bbt[chipnr])
2440 continue;
2441 /* update the BBT for chip */
20d8e248 2442 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2443 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2444 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
ace4dfee 2445 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2446 }
2447
1da177e4
LT		 2448 /* Return more or less happy */
2449 return ret;
2450}
2451
2452/**
2453 * nand_sync - [MTD Interface] sync
2454 * @mtd: MTD device structure
2455 *
2456 * Sync is actually a wait for chip ready function
2457 */
e0c7d767 2458static void nand_sync(struct mtd_info *mtd)
1da177e4 2459{
ace4dfee 2460 struct nand_chip *chip = mtd->priv;
1da177e4 2461
20d8e248 2462 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
1da177e4
LT		 2463
2464 /* Grab the lock and see if the device is available */
ace4dfee 2465 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2466 /* Release it and go back */
e0c7d767 2467 nand_release_device(mtd);
1da177e4
LT		 2468}
2469
1da177e4 2470/**
ace4dfee 2471 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1da177e4 2472 * @mtd: MTD device structure
844d3b42 2473 * @offs: offset relative to mtd start
1da177e4 2474 */
ace4dfee 2475static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2476{
2477 /* Check for invalid offset */
ace4dfee 2478 if (offs > mtd->size)
1da177e4 2479 return -EINVAL;
61b03bd7 2480
ace4dfee 2481 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2482}
2483
2484/**
ace4dfee 2485 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1da177e4
LT		 2486 * @mtd: MTD device structure
2487 * @ofs: offset relative to mtd start
2488 */
e0c7d767 2489static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2490{
ace4dfee 2491 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2492 int ret;
2493
e0c7d767
DW		 2494 if ((ret = nand_block_isbad(mtd, ofs))) {
2495 /* If it was bad already, return success and do nothing. */
1da177e4
LT		 2496 if (ret > 0)
2497 return 0;
e0c7d767
DW		 2498 return ret;
2499 }
1da177e4 2500
ace4dfee 2501 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2502}
2503
962034f4
VW		 2504/**
2505 * nand_suspend - [MTD Interface] Suspend the NAND flash
2506 * @mtd: MTD device structure
2507 */
2508static int nand_suspend(struct mtd_info *mtd)
2509{
ace4dfee 2510 struct nand_chip *chip = mtd->priv;
962034f4 2511
ace4dfee 2512 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2513}
2514
2515/**
2516 * nand_resume - [MTD Interface] Resume the NAND flash
2517 * @mtd: MTD device structure
2518 */
2519static void nand_resume(struct mtd_info *mtd)
2520{
ace4dfee 2521 struct nand_chip *chip = mtd->priv;
962034f4 2522
ace4dfee 2523 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2524 nand_release_device(mtd);
2525 else
20d8e248 2526 printk(KERN_ERR "%s called for a chip which is not "
2527 "in suspended state\n", __func__);
962034f4
VW		 2528}
2529
7aa65bfd
TG		 2530/*
2531 * Set default functions
2532 */
ace4dfee 2533static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2534{
1da177e4 2535 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2536 if (!chip->chip_delay)
2537 chip->chip_delay = 20;
1da177e4
LT		 2538
2539 /* check, if a user supplied command function given */
ace4dfee
TG		 2540 if (chip->cmdfunc == NULL)
2541 chip->cmdfunc = nand_command;
1da177e4
LT		 2542
2543 /* check, if a user supplied wait function given */
ace4dfee
TG		 2544 if (chip->waitfunc == NULL)
2545 chip->waitfunc = nand_wait;
2546
2547 if (!chip->select_chip)
2548 chip->select_chip = nand_select_chip;
2549 if (!chip->read_byte)
2550 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2551 if (!chip->read_word)
2552 chip->read_word = nand_read_word;
2553 if (!chip->block_bad)
2554 chip->block_bad = nand_block_bad;
2555 if (!chip->block_markbad)
2556 chip->block_markbad = nand_default_block_markbad;
2557 if (!chip->write_buf)
2558 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2559 if (!chip->read_buf)
2560 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2561 if (!chip->verify_buf)
2562 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2563 if (!chip->scan_bbt)
2564 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2565
2566 if (!chip->controller) {
2567 chip->controller = &chip->hwcontrol;
2568 spin_lock_init(&chip->controller->lock);
2569 init_waitqueue_head(&chip->controller->wq);
2570 }
2571
7aa65bfd
TG		 2572}
2573
2574/*
ace4dfee 2575 * Get the flash and manufacturer id and lookup if the type is supported
7aa65bfd
TG		 2576 */
2577static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2578 struct nand_chip *chip,
7aa65bfd
TG		 2579 int busw, int *maf_id)
2580{
2581 struct nand_flash_dev *type = NULL;
2582 int i, dev_id, maf_idx;
ed8165c7 2583 int tmp_id, tmp_manf;
1da177e4
LT		 2584
2585 /* Select the device */
ace4dfee 2586 chip->select_chip(mtd, 0);
1da177e4 2587
ef89a880
KB		 2588 /*
2589 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2590 * after power-up
2591 */
2592 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2593
1da177e4 2594 /* Send the command for reading device ID */
ace4dfee 2595 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2596
2597 /* Read manufacturer and device IDs */
ace4dfee
TG		 2598 *maf_id = chip->read_byte(mtd);
2599 dev_id = chip->read_byte(mtd);
1da177e4 2600
ed8165c7
BD		 2601 /* Try again to make sure, as some systems the bus-hold or other
2602 * interface concerns can cause random data which looks like a
2603 * possibly credible NAND flash to appear. If the two results do
2604 * not match, ignore the device completely.
2605 */
2606
2607 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2608
2609 /* Read manufacturer and device IDs */
2610
2611 tmp_manf = chip->read_byte(mtd);
2612 tmp_id = chip->read_byte(mtd);
2613
2614 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2615 printk(KERN_INFO "%s: second ID read did not match "
2616 "%02x,%02x against %02x,%02x\n", __func__,
2617 *maf_id, dev_id, tmp_manf, tmp_id);
2618 return ERR_PTR(-ENODEV);
2619 }
2620
7aa65bfd 2621 /* Lookup the flash id */
1da177e4 2622 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
7aa65bfd
TG		 2623 if (dev_id == nand_flash_ids[i].id) {
2624 type = &nand_flash_ids[i];
2625 break;
2626 }
2627 }
61b03bd7 2628
7aa65bfd
TG		 2629 if (!type)
2630 return ERR_PTR(-ENODEV);
2631
ba0251fe
TG		 2632 if (!mtd->name)
2633 mtd->name = type->name;
2634
69423d99 2635 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd
TG		 2636
2637 /* Newer devices have all the information in additional id bytes */
ba0251fe 2638 if (!type->pagesize) {
7aa65bfd 2639 int extid;
29072b96
TG		 2640 /* The 3rd id byte holds MLC / multichip data */
2641 chip->cellinfo = chip->read_byte(mtd);
7aa65bfd 2642 /* The 4th id byte is the important one */
ace4dfee 2643 extid = chip->read_byte(mtd);
7aa65bfd 2644 /* Calc pagesize */
4cbb9b80 2645 mtd->writesize = 1024 << (extid & 0x3);
7aa65bfd
TG		 2646 extid >>= 2;
2647 /* Calc oobsize */
4cbb9b80 2648 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
7aa65bfd
TG		 2649 extid >>= 2;
2650 /* Calc blocksize. Blocksize is multiples of 64KiB */
2651 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2652 extid >>= 2;
2653 /* Get buswidth information */
2654 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
61b03bd7 2655
7aa65bfd
TG		 2656 } else {
2657 /*
ace4dfee 2658 * Old devices have chip data hardcoded in the device id table
7aa65bfd 2659 */
ba0251fe
TG		 2660 mtd->erasesize = type->erasesize;
2661 mtd->writesize = type->pagesize;
4cbb9b80 2662 mtd->oobsize = mtd->writesize / 32;
ba0251fe 2663 busw = type->options & NAND_BUSWIDTH_16;
7aa65bfd 2664 }
1da177e4 2665
7aa65bfd 2666 /* Try to identify manufacturer */
9a909867 2667 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 2668 if (nand_manuf_ids[maf_idx].id == *maf_id)
2669 break;
2670 }
0ea4a755 2671
7aa65bfd
TG		 2672 /*
2673 * Check, if buswidth is correct. Hardware drivers should set
ace4dfee 2674 * chip correct !
7aa65bfd 2675 */
ace4dfee 2676 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
7aa65bfd
TG		 2677 printk(KERN_INFO "NAND device: Manufacturer ID:"
2678 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2679 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2680 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
ace4dfee 2681 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
7aa65bfd
TG		 2682 busw ? 16 : 8);
2683 return ERR_PTR(-EINVAL);
2684 }
61b03bd7 2685
7aa65bfd 2686 /* Calculate the address shift from the page size */
ace4dfee 2687 chip->page_shift = ffs(mtd->writesize) - 1;
7aa65bfd 2688 /* Convert chipsize to number of pages per chip -1. */
ace4dfee 2689 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 2690
ace4dfee 2691 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 2692 ffs(mtd->erasesize) - 1;
69423d99
AH		 2693 if (chip->chipsize & 0xffffffff)
2694 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2695 else
2696 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
1da177e4 2697
7aa65bfd 2698 /* Set the bad block position */
ace4dfee 2699 chip->badblockpos = mtd->writesize > 512 ?
7aa65bfd 2700 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
61b03bd7 2701
7aa65bfd 2702 /* Get chip options, preserve non chip based options */
ace4dfee 2703 chip->options &= ~NAND_CHIPOPTIONS_MSK;
ba0251fe 2704 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
7aa65bfd
TG		 2705
2706 /*
ace4dfee 2707 * Set chip as a default. Board drivers can override it, if necessary
7aa65bfd 2708 */
ace4dfee 2709 chip->options |= NAND_NO_AUTOINCR;
7aa65bfd 2710
ace4dfee 2711 /* Check if chip is a not a samsung device. Do not clear the
7aa65bfd
TG		 2712 * options for chips which are not having an extended id.
2713 */
ba0251fe 2714 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
ace4dfee 2715 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
7aa65bfd
TG		 2716
2717 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 2718 if (chip->options & NAND_4PAGE_ARRAY)
2719 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 2720 else
ace4dfee 2721 chip->erase_cmd = single_erase_cmd;
7aa65bfd
TG		 2722
2723 /* Do not replace user supplied command function ! */
ace4dfee
TG		 2724 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2725 chip->cmdfunc = nand_command_lp;
7aa65bfd
TG		 2726
2727 printk(KERN_INFO "NAND device: Manufacturer ID:"
2728 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2729 nand_manuf_ids[maf_idx].name, type->name);
2730
2731 return type;
2732}
2733
7aa65bfd 2734/**
3b85c321
DW		 2735 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2736 * @mtd: MTD device structure
2737 * @maxchips: Number of chips to scan for
7aa65bfd 2738 *
3b85c321
DW		 2739 * This is the first phase of the normal nand_scan() function. It
2740 * reads the flash ID and sets up MTD fields accordingly.
7aa65bfd 2741 *
3b85c321 2742 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 2743 */
3b85c321 2744int nand_scan_ident(struct mtd_info *mtd, int maxchips)
7aa65bfd
TG		 2745{
2746 int i, busw, nand_maf_id;
ace4dfee 2747 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 2748 struct nand_flash_dev *type;
2749
7aa65bfd 2750 /* Get buswidth to select the correct functions */
ace4dfee 2751 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 2752 /* Set the default functions */
ace4dfee 2753 nand_set_defaults(chip, busw);
7aa65bfd
TG		 2754
2755 /* Read the flash type */
ace4dfee 2756 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
7aa65bfd
TG		 2757
2758 if (IS_ERR(type)) {
e0c7d767 2759 printk(KERN_WARNING "No NAND device found!!!\n");
ace4dfee 2760 chip->select_chip(mtd, -1);
7aa65bfd 2761 return PTR_ERR(type);
1da177e4
LT		 2762 }
2763
7aa65bfd 2764 /* Check for a chip array */
e0c7d767 2765 for (i = 1; i < maxchips; i++) {
ace4dfee 2766 chip->select_chip(mtd, i);
ef89a880
KB		 2767 /* See comment in nand_get_flash_type for reset */
2768 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 2769 /* Send the command for reading device ID */
ace4dfee 2770 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 2771 /* Read manufacturer and device IDs */
ace4dfee
TG		 2772 if (nand_maf_id != chip->read_byte(mtd) ||
2773 type->id != chip->read_byte(mtd))
1da177e4
LT		 2774 break;
2775 }
2776 if (i > 1)
2777 printk(KERN_INFO "%d NAND chips detected\n", i);
61b03bd7 2778
1da177e4 2779 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 2780 chip->numchips = i;
2781 mtd->size = i * chip->chipsize;
7aa65bfd 2782
3b85c321
DW		 2783 return 0;
2784}
2785
2786
2787/**
2788 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2789 * @mtd: MTD device structure
3b85c321
DW		 2790 *
2791 * This is the second phase of the normal nand_scan() function. It
2792 * fills out all the uninitialized function pointers with the defaults
2793 * and scans for a bad block table if appropriate.
2794 */
2795int nand_scan_tail(struct mtd_info *mtd)
2796{
2797 int i;
2798 struct nand_chip *chip = mtd->priv;
2799
4bf63fcb
DW		 2800 if (!(chip->options & NAND_OWN_BUFFERS))
2801 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2802 if (!chip->buffers)
2803 return -ENOMEM;
2804
7dcdcbef 2805 /* Set the internal oob buffer location, just after the page data */
784f4d5e 2806 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 2807
7aa65bfd
TG		 2808 /*
2809 * If no default placement scheme is given, select an appropriate one
2810 */
5bd34c09 2811 if (!chip->ecc.layout) {
61b03bd7 2812 switch (mtd->oobsize) {
1da177e4 2813 case 8:
5bd34c09 2814 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 2815 break;
2816 case 16:
5bd34c09 2817 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 2818 break;
2819 case 64:
5bd34c09 2820 chip->ecc.layout = &nand_oob_64;
1da177e4 2821 break;
81ec5364
TG		 2822 case 128:
2823 chip->ecc.layout = &nand_oob_128;
2824 break;
1da177e4 2825 default:
7aa65bfd
TG		 2826 printk(KERN_WARNING "No oob scheme defined for "
2827 "oobsize %d\n", mtd->oobsize);
1da177e4
LT		 2828 BUG();
2829 }
2830 }
61b03bd7 2831
956e944c
DW		 2832 if (!chip->write_page)
2833 chip->write_page = nand_write_page;
2834
61b03bd7 2835 /*
7aa65bfd
TG		 2836 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2837 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 2838 */
956e944c 2839
ace4dfee 2840 switch (chip->ecc.mode) {
6e0cb135
SN		 2841 case NAND_ECC_HW_OOB_FIRST:
2842 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2843 if (!chip->ecc.calculate || !chip->ecc.correct ||
2844 !chip->ecc.hwctl) {
2845 printk(KERN_WARNING "No ECC functions supplied; "
2846 "Hardware ECC not possible\n");
2847 BUG();
2848 }
2849 if (!chip->ecc.read_page)
2850 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2851
6dfc6d25 2852 case NAND_ECC_HW:
f5bbdacc
TG		 2853 /* Use standard hwecc read page function ? */
2854 if (!chip->ecc.read_page)
2855 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 2856 if (!chip->ecc.write_page)
2857 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 2858 if (!chip->ecc.read_page_raw)
2859 chip->ecc.read_page_raw = nand_read_page_raw;
2860 if (!chip->ecc.write_page_raw)
2861 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 2862 if (!chip->ecc.read_oob)
2863 chip->ecc.read_oob = nand_read_oob_std;
2864 if (!chip->ecc.write_oob)
2865 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 2866
6dfc6d25 2867 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 2868 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2869 !chip->ecc.hwctl) &&
2870 (!chip->ecc.read_page ||
1c45f604 2871 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 2872 !chip->ecc.write_page ||
1c45f604 2873 chip->ecc.write_page == nand_write_page_hwecc)) {
6e0cb135 2874 printk(KERN_WARNING "No ECC functions supplied; "
6dfc6d25
TG		 2875 "Hardware ECC not possible\n");
2876 BUG();
2877 }
f75e5097 2878 /* Use standard syndrome read/write page function ? */
f5bbdacc
TG		 2879 if (!chip->ecc.read_page)
2880 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 2881 if (!chip->ecc.write_page)
2882 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 2883 if (!chip->ecc.read_page_raw)
2884 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2885 if (!chip->ecc.write_page_raw)
2886 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 2887 if (!chip->ecc.read_oob)
2888 chip->ecc.read_oob = nand_read_oob_syndrome;
2889 if (!chip->ecc.write_oob)
2890 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 2891
ace4dfee 2892 if (mtd->writesize >= chip->ecc.size)
6dfc6d25
TG		 2893 break;
2894 printk(KERN_WARNING "%d byte HW ECC not possible on "
2895 "%d byte page size, fallback to SW ECC\n",
ace4dfee
TG		 2896 chip->ecc.size, mtd->writesize);
2897 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 2898
6dfc6d25 2899 case NAND_ECC_SOFT:
ace4dfee
TG		 2900 chip->ecc.calculate = nand_calculate_ecc;
2901 chip->ecc.correct = nand_correct_data;
f5bbdacc 2902 chip->ecc.read_page = nand_read_page_swecc;
3d459559 2903 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 2904 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 2905 chip->ecc.read_page_raw = nand_read_page_raw;
2906 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 2907 chip->ecc.read_oob = nand_read_oob_std;
2908 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 2909 if (!chip->ecc.size)
2910 chip->ecc.size = 256;
ace4dfee 2911 chip->ecc.bytes = 3;
1da177e4 2912 break;
61b03bd7
TG		 2913
2914 case NAND_ECC_NONE:
7aa65bfd
TG		 2915 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2916 "This is not recommended !!\n");
8593fbc6
TG		 2917 chip->ecc.read_page = nand_read_page_raw;
2918 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 2919 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 2920 chip->ecc.read_page_raw = nand_read_page_raw;
2921 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 2922 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 2923 chip->ecc.size = mtd->writesize;
2924 chip->ecc.bytes = 0;
1da177e4 2925 break;
956e944c 2926
1da177e4 2927 default:
7aa65bfd 2928 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
ace4dfee 2929 chip->ecc.mode);
61b03bd7 2930 BUG();
1da177e4 2931 }
61b03bd7 2932
5bd34c09
TG		 2933 /*
2934 * The number of bytes available for a client to place data into
2935 * the out of band area
2936 */
2937 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 2938 for (i = 0; chip->ecc.layout->oobfree[i].length
2939 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 2940 chip->ecc.layout->oobavail +=
2941 chip->ecc.layout->oobfree[i].length;
1f92267c 2942 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 2943
7aa65bfd
TG		 2944 /*
2945 * Set the number of read / write steps for one page depending on ECC
2946 * mode
2947 */
ace4dfee
TG		 2948 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2949 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
6dfc6d25
TG		 2950 printk(KERN_WARNING "Invalid ecc parameters\n");
2951 BUG();
1da177e4 2952 }
f5bbdacc 2953 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 2954
29072b96
TG		 2955 /*
2956 * Allow subpage writes up to ecc.steps. Not possible for MLC
2957 * FLASH.
2958 */
2959 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2960 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2961 switch(chip->ecc.steps) {
2962 case 2:
2963 mtd->subpage_sft = 1;
2964 break;
2965 case 4:
2966 case 8:
81ec5364 2967 case 16:
29072b96
TG		 2968 mtd->subpage_sft = 2;
2969 break;
2970 }
2971 }
2972 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2973
04bbd0ea 2974 /* Initialize state */
ace4dfee 2975 chip->state = FL_READY;
1da177e4
LT		 2976
2977 /* De-select the device */
ace4dfee 2978 chip->select_chip(mtd, -1);
1da177e4
LT		 2979
2980 /* Invalidate the pagebuffer reference */
ace4dfee 2981 chip->pagebuf = -1;
1da177e4
LT		 2982
2983 /* Fill in remaining MTD driver data */
2984 mtd->type = MTD_NANDFLASH;
5fa43394 2985 mtd->flags = MTD_CAP_NANDFLASH;
1da177e4
LT		 2986 mtd->erase = nand_erase;
2987 mtd->point = NULL;
2988 mtd->unpoint = NULL;
2989 mtd->read = nand_read;
2990 mtd->write = nand_write;
2af7c653 2991 mtd->panic_write = panic_nand_write;
1da177e4
LT		 2992 mtd->read_oob = nand_read_oob;
2993 mtd->write_oob = nand_write_oob;
1da177e4
LT		 2994 mtd->sync = nand_sync;
2995 mtd->lock = NULL;
2996 mtd->unlock = NULL;
962034f4
VW		 2997 mtd->suspend = nand_suspend;
2998 mtd->resume = nand_resume;
1da177e4
LT		 2999 mtd->block_isbad = nand_block_isbad;
3000 mtd->block_markbad = nand_block_markbad;
3001
5bd34c09
TG		 3002 /* propagate ecc.layout to mtd_info */
3003 mtd->ecclayout = chip->ecc.layout;
1da177e4 3004
0040bf38 3005 /* Check, if we should skip the bad block table scan */
ace4dfee 3006 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3007 return 0;
1da177e4
LT		 3008
3009 /* Build bad block table */
ace4dfee 3010 return chip->scan_bbt(mtd);
1da177e4
LT		 3011}
3012
a6e6abd5 3013/* is_module_text_address() isn't exported, and it's mostly a pointless
3b85c321
DW		 3014 test if this is a module _anyway_ -- they'd have to try _really_ hard
3015 to call us from in-kernel code if the core NAND support is modular. */
3016#ifdef MODULE
3017#define caller_is_module() (1)
3018#else
3019#define caller_is_module() \
a6e6abd5 3020 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3021#endif
3022
3023/**
3024 * nand_scan - [NAND Interface] Scan for the NAND device
3025 * @mtd: MTD device structure
3026 * @maxchips: Number of chips to scan for
3027 *
3028 * This fills out all the uninitialized function pointers
3029 * with the defaults.
3030 * The flash ID is read and the mtd/chip structures are
3031 * filled with the appropriate values.
3032 * The mtd->owner field must be set to the module of the caller
3033 *
3034 */
3035int nand_scan(struct mtd_info *mtd, int maxchips)
3036{
3037 int ret;
3038
3039 /* Many callers got this wrong, so check for it for a while... */
3040 if (!mtd->owner && caller_is_module()) {
20d8e248 3041 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3042 __func__);
3b85c321
DW		 3043 BUG();
3044 }
3045
3046 ret = nand_scan_ident(mtd, maxchips);
3047 if (!ret)
3048 ret = nand_scan_tail(mtd);
3049 return ret;
3050}
3051
1da177e4 3052/**
61b03bd7 3053 * nand_release - [NAND Interface] Free resources held by the NAND device
1da177e4
LT		 3054 * @mtd: MTD device structure
3055*/
e0c7d767 3056void nand_release(struct mtd_info *mtd)
1da177e4 3057{
ace4dfee 3058 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 3059
3060#ifdef CONFIG_MTD_PARTITIONS
3061 /* Deregister partitions */
e0c7d767 3062 del_mtd_partitions(mtd);
1da177e4
LT		 3063#endif
3064 /* Deregister the device */
e0c7d767 3065 del_mtd_device(mtd);
1da177e4 3066
fa671646 3067 /* Free bad block table memory */
ace4dfee 3068 kfree(chip->bbt);
4bf63fcb
DW		 3069 if (!(chip->options & NAND_OWN_BUFFERS))
3070 kfree(chip->buffers);
1da177e4
LT		 3071}
3072
e0c7d767 3073EXPORT_SYMBOL_GPL(nand_scan);
3b85c321
DW		 3074EXPORT_SYMBOL_GPL(nand_scan_ident);
3075EXPORT_SYMBOL_GPL(nand_scan_tail);
e0c7d767 3076EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3077
3078static int __init nand_base_init(void)
3079{
3080 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3081 return 0;
3082}
3083
3084static void __exit nand_base_exit(void)
3085{
3086 led_trigger_unregister_simple(nand_led_trigger);
3087}
3088
3089module_init(nand_base_init);
3090module_exit(nand_base_exit);
3091
e0c7d767
DW		 3092MODULE_LICENSE("GPL");
3093MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3094MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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