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mtd: gpmi-nand: utilize oob_requested parameter
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 24 * if we have HW ECC support.
1da177e4
LT		 25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4 50#include <linux/mtd/partitions.h>
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
ace4dfee 96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 97 int new_state);
1da177e4 98
8593fbc6
TG		 99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
d470a97c 102/*
8e87d782 103 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
6fe5a6ac
VS		 108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 116 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 122 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 123 ret = -EINVAL;
124 }
125
6fe5a6ac
VS		 126 return ret;
127}
128
1da177e4
LT		 129/**
130 * nand_release_device - [GENERIC] release chip
8b6e50c9 131 * @mtd: MTD device structure
61b03bd7 132 *
8b6e50c9 133 * Deselect, release chip lock and wake up anyone waiting on the device.
1da177e4 134 */
e0c7d767 135static void nand_release_device(struct mtd_info *mtd)
1da177e4 136{
ace4dfee 137 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 138
139 /* De-select the NAND device */
ace4dfee 140 chip->select_chip(mtd, -1);
0dfc6246 141
a36ed299 142 /* Release the controller and the chip */
ace4dfee
TG		 143 spin_lock(&chip->controller->lock);
144 chip->controller->active = NULL;
145 chip->state = FL_READY;
146 wake_up(&chip->controller->wq);
147 spin_unlock(&chip->controller->lock);
1da177e4
LT		 148}
149
150/**
151 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 152 * @mtd: MTD device structure
1da177e4 153 *
7854d3f7 154 * Default read function for 8bit buswidth
1da177e4 155 */
58dd8f2b 156static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 157{
ace4dfee
TG		 158 struct nand_chip *chip = mtd->priv;
159 return readb(chip->IO_ADDR_R);
1da177e4
LT		 160}
161
1da177e4
LT		 162/**
163 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
7854d3f7 164 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 165 * @mtd: MTD device structure
1da177e4 166 *
7854d3f7
BN		 167 * Default read function for 16bit buswidth with endianness conversion.
168 *
1da177e4 169 */
58dd8f2b 170static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 171{
ace4dfee
TG		 172 struct nand_chip *chip = mtd->priv;
173 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 174}
175
1da177e4
LT		 176/**
177 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 178 * @mtd: MTD device structure
1da177e4 179 *
7854d3f7 180 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 181 */
182static u16 nand_read_word(struct mtd_info *mtd)
183{
ace4dfee
TG		 184 struct nand_chip *chip = mtd->priv;
185 return readw(chip->IO_ADDR_R);
1da177e4
LT		 186}
187
1da177e4
LT		 188/**
189 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 190 * @mtd: MTD device structure
191 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 192 *
193 * Default select function for 1 chip devices.
194 */
ace4dfee 195static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 196{
ace4dfee
TG		 197 struct nand_chip *chip = mtd->priv;
198
199 switch (chipnr) {
1da177e4 200 case -1:
ace4dfee 201 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 202 break;
203 case 0:
1da177e4
LT		 204 break;
205
206 default:
207 BUG();
208 }
209}
210
211/**
212 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 213 * @mtd: MTD device structure
214 * @buf: data buffer
215 * @len: number of bytes to write
1da177e4 216 *
7854d3f7 217 * Default write function for 8bit buswidth.
1da177e4 218 */
58dd8f2b 219static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 220{
221 int i;
ace4dfee 222 struct nand_chip *chip = mtd->priv;
1da177e4 223
e0c7d767 224 for (i = 0; i < len; i++)
ace4dfee 225 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 226}
227
228/**
61b03bd7 229 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
1da177e4 233 *
7854d3f7 234 * Default read function for 8bit buswidth.
1da177e4 235 */
58dd8f2b 236static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 237{
238 int i;
ace4dfee 239 struct nand_chip *chip = mtd->priv;
1da177e4 240
e0c7d767 241 for (i = 0; i < len; i++)
ace4dfee 242 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 243}
244
245/**
61b03bd7 246 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 247 * @mtd: MTD device structure
248 * @buf: buffer containing the data to compare
249 * @len: number of bytes to compare
1da177e4 250 *
7854d3f7 251 * Default verify function for 8bit buswidth.
1da177e4 252 */
58dd8f2b 253static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 254{
255 int i;
ace4dfee 256 struct nand_chip *chip = mtd->priv;
1da177e4 257
e0c7d767 258 for (i = 0; i < len; i++)
ace4dfee 259 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 260 return -EFAULT;
1da177e4
LT		 261 return 0;
262}
263
264/**
265 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 266 * @mtd: MTD device structure
267 * @buf: data buffer
268 * @len: number of bytes to write
1da177e4 269 *
7854d3f7 270 * Default write function for 16bit buswidth.
1da177e4 271 */
58dd8f2b 272static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 273{
274 int i;
ace4dfee 275 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 276 u16 *p = (u16 *) buf;
277 len >>= 1;
61b03bd7 278
e0c7d767 279 for (i = 0; i < len; i++)
ace4dfee 280 writew(p[i], chip->IO_ADDR_W);
61b03bd7 281
1da177e4
LT		 282}
283
284/**
61b03bd7 285 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 286 * @mtd: MTD device structure
287 * @buf: buffer to store date
288 * @len: number of bytes to read
1da177e4 289 *
7854d3f7 290 * Default read function for 16bit buswidth.
1da177e4 291 */
58dd8f2b 292static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 293{
294 int i;
ace4dfee 295 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 296 u16 *p = (u16 *) buf;
297 len >>= 1;
298
e0c7d767 299 for (i = 0; i < len; i++)
ace4dfee 300 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 301}
302
303/**
61b03bd7 304 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 305 * @mtd: MTD device structure
306 * @buf: buffer containing the data to compare
307 * @len: number of bytes to compare
1da177e4 308 *
7854d3f7 309 * Default verify function for 16bit buswidth.
1da177e4 310 */
58dd8f2b 311static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 312{
313 int i;
ace4dfee 314 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 315 u16 *p = (u16 *) buf;
316 len >>= 1;
317
e0c7d767 318 for (i = 0; i < len; i++)
ace4dfee 319 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 320 return -EFAULT;
321
322 return 0;
323}
324
325/**
326 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 327 * @mtd: MTD device structure
328 * @ofs: offset from device start
329 * @getchip: 0, if the chip is already selected
1da177e4 330 *
61b03bd7 331 * Check, if the block is bad.
1da177e4
LT		 332 */
333static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
334{
cdbec050 335 int page, chipnr, res = 0, i = 0;
ace4dfee 336 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 337 u16 bad;
338
5fb1549d 339 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 340 ofs += mtd->erasesize - mtd->writesize;
341
1a12f46a
TK		 342 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
343
1da177e4 344 if (getchip) {
ace4dfee 345 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 346
ace4dfee 347 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 348
349 /* Select the NAND device */
ace4dfee 350 chip->select_chip(mtd, chipnr);
1a12f46a 351 }
1da177e4 352
cdbec050
BN		 353 do {
354 if (chip->options & NAND_BUSWIDTH_16) {
355 chip->cmdfunc(mtd, NAND_CMD_READOOB,
356 chip->badblockpos & 0xFE, page);
357 bad = cpu_to_le16(chip->read_word(mtd));
358 if (chip->badblockpos & 0x1)
359 bad >>= 8;
360 else
361 bad &= 0xFF;
362 } else {
363 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
364 page);
365 bad = chip->read_byte(mtd);
366 }
367
368 if (likely(chip->badblockbits == 8))
369 res = bad != 0xFF;
e0b58d0a 370 else
cdbec050
BN		 371 res = hweight8(bad) < chip->badblockbits;
372 ofs += mtd->writesize;
373 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
374 i++;
375 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 376
ace4dfee 377 if (getchip)
1da177e4 378 nand_release_device(mtd);
61b03bd7 379
1da177e4
LT		 380 return res;
381}
382
383/**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 385 * @mtd: MTD device structure
386 * @ofs: offset from device start
1da177e4 387 *
8b6e50c9 388 * This is the default implementation, which can be overridden by a hardware
e2414f4c
BN		 389 * specific driver. We try operations in the following order, according to our
390 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
391 * (1) erase the affected block, to allow OOB marker to be written cleanly
392 * (2) update in-memory BBT
393 * (3) write bad block marker to OOB area of affected block
394 * (4) update flash-based BBT
395 * Note that we retain the first error encountered in (3) or (4), finish the
396 * procedures, and dump the error in the end.
1da177e4
LT		 397*/
398static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
399{
ace4dfee 400 struct nand_chip *chip = mtd->priv;
58dd8f2b 401 uint8_t buf[2] = { 0, 0 };
e2414f4c
BN		 402 int block, res, ret = 0, i = 0;
403 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
61b03bd7 404
e2414f4c 405 if (write_oob) {
00918429
BN		 406 struct erase_info einfo;
407
408 /* Attempt erase before marking OOB */
409 memset(&einfo, 0, sizeof(einfo));
410 einfo.mtd = mtd;
411 einfo.addr = ofs;
412 einfo.len = 1 << chip->phys_erase_shift;
413 nand_erase_nand(mtd, &einfo, 0);
414 }
415
1da177e4 416 /* Get block number */
4226b510 417 block = (int)(ofs >> chip->bbt_erase_shift);
e2414f4c 418 /* Mark block bad in memory-based BBT */
ace4dfee
TG		 419 if (chip->bbt)
420 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 421
e2414f4c
BN		 422 /* Write bad block marker to OOB */
423 if (write_oob) {
4a89ff88 424 struct mtd_oob_ops ops;
df698621 425 loff_t wr_ofs = ofs;
4a89ff88 426
c0b8ba7b 427 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 428
4a89ff88
BN		 429 ops.datbuf = NULL;
430 ops.oobbuf = buf;
85443319
BN		 431 ops.ooboffs = chip->badblockpos;
432 if (chip->options & NAND_BUSWIDTH_16) {
433 ops.ooboffs &= ~0x01;
434 ops.len = ops.ooblen = 2;
435 } else {
436 ops.len = ops.ooblen = 1;
437 }
23b1a99b 438 ops.mode = MTD_OPS_PLACE_OOB;
df698621 439
e2414f4c 440 /* Write to first/last page(s) if necessary */
df698621
BN		 441 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
442 wr_ofs += mtd->erasesize - mtd->writesize;
02ed70bb 443 do {
e2414f4c
BN		 444 res = nand_do_write_oob(mtd, wr_ofs, &ops);
445 if (!ret)
446 ret = res;
02ed70bb 447
02ed70bb 448 i++;
df698621 449 wr_ofs += mtd->writesize;
e2414f4c 450 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
02ed70bb 451
c0b8ba7b 452 nand_release_device(mtd);
f1a28c02 453 }
e2414f4c
BN		 454
455 /* Update flash-based bad block table */
456 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
457 res = nand_update_bbt(mtd, ofs);
458 if (!ret)
459 ret = res;
460 }
461
f1a28c02
TG		 462 if (!ret)
463 mtd->ecc_stats.badblocks++;
c0b8ba7b 464
f1a28c02 465 return ret;
1da177e4
LT		 466}
467
61b03bd7 468/**
1da177e4 469 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 470 * @mtd: MTD device structure
1da177e4 471 *
8b6e50c9
BN		 472 * Check, if the device is write protected. The function expects, that the
473 * device is already selected.
1da177e4 474 */
e0c7d767 475static int nand_check_wp(struct mtd_info *mtd)
1da177e4 476{
ace4dfee 477 struct nand_chip *chip = mtd->priv;
93edbad6 478
8b6e50c9 479 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 480 if (chip->options & NAND_BROKEN_XD)
481 return 0;
482
1da177e4 483 /* Check the WP bit */
ace4dfee
TG		 484 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
485 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 486}
487
488/**
489 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 490 * @mtd: MTD device structure
491 * @ofs: offset from device start
492 * @getchip: 0, if the chip is already selected
493 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 494 *
495 * Check, if the block is bad. Either by reading the bad block table or
496 * calling of the scan function.
497 */
2c0a2bed
TG		 498static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
499 int allowbbt)
1da177e4 500{
ace4dfee 501 struct nand_chip *chip = mtd->priv;
61b03bd7 502
ace4dfee
TG		 503 if (!chip->bbt)
504 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 505
1da177e4 506 /* Return info from the table */
e0c7d767 507 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 508}
509
2af7c653
SK		 510/**
511 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 512 * @mtd: MTD device structure
513 * @timeo: Timeout
2af7c653
SK		 514 *
515 * Helper function for nand_wait_ready used when needing to wait in interrupt
516 * context.
517 */
518static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
519{
520 struct nand_chip *chip = mtd->priv;
521 int i;
522
523 /* Wait for the device to get ready */
524 for (i = 0; i < timeo; i++) {
525 if (chip->dev_ready(mtd))
526 break;
527 touch_softlockup_watchdog();
528 mdelay(1);
529 }
530}
531
7854d3f7 532/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 533void nand_wait_ready(struct mtd_info *mtd)
3b88775c 534{
ace4dfee 535 struct nand_chip *chip = mtd->priv;
e0c7d767 536 unsigned long timeo = jiffies + 2;
3b88775c 537
2af7c653
SK		 538 /* 400ms timeout */
539 if (in_interrupt() || oops_in_progress)
540 return panic_nand_wait_ready(mtd, 400);
541
8fe833c1 542 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 543 /* Wait until command is processed or timeout occurs */
3b88775c 544 do {
ace4dfee 545 if (chip->dev_ready(mtd))
8fe833c1 546 break;
8446f1d3 547 touch_softlockup_watchdog();
61b03bd7 548 } while (time_before(jiffies, timeo));
8fe833c1 549 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 550}
4b648b02 551EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 552
1da177e4
LT		 553/**
554 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 555 * @mtd: MTD device structure
556 * @command: the command to be sent
557 * @column: the column address for this command, -1 if none
558 * @page_addr: the page address for this command, -1 if none
1da177e4 559 *
8b6e50c9
BN		 560 * Send command to NAND device. This function is used for small page devices
561 * (256/512 Bytes per page).
1da177e4 562 */
7abd3ef9
TG		 563static void nand_command(struct mtd_info *mtd, unsigned int command,
564 int column, int page_addr)
1da177e4 565{
ace4dfee 566 register struct nand_chip *chip = mtd->priv;
7abd3ef9 567 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 568
8b6e50c9 569 /* Write out the command to the device */
1da177e4
LT		 570 if (command == NAND_CMD_SEQIN) {
571 int readcmd;
572
28318776 573 if (column >= mtd->writesize) {
1da177e4 574 /* OOB area */
28318776 575 column -= mtd->writesize;
1da177e4
LT		 576 readcmd = NAND_CMD_READOOB;
577 } else if (column < 256) {
578 /* First 256 bytes --> READ0 */
579 readcmd = NAND_CMD_READ0;
580 } else {
581 column -= 256;
582 readcmd = NAND_CMD_READ1;
583 }
ace4dfee 584 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 585 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 586 }
ace4dfee 587 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 588
8b6e50c9 589 /* Address cycle, when necessary */
7abd3ef9
TG		 590 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
591 /* Serially input address */
592 if (column != -1) {
593 /* Adjust columns for 16 bit buswidth */
ace4dfee 594 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 595 column >>= 1;
ace4dfee 596 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 597 ctrl &= ~NAND_CTRL_CHANGE;
598 }
599 if (page_addr != -1) {
ace4dfee 600 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 601 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 602 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 603 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 604 if (chip->chipsize > (32 << 20))
605 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 606 }
ace4dfee 607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 608
609 /*
8b6e50c9
BN		 610 * Program and erase have their own busy handlers status and sequential
611 * in needs no delay
e0c7d767 612 */
1da177e4 613 switch (command) {
61b03bd7 614
1da177e4
LT		 615 case NAND_CMD_PAGEPROG:
616 case NAND_CMD_ERASE1:
617 case NAND_CMD_ERASE2:
618 case NAND_CMD_SEQIN:
619 case NAND_CMD_STATUS:
620 return;
621
622 case NAND_CMD_RESET:
ace4dfee 623 if (chip->dev_ready)
1da177e4 624 break;
ace4dfee
TG		 625 udelay(chip->chip_delay);
626 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 627 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 628 chip->cmd_ctrl(mtd,
629 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 630 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
631 ;
1da177e4
LT		 632 return;
633
e0c7d767 634 /* This applies to read commands */
1da177e4 635 default:
61b03bd7 636 /*
1da177e4
LT		 637 * If we don't have access to the busy pin, we apply the given
638 * command delay
e0c7d767 639 */
ace4dfee
TG		 640 if (!chip->dev_ready) {
641 udelay(chip->chip_delay);
1da177e4 642 return;
61b03bd7 643 }
1da177e4 644 }
8b6e50c9
BN		 645 /*
646 * Apply this short delay always to ensure that we do wait tWB in
647 * any case on any machine.
648 */
e0c7d767 649 ndelay(100);
3b88775c
TG		 650
651 nand_wait_ready(mtd);
1da177e4
LT		 652}
653
654/**
655 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 656 * @mtd: MTD device structure
657 * @command: the command to be sent
658 * @column: the column address for this command, -1 if none
659 * @page_addr: the page address for this command, -1 if none
1da177e4 660 *
7abd3ef9 661 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 662 * devices. We don't have the separate regions as we have in the small page
663 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 664 */
7abd3ef9
TG		 665static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
666 int column, int page_addr)
1da177e4 667{
ace4dfee 668 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 669
670 /* Emulate NAND_CMD_READOOB */
671 if (command == NAND_CMD_READOOB) {
28318776 672 column += mtd->writesize;
1da177e4
LT		 673 command = NAND_CMD_READ0;
674 }
61b03bd7 675
7abd3ef9 676 /* Command latch cycle */
ace4dfee 677 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 678 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 679
680 if (column != -1 || page_addr != -1) {
7abd3ef9 681 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 682
683 /* Serially input address */
684 if (column != -1) {
685 /* Adjust columns for 16 bit buswidth */
ace4dfee 686 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 687 column >>= 1;
ace4dfee 688 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 689 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 690 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 691 }
1da177e4 692 if (page_addr != -1) {
ace4dfee
TG		 693 chip->cmd_ctrl(mtd, page_addr, ctrl);
694 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 695 NAND_NCE | NAND_ALE);
1da177e4 696 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 697 if (chip->chipsize > (128 << 20))
698 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 699 NAND_NCE | NAND_ALE);
1da177e4 700 }
1da177e4 701 }
ace4dfee 702 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 703
704 /*
8b6e50c9
BN		 705 * Program and erase have their own busy handlers status, sequential
706 * in, and deplete1 need no delay.
30f464b7 707 */
1da177e4 708 switch (command) {
61b03bd7 709
1da177e4
LT		 710 case NAND_CMD_CACHEDPROG:
711 case NAND_CMD_PAGEPROG:
712 case NAND_CMD_ERASE1:
713 case NAND_CMD_ERASE2:
714 case NAND_CMD_SEQIN:
7bc3312b 715 case NAND_CMD_RNDIN:
1da177e4 716 case NAND_CMD_STATUS:
30f464b7 717 case NAND_CMD_DEPLETE1:
1da177e4
LT		 718 return;
719
30f464b7
DM		 720 case NAND_CMD_STATUS_ERROR:
721 case NAND_CMD_STATUS_ERROR0:
722 case NAND_CMD_STATUS_ERROR1:
723 case NAND_CMD_STATUS_ERROR2:
724 case NAND_CMD_STATUS_ERROR3:
8b6e50c9 725 /* Read error status commands require only a short delay */
ace4dfee 726 udelay(chip->chip_delay);
30f464b7 727 return;
1da177e4
LT		 728
729 case NAND_CMD_RESET:
ace4dfee 730 if (chip->dev_ready)
1da177e4 731 break;
ace4dfee 732 udelay(chip->chip_delay);
12efdde3
TG		 733 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
735 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
736 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 737 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
738 ;
1da177e4
LT		 739 return;
740
7bc3312b
TG		 741 case NAND_CMD_RNDOUT:
742 /* No ready / busy check necessary */
743 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
744 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
745 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
746 NAND_NCE | NAND_CTRL_CHANGE);
747 return;
748
1da177e4 749 case NAND_CMD_READ0:
12efdde3
TG		 750 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
751 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
752 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
753 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 754
e0c7d767 755 /* This applies to read commands */
1da177e4 756 default:
61b03bd7 757 /*
1da177e4 758 * If we don't have access to the busy pin, we apply the given
8b6e50c9 759 * command delay.
e0c7d767 760 */
ace4dfee
TG		 761 if (!chip->dev_ready) {
762 udelay(chip->chip_delay);
1da177e4 763 return;
61b03bd7 764 }
1da177e4 765 }
3b88775c 766
8b6e50c9
BN		 767 /*
768 * Apply this short delay always to ensure that we do wait tWB in
769 * any case on any machine.
770 */
e0c7d767 771 ndelay(100);
3b88775c
TG		 772
773 nand_wait_ready(mtd);
1da177e4
LT		 774}
775
2af7c653
SK		 776/**
777 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 778 * @chip: the nand chip descriptor
779 * @mtd: MTD device structure
780 * @new_state: the state which is requested
2af7c653
SK		 781 *
782 * Used when in panic, no locks are taken.
783 */
784static void panic_nand_get_device(struct nand_chip *chip,
785 struct mtd_info *mtd, int new_state)
786{
7854d3f7 787 /* Hardware controller shared among independent devices */
2af7c653
SK		 788 chip->controller->active = chip;
789 chip->state = new_state;
790}
791
1da177e4
LT		 792/**
793 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 794 * @chip: the nand chip descriptor
795 * @mtd: MTD device structure
796 * @new_state: the state which is requested
1da177e4
LT		 797 *
798 * Get the device and lock it for exclusive access
799 */
2c0a2bed 800static int
ace4dfee 801nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 802{
ace4dfee
TG		 803 spinlock_t *lock = &chip->controller->lock;
804 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 805 DECLARE_WAITQUEUE(wait, current);
7351d3a5 806retry:
0dfc6246
TG		 807 spin_lock(lock);
808
b8b3ee9a 809 /* Hardware controller shared among independent devices */
ace4dfee
TG		 810 if (!chip->controller->active)
811 chip->controller->active = chip;
a36ed299 812
ace4dfee
TG		 813 if (chip->controller->active == chip && chip->state == FL_READY) {
814 chip->state = new_state;
0dfc6246 815 spin_unlock(lock);
962034f4
VW		 816 return 0;
817 }
818 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 819 if (chip->controller->active->state == FL_PM_SUSPENDED) {
820 chip->state = FL_PM_SUSPENDED;
821 spin_unlock(lock);
822 return 0;
6b0d9a84 823 }
0dfc6246
TG		 824 }
825 set_current_state(TASK_UNINTERRUPTIBLE);
826 add_wait_queue(wq, &wait);
827 spin_unlock(lock);
828 schedule();
829 remove_wait_queue(wq, &wait);
1da177e4
LT		 830 goto retry;
831}
832
2af7c653 833/**
8b6e50c9
BN		 834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
837 * @timeo: timeout
2af7c653
SK		 838 *
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
b595076a 841 * an oops through mtdoops.
2af7c653
SK		 842 */
843static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
844 unsigned long timeo)
845{
846 int i;
847 for (i = 0; i < timeo; i++) {
848 if (chip->dev_ready) {
849 if (chip->dev_ready(mtd))
850 break;
851 } else {
852 if (chip->read_byte(mtd) & NAND_STATUS_READY)
853 break;
854 }
855 mdelay(1);
f8ac0414 856 }
2af7c653
SK		 857}
858
1da177e4 859/**
8b6e50c9
BN		 860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
1da177e4 863 *
8b6e50c9
BN		 864 * Wait for command done. This applies to erase and program only. Erase can
865 * take up to 400ms and program up to 20ms according to general NAND and
866 * SmartMedia specs.
844d3b42 867 */
7bc3312b 868static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 869{
870
e0c7d767 871 unsigned long timeo = jiffies;
7bc3312b 872 int status, state = chip->state;
61b03bd7 873
1da177e4 874 if (state == FL_ERASING)
e0c7d767 875 timeo += (HZ * 400) / 1000;
1da177e4 876 else
e0c7d767 877 timeo += (HZ * 20) / 1000;
1da177e4 878
8fe833c1
RP		 879 led_trigger_event(nand_led_trigger, LED_FULL);
880
8b6e50c9
BN		 881 /*
882 * Apply this short delay always to ensure that we do wait tWB in any
883 * case on any machine.
884 */
e0c7d767 885 ndelay(100);
1da177e4 886
ace4dfee
TG		 887 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
888 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 889 else
ace4dfee 890 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 891
2af7c653
SK		 892 if (in_interrupt() || oops_in_progress)
893 panic_nand_wait(mtd, chip, timeo);
894 else {
895 while (time_before(jiffies, timeo)) {
896 if (chip->dev_ready) {
897 if (chip->dev_ready(mtd))
898 break;
899 } else {
900 if (chip->read_byte(mtd) & NAND_STATUS_READY)
901 break;
902 }
903 cond_resched();
1da177e4 904 }
1da177e4 905 }
8fe833c1
RP		 906 led_trigger_event(nand_led_trigger, LED_OFF);
907
ace4dfee 908 status = (int)chip->read_byte(mtd);
1da177e4
LT		 909 return status;
910}
911
7d70f334 912/**
b6d676db 913 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 914 * @mtd: mtd info
915 * @ofs: offset to start unlock from
916 * @len: length to unlock
8b6e50c9
BN		 917 * @invert: when = 0, unlock the range of blocks within the lower and
918 * upper boundary address
919 * when = 1, unlock the range of blocks outside the boundaries
920 * of the lower and upper boundary address
7d70f334 921 *
8b6e50c9 922 * Returs unlock status.
7d70f334
VS		 923 */
924static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
925 uint64_t len, int invert)
926{
927 int ret = 0;
928 int status, page;
929 struct nand_chip *chip = mtd->priv;
930
931 /* Submit address of first page to unlock */
932 page = ofs >> chip->page_shift;
933 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
934
935 /* Submit address of last page to unlock */
936 page = (ofs + len) >> chip->page_shift;
937 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
938 (page | invert) & chip->pagemask);
939
940 /* Call wait ready function */
941 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 942 /* See if device thinks it succeeded */
943 if (status & 0x01) {
289c0522 944 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 945 __func__, status);
946 ret = -EIO;
947 }
948
949 return ret;
950}
951
952/**
b6d676db 953 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 954 * @mtd: mtd info
955 * @ofs: offset to start unlock from
956 * @len: length to unlock
7d70f334 957 *
8b6e50c9 958 * Returns unlock status.
7d70f334
VS		 959 */
960int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
961{
962 int ret = 0;
963 int chipnr;
964 struct nand_chip *chip = mtd->priv;
965
289c0522 966 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 967 __func__, (unsigned long long)ofs, len);
968
969 if (check_offs_len(mtd, ofs, len))
970 ret = -EINVAL;
971
972 /* Align to last block address if size addresses end of the device */
973 if (ofs + len == mtd->size)
974 len -= mtd->erasesize;
975
976 nand_get_device(chip, mtd, FL_UNLOCKING);
977
978 /* Shift to get chip number */
979 chipnr = ofs >> chip->chip_shift;
980
981 chip->select_chip(mtd, chipnr);
982
983 /* Check, if it is write protected */
984 if (nand_check_wp(mtd)) {
289c0522 985 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 986 __func__);
987 ret = -EIO;
988 goto out;
989 }
990
991 ret = __nand_unlock(mtd, ofs, len, 0);
992
993out:
7d70f334
VS		 994 nand_release_device(mtd);
995
996 return ret;
997}
7351d3a5 998EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 999
1000/**
b6d676db 1001 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 1002 * @mtd: mtd info
1003 * @ofs: offset to start unlock from
1004 * @len: length to unlock
7d70f334 1005 *
8b6e50c9
BN		 1006 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1007 * have this feature, but it allows only to lock all blocks, not for specified
1008 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1009 * now.
7d70f334 1010 *
8b6e50c9 1011 * Returns lock status.
7d70f334
VS		 1012 */
1013int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1014{
1015 int ret = 0;
1016 int chipnr, status, page;
1017 struct nand_chip *chip = mtd->priv;
1018
289c0522 1019 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1020 __func__, (unsigned long long)ofs, len);
1021
1022 if (check_offs_len(mtd, ofs, len))
1023 ret = -EINVAL;
1024
1025 nand_get_device(chip, mtd, FL_LOCKING);
1026
1027 /* Shift to get chip number */
1028 chipnr = ofs >> chip->chip_shift;
1029
1030 chip->select_chip(mtd, chipnr);
1031
1032 /* Check, if it is write protected */
1033 if (nand_check_wp(mtd)) {
289c0522 1034 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1035 __func__);
1036 status = MTD_ERASE_FAILED;
1037 ret = -EIO;
1038 goto out;
1039 }
1040
1041 /* Submit address of first page to lock */
1042 page = ofs >> chip->page_shift;
1043 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1044
1045 /* Call wait ready function */
1046 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 1047 /* See if device thinks it succeeded */
1048 if (status & 0x01) {
289c0522 1049 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1050 __func__, status);
1051 ret = -EIO;
1052 goto out;
1053 }
1054
1055 ret = __nand_unlock(mtd, ofs, len, 0x1);
1056
1057out:
7d70f334
VS		 1058 nand_release_device(mtd);
1059
1060 return ret;
1061}
7351d3a5 1062EXPORT_SYMBOL(nand_lock);
7d70f334 1063
8593fbc6 1064/**
7854d3f7 1065 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1fbb938d 1069 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1070 * @page: page number to read
52ff49df 1071 *
7854d3f7 1072 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1073 */
1074static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1075 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1076{
1077 chip->read_buf(mtd, buf, mtd->writesize);
1078 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1079 return 0;
1080}
1081
52ff49df 1082/**
7854d3f7 1083 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1084 * @mtd: mtd info structure
1085 * @chip: nand chip info structure
1086 * @buf: buffer to store read data
1fbb938d 1087 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1088 * @page: page number to read
52ff49df
DB		 1089 *
1090 * We need a special oob layout and handling even when OOB isn't used.
1091 */
7351d3a5 1092static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1093 struct nand_chip *chip, uint8_t *buf,
1094 int oob_required, int page)
52ff49df
DB		 1095{
1096 int eccsize = chip->ecc.size;
1097 int eccbytes = chip->ecc.bytes;
1098 uint8_t *oob = chip->oob_poi;
1099 int steps, size;
1100
1101 for (steps = chip->ecc.steps; steps > 0; steps--) {
1102 chip->read_buf(mtd, buf, eccsize);
1103 buf += eccsize;
1104
1105 if (chip->ecc.prepad) {
1106 chip->read_buf(mtd, oob, chip->ecc.prepad);
1107 oob += chip->ecc.prepad;
1108 }
1109
1110 chip->read_buf(mtd, oob, eccbytes);
1111 oob += eccbytes;
1112
1113 if (chip->ecc.postpad) {
1114 chip->read_buf(mtd, oob, chip->ecc.postpad);
1115 oob += chip->ecc.postpad;
1116 }
1117 }
1118
1119 size = mtd->oobsize - (oob - chip->oob_poi);
1120 if (size)
1121 chip->read_buf(mtd, oob, size);
1122
1123 return 0;
1124}
1125
1da177e4 1126/**
7854d3f7 1127 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1128 * @mtd: mtd info structure
1129 * @chip: nand chip info structure
1130 * @buf: buffer to store read data
1fbb938d 1131 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1132 * @page: page number to read
068e3c0a 1133 */
f5bbdacc 1134static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1135 uint8_t *buf, int oob_required, int page)
1da177e4 1136{
f5bbdacc
TG		 1137 int i, eccsize = chip->ecc.size;
1138 int eccbytes = chip->ecc.bytes;
1139 int eccsteps = chip->ecc.steps;
1140 uint8_t *p = buf;
4bf63fcb
DW		 1141 uint8_t *ecc_calc = chip->buffers->ecccalc;
1142 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1143 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1144 unsigned int max_bitflips = 0;
f5bbdacc 1145
1fbb938d 1146 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1147
1148 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1149 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1150
1151 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1152 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1153
1154 eccsteps = chip->ecc.steps;
1155 p = buf;
1156
1157 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1158 int stat;
1159
1160 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1161 if (stat < 0) {
f5bbdacc 1162 mtd->ecc_stats.failed++;
3f91e94f 1163 } else {
f5bbdacc 1164 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1165 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1166 }
f5bbdacc 1167 }
3f91e94f 1168 return max_bitflips;
22c60f5f 1169}
1da177e4 1170
3d459559 1171/**
7854d3f7 1172 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
8b6e50c9
BN		 1173 * @mtd: mtd info structure
1174 * @chip: nand chip info structure
1175 * @data_offs: offset of requested data within the page
1176 * @readlen: data length
1177 * @bufpoi: buffer to store read data
3d459559 1178 */
7351d3a5
FF		 1179static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1180 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1181{
1182 int start_step, end_step, num_steps;
1183 uint32_t *eccpos = chip->ecc.layout->eccpos;
1184 uint8_t *p;
1185 int data_col_addr, i, gaps = 0;
1186 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1187 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1188 int index = 0;
3f91e94f 1189 unsigned int max_bitflips = 0;
3d459559 1190
7854d3f7 1191 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1192 start_step = data_offs / chip->ecc.size;
1193 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1194 num_steps = end_step - start_step + 1;
1195
8b6e50c9 1196 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1197 datafrag_len = num_steps * chip->ecc.size;
1198 eccfrag_len = num_steps * chip->ecc.bytes;
1199
1200 data_col_addr = start_step * chip->ecc.size;
1201 /* If we read not a page aligned data */
1202 if (data_col_addr != 0)
1203 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1204
1205 p = bufpoi + data_col_addr;
1206 chip->read_buf(mtd, p, datafrag_len);
1207
8b6e50c9 1208 /* Calculate ECC */
3d459559
AK		 1209 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1210 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1211
8b6e50c9
BN		 1212 /*
1213 * The performance is faster if we position offsets according to
7854d3f7 1214 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1215 */
3d459559
AK		 1216 for (i = 0; i < eccfrag_len - 1; i++) {
1217 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1218 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1219 gaps = 1;
1220 break;
1221 }
1222 }
1223 if (gaps) {
1224 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1225 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1226 } else {
8b6e50c9 1227 /*
7854d3f7 1228 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1229 * about buswidth alignment in read_buf.
1230 */
7351d3a5
FF		 1231 index = start_step * chip->ecc.bytes;
1232
1233 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1234 aligned_len = eccfrag_len;
7351d3a5 1235 if (eccpos[index] & (busw - 1))
3d459559 1236 aligned_len++;
7351d3a5 1237 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1238 aligned_len++;
1239
7351d3a5
FF		 1240 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1241 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1242 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1243 }
1244
1245 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1246 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1247
1248 p = bufpoi + data_col_addr;
1249 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1250 int stat;
1251
7351d3a5
FF		 1252 stat = chip->ecc.correct(mtd, p,
1253 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1254 if (stat < 0) {
3d459559 1255 mtd->ecc_stats.failed++;
3f91e94f 1256 } else {
3d459559 1257 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1258 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1259 }
3d459559 1260 }
3f91e94f 1261 return max_bitflips;
3d459559
AK		 1262}
1263
068e3c0a 1264/**
7854d3f7 1265 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1266 * @mtd: mtd info structure
1267 * @chip: nand chip info structure
1268 * @buf: buffer to store read data
1fbb938d 1269 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1270 * @page: page number to read
068e3c0a 1271 *
7854d3f7 1272 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1273 */
f5bbdacc 1274static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1275 uint8_t *buf, int oob_required, int page)
1da177e4 1276{
f5bbdacc
TG		 1277 int i, eccsize = chip->ecc.size;
1278 int eccbytes = chip->ecc.bytes;
1279 int eccsteps = chip->ecc.steps;
1280 uint8_t *p = buf;
4bf63fcb
DW		 1281 uint8_t *ecc_calc = chip->buffers->ecccalc;
1282 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1283 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1284 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1285
1286 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1287 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1288 chip->read_buf(mtd, p, eccsize);
1289 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1290 }
f75e5097 1291 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1292
f5bbdacc 1293 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1294 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1295
f5bbdacc
TG		 1296 eccsteps = chip->ecc.steps;
1297 p = buf;
61b03bd7 1298
f5bbdacc
TG		 1299 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1300 int stat;
1da177e4 1301
f5bbdacc 1302 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1303 if (stat < 0) {
f5bbdacc 1304 mtd->ecc_stats.failed++;
3f91e94f 1305 } else {
f5bbdacc 1306 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1307 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1308 }
f5bbdacc 1309 }
3f91e94f 1310 return max_bitflips;
f5bbdacc 1311}
1da177e4 1312
6e0cb135 1313/**
7854d3f7 1314 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1315 * @mtd: mtd info structure
1316 * @chip: nand chip info structure
1317 * @buf: buffer to store read data
1fbb938d 1318 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1319 * @page: page number to read
6e0cb135 1320 *
8b6e50c9
BN		 1321 * Hardware ECC for large page chips, require OOB to be read first. For this
1322 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1323 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1324 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1325 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1326 */
1327static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1328 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1329{
1330 int i, eccsize = chip->ecc.size;
1331 int eccbytes = chip->ecc.bytes;
1332 int eccsteps = chip->ecc.steps;
1333 uint8_t *p = buf;
1334 uint8_t *ecc_code = chip->buffers->ecccode;
1335 uint32_t *eccpos = chip->ecc.layout->eccpos;
1336 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1337 unsigned int max_bitflips = 0;
6e0cb135
SN		 1338
1339 /* Read the OOB area first */
1340 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1341 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1342 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1343
1344 for (i = 0; i < chip->ecc.total; i++)
1345 ecc_code[i] = chip->oob_poi[eccpos[i]];
1346
1347 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1348 int stat;
1349
1350 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1351 chip->read_buf(mtd, p, eccsize);
1352 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1353
1354 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1355 if (stat < 0) {
6e0cb135 1356 mtd->ecc_stats.failed++;
3f91e94f 1357 } else {
6e0cb135 1358 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1359 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1360 }
6e0cb135 1361 }
3f91e94f 1362 return max_bitflips;
6e0cb135
SN		 1363}
1364
f5bbdacc 1365/**
7854d3f7 1366 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1367 * @mtd: mtd info structure
1368 * @chip: nand chip info structure
1369 * @buf: buffer to store read data
1fbb938d 1370 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1371 * @page: page number to read
f5bbdacc 1372 *
8b6e50c9
BN		 1373 * The hw generator calculates the error syndrome automatically. Therefore we
1374 * need a special oob layout and handling.
f5bbdacc
TG		 1375 */
1376static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1377 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1378{
1379 int i, eccsize = chip->ecc.size;
1380 int eccbytes = chip->ecc.bytes;
1381 int eccsteps = chip->ecc.steps;
1382 uint8_t *p = buf;
f75e5097 1383 uint8_t *oob = chip->oob_poi;
3f91e94f 1384 unsigned int max_bitflips = 0;
1da177e4 1385
f5bbdacc
TG		 1386 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1387 int stat;
61b03bd7 1388
f5bbdacc
TG		 1389 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1390 chip->read_buf(mtd, p, eccsize);
1da177e4 1391
f5bbdacc
TG		 1392 if (chip->ecc.prepad) {
1393 chip->read_buf(mtd, oob, chip->ecc.prepad);
1394 oob += chip->ecc.prepad;
1395 }
1da177e4 1396
f5bbdacc
TG		 1397 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1398 chip->read_buf(mtd, oob, eccbytes);
1399 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1400
3f91e94f 1401 if (stat < 0) {
f5bbdacc 1402 mtd->ecc_stats.failed++;
3f91e94f 1403 } else {
f5bbdacc 1404 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1405 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1406 }
61b03bd7 1407
f5bbdacc 1408 oob += eccbytes;
1da177e4 1409
f5bbdacc
TG		 1410 if (chip->ecc.postpad) {
1411 chip->read_buf(mtd, oob, chip->ecc.postpad);
1412 oob += chip->ecc.postpad;
61b03bd7 1413 }
f5bbdacc 1414 }
1da177e4 1415
f5bbdacc 1416 /* Calculate remaining oob bytes */
7e4178f9 1417 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1418 if (i)
1419 chip->read_buf(mtd, oob, i);
61b03bd7 1420
3f91e94f 1421 return max_bitflips;
f5bbdacc 1422}
1da177e4 1423
f5bbdacc 1424/**
7854d3f7 1425 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1426 * @chip: nand chip structure
1427 * @oob: oob destination address
1428 * @ops: oob ops structure
1429 * @len: size of oob to transfer
8593fbc6
TG		 1430 */
1431static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1432 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1433{
f8ac0414 1434 switch (ops->mode) {
8593fbc6 1435
0612b9dd
BN		 1436 case MTD_OPS_PLACE_OOB:
1437 case MTD_OPS_RAW:
8593fbc6
TG		 1438 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1439 return oob + len;
1440
0612b9dd 1441 case MTD_OPS_AUTO_OOB: {
8593fbc6 1442 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1443 uint32_t boffs = 0, roffs = ops->ooboffs;
1444 size_t bytes = 0;
8593fbc6 1445
f8ac0414 1446 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1447 /* Read request not from offset 0? */
7bc3312b
TG		 1448 if (unlikely(roffs)) {
1449 if (roffs >= free->length) {
1450 roffs -= free->length;
1451 continue;
1452 }
1453 boffs = free->offset + roffs;
1454 bytes = min_t(size_t, len,
1455 (free->length - roffs));
1456 roffs = 0;
1457 } else {
1458 bytes = min_t(size_t, len, free->length);
1459 boffs = free->offset;
1460 }
1461 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1462 oob += bytes;
1463 }
1464 return oob;
1465 }
1466 default:
1467 BUG();
1468 }
1469 return NULL;
1470}
1471
1472/**
7854d3f7 1473 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1474 * @mtd: MTD device structure
1475 * @from: offset to read from
1476 * @ops: oob ops structure
f5bbdacc
TG		 1477 *
1478 * Internal function. Called with chip held.
1479 */
8593fbc6
TG		 1480static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1481 struct mtd_oob_ops *ops)
f5bbdacc 1482{
e47f3db4 1483 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc
TG		 1484 struct nand_chip *chip = mtd->priv;
1485 struct mtd_ecc_stats stats;
f5bbdacc 1486 int ret = 0;
8593fbc6 1487 uint32_t readlen = ops->len;
7014568b 1488 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1489 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1490 mtd->oobavail : mtd->oobsize;
1491
8593fbc6 1492 uint8_t *bufpoi, *oob, *buf;
edbc4540 1493 unsigned int max_bitflips = 0;
1da177e4 1494
f5bbdacc 1495 stats = mtd->ecc_stats;
1da177e4 1496
f5bbdacc
TG		 1497 chipnr = (int)(from >> chip->chip_shift);
1498 chip->select_chip(mtd, chipnr);
61b03bd7 1499
f5bbdacc
TG		 1500 realpage = (int)(from >> chip->page_shift);
1501 page = realpage & chip->pagemask;
1da177e4 1502
f5bbdacc 1503 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1504
8593fbc6
TG		 1505 buf = ops->datbuf;
1506 oob = ops->oobbuf;
e47f3db4 1507 oob_required = oob ? 1 : 0;
8593fbc6 1508
f8ac0414 1509 while (1) {
f5bbdacc
TG		 1510 bytes = min(mtd->writesize - col, readlen);
1511 aligned = (bytes == mtd->writesize);
61b03bd7 1512
8b6e50c9 1513 /* Is the current page in the buffer? */
8593fbc6 1514 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1515 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1516
c00a0991 1517 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1518
edbc4540
MD		 1519 /*
1520 * Now read the page into the buffer. Absent an error,
1521 * the read methods return max bitflips per ecc step.
1522 */
0612b9dd 1523 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1524 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1525 oob_required,
1526 page);
3d459559 1527 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1528 ret = chip->ecc.read_subpage(mtd, chip,
1529 col, bytes, bufpoi);
956e944c 1530 else
46a8cf2d 1531 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1532 oob_required, page);
6d77b9d0
BN		 1533 if (ret < 0) {
1534 if (!aligned)
1535 /* Invalidate page cache */
1536 chip->pagebuf = -1;
1da177e4 1537 break;
6d77b9d0 1538 }
f5bbdacc 1539
edbc4540
MD		 1540 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1541
f5bbdacc
TG		 1542 /* Transfer not aligned data */
1543 if (!aligned) {
c1194c79 1544 if (!NAND_SUBPAGE_READ(chip) && !oob &&
6d77b9d0 1545 !(mtd->ecc_stats.failed - stats.failed) &&
edbc4540 1546 (ops->mode != MTD_OPS_RAW)) {
3d459559 1547 chip->pagebuf = realpage;
edbc4540
MD		 1548 chip->pagebuf_bitflips = ret;
1549 } else {
6d77b9d0
BN		 1550 /* Invalidate page cache */
1551 chip->pagebuf = -1;
edbc4540 1552 }
4bf63fcb 1553 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1554 }
1555
8593fbc6
TG		 1556 buf += bytes;
1557
1558 if (unlikely(oob)) {
b64d39d8
ML		 1559 int toread = min(oobreadlen, max_oobsize);
1560
1561 if (toread) {
1562 oob = nand_transfer_oob(chip,
1563 oob, ops, toread);
1564 oobreadlen -= toread;
1565 }
8593fbc6
TG		 1566 }
1567
f5bbdacc 1568 if (!(chip->options & NAND_NO_READRDY)) {
c00a0991 1569 /* Apply delay or wait for ready/busy pin */
f5bbdacc
TG		 1570 if (!chip->dev_ready)
1571 udelay(chip->chip_delay);
1572 else
1573 nand_wait_ready(mtd);
1da177e4 1574 }
8593fbc6 1575 } else {
4bf63fcb 1576 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1577 buf += bytes;
edbc4540
MD		 1578 max_bitflips = max_t(unsigned int, max_bitflips,
1579 chip->pagebuf_bitflips);
8593fbc6 1580 }
1da177e4 1581
f5bbdacc 1582 readlen -= bytes;
61b03bd7 1583
f5bbdacc 1584 if (!readlen)
61b03bd7 1585 break;
1da177e4 1586
8b6e50c9 1587 /* For subsequent reads align to page boundary */
1da177e4
LT		 1588 col = 0;
1589 /* Increment page address */
1590 realpage++;
1591
ace4dfee 1592 page = realpage & chip->pagemask;
1da177e4
LT		 1593 /* Check, if we cross a chip boundary */
1594 if (!page) {
1595 chipnr++;
ace4dfee
TG		 1596 chip->select_chip(mtd, -1);
1597 chip->select_chip(mtd, chipnr);
1da177e4 1598 }
1da177e4
LT		 1599 }
1600
8593fbc6 1601 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1602 if (oob)
1603 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1604
3f91e94f 1605 if (ret < 0)
f5bbdacc
TG		 1606 return ret;
1607
9a1fcdfd
TG		 1608 if (mtd->ecc_stats.failed - stats.failed)
1609 return -EBADMSG;
1610
edbc4540 1611 return max_bitflips;
f5bbdacc
TG		 1612}
1613
1614/**
25985edc 1615 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1616 * @mtd: MTD device structure
1617 * @from: offset to read from
1618 * @len: number of bytes to read
1619 * @retlen: pointer to variable to store the number of read bytes
1620 * @buf: the databuffer to put data
f5bbdacc 1621 *
8b6e50c9 1622 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1623 */
1624static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1625 size_t *retlen, uint8_t *buf)
1626{
8593fbc6 1627 struct nand_chip *chip = mtd->priv;
4a89ff88 1628 struct mtd_oob_ops ops;
f5bbdacc
TG		 1629 int ret;
1630
8593fbc6 1631 nand_get_device(chip, mtd, FL_READING);
4a89ff88
BN		 1632 ops.len = len;
1633 ops.datbuf = buf;
1634 ops.oobbuf = NULL;
23b1a99b 1635 ops.mode = 0;
4a89ff88 1636 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1637 *retlen = ops.retlen;
f5bbdacc 1638 nand_release_device(mtd);
f5bbdacc 1639 return ret;
1da177e4
LT		 1640}
1641
7bc3312b 1642/**
7854d3f7 1643 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1644 * @mtd: mtd info structure
1645 * @chip: nand chip info structure
1646 * @page: page number to read
1647 * @sndcmd: flag whether to issue read command or not
7bc3312b
TG		 1648 */
1649static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1650 int page, int sndcmd)
1651{
1652 if (sndcmd) {
1653 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1654 sndcmd = 0;
1655 }
1656 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1657 return sndcmd;
1658}
1659
1660/**
7854d3f7 1661 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1662 * with syndromes
8b6e50c9
BN		 1663 * @mtd: mtd info structure
1664 * @chip: nand chip info structure
1665 * @page: page number to read
1666 * @sndcmd: flag whether to issue read command or not
7bc3312b
TG		 1667 */
1668static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1669 int page, int sndcmd)
1670{
1671 uint8_t *buf = chip->oob_poi;
1672 int length = mtd->oobsize;
1673 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1674 int eccsize = chip->ecc.size;
1675 uint8_t *bufpoi = buf;
1676 int i, toread, sndrnd = 0, pos;
1677
1678 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1679 for (i = 0; i < chip->ecc.steps; i++) {
1680 if (sndrnd) {
1681 pos = eccsize + i * (eccsize + chunk);
1682 if (mtd->writesize > 512)
1683 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1684 else
1685 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1686 } else
1687 sndrnd = 1;
1688 toread = min_t(int, length, chunk);
1689 chip->read_buf(mtd, bufpoi, toread);
1690 bufpoi += toread;
1691 length -= toread;
1692 }
1693 if (length > 0)
1694 chip->read_buf(mtd, bufpoi, length);
1695
1696 return 1;
1697}
1698
1699/**
7854d3f7 1700 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1701 * @mtd: mtd info structure
1702 * @chip: nand chip info structure
1703 * @page: page number to write
7bc3312b
TG		 1704 */
1705static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1706 int page)
1707{
1708 int status = 0;
1709 const uint8_t *buf = chip->oob_poi;
1710 int length = mtd->oobsize;
1711
1712 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1713 chip->write_buf(mtd, buf, length);
1714 /* Send command to program the OOB data */
1715 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1716
1717 status = chip->waitfunc(mtd, chip);
1718
0d420f9d 1719 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1720}
1721
1722/**
7854d3f7 1723 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1724 * with syndrome - only for large page flash
1725 * @mtd: mtd info structure
1726 * @chip: nand chip info structure
1727 * @page: page number to write
7bc3312b
TG		 1728 */
1729static int nand_write_oob_syndrome(struct mtd_info *mtd,
1730 struct nand_chip *chip, int page)
1731{
1732 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1733 int eccsize = chip->ecc.size, length = mtd->oobsize;
1734 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1735 const uint8_t *bufpoi = chip->oob_poi;
1736
1737 /*
1738 * data-ecc-data-ecc ... ecc-oob
1739 * or
1740 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1741 */
1742 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1743 pos = steps * (eccsize + chunk);
1744 steps = 0;
1745 } else
8b0036ee 1746 pos = eccsize;
7bc3312b
TG		 1747
1748 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1749 for (i = 0; i < steps; i++) {
1750 if (sndcmd) {
1751 if (mtd->writesize <= 512) {
1752 uint32_t fill = 0xFFFFFFFF;
1753
1754 len = eccsize;
1755 while (len > 0) {
1756 int num = min_t(int, len, 4);
1757 chip->write_buf(mtd, (uint8_t *)&fill,
1758 num);
1759 len -= num;
1760 }
1761 } else {
1762 pos = eccsize + i * (eccsize + chunk);
1763 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1764 }
1765 } else
1766 sndcmd = 1;
1767 len = min_t(int, length, chunk);
1768 chip->write_buf(mtd, bufpoi, len);
1769 bufpoi += len;
1770 length -= len;
1771 }
1772 if (length > 0)
1773 chip->write_buf(mtd, bufpoi, length);
1774
1775 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1776 status = chip->waitfunc(mtd, chip);
1777
1778 return status & NAND_STATUS_FAIL ? -EIO : 0;
1779}
1780
1da177e4 1781/**
7854d3f7 1782 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1783 * @mtd: MTD device structure
1784 * @from: offset to read from
1785 * @ops: oob operations description structure
1da177e4 1786 *
8b6e50c9 1787 * NAND read out-of-band data from the spare area.
1da177e4 1788 */
8593fbc6
TG		 1789static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1790 struct mtd_oob_ops *ops)
1da177e4 1791{
c00a0991 1792 int page, realpage, chipnr;
ace4dfee 1793 struct nand_chip *chip = mtd->priv;
041e4575 1794 struct mtd_ecc_stats stats;
7014568b
VW		 1795 int readlen = ops->ooblen;
1796 int len;
7bc3312b 1797 uint8_t *buf = ops->oobbuf;
61b03bd7 1798
289c0522 1799 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1800 __func__, (unsigned long long)from, readlen);
1da177e4 1801
041e4575
BN		 1802 stats = mtd->ecc_stats;
1803
0612b9dd 1804 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1805 len = chip->ecc.layout->oobavail;
03736155
AH		 1806 else
1807 len = mtd->oobsize;
1808
1809 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1810 pr_debug("%s: attempt to start read outside oob\n",
1811 __func__);
03736155
AH		 1812 return -EINVAL;
1813 }
1814
1815 /* Do not allow reads past end of device */
1816 if (unlikely(from >= mtd->size ||
1817 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1818 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1819 pr_debug("%s: attempt to read beyond end of device\n",
1820 __func__);
03736155
AH		 1821 return -EINVAL;
1822 }
7014568b 1823
7314e9e7 1824 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1825 chip->select_chip(mtd, chipnr);
1da177e4 1826
7314e9e7
TG		 1827 /* Shift to get page */
1828 realpage = (int)(from >> chip->page_shift);
1829 page = realpage & chip->pagemask;
1da177e4 1830
f8ac0414 1831 while (1) {
0612b9dd 1832 if (ops->mode == MTD_OPS_RAW)
c00a0991 1833 chip->ecc.read_oob_raw(mtd, chip, page, 1);
c46f6483 1834 else
c00a0991 1835 chip->ecc.read_oob(mtd, chip, page, 1);
7014568b
VW		 1836
1837 len = min(len, readlen);
1838 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1839
7314e9e7 1840 if (!(chip->options & NAND_NO_READRDY)) {
c00a0991 1841 /* Apply delay or wait for ready/busy pin */
ace4dfee
TG		 1842 if (!chip->dev_ready)
1843 udelay(chip->chip_delay);
19870da7
TG		 1844 else
1845 nand_wait_ready(mtd);
7314e9e7 1846 }
19870da7 1847
7014568b 1848 readlen -= len;
0d420f9d
SZ		 1849 if (!readlen)
1850 break;
1851
7314e9e7
TG		 1852 /* Increment page address */
1853 realpage++;
1854
1855 page = realpage & chip->pagemask;
1856 /* Check, if we cross a chip boundary */
1857 if (!page) {
1858 chipnr++;
1859 chip->select_chip(mtd, -1);
1860 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1861 }
1862 }
1863
7014568b 1864 ops->oobretlen = ops->ooblen;
041e4575
BN		 1865
1866 if (mtd->ecc_stats.failed - stats.failed)
1867 return -EBADMSG;
1868
1869 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1870}
1871
1872/**
8593fbc6 1873 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1874 * @mtd: MTD device structure
1875 * @from: offset to read from
1876 * @ops: oob operation description structure
1da177e4 1877 *
8b6e50c9 1878 * NAND read data and/or out-of-band data.
1da177e4 1879 */
8593fbc6
TG		 1880static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1881 struct mtd_oob_ops *ops)
1da177e4 1882{
ace4dfee 1883 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1884 int ret = -ENOTSUPP;
1885
1886 ops->retlen = 0;
1da177e4
LT		 1887
1888 /* Do not allow reads past end of device */
7014568b 1889 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1890 pr_debug("%s: attempt to read beyond end of device\n",
1891 __func__);
1da177e4
LT		 1892 return -EINVAL;
1893 }
1894
ace4dfee 1895 nand_get_device(chip, mtd, FL_READING);
1da177e4 1896
f8ac0414 1897 switch (ops->mode) {
0612b9dd
BN		 1898 case MTD_OPS_PLACE_OOB:
1899 case MTD_OPS_AUTO_OOB:
1900 case MTD_OPS_RAW:
8593fbc6 1901 break;
1da177e4 1902
8593fbc6
TG		 1903 default:
1904 goto out;
1905 }
1da177e4 1906
8593fbc6
TG		 1907 if (!ops->datbuf)
1908 ret = nand_do_read_oob(mtd, from, ops);
1909 else
1910 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1911
7351d3a5 1912out:
8593fbc6
TG		 1913 nand_release_device(mtd);
1914 return ret;
1915}
61b03bd7 1916
1da177e4 1917
8593fbc6 1918/**
7854d3f7 1919 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1920 * @mtd: mtd info structure
1921 * @chip: nand chip info structure
1922 * @buf: data buffer
1fbb938d 1923 * @oob_required: must write chip->oob_poi to OOB
52ff49df 1924 *
7854d3f7 1925 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1926 */
1927static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1928 const uint8_t *buf, int oob_required)
8593fbc6
TG		 1929{
1930 chip->write_buf(mtd, buf, mtd->writesize);
1931 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1932}
1933
52ff49df 1934/**
7854d3f7 1935 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1936 * @mtd: mtd info structure
1937 * @chip: nand chip info structure
1938 * @buf: data buffer
1fbb938d 1939 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 1940 *
1941 * We need a special oob layout and handling even when ECC isn't checked.
1942 */
7351d3a5
FF		 1943static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1944 struct nand_chip *chip,
1fbb938d 1945 const uint8_t *buf, int oob_required)
52ff49df
DB		 1946{
1947 int eccsize = chip->ecc.size;
1948 int eccbytes = chip->ecc.bytes;
1949 uint8_t *oob = chip->oob_poi;
1950 int steps, size;
1951
1952 for (steps = chip->ecc.steps; steps > 0; steps--) {
1953 chip->write_buf(mtd, buf, eccsize);
1954 buf += eccsize;
1955
1956 if (chip->ecc.prepad) {
1957 chip->write_buf(mtd, oob, chip->ecc.prepad);
1958 oob += chip->ecc.prepad;
1959 }
1960
1961 chip->read_buf(mtd, oob, eccbytes);
1962 oob += eccbytes;
1963
1964 if (chip->ecc.postpad) {
1965 chip->write_buf(mtd, oob, chip->ecc.postpad);
1966 oob += chip->ecc.postpad;
1967 }
1968 }
1969
1970 size = mtd->oobsize - (oob - chip->oob_poi);
1971 if (size)
1972 chip->write_buf(mtd, oob, size);
1973}
9223a456 1974/**
7854d3f7 1975 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1976 * @mtd: mtd info structure
1977 * @chip: nand chip info structure
1978 * @buf: data buffer
1fbb938d 1979 * @oob_required: must write chip->oob_poi to OOB
9223a456 1980 */
f75e5097 1981static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1982 const uint8_t *buf, int oob_required)
9223a456 1983{
f75e5097
TG		 1984 int i, eccsize = chip->ecc.size;
1985 int eccbytes = chip->ecc.bytes;
1986 int eccsteps = chip->ecc.steps;
4bf63fcb 1987 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1988 const uint8_t *p = buf;
8b099a39 1989 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1990
7854d3f7 1991 /* Software ECC calculation */
8593fbc6
TG		 1992 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1993 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1994
8593fbc6
TG		 1995 for (i = 0; i < chip->ecc.total; i++)
1996 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1997
1fbb938d 1998 chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 1999}
9223a456 2000
f75e5097 2001/**
7854d3f7 2002 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2003 * @mtd: mtd info structure
2004 * @chip: nand chip info structure
2005 * @buf: data buffer
1fbb938d 2006 * @oob_required: must write chip->oob_poi to OOB
f75e5097
TG		 2007 */
2008static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2009 const uint8_t *buf, int oob_required)
f75e5097
TG		 2010{
2011 int i, eccsize = chip->ecc.size;
2012 int eccbytes = chip->ecc.bytes;
2013 int eccsteps = chip->ecc.steps;
4bf63fcb 2014 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2015 const uint8_t *p = buf;
8b099a39 2016 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2017
f75e5097
TG		 2018 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2019 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2020 chip->write_buf(mtd, p, eccsize);
f75e5097 2021 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2022 }
2023
f75e5097
TG		 2024 for (i = 0; i < chip->ecc.total; i++)
2025 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2026
2027 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 2028}
2029
61b03bd7 2030/**
7854d3f7 2031 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2032 * @mtd: mtd info structure
2033 * @chip: nand chip info structure
2034 * @buf: data buffer
1fbb938d 2035 * @oob_required: must write chip->oob_poi to OOB
1da177e4 2036 *
8b6e50c9
BN		 2037 * The hw generator calculates the error syndrome automatically. Therefore we
2038 * need a special oob layout and handling.
f75e5097
TG		 2039 */
2040static void nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 2041 struct nand_chip *chip,
2042 const uint8_t *buf, int oob_required)
1da177e4 2043{
f75e5097
TG		 2044 int i, eccsize = chip->ecc.size;
2045 int eccbytes = chip->ecc.bytes;
2046 int eccsteps = chip->ecc.steps;
2047 const uint8_t *p = buf;
2048 uint8_t *oob = chip->oob_poi;
1da177e4 2049
f75e5097 2050 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2051
f75e5097
TG		 2052 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2053 chip->write_buf(mtd, p, eccsize);
61b03bd7 2054
f75e5097
TG		 2055 if (chip->ecc.prepad) {
2056 chip->write_buf(mtd, oob, chip->ecc.prepad);
2057 oob += chip->ecc.prepad;
2058 }
2059
2060 chip->ecc.calculate(mtd, p, oob);
2061 chip->write_buf(mtd, oob, eccbytes);
2062 oob += eccbytes;
2063
2064 if (chip->ecc.postpad) {
2065 chip->write_buf(mtd, oob, chip->ecc.postpad);
2066 oob += chip->ecc.postpad;
1da177e4 2067 }
1da177e4 2068 }
f75e5097
TG		 2069
2070 /* Calculate remaining oob bytes */
7e4178f9 2071 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2072 if (i)
2073 chip->write_buf(mtd, oob, i);
2074}
2075
2076/**
956e944c 2077 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2078 * @mtd: MTD device structure
2079 * @chip: NAND chip descriptor
2080 * @buf: the data to write
1fbb938d 2081 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2082 * @page: page number to write
2083 * @cached: cached programming
2084 * @raw: use _raw version of write_page
f75e5097
TG		 2085 */
2086static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d
BN		 2087 const uint8_t *buf, int oob_required, int page,
2088 int cached, int raw)
f75e5097
TG		 2089{
2090 int status;
2091
2092 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2093
956e944c 2094 if (unlikely(raw))
1fbb938d 2095 chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
956e944c 2096 else
1fbb938d 2097 chip->ecc.write_page(mtd, chip, buf, oob_required);
f75e5097
TG		 2098
2099 /*
7854d3f7 2100 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2101 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2102 */
2103 cached = 0;
2104
2105 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2106
2107 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2108 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2109 /*
2110 * See if operation failed and additional status checks are
8b6e50c9 2111 * available.
f75e5097
TG		 2112 */
2113 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2114 status = chip->errstat(mtd, chip, FL_WRITING, status,
2115 page);
2116
2117 if (status & NAND_STATUS_FAIL)
2118 return -EIO;
2119 } else {
2120 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2121 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2122 }
2123
2124#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2125 /* Send command to read back the data */
2126 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2127
2128 if (chip->verify_buf(mtd, buf, mtd->writesize))
2129 return -EIO;
09cbe581
BH		 2130
2131 /* Make sure the next page prog is preceded by a status read */
2132 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
f75e5097
TG		 2133#endif
2134 return 0;
1da177e4
LT		 2135}
2136
8593fbc6 2137/**
7854d3f7 2138 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2139 * @mtd: MTD device structure
8b6e50c9
BN		 2140 * @oob: oob data buffer
2141 * @len: oob data write length
2142 * @ops: oob ops structure
8593fbc6 2143 */
f722013e
TAA		 2144static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2145 struct mtd_oob_ops *ops)
8593fbc6 2146{
f722013e
TAA		 2147 struct nand_chip *chip = mtd->priv;
2148
2149 /*
2150 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2151 * data from a previous OOB read.
2152 */
2153 memset(chip->oob_poi, 0xff, mtd->oobsize);
2154
f8ac0414 2155 switch (ops->mode) {
8593fbc6 2156
0612b9dd
BN		 2157 case MTD_OPS_PLACE_OOB:
2158 case MTD_OPS_RAW:
8593fbc6
TG		 2159 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2160 return oob + len;
2161
0612b9dd 2162 case MTD_OPS_AUTO_OOB: {
8593fbc6 2163 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2164 uint32_t boffs = 0, woffs = ops->ooboffs;
2165 size_t bytes = 0;
8593fbc6 2166
f8ac0414 2167 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2168 /* Write request not from offset 0? */
7bc3312b
TG		 2169 if (unlikely(woffs)) {
2170 if (woffs >= free->length) {
2171 woffs -= free->length;
2172 continue;
2173 }
2174 boffs = free->offset + woffs;
2175 bytes = min_t(size_t, len,
2176 (free->length - woffs));
2177 woffs = 0;
2178 } else {
2179 bytes = min_t(size_t, len, free->length);
2180 boffs = free->offset;
2181 }
8b0036ee 2182 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2183 oob += bytes;
2184 }
2185 return oob;
2186 }
2187 default:
2188 BUG();
2189 }
2190 return NULL;
2191}
2192
f8ac0414 2193#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2194
2195/**
7854d3f7 2196 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2197 * @mtd: MTD device structure
2198 * @to: offset to write to
2199 * @ops: oob operations description structure
1da177e4 2200 *
8b6e50c9 2201 * NAND write with ECC.
1da177e4 2202 */
8593fbc6
TG		 2203static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2204 struct mtd_oob_ops *ops)
1da177e4 2205{
29072b96 2206 int chipnr, realpage, page, blockmask, column;
ace4dfee 2207 struct nand_chip *chip = mtd->priv;
8593fbc6 2208 uint32_t writelen = ops->len;
782ce79a
ML		 2209
2210 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2211 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2212 mtd->oobavail : mtd->oobsize;
2213
8593fbc6
TG		 2214 uint8_t *oob = ops->oobbuf;
2215 uint8_t *buf = ops->datbuf;
29072b96 2216 int ret, subpage;
e47f3db4 2217 int oob_required = oob ? 1 : 0;
1da177e4 2218
8593fbc6 2219 ops->retlen = 0;
29072b96
TG		 2220 if (!writelen)
2221 return 0;
1da177e4 2222
8b6e50c9 2223 /* Reject writes, which are not page aligned */
8593fbc6 2224 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2225 pr_notice("%s: attempt to write non page aligned data\n",
2226 __func__);
1da177e4
LT		 2227 return -EINVAL;
2228 }
2229
29072b96
TG		 2230 column = to & (mtd->writesize - 1);
2231 subpage = column || (writelen & (mtd->writesize - 1));
2232
2233 if (subpage && oob)
2234 return -EINVAL;
1da177e4 2235
6a930961
TG		 2236 chipnr = (int)(to >> chip->chip_shift);
2237 chip->select_chip(mtd, chipnr);
2238
1da177e4
LT		 2239 /* Check, if it is write protected */
2240 if (nand_check_wp(mtd))
8593fbc6 2241 return -EIO;
1da177e4 2242
f75e5097
TG		 2243 realpage = (int)(to >> chip->page_shift);
2244 page = realpage & chip->pagemask;
2245 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2246
2247 /* Invalidate the page cache, when we write to the cached page */
2248 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2249 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2250 chip->pagebuf = -1;
61b03bd7 2251
782ce79a 2252 /* Don't allow multipage oob writes with offset */
cdcf12b2 2253 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2254 return -EINVAL;
2255
f8ac0414 2256 while (1) {
29072b96 2257 int bytes = mtd->writesize;
f75e5097 2258 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2259 uint8_t *wbuf = buf;
2260
8b6e50c9 2261 /* Partial page write? */
29072b96
TG		 2262 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2263 cached = 0;
2264 bytes = min_t(int, bytes - column, (int) writelen);
2265 chip->pagebuf = -1;
2266 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2267 memcpy(&chip->buffers->databuf[column], buf, bytes);
2268 wbuf = chip->buffers->databuf;
2269 }
1da177e4 2270
782ce79a
ML		 2271 if (unlikely(oob)) {
2272 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2273 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2274 oobwritelen -= len;
f722013e
TAA		 2275 } else {
2276 /* We still need to erase leftover OOB data */
2277 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2278 }
8593fbc6 2279
e47f3db4
BN		 2280 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2281 cached, (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2282 if (ret)
2283 break;
2284
2285 writelen -= bytes;
2286 if (!writelen)
2287 break;
2288
29072b96 2289 column = 0;
f75e5097
TG		 2290 buf += bytes;
2291 realpage++;
2292
2293 page = realpage & chip->pagemask;
2294 /* Check, if we cross a chip boundary */
2295 if (!page) {
2296 chipnr++;
2297 chip->select_chip(mtd, -1);
2298 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2299 }
2300 }
8593fbc6 2301
8593fbc6 2302 ops->retlen = ops->len - writelen;
7014568b
VW		 2303 if (unlikely(oob))
2304 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2305 return ret;
2306}
2307
2af7c653
SK		 2308/**
2309 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2310 * @mtd: MTD device structure
2311 * @to: offset to write to
2312 * @len: number of bytes to write
2313 * @retlen: pointer to variable to store the number of written bytes
2314 * @buf: the data to write
2af7c653
SK		 2315 *
2316 * NAND write with ECC. Used when performing writes in interrupt context, this
2317 * may for example be called by mtdoops when writing an oops while in panic.
2318 */
2319static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2320 size_t *retlen, const uint8_t *buf)
2321{
2322 struct nand_chip *chip = mtd->priv;
4a89ff88 2323 struct mtd_oob_ops ops;
2af7c653
SK		 2324 int ret;
2325
8b6e50c9 2326 /* Wait for the device to get ready */
2af7c653
SK		 2327 panic_nand_wait(mtd, chip, 400);
2328
8b6e50c9 2329 /* Grab the device */
2af7c653
SK		 2330 panic_nand_get_device(chip, mtd, FL_WRITING);
2331
4a89ff88
BN		 2332 ops.len = len;
2333 ops.datbuf = (uint8_t *)buf;
2334 ops.oobbuf = NULL;
23b1a99b 2335 ops.mode = 0;
2af7c653 2336
4a89ff88 2337 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2338
4a89ff88 2339 *retlen = ops.retlen;
2af7c653
SK		 2340 return ret;
2341}
2342
f75e5097 2343/**
8593fbc6 2344 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2345 * @mtd: MTD device structure
2346 * @to: offset to write to
2347 * @len: number of bytes to write
2348 * @retlen: pointer to variable to store the number of written bytes
2349 * @buf: the data to write
f75e5097 2350 *
8b6e50c9 2351 * NAND write with ECC.
f75e5097 2352 */
8593fbc6
TG		 2353static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2354 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2355{
2356 struct nand_chip *chip = mtd->priv;
4a89ff88 2357 struct mtd_oob_ops ops;
f75e5097
TG		 2358 int ret;
2359
7bc3312b 2360 nand_get_device(chip, mtd, FL_WRITING);
4a89ff88
BN		 2361 ops.len = len;
2362 ops.datbuf = (uint8_t *)buf;
2363 ops.oobbuf = NULL;
23b1a99b 2364 ops.mode = 0;
4a89ff88 2365 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2366 *retlen = ops.retlen;
f75e5097 2367 nand_release_device(mtd);
8593fbc6 2368 return ret;
f75e5097 2369}
7314e9e7 2370
1da177e4 2371/**
8593fbc6 2372 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2373 * @mtd: MTD device structure
2374 * @to: offset to write to
2375 * @ops: oob operation description structure
1da177e4 2376 *
8b6e50c9 2377 * NAND write out-of-band.
1da177e4 2378 */
8593fbc6
TG		 2379static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2380 struct mtd_oob_ops *ops)
1da177e4 2381{
03736155 2382 int chipnr, page, status, len;
ace4dfee 2383 struct nand_chip *chip = mtd->priv;
1da177e4 2384
289c0522 2385 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2386 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2387
0612b9dd 2388 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2389 len = chip->ecc.layout->oobavail;
2390 else
2391 len = mtd->oobsize;
2392
1da177e4 2393 /* Do not allow write past end of page */
03736155 2394 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2395 pr_debug("%s: attempt to write past end of page\n",
2396 __func__);
1da177e4
LT		 2397 return -EINVAL;
2398 }
2399
03736155 2400 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2401 pr_debug("%s: attempt to start write outside oob\n",
2402 __func__);
03736155
AH		 2403 return -EINVAL;
2404 }
2405
775adc3d 2406 /* Do not allow write past end of device */
03736155
AH		 2407 if (unlikely(to >= mtd->size ||
2408 ops->ooboffs + ops->ooblen >
2409 ((mtd->size >> chip->page_shift) -
2410 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2411 pr_debug("%s: attempt to write beyond end of device\n",
2412 __func__);
03736155
AH		 2413 return -EINVAL;
2414 }
2415
7314e9e7 2416 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2417 chip->select_chip(mtd, chipnr);
1da177e4 2418
7314e9e7
TG		 2419 /* Shift to get page */
2420 page = (int)(to >> chip->page_shift);
2421
2422 /*
2423 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2424 * of my DiskOnChip 2000 test units) will clear the whole data page too
2425 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2426 * it in the doc2000 driver in August 1999. dwmw2.
2427 */
ace4dfee 2428 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2429
2430 /* Check, if it is write protected */
2431 if (nand_check_wp(mtd))
8593fbc6 2432 return -EROFS;
61b03bd7 2433
1da177e4 2434 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2435 if (page == chip->pagebuf)
2436 chip->pagebuf = -1;
1da177e4 2437
f722013e 2438 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2439
0612b9dd 2440 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2441 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2442 else
2443 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2444
7bc3312b
TG		 2445 if (status)
2446 return status;
1da177e4 2447
7014568b 2448 ops->oobretlen = ops->ooblen;
1da177e4 2449
7bc3312b 2450 return 0;
8593fbc6
TG		 2451}
2452
2453/**
2454 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2455 * @mtd: MTD device structure
2456 * @to: offset to write to
2457 * @ops: oob operation description structure
8593fbc6
TG		 2458 */
2459static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2460 struct mtd_oob_ops *ops)
2461{
8593fbc6
TG		 2462 struct nand_chip *chip = mtd->priv;
2463 int ret = -ENOTSUPP;
2464
2465 ops->retlen = 0;
2466
2467 /* Do not allow writes past end of device */
7014568b 2468 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2469 pr_debug("%s: attempt to write beyond end of device\n",
2470 __func__);
8593fbc6
TG		 2471 return -EINVAL;
2472 }
2473
7bc3312b 2474 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2475
f8ac0414 2476 switch (ops->mode) {
0612b9dd
BN		 2477 case MTD_OPS_PLACE_OOB:
2478 case MTD_OPS_AUTO_OOB:
2479 case MTD_OPS_RAW:
8593fbc6
TG		 2480 break;
2481
2482 default:
2483 goto out;
2484 }
2485
2486 if (!ops->datbuf)
2487 ret = nand_do_write_oob(mtd, to, ops);
2488 else
2489 ret = nand_do_write_ops(mtd, to, ops);
2490
7351d3a5 2491out:
1da177e4 2492 nand_release_device(mtd);
1da177e4
LT		 2493 return ret;
2494}
2495
1da177e4 2496/**
7854d3f7 2497 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2498 * @mtd: MTD device structure
2499 * @page: the page address of the block which will be erased
1da177e4 2500 *
8b6e50c9 2501 * Standard erase command for NAND chips.
1da177e4 2502 */
e0c7d767 2503static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2504{
ace4dfee 2505 struct nand_chip *chip = mtd->priv;
1da177e4 2506 /* Send commands to erase a block */
ace4dfee
TG		 2507 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2508 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2509}
2510
2511/**
7854d3f7 2512 * multi_erase_cmd - [GENERIC] AND specific block erase command function
8b6e50c9
BN		 2513 * @mtd: MTD device structure
2514 * @page: the page address of the block which will be erased
1da177e4 2515 *
8b6e50c9 2516 * AND multi block erase command function. Erase 4 consecutive blocks.
1da177e4 2517 */
e0c7d767 2518static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2519{
ace4dfee 2520 struct nand_chip *chip = mtd->priv;
1da177e4 2521 /* Send commands to erase a block */
ace4dfee
TG		 2522 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2523 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2524 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2525 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2526 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2527}
2528
2529/**
2530 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2531 * @mtd: MTD device structure
2532 * @instr: erase instruction
1da177e4 2533 *
8b6e50c9 2534 * Erase one ore more blocks.
1da177e4 2535 */
e0c7d767 2536static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2537{
e0c7d767 2538 return nand_erase_nand(mtd, instr, 0);
1da177e4 2539}
61b03bd7 2540
30f464b7 2541#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2542/**
7854d3f7 2543 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2544 * @mtd: MTD device structure
2545 * @instr: erase instruction
2546 * @allowbbt: allow erasing the bbt area
1da177e4 2547 *
8b6e50c9 2548 * Erase one ore more blocks.
1da177e4 2549 */
ace4dfee
TG		 2550int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2551 int allowbbt)
1da177e4 2552{
69423d99 2553 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2554 struct nand_chip *chip = mtd->priv;
f8ac0414 2555 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2556 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2557 loff_t len;
1da177e4 2558
289c0522
BN		 2559 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2560 __func__, (unsigned long long)instr->addr,
2561 (unsigned long long)instr->len);
1da177e4 2562
6fe5a6ac 2563 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2564 return -EINVAL;
1da177e4 2565
1da177e4 2566 /* Grab the lock and see if the device is available */
ace4dfee 2567 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2568
2569 /* Shift to get first page */
ace4dfee
TG		 2570 page = (int)(instr->addr >> chip->page_shift);
2571 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2572
2573 /* Calculate pages in each block */
ace4dfee 2574 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2575
2576 /* Select the NAND device */
ace4dfee 2577 chip->select_chip(mtd, chipnr);
1da177e4 2578
1da177e4
LT		 2579 /* Check, if it is write protected */
2580 if (nand_check_wp(mtd)) {
289c0522
BN		 2581 pr_debug("%s: device is write protected!\n",
2582 __func__);
1da177e4
LT		 2583 instr->state = MTD_ERASE_FAILED;
2584 goto erase_exit;
2585 }
2586
ace4dfee
TG		 2587 /*
2588 * If BBT requires refresh, set the BBT page mask to see if the BBT
2589 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2590 * can not be matched. This is also done when the bbt is actually
7854d3f7 2591 * erased to avoid recursive updates.
ace4dfee
TG		 2592 */
2593 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2594 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2595
1da177e4
LT		 2596 /* Loop through the pages */
2597 len = instr->len;
2598
2599 instr->state = MTD_ERASING;
2600
2601 while (len) {
12183a20 2602 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2603 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2604 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2605 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2606 __func__, page);
1da177e4
LT		 2607 instr->state = MTD_ERASE_FAILED;
2608 goto erase_exit;
2609 }
61b03bd7 2610
ace4dfee
TG		 2611 /*
2612 * Invalidate the page cache, if we erase the block which
8b6e50c9 2613 * contains the current cached page.
ace4dfee
TG		 2614 */
2615 if (page <= chip->pagebuf && chip->pagebuf <
2616 (page + pages_per_block))
2617 chip->pagebuf = -1;
1da177e4 2618
ace4dfee 2619 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2620
7bc3312b 2621 status = chip->waitfunc(mtd, chip);
1da177e4 2622
ace4dfee
TG		 2623 /*
2624 * See if operation failed and additional status checks are
2625 * available
2626 */
2627 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2628 status = chip->errstat(mtd, chip, FL_ERASING,
2629 status, page);
068e3c0a 2630
1da177e4 2631 /* See if block erase succeeded */
a4ab4c5d 2632 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2633 pr_debug("%s: failed erase, page 0x%08x\n",
2634 __func__, page);
1da177e4 2635 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2636 instr->fail_addr =
2637 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2638 goto erase_exit;
2639 }
30f464b7 2640
ace4dfee
TG		 2641 /*
2642 * If BBT requires refresh, set the BBT rewrite flag to the
8b6e50c9 2643 * page being erased.
ace4dfee
TG		 2644 */
2645 if (bbt_masked_page != 0xffffffff &&
2646 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2647 rewrite_bbt[chipnr] =
2648 ((loff_t)page << chip->page_shift);
61b03bd7 2649
1da177e4 2650 /* Increment page address and decrement length */
ace4dfee 2651 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2652 page += pages_per_block;
2653
2654 /* Check, if we cross a chip boundary */
ace4dfee 2655 if (len && !(page & chip->pagemask)) {
1da177e4 2656 chipnr++;
ace4dfee
TG		 2657 chip->select_chip(mtd, -1);
2658 chip->select_chip(mtd, chipnr);
30f464b7 2659
ace4dfee
TG		 2660 /*
2661 * If BBT requires refresh and BBT-PERCHIP, set the BBT
8b6e50c9 2662 * page mask to see if this BBT should be rewritten.
ace4dfee
TG		 2663 */
2664 if (bbt_masked_page != 0xffffffff &&
2665 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2666 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2667 BBT_PAGE_MASK;
1da177e4
LT		 2668 }
2669 }
2670 instr->state = MTD_ERASE_DONE;
2671
7351d3a5 2672erase_exit:
1da177e4
LT		 2673
2674 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2675
2676 /* Deselect and wake up anyone waiting on the device */
2677 nand_release_device(mtd);
2678
49defc01
DW		 2679 /* Do call back function */
2680 if (!ret)
2681 mtd_erase_callback(instr);
2682
ace4dfee
TG		 2683 /*
2684 * If BBT requires refresh and erase was successful, rewrite any
8b6e50c9 2685 * selected bad block tables.
ace4dfee
TG		 2686 */
2687 if (bbt_masked_page == 0xffffffff || ret)
2688 return ret;
2689
2690 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2691 if (!rewrite_bbt[chipnr])
2692 continue;
8b6e50c9 2693 /* Update the BBT for chip */
289c0522
BN		 2694 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2695 __func__, chipnr, rewrite_bbt[chipnr],
2696 chip->bbt_td->pages[chipnr]);
ace4dfee 2697 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2698 }
2699
1da177e4
LT		 2700 /* Return more or less happy */
2701 return ret;
2702}
2703
2704/**
2705 * nand_sync - [MTD Interface] sync
8b6e50c9 2706 * @mtd: MTD device structure
1da177e4 2707 *
8b6e50c9 2708 * Sync is actually a wait for chip ready function.
1da177e4 2709 */
e0c7d767 2710static void nand_sync(struct mtd_info *mtd)
1da177e4 2711{
ace4dfee 2712 struct nand_chip *chip = mtd->priv;
1da177e4 2713
289c0522 2714 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2715
2716 /* Grab the lock and see if the device is available */
ace4dfee 2717 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2718 /* Release it and go back */
e0c7d767 2719 nand_release_device(mtd);
1da177e4
LT		 2720}
2721
1da177e4 2722/**
ace4dfee 2723 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2724 * @mtd: MTD device structure
2725 * @offs: offset relative to mtd start
1da177e4 2726 */
ace4dfee 2727static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2728{
ace4dfee 2729 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2730}
2731
2732/**
ace4dfee 2733 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2734 * @mtd: MTD device structure
2735 * @ofs: offset relative to mtd start
1da177e4 2736 */
e0c7d767 2737static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2738{
ace4dfee 2739 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2740 int ret;
2741
f8ac0414
FF		 2742 ret = nand_block_isbad(mtd, ofs);
2743 if (ret) {
8b6e50c9 2744 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2745 if (ret > 0)
2746 return 0;
e0c7d767
DW		 2747 return ret;
2748 }
1da177e4 2749
ace4dfee 2750 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2751}
2752
962034f4
VW		 2753/**
2754 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2755 * @mtd: MTD device structure
962034f4
VW		 2756 */
2757static int nand_suspend(struct mtd_info *mtd)
2758{
ace4dfee 2759 struct nand_chip *chip = mtd->priv;
962034f4 2760
ace4dfee 2761 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2762}
2763
2764/**
2765 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2766 * @mtd: MTD device structure
962034f4
VW		 2767 */
2768static void nand_resume(struct mtd_info *mtd)
2769{
ace4dfee 2770 struct nand_chip *chip = mtd->priv;
962034f4 2771
ace4dfee 2772 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2773 nand_release_device(mtd);
2774 else
d0370219
BN		 2775 pr_err("%s called for a chip which is not in suspended state\n",
2776 __func__);
962034f4
VW		 2777}
2778
8b6e50c9 2779/* Set default functions */
ace4dfee 2780static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2781{
1da177e4 2782 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2783 if (!chip->chip_delay)
2784 chip->chip_delay = 20;
1da177e4
LT		 2785
2786 /* check, if a user supplied command function given */
ace4dfee
TG		 2787 if (chip->cmdfunc == NULL)
2788 chip->cmdfunc = nand_command;
1da177e4
LT		 2789
2790 /* check, if a user supplied wait function given */
ace4dfee
TG		 2791 if (chip->waitfunc == NULL)
2792 chip->waitfunc = nand_wait;
2793
2794 if (!chip->select_chip)
2795 chip->select_chip = nand_select_chip;
2796 if (!chip->read_byte)
2797 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2798 if (!chip->read_word)
2799 chip->read_word = nand_read_word;
2800 if (!chip->block_bad)
2801 chip->block_bad = nand_block_bad;
2802 if (!chip->block_markbad)
2803 chip->block_markbad = nand_default_block_markbad;
2804 if (!chip->write_buf)
2805 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2806 if (!chip->read_buf)
2807 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2808 if (!chip->verify_buf)
2809 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2810 if (!chip->scan_bbt)
2811 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2812
2813 if (!chip->controller) {
2814 chip->controller = &chip->hwcontrol;
2815 spin_lock_init(&chip->controller->lock);
2816 init_waitqueue_head(&chip->controller->wq);
2817 }
2818
7aa65bfd
TG		 2819}
2820
8b6e50c9 2821/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2822static void sanitize_string(uint8_t *s, size_t len)
2823{
2824 ssize_t i;
2825
8b6e50c9 2826 /* Null terminate */
d1e1f4e4
FF		 2827 s[len - 1] = 0;
2828
8b6e50c9 2829 /* Remove non printable chars */
d1e1f4e4
FF		 2830 for (i = 0; i < len - 1; i++) {
2831 if (s[i] < ' ' || s[i] > 127)
2832 s[i] = '?';
2833 }
2834
8b6e50c9 2835 /* Remove trailing spaces */
d1e1f4e4
FF		 2836 strim(s);
2837}
2838
2839static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2840{
2841 int i;
2842 while (len--) {
2843 crc ^= *p++ << 8;
2844 for (i = 0; i < 8; i++)
2845 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2846 }
2847
2848 return crc;
2849}
2850
6fb277ba 2851/*
8b6e50c9 2852 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2853 */
2854static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2855 int *busw)
6fb277ba
FF		 2856{
2857 struct nand_onfi_params *p = &chip->onfi_params;
2858 int i;
2859 int val;
2860
7854d3f7 2861 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2862 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2863 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2864 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2865 return 0;
2866
6fb277ba
FF		 2867 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2868 for (i = 0; i < 3; i++) {
2869 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2870 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2871 le16_to_cpu(p->crc)) {
9a4d4d69 2872 pr_info("ONFI param page %d valid\n", i);
6fb277ba
FF		 2873 break;
2874 }
2875 }
2876
2877 if (i == 3)
2878 return 0;
2879
8b6e50c9 2880 /* Check version */
6fb277ba 2881 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2882 if (val & (1 << 5))
2883 chip->onfi_version = 23;
2884 else if (val & (1 << 4))
6fb277ba
FF		 2885 chip->onfi_version = 22;
2886 else if (val & (1 << 3))
2887 chip->onfi_version = 21;
2888 else if (val & (1 << 2))
2889 chip->onfi_version = 20;
b7b1a29d 2890 else if (val & (1 << 1))
6fb277ba 2891 chip->onfi_version = 10;
b7b1a29d
BN		 2892 else
2893 chip->onfi_version = 0;
2894
2895 if (!chip->onfi_version) {
d0370219 2896 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 2897 return 0;
2898 }
6fb277ba
FF		 2899
2900 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2901 sanitize_string(p->model, sizeof(p->model));
2902 if (!mtd->name)
2903 mtd->name = p->model;
2904 mtd->writesize = le32_to_cpu(p->byte_per_page);
2905 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2906 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
63795755
MC		 2907 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2908 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
08c248fb 2909 *busw = 0;
6fb277ba 2910 if (le16_to_cpu(p->features) & 1)
08c248fb 2911 *busw = NAND_BUSWIDTH_16;
6fb277ba
FF		 2912
2913 chip->options &= ~NAND_CHIPOPTIONS_MSK;
1826dbcc 2914 chip->options |= NAND_NO_READRDY & NAND_CHIPOPTIONS_MSK;
6fb277ba 2915
d42b5de3 2916 pr_info("ONFI flash detected\n");
6fb277ba
FF		 2917 return 1;
2918}
2919
7aa65bfd 2920/*
8b6e50c9 2921 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 2922 */
2923static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2924 struct nand_chip *chip,
7351d3a5
FF		 2925 int busw,
2926 int *maf_id, int *dev_id,
5e81e88a 2927 struct nand_flash_dev *type)
7aa65bfd 2928{
d1e1f4e4 2929 int i, maf_idx;
426c457a 2930 u8 id_data[8];
6fb277ba 2931 int ret;
1da177e4
LT		 2932
2933 /* Select the device */
ace4dfee 2934 chip->select_chip(mtd, 0);
1da177e4 2935
ef89a880
KB		 2936 /*
2937 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 2938 * after power-up.
ef89a880
KB		 2939 */
2940 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2941
1da177e4 2942 /* Send the command for reading device ID */
ace4dfee 2943 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2944
2945 /* Read manufacturer and device IDs */
ace4dfee 2946 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2947 *dev_id = chip->read_byte(mtd);
1da177e4 2948
8b6e50c9
BN		 2949 /*
2950 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 2951 * interface concerns can cause random data which looks like a
2952 * possibly credible NAND flash to appear. If the two results do
2953 * not match, ignore the device completely.
2954 */
2955
2956 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2957
d1e1f4e4 2958 for (i = 0; i < 2; i++)
426c457a 2959 id_data[i] = chip->read_byte(mtd);
ed8165c7 2960
d1e1f4e4 2961 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 2962 pr_info("%s: second ID read did not match "
d0370219
BN		 2963 "%02x,%02x against %02x,%02x\n", __func__,
2964 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2965 return ERR_PTR(-ENODEV);
2966 }
2967
7aa65bfd 2968 if (!type)
5e81e88a
DW		 2969 type = nand_flash_ids;
2970
2971 for (; type->name != NULL; type++)
d1e1f4e4 2972 if (*dev_id == type->id)
f8ac0414 2973 break;
5e81e88a 2974
d1e1f4e4
FF		 2975 chip->onfi_version = 0;
2976 if (!type->name || !type->pagesize) {
6fb277ba 2977 /* Check is chip is ONFI compliant */
08c248fb 2978 ret = nand_flash_detect_onfi(mtd, chip, &busw);
6fb277ba
FF		 2979 if (ret)
2980 goto ident_done;
d1e1f4e4
FF		 2981 }
2982
2983 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2984
2985 /* Read entire ID string */
2986
2987 for (i = 0; i < 8; i++)
2988 id_data[i] = chip->read_byte(mtd);
2989
5e81e88a 2990 if (!type->name)
7aa65bfd
TG		 2991 return ERR_PTR(-ENODEV);
2992
ba0251fe
TG		 2993 if (!mtd->name)
2994 mtd->name = type->name;
2995
69423d99 2996 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 2997
12a40a57 2998 if (!type->pagesize && chip->init_size) {
8b6e50c9 2999 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3000 busw = chip->init_size(mtd, chip, id_data);
3001 } else if (!type->pagesize) {
7aa65bfd 3002 int extid;
29072b96 3003 /* The 3rd id byte holds MLC / multichip data */
426c457a 3004 chip->cellinfo = id_data[2];
7aa65bfd 3005 /* The 4th id byte is the important one */
426c457a 3006 extid = id_data[3];
61b03bd7 3007
426c457a
KC		 3008 /*
3009 * Field definitions are in the following datasheets:
3010 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 3011 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 3012 *
3013 * Check for wraparound + Samsung ID + nonzero 6th byte
3014 * to decide what to do.
3015 */
3016 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3017 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 3018 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 3019 id_data[5] != 0x00) {
3020 /* Calc pagesize */
3021 mtd->writesize = 2048 << (extid & 0x03);
3022 extid >>= 2;
3023 /* Calc oobsize */
34c5bf6c
BN		 3024 switch (extid & 0x03) {
3025 case 1:
3026 mtd->oobsize = 128;
3027 break;
3028 case 2:
3029 mtd->oobsize = 218;
3030 break;
3031 case 3:
3032 mtd->oobsize = 400;
3033 break;
3034 default:
3035 mtd->oobsize = 436;
3036 break;
3037 }
426c457a
KC		 3038 extid >>= 2;
3039 /* Calc blocksize */
3040 mtd->erasesize = (128 * 1024) <<
3041 (((extid >> 1) & 0x04) | (extid & 0x03));
3042 busw = 0;
3043 } else {
3044 /* Calc pagesize */
3045 mtd->writesize = 1024 << (extid & 0x03);
3046 extid >>= 2;
3047 /* Calc oobsize */
3048 mtd->oobsize = (8 << (extid & 0x01)) *
3049 (mtd->writesize >> 9);
3050 extid >>= 2;
3051 /* Calc blocksize. Blocksize is multiples of 64KiB */
3052 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3053 extid >>= 2;
3054 /* Get buswidth information */
3055 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3056 }
7aa65bfd
TG		 3057 } else {
3058 /*
8b6e50c9 3059 * Old devices have chip data hardcoded in the device id table.
7aa65bfd 3060 */
ba0251fe
TG		 3061 mtd->erasesize = type->erasesize;
3062 mtd->writesize = type->pagesize;
4cbb9b80 3063 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3064 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3065
3066 /*
3067 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3068 * some Spansion chips have erasesize that conflicts with size
8b6e50c9 3069 * listed in nand_ids table.
2173bae8
BN		 3070 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3071 */
3072 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3073 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3074 id_data[7] == 0x00 && mtd->writesize == 512) {
3075 mtd->erasesize = 128 * 1024;
3076 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3077 }
7aa65bfd 3078 }
d1e1f4e4
FF		 3079 /* Get chip options, preserve non chip based options */
3080 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3081 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3082
8b6e50c9
BN		 3083 /*
3084 * Check if chip is not a Samsung device. Do not clear the
3085 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3086 */
3087 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3088 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3089ident_done:
3090
7aa65bfd 3091 /* Try to identify manufacturer */
9a909867 3092 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3093 if (nand_manuf_ids[maf_idx].id == *maf_id)
3094 break;
3095 }
0ea4a755 3096
7aa65bfd
TG		 3097 /*
3098 * Check, if buswidth is correct. Hardware drivers should set
8b6e50c9 3099 * chip correct!
7aa65bfd 3100 */
ace4dfee 3101 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
9a4d4d69 3102 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 3103 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3104 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 3105 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 3106 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3107 busw ? 16 : 8);
7aa65bfd
TG		 3108 return ERR_PTR(-EINVAL);
3109 }
61b03bd7 3110
7aa65bfd 3111 /* Calculate the address shift from the page size */
ace4dfee 3112 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3113 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3114 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3115
ace4dfee 3116 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3117 ffs(mtd->erasesize) - 1;
69423d99
AH		 3118 if (chip->chipsize & 0xffffffff)
3119 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3120 else {
3121 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3122 chip->chip_shift += 32 - 1;
3123 }
1da177e4 3124
26d9be11
AB		 3125 chip->badblockbits = 8;
3126
7aa65bfd 3127 /* Set the bad block position */
065a1ed8 3128 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3129 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3130 else
3131 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3132
b60b08b0
KC		 3133 /*
3134 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3135 * on Samsung and Hynix MLC devices; stored in first two pages
3136 * of each block on Micron devices with 2KiB pages and on
8c342335
BN		 3137 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
3138 * All others scan only the first page.
b60b08b0
KC		 3139 */
3140 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3141 (*maf_id == NAND_MFR_SAMSUNG ||
3142 *maf_id == NAND_MFR_HYNIX))
5fb1549d 3143 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3144 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3145 (*maf_id == NAND_MFR_SAMSUNG ||
3146 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3147 *maf_id == NAND_MFR_TOSHIBA ||
8c342335
BN		 3148 *maf_id == NAND_MFR_AMD ||
3149 *maf_id == NAND_MFR_MACRONIX)) ||
c7b28e25
BN		 3150 (mtd->writesize == 2048 &&
3151 *maf_id == NAND_MFR_MICRON))
5fb1549d 3152 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
c7b28e25 3153
7aa65bfd 3154 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3155 if (chip->options & NAND_4PAGE_ARRAY)
3156 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3157 else
ace4dfee 3158 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3159
8b6e50c9 3160 /* Do not replace user supplied command function! */
ace4dfee
TG		 3161 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3162 chip->cmdfunc = nand_command_lp;
7aa65bfd 3163
886bd33d
HS		 3164 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3165 " page size: %d, OOB size: %d\n",
3166 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3167 chip->onfi_version ? chip->onfi_params.model : type->name,
3168 mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3169
3170 return type;
3171}
3172
7aa65bfd 3173/**
3b85c321 3174 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3175 * @mtd: MTD device structure
3176 * @maxchips: number of chips to scan for
3177 * @table: alternative NAND ID table
7aa65bfd 3178 *
8b6e50c9
BN		 3179 * This is the first phase of the normal nand_scan() function. It reads the
3180 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3181 *
3b85c321 3182 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3183 */
5e81e88a
DW		 3184int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3185 struct nand_flash_dev *table)
7aa65bfd 3186{
d1e1f4e4 3187 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3188 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3189 struct nand_flash_dev *type;
3190
7aa65bfd 3191 /* Get buswidth to select the correct functions */
ace4dfee 3192 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3193 /* Set the default functions */
ace4dfee 3194 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3195
3196 /* Read the flash type */
7351d3a5
FF		 3197 type = nand_get_flash_type(mtd, chip, busw,
3198 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3199
3200 if (IS_ERR(type)) {
b1c6e6db 3201 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3202 pr_warn("No NAND device found\n");
ace4dfee 3203 chip->select_chip(mtd, -1);
7aa65bfd 3204 return PTR_ERR(type);
1da177e4
LT		 3205 }
3206
7aa65bfd 3207 /* Check for a chip array */
e0c7d767 3208 for (i = 1; i < maxchips; i++) {
ace4dfee 3209 chip->select_chip(mtd, i);
ef89a880
KB		 3210 /* See comment in nand_get_flash_type for reset */
3211 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3212 /* Send the command for reading device ID */
ace4dfee 3213 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3214 /* Read manufacturer and device IDs */
ace4dfee 3215 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3216 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3217 break;
3218 }
3219 if (i > 1)
9a4d4d69 3220 pr_info("%d NAND chips detected\n", i);
61b03bd7 3221
1da177e4 3222 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3223 chip->numchips = i;
3224 mtd->size = i * chip->chipsize;
7aa65bfd 3225
3b85c321
DW		 3226 return 0;
3227}
7351d3a5 3228EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3229
3230
3231/**
3232 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3233 * @mtd: MTD device structure
3b85c321 3234 *
8b6e50c9
BN		 3235 * This is the second phase of the normal nand_scan() function. It fills out
3236 * all the uninitialized function pointers with the defaults and scans for a
3237 * bad block table if appropriate.
3b85c321
DW		 3238 */
3239int nand_scan_tail(struct mtd_info *mtd)
3240{
3241 int i;
3242 struct nand_chip *chip = mtd->priv;
3243
e2414f4c
BN		 3244 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3245 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3246 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3247
4bf63fcb
DW		 3248 if (!(chip->options & NAND_OWN_BUFFERS))
3249 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3250 if (!chip->buffers)
3251 return -ENOMEM;
3252
7dcdcbef 3253 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3254 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3255
7aa65bfd 3256 /*
8b6e50c9 3257 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3258 */
193bd400 3259 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3260 switch (mtd->oobsize) {
1da177e4 3261 case 8:
5bd34c09 3262 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3263 break;
3264 case 16:
5bd34c09 3265 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3266 break;
3267 case 64:
5bd34c09 3268 chip->ecc.layout = &nand_oob_64;
1da177e4 3269 break;
81ec5364
TG		 3270 case 128:
3271 chip->ecc.layout = &nand_oob_128;
3272 break;
1da177e4 3273 default:
d0370219
BN		 3274 pr_warn("No oob scheme defined for oobsize %d\n",
3275 mtd->oobsize);
1da177e4
LT		 3276 BUG();
3277 }
3278 }
61b03bd7 3279
956e944c
DW		 3280 if (!chip->write_page)
3281 chip->write_page = nand_write_page;
3282
61b03bd7 3283 /*
8b6e50c9 3284 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3285 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3286 */
956e944c 3287
ace4dfee 3288 switch (chip->ecc.mode) {
6e0cb135
SN		 3289 case NAND_ECC_HW_OOB_FIRST:
3290 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3291 if (!chip->ecc.calculate || !chip->ecc.correct ||
3292 !chip->ecc.hwctl) {
9a4d4d69 3293 pr_warn("No ECC functions supplied; "
d0370219 3294 "hardware ECC not possible\n");
6e0cb135
SN		 3295 BUG();
3296 }
3297 if (!chip->ecc.read_page)
3298 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3299
6dfc6d25 3300 case NAND_ECC_HW:
8b6e50c9 3301 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3302 if (!chip->ecc.read_page)
3303 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3304 if (!chip->ecc.write_page)
3305 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3306 if (!chip->ecc.read_page_raw)
3307 chip->ecc.read_page_raw = nand_read_page_raw;
3308 if (!chip->ecc.write_page_raw)
3309 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3310 if (!chip->ecc.read_oob)
3311 chip->ecc.read_oob = nand_read_oob_std;
3312 if (!chip->ecc.write_oob)
3313 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3314
6dfc6d25 3315 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3316 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3317 !chip->ecc.hwctl) &&
3318 (!chip->ecc.read_page ||
1c45f604 3319 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3320 !chip->ecc.write_page ||
1c45f604 3321 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 3322 pr_warn("No ECC functions supplied; "
d0370219 3323 "hardware ECC not possible\n");
6dfc6d25
TG		 3324 BUG();
3325 }
8b6e50c9 3326 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3327 if (!chip->ecc.read_page)
3328 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3329 if (!chip->ecc.write_page)
3330 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3331 if (!chip->ecc.read_page_raw)
3332 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3333 if (!chip->ecc.write_page_raw)
3334 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3335 if (!chip->ecc.read_oob)
3336 chip->ecc.read_oob = nand_read_oob_syndrome;
3337 if (!chip->ecc.write_oob)
3338 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3339
e2788c98
MD		 3340 if (mtd->writesize >= chip->ecc.size) {
3341 if (!chip->ecc.strength) {
3342 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3343 BUG();
3344 }
6dfc6d25 3345 break;
e2788c98 3346 }
9a4d4d69 3347 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 3348 "%d byte page size, fallback to SW ECC\n",
3349 chip->ecc.size, mtd->writesize);
ace4dfee 3350 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3351
6dfc6d25 3352 case NAND_ECC_SOFT:
ace4dfee
TG		 3353 chip->ecc.calculate = nand_calculate_ecc;
3354 chip->ecc.correct = nand_correct_data;
f5bbdacc 3355 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3356 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3357 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3358 chip->ecc.read_page_raw = nand_read_page_raw;
3359 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3360 chip->ecc.read_oob = nand_read_oob_std;
3361 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3362 if (!chip->ecc.size)
3363 chip->ecc.size = 256;
ace4dfee 3364 chip->ecc.bytes = 3;
6a918bad 3365 chip->ecc.strength = 1;
1da177e4 3366 break;
61b03bd7 3367
193bd400
ID		 3368 case NAND_ECC_SOFT_BCH:
3369 if (!mtd_nand_has_bch()) {
9a4d4d69 3370 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3371 BUG();
3372 }
3373 chip->ecc.calculate = nand_bch_calculate_ecc;
3374 chip->ecc.correct = nand_bch_correct_data;
3375 chip->ecc.read_page = nand_read_page_swecc;
3376 chip->ecc.read_subpage = nand_read_subpage;
3377 chip->ecc.write_page = nand_write_page_swecc;
3378 chip->ecc.read_page_raw = nand_read_page_raw;
3379 chip->ecc.write_page_raw = nand_write_page_raw;
3380 chip->ecc.read_oob = nand_read_oob_std;
3381 chip->ecc.write_oob = nand_write_oob_std;
3382 /*
3383 * Board driver should supply ecc.size and ecc.bytes values to
3384 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3385 * for details. Otherwise, default to 4 bits for large page
3386 * devices.
193bd400
ID		 3387 */
3388 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3389 chip->ecc.size = 512;
3390 chip->ecc.bytes = 7;
3391 }
3392 chip->ecc.priv = nand_bch_init(mtd,
3393 chip->ecc.size,
3394 chip->ecc.bytes,
3395 &chip->ecc.layout);
3396 if (!chip->ecc.priv) {
9a4d4d69 3397 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3398 BUG();
3399 }
6a918bad 3400 chip->ecc.strength =
e2788c98 3401 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
193bd400
ID		 3402 break;
3403
61b03bd7 3404 case NAND_ECC_NONE:
9a4d4d69 3405 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3406 "This is not recommended!\n");
8593fbc6
TG		 3407 chip->ecc.read_page = nand_read_page_raw;
3408 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3409 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3410 chip->ecc.read_page_raw = nand_read_page_raw;
3411 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3412 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3413 chip->ecc.size = mtd->writesize;
3414 chip->ecc.bytes = 0;
6a918bad 3415 chip->ecc.strength = 0;
1da177e4 3416 break;
956e944c 3417
1da177e4 3418 default:
d0370219 3419 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 3420 BUG();
1da177e4 3421 }
61b03bd7 3422
9ce244b3 3423 /* For many systems, the standard OOB write also works for raw */
c46f6483
BN		 3424 if (!chip->ecc.read_oob_raw)
3425 chip->ecc.read_oob_raw = chip->ecc.read_oob;
9ce244b3
BN		 3426 if (!chip->ecc.write_oob_raw)
3427 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3428
5bd34c09
TG		 3429 /*
3430 * The number of bytes available for a client to place data into
8b6e50c9 3431 * the out of band area.
5bd34c09
TG		 3432 */
3433 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3434 for (i = 0; chip->ecc.layout->oobfree[i].length
3435 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3436 chip->ecc.layout->oobavail +=
3437 chip->ecc.layout->oobfree[i].length;
1f92267c 3438 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3439
7aa65bfd
TG		 3440 /*
3441 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3442 * mode.
7aa65bfd 3443 */
ace4dfee 3444 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3445 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 3446 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3447 BUG();
1da177e4 3448 }
f5bbdacc 3449 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3450
8b6e50c9 3451 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 3452 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3453 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3454 switch (chip->ecc.steps) {
29072b96
TG		 3455 case 2:
3456 mtd->subpage_sft = 1;
3457 break;
3458 case 4:
3459 case 8:
81ec5364 3460 case 16:
29072b96
TG		 3461 mtd->subpage_sft = 2;
3462 break;
3463 }
3464 }
3465 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3466
04bbd0ea 3467 /* Initialize state */
ace4dfee 3468 chip->state = FL_READY;
1da177e4
LT		 3469
3470 /* De-select the device */
ace4dfee 3471 chip->select_chip(mtd, -1);
1da177e4
LT		 3472
3473 /* Invalidate the pagebuffer reference */
ace4dfee 3474 chip->pagebuf = -1;
1da177e4
LT		 3475
3476 /* Fill in remaining MTD driver data */
3477 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3478 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3479 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 3480 mtd->_erase = nand_erase;
3481 mtd->_point = NULL;
3482 mtd->_unpoint = NULL;
3483 mtd->_read = nand_read;
3484 mtd->_write = nand_write;
3485 mtd->_panic_write = panic_nand_write;
3486 mtd->_read_oob = nand_read_oob;
3487 mtd->_write_oob = nand_write_oob;
3488 mtd->_sync = nand_sync;
3489 mtd->_lock = NULL;
3490 mtd->_unlock = NULL;
3491 mtd->_suspend = nand_suspend;
3492 mtd->_resume = nand_resume;
3493 mtd->_block_isbad = nand_block_isbad;
3494 mtd->_block_markbad = nand_block_markbad;
cbcab65a 3495 mtd->writebufsize = mtd->writesize;
1da177e4 3496
6a918bad 3497 /* propagate ecc info to mtd_info */
5bd34c09 3498 mtd->ecclayout = chip->ecc.layout;
86c2072b 3499 mtd->ecc_strength = chip->ecc.strength;
1da177e4 3500
0040bf38 3501 /* Check, if we should skip the bad block table scan */
ace4dfee 3502 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3503 return 0;
1da177e4
LT		 3504
3505 /* Build bad block table */
ace4dfee 3506 return chip->scan_bbt(mtd);
1da177e4 3507}
7351d3a5 3508EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3509
8b6e50c9
BN		 3510/*
3511 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3512 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3513 * to call us from in-kernel code if the core NAND support is modular.
3514 */
3b85c321
DW		 3515#ifdef MODULE
3516#define caller_is_module() (1)
3517#else
3518#define caller_is_module() \
a6e6abd5 3519 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3520#endif
3521
3522/**
3523 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3524 * @mtd: MTD device structure
3525 * @maxchips: number of chips to scan for
3b85c321 3526 *
8b6e50c9
BN		 3527 * This fills out all the uninitialized function pointers with the defaults.
3528 * The flash ID is read and the mtd/chip structures are filled with the
3529 * appropriate values. The mtd->owner field must be set to the module of the
3530 * caller.
3b85c321
DW		 3531 */
3532int nand_scan(struct mtd_info *mtd, int maxchips)
3533{
3534 int ret;
3535
3536 /* Many callers got this wrong, so check for it for a while... */
3537 if (!mtd->owner && caller_is_module()) {
d0370219 3538 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3539 BUG();
3540 }
3541
5e81e88a 3542 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3543 if (!ret)
3544 ret = nand_scan_tail(mtd);
3545 return ret;
3546}
7351d3a5 3547EXPORT_SYMBOL(nand_scan);
3b85c321 3548
1da177e4 3549/**
61b03bd7 3550 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3551 * @mtd: MTD device structure
3552 */
e0c7d767 3553void nand_release(struct mtd_info *mtd)
1da177e4 3554{
ace4dfee 3555 struct nand_chip *chip = mtd->priv;
1da177e4 3556
193bd400
ID		 3557 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3558 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3559
5ffcaf3d 3560 mtd_device_unregister(mtd);
1da177e4 3561
fa671646 3562 /* Free bad block table memory */
ace4dfee 3563 kfree(chip->bbt);
4bf63fcb
DW		 3564 if (!(chip->options & NAND_OWN_BUFFERS))
3565 kfree(chip->buffers);
58373ff0
BN		 3566
3567 /* Free bad block descriptor memory */
3568 if (chip->badblock_pattern && chip->badblock_pattern->options
3569 & NAND_BBT_DYNAMICSTRUCT)
3570 kfree(chip->badblock_pattern);
1da177e4 3571}
e0c7d767 3572EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3573
3574static int __init nand_base_init(void)
3575{
3576 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3577 return 0;
3578}
3579
3580static void __exit nand_base_exit(void)
3581{
3582 led_trigger_unregister_simple(nand_led_trigger);
3583}
3584
3585module_init(nand_base_init);
3586module_exit(nand_base_exit);
3587
e0c7d767 3588MODULE_LICENSE("GPL");
7351d3a5
FF		 3589MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3590MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3591MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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