Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Additional technical information is available on |
8b2b403c | 10 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 24 | * if we have HW ECC support. |
1da177e4 LT |
25 | * The AG-AND chips have nice features for speed improvement, |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
c0b8ba7b | 27 | * BBT table is not serialized, has to be fixed |
1da177e4 | 28 | * |
1da177e4 LT |
29 | * This program is free software; you can redistribute it and/or modify |
30 | * it under the terms of the GNU General Public License version 2 as | |
31 | * published by the Free Software Foundation. | |
32 | * | |
33 | */ | |
34 | ||
552d9205 | 35 | #include <linux/module.h> |
1da177e4 LT |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
7aa65bfd | 38 | #include <linux/err.h> |
1da177e4 LT |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 45 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
46 | #include <linux/interrupt.h> |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
7351d3a5 | 49 | #include <linux/io.h> |
1da177e4 | 50 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
51 | |
52 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 53 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
54 | .eccbytes = 3, |
55 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
56 | .oobfree = { |
57 | {.offset = 3, | |
58 | .length = 2}, | |
59 | {.offset = 6, | |
f8ac0414 | 60 | .length = 2} } |
1da177e4 LT |
61 | }; |
62 | ||
5bd34c09 | 63 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
64 | .eccbytes = 6, |
65 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
66 | .oobfree = { |
67 | {.offset = 8, | |
f8ac0414 | 68 | . length = 8} } |
1da177e4 LT |
69 | }; |
70 | ||
5bd34c09 | 71 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
72 | .eccbytes = 24, |
73 | .eccpos = { | |
e0c7d767 DW |
74 | 40, 41, 42, 43, 44, 45, 46, 47, |
75 | 48, 49, 50, 51, 52, 53, 54, 55, | |
76 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
77 | .oobfree = { |
78 | {.offset = 2, | |
f8ac0414 | 79 | .length = 38} } |
1da177e4 LT |
80 | }; |
81 | ||
81ec5364 TG |
82 | static struct nand_ecclayout nand_oob_128 = { |
83 | .eccbytes = 48, | |
84 | .eccpos = { | |
85 | 80, 81, 82, 83, 84, 85, 86, 87, | |
86 | 88, 89, 90, 91, 92, 93, 94, 95, | |
87 | 96, 97, 98, 99, 100, 101, 102, 103, | |
88 | 104, 105, 106, 107, 108, 109, 110, 111, | |
89 | 112, 113, 114, 115, 116, 117, 118, 119, | |
90 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
91 | .oobfree = { | |
92 | {.offset = 2, | |
f8ac0414 | 93 | .length = 78} } |
81ec5364 TG |
94 | }; |
95 | ||
6a8214aa | 96 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
1da177e4 | 97 | |
8593fbc6 TG |
98 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
99 | struct mtd_oob_ops *ops); | |
100 | ||
d470a97c | 101 | /* |
8e87d782 | 102 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
103 | * compiled away when LED support is disabled. |
104 | */ | |
105 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
106 | ||
6fe5a6ac VS |
107 | static int check_offs_len(struct mtd_info *mtd, |
108 | loff_t ofs, uint64_t len) | |
109 | { | |
110 | struct nand_chip *chip = mtd->priv; | |
111 | int ret = 0; | |
112 | ||
113 | /* Start address must align on block boundary */ | |
114 | if (ofs & ((1 << chip->phys_erase_shift) - 1)) { | |
289c0522 | 115 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
116 | ret = -EINVAL; |
117 | } | |
118 | ||
119 | /* Length must align on block boundary */ | |
120 | if (len & ((1 << chip->phys_erase_shift) - 1)) { | |
289c0522 | 121 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
122 | ret = -EINVAL; |
123 | } | |
124 | ||
6fe5a6ac VS |
125 | return ret; |
126 | } | |
127 | ||
1da177e4 LT |
128 | /** |
129 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 130 | * @mtd: MTD device structure |
61b03bd7 | 131 | * |
b0bb6903 | 132 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 133 | */ |
e0c7d767 | 134 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 135 | { |
ace4dfee | 136 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 137 | |
a36ed299 | 138 | /* Release the controller and the chip */ |
ace4dfee TG |
139 | spin_lock(&chip->controller->lock); |
140 | chip->controller->active = NULL; | |
141 | chip->state = FL_READY; | |
142 | wake_up(&chip->controller->wq); | |
143 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
144 | } |
145 | ||
146 | /** | |
147 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 148 | * @mtd: MTD device structure |
1da177e4 | 149 | * |
7854d3f7 | 150 | * Default read function for 8bit buswidth |
1da177e4 | 151 | */ |
58dd8f2b | 152 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 153 | { |
ace4dfee TG |
154 | struct nand_chip *chip = mtd->priv; |
155 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
156 | } |
157 | ||
1da177e4 | 158 | /** |
064a7694 | 159 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
7854d3f7 | 160 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 161 | * @mtd: MTD device structure |
1da177e4 | 162 | * |
7854d3f7 BN |
163 | * Default read function for 16bit buswidth with endianness conversion. |
164 | * | |
1da177e4 | 165 | */ |
58dd8f2b | 166 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 167 | { |
ace4dfee TG |
168 | struct nand_chip *chip = mtd->priv; |
169 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
170 | } |
171 | ||
1da177e4 LT |
172 | /** |
173 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 174 | * @mtd: MTD device structure |
1da177e4 | 175 | * |
7854d3f7 | 176 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
177 | */ |
178 | static u16 nand_read_word(struct mtd_info *mtd) | |
179 | { | |
ace4dfee TG |
180 | struct nand_chip *chip = mtd->priv; |
181 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
182 | } |
183 | ||
1da177e4 LT |
184 | /** |
185 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
186 | * @mtd: MTD device structure |
187 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
188 | * |
189 | * Default select function for 1 chip devices. | |
190 | */ | |
ace4dfee | 191 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 192 | { |
ace4dfee TG |
193 | struct nand_chip *chip = mtd->priv; |
194 | ||
195 | switch (chipnr) { | |
1da177e4 | 196 | case -1: |
ace4dfee | 197 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
198 | break; |
199 | case 0: | |
1da177e4 LT |
200 | break; |
201 | ||
202 | default: | |
203 | BUG(); | |
204 | } | |
205 | } | |
206 | ||
207 | /** | |
208 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
209 | * @mtd: MTD device structure |
210 | * @buf: data buffer | |
211 | * @len: number of bytes to write | |
1da177e4 | 212 | * |
7854d3f7 | 213 | * Default write function for 8bit buswidth. |
1da177e4 | 214 | */ |
58dd8f2b | 215 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
216 | { |
217 | int i; | |
ace4dfee | 218 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 219 | |
e0c7d767 | 220 | for (i = 0; i < len; i++) |
ace4dfee | 221 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
222 | } |
223 | ||
224 | /** | |
61b03bd7 | 225 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
226 | * @mtd: MTD device structure |
227 | * @buf: buffer to store date | |
228 | * @len: number of bytes to read | |
1da177e4 | 229 | * |
7854d3f7 | 230 | * Default read function for 8bit buswidth. |
1da177e4 | 231 | */ |
58dd8f2b | 232 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
233 | { |
234 | int i; | |
ace4dfee | 235 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 236 | |
e0c7d767 | 237 | for (i = 0; i < len; i++) |
ace4dfee | 238 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
239 | } |
240 | ||
1da177e4 LT |
241 | /** |
242 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
243 | * @mtd: MTD device structure |
244 | * @buf: data buffer | |
245 | * @len: number of bytes to write | |
1da177e4 | 246 | * |
7854d3f7 | 247 | * Default write function for 16bit buswidth. |
1da177e4 | 248 | */ |
58dd8f2b | 249 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
250 | { |
251 | int i; | |
ace4dfee | 252 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
253 | u16 *p = (u16 *) buf; |
254 | len >>= 1; | |
61b03bd7 | 255 | |
e0c7d767 | 256 | for (i = 0; i < len; i++) |
ace4dfee | 257 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 258 | |
1da177e4 LT |
259 | } |
260 | ||
261 | /** | |
61b03bd7 | 262 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
263 | * @mtd: MTD device structure |
264 | * @buf: buffer to store date | |
265 | * @len: number of bytes to read | |
1da177e4 | 266 | * |
7854d3f7 | 267 | * Default read function for 16bit buswidth. |
1da177e4 | 268 | */ |
58dd8f2b | 269 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
270 | { |
271 | int i; | |
ace4dfee | 272 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
273 | u16 *p = (u16 *) buf; |
274 | len >>= 1; | |
275 | ||
e0c7d767 | 276 | for (i = 0; i < len; i++) |
ace4dfee | 277 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
278 | } |
279 | ||
1da177e4 LT |
280 | /** |
281 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
282 | * @mtd: MTD device structure |
283 | * @ofs: offset from device start | |
284 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 285 | * |
61b03bd7 | 286 | * Check, if the block is bad. |
1da177e4 LT |
287 | */ |
288 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
289 | { | |
cdbec050 | 290 | int page, chipnr, res = 0, i = 0; |
ace4dfee | 291 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
292 | u16 bad; |
293 | ||
5fb1549d | 294 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
295 | ofs += mtd->erasesize - mtd->writesize; |
296 | ||
1a12f46a TK |
297 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
298 | ||
1da177e4 | 299 | if (getchip) { |
ace4dfee | 300 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 301 | |
6a8214aa | 302 | nand_get_device(mtd, FL_READING); |
1da177e4 LT |
303 | |
304 | /* Select the NAND device */ | |
ace4dfee | 305 | chip->select_chip(mtd, chipnr); |
1a12f46a | 306 | } |
1da177e4 | 307 | |
cdbec050 BN |
308 | do { |
309 | if (chip->options & NAND_BUSWIDTH_16) { | |
310 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
311 | chip->badblockpos & 0xFE, page); | |
312 | bad = cpu_to_le16(chip->read_word(mtd)); | |
313 | if (chip->badblockpos & 0x1) | |
314 | bad >>= 8; | |
315 | else | |
316 | bad &= 0xFF; | |
317 | } else { | |
318 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
319 | page); | |
320 | bad = chip->read_byte(mtd); | |
321 | } | |
322 | ||
323 | if (likely(chip->badblockbits == 8)) | |
324 | res = bad != 0xFF; | |
e0b58d0a | 325 | else |
cdbec050 BN |
326 | res = hweight8(bad) < chip->badblockbits; |
327 | ofs += mtd->writesize; | |
328 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
329 | i++; | |
330 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 331 | |
b0bb6903 HS |
332 | if (getchip) { |
333 | chip->select_chip(mtd, -1); | |
1da177e4 | 334 | nand_release_device(mtd); |
b0bb6903 | 335 | } |
61b03bd7 | 336 | |
1da177e4 LT |
337 | return res; |
338 | } | |
339 | ||
340 | /** | |
341 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
8b6e50c9 BN |
342 | * @mtd: MTD device structure |
343 | * @ofs: offset from device start | |
1da177e4 | 344 | * |
8b6e50c9 | 345 | * This is the default implementation, which can be overridden by a hardware |
e2414f4c BN |
346 | * specific driver. We try operations in the following order, according to our |
347 | * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH): | |
348 | * (1) erase the affected block, to allow OOB marker to be written cleanly | |
349 | * (2) update in-memory BBT | |
350 | * (3) write bad block marker to OOB area of affected block | |
351 | * (4) update flash-based BBT | |
352 | * Note that we retain the first error encountered in (3) or (4), finish the | |
353 | * procedures, and dump the error in the end. | |
1da177e4 LT |
354 | */ |
355 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
356 | { | |
ace4dfee | 357 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 358 | uint8_t buf[2] = { 0, 0 }; |
e2414f4c BN |
359 | int block, res, ret = 0, i = 0; |
360 | int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM); | |
61b03bd7 | 361 | |
e2414f4c | 362 | if (write_oob) { |
00918429 BN |
363 | struct erase_info einfo; |
364 | ||
365 | /* Attempt erase before marking OOB */ | |
366 | memset(&einfo, 0, sizeof(einfo)); | |
367 | einfo.mtd = mtd; | |
368 | einfo.addr = ofs; | |
369 | einfo.len = 1 << chip->phys_erase_shift; | |
370 | nand_erase_nand(mtd, &einfo, 0); | |
371 | } | |
372 | ||
1da177e4 | 373 | /* Get block number */ |
4226b510 | 374 | block = (int)(ofs >> chip->bbt_erase_shift); |
e2414f4c | 375 | /* Mark block bad in memory-based BBT */ |
ace4dfee TG |
376 | if (chip->bbt) |
377 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 | 378 | |
e2414f4c BN |
379 | /* Write bad block marker to OOB */ |
380 | if (write_oob) { | |
4a89ff88 | 381 | struct mtd_oob_ops ops; |
df698621 | 382 | loff_t wr_ofs = ofs; |
4a89ff88 | 383 | |
6a8214aa | 384 | nand_get_device(mtd, FL_WRITING); |
f1a28c02 | 385 | |
4a89ff88 BN |
386 | ops.datbuf = NULL; |
387 | ops.oobbuf = buf; | |
85443319 BN |
388 | ops.ooboffs = chip->badblockpos; |
389 | if (chip->options & NAND_BUSWIDTH_16) { | |
390 | ops.ooboffs &= ~0x01; | |
391 | ops.len = ops.ooblen = 2; | |
392 | } else { | |
393 | ops.len = ops.ooblen = 1; | |
394 | } | |
23b1a99b | 395 | ops.mode = MTD_OPS_PLACE_OOB; |
df698621 | 396 | |
e2414f4c | 397 | /* Write to first/last page(s) if necessary */ |
df698621 BN |
398 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
399 | wr_ofs += mtd->erasesize - mtd->writesize; | |
02ed70bb | 400 | do { |
e2414f4c BN |
401 | res = nand_do_write_oob(mtd, wr_ofs, &ops); |
402 | if (!ret) | |
403 | ret = res; | |
02ed70bb | 404 | |
02ed70bb | 405 | i++; |
df698621 | 406 | wr_ofs += mtd->writesize; |
e2414f4c | 407 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); |
02ed70bb | 408 | |
c0b8ba7b | 409 | nand_release_device(mtd); |
f1a28c02 | 410 | } |
e2414f4c BN |
411 | |
412 | /* Update flash-based bad block table */ | |
413 | if (chip->bbt_options & NAND_BBT_USE_FLASH) { | |
414 | res = nand_update_bbt(mtd, ofs); | |
415 | if (!ret) | |
416 | ret = res; | |
417 | } | |
418 | ||
f1a28c02 TG |
419 | if (!ret) |
420 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 421 | |
f1a28c02 | 422 | return ret; |
1da177e4 LT |
423 | } |
424 | ||
61b03bd7 | 425 | /** |
1da177e4 | 426 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 427 | * @mtd: MTD device structure |
1da177e4 | 428 | * |
8b6e50c9 BN |
429 | * Check, if the device is write protected. The function expects, that the |
430 | * device is already selected. | |
1da177e4 | 431 | */ |
e0c7d767 | 432 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 433 | { |
ace4dfee | 434 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 435 | |
8b6e50c9 | 436 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
437 | if (chip->options & NAND_BROKEN_XD) |
438 | return 0; | |
439 | ||
1da177e4 | 440 | /* Check the WP bit */ |
ace4dfee TG |
441 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
442 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
443 | } |
444 | ||
445 | /** | |
446 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
447 | * @mtd: MTD device structure |
448 | * @ofs: offset from device start | |
449 | * @getchip: 0, if the chip is already selected | |
450 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
451 | * |
452 | * Check, if the block is bad. Either by reading the bad block table or | |
453 | * calling of the scan function. | |
454 | */ | |
2c0a2bed TG |
455 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
456 | int allowbbt) | |
1da177e4 | 457 | { |
ace4dfee | 458 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 459 | |
ace4dfee TG |
460 | if (!chip->bbt) |
461 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 462 | |
1da177e4 | 463 | /* Return info from the table */ |
e0c7d767 | 464 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
465 | } |
466 | ||
2af7c653 SK |
467 | /** |
468 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
469 | * @mtd: MTD device structure |
470 | * @timeo: Timeout | |
2af7c653 SK |
471 | * |
472 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
473 | * context. | |
474 | */ | |
475 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
476 | { | |
477 | struct nand_chip *chip = mtd->priv; | |
478 | int i; | |
479 | ||
480 | /* Wait for the device to get ready */ | |
481 | for (i = 0; i < timeo; i++) { | |
482 | if (chip->dev_ready(mtd)) | |
483 | break; | |
484 | touch_softlockup_watchdog(); | |
485 | mdelay(1); | |
486 | } | |
487 | } | |
488 | ||
7854d3f7 | 489 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 490 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 491 | { |
ace4dfee | 492 | struct nand_chip *chip = mtd->priv; |
ca6a2489 | 493 | unsigned long timeo = jiffies + msecs_to_jiffies(20); |
3b88775c | 494 | |
2af7c653 SK |
495 | /* 400ms timeout */ |
496 | if (in_interrupt() || oops_in_progress) | |
497 | return panic_nand_wait_ready(mtd, 400); | |
498 | ||
8fe833c1 | 499 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 500 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 501 | do { |
ace4dfee | 502 | if (chip->dev_ready(mtd)) |
8fe833c1 | 503 | break; |
8446f1d3 | 504 | touch_softlockup_watchdog(); |
61b03bd7 | 505 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 506 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 507 | } |
4b648b02 | 508 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 509 | |
1da177e4 LT |
510 | /** |
511 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
512 | * @mtd: MTD device structure |
513 | * @command: the command to be sent | |
514 | * @column: the column address for this command, -1 if none | |
515 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 516 | * |
8b6e50c9 BN |
517 | * Send command to NAND device. This function is used for small page devices |
518 | * (256/512 Bytes per page). | |
1da177e4 | 519 | */ |
7abd3ef9 TG |
520 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
521 | int column, int page_addr) | |
1da177e4 | 522 | { |
ace4dfee | 523 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 524 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 525 | |
8b6e50c9 | 526 | /* Write out the command to the device */ |
1da177e4 LT |
527 | if (command == NAND_CMD_SEQIN) { |
528 | int readcmd; | |
529 | ||
28318776 | 530 | if (column >= mtd->writesize) { |
1da177e4 | 531 | /* OOB area */ |
28318776 | 532 | column -= mtd->writesize; |
1da177e4 LT |
533 | readcmd = NAND_CMD_READOOB; |
534 | } else if (column < 256) { | |
535 | /* First 256 bytes --> READ0 */ | |
536 | readcmd = NAND_CMD_READ0; | |
537 | } else { | |
538 | column -= 256; | |
539 | readcmd = NAND_CMD_READ1; | |
540 | } | |
ace4dfee | 541 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 542 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 543 | } |
ace4dfee | 544 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 545 | |
8b6e50c9 | 546 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
547 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
548 | /* Serially input address */ | |
549 | if (column != -1) { | |
550 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 551 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 552 | column >>= 1; |
ace4dfee | 553 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
554 | ctrl &= ~NAND_CTRL_CHANGE; |
555 | } | |
556 | if (page_addr != -1) { | |
ace4dfee | 557 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 558 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 559 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 560 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
561 | if (chip->chipsize > (32 << 20)) |
562 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 563 | } |
ace4dfee | 564 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
565 | |
566 | /* | |
8b6e50c9 BN |
567 | * Program and erase have their own busy handlers status and sequential |
568 | * in needs no delay | |
e0c7d767 | 569 | */ |
1da177e4 | 570 | switch (command) { |
61b03bd7 | 571 | |
1da177e4 LT |
572 | case NAND_CMD_PAGEPROG: |
573 | case NAND_CMD_ERASE1: | |
574 | case NAND_CMD_ERASE2: | |
575 | case NAND_CMD_SEQIN: | |
576 | case NAND_CMD_STATUS: | |
577 | return; | |
578 | ||
579 | case NAND_CMD_RESET: | |
ace4dfee | 580 | if (chip->dev_ready) |
1da177e4 | 581 | break; |
ace4dfee TG |
582 | udelay(chip->chip_delay); |
583 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 584 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
585 | chip->cmd_ctrl(mtd, |
586 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
587 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
588 | ; | |
1da177e4 LT |
589 | return; |
590 | ||
e0c7d767 | 591 | /* This applies to read commands */ |
1da177e4 | 592 | default: |
61b03bd7 | 593 | /* |
1da177e4 LT |
594 | * If we don't have access to the busy pin, we apply the given |
595 | * command delay | |
e0c7d767 | 596 | */ |
ace4dfee TG |
597 | if (!chip->dev_ready) { |
598 | udelay(chip->chip_delay); | |
1da177e4 | 599 | return; |
61b03bd7 | 600 | } |
1da177e4 | 601 | } |
8b6e50c9 BN |
602 | /* |
603 | * Apply this short delay always to ensure that we do wait tWB in | |
604 | * any case on any machine. | |
605 | */ | |
e0c7d767 | 606 | ndelay(100); |
3b88775c TG |
607 | |
608 | nand_wait_ready(mtd); | |
1da177e4 LT |
609 | } |
610 | ||
611 | /** | |
612 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
613 | * @mtd: MTD device structure |
614 | * @command: the command to be sent | |
615 | * @column: the column address for this command, -1 if none | |
616 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 617 | * |
7abd3ef9 | 618 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
619 | * devices. We don't have the separate regions as we have in the small page |
620 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 621 | */ |
7abd3ef9 TG |
622 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
623 | int column, int page_addr) | |
1da177e4 | 624 | { |
ace4dfee | 625 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
626 | |
627 | /* Emulate NAND_CMD_READOOB */ | |
628 | if (command == NAND_CMD_READOOB) { | |
28318776 | 629 | column += mtd->writesize; |
1da177e4 LT |
630 | command = NAND_CMD_READ0; |
631 | } | |
61b03bd7 | 632 | |
7abd3ef9 | 633 | /* Command latch cycle */ |
ace4dfee | 634 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 635 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
636 | |
637 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 638 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
639 | |
640 | /* Serially input address */ | |
641 | if (column != -1) { | |
642 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 643 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 644 | column >>= 1; |
ace4dfee | 645 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 646 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 647 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 648 | } |
1da177e4 | 649 | if (page_addr != -1) { |
ace4dfee TG |
650 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
651 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 652 | NAND_NCE | NAND_ALE); |
1da177e4 | 653 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
654 | if (chip->chipsize > (128 << 20)) |
655 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 656 | NAND_NCE | NAND_ALE); |
1da177e4 | 657 | } |
1da177e4 | 658 | } |
ace4dfee | 659 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
660 | |
661 | /* | |
8b6e50c9 BN |
662 | * Program and erase have their own busy handlers status, sequential |
663 | * in, and deplete1 need no delay. | |
30f464b7 | 664 | */ |
1da177e4 | 665 | switch (command) { |
61b03bd7 | 666 | |
1da177e4 LT |
667 | case NAND_CMD_CACHEDPROG: |
668 | case NAND_CMD_PAGEPROG: | |
669 | case NAND_CMD_ERASE1: | |
670 | case NAND_CMD_ERASE2: | |
671 | case NAND_CMD_SEQIN: | |
7bc3312b | 672 | case NAND_CMD_RNDIN: |
1da177e4 | 673 | case NAND_CMD_STATUS: |
30f464b7 | 674 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
675 | return; |
676 | ||
30f464b7 DM |
677 | case NAND_CMD_STATUS_ERROR: |
678 | case NAND_CMD_STATUS_ERROR0: | |
679 | case NAND_CMD_STATUS_ERROR1: | |
680 | case NAND_CMD_STATUS_ERROR2: | |
681 | case NAND_CMD_STATUS_ERROR3: | |
8b6e50c9 | 682 | /* Read error status commands require only a short delay */ |
ace4dfee | 683 | udelay(chip->chip_delay); |
30f464b7 | 684 | return; |
1da177e4 LT |
685 | |
686 | case NAND_CMD_RESET: | |
ace4dfee | 687 | if (chip->dev_ready) |
1da177e4 | 688 | break; |
ace4dfee | 689 | udelay(chip->chip_delay); |
12efdde3 TG |
690 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
691 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
692 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
693 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
694 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
695 | ; | |
1da177e4 LT |
696 | return; |
697 | ||
7bc3312b TG |
698 | case NAND_CMD_RNDOUT: |
699 | /* No ready / busy check necessary */ | |
700 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
701 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
702 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
703 | NAND_NCE | NAND_CTRL_CHANGE); | |
704 | return; | |
705 | ||
1da177e4 | 706 | case NAND_CMD_READ0: |
12efdde3 TG |
707 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
708 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
709 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
710 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 711 | |
e0c7d767 | 712 | /* This applies to read commands */ |
1da177e4 | 713 | default: |
61b03bd7 | 714 | /* |
1da177e4 | 715 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 716 | * command delay. |
e0c7d767 | 717 | */ |
ace4dfee TG |
718 | if (!chip->dev_ready) { |
719 | udelay(chip->chip_delay); | |
1da177e4 | 720 | return; |
61b03bd7 | 721 | } |
1da177e4 | 722 | } |
3b88775c | 723 | |
8b6e50c9 BN |
724 | /* |
725 | * Apply this short delay always to ensure that we do wait tWB in | |
726 | * any case on any machine. | |
727 | */ | |
e0c7d767 | 728 | ndelay(100); |
3b88775c TG |
729 | |
730 | nand_wait_ready(mtd); | |
1da177e4 LT |
731 | } |
732 | ||
2af7c653 SK |
733 | /** |
734 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
735 | * @chip: the nand chip descriptor |
736 | * @mtd: MTD device structure | |
737 | * @new_state: the state which is requested | |
2af7c653 SK |
738 | * |
739 | * Used when in panic, no locks are taken. | |
740 | */ | |
741 | static void panic_nand_get_device(struct nand_chip *chip, | |
742 | struct mtd_info *mtd, int new_state) | |
743 | { | |
7854d3f7 | 744 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
745 | chip->controller->active = chip; |
746 | chip->state = new_state; | |
747 | } | |
748 | ||
1da177e4 LT |
749 | /** |
750 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
751 | * @mtd: MTD device structure |
752 | * @new_state: the state which is requested | |
1da177e4 LT |
753 | * |
754 | * Get the device and lock it for exclusive access | |
755 | */ | |
2c0a2bed | 756 | static int |
6a8214aa | 757 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 758 | { |
6a8214aa | 759 | struct nand_chip *chip = mtd->priv; |
ace4dfee TG |
760 | spinlock_t *lock = &chip->controller->lock; |
761 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 762 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 763 | retry: |
0dfc6246 TG |
764 | spin_lock(lock); |
765 | ||
b8b3ee9a | 766 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
767 | if (!chip->controller->active) |
768 | chip->controller->active = chip; | |
a36ed299 | 769 | |
ace4dfee TG |
770 | if (chip->controller->active == chip && chip->state == FL_READY) { |
771 | chip->state = new_state; | |
0dfc6246 | 772 | spin_unlock(lock); |
962034f4 VW |
773 | return 0; |
774 | } | |
775 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
776 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
777 | chip->state = FL_PM_SUSPENDED; | |
778 | spin_unlock(lock); | |
779 | return 0; | |
6b0d9a84 | 780 | } |
0dfc6246 TG |
781 | } |
782 | set_current_state(TASK_UNINTERRUPTIBLE); | |
783 | add_wait_queue(wq, &wait); | |
784 | spin_unlock(lock); | |
785 | schedule(); | |
786 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
787 | goto retry; |
788 | } | |
789 | ||
2af7c653 | 790 | /** |
8b6e50c9 BN |
791 | * panic_nand_wait - [GENERIC] wait until the command is done |
792 | * @mtd: MTD device structure | |
793 | * @chip: NAND chip structure | |
794 | * @timeo: timeout | |
2af7c653 SK |
795 | * |
796 | * Wait for command done. This is a helper function for nand_wait used when | |
797 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 798 | * an oops through mtdoops. |
2af7c653 SK |
799 | */ |
800 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
801 | unsigned long timeo) | |
802 | { | |
803 | int i; | |
804 | for (i = 0; i < timeo; i++) { | |
805 | if (chip->dev_ready) { | |
806 | if (chip->dev_ready(mtd)) | |
807 | break; | |
808 | } else { | |
809 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
810 | break; | |
811 | } | |
812 | mdelay(1); | |
f8ac0414 | 813 | } |
2af7c653 SK |
814 | } |
815 | ||
1da177e4 | 816 | /** |
8b6e50c9 BN |
817 | * nand_wait - [DEFAULT] wait until the command is done |
818 | * @mtd: MTD device structure | |
819 | * @chip: NAND chip structure | |
1da177e4 | 820 | * |
8b6e50c9 BN |
821 | * Wait for command done. This applies to erase and program only. Erase can |
822 | * take up to 400ms and program up to 20ms according to general NAND and | |
823 | * SmartMedia specs. | |
844d3b42 | 824 | */ |
7bc3312b | 825 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
826 | { |
827 | ||
e0c7d767 | 828 | unsigned long timeo = jiffies; |
7bc3312b | 829 | int status, state = chip->state; |
61b03bd7 | 830 | |
1da177e4 | 831 | if (state == FL_ERASING) |
e0c7d767 | 832 | timeo += (HZ * 400) / 1000; |
1da177e4 | 833 | else |
e0c7d767 | 834 | timeo += (HZ * 20) / 1000; |
1da177e4 | 835 | |
8fe833c1 RP |
836 | led_trigger_event(nand_led_trigger, LED_FULL); |
837 | ||
8b6e50c9 BN |
838 | /* |
839 | * Apply this short delay always to ensure that we do wait tWB in any | |
840 | * case on any machine. | |
841 | */ | |
e0c7d767 | 842 | ndelay(100); |
1da177e4 | 843 | |
ace4dfee TG |
844 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
845 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 846 | else |
ace4dfee | 847 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 848 | |
2af7c653 SK |
849 | if (in_interrupt() || oops_in_progress) |
850 | panic_nand_wait(mtd, chip, timeo); | |
851 | else { | |
852 | while (time_before(jiffies, timeo)) { | |
853 | if (chip->dev_ready) { | |
854 | if (chip->dev_ready(mtd)) | |
855 | break; | |
856 | } else { | |
857 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
858 | break; | |
859 | } | |
860 | cond_resched(); | |
1da177e4 | 861 | } |
1da177e4 | 862 | } |
8fe833c1 RP |
863 | led_trigger_event(nand_led_trigger, LED_OFF); |
864 | ||
ace4dfee | 865 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
866 | /* This can happen if in case of timeout or buggy dev_ready */ |
867 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
868 | return status; |
869 | } | |
870 | ||
7d70f334 | 871 | /** |
b6d676db | 872 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
873 | * @mtd: mtd info |
874 | * @ofs: offset to start unlock from | |
875 | * @len: length to unlock | |
8b6e50c9 BN |
876 | * @invert: when = 0, unlock the range of blocks within the lower and |
877 | * upper boundary address | |
878 | * when = 1, unlock the range of blocks outside the boundaries | |
879 | * of the lower and upper boundary address | |
7d70f334 | 880 | * |
8b6e50c9 | 881 | * Returs unlock status. |
7d70f334 VS |
882 | */ |
883 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
884 | uint64_t len, int invert) | |
885 | { | |
886 | int ret = 0; | |
887 | int status, page; | |
888 | struct nand_chip *chip = mtd->priv; | |
889 | ||
890 | /* Submit address of first page to unlock */ | |
891 | page = ofs >> chip->page_shift; | |
892 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
893 | ||
894 | /* Submit address of last page to unlock */ | |
895 | page = (ofs + len) >> chip->page_shift; | |
896 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
897 | (page | invert) & chip->pagemask); | |
898 | ||
899 | /* Call wait ready function */ | |
900 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 901 | /* See if device thinks it succeeded */ |
74830966 | 902 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 903 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
904 | __func__, status); |
905 | ret = -EIO; | |
906 | } | |
907 | ||
908 | return ret; | |
909 | } | |
910 | ||
911 | /** | |
b6d676db | 912 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
913 | * @mtd: mtd info |
914 | * @ofs: offset to start unlock from | |
915 | * @len: length to unlock | |
7d70f334 | 916 | * |
8b6e50c9 | 917 | * Returns unlock status. |
7d70f334 VS |
918 | */ |
919 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
920 | { | |
921 | int ret = 0; | |
922 | int chipnr; | |
923 | struct nand_chip *chip = mtd->priv; | |
924 | ||
289c0522 | 925 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
926 | __func__, (unsigned long long)ofs, len); |
927 | ||
928 | if (check_offs_len(mtd, ofs, len)) | |
929 | ret = -EINVAL; | |
930 | ||
931 | /* Align to last block address if size addresses end of the device */ | |
932 | if (ofs + len == mtd->size) | |
933 | len -= mtd->erasesize; | |
934 | ||
6a8214aa | 935 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
936 | |
937 | /* Shift to get chip number */ | |
938 | chipnr = ofs >> chip->chip_shift; | |
939 | ||
940 | chip->select_chip(mtd, chipnr); | |
941 | ||
942 | /* Check, if it is write protected */ | |
943 | if (nand_check_wp(mtd)) { | |
289c0522 | 944 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
945 | __func__); |
946 | ret = -EIO; | |
947 | goto out; | |
948 | } | |
949 | ||
950 | ret = __nand_unlock(mtd, ofs, len, 0); | |
951 | ||
952 | out: | |
b0bb6903 | 953 | chip->select_chip(mtd, -1); |
7d70f334 VS |
954 | nand_release_device(mtd); |
955 | ||
956 | return ret; | |
957 | } | |
7351d3a5 | 958 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
959 | |
960 | /** | |
b6d676db | 961 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
962 | * @mtd: mtd info |
963 | * @ofs: offset to start unlock from | |
964 | * @len: length to unlock | |
7d70f334 | 965 | * |
8b6e50c9 BN |
966 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
967 | * have this feature, but it allows only to lock all blocks, not for specified | |
968 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
969 | * now. | |
7d70f334 | 970 | * |
8b6e50c9 | 971 | * Returns lock status. |
7d70f334 VS |
972 | */ |
973 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
974 | { | |
975 | int ret = 0; | |
976 | int chipnr, status, page; | |
977 | struct nand_chip *chip = mtd->priv; | |
978 | ||
289c0522 | 979 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
980 | __func__, (unsigned long long)ofs, len); |
981 | ||
982 | if (check_offs_len(mtd, ofs, len)) | |
983 | ret = -EINVAL; | |
984 | ||
6a8214aa | 985 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
986 | |
987 | /* Shift to get chip number */ | |
988 | chipnr = ofs >> chip->chip_shift; | |
989 | ||
990 | chip->select_chip(mtd, chipnr); | |
991 | ||
992 | /* Check, if it is write protected */ | |
993 | if (nand_check_wp(mtd)) { | |
289c0522 | 994 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
995 | __func__); |
996 | status = MTD_ERASE_FAILED; | |
997 | ret = -EIO; | |
998 | goto out; | |
999 | } | |
1000 | ||
1001 | /* Submit address of first page to lock */ | |
1002 | page = ofs >> chip->page_shift; | |
1003 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1004 | ||
1005 | /* Call wait ready function */ | |
1006 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1007 | /* See if device thinks it succeeded */ |
74830966 | 1008 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1009 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1010 | __func__, status); |
1011 | ret = -EIO; | |
1012 | goto out; | |
1013 | } | |
1014 | ||
1015 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1016 | ||
1017 | out: | |
b0bb6903 | 1018 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1019 | nand_release_device(mtd); |
1020 | ||
1021 | return ret; | |
1022 | } | |
7351d3a5 | 1023 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1024 | |
8593fbc6 | 1025 | /** |
7854d3f7 | 1026 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1027 | * @mtd: mtd info structure |
1028 | * @chip: nand chip info structure | |
1029 | * @buf: buffer to store read data | |
1fbb938d | 1030 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1031 | * @page: page number to read |
52ff49df | 1032 | * |
7854d3f7 | 1033 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1034 | */ |
1035 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1036 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1037 | { |
1038 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1039 | if (oob_required) |
1040 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1041 | return 0; |
1042 | } | |
1043 | ||
52ff49df | 1044 | /** |
7854d3f7 | 1045 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1046 | * @mtd: mtd info structure |
1047 | * @chip: nand chip info structure | |
1048 | * @buf: buffer to store read data | |
1fbb938d | 1049 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1050 | * @page: page number to read |
52ff49df DB |
1051 | * |
1052 | * We need a special oob layout and handling even when OOB isn't used. | |
1053 | */ | |
7351d3a5 | 1054 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1055 | struct nand_chip *chip, uint8_t *buf, |
1056 | int oob_required, int page) | |
52ff49df DB |
1057 | { |
1058 | int eccsize = chip->ecc.size; | |
1059 | int eccbytes = chip->ecc.bytes; | |
1060 | uint8_t *oob = chip->oob_poi; | |
1061 | int steps, size; | |
1062 | ||
1063 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1064 | chip->read_buf(mtd, buf, eccsize); | |
1065 | buf += eccsize; | |
1066 | ||
1067 | if (chip->ecc.prepad) { | |
1068 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1069 | oob += chip->ecc.prepad; | |
1070 | } | |
1071 | ||
1072 | chip->read_buf(mtd, oob, eccbytes); | |
1073 | oob += eccbytes; | |
1074 | ||
1075 | if (chip->ecc.postpad) { | |
1076 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1077 | oob += chip->ecc.postpad; | |
1078 | } | |
1079 | } | |
1080 | ||
1081 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1082 | if (size) | |
1083 | chip->read_buf(mtd, oob, size); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1da177e4 | 1088 | /** |
7854d3f7 | 1089 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1090 | * @mtd: mtd info structure |
1091 | * @chip: nand chip info structure | |
1092 | * @buf: buffer to store read data | |
1fbb938d | 1093 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1094 | * @page: page number to read |
068e3c0a | 1095 | */ |
f5bbdacc | 1096 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1097 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1098 | { |
f5bbdacc TG |
1099 | int i, eccsize = chip->ecc.size; |
1100 | int eccbytes = chip->ecc.bytes; | |
1101 | int eccsteps = chip->ecc.steps; | |
1102 | uint8_t *p = buf; | |
4bf63fcb DW |
1103 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1104 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1105 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1106 | unsigned int max_bitflips = 0; |
f5bbdacc | 1107 | |
1fbb938d | 1108 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1109 | |
1110 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1111 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1112 | ||
1113 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1114 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1115 | |
1116 | eccsteps = chip->ecc.steps; | |
1117 | p = buf; | |
1118 | ||
1119 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1120 | int stat; | |
1121 | ||
1122 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1123 | if (stat < 0) { |
f5bbdacc | 1124 | mtd->ecc_stats.failed++; |
3f91e94f | 1125 | } else { |
f5bbdacc | 1126 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1127 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1128 | } | |
f5bbdacc | 1129 | } |
3f91e94f | 1130 | return max_bitflips; |
22c60f5f | 1131 | } |
1da177e4 | 1132 | |
3d459559 | 1133 | /** |
7854d3f7 | 1134 | * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function |
8b6e50c9 BN |
1135 | * @mtd: mtd info structure |
1136 | * @chip: nand chip info structure | |
1137 | * @data_offs: offset of requested data within the page | |
1138 | * @readlen: data length | |
1139 | * @bufpoi: buffer to store read data | |
3d459559 | 1140 | */ |
7351d3a5 FF |
1141 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
1142 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) | |
3d459559 AK |
1143 | { |
1144 | int start_step, end_step, num_steps; | |
1145 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1146 | uint8_t *p; | |
1147 | int data_col_addr, i, gaps = 0; | |
1148 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1149 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
7351d3a5 | 1150 | int index = 0; |
3f91e94f | 1151 | unsigned int max_bitflips = 0; |
3d459559 | 1152 | |
7854d3f7 | 1153 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1154 | start_step = data_offs / chip->ecc.size; |
1155 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1156 | num_steps = end_step - start_step + 1; | |
1157 | ||
8b6e50c9 | 1158 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1159 | datafrag_len = num_steps * chip->ecc.size; |
1160 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1161 | ||
1162 | data_col_addr = start_step * chip->ecc.size; | |
1163 | /* If we read not a page aligned data */ | |
1164 | if (data_col_addr != 0) | |
1165 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1166 | ||
1167 | p = bufpoi + data_col_addr; | |
1168 | chip->read_buf(mtd, p, datafrag_len); | |
1169 | ||
8b6e50c9 | 1170 | /* Calculate ECC */ |
3d459559 AK |
1171 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1172 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1173 | ||
8b6e50c9 BN |
1174 | /* |
1175 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1176 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1177 | */ |
3d459559 AK |
1178 | for (i = 0; i < eccfrag_len - 1; i++) { |
1179 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1180 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1181 | gaps = 1; | |
1182 | break; | |
1183 | } | |
1184 | } | |
1185 | if (gaps) { | |
1186 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1187 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1188 | } else { | |
8b6e50c9 | 1189 | /* |
7854d3f7 | 1190 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1191 | * about buswidth alignment in read_buf. |
1192 | */ | |
7351d3a5 FF |
1193 | index = start_step * chip->ecc.bytes; |
1194 | ||
1195 | aligned_pos = eccpos[index] & ~(busw - 1); | |
3d459559 | 1196 | aligned_len = eccfrag_len; |
7351d3a5 | 1197 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1198 | aligned_len++; |
7351d3a5 | 1199 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1200 | aligned_len++; |
1201 | ||
7351d3a5 FF |
1202 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1203 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1204 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1205 | } | |
1206 | ||
1207 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1208 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1209 | |
1210 | p = bufpoi + data_col_addr; | |
1211 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1212 | int stat; | |
1213 | ||
7351d3a5 FF |
1214 | stat = chip->ecc.correct(mtd, p, |
1215 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
3f91e94f | 1216 | if (stat < 0) { |
3d459559 | 1217 | mtd->ecc_stats.failed++; |
3f91e94f | 1218 | } else { |
3d459559 | 1219 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1220 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1221 | } | |
3d459559 | 1222 | } |
3f91e94f | 1223 | return max_bitflips; |
3d459559 AK |
1224 | } |
1225 | ||
068e3c0a | 1226 | /** |
7854d3f7 | 1227 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1228 | * @mtd: mtd info structure |
1229 | * @chip: nand chip info structure | |
1230 | * @buf: buffer to store read data | |
1fbb938d | 1231 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1232 | * @page: page number to read |
068e3c0a | 1233 | * |
7854d3f7 | 1234 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1235 | */ |
f5bbdacc | 1236 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1237 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1238 | { |
f5bbdacc TG |
1239 | int i, eccsize = chip->ecc.size; |
1240 | int eccbytes = chip->ecc.bytes; | |
1241 | int eccsteps = chip->ecc.steps; | |
1242 | uint8_t *p = buf; | |
4bf63fcb DW |
1243 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1244 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1245 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1246 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1247 | |
1248 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1249 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1250 | chip->read_buf(mtd, p, eccsize); | |
1251 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1252 | } |
f75e5097 | 1253 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1254 | |
f5bbdacc | 1255 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1256 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1257 | |
f5bbdacc TG |
1258 | eccsteps = chip->ecc.steps; |
1259 | p = buf; | |
61b03bd7 | 1260 | |
f5bbdacc TG |
1261 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1262 | int stat; | |
1da177e4 | 1263 | |
f5bbdacc | 1264 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
3f91e94f | 1265 | if (stat < 0) { |
f5bbdacc | 1266 | mtd->ecc_stats.failed++; |
3f91e94f | 1267 | } else { |
f5bbdacc | 1268 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1269 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1270 | } | |
f5bbdacc | 1271 | } |
3f91e94f | 1272 | return max_bitflips; |
f5bbdacc | 1273 | } |
1da177e4 | 1274 | |
6e0cb135 | 1275 | /** |
7854d3f7 | 1276 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1277 | * @mtd: mtd info structure |
1278 | * @chip: nand chip info structure | |
1279 | * @buf: buffer to store read data | |
1fbb938d | 1280 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1281 | * @page: page number to read |
6e0cb135 | 1282 | * |
8b6e50c9 BN |
1283 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1284 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1285 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1286 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1287 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1288 | */ |
1289 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1290 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1291 | { |
1292 | int i, eccsize = chip->ecc.size; | |
1293 | int eccbytes = chip->ecc.bytes; | |
1294 | int eccsteps = chip->ecc.steps; | |
1295 | uint8_t *p = buf; | |
1296 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1297 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1298 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1299 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1300 | |
1301 | /* Read the OOB area first */ | |
1302 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1303 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1304 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1305 | ||
1306 | for (i = 0; i < chip->ecc.total; i++) | |
1307 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1308 | ||
1309 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1310 | int stat; | |
1311 | ||
1312 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1313 | chip->read_buf(mtd, p, eccsize); | |
1314 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1315 | ||
1316 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
3f91e94f | 1317 | if (stat < 0) { |
6e0cb135 | 1318 | mtd->ecc_stats.failed++; |
3f91e94f | 1319 | } else { |
6e0cb135 | 1320 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1321 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1322 | } | |
6e0cb135 | 1323 | } |
3f91e94f | 1324 | return max_bitflips; |
6e0cb135 SN |
1325 | } |
1326 | ||
f5bbdacc | 1327 | /** |
7854d3f7 | 1328 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1329 | * @mtd: mtd info structure |
1330 | * @chip: nand chip info structure | |
1331 | * @buf: buffer to store read data | |
1fbb938d | 1332 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1333 | * @page: page number to read |
f5bbdacc | 1334 | * |
8b6e50c9 BN |
1335 | * The hw generator calculates the error syndrome automatically. Therefore we |
1336 | * need a special oob layout and handling. | |
f5bbdacc TG |
1337 | */ |
1338 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1339 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1340 | { |
1341 | int i, eccsize = chip->ecc.size; | |
1342 | int eccbytes = chip->ecc.bytes; | |
1343 | int eccsteps = chip->ecc.steps; | |
1344 | uint8_t *p = buf; | |
f75e5097 | 1345 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1346 | unsigned int max_bitflips = 0; |
1da177e4 | 1347 | |
f5bbdacc TG |
1348 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1349 | int stat; | |
61b03bd7 | 1350 | |
f5bbdacc TG |
1351 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1352 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1353 | |
f5bbdacc TG |
1354 | if (chip->ecc.prepad) { |
1355 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1356 | oob += chip->ecc.prepad; | |
1357 | } | |
1da177e4 | 1358 | |
f5bbdacc TG |
1359 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1360 | chip->read_buf(mtd, oob, eccbytes); | |
1361 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1362 | |
3f91e94f | 1363 | if (stat < 0) { |
f5bbdacc | 1364 | mtd->ecc_stats.failed++; |
3f91e94f | 1365 | } else { |
f5bbdacc | 1366 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1367 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1368 | } | |
61b03bd7 | 1369 | |
f5bbdacc | 1370 | oob += eccbytes; |
1da177e4 | 1371 | |
f5bbdacc TG |
1372 | if (chip->ecc.postpad) { |
1373 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1374 | oob += chip->ecc.postpad; | |
61b03bd7 | 1375 | } |
f5bbdacc | 1376 | } |
1da177e4 | 1377 | |
f5bbdacc | 1378 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1379 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1380 | if (i) |
1381 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1382 | |
3f91e94f | 1383 | return max_bitflips; |
f5bbdacc | 1384 | } |
1da177e4 | 1385 | |
f5bbdacc | 1386 | /** |
7854d3f7 | 1387 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1388 | * @chip: nand chip structure |
1389 | * @oob: oob destination address | |
1390 | * @ops: oob ops structure | |
1391 | * @len: size of oob to transfer | |
8593fbc6 TG |
1392 | */ |
1393 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1394 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1395 | { |
f8ac0414 | 1396 | switch (ops->mode) { |
8593fbc6 | 1397 | |
0612b9dd BN |
1398 | case MTD_OPS_PLACE_OOB: |
1399 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1400 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1401 | return oob + len; | |
1402 | ||
0612b9dd | 1403 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1404 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1405 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1406 | size_t bytes = 0; | |
8593fbc6 | 1407 | |
f8ac0414 | 1408 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1409 | /* Read request not from offset 0? */ |
7bc3312b TG |
1410 | if (unlikely(roffs)) { |
1411 | if (roffs >= free->length) { | |
1412 | roffs -= free->length; | |
1413 | continue; | |
1414 | } | |
1415 | boffs = free->offset + roffs; | |
1416 | bytes = min_t(size_t, len, | |
1417 | (free->length - roffs)); | |
1418 | roffs = 0; | |
1419 | } else { | |
1420 | bytes = min_t(size_t, len, free->length); | |
1421 | boffs = free->offset; | |
1422 | } | |
1423 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1424 | oob += bytes; |
1425 | } | |
1426 | return oob; | |
1427 | } | |
1428 | default: | |
1429 | BUG(); | |
1430 | } | |
1431 | return NULL; | |
1432 | } | |
1433 | ||
1434 | /** | |
7854d3f7 | 1435 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1436 | * @mtd: MTD device structure |
1437 | * @from: offset to read from | |
1438 | * @ops: oob ops structure | |
f5bbdacc TG |
1439 | * |
1440 | * Internal function. Called with chip held. | |
1441 | */ | |
8593fbc6 TG |
1442 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1443 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1444 | { |
e47f3db4 | 1445 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
f5bbdacc TG |
1446 | struct nand_chip *chip = mtd->priv; |
1447 | struct mtd_ecc_stats stats; | |
f5bbdacc | 1448 | int ret = 0; |
8593fbc6 | 1449 | uint32_t readlen = ops->len; |
7014568b | 1450 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1451 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1452 | mtd->oobavail : mtd->oobsize; |
1453 | ||
8593fbc6 | 1454 | uint8_t *bufpoi, *oob, *buf; |
edbc4540 | 1455 | unsigned int max_bitflips = 0; |
1da177e4 | 1456 | |
f5bbdacc | 1457 | stats = mtd->ecc_stats; |
1da177e4 | 1458 | |
f5bbdacc TG |
1459 | chipnr = (int)(from >> chip->chip_shift); |
1460 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1461 | |
f5bbdacc TG |
1462 | realpage = (int)(from >> chip->page_shift); |
1463 | page = realpage & chip->pagemask; | |
1da177e4 | 1464 | |
f5bbdacc | 1465 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1466 | |
8593fbc6 TG |
1467 | buf = ops->datbuf; |
1468 | oob = ops->oobbuf; | |
e47f3db4 | 1469 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1470 | |
f8ac0414 | 1471 | while (1) { |
f5bbdacc TG |
1472 | bytes = min(mtd->writesize - col, readlen); |
1473 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1474 | |
8b6e50c9 | 1475 | /* Is the current page in the buffer? */ |
8593fbc6 | 1476 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1477 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1478 | |
c00a0991 | 1479 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1480 | |
edbc4540 MD |
1481 | /* |
1482 | * Now read the page into the buffer. Absent an error, | |
1483 | * the read methods return max bitflips per ecc step. | |
1484 | */ | |
0612b9dd | 1485 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1486 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1487 | oob_required, |
1488 | page); | |
a5ff4f10 JW |
1489 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1490 | !oob) | |
7351d3a5 FF |
1491 | ret = chip->ecc.read_subpage(mtd, chip, |
1492 | col, bytes, bufpoi); | |
956e944c | 1493 | else |
46a8cf2d | 1494 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1495 | oob_required, page); |
6d77b9d0 BN |
1496 | if (ret < 0) { |
1497 | if (!aligned) | |
1498 | /* Invalidate page cache */ | |
1499 | chip->pagebuf = -1; | |
1da177e4 | 1500 | break; |
6d77b9d0 | 1501 | } |
f5bbdacc | 1502 | |
edbc4540 MD |
1503 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1504 | ||
f5bbdacc TG |
1505 | /* Transfer not aligned data */ |
1506 | if (!aligned) { | |
a5ff4f10 | 1507 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
6d77b9d0 | 1508 | !(mtd->ecc_stats.failed - stats.failed) && |
edbc4540 | 1509 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1510 | chip->pagebuf = realpage; |
edbc4540 MD |
1511 | chip->pagebuf_bitflips = ret; |
1512 | } else { | |
6d77b9d0 BN |
1513 | /* Invalidate page cache */ |
1514 | chip->pagebuf = -1; | |
edbc4540 | 1515 | } |
4bf63fcb | 1516 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1517 | } |
1518 | ||
8593fbc6 TG |
1519 | buf += bytes; |
1520 | ||
1521 | if (unlikely(oob)) { | |
b64d39d8 ML |
1522 | int toread = min(oobreadlen, max_oobsize); |
1523 | ||
1524 | if (toread) { | |
1525 | oob = nand_transfer_oob(chip, | |
1526 | oob, ops, toread); | |
1527 | oobreadlen -= toread; | |
1528 | } | |
8593fbc6 | 1529 | } |
8593fbc6 | 1530 | } else { |
4bf63fcb | 1531 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1532 | buf += bytes; |
edbc4540 MD |
1533 | max_bitflips = max_t(unsigned int, max_bitflips, |
1534 | chip->pagebuf_bitflips); | |
8593fbc6 | 1535 | } |
1da177e4 | 1536 | |
f5bbdacc | 1537 | readlen -= bytes; |
61b03bd7 | 1538 | |
f5bbdacc | 1539 | if (!readlen) |
61b03bd7 | 1540 | break; |
1da177e4 | 1541 | |
8b6e50c9 | 1542 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1543 | col = 0; |
1544 | /* Increment page address */ | |
1545 | realpage++; | |
1546 | ||
ace4dfee | 1547 | page = realpage & chip->pagemask; |
1da177e4 LT |
1548 | /* Check, if we cross a chip boundary */ |
1549 | if (!page) { | |
1550 | chipnr++; | |
ace4dfee TG |
1551 | chip->select_chip(mtd, -1); |
1552 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1553 | } |
1da177e4 | 1554 | } |
b0bb6903 | 1555 | chip->select_chip(mtd, -1); |
1da177e4 | 1556 | |
8593fbc6 | 1557 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1558 | if (oob) |
1559 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1560 | |
3f91e94f | 1561 | if (ret < 0) |
f5bbdacc TG |
1562 | return ret; |
1563 | ||
9a1fcdfd TG |
1564 | if (mtd->ecc_stats.failed - stats.failed) |
1565 | return -EBADMSG; | |
1566 | ||
edbc4540 | 1567 | return max_bitflips; |
f5bbdacc TG |
1568 | } |
1569 | ||
1570 | /** | |
25985edc | 1571 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1572 | * @mtd: MTD device structure |
1573 | * @from: offset to read from | |
1574 | * @len: number of bytes to read | |
1575 | * @retlen: pointer to variable to store the number of read bytes | |
1576 | * @buf: the databuffer to put data | |
f5bbdacc | 1577 | * |
8b6e50c9 | 1578 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1579 | */ |
1580 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1581 | size_t *retlen, uint8_t *buf) | |
1582 | { | |
4a89ff88 | 1583 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1584 | int ret; |
1585 | ||
6a8214aa | 1586 | nand_get_device(mtd, FL_READING); |
4a89ff88 BN |
1587 | ops.len = len; |
1588 | ops.datbuf = buf; | |
1589 | ops.oobbuf = NULL; | |
11041ae6 | 1590 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1591 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1592 | *retlen = ops.retlen; |
f5bbdacc | 1593 | nand_release_device(mtd); |
f5bbdacc | 1594 | return ret; |
1da177e4 LT |
1595 | } |
1596 | ||
7bc3312b | 1597 | /** |
7854d3f7 | 1598 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1599 | * @mtd: mtd info structure |
1600 | * @chip: nand chip info structure | |
1601 | * @page: page number to read | |
7bc3312b TG |
1602 | */ |
1603 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1604 | int page) |
7bc3312b | 1605 | { |
5c2ffb11 | 1606 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1607 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1608 | return 0; |
7bc3312b TG |
1609 | } |
1610 | ||
1611 | /** | |
7854d3f7 | 1612 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1613 | * with syndromes |
8b6e50c9 BN |
1614 | * @mtd: mtd info structure |
1615 | * @chip: nand chip info structure | |
1616 | * @page: page number to read | |
7bc3312b TG |
1617 | */ |
1618 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1619 | int page) |
7bc3312b TG |
1620 | { |
1621 | uint8_t *buf = chip->oob_poi; | |
1622 | int length = mtd->oobsize; | |
1623 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1624 | int eccsize = chip->ecc.size; | |
1625 | uint8_t *bufpoi = buf; | |
1626 | int i, toread, sndrnd = 0, pos; | |
1627 | ||
1628 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1629 | for (i = 0; i < chip->ecc.steps; i++) { | |
1630 | if (sndrnd) { | |
1631 | pos = eccsize + i * (eccsize + chunk); | |
1632 | if (mtd->writesize > 512) | |
1633 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1634 | else | |
1635 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1636 | } else | |
1637 | sndrnd = 1; | |
1638 | toread = min_t(int, length, chunk); | |
1639 | chip->read_buf(mtd, bufpoi, toread); | |
1640 | bufpoi += toread; | |
1641 | length -= toread; | |
1642 | } | |
1643 | if (length > 0) | |
1644 | chip->read_buf(mtd, bufpoi, length); | |
1645 | ||
5c2ffb11 | 1646 | return 0; |
7bc3312b TG |
1647 | } |
1648 | ||
1649 | /** | |
7854d3f7 | 1650 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1651 | * @mtd: mtd info structure |
1652 | * @chip: nand chip info structure | |
1653 | * @page: page number to write | |
7bc3312b TG |
1654 | */ |
1655 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1656 | int page) | |
1657 | { | |
1658 | int status = 0; | |
1659 | const uint8_t *buf = chip->oob_poi; | |
1660 | int length = mtd->oobsize; | |
1661 | ||
1662 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1663 | chip->write_buf(mtd, buf, length); | |
1664 | /* Send command to program the OOB data */ | |
1665 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1666 | ||
1667 | status = chip->waitfunc(mtd, chip); | |
1668 | ||
0d420f9d | 1669 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1670 | } |
1671 | ||
1672 | /** | |
7854d3f7 | 1673 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1674 | * with syndrome - only for large page flash |
1675 | * @mtd: mtd info structure | |
1676 | * @chip: nand chip info structure | |
1677 | * @page: page number to write | |
7bc3312b TG |
1678 | */ |
1679 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1680 | struct nand_chip *chip, int page) | |
1681 | { | |
1682 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1683 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1684 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1685 | const uint8_t *bufpoi = chip->oob_poi; | |
1686 | ||
1687 | /* | |
1688 | * data-ecc-data-ecc ... ecc-oob | |
1689 | * or | |
1690 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1691 | */ | |
1692 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1693 | pos = steps * (eccsize + chunk); | |
1694 | steps = 0; | |
1695 | } else | |
8b0036ee | 1696 | pos = eccsize; |
7bc3312b TG |
1697 | |
1698 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1699 | for (i = 0; i < steps; i++) { | |
1700 | if (sndcmd) { | |
1701 | if (mtd->writesize <= 512) { | |
1702 | uint32_t fill = 0xFFFFFFFF; | |
1703 | ||
1704 | len = eccsize; | |
1705 | while (len > 0) { | |
1706 | int num = min_t(int, len, 4); | |
1707 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1708 | num); | |
1709 | len -= num; | |
1710 | } | |
1711 | } else { | |
1712 | pos = eccsize + i * (eccsize + chunk); | |
1713 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1714 | } | |
1715 | } else | |
1716 | sndcmd = 1; | |
1717 | len = min_t(int, length, chunk); | |
1718 | chip->write_buf(mtd, bufpoi, len); | |
1719 | bufpoi += len; | |
1720 | length -= len; | |
1721 | } | |
1722 | if (length > 0) | |
1723 | chip->write_buf(mtd, bufpoi, length); | |
1724 | ||
1725 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1726 | status = chip->waitfunc(mtd, chip); | |
1727 | ||
1728 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1729 | } | |
1730 | ||
1da177e4 | 1731 | /** |
7854d3f7 | 1732 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
1733 | * @mtd: MTD device structure |
1734 | * @from: offset to read from | |
1735 | * @ops: oob operations description structure | |
1da177e4 | 1736 | * |
8b6e50c9 | 1737 | * NAND read out-of-band data from the spare area. |
1da177e4 | 1738 | */ |
8593fbc6 TG |
1739 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1740 | struct mtd_oob_ops *ops) | |
1da177e4 | 1741 | { |
c00a0991 | 1742 | int page, realpage, chipnr; |
ace4dfee | 1743 | struct nand_chip *chip = mtd->priv; |
041e4575 | 1744 | struct mtd_ecc_stats stats; |
7014568b VW |
1745 | int readlen = ops->ooblen; |
1746 | int len; | |
7bc3312b | 1747 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 1748 | int ret = 0; |
61b03bd7 | 1749 | |
289c0522 | 1750 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 1751 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 1752 | |
041e4575 BN |
1753 | stats = mtd->ecc_stats; |
1754 | ||
0612b9dd | 1755 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 1756 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1757 | else |
1758 | len = mtd->oobsize; | |
1759 | ||
1760 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
1761 | pr_debug("%s: attempt to start read outside oob\n", |
1762 | __func__); | |
03736155 AH |
1763 | return -EINVAL; |
1764 | } | |
1765 | ||
1766 | /* Do not allow reads past end of device */ | |
1767 | if (unlikely(from >= mtd->size || | |
1768 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1769 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
1770 | pr_debug("%s: attempt to read beyond end of device\n", |
1771 | __func__); | |
03736155 AH |
1772 | return -EINVAL; |
1773 | } | |
7014568b | 1774 | |
7314e9e7 | 1775 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1776 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1777 | |
7314e9e7 TG |
1778 | /* Shift to get page */ |
1779 | realpage = (int)(from >> chip->page_shift); | |
1780 | page = realpage & chip->pagemask; | |
1da177e4 | 1781 | |
f8ac0414 | 1782 | while (1) { |
0612b9dd | 1783 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 1784 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 1785 | else |
1951f2f7 SL |
1786 | ret = chip->ecc.read_oob(mtd, chip, page); |
1787 | ||
1788 | if (ret < 0) | |
1789 | break; | |
7014568b VW |
1790 | |
1791 | len = min(len, readlen); | |
1792 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1793 | |
7014568b | 1794 | readlen -= len; |
0d420f9d SZ |
1795 | if (!readlen) |
1796 | break; | |
1797 | ||
7314e9e7 TG |
1798 | /* Increment page address */ |
1799 | realpage++; | |
1800 | ||
1801 | page = realpage & chip->pagemask; | |
1802 | /* Check, if we cross a chip boundary */ | |
1803 | if (!page) { | |
1804 | chipnr++; | |
1805 | chip->select_chip(mtd, -1); | |
1806 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1807 | } |
1808 | } | |
b0bb6903 | 1809 | chip->select_chip(mtd, -1); |
1da177e4 | 1810 | |
1951f2f7 SL |
1811 | ops->oobretlen = ops->ooblen - readlen; |
1812 | ||
1813 | if (ret < 0) | |
1814 | return ret; | |
041e4575 BN |
1815 | |
1816 | if (mtd->ecc_stats.failed - stats.failed) | |
1817 | return -EBADMSG; | |
1818 | ||
1819 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
1820 | } |
1821 | ||
1822 | /** | |
8593fbc6 | 1823 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
1824 | * @mtd: MTD device structure |
1825 | * @from: offset to read from | |
1826 | * @ops: oob operation description structure | |
1da177e4 | 1827 | * |
8b6e50c9 | 1828 | * NAND read data and/or out-of-band data. |
1da177e4 | 1829 | */ |
8593fbc6 TG |
1830 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1831 | struct mtd_oob_ops *ops) | |
1da177e4 | 1832 | { |
8593fbc6 TG |
1833 | int ret = -ENOTSUPP; |
1834 | ||
1835 | ops->retlen = 0; | |
1da177e4 LT |
1836 | |
1837 | /* Do not allow reads past end of device */ | |
7014568b | 1838 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
1839 | pr_debug("%s: attempt to read beyond end of device\n", |
1840 | __func__); | |
1da177e4 LT |
1841 | return -EINVAL; |
1842 | } | |
1843 | ||
6a8214aa | 1844 | nand_get_device(mtd, FL_READING); |
1da177e4 | 1845 | |
f8ac0414 | 1846 | switch (ops->mode) { |
0612b9dd BN |
1847 | case MTD_OPS_PLACE_OOB: |
1848 | case MTD_OPS_AUTO_OOB: | |
1849 | case MTD_OPS_RAW: | |
8593fbc6 | 1850 | break; |
1da177e4 | 1851 | |
8593fbc6 TG |
1852 | default: |
1853 | goto out; | |
1854 | } | |
1da177e4 | 1855 | |
8593fbc6 TG |
1856 | if (!ops->datbuf) |
1857 | ret = nand_do_read_oob(mtd, from, ops); | |
1858 | else | |
1859 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1860 | |
7351d3a5 | 1861 | out: |
8593fbc6 TG |
1862 | nand_release_device(mtd); |
1863 | return ret; | |
1864 | } | |
61b03bd7 | 1865 | |
1da177e4 | 1866 | |
8593fbc6 | 1867 | /** |
7854d3f7 | 1868 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
1869 | * @mtd: mtd info structure |
1870 | * @chip: nand chip info structure | |
1871 | * @buf: data buffer | |
1fbb938d | 1872 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df | 1873 | * |
7854d3f7 | 1874 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 1875 | */ |
fdbad98d | 1876 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1877 | const uint8_t *buf, int oob_required) |
8593fbc6 TG |
1878 | { |
1879 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1880 | if (oob_required) |
1881 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
1882 | |
1883 | return 0; | |
1da177e4 LT |
1884 | } |
1885 | ||
52ff49df | 1886 | /** |
7854d3f7 | 1887 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
1888 | * @mtd: mtd info structure |
1889 | * @chip: nand chip info structure | |
1890 | * @buf: data buffer | |
1fbb938d | 1891 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df DB |
1892 | * |
1893 | * We need a special oob layout and handling even when ECC isn't checked. | |
1894 | */ | |
fdbad98d | 1895 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 1896 | struct nand_chip *chip, |
1fbb938d | 1897 | const uint8_t *buf, int oob_required) |
52ff49df DB |
1898 | { |
1899 | int eccsize = chip->ecc.size; | |
1900 | int eccbytes = chip->ecc.bytes; | |
1901 | uint8_t *oob = chip->oob_poi; | |
1902 | int steps, size; | |
1903 | ||
1904 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1905 | chip->write_buf(mtd, buf, eccsize); | |
1906 | buf += eccsize; | |
1907 | ||
1908 | if (chip->ecc.prepad) { | |
1909 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1910 | oob += chip->ecc.prepad; | |
1911 | } | |
1912 | ||
1913 | chip->read_buf(mtd, oob, eccbytes); | |
1914 | oob += eccbytes; | |
1915 | ||
1916 | if (chip->ecc.postpad) { | |
1917 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1918 | oob += chip->ecc.postpad; | |
1919 | } | |
1920 | } | |
1921 | ||
1922 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1923 | if (size) | |
1924 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
1925 | |
1926 | return 0; | |
52ff49df | 1927 | } |
9223a456 | 1928 | /** |
7854d3f7 | 1929 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
1930 | * @mtd: mtd info structure |
1931 | * @chip: nand chip info structure | |
1932 | * @buf: data buffer | |
1fbb938d | 1933 | * @oob_required: must write chip->oob_poi to OOB |
9223a456 | 1934 | */ |
fdbad98d | 1935 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1936 | const uint8_t *buf, int oob_required) |
9223a456 | 1937 | { |
f75e5097 TG |
1938 | int i, eccsize = chip->ecc.size; |
1939 | int eccbytes = chip->ecc.bytes; | |
1940 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1941 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1942 | const uint8_t *p = buf; |
8b099a39 | 1943 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1944 | |
7854d3f7 | 1945 | /* Software ECC calculation */ |
8593fbc6 TG |
1946 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
1947 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1948 | |
8593fbc6 TG |
1949 | for (i = 0; i < chip->ecc.total; i++) |
1950 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1951 | |
fdbad98d | 1952 | return chip->ecc.write_page_raw(mtd, chip, buf, 1); |
f75e5097 | 1953 | } |
9223a456 | 1954 | |
f75e5097 | 1955 | /** |
7854d3f7 | 1956 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
1957 | * @mtd: mtd info structure |
1958 | * @chip: nand chip info structure | |
1959 | * @buf: data buffer | |
1fbb938d | 1960 | * @oob_required: must write chip->oob_poi to OOB |
f75e5097 | 1961 | */ |
fdbad98d | 1962 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1963 | const uint8_t *buf, int oob_required) |
f75e5097 TG |
1964 | { |
1965 | int i, eccsize = chip->ecc.size; | |
1966 | int eccbytes = chip->ecc.bytes; | |
1967 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1968 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1969 | const uint8_t *p = buf; |
8b099a39 | 1970 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1971 | |
f75e5097 TG |
1972 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1973 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 1974 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 1975 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
1976 | } |
1977 | ||
f75e5097 TG |
1978 | for (i = 0; i < chip->ecc.total; i++) |
1979 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1980 | ||
1981 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
1982 | |
1983 | return 0; | |
9223a456 TG |
1984 | } |
1985 | ||
61b03bd7 | 1986 | /** |
7854d3f7 | 1987 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
1988 | * @mtd: mtd info structure |
1989 | * @chip: nand chip info structure | |
1990 | * @buf: data buffer | |
1fbb938d | 1991 | * @oob_required: must write chip->oob_poi to OOB |
1da177e4 | 1992 | * |
8b6e50c9 BN |
1993 | * The hw generator calculates the error syndrome automatically. Therefore we |
1994 | * need a special oob layout and handling. | |
f75e5097 | 1995 | */ |
fdbad98d | 1996 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1997 | struct nand_chip *chip, |
1998 | const uint8_t *buf, int oob_required) | |
1da177e4 | 1999 | { |
f75e5097 TG |
2000 | int i, eccsize = chip->ecc.size; |
2001 | int eccbytes = chip->ecc.bytes; | |
2002 | int eccsteps = chip->ecc.steps; | |
2003 | const uint8_t *p = buf; | |
2004 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2005 | |
f75e5097 | 2006 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2007 | |
f75e5097 TG |
2008 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2009 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2010 | |
f75e5097 TG |
2011 | if (chip->ecc.prepad) { |
2012 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2013 | oob += chip->ecc.prepad; | |
2014 | } | |
2015 | ||
2016 | chip->ecc.calculate(mtd, p, oob); | |
2017 | chip->write_buf(mtd, oob, eccbytes); | |
2018 | oob += eccbytes; | |
2019 | ||
2020 | if (chip->ecc.postpad) { | |
2021 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2022 | oob += chip->ecc.postpad; | |
1da177e4 | 2023 | } |
1da177e4 | 2024 | } |
f75e5097 TG |
2025 | |
2026 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2027 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2028 | if (i) |
2029 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2030 | |
2031 | return 0; | |
f75e5097 TG |
2032 | } |
2033 | ||
2034 | /** | |
956e944c | 2035 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2036 | * @mtd: MTD device structure |
2037 | * @chip: NAND chip descriptor | |
2038 | * @buf: the data to write | |
1fbb938d | 2039 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2040 | * @page: page number to write |
2041 | * @cached: cached programming | |
2042 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2043 | */ |
2044 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d BN |
2045 | const uint8_t *buf, int oob_required, int page, |
2046 | int cached, int raw) | |
f75e5097 TG |
2047 | { |
2048 | int status; | |
2049 | ||
2050 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2051 | ||
956e944c | 2052 | if (unlikely(raw)) |
fdbad98d | 2053 | status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required); |
956e944c | 2054 | else |
fdbad98d JW |
2055 | status = chip->ecc.write_page(mtd, chip, buf, oob_required); |
2056 | ||
2057 | if (status < 0) | |
2058 | return status; | |
f75e5097 TG |
2059 | |
2060 | /* | |
7854d3f7 | 2061 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2062 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2063 | */ |
2064 | cached = 0; | |
2065 | ||
2066 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
2067 | ||
2068 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2069 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2070 | /* |
2071 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2072 | * available. |
f75e5097 TG |
2073 | */ |
2074 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2075 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2076 | page); | |
2077 | ||
2078 | if (status & NAND_STATUS_FAIL) | |
2079 | return -EIO; | |
2080 | } else { | |
2081 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2082 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2083 | } |
2084 | ||
f75e5097 | 2085 | return 0; |
1da177e4 LT |
2086 | } |
2087 | ||
8593fbc6 | 2088 | /** |
7854d3f7 | 2089 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2090 | * @mtd: MTD device structure |
8b6e50c9 BN |
2091 | * @oob: oob data buffer |
2092 | * @len: oob data write length | |
2093 | * @ops: oob ops structure | |
8593fbc6 | 2094 | */ |
f722013e TAA |
2095 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2096 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2097 | { |
f722013e TAA |
2098 | struct nand_chip *chip = mtd->priv; |
2099 | ||
2100 | /* | |
2101 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2102 | * data from a previous OOB read. | |
2103 | */ | |
2104 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2105 | ||
f8ac0414 | 2106 | switch (ops->mode) { |
8593fbc6 | 2107 | |
0612b9dd BN |
2108 | case MTD_OPS_PLACE_OOB: |
2109 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2110 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2111 | return oob + len; | |
2112 | ||
0612b9dd | 2113 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2114 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2115 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2116 | size_t bytes = 0; | |
8593fbc6 | 2117 | |
f8ac0414 | 2118 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2119 | /* Write request not from offset 0? */ |
7bc3312b TG |
2120 | if (unlikely(woffs)) { |
2121 | if (woffs >= free->length) { | |
2122 | woffs -= free->length; | |
2123 | continue; | |
2124 | } | |
2125 | boffs = free->offset + woffs; | |
2126 | bytes = min_t(size_t, len, | |
2127 | (free->length - woffs)); | |
2128 | woffs = 0; | |
2129 | } else { | |
2130 | bytes = min_t(size_t, len, free->length); | |
2131 | boffs = free->offset; | |
2132 | } | |
8b0036ee | 2133 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2134 | oob += bytes; |
2135 | } | |
2136 | return oob; | |
2137 | } | |
2138 | default: | |
2139 | BUG(); | |
2140 | } | |
2141 | return NULL; | |
2142 | } | |
2143 | ||
f8ac0414 | 2144 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2145 | |
2146 | /** | |
7854d3f7 | 2147 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2148 | * @mtd: MTD device structure |
2149 | * @to: offset to write to | |
2150 | * @ops: oob operations description structure | |
1da177e4 | 2151 | * |
8b6e50c9 | 2152 | * NAND write with ECC. |
1da177e4 | 2153 | */ |
8593fbc6 TG |
2154 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2155 | struct mtd_oob_ops *ops) | |
1da177e4 | 2156 | { |
29072b96 | 2157 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2158 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2159 | uint32_t writelen = ops->len; |
782ce79a ML |
2160 | |
2161 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2162 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2163 | mtd->oobavail : mtd->oobsize; |
2164 | ||
8593fbc6 TG |
2165 | uint8_t *oob = ops->oobbuf; |
2166 | uint8_t *buf = ops->datbuf; | |
29072b96 | 2167 | int ret, subpage; |
e47f3db4 | 2168 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2169 | |
8593fbc6 | 2170 | ops->retlen = 0; |
29072b96 TG |
2171 | if (!writelen) |
2172 | return 0; | |
1da177e4 | 2173 | |
8b6e50c9 | 2174 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2175 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2176 | pr_notice("%s: attempt to write non page aligned data\n", |
2177 | __func__); | |
1da177e4 LT |
2178 | return -EINVAL; |
2179 | } | |
2180 | ||
29072b96 TG |
2181 | column = to & (mtd->writesize - 1); |
2182 | subpage = column || (writelen & (mtd->writesize - 1)); | |
2183 | ||
2184 | if (subpage && oob) | |
2185 | return -EINVAL; | |
1da177e4 | 2186 | |
6a930961 TG |
2187 | chipnr = (int)(to >> chip->chip_shift); |
2188 | chip->select_chip(mtd, chipnr); | |
2189 | ||
1da177e4 | 2190 | /* Check, if it is write protected */ |
b0bb6903 HS |
2191 | if (nand_check_wp(mtd)) { |
2192 | ret = -EIO; | |
2193 | goto err_out; | |
2194 | } | |
1da177e4 | 2195 | |
f75e5097 TG |
2196 | realpage = (int)(to >> chip->page_shift); |
2197 | page = realpage & chip->pagemask; | |
2198 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2199 | ||
2200 | /* Invalidate the page cache, when we write to the cached page */ | |
2201 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2202 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2203 | chip->pagebuf = -1; |
61b03bd7 | 2204 | |
782ce79a | 2205 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2206 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2207 | ret = -EINVAL; | |
2208 | goto err_out; | |
2209 | } | |
782ce79a | 2210 | |
f8ac0414 | 2211 | while (1) { |
29072b96 | 2212 | int bytes = mtd->writesize; |
f75e5097 | 2213 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2214 | uint8_t *wbuf = buf; |
2215 | ||
8b6e50c9 | 2216 | /* Partial page write? */ |
29072b96 TG |
2217 | if (unlikely(column || writelen < (mtd->writesize - 1))) { |
2218 | cached = 0; | |
2219 | bytes = min_t(int, bytes - column, (int) writelen); | |
2220 | chip->pagebuf = -1; | |
2221 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2222 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2223 | wbuf = chip->buffers->databuf; | |
2224 | } | |
1da177e4 | 2225 | |
782ce79a ML |
2226 | if (unlikely(oob)) { |
2227 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2228 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2229 | oobwritelen -= len; |
f722013e TAA |
2230 | } else { |
2231 | /* We still need to erase leftover OOB data */ | |
2232 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2233 | } |
8593fbc6 | 2234 | |
e47f3db4 BN |
2235 | ret = chip->write_page(mtd, chip, wbuf, oob_required, page, |
2236 | cached, (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2237 | if (ret) |
2238 | break; | |
2239 | ||
2240 | writelen -= bytes; | |
2241 | if (!writelen) | |
2242 | break; | |
2243 | ||
29072b96 | 2244 | column = 0; |
f75e5097 TG |
2245 | buf += bytes; |
2246 | realpage++; | |
2247 | ||
2248 | page = realpage & chip->pagemask; | |
2249 | /* Check, if we cross a chip boundary */ | |
2250 | if (!page) { | |
2251 | chipnr++; | |
2252 | chip->select_chip(mtd, -1); | |
2253 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2254 | } |
2255 | } | |
8593fbc6 | 2256 | |
8593fbc6 | 2257 | ops->retlen = ops->len - writelen; |
7014568b VW |
2258 | if (unlikely(oob)) |
2259 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2260 | |
2261 | err_out: | |
2262 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2263 | return ret; |
2264 | } | |
2265 | ||
2af7c653 SK |
2266 | /** |
2267 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2268 | * @mtd: MTD device structure |
2269 | * @to: offset to write to | |
2270 | * @len: number of bytes to write | |
2271 | * @retlen: pointer to variable to store the number of written bytes | |
2272 | * @buf: the data to write | |
2af7c653 SK |
2273 | * |
2274 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2275 | * may for example be called by mtdoops when writing an oops while in panic. | |
2276 | */ | |
2277 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2278 | size_t *retlen, const uint8_t *buf) | |
2279 | { | |
2280 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2281 | struct mtd_oob_ops ops; |
2af7c653 SK |
2282 | int ret; |
2283 | ||
8b6e50c9 | 2284 | /* Wait for the device to get ready */ |
2af7c653 SK |
2285 | panic_nand_wait(mtd, chip, 400); |
2286 | ||
8b6e50c9 | 2287 | /* Grab the device */ |
2af7c653 SK |
2288 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2289 | ||
4a89ff88 BN |
2290 | ops.len = len; |
2291 | ops.datbuf = (uint8_t *)buf; | |
2292 | ops.oobbuf = NULL; | |
11041ae6 | 2293 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2294 | |
4a89ff88 | 2295 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2296 | |
4a89ff88 | 2297 | *retlen = ops.retlen; |
2af7c653 SK |
2298 | return ret; |
2299 | } | |
2300 | ||
f75e5097 | 2301 | /** |
8593fbc6 | 2302 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2303 | * @mtd: MTD device structure |
2304 | * @to: offset to write to | |
2305 | * @len: number of bytes to write | |
2306 | * @retlen: pointer to variable to store the number of written bytes | |
2307 | * @buf: the data to write | |
f75e5097 | 2308 | * |
8b6e50c9 | 2309 | * NAND write with ECC. |
f75e5097 | 2310 | */ |
8593fbc6 TG |
2311 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2312 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2313 | { |
4a89ff88 | 2314 | struct mtd_oob_ops ops; |
f75e5097 TG |
2315 | int ret; |
2316 | ||
6a8214aa | 2317 | nand_get_device(mtd, FL_WRITING); |
4a89ff88 BN |
2318 | ops.len = len; |
2319 | ops.datbuf = (uint8_t *)buf; | |
2320 | ops.oobbuf = NULL; | |
11041ae6 | 2321 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2322 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2323 | *retlen = ops.retlen; |
f75e5097 | 2324 | nand_release_device(mtd); |
8593fbc6 | 2325 | return ret; |
f75e5097 | 2326 | } |
7314e9e7 | 2327 | |
1da177e4 | 2328 | /** |
8593fbc6 | 2329 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2330 | * @mtd: MTD device structure |
2331 | * @to: offset to write to | |
2332 | * @ops: oob operation description structure | |
1da177e4 | 2333 | * |
8b6e50c9 | 2334 | * NAND write out-of-band. |
1da177e4 | 2335 | */ |
8593fbc6 TG |
2336 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2337 | struct mtd_oob_ops *ops) | |
1da177e4 | 2338 | { |
03736155 | 2339 | int chipnr, page, status, len; |
ace4dfee | 2340 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2341 | |
289c0522 | 2342 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2343 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2344 | |
0612b9dd | 2345 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2346 | len = chip->ecc.layout->oobavail; |
2347 | else | |
2348 | len = mtd->oobsize; | |
2349 | ||
1da177e4 | 2350 | /* Do not allow write past end of page */ |
03736155 | 2351 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2352 | pr_debug("%s: attempt to write past end of page\n", |
2353 | __func__); | |
1da177e4 LT |
2354 | return -EINVAL; |
2355 | } | |
2356 | ||
03736155 | 2357 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2358 | pr_debug("%s: attempt to start write outside oob\n", |
2359 | __func__); | |
03736155 AH |
2360 | return -EINVAL; |
2361 | } | |
2362 | ||
775adc3d | 2363 | /* Do not allow write past end of device */ |
03736155 AH |
2364 | if (unlikely(to >= mtd->size || |
2365 | ops->ooboffs + ops->ooblen > | |
2366 | ((mtd->size >> chip->page_shift) - | |
2367 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2368 | pr_debug("%s: attempt to write beyond end of device\n", |
2369 | __func__); | |
03736155 AH |
2370 | return -EINVAL; |
2371 | } | |
2372 | ||
7314e9e7 | 2373 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2374 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2375 | |
7314e9e7 TG |
2376 | /* Shift to get page */ |
2377 | page = (int)(to >> chip->page_shift); | |
2378 | ||
2379 | /* | |
2380 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2381 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2382 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2383 | * it in the doc2000 driver in August 1999. dwmw2. | |
2384 | */ | |
ace4dfee | 2385 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2386 | |
2387 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2388 | if (nand_check_wp(mtd)) { |
2389 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2390 | return -EROFS; |
b0bb6903 | 2391 | } |
61b03bd7 | 2392 | |
1da177e4 | 2393 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2394 | if (page == chip->pagebuf) |
2395 | chip->pagebuf = -1; | |
1da177e4 | 2396 | |
f722013e | 2397 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2398 | |
0612b9dd | 2399 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2400 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2401 | else | |
2402 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2403 | |
b0bb6903 HS |
2404 | chip->select_chip(mtd, -1); |
2405 | ||
7bc3312b TG |
2406 | if (status) |
2407 | return status; | |
1da177e4 | 2408 | |
7014568b | 2409 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2410 | |
7bc3312b | 2411 | return 0; |
8593fbc6 TG |
2412 | } |
2413 | ||
2414 | /** | |
2415 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2416 | * @mtd: MTD device structure |
2417 | * @to: offset to write to | |
2418 | * @ops: oob operation description structure | |
8593fbc6 TG |
2419 | */ |
2420 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2421 | struct mtd_oob_ops *ops) | |
2422 | { | |
8593fbc6 TG |
2423 | int ret = -ENOTSUPP; |
2424 | ||
2425 | ops->retlen = 0; | |
2426 | ||
2427 | /* Do not allow writes past end of device */ | |
7014568b | 2428 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2429 | pr_debug("%s: attempt to write beyond end of device\n", |
2430 | __func__); | |
8593fbc6 TG |
2431 | return -EINVAL; |
2432 | } | |
2433 | ||
6a8214aa | 2434 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2435 | |
f8ac0414 | 2436 | switch (ops->mode) { |
0612b9dd BN |
2437 | case MTD_OPS_PLACE_OOB: |
2438 | case MTD_OPS_AUTO_OOB: | |
2439 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2440 | break; |
2441 | ||
2442 | default: | |
2443 | goto out; | |
2444 | } | |
2445 | ||
2446 | if (!ops->datbuf) | |
2447 | ret = nand_do_write_oob(mtd, to, ops); | |
2448 | else | |
2449 | ret = nand_do_write_ops(mtd, to, ops); | |
2450 | ||
7351d3a5 | 2451 | out: |
1da177e4 | 2452 | nand_release_device(mtd); |
1da177e4 LT |
2453 | return ret; |
2454 | } | |
2455 | ||
1da177e4 | 2456 | /** |
7854d3f7 | 2457 | * single_erase_cmd - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2458 | * @mtd: MTD device structure |
2459 | * @page: the page address of the block which will be erased | |
1da177e4 | 2460 | * |
8b6e50c9 | 2461 | * Standard erase command for NAND chips. |
1da177e4 | 2462 | */ |
e0c7d767 | 2463 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2464 | { |
ace4dfee | 2465 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2466 | /* Send commands to erase a block */ |
ace4dfee TG |
2467 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2468 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2469 | } |
2470 | ||
2471 | /** | |
7854d3f7 | 2472 | * multi_erase_cmd - [GENERIC] AND specific block erase command function |
8b6e50c9 BN |
2473 | * @mtd: MTD device structure |
2474 | * @page: the page address of the block which will be erased | |
1da177e4 | 2475 | * |
8b6e50c9 | 2476 | * AND multi block erase command function. Erase 4 consecutive blocks. |
1da177e4 | 2477 | */ |
e0c7d767 | 2478 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2479 | { |
ace4dfee | 2480 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2481 | /* Send commands to erase a block */ |
ace4dfee TG |
2482 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2483 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2484 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2485 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
2486 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2487 | } |
2488 | ||
2489 | /** | |
2490 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2491 | * @mtd: MTD device structure |
2492 | * @instr: erase instruction | |
1da177e4 | 2493 | * |
8b6e50c9 | 2494 | * Erase one ore more blocks. |
1da177e4 | 2495 | */ |
e0c7d767 | 2496 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2497 | { |
e0c7d767 | 2498 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2499 | } |
61b03bd7 | 2500 | |
30f464b7 | 2501 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 2502 | /** |
7854d3f7 | 2503 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2504 | * @mtd: MTD device structure |
2505 | * @instr: erase instruction | |
2506 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2507 | * |
8b6e50c9 | 2508 | * Erase one ore more blocks. |
1da177e4 | 2509 | */ |
ace4dfee TG |
2510 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2511 | int allowbbt) | |
1da177e4 | 2512 | { |
69423d99 | 2513 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2514 | struct nand_chip *chip = mtd->priv; |
f8ac0414 | 2515 | loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0}; |
ace4dfee | 2516 | unsigned int bbt_masked_page = 0xffffffff; |
69423d99 | 2517 | loff_t len; |
1da177e4 | 2518 | |
289c0522 BN |
2519 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2520 | __func__, (unsigned long long)instr->addr, | |
2521 | (unsigned long long)instr->len); | |
1da177e4 | 2522 | |
6fe5a6ac | 2523 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2524 | return -EINVAL; |
1da177e4 | 2525 | |
1da177e4 | 2526 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2527 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2528 | |
2529 | /* Shift to get first page */ | |
ace4dfee TG |
2530 | page = (int)(instr->addr >> chip->page_shift); |
2531 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2532 | |
2533 | /* Calculate pages in each block */ | |
ace4dfee | 2534 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2535 | |
2536 | /* Select the NAND device */ | |
ace4dfee | 2537 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2538 | |
1da177e4 LT |
2539 | /* Check, if it is write protected */ |
2540 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2541 | pr_debug("%s: device is write protected!\n", |
2542 | __func__); | |
1da177e4 LT |
2543 | instr->state = MTD_ERASE_FAILED; |
2544 | goto erase_exit; | |
2545 | } | |
2546 | ||
ace4dfee TG |
2547 | /* |
2548 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
2549 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
2550 | * can not be matched. This is also done when the bbt is actually | |
7854d3f7 | 2551 | * erased to avoid recursive updates. |
ace4dfee TG |
2552 | */ |
2553 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
2554 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 2555 | |
1da177e4 LT |
2556 | /* Loop through the pages */ |
2557 | len = instr->len; | |
2558 | ||
2559 | instr->state = MTD_ERASING; | |
2560 | ||
2561 | while (len) { | |
12183a20 | 2562 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2563 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2564 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2565 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2566 | __func__, page); | |
1da177e4 LT |
2567 | instr->state = MTD_ERASE_FAILED; |
2568 | goto erase_exit; | |
2569 | } | |
61b03bd7 | 2570 | |
ace4dfee TG |
2571 | /* |
2572 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2573 | * contains the current cached page. |
ace4dfee TG |
2574 | */ |
2575 | if (page <= chip->pagebuf && chip->pagebuf < | |
2576 | (page + pages_per_block)) | |
2577 | chip->pagebuf = -1; | |
1da177e4 | 2578 | |
ace4dfee | 2579 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2580 | |
7bc3312b | 2581 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2582 | |
ace4dfee TG |
2583 | /* |
2584 | * See if operation failed and additional status checks are | |
2585 | * available | |
2586 | */ | |
2587 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2588 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2589 | status, page); | |
068e3c0a | 2590 | |
1da177e4 | 2591 | /* See if block erase succeeded */ |
a4ab4c5d | 2592 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2593 | pr_debug("%s: failed erase, page 0x%08x\n", |
2594 | __func__, page); | |
1da177e4 | 2595 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2596 | instr->fail_addr = |
2597 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2598 | goto erase_exit; |
2599 | } | |
30f464b7 | 2600 | |
ace4dfee TG |
2601 | /* |
2602 | * If BBT requires refresh, set the BBT rewrite flag to the | |
8b6e50c9 | 2603 | * page being erased. |
ace4dfee TG |
2604 | */ |
2605 | if (bbt_masked_page != 0xffffffff && | |
2606 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
69423d99 AH |
2607 | rewrite_bbt[chipnr] = |
2608 | ((loff_t)page << chip->page_shift); | |
61b03bd7 | 2609 | |
1da177e4 | 2610 | /* Increment page address and decrement length */ |
ace4dfee | 2611 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
2612 | page += pages_per_block; |
2613 | ||
2614 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2615 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2616 | chipnr++; |
ace4dfee TG |
2617 | chip->select_chip(mtd, -1); |
2618 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 2619 | |
ace4dfee TG |
2620 | /* |
2621 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
8b6e50c9 | 2622 | * page mask to see if this BBT should be rewritten. |
ace4dfee TG |
2623 | */ |
2624 | if (bbt_masked_page != 0xffffffff && | |
2625 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
2626 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
2627 | BBT_PAGE_MASK; | |
1da177e4 LT |
2628 | } |
2629 | } | |
2630 | instr->state = MTD_ERASE_DONE; | |
2631 | ||
7351d3a5 | 2632 | erase_exit: |
1da177e4 LT |
2633 | |
2634 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2635 | |
2636 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2637 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2638 | nand_release_device(mtd); |
2639 | ||
49defc01 DW |
2640 | /* Do call back function */ |
2641 | if (!ret) | |
2642 | mtd_erase_callback(instr); | |
2643 | ||
ace4dfee TG |
2644 | /* |
2645 | * If BBT requires refresh and erase was successful, rewrite any | |
8b6e50c9 | 2646 | * selected bad block tables. |
ace4dfee TG |
2647 | */ |
2648 | if (bbt_masked_page == 0xffffffff || ret) | |
2649 | return ret; | |
2650 | ||
2651 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2652 | if (!rewrite_bbt[chipnr]) | |
2653 | continue; | |
8b6e50c9 | 2654 | /* Update the BBT for chip */ |
289c0522 BN |
2655 | pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n", |
2656 | __func__, chipnr, rewrite_bbt[chipnr], | |
2657 | chip->bbt_td->pages[chipnr]); | |
ace4dfee | 2658 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); |
30f464b7 DM |
2659 | } |
2660 | ||
1da177e4 LT |
2661 | /* Return more or less happy */ |
2662 | return ret; | |
2663 | } | |
2664 | ||
2665 | /** | |
2666 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2667 | * @mtd: MTD device structure |
1da177e4 | 2668 | * |
8b6e50c9 | 2669 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2670 | */ |
e0c7d767 | 2671 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2672 | { |
289c0522 | 2673 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2674 | |
2675 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 2676 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 2677 | /* Release it and go back */ |
e0c7d767 | 2678 | nand_release_device(mtd); |
1da177e4 LT |
2679 | } |
2680 | ||
1da177e4 | 2681 | /** |
ace4dfee | 2682 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2683 | * @mtd: MTD device structure |
2684 | * @offs: offset relative to mtd start | |
1da177e4 | 2685 | */ |
ace4dfee | 2686 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 2687 | { |
ace4dfee | 2688 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2689 | } |
2690 | ||
2691 | /** | |
ace4dfee | 2692 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2693 | * @mtd: MTD device structure |
2694 | * @ofs: offset relative to mtd start | |
1da177e4 | 2695 | */ |
e0c7d767 | 2696 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2697 | { |
ace4dfee | 2698 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2699 | int ret; |
2700 | ||
f8ac0414 FF |
2701 | ret = nand_block_isbad(mtd, ofs); |
2702 | if (ret) { | |
8b6e50c9 | 2703 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
2704 | if (ret > 0) |
2705 | return 0; | |
e0c7d767 DW |
2706 | return ret; |
2707 | } | |
1da177e4 | 2708 | |
ace4dfee | 2709 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2710 | } |
2711 | ||
7db03ecc HS |
2712 | /** |
2713 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
2714 | * @mtd: MTD device structure | |
2715 | * @chip: nand chip info structure | |
2716 | * @addr: feature address. | |
2717 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2718 | */ | |
2719 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2720 | int addr, uint8_t *subfeature_param) | |
2721 | { | |
2722 | int status; | |
2723 | ||
2724 | if (!chip->onfi_version) | |
2725 | return -EINVAL; | |
2726 | ||
2727 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
2728 | chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN); | |
2729 | status = chip->waitfunc(mtd, chip); | |
2730 | if (status & NAND_STATUS_FAIL) | |
2731 | return -EIO; | |
2732 | return 0; | |
2733 | } | |
2734 | ||
2735 | /** | |
2736 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
2737 | * @mtd: MTD device structure | |
2738 | * @chip: nand chip info structure | |
2739 | * @addr: feature address. | |
2740 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2741 | */ | |
2742 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2743 | int addr, uint8_t *subfeature_param) | |
2744 | { | |
2745 | if (!chip->onfi_version) | |
2746 | return -EINVAL; | |
2747 | ||
2748 | /* clear the sub feature parameters */ | |
2749 | memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); | |
2750 | ||
2751 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); | |
2752 | chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN); | |
2753 | return 0; | |
2754 | } | |
2755 | ||
962034f4 VW |
2756 | /** |
2757 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 2758 | * @mtd: MTD device structure |
962034f4 VW |
2759 | */ |
2760 | static int nand_suspend(struct mtd_info *mtd) | |
2761 | { | |
6a8214aa | 2762 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2763 | } |
2764 | ||
2765 | /** | |
2766 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 2767 | * @mtd: MTD device structure |
962034f4 VW |
2768 | */ |
2769 | static void nand_resume(struct mtd_info *mtd) | |
2770 | { | |
ace4dfee | 2771 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2772 | |
ace4dfee | 2773 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2774 | nand_release_device(mtd); |
2775 | else | |
d0370219 BN |
2776 | pr_err("%s called for a chip which is not in suspended state\n", |
2777 | __func__); | |
962034f4 VW |
2778 | } |
2779 | ||
8b6e50c9 | 2780 | /* Set default functions */ |
ace4dfee | 2781 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2782 | { |
1da177e4 | 2783 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2784 | if (!chip->chip_delay) |
2785 | chip->chip_delay = 20; | |
1da177e4 LT |
2786 | |
2787 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2788 | if (chip->cmdfunc == NULL) |
2789 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2790 | |
2791 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2792 | if (chip->waitfunc == NULL) |
2793 | chip->waitfunc = nand_wait; | |
2794 | ||
2795 | if (!chip->select_chip) | |
2796 | chip->select_chip = nand_select_chip; | |
2797 | if (!chip->read_byte) | |
2798 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2799 | if (!chip->read_word) | |
2800 | chip->read_word = nand_read_word; | |
2801 | if (!chip->block_bad) | |
2802 | chip->block_bad = nand_block_bad; | |
2803 | if (!chip->block_markbad) | |
2804 | chip->block_markbad = nand_default_block_markbad; | |
2805 | if (!chip->write_buf) | |
2806 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2807 | if (!chip->read_buf) | |
2808 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
ace4dfee TG |
2809 | if (!chip->scan_bbt) |
2810 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2811 | |
2812 | if (!chip->controller) { | |
2813 | chip->controller = &chip->hwcontrol; | |
2814 | spin_lock_init(&chip->controller->lock); | |
2815 | init_waitqueue_head(&chip->controller->wq); | |
2816 | } | |
2817 | ||
7aa65bfd TG |
2818 | } |
2819 | ||
8b6e50c9 | 2820 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
2821 | static void sanitize_string(uint8_t *s, size_t len) |
2822 | { | |
2823 | ssize_t i; | |
2824 | ||
8b6e50c9 | 2825 | /* Null terminate */ |
d1e1f4e4 FF |
2826 | s[len - 1] = 0; |
2827 | ||
8b6e50c9 | 2828 | /* Remove non printable chars */ |
d1e1f4e4 FF |
2829 | for (i = 0; i < len - 1; i++) { |
2830 | if (s[i] < ' ' || s[i] > 127) | |
2831 | s[i] = '?'; | |
2832 | } | |
2833 | ||
8b6e50c9 | 2834 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
2835 | strim(s); |
2836 | } | |
2837 | ||
2838 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
2839 | { | |
2840 | int i; | |
2841 | while (len--) { | |
2842 | crc ^= *p++ << 8; | |
2843 | for (i = 0; i < 8; i++) | |
2844 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
2845 | } | |
2846 | ||
2847 | return crc; | |
2848 | } | |
2849 | ||
6fb277ba | 2850 | /* |
8b6e50c9 | 2851 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
2852 | */ |
2853 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 2854 | int *busw) |
6fb277ba FF |
2855 | { |
2856 | struct nand_onfi_params *p = &chip->onfi_params; | |
2857 | int i; | |
2858 | int val; | |
2859 | ||
ff3206b2 MC |
2860 | /* ONFI need to be probed in 8 bits mode */ |
2861 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
7854d3f7 | 2862 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
2863 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
2864 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
2865 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
2866 | return 0; | |
2867 | ||
6fb277ba FF |
2868 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
2869 | for (i = 0; i < 3; i++) { | |
2870 | chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); | |
2871 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == | |
2872 | le16_to_cpu(p->crc)) { | |
9a4d4d69 | 2873 | pr_info("ONFI param page %d valid\n", i); |
6fb277ba FF |
2874 | break; |
2875 | } | |
2876 | } | |
2877 | ||
2878 | if (i == 3) | |
2879 | return 0; | |
2880 | ||
8b6e50c9 | 2881 | /* Check version */ |
6fb277ba | 2882 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
2883 | if (val & (1 << 5)) |
2884 | chip->onfi_version = 23; | |
2885 | else if (val & (1 << 4)) | |
6fb277ba FF |
2886 | chip->onfi_version = 22; |
2887 | else if (val & (1 << 3)) | |
2888 | chip->onfi_version = 21; | |
2889 | else if (val & (1 << 2)) | |
2890 | chip->onfi_version = 20; | |
b7b1a29d | 2891 | else if (val & (1 << 1)) |
6fb277ba | 2892 | chip->onfi_version = 10; |
b7b1a29d BN |
2893 | else |
2894 | chip->onfi_version = 0; | |
2895 | ||
2896 | if (!chip->onfi_version) { | |
d0370219 | 2897 | pr_info("%s: unsupported ONFI version: %d\n", __func__, val); |
b7b1a29d BN |
2898 | return 0; |
2899 | } | |
6fb277ba FF |
2900 | |
2901 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
2902 | sanitize_string(p->model, sizeof(p->model)); | |
2903 | if (!mtd->name) | |
2904 | mtd->name = p->model; | |
2905 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
2906 | mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; | |
2907 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
63795755 MC |
2908 | chip->chipsize = le32_to_cpu(p->blocks_per_lun); |
2909 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
08c248fb | 2910 | *busw = 0; |
6fb277ba | 2911 | if (le16_to_cpu(p->features) & 1) |
08c248fb | 2912 | *busw = NAND_BUSWIDTH_16; |
6fb277ba | 2913 | |
d42b5de3 | 2914 | pr_info("ONFI flash detected\n"); |
6fb277ba FF |
2915 | return 1; |
2916 | } | |
2917 | ||
e3b88bd6 BN |
2918 | /* |
2919 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
2920 | * @id_data: the ID string | |
2921 | * @arrlen: the length of the @id_data array | |
2922 | * @period: the period of repitition | |
2923 | * | |
2924 | * Check if an ID string is repeated within a given sequence of bytes at | |
2925 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
2926 | * period of 2). This is a helper function for nand_id_len(). Returns non-zero | |
2927 | * if the repetition has a period of @period; otherwise, returns zero. | |
2928 | */ | |
2929 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
2930 | { | |
2931 | int i, j; | |
2932 | for (i = 0; i < period; i++) | |
2933 | for (j = i + period; j < arrlen; j += period) | |
2934 | if (id_data[i] != id_data[j]) | |
2935 | return 0; | |
2936 | return 1; | |
2937 | } | |
2938 | ||
2939 | /* | |
2940 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
2941 | * @id_data: the ID string | |
2942 | * @arrlen: the length of the @id_data array | |
2943 | ||
2944 | * Returns the length of the ID string, according to known wraparound/trailing | |
2945 | * zero patterns. If no pattern exists, returns the length of the array. | |
2946 | */ | |
2947 | static int nand_id_len(u8 *id_data, int arrlen) | |
2948 | { | |
2949 | int last_nonzero, period; | |
2950 | ||
2951 | /* Find last non-zero byte */ | |
2952 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
2953 | if (id_data[last_nonzero]) | |
2954 | break; | |
2955 | ||
2956 | /* All zeros */ | |
2957 | if (last_nonzero < 0) | |
2958 | return 0; | |
2959 | ||
2960 | /* Calculate wraparound period */ | |
2961 | for (period = 1; period < arrlen; period++) | |
2962 | if (nand_id_has_period(id_data, arrlen, period)) | |
2963 | break; | |
2964 | ||
2965 | /* There's a repeated pattern */ | |
2966 | if (period < arrlen) | |
2967 | return period; | |
2968 | ||
2969 | /* There are trailing zeros */ | |
2970 | if (last_nonzero < arrlen - 1) | |
2971 | return last_nonzero + 1; | |
2972 | ||
2973 | /* No pattern detected */ | |
2974 | return arrlen; | |
2975 | } | |
2976 | ||
fc09bbc0 BN |
2977 | /* |
2978 | * Many new NAND share similar device ID codes, which represent the size of the | |
2979 | * chip. The rest of the parameters must be decoded according to generic or | |
2980 | * manufacturer-specific "extended ID" decoding patterns. | |
2981 | */ | |
2982 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
2983 | u8 id_data[8], int *busw) | |
2984 | { | |
e3b88bd6 | 2985 | int extid, id_len; |
fc09bbc0 BN |
2986 | /* The 3rd id byte holds MLC / multichip data */ |
2987 | chip->cellinfo = id_data[2]; | |
2988 | /* The 4th id byte is the important one */ | |
2989 | extid = id_data[3]; | |
2990 | ||
e3b88bd6 BN |
2991 | id_len = nand_id_len(id_data, 8); |
2992 | ||
fc09bbc0 BN |
2993 | /* |
2994 | * Field definitions are in the following datasheets: | |
2995 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 2996 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 2997 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 2998 | * |
af451af4 BN |
2999 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3000 | * ID to decide what to do. | |
fc09bbc0 | 3001 | */ |
af451af4 | 3002 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
6924d99f | 3003 | (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && |
af451af4 | 3004 | id_data[5] != 0x00) { |
fc09bbc0 BN |
3005 | /* Calc pagesize */ |
3006 | mtd->writesize = 2048 << (extid & 0x03); | |
3007 | extid >>= 2; | |
3008 | /* Calc oobsize */ | |
e2d3a35e | 3009 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3010 | case 1: |
3011 | mtd->oobsize = 128; | |
3012 | break; | |
3013 | case 2: | |
3014 | mtd->oobsize = 218; | |
3015 | break; | |
3016 | case 3: | |
3017 | mtd->oobsize = 400; | |
3018 | break; | |
e2d3a35e | 3019 | case 4: |
fc09bbc0 BN |
3020 | mtd->oobsize = 436; |
3021 | break; | |
e2d3a35e BN |
3022 | case 5: |
3023 | mtd->oobsize = 512; | |
3024 | break; | |
3025 | case 6: | |
3026 | default: /* Other cases are "reserved" (unknown) */ | |
3027 | mtd->oobsize = 640; | |
3028 | break; | |
fc09bbc0 BN |
3029 | } |
3030 | extid >>= 2; | |
3031 | /* Calc blocksize */ | |
3032 | mtd->erasesize = (128 * 1024) << | |
3033 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3034 | *busw = 0; | |
73ca392f BN |
3035 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
3036 | (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
3037 | unsigned int tmp; | |
3038 | ||
3039 | /* Calc pagesize */ | |
3040 | mtd->writesize = 2048 << (extid & 0x03); | |
3041 | extid >>= 2; | |
3042 | /* Calc oobsize */ | |
3043 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3044 | case 0: | |
3045 | mtd->oobsize = 128; | |
3046 | break; | |
3047 | case 1: | |
3048 | mtd->oobsize = 224; | |
3049 | break; | |
3050 | case 2: | |
3051 | mtd->oobsize = 448; | |
3052 | break; | |
3053 | case 3: | |
3054 | mtd->oobsize = 64; | |
3055 | break; | |
3056 | case 4: | |
3057 | mtd->oobsize = 32; | |
3058 | break; | |
3059 | case 5: | |
3060 | mtd->oobsize = 16; | |
3061 | break; | |
3062 | default: | |
3063 | mtd->oobsize = 640; | |
3064 | break; | |
3065 | } | |
3066 | extid >>= 2; | |
3067 | /* Calc blocksize */ | |
3068 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3069 | if (tmp < 0x03) | |
3070 | mtd->erasesize = (128 * 1024) << tmp; | |
3071 | else if (tmp == 0x03) | |
3072 | mtd->erasesize = 768 * 1024; | |
3073 | else | |
3074 | mtd->erasesize = (64 * 1024) << tmp; | |
3075 | *busw = 0; | |
fc09bbc0 BN |
3076 | } else { |
3077 | /* Calc pagesize */ | |
3078 | mtd->writesize = 1024 << (extid & 0x03); | |
3079 | extid >>= 2; | |
3080 | /* Calc oobsize */ | |
3081 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3082 | (mtd->writesize >> 9); | |
3083 | extid >>= 2; | |
3084 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3085 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3086 | extid >>= 2; | |
3087 | /* Get buswidth information */ | |
3088 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
3089 | } | |
3090 | } | |
3091 | ||
f23a481c BN |
3092 | /* |
3093 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3094 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3095 | * the chip. | |
3096 | */ | |
3097 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3098 | struct nand_flash_dev *type, u8 id_data[8], | |
3099 | int *busw) | |
3100 | { | |
3101 | int maf_id = id_data[0]; | |
3102 | ||
3103 | mtd->erasesize = type->erasesize; | |
3104 | mtd->writesize = type->pagesize; | |
3105 | mtd->oobsize = mtd->writesize / 32; | |
3106 | *busw = type->options & NAND_BUSWIDTH_16; | |
3107 | ||
3108 | /* | |
3109 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3110 | * some Spansion chips have erasesize that conflicts with size | |
3111 | * listed in nand_ids table. | |
3112 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3113 | */ | |
3114 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3115 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3116 | && mtd->writesize == 512) { | |
3117 | mtd->erasesize = 128 * 1024; | |
3118 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3119 | } | |
3120 | } | |
3121 | ||
7e74c2d7 BN |
3122 | /* |
3123 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3124 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3125 | * page size, cell-type information). | |
3126 | */ | |
3127 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3128 | struct nand_chip *chip, u8 id_data[8]) | |
3129 | { | |
3130 | int maf_id = id_data[0]; | |
3131 | ||
3132 | /* Set the bad block position */ | |
3133 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3134 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3135 | else | |
3136 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3137 | ||
3138 | /* | |
3139 | * Bad block marker is stored in the last page of each block on Samsung | |
3140 | * and Hynix MLC devices; stored in first two pages of each block on | |
3141 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3142 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3143 | */ | |
3144 | if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && | |
3145 | (maf_id == NAND_MFR_SAMSUNG || | |
3146 | maf_id == NAND_MFR_HYNIX)) | |
3147 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
3148 | else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && | |
3149 | (maf_id == NAND_MFR_SAMSUNG || | |
3150 | maf_id == NAND_MFR_HYNIX || | |
3151 | maf_id == NAND_MFR_TOSHIBA || | |
3152 | maf_id == NAND_MFR_AMD || | |
3153 | maf_id == NAND_MFR_MACRONIX)) || | |
3154 | (mtd->writesize == 2048 && | |
3155 | maf_id == NAND_MFR_MICRON)) | |
3156 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3157 | } | |
3158 | ||
7aa65bfd | 3159 | /* |
8b6e50c9 | 3160 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3161 | */ |
3162 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3163 | struct nand_chip *chip, |
7351d3a5 FF |
3164 | int busw, |
3165 | int *maf_id, int *dev_id, | |
5e81e88a | 3166 | struct nand_flash_dev *type) |
7aa65bfd | 3167 | { |
d1e1f4e4 | 3168 | int i, maf_idx; |
426c457a | 3169 | u8 id_data[8]; |
1da177e4 LT |
3170 | |
3171 | /* Select the device */ | |
ace4dfee | 3172 | chip->select_chip(mtd, 0); |
1da177e4 | 3173 | |
ef89a880 KB |
3174 | /* |
3175 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3176 | * after power-up. |
ef89a880 KB |
3177 | */ |
3178 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3179 | ||
1da177e4 | 3180 | /* Send the command for reading device ID */ |
ace4dfee | 3181 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3182 | |
3183 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3184 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3185 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3186 | |
8b6e50c9 BN |
3187 | /* |
3188 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3189 | * interface concerns can cause random data which looks like a |
3190 | * possibly credible NAND flash to appear. If the two results do | |
3191 | * not match, ignore the device completely. | |
3192 | */ | |
3193 | ||
3194 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3195 | ||
4aef9b78 BN |
3196 | /* Read entire ID string */ |
3197 | for (i = 0; i < 8; i++) | |
426c457a | 3198 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3199 | |
d1e1f4e4 | 3200 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
9a4d4d69 | 3201 | pr_info("%s: second ID read did not match " |
d0370219 BN |
3202 | "%02x,%02x against %02x,%02x\n", __func__, |
3203 | *maf_id, *dev_id, id_data[0], id_data[1]); | |
ed8165c7 BD |
3204 | return ERR_PTR(-ENODEV); |
3205 | } | |
3206 | ||
7aa65bfd | 3207 | if (!type) |
5e81e88a DW |
3208 | type = nand_flash_ids; |
3209 | ||
3210 | for (; type->name != NULL; type++) | |
d1e1f4e4 | 3211 | if (*dev_id == type->id) |
f8ac0414 | 3212 | break; |
5e81e88a | 3213 | |
d1e1f4e4 FF |
3214 | chip->onfi_version = 0; |
3215 | if (!type->name || !type->pagesize) { | |
6fb277ba | 3216 | /* Check is chip is ONFI compliant */ |
47450b35 | 3217 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3218 | goto ident_done; |
d1e1f4e4 FF |
3219 | } |
3220 | ||
5e81e88a | 3221 | if (!type->name) |
7aa65bfd TG |
3222 | return ERR_PTR(-ENODEV); |
3223 | ||
ba0251fe TG |
3224 | if (!mtd->name) |
3225 | mtd->name = type->name; | |
3226 | ||
69423d99 | 3227 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3228 | |
12a40a57 | 3229 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 3230 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
3231 | busw = chip->init_size(mtd, chip, id_data); |
3232 | } else if (!type->pagesize) { | |
fc09bbc0 BN |
3233 | /* Decode parameters from extended ID */ |
3234 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3235 | } else { |
f23a481c | 3236 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3237 | } |
bf7a01bf BN |
3238 | /* Get chip options */ |
3239 | chip->options |= type->options; | |
d1e1f4e4 | 3240 | |
8b6e50c9 BN |
3241 | /* |
3242 | * Check if chip is not a Samsung device. Do not clear the | |
3243 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3244 | */ |
3245 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3246 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3247 | ident_done: | |
3248 | ||
7aa65bfd | 3249 | /* Try to identify manufacturer */ |
9a909867 | 3250 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3251 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3252 | break; | |
3253 | } | |
0ea4a755 | 3254 | |
64b37b2a MC |
3255 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
3256 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
3257 | chip->options |= busw; | |
3258 | nand_set_defaults(chip, busw); | |
3259 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { | |
3260 | /* | |
3261 | * Check, if buswidth is correct. Hardware drivers should set | |
3262 | * chip correct! | |
3263 | */ | |
9a4d4d69 | 3264 | pr_info("NAND device: Manufacturer ID:" |
d0370219 BN |
3265 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, |
3266 | *dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
9a4d4d69 | 3267 | pr_warn("NAND bus width %d instead %d bit\n", |
d0370219 BN |
3268 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3269 | busw ? 16 : 8); | |
7aa65bfd TG |
3270 | return ERR_PTR(-EINVAL); |
3271 | } | |
61b03bd7 | 3272 | |
7e74c2d7 BN |
3273 | nand_decode_bbm_options(mtd, chip, id_data); |
3274 | ||
7aa65bfd | 3275 | /* Calculate the address shift from the page size */ |
ace4dfee | 3276 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3277 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3278 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3279 | |
ace4dfee | 3280 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3281 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3282 | if (chip->chipsize & 0xffffffff) |
3283 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3284 | else { |
3285 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3286 | chip->chip_shift += 32 - 1; | |
3287 | } | |
1da177e4 | 3288 | |
26d9be11 AB |
3289 | chip->badblockbits = 8; |
3290 | ||
7aa65bfd | 3291 | /* Check for AND chips with 4 page planes */ |
ace4dfee TG |
3292 | if (chip->options & NAND_4PAGE_ARRAY) |
3293 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 3294 | else |
ace4dfee | 3295 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd | 3296 | |
8b6e50c9 | 3297 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3298 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3299 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3300 | |
886bd33d | 3301 | pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s)," |
2fd71a29 | 3302 | " %dMiB, page size: %d, OOB size: %d\n", |
886bd33d HS |
3303 | *maf_id, *dev_id, nand_manuf_ids[maf_idx].name, |
3304 | chip->onfi_version ? chip->onfi_params.model : type->name, | |
2fd71a29 | 3305 | (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize); |
7aa65bfd TG |
3306 | |
3307 | return type; | |
3308 | } | |
3309 | ||
7aa65bfd | 3310 | /** |
3b85c321 | 3311 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3312 | * @mtd: MTD device structure |
3313 | * @maxchips: number of chips to scan for | |
3314 | * @table: alternative NAND ID table | |
7aa65bfd | 3315 | * |
8b6e50c9 BN |
3316 | * This is the first phase of the normal nand_scan() function. It reads the |
3317 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3318 | * |
3b85c321 | 3319 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3320 | */ |
5e81e88a DW |
3321 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3322 | struct nand_flash_dev *table) | |
7aa65bfd | 3323 | { |
d1e1f4e4 | 3324 | int i, busw, nand_maf_id, nand_dev_id; |
ace4dfee | 3325 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3326 | struct nand_flash_dev *type; |
3327 | ||
7aa65bfd | 3328 | /* Get buswidth to select the correct functions */ |
ace4dfee | 3329 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 3330 | /* Set the default functions */ |
ace4dfee | 3331 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
3332 | |
3333 | /* Read the flash type */ | |
7351d3a5 FF |
3334 | type = nand_get_flash_type(mtd, chip, busw, |
3335 | &nand_maf_id, &nand_dev_id, table); | |
7aa65bfd TG |
3336 | |
3337 | if (IS_ERR(type)) { | |
b1c6e6db | 3338 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3339 | pr_warn("No NAND device found\n"); |
ace4dfee | 3340 | chip->select_chip(mtd, -1); |
7aa65bfd | 3341 | return PTR_ERR(type); |
1da177e4 LT |
3342 | } |
3343 | ||
07300164 HS |
3344 | chip->select_chip(mtd, -1); |
3345 | ||
7aa65bfd | 3346 | /* Check for a chip array */ |
e0c7d767 | 3347 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3348 | chip->select_chip(mtd, i); |
ef89a880 KB |
3349 | /* See comment in nand_get_flash_type for reset */ |
3350 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3351 | /* Send the command for reading device ID */ |
ace4dfee | 3352 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3353 | /* Read manufacturer and device IDs */ |
ace4dfee | 3354 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
3355 | nand_dev_id != chip->read_byte(mtd)) { |
3356 | chip->select_chip(mtd, -1); | |
1da177e4 | 3357 | break; |
07300164 HS |
3358 | } |
3359 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
3360 | } |
3361 | if (i > 1) | |
9a4d4d69 | 3362 | pr_info("%d NAND chips detected\n", i); |
61b03bd7 | 3363 | |
1da177e4 | 3364 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3365 | chip->numchips = i; |
3366 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3367 | |
3b85c321 DW |
3368 | return 0; |
3369 | } | |
7351d3a5 | 3370 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 DW |
3371 | |
3372 | ||
3373 | /** | |
3374 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 3375 | * @mtd: MTD device structure |
3b85c321 | 3376 | * |
8b6e50c9 BN |
3377 | * This is the second phase of the normal nand_scan() function. It fills out |
3378 | * all the uninitialized function pointers with the defaults and scans for a | |
3379 | * bad block table if appropriate. | |
3b85c321 DW |
3380 | */ |
3381 | int nand_scan_tail(struct mtd_info *mtd) | |
3382 | { | |
3383 | int i; | |
3384 | struct nand_chip *chip = mtd->priv; | |
3385 | ||
e2414f4c BN |
3386 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
3387 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
3388 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
3389 | ||
4bf63fcb DW |
3390 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3391 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
3392 | if (!chip->buffers) | |
3393 | return -ENOMEM; | |
3394 | ||
7dcdcbef | 3395 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3396 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3397 | |
7aa65bfd | 3398 | /* |
8b6e50c9 | 3399 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 3400 | */ |
193bd400 | 3401 | if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3402 | switch (mtd->oobsize) { |
1da177e4 | 3403 | case 8: |
5bd34c09 | 3404 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
3405 | break; |
3406 | case 16: | |
5bd34c09 | 3407 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
3408 | break; |
3409 | case 64: | |
5bd34c09 | 3410 | chip->ecc.layout = &nand_oob_64; |
1da177e4 | 3411 | break; |
81ec5364 TG |
3412 | case 128: |
3413 | chip->ecc.layout = &nand_oob_128; | |
3414 | break; | |
1da177e4 | 3415 | default: |
d0370219 BN |
3416 | pr_warn("No oob scheme defined for oobsize %d\n", |
3417 | mtd->oobsize); | |
1da177e4 LT |
3418 | BUG(); |
3419 | } | |
3420 | } | |
61b03bd7 | 3421 | |
956e944c DW |
3422 | if (!chip->write_page) |
3423 | chip->write_page = nand_write_page; | |
3424 | ||
7db03ecc HS |
3425 | /* set for ONFI nand */ |
3426 | if (!chip->onfi_set_features) | |
3427 | chip->onfi_set_features = nand_onfi_set_features; | |
3428 | if (!chip->onfi_get_features) | |
3429 | chip->onfi_get_features = nand_onfi_get_features; | |
3430 | ||
61b03bd7 | 3431 | /* |
8b6e50c9 | 3432 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 3433 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 3434 | */ |
956e944c | 3435 | |
ace4dfee | 3436 | switch (chip->ecc.mode) { |
6e0cb135 SN |
3437 | case NAND_ECC_HW_OOB_FIRST: |
3438 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
3439 | if (!chip->ecc.calculate || !chip->ecc.correct || | |
3440 | !chip->ecc.hwctl) { | |
9a4d4d69 | 3441 | pr_warn("No ECC functions supplied; " |
d0370219 | 3442 | "hardware ECC not possible\n"); |
6e0cb135 SN |
3443 | BUG(); |
3444 | } | |
3445 | if (!chip->ecc.read_page) | |
3446 | chip->ecc.read_page = nand_read_page_hwecc_oob_first; | |
3447 | ||
6dfc6d25 | 3448 | case NAND_ECC_HW: |
8b6e50c9 | 3449 | /* Use standard hwecc read page function? */ |
f5bbdacc TG |
3450 | if (!chip->ecc.read_page) |
3451 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
3452 | if (!chip->ecc.write_page) |
3453 | chip->ecc.write_page = nand_write_page_hwecc; | |
52ff49df DB |
3454 | if (!chip->ecc.read_page_raw) |
3455 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3456 | if (!chip->ecc.write_page_raw) | |
3457 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3458 | if (!chip->ecc.read_oob) |
3459 | chip->ecc.read_oob = nand_read_oob_std; | |
3460 | if (!chip->ecc.write_oob) | |
3461 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 3462 | |
6dfc6d25 | 3463 | case NAND_ECC_HW_SYNDROME: |
78b65179 SW |
3464 | if ((!chip->ecc.calculate || !chip->ecc.correct || |
3465 | !chip->ecc.hwctl) && | |
3466 | (!chip->ecc.read_page || | |
1c45f604 | 3467 | chip->ecc.read_page == nand_read_page_hwecc || |
78b65179 | 3468 | !chip->ecc.write_page || |
1c45f604 | 3469 | chip->ecc.write_page == nand_write_page_hwecc)) { |
9a4d4d69 | 3470 | pr_warn("No ECC functions supplied; " |
d0370219 | 3471 | "hardware ECC not possible\n"); |
6dfc6d25 TG |
3472 | BUG(); |
3473 | } | |
8b6e50c9 | 3474 | /* Use standard syndrome read/write page function? */ |
f5bbdacc TG |
3475 | if (!chip->ecc.read_page) |
3476 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
3477 | if (!chip->ecc.write_page) |
3478 | chip->ecc.write_page = nand_write_page_syndrome; | |
52ff49df DB |
3479 | if (!chip->ecc.read_page_raw) |
3480 | chip->ecc.read_page_raw = nand_read_page_raw_syndrome; | |
3481 | if (!chip->ecc.write_page_raw) | |
3482 | chip->ecc.write_page_raw = nand_write_page_raw_syndrome; | |
7bc3312b TG |
3483 | if (!chip->ecc.read_oob) |
3484 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
3485 | if (!chip->ecc.write_oob) | |
3486 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 3487 | |
e2788c98 MD |
3488 | if (mtd->writesize >= chip->ecc.size) { |
3489 | if (!chip->ecc.strength) { | |
3490 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); | |
3491 | BUG(); | |
3492 | } | |
6dfc6d25 | 3493 | break; |
e2788c98 | 3494 | } |
9a4d4d69 | 3495 | pr_warn("%d byte HW ECC not possible on " |
d0370219 BN |
3496 | "%d byte page size, fallback to SW ECC\n", |
3497 | chip->ecc.size, mtd->writesize); | |
ace4dfee | 3498 | chip->ecc.mode = NAND_ECC_SOFT; |
61b03bd7 | 3499 | |
6dfc6d25 | 3500 | case NAND_ECC_SOFT: |
ace4dfee TG |
3501 | chip->ecc.calculate = nand_calculate_ecc; |
3502 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 3503 | chip->ecc.read_page = nand_read_page_swecc; |
3d459559 | 3504 | chip->ecc.read_subpage = nand_read_subpage; |
f75e5097 | 3505 | chip->ecc.write_page = nand_write_page_swecc; |
52ff49df DB |
3506 | chip->ecc.read_page_raw = nand_read_page_raw; |
3507 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3508 | chip->ecc.read_oob = nand_read_oob_std; |
3509 | chip->ecc.write_oob = nand_write_oob_std; | |
9a73290d SV |
3510 | if (!chip->ecc.size) |
3511 | chip->ecc.size = 256; | |
ace4dfee | 3512 | chip->ecc.bytes = 3; |
6a918bad | 3513 | chip->ecc.strength = 1; |
1da177e4 | 3514 | break; |
61b03bd7 | 3515 | |
193bd400 ID |
3516 | case NAND_ECC_SOFT_BCH: |
3517 | if (!mtd_nand_has_bch()) { | |
9a4d4d69 | 3518 | pr_warn("CONFIG_MTD_ECC_BCH not enabled\n"); |
193bd400 ID |
3519 | BUG(); |
3520 | } | |
3521 | chip->ecc.calculate = nand_bch_calculate_ecc; | |
3522 | chip->ecc.correct = nand_bch_correct_data; | |
3523 | chip->ecc.read_page = nand_read_page_swecc; | |
3524 | chip->ecc.read_subpage = nand_read_subpage; | |
3525 | chip->ecc.write_page = nand_write_page_swecc; | |
3526 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3527 | chip->ecc.write_page_raw = nand_write_page_raw; | |
3528 | chip->ecc.read_oob = nand_read_oob_std; | |
3529 | chip->ecc.write_oob = nand_write_oob_std; | |
3530 | /* | |
3531 | * Board driver should supply ecc.size and ecc.bytes values to | |
3532 | * select how many bits are correctable; see nand_bch_init() | |
8b6e50c9 BN |
3533 | * for details. Otherwise, default to 4 bits for large page |
3534 | * devices. | |
193bd400 ID |
3535 | */ |
3536 | if (!chip->ecc.size && (mtd->oobsize >= 64)) { | |
3537 | chip->ecc.size = 512; | |
3538 | chip->ecc.bytes = 7; | |
3539 | } | |
3540 | chip->ecc.priv = nand_bch_init(mtd, | |
3541 | chip->ecc.size, | |
3542 | chip->ecc.bytes, | |
3543 | &chip->ecc.layout); | |
3544 | if (!chip->ecc.priv) { | |
9a4d4d69 | 3545 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
3546 | BUG(); |
3547 | } | |
6a918bad | 3548 | chip->ecc.strength = |
e2788c98 | 3549 | chip->ecc.bytes * 8 / fls(8 * chip->ecc.size); |
193bd400 ID |
3550 | break; |
3551 | ||
61b03bd7 | 3552 | case NAND_ECC_NONE: |
9a4d4d69 | 3553 | pr_warn("NAND_ECC_NONE selected by board driver. " |
d0370219 | 3554 | "This is not recommended!\n"); |
8593fbc6 TG |
3555 | chip->ecc.read_page = nand_read_page_raw; |
3556 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b | 3557 | chip->ecc.read_oob = nand_read_oob_std; |
52ff49df DB |
3558 | chip->ecc.read_page_raw = nand_read_page_raw; |
3559 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b | 3560 | chip->ecc.write_oob = nand_write_oob_std; |
ace4dfee TG |
3561 | chip->ecc.size = mtd->writesize; |
3562 | chip->ecc.bytes = 0; | |
6a918bad | 3563 | chip->ecc.strength = 0; |
1da177e4 | 3564 | break; |
956e944c | 3565 | |
1da177e4 | 3566 | default: |
d0370219 | 3567 | pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode); |
61b03bd7 | 3568 | BUG(); |
1da177e4 | 3569 | } |
61b03bd7 | 3570 | |
9ce244b3 | 3571 | /* For many systems, the standard OOB write also works for raw */ |
c46f6483 BN |
3572 | if (!chip->ecc.read_oob_raw) |
3573 | chip->ecc.read_oob_raw = chip->ecc.read_oob; | |
9ce244b3 BN |
3574 | if (!chip->ecc.write_oob_raw) |
3575 | chip->ecc.write_oob_raw = chip->ecc.write_oob; | |
3576 | ||
5bd34c09 TG |
3577 | /* |
3578 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 3579 | * the out of band area. |
5bd34c09 TG |
3580 | */ |
3581 | chip->ecc.layout->oobavail = 0; | |
81d19b04 DB |
3582 | for (i = 0; chip->ecc.layout->oobfree[i].length |
3583 | && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) | |
5bd34c09 TG |
3584 | chip->ecc.layout->oobavail += |
3585 | chip->ecc.layout->oobfree[i].length; | |
1f92267c | 3586 | mtd->oobavail = chip->ecc.layout->oobavail; |
5bd34c09 | 3587 | |
7aa65bfd TG |
3588 | /* |
3589 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 3590 | * mode. |
7aa65bfd | 3591 | */ |
ace4dfee | 3592 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
f8ac0414 | 3593 | if (chip->ecc.steps * chip->ecc.size != mtd->writesize) { |
9a4d4d69 | 3594 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 3595 | BUG(); |
1da177e4 | 3596 | } |
f5bbdacc | 3597 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 3598 | |
8b6e50c9 | 3599 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
29072b96 TG |
3600 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && |
3601 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
f8ac0414 | 3602 | switch (chip->ecc.steps) { |
29072b96 TG |
3603 | case 2: |
3604 | mtd->subpage_sft = 1; | |
3605 | break; | |
3606 | case 4: | |
3607 | case 8: | |
81ec5364 | 3608 | case 16: |
29072b96 TG |
3609 | mtd->subpage_sft = 2; |
3610 | break; | |
3611 | } | |
3612 | } | |
3613 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
3614 | ||
04bbd0ea | 3615 | /* Initialize state */ |
ace4dfee | 3616 | chip->state = FL_READY; |
1da177e4 | 3617 | |
1da177e4 | 3618 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 3619 | chip->pagebuf = -1; |
1da177e4 | 3620 | |
a5ff4f10 JW |
3621 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
3622 | if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9)) | |
3623 | chip->options |= NAND_SUBPAGE_READ; | |
3624 | ||
1da177e4 LT |
3625 | /* Fill in remaining MTD driver data */ |
3626 | mtd->type = MTD_NANDFLASH; | |
93edbad6 ML |
3627 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
3628 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
3629 | mtd->_erase = nand_erase; |
3630 | mtd->_point = NULL; | |
3631 | mtd->_unpoint = NULL; | |
3632 | mtd->_read = nand_read; | |
3633 | mtd->_write = nand_write; | |
3634 | mtd->_panic_write = panic_nand_write; | |
3635 | mtd->_read_oob = nand_read_oob; | |
3636 | mtd->_write_oob = nand_write_oob; | |
3637 | mtd->_sync = nand_sync; | |
3638 | mtd->_lock = NULL; | |
3639 | mtd->_unlock = NULL; | |
3640 | mtd->_suspend = nand_suspend; | |
3641 | mtd->_resume = nand_resume; | |
3642 | mtd->_block_isbad = nand_block_isbad; | |
3643 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 3644 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 3645 | |
6a918bad | 3646 | /* propagate ecc info to mtd_info */ |
5bd34c09 | 3647 | mtd->ecclayout = chip->ecc.layout; |
86c2072b | 3648 | mtd->ecc_strength = chip->ecc.strength; |
ea3b2ea2 SL |
3649 | /* |
3650 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
3651 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
3652 | * properly set. | |
3653 | */ | |
3654 | if (!mtd->bitflip_threshold) | |
3655 | mtd->bitflip_threshold = mtd->ecc_strength; | |
1da177e4 | 3656 | |
0040bf38 | 3657 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 3658 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 3659 | return 0; |
1da177e4 LT |
3660 | |
3661 | /* Build bad block table */ | |
ace4dfee | 3662 | return chip->scan_bbt(mtd); |
1da177e4 | 3663 | } |
7351d3a5 | 3664 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 3665 | |
8b6e50c9 BN |
3666 | /* |
3667 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 3668 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
3669 | * to call us from in-kernel code if the core NAND support is modular. |
3670 | */ | |
3b85c321 DW |
3671 | #ifdef MODULE |
3672 | #define caller_is_module() (1) | |
3673 | #else | |
3674 | #define caller_is_module() \ | |
a6e6abd5 | 3675 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
3676 | #endif |
3677 | ||
3678 | /** | |
3679 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
3680 | * @mtd: MTD device structure |
3681 | * @maxchips: number of chips to scan for | |
3b85c321 | 3682 | * |
8b6e50c9 BN |
3683 | * This fills out all the uninitialized function pointers with the defaults. |
3684 | * The flash ID is read and the mtd/chip structures are filled with the | |
3685 | * appropriate values. The mtd->owner field must be set to the module of the | |
3686 | * caller. | |
3b85c321 DW |
3687 | */ |
3688 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
3689 | { | |
3690 | int ret; | |
3691 | ||
3692 | /* Many callers got this wrong, so check for it for a while... */ | |
3693 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 3694 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
3695 | BUG(); |
3696 | } | |
3697 | ||
5e81e88a | 3698 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
3699 | if (!ret) |
3700 | ret = nand_scan_tail(mtd); | |
3701 | return ret; | |
3702 | } | |
7351d3a5 | 3703 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 3704 | |
1da177e4 | 3705 | /** |
61b03bd7 | 3706 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
3707 | * @mtd: MTD device structure |
3708 | */ | |
e0c7d767 | 3709 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 3710 | { |
ace4dfee | 3711 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 3712 | |
193bd400 ID |
3713 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
3714 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
3715 | ||
5ffcaf3d | 3716 | mtd_device_unregister(mtd); |
1da177e4 | 3717 | |
fa671646 | 3718 | /* Free bad block table memory */ |
ace4dfee | 3719 | kfree(chip->bbt); |
4bf63fcb DW |
3720 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3721 | kfree(chip->buffers); | |
58373ff0 BN |
3722 | |
3723 | /* Free bad block descriptor memory */ | |
3724 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
3725 | & NAND_BBT_DYNAMICSTRUCT) | |
3726 | kfree(chip->badblock_pattern); | |
1da177e4 | 3727 | } |
e0c7d767 | 3728 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
3729 | |
3730 | static int __init nand_base_init(void) | |
3731 | { | |
3732 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
3733 | return 0; | |
3734 | } | |
3735 | ||
3736 | static void __exit nand_base_exit(void) | |
3737 | { | |
3738 | led_trigger_unregister_simple(nand_led_trigger); | |
3739 | } | |
3740 | ||
3741 | module_init(nand_base_init); | |
3742 | module_exit(nand_base_exit); | |
3743 | ||
e0c7d767 | 3744 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
3745 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
3746 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 3747 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |