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Merge tag 'iwlwifi-next-for-kalle-2016-01-31_2' of https://git.kernel.org/pub/scm...
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Overview:
3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
61b03bd7 5 *
1da177e4 6 * Additional technical information is available on
8b2b403c 7 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 8 *
1da177e4 9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 11 *
ace4dfee 12 * Credits:
61b03bd7
TG		 13 * David Woodhouse for adding multichip support
14 *
1da177e4
LT		 15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
17 *
ace4dfee 18 * TODO:
1da177e4
LT		 19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 21 * if we have HW ECC support.
c0b8ba7b 22 * BBT table is not serialized, has to be fixed
1da177e4 23 *
1da177e4
LT		 24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
20171642
EG		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
552d9205 32#include <linux/module.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/errno.h>
7aa65bfd 35#include <linux/err.h>
1da177e4
LT		 36#include <linux/sched.h>
37#include <linux/slab.h>
66507c7b 38#include <linux/mm.h>
1da177e4
LT		 39#include <linux/types.h>
40#include <linux/mtd/mtd.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/nand_ecc.h>
193bd400 43#include <linux/mtd/nand_bch.h>
1da177e4
LT		 44#include <linux/interrupt.h>
45#include <linux/bitops.h>
8fe833c1 46#include <linux/leds.h>
7351d3a5 47#include <linux/io.h>
1da177e4 48#include <linux/mtd/partitions.h>
5844feea 49#include <linux/of_mtd.h>
1da177e4
LT		 50
51/* Define default oob placement schemes for large and small page devices */
5bd34c09 52static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 53 .eccbytes = 3,
54 .eccpos = {0, 1, 2},
5bd34c09
TG		 55 .oobfree = {
56 {.offset = 3,
57 .length = 2},
58 {.offset = 6,
f8ac0414 59 .length = 2} }
1da177e4
LT		 60};
61
5bd34c09 62static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 63 .eccbytes = 6,
64 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 65 .oobfree = {
66 {.offset = 8,
f8ac0414 67 . length = 8} }
1da177e4
LT		 68};
69
5bd34c09 70static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 71 .eccbytes = 24,
72 .eccpos = {
e0c7d767
DW		 73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 76 .oobfree = {
77 {.offset = 2,
f8ac0414 78 .length = 38} }
1da177e4
LT		 79};
80
81ec5364
TG		 81static struct nand_ecclayout nand_oob_128 = {
82 .eccbytes = 48,
83 .eccpos = {
84 80, 81, 82, 83, 84, 85, 86, 87,
85 88, 89, 90, 91, 92, 93, 94, 95,
86 96, 97, 98, 99, 100, 101, 102, 103,
87 104, 105, 106, 107, 108, 109, 110, 111,
88 112, 113, 114, 115, 116, 117, 118, 119,
89 120, 121, 122, 123, 124, 125, 126, 127},
90 .oobfree = {
91 {.offset = 2,
f8ac0414 92 .length = 78} }
81ec5364
TG		 93};
94
6a8214aa 95static int nand_get_device(struct mtd_info *mtd, int new_state);
1da177e4 96
8593fbc6
TG		 97static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
98 struct mtd_oob_ops *ops);
99
d470a97c 100/*
8e87d782 101 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 102 * compiled away when LED support is disabled.
103 */
104DEFINE_LED_TRIGGER(nand_led_trigger);
105
6fe5a6ac
VS		 106static int check_offs_len(struct mtd_info *mtd,
107 loff_t ofs, uint64_t len)
108{
862eba51 109 struct nand_chip *chip = mtd_to_nand(mtd);
6fe5a6ac
VS		 110 int ret = 0;
111
112 /* Start address must align on block boundary */
daae74ca 113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 114 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 115 ret = -EINVAL;
116 }
117
118 /* Length must align on block boundary */
daae74ca 119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 120 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 121 ret = -EINVAL;
122 }
123
6fe5a6ac
VS		 124 return ret;
125}
126
1da177e4
LT		 127/**
128 * nand_release_device - [GENERIC] release chip
8b6e50c9 129 * @mtd: MTD device structure
61b03bd7 130 *
b0bb6903 131 * Release chip lock and wake up anyone waiting on the device.
1da177e4 132 */
e0c7d767 133static void nand_release_device(struct mtd_info *mtd)
1da177e4 134{
862eba51 135 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 136
a36ed299 137 /* Release the controller and the chip */
ace4dfee
TG		 138 spin_lock(&chip->controller->lock);
139 chip->controller->active = NULL;
140 chip->state = FL_READY;
141 wake_up(&chip->controller->wq);
142 spin_unlock(&chip->controller->lock);
1da177e4
LT		 143}
144
145/**
146 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 147 * @mtd: MTD device structure
1da177e4 148 *
7854d3f7 149 * Default read function for 8bit buswidth
1da177e4 150 */
58dd8f2b 151static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 152{
862eba51 153 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 154 return readb(chip->IO_ADDR_R);
1da177e4
LT		 155}
156
1da177e4 157/**
7854d3f7 158 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 159 * @mtd: MTD device structure
1da177e4 160 *
7854d3f7
BN		 161 * Default read function for 16bit buswidth with endianness conversion.
162 *
1da177e4 163 */
58dd8f2b 164static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 165{
862eba51 166 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 167 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 168}
169
1da177e4
LT		 170/**
171 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 172 * @mtd: MTD device structure
1da177e4 173 *
7854d3f7 174 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 175 */
176static u16 nand_read_word(struct mtd_info *mtd)
177{
862eba51 178 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 179 return readw(chip->IO_ADDR_R);
1da177e4
LT		 180}
181
1da177e4
LT		 182/**
183 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 184 * @mtd: MTD device structure
185 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 186 *
187 * Default select function for 1 chip devices.
188 */
ace4dfee 189static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 190{
862eba51 191 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee
TG		 192
193 switch (chipnr) {
1da177e4 194 case -1:
ace4dfee 195 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 196 break;
197 case 0:
1da177e4
LT		 198 break;
199
200 default:
201 BUG();
202 }
203}
204
05f78359
UKK		 205/**
206 * nand_write_byte - [DEFAULT] write single byte to chip
207 * @mtd: MTD device structure
208 * @byte: value to write
209 *
210 * Default function to write a byte to I/O[7:0]
211 */
212static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
213{
862eba51 214 struct nand_chip *chip = mtd_to_nand(mtd);
05f78359
UKK		 215
216 chip->write_buf(mtd, &byte, 1);
217}
218
219/**
220 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
221 * @mtd: MTD device structure
222 * @byte: value to write
223 *
224 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
225 */
226static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
227{
862eba51 228 struct nand_chip *chip = mtd_to_nand(mtd);
05f78359
UKK		 229 uint16_t word = byte;
230
231 /*
232 * It's not entirely clear what should happen to I/O[15:8] when writing
233 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
234 *
235 * When the host supports a 16-bit bus width, only data is
236 * transferred at the 16-bit width. All address and command line
237 * transfers shall use only the lower 8-bits of the data bus. During
238 * command transfers, the host may place any value on the upper
239 * 8-bits of the data bus. During address transfers, the host shall
240 * set the upper 8-bits of the data bus to 00h.
241 *
242 * One user of the write_byte callback is nand_onfi_set_features. The
243 * four parameters are specified to be written to I/O[7:0], but this is
244 * neither an address nor a command transfer. Let's assume a 0 on the
245 * upper I/O lines is OK.
246 */
247 chip->write_buf(mtd, (uint8_t *)&word, 2);
248}
249
1da177e4
LT		 250/**
251 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 252 * @mtd: MTD device structure
253 * @buf: data buffer
254 * @len: number of bytes to write
1da177e4 255 *
7854d3f7 256 * Default write function for 8bit buswidth.
1da177e4 257 */
58dd8f2b 258static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 259{
862eba51 260 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 261
76413839 262 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 263}
264
265/**
61b03bd7 266 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 267 * @mtd: MTD device structure
268 * @buf: buffer to store date
269 * @len: number of bytes to read
1da177e4 270 *
7854d3f7 271 * Default read function for 8bit buswidth.
1da177e4 272 */
58dd8f2b 273static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 274{
862eba51 275 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 276
76413839 277 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 278}
279
1da177e4
LT		 280/**
281 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 282 * @mtd: MTD device structure
283 * @buf: data buffer
284 * @len: number of bytes to write
1da177e4 285 *
7854d3f7 286 * Default write function for 16bit buswidth.
1da177e4 287 */
58dd8f2b 288static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 289{
862eba51 290 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 291 u16 *p = (u16 *) buf;
61b03bd7 292
76413839 293 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 294}
295
296/**
61b03bd7 297 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 298 * @mtd: MTD device structure
299 * @buf: buffer to store date
300 * @len: number of bytes to read
1da177e4 301 *
7854d3f7 302 * Default read function for 16bit buswidth.
1da177e4 303 */
58dd8f2b 304static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 305{
862eba51 306 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 307 u16 *p = (u16 *) buf;
1da177e4 308
76413839 309 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 310}
311
1da177e4
LT		 312/**
313 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 314 * @mtd: MTD device structure
315 * @ofs: offset from device start
316 * @getchip: 0, if the chip is already selected
1da177e4 317 *
61b03bd7 318 * Check, if the block is bad.
1da177e4
LT		 319 */
320static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
321{
cdbec050 322 int page, chipnr, res = 0, i = 0;
862eba51 323 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4
LT		 324 u16 bad;
325
5fb1549d 326 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 327 ofs += mtd->erasesize - mtd->writesize;
328
1a12f46a
TK		 329 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
330
1da177e4 331 if (getchip) {
ace4dfee 332 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 333
6a8214aa 334 nand_get_device(mtd, FL_READING);
1da177e4
LT		 335
336 /* Select the NAND device */
ace4dfee 337 chip->select_chip(mtd, chipnr);
1a12f46a 338 }
1da177e4 339
cdbec050
BN		 340 do {
341 if (chip->options & NAND_BUSWIDTH_16) {
342 chip->cmdfunc(mtd, NAND_CMD_READOOB,
343 chip->badblockpos & 0xFE, page);
344 bad = cpu_to_le16(chip->read_word(mtd));
345 if (chip->badblockpos & 0x1)
346 bad >>= 8;
347 else
348 bad &= 0xFF;
349 } else {
350 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
351 page);
352 bad = chip->read_byte(mtd);
353 }
354
355 if (likely(chip->badblockbits == 8))
356 res = bad != 0xFF;
e0b58d0a 357 else
cdbec050
BN		 358 res = hweight8(bad) < chip->badblockbits;
359 ofs += mtd->writesize;
360 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
361 i++;
362 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 363
b0bb6903
HS		 364 if (getchip) {
365 chip->select_chip(mtd, -1);
1da177e4 366 nand_release_device(mtd);
b0bb6903 367 }
61b03bd7 368
1da177e4
LT		 369 return res;
370}
371
372/**
5a0edb25 373 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
8b6e50c9
BN		 374 * @mtd: MTD device structure
375 * @ofs: offset from device start
1da177e4 376 *
8b6e50c9 377 * This is the default implementation, which can be overridden by a hardware
5a0edb25
BN		 378 * specific driver. It provides the details for writing a bad block marker to a
379 * block.
380 */
381static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
382{
862eba51 383 struct nand_chip *chip = mtd_to_nand(mtd);
5a0edb25
BN		 384 struct mtd_oob_ops ops;
385 uint8_t buf[2] = { 0, 0 };
386 int ret = 0, res, i = 0;
387
0ec56dc4 388 memset(&ops, 0, sizeof(ops));
5a0edb25
BN		 389 ops.oobbuf = buf;
390 ops.ooboffs = chip->badblockpos;
391 if (chip->options & NAND_BUSWIDTH_16) {
392 ops.ooboffs &= ~0x01;
393 ops.len = ops.ooblen = 2;
394 } else {
395 ops.len = ops.ooblen = 1;
396 }
397 ops.mode = MTD_OPS_PLACE_OOB;
398
399 /* Write to first/last page(s) if necessary */
400 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
401 ofs += mtd->erasesize - mtd->writesize;
402 do {
403 res = nand_do_write_oob(mtd, ofs, &ops);
404 if (!ret)
405 ret = res;
406
407 i++;
408 ofs += mtd->writesize;
409 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
410
411 return ret;
412}
413
414/**
415 * nand_block_markbad_lowlevel - mark a block bad
416 * @mtd: MTD device structure
417 * @ofs: offset from device start
418 *
419 * This function performs the generic NAND bad block marking steps (i.e., bad
420 * block table(s) and/or marker(s)). We only allow the hardware driver to
421 * specify how to write bad block markers to OOB (chip->block_markbad).
422 *
b32843b7 423 * We try operations in the following order:
e2414f4c 424 * (1) erase the affected block, to allow OOB marker to be written cleanly
b32843b7
BN		 425 * (2) write bad block marker to OOB area of affected block (unless flag
426 * NAND_BBT_NO_OOB_BBM is present)
427 * (3) update the BBT
428 * Note that we retain the first error encountered in (2) or (3), finish the
e2414f4c 429 * procedures, and dump the error in the end.
1da177e4 430*/
5a0edb25 431static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
1da177e4 432{
862eba51 433 struct nand_chip *chip = mtd_to_nand(mtd);
b32843b7 434 int res, ret = 0;
61b03bd7 435
b32843b7 436 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
00918429
BN		 437 struct erase_info einfo;
438
439 /* Attempt erase before marking OOB */
440 memset(&einfo, 0, sizeof(einfo));
441 einfo.mtd = mtd;
442 einfo.addr = ofs;
daae74ca 443 einfo.len = 1ULL << chip->phys_erase_shift;
00918429 444 nand_erase_nand(mtd, &einfo, 0);
1da177e4 445
b32843b7 446 /* Write bad block marker to OOB */
6a8214aa 447 nand_get_device(mtd, FL_WRITING);
5a0edb25 448 ret = chip->block_markbad(mtd, ofs);
c0b8ba7b 449 nand_release_device(mtd);
f1a28c02 450 }
e2414f4c 451
b32843b7
BN		 452 /* Mark block bad in BBT */
453 if (chip->bbt) {
454 res = nand_markbad_bbt(mtd, ofs);
e2414f4c
BN		 455 if (!ret)
456 ret = res;
457 }
458
f1a28c02
TG		 459 if (!ret)
460 mtd->ecc_stats.badblocks++;
c0b8ba7b 461
f1a28c02 462 return ret;
1da177e4
LT		 463}
464
61b03bd7 465/**
1da177e4 466 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 467 * @mtd: MTD device structure
1da177e4 468 *
8b6e50c9
BN		 469 * Check, if the device is write protected. The function expects, that the
470 * device is already selected.
1da177e4 471 */
e0c7d767 472static int nand_check_wp(struct mtd_info *mtd)
1da177e4 473{
862eba51 474 struct nand_chip *chip = mtd_to_nand(mtd);
93edbad6 475
8b6e50c9 476 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 477 if (chip->options & NAND_BROKEN_XD)
478 return 0;
479
1da177e4 480 /* Check the WP bit */
ace4dfee
TG		 481 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
482 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 483}
484
8471bb73 485/**
c30e1f79 486 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
8471bb73
EG		 487 * @mtd: MTD device structure
488 * @ofs: offset from device start
489 *
c30e1f79 490 * Check if the block is marked as reserved.
8471bb73
EG		 491 */
492static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
493{
862eba51 494 struct nand_chip *chip = mtd_to_nand(mtd);
8471bb73
EG		 495
496 if (!chip->bbt)
497 return 0;
498 /* Return info from the table */
499 return nand_isreserved_bbt(mtd, ofs);
500}
501
1da177e4
LT		 502/**
503 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 504 * @mtd: MTD device structure
505 * @ofs: offset from device start
506 * @getchip: 0, if the chip is already selected
507 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 508 *
509 * Check, if the block is bad. Either by reading the bad block table or
510 * calling of the scan function.
511 */
2c0a2bed
TG		 512static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
513 int allowbbt)
1da177e4 514{
862eba51 515 struct nand_chip *chip = mtd_to_nand(mtd);
61b03bd7 516
ace4dfee
TG		 517 if (!chip->bbt)
518 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 519
1da177e4 520 /* Return info from the table */
e0c7d767 521 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 522}
523
2af7c653
SK		 524/**
525 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 526 * @mtd: MTD device structure
527 * @timeo: Timeout
2af7c653
SK		 528 *
529 * Helper function for nand_wait_ready used when needing to wait in interrupt
530 * context.
531 */
532static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
533{
862eba51 534 struct nand_chip *chip = mtd_to_nand(mtd);
2af7c653
SK		 535 int i;
536
537 /* Wait for the device to get ready */
538 for (i = 0; i < timeo; i++) {
539 if (chip->dev_ready(mtd))
540 break;
541 touch_softlockup_watchdog();
542 mdelay(1);
543 }
544}
545
b70af9be
AS		 546/**
547 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
548 * @mtd: MTD device structure
549 *
550 * Wait for the ready pin after a command, and warn if a timeout occurs.
551 */
4b648b02 552void nand_wait_ready(struct mtd_info *mtd)
3b88775c 553{
862eba51 554 struct nand_chip *chip = mtd_to_nand(mtd);
b70af9be 555 unsigned long timeo = 400;
3b88775c 556
2af7c653 557 if (in_interrupt() || oops_in_progress)
b70af9be 558 return panic_nand_wait_ready(mtd, timeo);
2af7c653 559
8fe833c1 560 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 561 /* Wait until command is processed or timeout occurs */
b70af9be 562 timeo = jiffies + msecs_to_jiffies(timeo);
3b88775c 563 do {
ace4dfee 564 if (chip->dev_ready(mtd))
b70af9be
AS		 565 goto out;
566 cond_resched();
61b03bd7 567 } while (time_before(jiffies, timeo));
b70af9be
AS		 568
569 pr_warn_ratelimited(
570 "timeout while waiting for chip to become ready\n");
571out:
8fe833c1 572 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 573}
4b648b02 574EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 575
60c70d66
RQ		 576/**
577 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
578 * @mtd: MTD device structure
579 * @timeo: Timeout in ms
580 *
581 * Wait for status ready (i.e. command done) or timeout.
582 */
583static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
584{
862eba51 585 register struct nand_chip *chip = mtd_to_nand(mtd);
60c70d66
RQ		 586
587 timeo = jiffies + msecs_to_jiffies(timeo);
588 do {
589 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
590 break;
591 touch_softlockup_watchdog();
592 } while (time_before(jiffies, timeo));
593};
594
1da177e4
LT		 595/**
596 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 597 * @mtd: MTD device structure
598 * @command: the command to be sent
599 * @column: the column address for this command, -1 if none
600 * @page_addr: the page address for this command, -1 if none
1da177e4 601 *
8b6e50c9 602 * Send command to NAND device. This function is used for small page devices
51148f1f 603 * (512 Bytes per page).
1da177e4 604 */
7abd3ef9
TG		 605static void nand_command(struct mtd_info *mtd, unsigned int command,
606 int column, int page_addr)
1da177e4 607{
862eba51 608 register struct nand_chip *chip = mtd_to_nand(mtd);
7abd3ef9 609 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 610
8b6e50c9 611 /* Write out the command to the device */
1da177e4
LT		 612 if (command == NAND_CMD_SEQIN) {
613 int readcmd;
614
28318776 615 if (column >= mtd->writesize) {
1da177e4 616 /* OOB area */
28318776 617 column -= mtd->writesize;
1da177e4
LT		 618 readcmd = NAND_CMD_READOOB;
619 } else if (column < 256) {
620 /* First 256 bytes --> READ0 */
621 readcmd = NAND_CMD_READ0;
622 } else {
623 column -= 256;
624 readcmd = NAND_CMD_READ1;
625 }
ace4dfee 626 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 627 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 628 }
ace4dfee 629 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 630
8b6e50c9 631 /* Address cycle, when necessary */
7abd3ef9
TG		 632 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
633 /* Serially input address */
634 if (column != -1) {
635 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 636 if (chip->options & NAND_BUSWIDTH_16 &&
637 !nand_opcode_8bits(command))
7abd3ef9 638 column >>= 1;
ace4dfee 639 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 640 ctrl &= ~NAND_CTRL_CHANGE;
641 }
642 if (page_addr != -1) {
ace4dfee 643 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 644 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 645 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 646 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 647 if (chip->chipsize > (32 << 20))
648 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 649 }
ace4dfee 650 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 651
652 /*
8b6e50c9
BN		 653 * Program and erase have their own busy handlers status and sequential
654 * in needs no delay
e0c7d767 655 */
1da177e4 656 switch (command) {
61b03bd7 657
1da177e4
LT		 658 case NAND_CMD_PAGEPROG:
659 case NAND_CMD_ERASE1:
660 case NAND_CMD_ERASE2:
661 case NAND_CMD_SEQIN:
662 case NAND_CMD_STATUS:
663 return;
664
665 case NAND_CMD_RESET:
ace4dfee 666 if (chip->dev_ready)
1da177e4 667 break;
ace4dfee
TG		 668 udelay(chip->chip_delay);
669 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 670 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 671 chip->cmd_ctrl(mtd,
672 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 673 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
674 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 675 return;
676
e0c7d767 677 /* This applies to read commands */
1da177e4 678 default:
61b03bd7 679 /*
1da177e4
LT		 680 * If we don't have access to the busy pin, we apply the given
681 * command delay
e0c7d767 682 */
ace4dfee
TG		 683 if (!chip->dev_ready) {
684 udelay(chip->chip_delay);
1da177e4 685 return;
61b03bd7 686 }
1da177e4 687 }
8b6e50c9
BN		 688 /*
689 * Apply this short delay always to ensure that we do wait tWB in
690 * any case on any machine.
691 */
e0c7d767 692 ndelay(100);
3b88775c
TG		 693
694 nand_wait_ready(mtd);
1da177e4
LT		 695}
696
697/**
698 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 699 * @mtd: MTD device structure
700 * @command: the command to be sent
701 * @column: the column address for this command, -1 if none
702 * @page_addr: the page address for this command, -1 if none
1da177e4 703 *
7abd3ef9 704 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 705 * devices. We don't have the separate regions as we have in the small page
706 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 707 */
7abd3ef9
TG		 708static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
709 int column, int page_addr)
1da177e4 710{
862eba51 711 register struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4
LT		 712
713 /* Emulate NAND_CMD_READOOB */
714 if (command == NAND_CMD_READOOB) {
28318776 715 column += mtd->writesize;
1da177e4
LT		 716 command = NAND_CMD_READ0;
717 }
61b03bd7 718
7abd3ef9 719 /* Command latch cycle */
fb066ada 720 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 721
722 if (column != -1 || page_addr != -1) {
7abd3ef9 723 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 724
725 /* Serially input address */
726 if (column != -1) {
727 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 728 if (chip->options & NAND_BUSWIDTH_16 &&
729 !nand_opcode_8bits(command))
1da177e4 730 column >>= 1;
ace4dfee 731 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 732 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 733 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 734 }
1da177e4 735 if (page_addr != -1) {
ace4dfee
TG		 736 chip->cmd_ctrl(mtd, page_addr, ctrl);
737 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 738 NAND_NCE | NAND_ALE);
1da177e4 739 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 740 if (chip->chipsize > (128 << 20))
741 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 742 NAND_NCE | NAND_ALE);
1da177e4 743 }
1da177e4 744 }
ace4dfee 745 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 746
747 /*
8b6e50c9 748 * Program and erase have their own busy handlers status, sequential
7a442f17 749 * in and status need no delay.
30f464b7 750 */
1da177e4 751 switch (command) {
61b03bd7 752
1da177e4
LT		 753 case NAND_CMD_CACHEDPROG:
754 case NAND_CMD_PAGEPROG:
755 case NAND_CMD_ERASE1:
756 case NAND_CMD_ERASE2:
757 case NAND_CMD_SEQIN:
7bc3312b 758 case NAND_CMD_RNDIN:
1da177e4 759 case NAND_CMD_STATUS:
30f464b7 760 return;
1da177e4
LT		 761
762 case NAND_CMD_RESET:
ace4dfee 763 if (chip->dev_ready)
1da177e4 764 break;
ace4dfee 765 udelay(chip->chip_delay);
12efdde3
TG		 766 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
767 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
768 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
769 NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 770 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
771 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 772 return;
773
7bc3312b
TG		 774 case NAND_CMD_RNDOUT:
775 /* No ready / busy check necessary */
776 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
777 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
778 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
779 NAND_NCE | NAND_CTRL_CHANGE);
780 return;
781
1da177e4 782 case NAND_CMD_READ0:
12efdde3
TG		 783 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
784 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
785 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
786 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 787
e0c7d767 788 /* This applies to read commands */
1da177e4 789 default:
61b03bd7 790 /*
1da177e4 791 * If we don't have access to the busy pin, we apply the given
8b6e50c9 792 * command delay.
e0c7d767 793 */
ace4dfee
TG		 794 if (!chip->dev_ready) {
795 udelay(chip->chip_delay);
1da177e4 796 return;
61b03bd7 797 }
1da177e4 798 }
3b88775c 799
8b6e50c9
BN		 800 /*
801 * Apply this short delay always to ensure that we do wait tWB in
802 * any case on any machine.
803 */
e0c7d767 804 ndelay(100);
3b88775c
TG		 805
806 nand_wait_ready(mtd);
1da177e4
LT		 807}
808
2af7c653
SK		 809/**
810 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 811 * @chip: the nand chip descriptor
812 * @mtd: MTD device structure
813 * @new_state: the state which is requested
2af7c653
SK		 814 *
815 * Used when in panic, no locks are taken.
816 */
817static void panic_nand_get_device(struct nand_chip *chip,
818 struct mtd_info *mtd, int new_state)
819{
7854d3f7 820 /* Hardware controller shared among independent devices */
2af7c653
SK		 821 chip->controller->active = chip;
822 chip->state = new_state;
823}
824
1da177e4
LT		 825/**
826 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 827 * @mtd: MTD device structure
828 * @new_state: the state which is requested
1da177e4
LT		 829 *
830 * Get the device and lock it for exclusive access
831 */
2c0a2bed 832static int
6a8214aa 833nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 834{
862eba51 835 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee
TG		 836 spinlock_t *lock = &chip->controller->lock;
837 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 838 DECLARE_WAITQUEUE(wait, current);
7351d3a5 839retry:
0dfc6246
TG		 840 spin_lock(lock);
841
b8b3ee9a 842 /* Hardware controller shared among independent devices */
ace4dfee
TG		 843 if (!chip->controller->active)
844 chip->controller->active = chip;
a36ed299 845
ace4dfee
TG		 846 if (chip->controller->active == chip && chip->state == FL_READY) {
847 chip->state = new_state;
0dfc6246 848 spin_unlock(lock);
962034f4
VW		 849 return 0;
850 }
851 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 852 if (chip->controller->active->state == FL_PM_SUSPENDED) {
853 chip->state = FL_PM_SUSPENDED;
854 spin_unlock(lock);
855 return 0;
6b0d9a84 856 }
0dfc6246
TG		 857 }
858 set_current_state(TASK_UNINTERRUPTIBLE);
859 add_wait_queue(wq, &wait);
860 spin_unlock(lock);
861 schedule();
862 remove_wait_queue(wq, &wait);
1da177e4
LT		 863 goto retry;
864}
865
2af7c653 866/**
8b6e50c9
BN		 867 * panic_nand_wait - [GENERIC] wait until the command is done
868 * @mtd: MTD device structure
869 * @chip: NAND chip structure
870 * @timeo: timeout
2af7c653
SK		 871 *
872 * Wait for command done. This is a helper function for nand_wait used when
873 * we are in interrupt context. May happen when in panic and trying to write
b595076a 874 * an oops through mtdoops.
2af7c653
SK		 875 */
876static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
877 unsigned long timeo)
878{
879 int i;
880 for (i = 0; i < timeo; i++) {
881 if (chip->dev_ready) {
882 if (chip->dev_ready(mtd))
883 break;
884 } else {
885 if (chip->read_byte(mtd) & NAND_STATUS_READY)
886 break;
887 }
888 mdelay(1);
f8ac0414 889 }
2af7c653
SK		 890}
891
1da177e4 892/**
8b6e50c9
BN		 893 * nand_wait - [DEFAULT] wait until the command is done
894 * @mtd: MTD device structure
895 * @chip: NAND chip structure
1da177e4 896 *
b70af9be 897 * Wait for command done. This applies to erase and program only.
844d3b42 898 */
7bc3312b 899static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 900{
901
b70af9be
AS		 902 int status;
903 unsigned long timeo = 400;
1da177e4 904
8fe833c1
RP		 905 led_trigger_event(nand_led_trigger, LED_FULL);
906
8b6e50c9
BN		 907 /*
908 * Apply this short delay always to ensure that we do wait tWB in any
909 * case on any machine.
910 */
e0c7d767 911 ndelay(100);
1da177e4 912
14c65786 913 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 914
2af7c653
SK		 915 if (in_interrupt() || oops_in_progress)
916 panic_nand_wait(mtd, chip, timeo);
917 else {
6d2559f8 918 timeo = jiffies + msecs_to_jiffies(timeo);
b70af9be 919 do {
2af7c653
SK		 920 if (chip->dev_ready) {
921 if (chip->dev_ready(mtd))
922 break;
923 } else {
924 if (chip->read_byte(mtd) & NAND_STATUS_READY)
925 break;
926 }
927 cond_resched();
b70af9be 928 } while (time_before(jiffies, timeo));
1da177e4 929 }
8fe833c1
RP		 930 led_trigger_event(nand_led_trigger, LED_OFF);
931
ace4dfee 932 status = (int)chip->read_byte(mtd);
f251b8df
MC		 933 /* This can happen if in case of timeout or buggy dev_ready */
934 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 935 return status;
936}
937
7d70f334 938/**
b6d676db 939 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 940 * @mtd: mtd info
941 * @ofs: offset to start unlock from
942 * @len: length to unlock
8b6e50c9
BN		 943 * @invert: when = 0, unlock the range of blocks within the lower and
944 * upper boundary address
945 * when = 1, unlock the range of blocks outside the boundaries
946 * of the lower and upper boundary address
7d70f334 947 *
8b6e50c9 948 * Returs unlock status.
7d70f334
VS		 949 */
950static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
951 uint64_t len, int invert)
952{
953 int ret = 0;
954 int status, page;
862eba51 955 struct nand_chip *chip = mtd_to_nand(mtd);
7d70f334
VS		 956
957 /* Submit address of first page to unlock */
958 page = ofs >> chip->page_shift;
959 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
960
961 /* Submit address of last page to unlock */
962 page = (ofs + len) >> chip->page_shift;
963 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
964 (page | invert) & chip->pagemask);
965
966 /* Call wait ready function */
967 status = chip->waitfunc(mtd, chip);
7d70f334 968 /* See if device thinks it succeeded */
74830966 969 if (status & NAND_STATUS_FAIL) {
289c0522 970 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 971 __func__, status);
972 ret = -EIO;
973 }
974
975 return ret;
976}
977
978/**
b6d676db 979 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 980 * @mtd: mtd info
981 * @ofs: offset to start unlock from
982 * @len: length to unlock
7d70f334 983 *
8b6e50c9 984 * Returns unlock status.
7d70f334
VS		 985 */
986int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
987{
988 int ret = 0;
989 int chipnr;
862eba51 990 struct nand_chip *chip = mtd_to_nand(mtd);
7d70f334 991
289c0522 992 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 993 __func__, (unsigned long long)ofs, len);
994
995 if (check_offs_len(mtd, ofs, len))
b1a2348a 996 return -EINVAL;
7d70f334
VS		 997
998 /* Align to last block address if size addresses end of the device */
999 if (ofs + len == mtd->size)
1000 len -= mtd->erasesize;
1001
6a8214aa 1002 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 1003
1004 /* Shift to get chip number */
1005 chipnr = ofs >> chip->chip_shift;
1006
1007 chip->select_chip(mtd, chipnr);
1008
57d3a9a8
WD		 1009 /*
1010 * Reset the chip.
1011 * If we want to check the WP through READ STATUS and check the bit 7
1012 * we must reset the chip
1013 * some operation can also clear the bit 7 of status register
1014 * eg. erase/program a locked block
1015 */
1016 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1017
7d70f334
VS		 1018 /* Check, if it is write protected */
1019 if (nand_check_wp(mtd)) {
289c0522 1020 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1021 __func__);
1022 ret = -EIO;
1023 goto out;
1024 }
1025
1026 ret = __nand_unlock(mtd, ofs, len, 0);
1027
1028out:
b0bb6903 1029 chip->select_chip(mtd, -1);
7d70f334
VS		 1030 nand_release_device(mtd);
1031
1032 return ret;
1033}
7351d3a5 1034EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 1035
1036/**
b6d676db 1037 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 1038 * @mtd: mtd info
1039 * @ofs: offset to start unlock from
1040 * @len: length to unlock
7d70f334 1041 *
8b6e50c9
BN		 1042 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1043 * have this feature, but it allows only to lock all blocks, not for specified
1044 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1045 * now.
7d70f334 1046 *
8b6e50c9 1047 * Returns lock status.
7d70f334
VS		 1048 */
1049int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1050{
1051 int ret = 0;
1052 int chipnr, status, page;
862eba51 1053 struct nand_chip *chip = mtd_to_nand(mtd);
7d70f334 1054
289c0522 1055 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1056 __func__, (unsigned long long)ofs, len);
1057
1058 if (check_offs_len(mtd, ofs, len))
b1a2348a 1059 return -EINVAL;
7d70f334 1060
6a8214aa 1061 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 1062
1063 /* Shift to get chip number */
1064 chipnr = ofs >> chip->chip_shift;
1065
1066 chip->select_chip(mtd, chipnr);
1067
57d3a9a8
WD		 1068 /*
1069 * Reset the chip.
1070 * If we want to check the WP through READ STATUS and check the bit 7
1071 * we must reset the chip
1072 * some operation can also clear the bit 7 of status register
1073 * eg. erase/program a locked block
1074 */
1075 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1076
7d70f334
VS		 1077 /* Check, if it is write protected */
1078 if (nand_check_wp(mtd)) {
289c0522 1079 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1080 __func__);
1081 status = MTD_ERASE_FAILED;
1082 ret = -EIO;
1083 goto out;
1084 }
1085
1086 /* Submit address of first page to lock */
1087 page = ofs >> chip->page_shift;
1088 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1089
1090 /* Call wait ready function */
1091 status = chip->waitfunc(mtd, chip);
7d70f334 1092 /* See if device thinks it succeeded */
74830966 1093 if (status & NAND_STATUS_FAIL) {
289c0522 1094 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1095 __func__, status);
1096 ret = -EIO;
1097 goto out;
1098 }
1099
1100 ret = __nand_unlock(mtd, ofs, len, 0x1);
1101
1102out:
b0bb6903 1103 chip->select_chip(mtd, -1);
7d70f334
VS		 1104 nand_release_device(mtd);
1105
1106 return ret;
1107}
7351d3a5 1108EXPORT_SYMBOL(nand_lock);
7d70f334 1109
730a43fb
BB		 1110/**
1111 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1112 * @buf: buffer to test
1113 * @len: buffer length
1114 * @bitflips_threshold: maximum number of bitflips
1115 *
1116 * Check if a buffer contains only 0xff, which means the underlying region
1117 * has been erased and is ready to be programmed.
1118 * The bitflips_threshold specify the maximum number of bitflips before
1119 * considering the region is not erased.
1120 * Note: The logic of this function has been extracted from the memweight
1121 * implementation, except that nand_check_erased_buf function exit before
1122 * testing the whole buffer if the number of bitflips exceed the
1123 * bitflips_threshold value.
1124 *
1125 * Returns a positive number of bitflips less than or equal to
1126 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1127 * threshold.
1128 */
1129static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1130{
1131 const unsigned char *bitmap = buf;
1132 int bitflips = 0;
1133 int weight;
1134
1135 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1136 len--, bitmap++) {
1137 weight = hweight8(*bitmap);
1138 bitflips += BITS_PER_BYTE - weight;
1139 if (unlikely(bitflips > bitflips_threshold))
1140 return -EBADMSG;
1141 }
1142
1143 for (; len >= sizeof(long);
1144 len -= sizeof(long), bitmap += sizeof(long)) {
1145 weight = hweight_long(*((unsigned long *)bitmap));
1146 bitflips += BITS_PER_LONG - weight;
1147 if (unlikely(bitflips > bitflips_threshold))
1148 return -EBADMSG;
1149 }
1150
1151 for (; len > 0; len--, bitmap++) {
1152 weight = hweight8(*bitmap);
1153 bitflips += BITS_PER_BYTE - weight;
1154 if (unlikely(bitflips > bitflips_threshold))
1155 return -EBADMSG;
1156 }
1157
1158 return bitflips;
1159}
1160
1161/**
1162 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1163 * 0xff data
1164 * @data: data buffer to test
1165 * @datalen: data length
1166 * @ecc: ECC buffer
1167 * @ecclen: ECC length
1168 * @extraoob: extra OOB buffer
1169 * @extraooblen: extra OOB length
1170 * @bitflips_threshold: maximum number of bitflips
1171 *
1172 * Check if a data buffer and its associated ECC and OOB data contains only
1173 * 0xff pattern, which means the underlying region has been erased and is
1174 * ready to be programmed.
1175 * The bitflips_threshold specify the maximum number of bitflips before
1176 * considering the region as not erased.
1177 *
1178 * Note:
1179 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1180 * different from the NAND page size. When fixing bitflips, ECC engines will
1181 * report the number of errors per chunk, and the NAND core infrastructure
1182 * expect you to return the maximum number of bitflips for the whole page.
1183 * This is why you should always use this function on a single chunk and
1184 * not on the whole page. After checking each chunk you should update your
1185 * max_bitflips value accordingly.
1186 * 2/ When checking for bitflips in erased pages you should not only check
1187 * the payload data but also their associated ECC data, because a user might
1188 * have programmed almost all bits to 1 but a few. In this case, we
1189 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1190 * this case.
1191 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1192 * data are protected by the ECC engine.
1193 * It could also be used if you support subpages and want to attach some
1194 * extra OOB data to an ECC chunk.
1195 *
1196 * Returns a positive number of bitflips less than or equal to
1197 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1198 * threshold. In case of success, the passed buffers are filled with 0xff.
1199 */
1200int nand_check_erased_ecc_chunk(void *data, int datalen,
1201 void *ecc, int ecclen,
1202 void *extraoob, int extraooblen,
1203 int bitflips_threshold)
1204{
1205 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1206
1207 data_bitflips = nand_check_erased_buf(data, datalen,
1208 bitflips_threshold);
1209 if (data_bitflips < 0)
1210 return data_bitflips;
1211
1212 bitflips_threshold -= data_bitflips;
1213
1214 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1215 if (ecc_bitflips < 0)
1216 return ecc_bitflips;
1217
1218 bitflips_threshold -= ecc_bitflips;
1219
1220 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1221 bitflips_threshold);
1222 if (extraoob_bitflips < 0)
1223 return extraoob_bitflips;
1224
1225 if (data_bitflips)
1226 memset(data, 0xff, datalen);
1227
1228 if (ecc_bitflips)
1229 memset(ecc, 0xff, ecclen);
1230
1231 if (extraoob_bitflips)
1232 memset(extraoob, 0xff, extraooblen);
1233
1234 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1235}
1236EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1237
8593fbc6 1238/**
7854d3f7 1239 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1240 * @mtd: mtd info structure
1241 * @chip: nand chip info structure
1242 * @buf: buffer to store read data
1fbb938d 1243 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1244 * @page: page number to read
52ff49df 1245 *
7854d3f7 1246 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1247 */
1248static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1249 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1250{
1251 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1252 if (oob_required)
1253 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1254 return 0;
1255}
1256
52ff49df 1257/**
7854d3f7 1258 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1259 * @mtd: mtd info structure
1260 * @chip: nand chip info structure
1261 * @buf: buffer to store read data
1fbb938d 1262 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1263 * @page: page number to read
52ff49df
DB		 1264 *
1265 * We need a special oob layout and handling even when OOB isn't used.
1266 */
7351d3a5 1267static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1268 struct nand_chip *chip, uint8_t *buf,
1269 int oob_required, int page)
52ff49df
DB		 1270{
1271 int eccsize = chip->ecc.size;
1272 int eccbytes = chip->ecc.bytes;
1273 uint8_t *oob = chip->oob_poi;
1274 int steps, size;
1275
1276 for (steps = chip->ecc.steps; steps > 0; steps--) {
1277 chip->read_buf(mtd, buf, eccsize);
1278 buf += eccsize;
1279
1280 if (chip->ecc.prepad) {
1281 chip->read_buf(mtd, oob, chip->ecc.prepad);
1282 oob += chip->ecc.prepad;
1283 }
1284
1285 chip->read_buf(mtd, oob, eccbytes);
1286 oob += eccbytes;
1287
1288 if (chip->ecc.postpad) {
1289 chip->read_buf(mtd, oob, chip->ecc.postpad);
1290 oob += chip->ecc.postpad;
1291 }
1292 }
1293
1294 size = mtd->oobsize - (oob - chip->oob_poi);
1295 if (size)
1296 chip->read_buf(mtd, oob, size);
1297
1298 return 0;
1299}
1300
1da177e4 1301/**
7854d3f7 1302 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1303 * @mtd: mtd info structure
1304 * @chip: nand chip info structure
1305 * @buf: buffer to store read data
1fbb938d 1306 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1307 * @page: page number to read
068e3c0a 1308 */
f5bbdacc 1309static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1310 uint8_t *buf, int oob_required, int page)
1da177e4 1311{
f5bbdacc
TG		 1312 int i, eccsize = chip->ecc.size;
1313 int eccbytes = chip->ecc.bytes;
1314 int eccsteps = chip->ecc.steps;
1315 uint8_t *p = buf;
4bf63fcb
DW		 1316 uint8_t *ecc_calc = chip->buffers->ecccalc;
1317 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1318 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1319 unsigned int max_bitflips = 0;
f5bbdacc 1320
1fbb938d 1321 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1322
1323 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1324 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1325
1326 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1327 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1328
1329 eccsteps = chip->ecc.steps;
1330 p = buf;
1331
1332 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1333 int stat;
1334
1335 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1336 if (stat < 0) {
f5bbdacc 1337 mtd->ecc_stats.failed++;
3f91e94f 1338 } else {
f5bbdacc 1339 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1340 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1341 }
f5bbdacc 1342 }
3f91e94f 1343 return max_bitflips;
22c60f5f 1344}
1da177e4 1345
3d459559 1346/**
837a6ba4 1347 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1348 * @mtd: mtd info structure
1349 * @chip: nand chip info structure
1350 * @data_offs: offset of requested data within the page
1351 * @readlen: data length
1352 * @bufpoi: buffer to store read data
e004debd 1353 * @page: page number to read
3d459559 1354 */
7351d3a5 1355static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
e004debd
HS		 1356 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1357 int page)
3d459559
AK		 1358{
1359 int start_step, end_step, num_steps;
1360 uint32_t *eccpos = chip->ecc.layout->eccpos;
1361 uint8_t *p;
1362 int data_col_addr, i, gaps = 0;
1363 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1364 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
4a4163ca 1365 int index;
3f91e94f 1366 unsigned int max_bitflips = 0;
3d459559 1367
7854d3f7 1368 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1369 start_step = data_offs / chip->ecc.size;
1370 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1371 num_steps = end_step - start_step + 1;
4a4163ca 1372 index = start_step * chip->ecc.bytes;
3d459559 1373
8b6e50c9 1374 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1375 datafrag_len = num_steps * chip->ecc.size;
1376 eccfrag_len = num_steps * chip->ecc.bytes;
1377
1378 data_col_addr = start_step * chip->ecc.size;
1379 /* If we read not a page aligned data */
1380 if (data_col_addr != 0)
1381 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1382
1383 p = bufpoi + data_col_addr;
1384 chip->read_buf(mtd, p, datafrag_len);
1385
8b6e50c9 1386 /* Calculate ECC */
3d459559
AK		 1387 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1388 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1389
8b6e50c9
BN		 1390 /*
1391 * The performance is faster if we position offsets according to
7854d3f7 1392 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1393 */
3d459559 1394 for (i = 0; i < eccfrag_len - 1; i++) {
47570bb1 1395 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
3d459559
AK		 1396 gaps = 1;
1397 break;
1398 }
1399 }
1400 if (gaps) {
1401 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1402 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1403 } else {
8b6e50c9 1404 /*
7854d3f7 1405 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1406 * about buswidth alignment in read_buf.
1407 */
7351d3a5 1408 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1409 aligned_len = eccfrag_len;
7351d3a5 1410 if (eccpos[index] & (busw - 1))
3d459559 1411 aligned_len++;
7351d3a5 1412 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1413 aligned_len++;
1414
7351d3a5
FF		 1415 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1416 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1417 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1418 }
1419
1420 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1421 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1422
1423 p = bufpoi + data_col_addr;
1424 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1425 int stat;
1426
7351d3a5
FF		 1427 stat = chip->ecc.correct(mtd, p,
1428 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
40cbe6ee
BB		 1429 if (stat == -EBADMSG &&
1430 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1431 /* check for empty pages with bitflips */
1432 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1433 &chip->buffers->ecccode[i],
1434 chip->ecc.bytes,
1435 NULL, 0,
1436 chip->ecc.strength);
1437 }
1438
3f91e94f 1439 if (stat < 0) {
3d459559 1440 mtd->ecc_stats.failed++;
3f91e94f 1441 } else {
3d459559 1442 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1443 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1444 }
3d459559 1445 }
3f91e94f 1446 return max_bitflips;
3d459559
AK		 1447}
1448
068e3c0a 1449/**
7854d3f7 1450 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1451 * @mtd: mtd info structure
1452 * @chip: nand chip info structure
1453 * @buf: buffer to store read data
1fbb938d 1454 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1455 * @page: page number to read
068e3c0a 1456 *
7854d3f7 1457 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1458 */
f5bbdacc 1459static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1460 uint8_t *buf, int oob_required, int page)
1da177e4 1461{
f5bbdacc
TG		 1462 int i, eccsize = chip->ecc.size;
1463 int eccbytes = chip->ecc.bytes;
1464 int eccsteps = chip->ecc.steps;
1465 uint8_t *p = buf;
4bf63fcb
DW		 1466 uint8_t *ecc_calc = chip->buffers->ecccalc;
1467 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1468 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1469 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1470
1471 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1472 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1473 chip->read_buf(mtd, p, eccsize);
1474 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1475 }
f75e5097 1476 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1477
f5bbdacc 1478 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1479 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1480
f5bbdacc
TG		 1481 eccsteps = chip->ecc.steps;
1482 p = buf;
61b03bd7 1483
f5bbdacc
TG		 1484 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1485 int stat;
1da177e4 1486
f5bbdacc 1487 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
40cbe6ee
BB		 1488 if (stat == -EBADMSG &&
1489 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1490 /* check for empty pages with bitflips */
1491 stat = nand_check_erased_ecc_chunk(p, eccsize,
1492 &ecc_code[i], eccbytes,
1493 NULL, 0,
1494 chip->ecc.strength);
1495 }
1496
3f91e94f 1497 if (stat < 0) {
f5bbdacc 1498 mtd->ecc_stats.failed++;
3f91e94f 1499 } else {
f5bbdacc 1500 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1501 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1502 }
f5bbdacc 1503 }
3f91e94f 1504 return max_bitflips;
f5bbdacc 1505}
1da177e4 1506
6e0cb135 1507/**
7854d3f7 1508 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1509 * @mtd: mtd info structure
1510 * @chip: nand chip info structure
1511 * @buf: buffer to store read data
1fbb938d 1512 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1513 * @page: page number to read
6e0cb135 1514 *
8b6e50c9
BN		 1515 * Hardware ECC for large page chips, require OOB to be read first. For this
1516 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1517 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1518 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1519 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1520 */
1521static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1522 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1523{
1524 int i, eccsize = chip->ecc.size;
1525 int eccbytes = chip->ecc.bytes;
1526 int eccsteps = chip->ecc.steps;
1527 uint8_t *p = buf;
1528 uint8_t *ecc_code = chip->buffers->ecccode;
1529 uint32_t *eccpos = chip->ecc.layout->eccpos;
1530 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1531 unsigned int max_bitflips = 0;
6e0cb135
SN		 1532
1533 /* Read the OOB area first */
1534 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1535 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1536 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1537
1538 for (i = 0; i < chip->ecc.total; i++)
1539 ecc_code[i] = chip->oob_poi[eccpos[i]];
1540
1541 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1542 int stat;
1543
1544 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1545 chip->read_buf(mtd, p, eccsize);
1546 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1547
1548 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
40cbe6ee
BB		 1549 if (stat == -EBADMSG &&
1550 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1551 /* check for empty pages with bitflips */
1552 stat = nand_check_erased_ecc_chunk(p, eccsize,
1553 &ecc_code[i], eccbytes,
1554 NULL, 0,
1555 chip->ecc.strength);
1556 }
1557
3f91e94f 1558 if (stat < 0) {
6e0cb135 1559 mtd->ecc_stats.failed++;
3f91e94f 1560 } else {
6e0cb135 1561 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1562 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1563 }
6e0cb135 1564 }
3f91e94f 1565 return max_bitflips;
6e0cb135
SN		 1566}
1567
f5bbdacc 1568/**
7854d3f7 1569 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1570 * @mtd: mtd info structure
1571 * @chip: nand chip info structure
1572 * @buf: buffer to store read data
1fbb938d 1573 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1574 * @page: page number to read
f5bbdacc 1575 *
8b6e50c9
BN		 1576 * The hw generator calculates the error syndrome automatically. Therefore we
1577 * need a special oob layout and handling.
f5bbdacc
TG		 1578 */
1579static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1580 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1581{
1582 int i, eccsize = chip->ecc.size;
1583 int eccbytes = chip->ecc.bytes;
1584 int eccsteps = chip->ecc.steps;
40cbe6ee 1585 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
f5bbdacc 1586 uint8_t *p = buf;
f75e5097 1587 uint8_t *oob = chip->oob_poi;
3f91e94f 1588 unsigned int max_bitflips = 0;
1da177e4 1589
f5bbdacc
TG		 1590 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1591 int stat;
61b03bd7 1592
f5bbdacc
TG		 1593 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1594 chip->read_buf(mtd, p, eccsize);
1da177e4 1595
f5bbdacc
TG		 1596 if (chip->ecc.prepad) {
1597 chip->read_buf(mtd, oob, chip->ecc.prepad);
1598 oob += chip->ecc.prepad;
1599 }
1da177e4 1600
f5bbdacc
TG		 1601 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1602 chip->read_buf(mtd, oob, eccbytes);
1603 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1604
f5bbdacc 1605 oob += eccbytes;
1da177e4 1606
f5bbdacc
TG		 1607 if (chip->ecc.postpad) {
1608 chip->read_buf(mtd, oob, chip->ecc.postpad);
1609 oob += chip->ecc.postpad;
61b03bd7 1610 }
40cbe6ee
BB		 1611
1612 if (stat == -EBADMSG &&
1613 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1614 /* check for empty pages with bitflips */
1615 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1616 oob - eccpadbytes,
1617 eccpadbytes,
1618 NULL, 0,
1619 chip->ecc.strength);
1620 }
1621
1622 if (stat < 0) {
1623 mtd->ecc_stats.failed++;
1624 } else {
1625 mtd->ecc_stats.corrected += stat;
1626 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1627 }
f5bbdacc 1628 }
1da177e4 1629
f5bbdacc 1630 /* Calculate remaining oob bytes */
7e4178f9 1631 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1632 if (i)
1633 chip->read_buf(mtd, oob, i);
61b03bd7 1634
3f91e94f 1635 return max_bitflips;
f5bbdacc 1636}
1da177e4 1637
f5bbdacc 1638/**
7854d3f7 1639 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1640 * @chip: nand chip structure
1641 * @oob: oob destination address
1642 * @ops: oob ops structure
1643 * @len: size of oob to transfer
8593fbc6
TG		 1644 */
1645static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1646 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1647{
f8ac0414 1648 switch (ops->mode) {
8593fbc6 1649
0612b9dd
BN		 1650 case MTD_OPS_PLACE_OOB:
1651 case MTD_OPS_RAW:
8593fbc6
TG		 1652 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1653 return oob + len;
1654
0612b9dd 1655 case MTD_OPS_AUTO_OOB: {
8593fbc6 1656 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1657 uint32_t boffs = 0, roffs = ops->ooboffs;
1658 size_t bytes = 0;
8593fbc6 1659
f8ac0414 1660 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1661 /* Read request not from offset 0? */
7bc3312b
TG		 1662 if (unlikely(roffs)) {
1663 if (roffs >= free->length) {
1664 roffs -= free->length;
1665 continue;
1666 }
1667 boffs = free->offset + roffs;
1668 bytes = min_t(size_t, len,
1669 (free->length - roffs));
1670 roffs = 0;
1671 } else {
1672 bytes = min_t(size_t, len, free->length);
1673 boffs = free->offset;
1674 }
1675 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1676 oob += bytes;
1677 }
1678 return oob;
1679 }
1680 default:
1681 BUG();
1682 }
1683 return NULL;
1684}
1685
ba84fb59
BN		 1686/**
1687 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1688 * @mtd: MTD device structure
1689 * @retry_mode: the retry mode to use
1690 *
1691 * Some vendors supply a special command to shift the Vt threshold, to be used
1692 * when there are too many bitflips in a page (i.e., ECC error). After setting
1693 * a new threshold, the host should retry reading the page.
1694 */
1695static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1696{
862eba51 1697 struct nand_chip *chip = mtd_to_nand(mtd);
ba84fb59
BN		 1698
1699 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1700
1701 if (retry_mode >= chip->read_retries)
1702 return -EINVAL;
1703
1704 if (!chip->setup_read_retry)
1705 return -EOPNOTSUPP;
1706
1707 return chip->setup_read_retry(mtd, retry_mode);
1708}
1709
8593fbc6 1710/**
7854d3f7 1711 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1712 * @mtd: MTD device structure
1713 * @from: offset to read from
1714 * @ops: oob ops structure
f5bbdacc
TG		 1715 *
1716 * Internal function. Called with chip held.
1717 */
8593fbc6
TG		 1718static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1719 struct mtd_oob_ops *ops)
f5bbdacc 1720{
e47f3db4 1721 int chipnr, page, realpage, col, bytes, aligned, oob_required;
862eba51 1722 struct nand_chip *chip = mtd_to_nand(mtd);
f5bbdacc 1723 int ret = 0;
8593fbc6 1724 uint32_t readlen = ops->len;
7014568b 1725 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1726 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1727 mtd->oobavail : mtd->oobsize;
1728
8593fbc6 1729 uint8_t *bufpoi, *oob, *buf;
66507c7b 1730 int use_bufpoi;
edbc4540 1731 unsigned int max_bitflips = 0;
ba84fb59 1732 int retry_mode = 0;
b72f3dfb 1733 bool ecc_fail = false;
1da177e4 1734
f5bbdacc
TG		 1735 chipnr = (int)(from >> chip->chip_shift);
1736 chip->select_chip(mtd, chipnr);
61b03bd7 1737
f5bbdacc
TG		 1738 realpage = (int)(from >> chip->page_shift);
1739 page = realpage & chip->pagemask;
1da177e4 1740
f5bbdacc 1741 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1742
8593fbc6
TG		 1743 buf = ops->datbuf;
1744 oob = ops->oobbuf;
e47f3db4 1745 oob_required = oob ? 1 : 0;
8593fbc6 1746
f8ac0414 1747 while (1) {
b72f3dfb
BN		 1748 unsigned int ecc_failures = mtd->ecc_stats.failed;
1749
f5bbdacc
TG		 1750 bytes = min(mtd->writesize - col, readlen);
1751 aligned = (bytes == mtd->writesize);
61b03bd7 1752
66507c7b
KD		 1753 if (!aligned)
1754 use_bufpoi = 1;
1755 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1756 use_bufpoi = !virt_addr_valid(buf);
1757 else
1758 use_bufpoi = 0;
1759
8b6e50c9 1760 /* Is the current page in the buffer? */
8593fbc6 1761 if (realpage != chip->pagebuf || oob) {
66507c7b
KD		 1762 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1763
1764 if (use_bufpoi && aligned)
1765 pr_debug("%s: using read bounce buffer for buf@%p\n",
1766 __func__, buf);
61b03bd7 1767
ba84fb59 1768read_retry:
c00a0991 1769 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1770
edbc4540
MD		 1771 /*
1772 * Now read the page into the buffer. Absent an error,
1773 * the read methods return max bitflips per ecc step.
1774 */
0612b9dd 1775 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1776 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1777 oob_required,
1778 page);
a5ff4f10
JW		 1779 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1780 !oob)
7351d3a5 1781 ret = chip->ecc.read_subpage(mtd, chip,
e004debd
HS		 1782 col, bytes, bufpoi,
1783 page);
956e944c 1784 else
46a8cf2d 1785 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1786 oob_required, page);
6d77b9d0 1787 if (ret < 0) {
66507c7b 1788 if (use_bufpoi)
6d77b9d0
BN		 1789 /* Invalidate page cache */
1790 chip->pagebuf = -1;
1da177e4 1791 break;
6d77b9d0 1792 }
f5bbdacc 1793
edbc4540
MD		 1794 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1795
f5bbdacc 1796 /* Transfer not aligned data */
66507c7b 1797 if (use_bufpoi) {
a5ff4f10 1798 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
b72f3dfb 1799 !(mtd->ecc_stats.failed - ecc_failures) &&
edbc4540 1800 (ops->mode != MTD_OPS_RAW)) {
3d459559 1801 chip->pagebuf = realpage;
edbc4540
MD		 1802 chip->pagebuf_bitflips = ret;
1803 } else {
6d77b9d0
BN		 1804 /* Invalidate page cache */
1805 chip->pagebuf = -1;
edbc4540 1806 }
4bf63fcb 1807 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1808 }
1809
8593fbc6 1810 if (unlikely(oob)) {
b64d39d8
ML		 1811 int toread = min(oobreadlen, max_oobsize);
1812
1813 if (toread) {
1814 oob = nand_transfer_oob(chip,
1815 oob, ops, toread);
1816 oobreadlen -= toread;
1817 }
8593fbc6 1818 }
5bc7c33c
BN		 1819
1820 if (chip->options & NAND_NEED_READRDY) {
1821 /* Apply delay or wait for ready/busy pin */
1822 if (!chip->dev_ready)
1823 udelay(chip->chip_delay);
1824 else
1825 nand_wait_ready(mtd);
1826 }
b72f3dfb 1827
ba84fb59 1828 if (mtd->ecc_stats.failed - ecc_failures) {
28fa65e6 1829 if (retry_mode + 1 < chip->read_retries) {
ba84fb59
BN		 1830 retry_mode++;
1831 ret = nand_setup_read_retry(mtd,
1832 retry_mode);
1833 if (ret < 0)
1834 break;
1835
1836 /* Reset failures; retry */
1837 mtd->ecc_stats.failed = ecc_failures;
1838 goto read_retry;
1839 } else {
1840 /* No more retry modes; real failure */
1841 ecc_fail = true;
1842 }
1843 }
1844
1845 buf += bytes;
8593fbc6 1846 } else {
4bf63fcb 1847 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1848 buf += bytes;
edbc4540
MD		 1849 max_bitflips = max_t(unsigned int, max_bitflips,
1850 chip->pagebuf_bitflips);
8593fbc6 1851 }
1da177e4 1852
f5bbdacc 1853 readlen -= bytes;
61b03bd7 1854
ba84fb59
BN		 1855 /* Reset to retry mode 0 */
1856 if (retry_mode) {
1857 ret = nand_setup_read_retry(mtd, 0);
1858 if (ret < 0)
1859 break;
1860 retry_mode = 0;
1861 }
1862
f5bbdacc 1863 if (!readlen)
61b03bd7 1864 break;
1da177e4 1865
8b6e50c9 1866 /* For subsequent reads align to page boundary */
1da177e4
LT		 1867 col = 0;
1868 /* Increment page address */
1869 realpage++;
1870
ace4dfee 1871 page = realpage & chip->pagemask;
1da177e4
LT		 1872 /* Check, if we cross a chip boundary */
1873 if (!page) {
1874 chipnr++;
ace4dfee
TG		 1875 chip->select_chip(mtd, -1);
1876 chip->select_chip(mtd, chipnr);
1da177e4 1877 }
1da177e4 1878 }
b0bb6903 1879 chip->select_chip(mtd, -1);
1da177e4 1880
8593fbc6 1881 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1882 if (oob)
1883 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1884
3f91e94f 1885 if (ret < 0)
f5bbdacc
TG		 1886 return ret;
1887
b72f3dfb 1888 if (ecc_fail)
9a1fcdfd
TG		 1889 return -EBADMSG;
1890
edbc4540 1891 return max_bitflips;
f5bbdacc
TG		 1892}
1893
1894/**
25985edc 1895 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1896 * @mtd: MTD device structure
1897 * @from: offset to read from
1898 * @len: number of bytes to read
1899 * @retlen: pointer to variable to store the number of read bytes
1900 * @buf: the databuffer to put data
f5bbdacc 1901 *
8b6e50c9 1902 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1903 */
1904static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1905 size_t *retlen, uint8_t *buf)
1906{
4a89ff88 1907 struct mtd_oob_ops ops;
f5bbdacc
TG		 1908 int ret;
1909
6a8214aa 1910 nand_get_device(mtd, FL_READING);
0ec56dc4 1911 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 1912 ops.len = len;
1913 ops.datbuf = buf;
11041ae6 1914 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1915 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1916 *retlen = ops.retlen;
f5bbdacc 1917 nand_release_device(mtd);
f5bbdacc 1918 return ret;
1da177e4
LT		 1919}
1920
7bc3312b 1921/**
7854d3f7 1922 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1923 * @mtd: mtd info structure
1924 * @chip: nand chip info structure
1925 * @page: page number to read
7bc3312b
TG		 1926 */
1927static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1928 int page)
7bc3312b 1929{
5c2ffb11 1930 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1931 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1932 return 0;
7bc3312b
TG		 1933}
1934
1935/**
7854d3f7 1936 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1937 * with syndromes
8b6e50c9
BN		 1938 * @mtd: mtd info structure
1939 * @chip: nand chip info structure
1940 * @page: page number to read
7bc3312b
TG		 1941 */
1942static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1943 int page)
7bc3312b 1944{
7bc3312b
TG		 1945 int length = mtd->oobsize;
1946 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1947 int eccsize = chip->ecc.size;
2ea69d21 1948 uint8_t *bufpoi = chip->oob_poi;
7bc3312b
TG		 1949 int i, toread, sndrnd = 0, pos;
1950
1951 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1952 for (i = 0; i < chip->ecc.steps; i++) {
1953 if (sndrnd) {
1954 pos = eccsize + i * (eccsize + chunk);
1955 if (mtd->writesize > 512)
1956 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1957 else
1958 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1959 } else
1960 sndrnd = 1;
1961 toread = min_t(int, length, chunk);
1962 chip->read_buf(mtd, bufpoi, toread);
1963 bufpoi += toread;
1964 length -= toread;
1965 }
1966 if (length > 0)
1967 chip->read_buf(mtd, bufpoi, length);
1968
5c2ffb11 1969 return 0;
7bc3312b
TG		 1970}
1971
1972/**
7854d3f7 1973 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1974 * @mtd: mtd info structure
1975 * @chip: nand chip info structure
1976 * @page: page number to write
7bc3312b
TG		 1977 */
1978static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1979 int page)
1980{
1981 int status = 0;
1982 const uint8_t *buf = chip->oob_poi;
1983 int length = mtd->oobsize;
1984
1985 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1986 chip->write_buf(mtd, buf, length);
1987 /* Send command to program the OOB data */
1988 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1989
1990 status = chip->waitfunc(mtd, chip);
1991
0d420f9d 1992 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1993}
1994
1995/**
7854d3f7 1996 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1997 * with syndrome - only for large page flash
1998 * @mtd: mtd info structure
1999 * @chip: nand chip info structure
2000 * @page: page number to write
7bc3312b
TG		 2001 */
2002static int nand_write_oob_syndrome(struct mtd_info *mtd,
2003 struct nand_chip *chip, int page)
2004{
2005 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2006 int eccsize = chip->ecc.size, length = mtd->oobsize;
2007 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
2008 const uint8_t *bufpoi = chip->oob_poi;
2009
2010 /*
2011 * data-ecc-data-ecc ... ecc-oob
2012 * or
2013 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2014 */
2015 if (!chip->ecc.prepad && !chip->ecc.postpad) {
2016 pos = steps * (eccsize + chunk);
2017 steps = 0;
2018 } else
8b0036ee 2019 pos = eccsize;
7bc3312b
TG		 2020
2021 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
2022 for (i = 0; i < steps; i++) {
2023 if (sndcmd) {
2024 if (mtd->writesize <= 512) {
2025 uint32_t fill = 0xFFFFFFFF;
2026
2027 len = eccsize;
2028 while (len > 0) {
2029 int num = min_t(int, len, 4);
2030 chip->write_buf(mtd, (uint8_t *)&fill,
2031 num);
2032 len -= num;
2033 }
2034 } else {
2035 pos = eccsize + i * (eccsize + chunk);
2036 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2037 }
2038 } else
2039 sndcmd = 1;
2040 len = min_t(int, length, chunk);
2041 chip->write_buf(mtd, bufpoi, len);
2042 bufpoi += len;
2043 length -= len;
2044 }
2045 if (length > 0)
2046 chip->write_buf(mtd, bufpoi, length);
2047
2048 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2049 status = chip->waitfunc(mtd, chip);
2050
2051 return status & NAND_STATUS_FAIL ? -EIO : 0;
2052}
2053
1da177e4 2054/**
7854d3f7 2055 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 2056 * @mtd: MTD device structure
2057 * @from: offset to read from
2058 * @ops: oob operations description structure
1da177e4 2059 *
8b6e50c9 2060 * NAND read out-of-band data from the spare area.
1da177e4 2061 */
8593fbc6
TG		 2062static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2063 struct mtd_oob_ops *ops)
1da177e4 2064{
c00a0991 2065 int page, realpage, chipnr;
862eba51 2066 struct nand_chip *chip = mtd_to_nand(mtd);
041e4575 2067 struct mtd_ecc_stats stats;
7014568b
VW		 2068 int readlen = ops->ooblen;
2069 int len;
7bc3312b 2070 uint8_t *buf = ops->oobbuf;
1951f2f7 2071 int ret = 0;
61b03bd7 2072
289c0522 2073 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 2074 __func__, (unsigned long long)from, readlen);
1da177e4 2075
041e4575
BN		 2076 stats = mtd->ecc_stats;
2077
0612b9dd 2078 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 2079 len = chip->ecc.layout->oobavail;
03736155
AH		 2080 else
2081 len = mtd->oobsize;
2082
2083 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2084 pr_debug("%s: attempt to start read outside oob\n",
2085 __func__);
03736155
AH		 2086 return -EINVAL;
2087 }
2088
2089 /* Do not allow reads past end of device */
2090 if (unlikely(from >= mtd->size ||
2091 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2092 (from >> chip->page_shift)) * len)) {
289c0522
BN		 2093 pr_debug("%s: attempt to read beyond end of device\n",
2094 __func__);
03736155
AH		 2095 return -EINVAL;
2096 }
7014568b 2097
7314e9e7 2098 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 2099 chip->select_chip(mtd, chipnr);
1da177e4 2100
7314e9e7
TG		 2101 /* Shift to get page */
2102 realpage = (int)(from >> chip->page_shift);
2103 page = realpage & chip->pagemask;
1da177e4 2104
f8ac0414 2105 while (1) {
0612b9dd 2106 if (ops->mode == MTD_OPS_RAW)
1951f2f7 2107 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 2108 else
1951f2f7
SL		 2109 ret = chip->ecc.read_oob(mtd, chip, page);
2110
2111 if (ret < 0)
2112 break;
7014568b
VW		 2113
2114 len = min(len, readlen);
2115 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 2116
5bc7c33c
BN		 2117 if (chip->options & NAND_NEED_READRDY) {
2118 /* Apply delay or wait for ready/busy pin */
2119 if (!chip->dev_ready)
2120 udelay(chip->chip_delay);
2121 else
2122 nand_wait_ready(mtd);
2123 }
2124
7014568b 2125 readlen -= len;
0d420f9d
SZ		 2126 if (!readlen)
2127 break;
2128
7314e9e7
TG		 2129 /* Increment page address */
2130 realpage++;
2131
2132 page = realpage & chip->pagemask;
2133 /* Check, if we cross a chip boundary */
2134 if (!page) {
2135 chipnr++;
2136 chip->select_chip(mtd, -1);
2137 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2138 }
2139 }
b0bb6903 2140 chip->select_chip(mtd, -1);
1da177e4 2141
1951f2f7
SL		 2142 ops->oobretlen = ops->ooblen - readlen;
2143
2144 if (ret < 0)
2145 return ret;
041e4575
BN		 2146
2147 if (mtd->ecc_stats.failed - stats.failed)
2148 return -EBADMSG;
2149
2150 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 2151}
2152
2153/**
8593fbc6 2154 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 2155 * @mtd: MTD device structure
2156 * @from: offset to read from
2157 * @ops: oob operation description structure
1da177e4 2158 *
8b6e50c9 2159 * NAND read data and/or out-of-band data.
1da177e4 2160 */
8593fbc6
TG		 2161static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2162 struct mtd_oob_ops *ops)
1da177e4 2163{
8593fbc6
TG		 2164 int ret = -ENOTSUPP;
2165
2166 ops->retlen = 0;
1da177e4
LT		 2167
2168 /* Do not allow reads past end of device */
7014568b 2169 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 2170 pr_debug("%s: attempt to read beyond end of device\n",
2171 __func__);
1da177e4
LT		 2172 return -EINVAL;
2173 }
2174
6a8214aa 2175 nand_get_device(mtd, FL_READING);
1da177e4 2176
f8ac0414 2177 switch (ops->mode) {
0612b9dd
BN		 2178 case MTD_OPS_PLACE_OOB:
2179 case MTD_OPS_AUTO_OOB:
2180 case MTD_OPS_RAW:
8593fbc6 2181 break;
1da177e4 2182
8593fbc6
TG		 2183 default:
2184 goto out;
2185 }
1da177e4 2186
8593fbc6
TG		 2187 if (!ops->datbuf)
2188 ret = nand_do_read_oob(mtd, from, ops);
2189 else
2190 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 2191
7351d3a5 2192out:
8593fbc6
TG		 2193 nand_release_device(mtd);
2194 return ret;
2195}
61b03bd7 2196
1da177e4 2197
8593fbc6 2198/**
7854d3f7 2199 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 2200 * @mtd: mtd info structure
2201 * @chip: nand chip info structure
2202 * @buf: data buffer
1fbb938d 2203 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2204 * @page: page number to write
52ff49df 2205 *
7854d3f7 2206 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 2207 */
fdbad98d 2208static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9 2209 const uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 2210{
2211 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 2212 if (oob_required)
2213 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2214
2215 return 0;
1da177e4
LT		 2216}
2217
52ff49df 2218/**
7854d3f7 2219 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 2220 * @mtd: mtd info structure
2221 * @chip: nand chip info structure
2222 * @buf: data buffer
1fbb938d 2223 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2224 * @page: page number to write
52ff49df
DB		 2225 *
2226 * We need a special oob layout and handling even when ECC isn't checked.
2227 */
fdbad98d 2228static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 2229 struct nand_chip *chip,
45aaeff9
BB		 2230 const uint8_t *buf, int oob_required,
2231 int page)
52ff49df
DB		 2232{
2233 int eccsize = chip->ecc.size;
2234 int eccbytes = chip->ecc.bytes;
2235 uint8_t *oob = chip->oob_poi;
2236 int steps, size;
2237
2238 for (steps = chip->ecc.steps; steps > 0; steps--) {
2239 chip->write_buf(mtd, buf, eccsize);
2240 buf += eccsize;
2241
2242 if (chip->ecc.prepad) {
2243 chip->write_buf(mtd, oob, chip->ecc.prepad);
2244 oob += chip->ecc.prepad;
2245 }
2246
60c3bc1f 2247 chip->write_buf(mtd, oob, eccbytes);
52ff49df
DB		 2248 oob += eccbytes;
2249
2250 if (chip->ecc.postpad) {
2251 chip->write_buf(mtd, oob, chip->ecc.postpad);
2252 oob += chip->ecc.postpad;
2253 }
2254 }
2255
2256 size = mtd->oobsize - (oob - chip->oob_poi);
2257 if (size)
2258 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 2259
2260 return 0;
52ff49df 2261}
9223a456 2262/**
7854d3f7 2263 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 2264 * @mtd: mtd info structure
2265 * @chip: nand chip info structure
2266 * @buf: data buffer
1fbb938d 2267 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2268 * @page: page number to write
9223a456 2269 */
fdbad98d 2270static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9
BB		 2271 const uint8_t *buf, int oob_required,
2272 int page)
9223a456 2273{
f75e5097
TG		 2274 int i, eccsize = chip->ecc.size;
2275 int eccbytes = chip->ecc.bytes;
2276 int eccsteps = chip->ecc.steps;
4bf63fcb 2277 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2278 const uint8_t *p = buf;
8b099a39 2279 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2280
7854d3f7 2281 /* Software ECC calculation */
8593fbc6
TG		 2282 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2283 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 2284
8593fbc6
TG		 2285 for (i = 0; i < chip->ecc.total; i++)
2286 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 2287
45aaeff9 2288 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
f75e5097 2289}
9223a456 2290
f75e5097 2291/**
7854d3f7 2292 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2293 * @mtd: mtd info structure
2294 * @chip: nand chip info structure
2295 * @buf: data buffer
1fbb938d 2296 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2297 * @page: page number to write
f75e5097 2298 */
fdbad98d 2299static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9
BB		 2300 const uint8_t *buf, int oob_required,
2301 int page)
f75e5097
TG		 2302{
2303 int i, eccsize = chip->ecc.size;
2304 int eccbytes = chip->ecc.bytes;
2305 int eccsteps = chip->ecc.steps;
4bf63fcb 2306 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2307 const uint8_t *p = buf;
8b099a39 2308 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2309
f75e5097
TG		 2310 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2311 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2312 chip->write_buf(mtd, p, eccsize);
f75e5097 2313 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2314 }
2315
f75e5097
TG		 2316 for (i = 0; i < chip->ecc.total; i++)
2317 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2318
2319 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2320
2321 return 0;
9223a456
TG		 2322}
2323
837a6ba4
GP		 2324
2325/**
73c8aaf4 2326 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
837a6ba4
GP		 2327 * @mtd: mtd info structure
2328 * @chip: nand chip info structure
d6a95080 2329 * @offset: column address of subpage within the page
837a6ba4 2330 * @data_len: data length
d6a95080 2331 * @buf: data buffer
837a6ba4 2332 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2333 * @page: page number to write
837a6ba4
GP		 2334 */
2335static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2336 struct nand_chip *chip, uint32_t offset,
d6a95080 2337 uint32_t data_len, const uint8_t *buf,
45aaeff9 2338 int oob_required, int page)
837a6ba4
GP		 2339{
2340 uint8_t *oob_buf = chip->oob_poi;
2341 uint8_t *ecc_calc = chip->buffers->ecccalc;
2342 int ecc_size = chip->ecc.size;
2343 int ecc_bytes = chip->ecc.bytes;
2344 int ecc_steps = chip->ecc.steps;
2345 uint32_t *eccpos = chip->ecc.layout->eccpos;
2346 uint32_t start_step = offset / ecc_size;
2347 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2348 int oob_bytes = mtd->oobsize / ecc_steps;
2349 int step, i;
2350
2351 for (step = 0; step < ecc_steps; step++) {
2352 /* configure controller for WRITE access */
2353 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2354
2355 /* write data (untouched subpages already masked by 0xFF) */
d6a95080 2356 chip->write_buf(mtd, buf, ecc_size);
837a6ba4
GP		 2357
2358 /* mask ECC of un-touched subpages by padding 0xFF */
2359 if ((step < start_step) || (step > end_step))
2360 memset(ecc_calc, 0xff, ecc_bytes);
2361 else
d6a95080 2362 chip->ecc.calculate(mtd, buf, ecc_calc);
837a6ba4
GP		 2363
2364 /* mask OOB of un-touched subpages by padding 0xFF */
2365 /* if oob_required, preserve OOB metadata of written subpage */
2366 if (!oob_required || (step < start_step) || (step > end_step))
2367 memset(oob_buf, 0xff, oob_bytes);
2368
d6a95080 2369 buf += ecc_size;
837a6ba4
GP		 2370 ecc_calc += ecc_bytes;
2371 oob_buf += oob_bytes;
2372 }
2373
2374 /* copy calculated ECC for whole page to chip->buffer->oob */
2375 /* this include masked-value(0xFF) for unwritten subpages */
2376 ecc_calc = chip->buffers->ecccalc;
2377 for (i = 0; i < chip->ecc.total; i++)
2378 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2379
2380 /* write OOB buffer to NAND device */
2381 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2382
2383 return 0;
2384}
2385
2386
61b03bd7 2387/**
7854d3f7 2388 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2389 * @mtd: mtd info structure
2390 * @chip: nand chip info structure
2391 * @buf: data buffer
1fbb938d 2392 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2393 * @page: page number to write
1da177e4 2394 *
8b6e50c9
BN		 2395 * The hw generator calculates the error syndrome automatically. Therefore we
2396 * need a special oob layout and handling.
f75e5097 2397 */
fdbad98d 2398static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d 2399 struct nand_chip *chip,
45aaeff9
BB		 2400 const uint8_t *buf, int oob_required,
2401 int page)
1da177e4 2402{
f75e5097
TG		 2403 int i, eccsize = chip->ecc.size;
2404 int eccbytes = chip->ecc.bytes;
2405 int eccsteps = chip->ecc.steps;
2406 const uint8_t *p = buf;
2407 uint8_t *oob = chip->oob_poi;
1da177e4 2408
f75e5097 2409 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2410
f75e5097
TG		 2411 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2412 chip->write_buf(mtd, p, eccsize);
61b03bd7 2413
f75e5097
TG		 2414 if (chip->ecc.prepad) {
2415 chip->write_buf(mtd, oob, chip->ecc.prepad);
2416 oob += chip->ecc.prepad;
2417 }
2418
2419 chip->ecc.calculate(mtd, p, oob);
2420 chip->write_buf(mtd, oob, eccbytes);
2421 oob += eccbytes;
2422
2423 if (chip->ecc.postpad) {
2424 chip->write_buf(mtd, oob, chip->ecc.postpad);
2425 oob += chip->ecc.postpad;
1da177e4 2426 }
1da177e4 2427 }
f75e5097
TG		 2428
2429 /* Calculate remaining oob bytes */
7e4178f9 2430 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2431 if (i)
2432 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2433
2434 return 0;
f75e5097
TG		 2435}
2436
2437/**
956e944c 2438 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2439 * @mtd: MTD device structure
2440 * @chip: NAND chip descriptor
837a6ba4
GP		 2441 * @offset: address offset within the page
2442 * @data_len: length of actual data to be written
8b6e50c9 2443 * @buf: the data to write
1fbb938d 2444 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2445 * @page: page number to write
2446 * @cached: cached programming
2447 * @raw: use _raw version of write_page
f75e5097
TG		 2448 */
2449static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4
GP		 2450 uint32_t offset, int data_len, const uint8_t *buf,
2451 int oob_required, int page, int cached, int raw)
f75e5097 2452{
837a6ba4
GP		 2453 int status, subpage;
2454
2455 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2456 chip->ecc.write_subpage)
2457 subpage = offset || (data_len < mtd->writesize);
2458 else
2459 subpage = 0;
f75e5097
TG		 2460
2461 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2462
956e944c 2463 if (unlikely(raw))
837a6ba4 2464 status = chip->ecc.write_page_raw(mtd, chip, buf,
45aaeff9 2465 oob_required, page);
837a6ba4
GP		 2466 else if (subpage)
2467 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
45aaeff9 2468 buf, oob_required, page);
956e944c 2469 else
45aaeff9
BB		 2470 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2471 page);
fdbad98d
JW		 2472
2473 if (status < 0)
2474 return status;
f75e5097
TG		 2475
2476 /*
7854d3f7 2477 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2478 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2479 */
2480 cached = 0;
2481
3239a6cd 2482 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2483
2484 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2485 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2486 /*
2487 * See if operation failed and additional status checks are
8b6e50c9 2488 * available.
f75e5097
TG		 2489 */
2490 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2491 status = chip->errstat(mtd, chip, FL_WRITING, status,
2492 page);
2493
2494 if (status & NAND_STATUS_FAIL)
2495 return -EIO;
2496 } else {
2497 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2498 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2499 }
2500
f75e5097 2501 return 0;
1da177e4
LT		 2502}
2503
8593fbc6 2504/**
7854d3f7 2505 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2506 * @mtd: MTD device structure
8b6e50c9
BN		 2507 * @oob: oob data buffer
2508 * @len: oob data write length
2509 * @ops: oob ops structure
8593fbc6 2510 */
f722013e
TAA		 2511static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2512 struct mtd_oob_ops *ops)
8593fbc6 2513{
862eba51 2514 struct nand_chip *chip = mtd_to_nand(mtd);
f722013e
TAA		 2515
2516 /*
2517 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2518 * data from a previous OOB read.
2519 */
2520 memset(chip->oob_poi, 0xff, mtd->oobsize);
2521
f8ac0414 2522 switch (ops->mode) {
8593fbc6 2523
0612b9dd
BN		 2524 case MTD_OPS_PLACE_OOB:
2525 case MTD_OPS_RAW:
8593fbc6
TG		 2526 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2527 return oob + len;
2528
0612b9dd 2529 case MTD_OPS_AUTO_OOB: {
8593fbc6 2530 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2531 uint32_t boffs = 0, woffs = ops->ooboffs;
2532 size_t bytes = 0;
8593fbc6 2533
f8ac0414 2534 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2535 /* Write request not from offset 0? */
7bc3312b
TG		 2536 if (unlikely(woffs)) {
2537 if (woffs >= free->length) {
2538 woffs -= free->length;
2539 continue;
2540 }
2541 boffs = free->offset + woffs;
2542 bytes = min_t(size_t, len,
2543 (free->length - woffs));
2544 woffs = 0;
2545 } else {
2546 bytes = min_t(size_t, len, free->length);
2547 boffs = free->offset;
2548 }
8b0036ee 2549 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2550 oob += bytes;
2551 }
2552 return oob;
2553 }
2554 default:
2555 BUG();
2556 }
2557 return NULL;
2558}
2559
f8ac0414 2560#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2561
2562/**
7854d3f7 2563 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2564 * @mtd: MTD device structure
2565 * @to: offset to write to
2566 * @ops: oob operations description structure
1da177e4 2567 *
8b6e50c9 2568 * NAND write with ECC.
1da177e4 2569 */
8593fbc6
TG		 2570static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2571 struct mtd_oob_ops *ops)
1da177e4 2572{
29072b96 2573 int chipnr, realpage, page, blockmask, column;
862eba51 2574 struct nand_chip *chip = mtd_to_nand(mtd);
8593fbc6 2575 uint32_t writelen = ops->len;
782ce79a
ML		 2576
2577 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2578 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2579 mtd->oobavail : mtd->oobsize;
2580
8593fbc6
TG		 2581 uint8_t *oob = ops->oobbuf;
2582 uint8_t *buf = ops->datbuf;
837a6ba4 2583 int ret;
e47f3db4 2584 int oob_required = oob ? 1 : 0;
1da177e4 2585
8593fbc6 2586 ops->retlen = 0;
29072b96
TG		 2587 if (!writelen)
2588 return 0;
1da177e4 2589
8b6e50c9 2590 /* Reject writes, which are not page aligned */
8593fbc6 2591 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2592 pr_notice("%s: attempt to write non page aligned data\n",
2593 __func__);
1da177e4
LT		 2594 return -EINVAL;
2595 }
2596
29072b96 2597 column = to & (mtd->writesize - 1);
1da177e4 2598
6a930961
TG		 2599 chipnr = (int)(to >> chip->chip_shift);
2600 chip->select_chip(mtd, chipnr);
2601
1da177e4 2602 /* Check, if it is write protected */
b0bb6903
HS		 2603 if (nand_check_wp(mtd)) {
2604 ret = -EIO;
2605 goto err_out;
2606 }
1da177e4 2607
f75e5097
TG		 2608 realpage = (int)(to >> chip->page_shift);
2609 page = realpage & chip->pagemask;
2610 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2611
2612 /* Invalidate the page cache, when we write to the cached page */
537ab1bd
BN		 2613 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2614 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2615 chip->pagebuf = -1;
61b03bd7 2616
782ce79a 2617 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2618 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2619 ret = -EINVAL;
2620 goto err_out;
2621 }
782ce79a 2622
f8ac0414 2623 while (1) {
29072b96 2624 int bytes = mtd->writesize;
f75e5097 2625 int cached = writelen > bytes && page != blockmask;
29072b96 2626 uint8_t *wbuf = buf;
66507c7b
KD		 2627 int use_bufpoi;
2628 int part_pagewr = (column || writelen < (mtd->writesize - 1));
2629
2630 if (part_pagewr)
2631 use_bufpoi = 1;
2632 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2633 use_bufpoi = !virt_addr_valid(buf);
2634 else
2635 use_bufpoi = 0;
29072b96 2636
66507c7b
KD		 2637 /* Partial page write?, or need to use bounce buffer */
2638 if (use_bufpoi) {
2639 pr_debug("%s: using write bounce buffer for buf@%p\n",
2640 __func__, buf);
29072b96 2641 cached = 0;
66507c7b
KD		 2642 if (part_pagewr)
2643 bytes = min_t(int, bytes - column, writelen);
29072b96
TG		 2644 chip->pagebuf = -1;
2645 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2646 memcpy(&chip->buffers->databuf[column], buf, bytes);
2647 wbuf = chip->buffers->databuf;
2648 }
1da177e4 2649
782ce79a
ML		 2650 if (unlikely(oob)) {
2651 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2652 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2653 oobwritelen -= len;
f722013e
TAA		 2654 } else {
2655 /* We still need to erase leftover OOB data */
2656 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2657 }
837a6ba4
GP		 2658 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2659 oob_required, page, cached,
2660 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2661 if (ret)
2662 break;
2663
2664 writelen -= bytes;
2665 if (!writelen)
2666 break;
2667
29072b96 2668 column = 0;
f75e5097
TG		 2669 buf += bytes;
2670 realpage++;
2671
2672 page = realpage & chip->pagemask;
2673 /* Check, if we cross a chip boundary */
2674 if (!page) {
2675 chipnr++;
2676 chip->select_chip(mtd, -1);
2677 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2678 }
2679 }
8593fbc6 2680
8593fbc6 2681 ops->retlen = ops->len - writelen;
7014568b
VW		 2682 if (unlikely(oob))
2683 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2684
2685err_out:
2686 chip->select_chip(mtd, -1);
1da177e4
LT		 2687 return ret;
2688}
2689
2af7c653
SK		 2690/**
2691 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2692 * @mtd: MTD device structure
2693 * @to: offset to write to
2694 * @len: number of bytes to write
2695 * @retlen: pointer to variable to store the number of written bytes
2696 * @buf: the data to write
2af7c653
SK		 2697 *
2698 * NAND write with ECC. Used when performing writes in interrupt context, this
2699 * may for example be called by mtdoops when writing an oops while in panic.
2700 */
2701static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2702 size_t *retlen, const uint8_t *buf)
2703{
862eba51 2704 struct nand_chip *chip = mtd_to_nand(mtd);
4a89ff88 2705 struct mtd_oob_ops ops;
2af7c653
SK		 2706 int ret;
2707
8b6e50c9 2708 /* Wait for the device to get ready */
2af7c653
SK		 2709 panic_nand_wait(mtd, chip, 400);
2710
8b6e50c9 2711 /* Grab the device */
2af7c653
SK		 2712 panic_nand_get_device(chip, mtd, FL_WRITING);
2713
0ec56dc4 2714 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2715 ops.len = len;
2716 ops.datbuf = (uint8_t *)buf;
11041ae6 2717 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2718
4a89ff88 2719 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2720
4a89ff88 2721 *retlen = ops.retlen;
2af7c653
SK		 2722 return ret;
2723}
2724
f75e5097 2725/**
8593fbc6 2726 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2727 * @mtd: MTD device structure
2728 * @to: offset to write to
2729 * @len: number of bytes to write
2730 * @retlen: pointer to variable to store the number of written bytes
2731 * @buf: the data to write
f75e5097 2732 *
8b6e50c9 2733 * NAND write with ECC.
f75e5097 2734 */
8593fbc6
TG		 2735static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2736 size_t *retlen, const uint8_t *buf)
f75e5097 2737{
4a89ff88 2738 struct mtd_oob_ops ops;
f75e5097
TG		 2739 int ret;
2740
6a8214aa 2741 nand_get_device(mtd, FL_WRITING);
0ec56dc4 2742 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2743 ops.len = len;
2744 ops.datbuf = (uint8_t *)buf;
11041ae6 2745 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2746 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2747 *retlen = ops.retlen;
f75e5097 2748 nand_release_device(mtd);
8593fbc6 2749 return ret;
f75e5097 2750}
7314e9e7 2751
1da177e4 2752/**
8593fbc6 2753 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2754 * @mtd: MTD device structure
2755 * @to: offset to write to
2756 * @ops: oob operation description structure
1da177e4 2757 *
8b6e50c9 2758 * NAND write out-of-band.
1da177e4 2759 */
8593fbc6
TG		 2760static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2761 struct mtd_oob_ops *ops)
1da177e4 2762{
03736155 2763 int chipnr, page, status, len;
862eba51 2764 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 2765
289c0522 2766 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2767 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2768
0612b9dd 2769 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2770 len = chip->ecc.layout->oobavail;
2771 else
2772 len = mtd->oobsize;
2773
1da177e4 2774 /* Do not allow write past end of page */
03736155 2775 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2776 pr_debug("%s: attempt to write past end of page\n",
2777 __func__);
1da177e4
LT		 2778 return -EINVAL;
2779 }
2780
03736155 2781 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2782 pr_debug("%s: attempt to start write outside oob\n",
2783 __func__);
03736155
AH		 2784 return -EINVAL;
2785 }
2786
775adc3d 2787 /* Do not allow write past end of device */
03736155
AH		 2788 if (unlikely(to >= mtd->size ||
2789 ops->ooboffs + ops->ooblen >
2790 ((mtd->size >> chip->page_shift) -
2791 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2792 pr_debug("%s: attempt to write beyond end of device\n",
2793 __func__);
03736155
AH		 2794 return -EINVAL;
2795 }
2796
7314e9e7 2797 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2798 chip->select_chip(mtd, chipnr);
1da177e4 2799
7314e9e7
TG		 2800 /* Shift to get page */
2801 page = (int)(to >> chip->page_shift);
2802
2803 /*
2804 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2805 * of my DiskOnChip 2000 test units) will clear the whole data page too
2806 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2807 * it in the doc2000 driver in August 1999. dwmw2.
2808 */
ace4dfee 2809 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2810
2811 /* Check, if it is write protected */
b0bb6903
HS		 2812 if (nand_check_wp(mtd)) {
2813 chip->select_chip(mtd, -1);
8593fbc6 2814 return -EROFS;
b0bb6903 2815 }
61b03bd7 2816
1da177e4 2817 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2818 if (page == chip->pagebuf)
2819 chip->pagebuf = -1;
1da177e4 2820
f722013e 2821 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2822
0612b9dd 2823 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2824 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2825 else
2826 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2827
b0bb6903
HS		 2828 chip->select_chip(mtd, -1);
2829
7bc3312b
TG		 2830 if (status)
2831 return status;
1da177e4 2832
7014568b 2833 ops->oobretlen = ops->ooblen;
1da177e4 2834
7bc3312b 2835 return 0;
8593fbc6
TG		 2836}
2837
2838/**
2839 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2840 * @mtd: MTD device structure
2841 * @to: offset to write to
2842 * @ops: oob operation description structure
8593fbc6
TG		 2843 */
2844static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2845 struct mtd_oob_ops *ops)
2846{
8593fbc6
TG		 2847 int ret = -ENOTSUPP;
2848
2849 ops->retlen = 0;
2850
2851 /* Do not allow writes past end of device */
7014568b 2852 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2853 pr_debug("%s: attempt to write beyond end of device\n",
2854 __func__);
8593fbc6
TG		 2855 return -EINVAL;
2856 }
2857
6a8214aa 2858 nand_get_device(mtd, FL_WRITING);
8593fbc6 2859
f8ac0414 2860 switch (ops->mode) {
0612b9dd
BN		 2861 case MTD_OPS_PLACE_OOB:
2862 case MTD_OPS_AUTO_OOB:
2863 case MTD_OPS_RAW:
8593fbc6
TG		 2864 break;
2865
2866 default:
2867 goto out;
2868 }
2869
2870 if (!ops->datbuf)
2871 ret = nand_do_write_oob(mtd, to, ops);
2872 else
2873 ret = nand_do_write_ops(mtd, to, ops);
2874
7351d3a5 2875out:
1da177e4 2876 nand_release_device(mtd);
1da177e4
LT		 2877 return ret;
2878}
2879
1da177e4 2880/**
49c50b97 2881 * single_erase - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2882 * @mtd: MTD device structure
2883 * @page: the page address of the block which will be erased
1da177e4 2884 *
49c50b97 2885 * Standard erase command for NAND chips. Returns NAND status.
1da177e4 2886 */
49c50b97 2887static int single_erase(struct mtd_info *mtd, int page)
1da177e4 2888{
862eba51 2889 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 2890 /* Send commands to erase a block */
ace4dfee
TG		 2891 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2892 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
49c50b97
BN		 2893
2894 return chip->waitfunc(mtd, chip);
1da177e4
LT		 2895}
2896
1da177e4
LT		 2897/**
2898 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2899 * @mtd: MTD device structure
2900 * @instr: erase instruction
1da177e4 2901 *
8b6e50c9 2902 * Erase one ore more blocks.
1da177e4 2903 */
e0c7d767 2904static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2905{
e0c7d767 2906 return nand_erase_nand(mtd, instr, 0);
1da177e4 2907}
61b03bd7 2908
1da177e4 2909/**
7854d3f7 2910 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2911 * @mtd: MTD device structure
2912 * @instr: erase instruction
2913 * @allowbbt: allow erasing the bbt area
1da177e4 2914 *
8b6e50c9 2915 * Erase one ore more blocks.
1da177e4 2916 */
ace4dfee
TG		 2917int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2918 int allowbbt)
1da177e4 2919{
69423d99 2920 int page, status, pages_per_block, ret, chipnr;
862eba51 2921 struct nand_chip *chip = mtd_to_nand(mtd);
69423d99 2922 loff_t len;
1da177e4 2923
289c0522
BN		 2924 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2925 __func__, (unsigned long long)instr->addr,
2926 (unsigned long long)instr->len);
1da177e4 2927
6fe5a6ac 2928 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2929 return -EINVAL;
1da177e4 2930
1da177e4 2931 /* Grab the lock and see if the device is available */
6a8214aa 2932 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 2933
2934 /* Shift to get first page */
ace4dfee
TG		 2935 page = (int)(instr->addr >> chip->page_shift);
2936 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2937
2938 /* Calculate pages in each block */
ace4dfee 2939 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2940
2941 /* Select the NAND device */
ace4dfee 2942 chip->select_chip(mtd, chipnr);
1da177e4 2943
1da177e4
LT		 2944 /* Check, if it is write protected */
2945 if (nand_check_wp(mtd)) {
289c0522
BN		 2946 pr_debug("%s: device is write protected!\n",
2947 __func__);
1da177e4
LT		 2948 instr->state = MTD_ERASE_FAILED;
2949 goto erase_exit;
2950 }
2951
2952 /* Loop through the pages */
2953 len = instr->len;
2954
2955 instr->state = MTD_ERASING;
2956
2957 while (len) {
12183a20 2958 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2959 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2960 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2961 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2962 __func__, page);
1da177e4
LT		 2963 instr->state = MTD_ERASE_FAILED;
2964 goto erase_exit;
2965 }
61b03bd7 2966
ace4dfee
TG		 2967 /*
2968 * Invalidate the page cache, if we erase the block which
8b6e50c9 2969 * contains the current cached page.
ace4dfee
TG		 2970 */
2971 if (page <= chip->pagebuf && chip->pagebuf <
2972 (page + pages_per_block))
2973 chip->pagebuf = -1;
1da177e4 2974
49c50b97 2975 status = chip->erase(mtd, page & chip->pagemask);
1da177e4 2976
ace4dfee
TG		 2977 /*
2978 * See if operation failed and additional status checks are
2979 * available
2980 */
2981 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2982 status = chip->errstat(mtd, chip, FL_ERASING,
2983 status, page);
068e3c0a 2984
1da177e4 2985 /* See if block erase succeeded */
a4ab4c5d 2986 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2987 pr_debug("%s: failed erase, page 0x%08x\n",
2988 __func__, page);
1da177e4 2989 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2990 instr->fail_addr =
2991 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2992 goto erase_exit;
2993 }
30f464b7 2994
1da177e4 2995 /* Increment page address and decrement length */
daae74ca 2996 len -= (1ULL << chip->phys_erase_shift);
1da177e4
LT		 2997 page += pages_per_block;
2998
2999 /* Check, if we cross a chip boundary */
ace4dfee 3000 if (len && !(page & chip->pagemask)) {
1da177e4 3001 chipnr++;
ace4dfee
TG		 3002 chip->select_chip(mtd, -1);
3003 chip->select_chip(mtd, chipnr);
1da177e4
LT		 3004 }
3005 }
3006 instr->state = MTD_ERASE_DONE;
3007
7351d3a5 3008erase_exit:
1da177e4
LT		 3009
3010 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 3011
3012 /* Deselect and wake up anyone waiting on the device */
b0bb6903 3013 chip->select_chip(mtd, -1);
1da177e4
LT		 3014 nand_release_device(mtd);
3015
49defc01
DW		 3016 /* Do call back function */
3017 if (!ret)
3018 mtd_erase_callback(instr);
3019
1da177e4
LT		 3020 /* Return more or less happy */
3021 return ret;
3022}
3023
3024/**
3025 * nand_sync - [MTD Interface] sync
8b6e50c9 3026 * @mtd: MTD device structure
1da177e4 3027 *
8b6e50c9 3028 * Sync is actually a wait for chip ready function.
1da177e4 3029 */
e0c7d767 3030static void nand_sync(struct mtd_info *mtd)
1da177e4 3031{
289c0522 3032 pr_debug("%s: called\n", __func__);
1da177e4
LT		 3033
3034 /* Grab the lock and see if the device is available */
6a8214aa 3035 nand_get_device(mtd, FL_SYNCING);
1da177e4 3036 /* Release it and go back */
e0c7d767 3037 nand_release_device(mtd);
1da177e4
LT		 3038}
3039
1da177e4 3040/**
ace4dfee 3041 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 3042 * @mtd: MTD device structure
3043 * @offs: offset relative to mtd start
1da177e4 3044 */
ace4dfee 3045static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 3046{
ace4dfee 3047 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 3048}
3049
3050/**
ace4dfee 3051 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 3052 * @mtd: MTD device structure
3053 * @ofs: offset relative to mtd start
1da177e4 3054 */
e0c7d767 3055static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 3056{
1da177e4
LT		 3057 int ret;
3058
f8ac0414
FF		 3059 ret = nand_block_isbad(mtd, ofs);
3060 if (ret) {
8b6e50c9 3061 /* If it was bad already, return success and do nothing */
1da177e4
LT		 3062 if (ret > 0)
3063 return 0;
e0c7d767
DW		 3064 return ret;
3065 }
1da177e4 3066
5a0edb25 3067 return nand_block_markbad_lowlevel(mtd, ofs);
1da177e4
LT		 3068}
3069
7db03ecc
HS		 3070/**
3071 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3072 * @mtd: MTD device structure
3073 * @chip: nand chip info structure
3074 * @addr: feature address.
3075 * @subfeature_param: the subfeature parameters, a four bytes array.
3076 */
3077static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3078 int addr, uint8_t *subfeature_param)
3079{
3080 int status;
05f78359 3081 int i;
7db03ecc 3082
d914c932
DM		 3083 if (!chip->onfi_version ||
3084 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3085 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 3086 return -EINVAL;
3087
3088 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
05f78359
UKK		 3089 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3090 chip->write_byte(mtd, subfeature_param[i]);
3091
7db03ecc
HS		 3092 status = chip->waitfunc(mtd, chip);
3093 if (status & NAND_STATUS_FAIL)
3094 return -EIO;
3095 return 0;
3096}
3097
3098/**
3099 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3100 * @mtd: MTD device structure
3101 * @chip: nand chip info structure
3102 * @addr: feature address.
3103 * @subfeature_param: the subfeature parameters, a four bytes array.
3104 */
3105static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3106 int addr, uint8_t *subfeature_param)
3107{
05f78359
UKK		 3108 int i;
3109
d914c932
DM		 3110 if (!chip->onfi_version ||
3111 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3112 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 3113 return -EINVAL;
3114
7db03ecc 3115 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
05f78359
UKK		 3116 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3117 *subfeature_param++ = chip->read_byte(mtd);
7db03ecc
HS		 3118 return 0;
3119}
3120
962034f4
VW		 3121/**
3122 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 3123 * @mtd: MTD device structure
962034f4
VW		 3124 */
3125static int nand_suspend(struct mtd_info *mtd)
3126{
6a8214aa 3127 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 3128}
3129
3130/**
3131 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 3132 * @mtd: MTD device structure
962034f4
VW		 3133 */
3134static void nand_resume(struct mtd_info *mtd)
3135{
862eba51 3136 struct nand_chip *chip = mtd_to_nand(mtd);
962034f4 3137
ace4dfee 3138 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 3139 nand_release_device(mtd);
3140 else
d0370219
BN		 3141 pr_err("%s called for a chip which is not in suspended state\n",
3142 __func__);
962034f4
VW		 3143}
3144
72ea4036
SB		 3145/**
3146 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3147 * prevent further operations
3148 * @mtd: MTD device structure
3149 */
3150static void nand_shutdown(struct mtd_info *mtd)
3151{
9ca641b0 3152 nand_get_device(mtd, FL_PM_SUSPENDED);
72ea4036
SB		 3153}
3154
8b6e50c9 3155/* Set default functions */
ace4dfee 3156static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 3157{
1da177e4 3158 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 3159 if (!chip->chip_delay)
3160 chip->chip_delay = 20;
1da177e4
LT		 3161
3162 /* check, if a user supplied command function given */
ace4dfee
TG		 3163 if (chip->cmdfunc == NULL)
3164 chip->cmdfunc = nand_command;
1da177e4
LT		 3165
3166 /* check, if a user supplied wait function given */
ace4dfee
TG		 3167 if (chip->waitfunc == NULL)
3168 chip->waitfunc = nand_wait;
3169
3170 if (!chip->select_chip)
3171 chip->select_chip = nand_select_chip;
68e80780 3172
4204cccd
HS		 3173 /* set for ONFI nand */
3174 if (!chip->onfi_set_features)
3175 chip->onfi_set_features = nand_onfi_set_features;
3176 if (!chip->onfi_get_features)
3177 chip->onfi_get_features = nand_onfi_get_features;
3178
68e80780
BN		 3179 /* If called twice, pointers that depend on busw may need to be reset */
3180 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 3181 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3182 if (!chip->read_word)
3183 chip->read_word = nand_read_word;
3184 if (!chip->block_bad)
3185 chip->block_bad = nand_block_bad;
3186 if (!chip->block_markbad)
3187 chip->block_markbad = nand_default_block_markbad;
68e80780 3188 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 3189 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
05f78359
UKK		 3190 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3191 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
68e80780 3192 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 3193 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 3194 if (!chip->scan_bbt)
3195 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 3196
3197 if (!chip->controller) {
3198 chip->controller = &chip->hwcontrol;
3199 spin_lock_init(&chip->controller->lock);
3200 init_waitqueue_head(&chip->controller->wq);
3201 }
3202
7aa65bfd
TG		 3203}
3204
8b6e50c9 3205/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 3206static void sanitize_string(uint8_t *s, size_t len)
3207{
3208 ssize_t i;
3209
8b6e50c9 3210 /* Null terminate */
d1e1f4e4
FF		 3211 s[len - 1] = 0;
3212
8b6e50c9 3213 /* Remove non printable chars */
d1e1f4e4
FF		 3214 for (i = 0; i < len - 1; i++) {
3215 if (s[i] < ' ' || s[i] > 127)
3216 s[i] = '?';
3217 }
3218
8b6e50c9 3219 /* Remove trailing spaces */
d1e1f4e4
FF		 3220 strim(s);
3221}
3222
3223static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3224{
3225 int i;
3226 while (len--) {
3227 crc ^= *p++ << 8;
3228 for (i = 0; i < 8; i++)
3229 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3230 }
3231
3232 return crc;
3233}
3234
6dcbe0cd
HS		 3235/* Parse the Extended Parameter Page. */
3236static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3237 struct nand_chip *chip, struct nand_onfi_params *p)
3238{
3239 struct onfi_ext_param_page *ep;
3240 struct onfi_ext_section *s;
3241 struct onfi_ext_ecc_info *ecc;
3242 uint8_t *cursor;
3243 int ret = -EINVAL;
3244 int len;
3245 int i;
3246
3247 len = le16_to_cpu(p->ext_param_page_length) * 16;
3248 ep = kmalloc(len, GFP_KERNEL);
5cb13271
BN		 3249 if (!ep)
3250 return -ENOMEM;
6dcbe0cd
HS		 3251
3252 /* Send our own NAND_CMD_PARAM. */
3253 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3254
3255 /* Use the Change Read Column command to skip the ONFI param pages. */
3256 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3257 sizeof(*p) * p->num_of_param_pages , -1);
3258
3259 /* Read out the Extended Parameter Page. */
3260 chip->read_buf(mtd, (uint8_t *)ep, len);
3261 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3262 != le16_to_cpu(ep->crc))) {
3263 pr_debug("fail in the CRC.\n");
3264 goto ext_out;
3265 }
3266
3267 /*
3268 * Check the signature.
3269 * Do not strictly follow the ONFI spec, maybe changed in future.
3270 */
3271 if (strncmp(ep->sig, "EPPS", 4)) {
3272 pr_debug("The signature is invalid.\n");
3273 goto ext_out;
3274 }
3275
3276 /* find the ECC section. */
3277 cursor = (uint8_t *)(ep + 1);
3278 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3279 s = ep->sections + i;
3280 if (s->type == ONFI_SECTION_TYPE_2)
3281 break;
3282 cursor += s->length * 16;
3283 }
3284 if (i == ONFI_EXT_SECTION_MAX) {
3285 pr_debug("We can not find the ECC section.\n");
3286 goto ext_out;
3287 }
3288
3289 /* get the info we want. */
3290 ecc = (struct onfi_ext_ecc_info *)cursor;
3291
4ae7d228
BN		 3292 if (!ecc->codeword_size) {
3293 pr_debug("Invalid codeword size\n");
3294 goto ext_out;
6dcbe0cd
HS		 3295 }
3296
4ae7d228
BN		 3297 chip->ecc_strength_ds = ecc->ecc_bits;
3298 chip->ecc_step_ds = 1 << ecc->codeword_size;
5cb13271 3299 ret = 0;
6dcbe0cd
HS		 3300
3301ext_out:
3302 kfree(ep);
3303 return ret;
3304}
3305
8429bb39
BN		 3306static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3307{
862eba51 3308 struct nand_chip *chip = mtd_to_nand(mtd);
8429bb39
BN		 3309 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3310
3311 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3312 feature);
3313}
3314
3315/*
3316 * Configure chip properties from Micron vendor-specific ONFI table
3317 */
3318static void nand_onfi_detect_micron(struct nand_chip *chip,
3319 struct nand_onfi_params *p)
3320{
3321 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3322
3323 if (le16_to_cpu(p->vendor_revision) < 1)
3324 return;
3325
3326 chip->read_retries = micron->read_retry_options;
3327 chip->setup_read_retry = nand_setup_read_retry_micron;
3328}
3329
6fb277ba 3330/*
8b6e50c9 3331 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 3332 */
3333static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 3334 int *busw)
6fb277ba
FF		 3335{
3336 struct nand_onfi_params *p = &chip->onfi_params;
bd9c6e99 3337 int i, j;
6fb277ba
FF		 3338 int val;
3339
7854d3f7 3340 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 3341 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3342 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3343 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3344 return 0;
3345
6fb277ba
FF		 3346 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3347 for (i = 0; i < 3; i++) {
bd9c6e99
BN		 3348 for (j = 0; j < sizeof(*p); j++)
3349 ((uint8_t *)p)[j] = chip->read_byte(mtd);
6fb277ba
FF		 3350 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3351 le16_to_cpu(p->crc)) {
6fb277ba
FF		 3352 break;
3353 }
3354 }
3355
c7f23a70
BN		 3356 if (i == 3) {
3357 pr_err("Could not find valid ONFI parameter page; aborting\n");
6fb277ba 3358 return 0;
c7f23a70 3359 }
6fb277ba 3360
8b6e50c9 3361 /* Check version */
6fb277ba 3362 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 3363 if (val & (1 << 5))
3364 chip->onfi_version = 23;
3365 else if (val & (1 << 4))
6fb277ba
FF		 3366 chip->onfi_version = 22;
3367 else if (val & (1 << 3))
3368 chip->onfi_version = 21;
3369 else if (val & (1 << 2))
3370 chip->onfi_version = 20;
b7b1a29d 3371 else if (val & (1 << 1))
6fb277ba 3372 chip->onfi_version = 10;
b7b1a29d
BN		 3373
3374 if (!chip->onfi_version) {
20171642 3375 pr_info("unsupported ONFI version: %d\n", val);
b7b1a29d
BN		 3376 return 0;
3377 }
6fb277ba
FF		 3378
3379 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3380 sanitize_string(p->model, sizeof(p->model));
3381 if (!mtd->name)
3382 mtd->name = p->model;
4355b70c 3383
6fb277ba 3384 mtd->writesize = le32_to_cpu(p->byte_per_page);
4355b70c
BN		 3385
3386 /*
3387 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3388 * (don't ask me who thought of this...). MTD assumes that these
3389 * dimensions will be power-of-2, so just truncate the remaining area.
3390 */
3391 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3392 mtd->erasesize *= mtd->writesize;
3393
6fb277ba 3394 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4355b70c
BN		 3395
3396 /* See erasesize comment */
3397 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3398 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
13fbd179 3399 chip->bits_per_cell = p->bits_per_cell;
e2985fc1
HS		 3400
3401 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
08c248fb 3402 *busw = NAND_BUSWIDTH_16;
e2985fc1
HS		 3403 else
3404 *busw = 0;
6fb277ba 3405
10c86bab
HS		 3406 if (p->ecc_bits != 0xff) {
3407 chip->ecc_strength_ds = p->ecc_bits;
3408 chip->ecc_step_ds = 512;
6dcbe0cd
HS		 3409 } else if (chip->onfi_version >= 21 &&
3410 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3411
3412 /*
3413 * The nand_flash_detect_ext_param_page() uses the
3414 * Change Read Column command which maybe not supported
3415 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3416 * now. We do not replace user supplied command function.
3417 */
3418 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3419 chip->cmdfunc = nand_command_lp;
3420
3421 /* The Extended Parameter Page is supported since ONFI 2.1. */
3422 if (nand_flash_detect_ext_param_page(mtd, chip, p))
c7f23a70
BN		 3423 pr_warn("Failed to detect ONFI extended param page\n");
3424 } else {
3425 pr_warn("Could not retrieve ONFI ECC requirements\n");
10c86bab
HS		 3426 }
3427
8429bb39
BN		 3428 if (p->jedec_id == NAND_MFR_MICRON)
3429 nand_onfi_detect_micron(chip, p);
3430
6fb277ba
FF		 3431 return 1;
3432}
3433
91361818
HS		 3434/*
3435 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3436 */
3437static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3438 int *busw)
3439{
3440 struct nand_jedec_params *p = &chip->jedec_params;
3441 struct jedec_ecc_info *ecc;
3442 int val;
3443 int i, j;
3444
3445 /* Try JEDEC for unknown chip or LP */
3446 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3447 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3448 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3449 chip->read_byte(mtd) != 'C')
3450 return 0;
3451
3452 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3453 for (i = 0; i < 3; i++) {
3454 for (j = 0; j < sizeof(*p); j++)
3455 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3456
3457 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3458 le16_to_cpu(p->crc))
3459 break;
3460 }
3461
3462 if (i == 3) {
3463 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3464 return 0;
3465 }
3466
3467 /* Check version */
3468 val = le16_to_cpu(p->revision);
3469 if (val & (1 << 2))
3470 chip->jedec_version = 10;
3471 else if (val & (1 << 1))
3472 chip->jedec_version = 1; /* vendor specific version */
3473
3474 if (!chip->jedec_version) {
3475 pr_info("unsupported JEDEC version: %d\n", val);
3476 return 0;
3477 }
3478
3479 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3480 sanitize_string(p->model, sizeof(p->model));
3481 if (!mtd->name)
3482 mtd->name = p->model;
3483
3484 mtd->writesize = le32_to_cpu(p->byte_per_page);
3485
3486 /* Please reference to the comment for nand_flash_detect_onfi. */
3487 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3488 mtd->erasesize *= mtd->writesize;
3489
3490 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3491
3492 /* Please reference to the comment for nand_flash_detect_onfi. */
3493 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3494 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3495 chip->bits_per_cell = p->bits_per_cell;
3496
3497 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3498 *busw = NAND_BUSWIDTH_16;
3499 else
3500 *busw = 0;
3501
3502 /* ECC info */
3503 ecc = &p->ecc_info[0];
3504
3505 if (ecc->codeword_size >= 9) {
3506 chip->ecc_strength_ds = ecc->ecc_bits;
3507 chip->ecc_step_ds = 1 << ecc->codeword_size;
3508 } else {
3509 pr_warn("Invalid codeword size\n");
3510 }
3511
3512 return 1;
3513}
3514
e3b88bd6
BN		 3515/*
3516 * nand_id_has_period - Check if an ID string has a given wraparound period
3517 * @id_data: the ID string
3518 * @arrlen: the length of the @id_data array
3519 * @period: the period of repitition
3520 *
3521 * Check if an ID string is repeated within a given sequence of bytes at
3522 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3523 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3524 * if the repetition has a period of @period; otherwise, returns zero.
3525 */
3526static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3527{
3528 int i, j;
3529 for (i = 0; i < period; i++)
3530 for (j = i + period; j < arrlen; j += period)
3531 if (id_data[i] != id_data[j])
3532 return 0;
3533 return 1;
3534}
3535
3536/*
3537 * nand_id_len - Get the length of an ID string returned by CMD_READID
3538 * @id_data: the ID string
3539 * @arrlen: the length of the @id_data array
3540
3541 * Returns the length of the ID string, according to known wraparound/trailing
3542 * zero patterns. If no pattern exists, returns the length of the array.
3543 */
3544static int nand_id_len(u8 *id_data, int arrlen)
3545{
3546 int last_nonzero, period;
3547
3548 /* Find last non-zero byte */
3549 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3550 if (id_data[last_nonzero])
3551 break;
3552
3553 /* All zeros */
3554 if (last_nonzero < 0)
3555 return 0;
3556
3557 /* Calculate wraparound period */
3558 for (period = 1; period < arrlen; period++)
3559 if (nand_id_has_period(id_data, arrlen, period))
3560 break;
3561
3562 /* There's a repeated pattern */
3563 if (period < arrlen)
3564 return period;
3565
3566 /* There are trailing zeros */
3567 if (last_nonzero < arrlen - 1)
3568 return last_nonzero + 1;
3569
3570 /* No pattern detected */
3571 return arrlen;
3572}
3573
7db906b7
HS		 3574/* Extract the bits of per cell from the 3rd byte of the extended ID */
3575static int nand_get_bits_per_cell(u8 cellinfo)
3576{
3577 int bits;
3578
3579 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3580 bits >>= NAND_CI_CELLTYPE_SHIFT;
3581 return bits + 1;
3582}
3583
fc09bbc0
BN		 3584/*
3585 * Many new NAND share similar device ID codes, which represent the size of the
3586 * chip. The rest of the parameters must be decoded according to generic or
3587 * manufacturer-specific "extended ID" decoding patterns.
3588 */
3589static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3590 u8 id_data[8], int *busw)
3591{
e3b88bd6 3592 int extid, id_len;
fc09bbc0 3593 /* The 3rd id byte holds MLC / multichip data */
7db906b7 3594 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
fc09bbc0
BN		 3595 /* The 4th id byte is the important one */
3596 extid = id_data[3];
3597
e3b88bd6
BN		 3598 id_len = nand_id_len(id_data, 8);
3599
fc09bbc0
BN		 3600 /*
3601 * Field definitions are in the following datasheets:
3602 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 3603 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 3604 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 3605 *
af451af4
BN		 3606 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3607 * ID to decide what to do.
fc09bbc0 3608 */
af451af4 3609 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
1d0ed69d 3610 !nand_is_slc(chip) && id_data[5] != 0x00) {
fc09bbc0
BN		 3611 /* Calc pagesize */
3612 mtd->writesize = 2048 << (extid & 0x03);
3613 extid >>= 2;
3614 /* Calc oobsize */
e2d3a35e 3615 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 3616 case 1:
3617 mtd->oobsize = 128;
3618 break;
3619 case 2:
3620 mtd->oobsize = 218;
3621 break;
3622 case 3:
3623 mtd->oobsize = 400;
3624 break;
e2d3a35e 3625 case 4:
fc09bbc0
BN		 3626 mtd->oobsize = 436;
3627 break;
e2d3a35e
BN		 3628 case 5:
3629 mtd->oobsize = 512;
3630 break;
3631 case 6:
e2d3a35e
BN		 3632 mtd->oobsize = 640;
3633 break;
94d04e82
HS		 3634 case 7:
3635 default: /* Other cases are "reserved" (unknown) */
3636 mtd->oobsize = 1024;
3637 break;
fc09bbc0
BN		 3638 }
3639 extid >>= 2;
3640 /* Calc blocksize */
3641 mtd->erasesize = (128 * 1024) <<
3642 (((extid >> 1) & 0x04) | (extid & 0x03));
3643 *busw = 0;
73ca392f 3644 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
1d0ed69d 3645 !nand_is_slc(chip)) {
73ca392f
BN		 3646 unsigned int tmp;
3647
3648 /* Calc pagesize */
3649 mtd->writesize = 2048 << (extid & 0x03);
3650 extid >>= 2;
3651 /* Calc oobsize */
3652 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3653 case 0:
3654 mtd->oobsize = 128;
3655 break;
3656 case 1:
3657 mtd->oobsize = 224;
3658 break;
3659 case 2:
3660 mtd->oobsize = 448;
3661 break;
3662 case 3:
3663 mtd->oobsize = 64;
3664 break;
3665 case 4:
3666 mtd->oobsize = 32;
3667 break;
3668 case 5:
3669 mtd->oobsize = 16;
3670 break;
3671 default:
3672 mtd->oobsize = 640;
3673 break;
3674 }
3675 extid >>= 2;
3676 /* Calc blocksize */
3677 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3678 if (tmp < 0x03)
3679 mtd->erasesize = (128 * 1024) << tmp;
3680 else if (tmp == 0x03)
3681 mtd->erasesize = 768 * 1024;
3682 else
3683 mtd->erasesize = (64 * 1024) << tmp;
3684 *busw = 0;
fc09bbc0
BN		 3685 } else {
3686 /* Calc pagesize */
3687 mtd->writesize = 1024 << (extid & 0x03);
3688 extid >>= 2;
3689 /* Calc oobsize */
3690 mtd->oobsize = (8 << (extid & 0x01)) *
3691 (mtd->writesize >> 9);
3692 extid >>= 2;
3693 /* Calc blocksize. Blocksize is multiples of 64KiB */
3694 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3695 extid >>= 2;
3696 /* Get buswidth information */
3697 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
60c67382
BN		 3698
3699 /*
3700 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3701 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3702 * follows:
3703 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3704 * 110b -> 24nm
3705 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3706 */
3707 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
1d0ed69d 3708 nand_is_slc(chip) &&
60c67382
BN		 3709 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3710 !(id_data[4] & 0x80) /* !BENAND */) {
3711 mtd->oobsize = 32 * mtd->writesize >> 9;
3712 }
3713
fc09bbc0
BN		 3714 }
3715}
3716
f23a481c
BN		 3717/*
3718 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3719 * decodes a matching ID table entry and assigns the MTD size parameters for
3720 * the chip.
3721 */
3722static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3723 struct nand_flash_dev *type, u8 id_data[8],
3724 int *busw)
3725{
3726 int maf_id = id_data[0];
3727
3728 mtd->erasesize = type->erasesize;
3729 mtd->writesize = type->pagesize;
3730 mtd->oobsize = mtd->writesize / 32;
3731 *busw = type->options & NAND_BUSWIDTH_16;
3732
1c195e90
HS		 3733 /* All legacy ID NAND are small-page, SLC */
3734 chip->bits_per_cell = 1;
3735
f23a481c
BN		 3736 /*
3737 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3738 * some Spansion chips have erasesize that conflicts with size
3739 * listed in nand_ids table.
3740 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3741 */
3742 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3743 && id_data[6] == 0x00 && id_data[7] == 0x00
3744 && mtd->writesize == 512) {
3745 mtd->erasesize = 128 * 1024;
3746 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3747 }
3748}
3749
7e74c2d7
BN		 3750/*
3751 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3752 * heuristic patterns using various detected parameters (e.g., manufacturer,
3753 * page size, cell-type information).
3754 */
3755static void nand_decode_bbm_options(struct mtd_info *mtd,
3756 struct nand_chip *chip, u8 id_data[8])
3757{
3758 int maf_id = id_data[0];
3759
3760 /* Set the bad block position */
3761 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3762 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3763 else
3764 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3765
3766 /*
3767 * Bad block marker is stored in the last page of each block on Samsung
3768 * and Hynix MLC devices; stored in first two pages of each block on
3769 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3770 * AMD/Spansion, and Macronix. All others scan only the first page.
3771 */
1d0ed69d 3772 if (!nand_is_slc(chip) &&
7e74c2d7
BN		 3773 (maf_id == NAND_MFR_SAMSUNG ||
3774 maf_id == NAND_MFR_HYNIX))
3775 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
1d0ed69d 3776 else if ((nand_is_slc(chip) &&
7e74c2d7
BN		 3777 (maf_id == NAND_MFR_SAMSUNG ||
3778 maf_id == NAND_MFR_HYNIX ||
3779 maf_id == NAND_MFR_TOSHIBA ||
3780 maf_id == NAND_MFR_AMD ||
3781 maf_id == NAND_MFR_MACRONIX)) ||
3782 (mtd->writesize == 2048 &&
3783 maf_id == NAND_MFR_MICRON))
3784 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3785}
3786
ec6e87e3
HS		 3787static inline bool is_full_id_nand(struct nand_flash_dev *type)
3788{
3789 return type->id_len;
3790}
3791
3792static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3793 struct nand_flash_dev *type, u8 *id_data, int *busw)
3794{
3795 if (!strncmp(type->id, id_data, type->id_len)) {
3796 mtd->writesize = type->pagesize;
3797 mtd->erasesize = type->erasesize;
3798 mtd->oobsize = type->oobsize;
3799
7db906b7 3800 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
ec6e87e3
HS		 3801 chip->chipsize = (uint64_t)type->chipsize << 20;
3802 chip->options |= type->options;
57219342
HS		 3803 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3804 chip->ecc_step_ds = NAND_ECC_STEP(type);
57a94e24
BB		 3805 chip->onfi_timing_mode_default =
3806 type->onfi_timing_mode_default;
ec6e87e3
HS		 3807
3808 *busw = type->options & NAND_BUSWIDTH_16;
3809
092b6a1d
CZ		 3810 if (!mtd->name)
3811 mtd->name = type->name;
3812
ec6e87e3
HS		 3813 return true;
3814 }
3815 return false;
3816}
3817
7aa65bfd 3818/*
8b6e50c9 3819 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3820 */
3821static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3822 struct nand_chip *chip,
7351d3a5 3823 int *maf_id, int *dev_id,
5e81e88a 3824 struct nand_flash_dev *type)
7aa65bfd 3825{
bb77082f 3826 int busw;
d1e1f4e4 3827 int i, maf_idx;
426c457a 3828 u8 id_data[8];
1da177e4
LT		 3829
3830 /* Select the device */
ace4dfee 3831 chip->select_chip(mtd, 0);
1da177e4 3832
ef89a880
KB		 3833 /*
3834 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3835 * after power-up.
ef89a880
KB		 3836 */
3837 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3838
1da177e4 3839 /* Send the command for reading device ID */
ace4dfee 3840 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3841
3842 /* Read manufacturer and device IDs */
ace4dfee 3843 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3844 *dev_id = chip->read_byte(mtd);
1da177e4 3845
8b6e50c9
BN		 3846 /*
3847 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3848 * interface concerns can cause random data which looks like a
3849 * possibly credible NAND flash to appear. If the two results do
3850 * not match, ignore the device completely.
3851 */
3852
3853 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3854
4aef9b78
BN		 3855 /* Read entire ID string */
3856 for (i = 0; i < 8; i++)
426c457a 3857 id_data[i] = chip->read_byte(mtd);
ed8165c7 3858
d1e1f4e4 3859 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
20171642 3860 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
d0370219 3861 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3862 return ERR_PTR(-ENODEV);
3863 }
3864
7aa65bfd 3865 if (!type)
5e81e88a
DW		 3866 type = nand_flash_ids;
3867
ec6e87e3
HS		 3868 for (; type->name != NULL; type++) {
3869 if (is_full_id_nand(type)) {
3870 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3871 goto ident_done;
3872 } else if (*dev_id == type->dev_id) {
db5b09f6 3873 break;
ec6e87e3
HS		 3874 }
3875 }
5e81e88a 3876
d1e1f4e4
FF		 3877 chip->onfi_version = 0;
3878 if (!type->name || !type->pagesize) {
35fc5195 3879 /* Check if the chip is ONFI compliant */
47450b35 3880 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3881 goto ident_done;
91361818
HS		 3882
3883 /* Check if the chip is JEDEC compliant */
3884 if (nand_flash_detect_jedec(mtd, chip, &busw))
3885 goto ident_done;
d1e1f4e4
FF		 3886 }
3887
5e81e88a 3888 if (!type->name)
7aa65bfd
TG		 3889 return ERR_PTR(-ENODEV);
3890
ba0251fe
TG		 3891 if (!mtd->name)
3892 mtd->name = type->name;
3893
69423d99 3894 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3895
a7f5ba40 3896 if (!type->pagesize) {
fc09bbc0
BN		 3897 /* Decode parameters from extended ID */
3898 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3899 } else {
f23a481c 3900 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3901 }
bf7a01bf
BN		 3902 /* Get chip options */
3903 chip->options |= type->options;
d1e1f4e4 3904
8b6e50c9
BN		 3905 /*
3906 * Check if chip is not a Samsung device. Do not clear the
3907 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3908 */
3909 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3910 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3911ident_done:
3912
7aa65bfd 3913 /* Try to identify manufacturer */
9a909867 3914 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3915 if (nand_manuf_ids[maf_idx].id == *maf_id)
3916 break;
3917 }
0ea4a755 3918
64b37b2a
MC		 3919 if (chip->options & NAND_BUSWIDTH_AUTO) {
3920 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3921 chip->options |= busw;
3922 nand_set_defaults(chip, busw);
3923 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3924 /*
3925 * Check, if buswidth is correct. Hardware drivers should set
3926 * chip correct!
3927 */
20171642
EG		 3928 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3929 *maf_id, *dev_id);
3930 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3931 pr_warn("bus width %d instead %d bit\n",
d0370219
BN		 3932 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3933 busw ? 16 : 8);
7aa65bfd
TG		 3934 return ERR_PTR(-EINVAL);
3935 }
61b03bd7 3936
7e74c2d7
BN		 3937 nand_decode_bbm_options(mtd, chip, id_data);
3938
7aa65bfd 3939 /* Calculate the address shift from the page size */
ace4dfee 3940 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3941 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3942 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3943
ace4dfee 3944 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3945 ffs(mtd->erasesize) - 1;
69423d99
AH		 3946 if (chip->chipsize & 0xffffffff)
3947 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3948 else {
3949 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3950 chip->chip_shift += 32 - 1;
3951 }
1da177e4 3952
26d9be11 3953 chip->badblockbits = 8;
49c50b97 3954 chip->erase = single_erase;
7aa65bfd 3955
8b6e50c9 3956 /* Do not replace user supplied command function! */
ace4dfee
TG		 3957 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3958 chip->cmdfunc = nand_command_lp;
7aa65bfd 3959
20171642
EG		 3960 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3961 *maf_id, *dev_id);
ffdac6cd
HS		 3962
3963 if (chip->onfi_version)
3964 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3965 chip->onfi_params.model);
3966 else if (chip->jedec_version)
3967 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3968 chip->jedec_params.model);
3969 else
3970 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3971 type->name);
3972
3755a991 3973 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3723e93c 3974 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3755a991 3975 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3976 return type;
3977}
3978
7194a29a 3979static int nand_dt_init(struct nand_chip *chip)
5844feea 3980{
7194a29a 3981 struct device_node *dn = nand_get_flash_node(chip);
5844feea
BN		 3982 int ecc_mode, ecc_strength, ecc_step;
3983
7194a29a
BB		 3984 if (!dn)
3985 return 0;
3986
5844feea
BN		 3987 if (of_get_nand_bus_width(dn) == 16)
3988 chip->options |= NAND_BUSWIDTH_16;
3989
3990 if (of_get_nand_on_flash_bbt(dn))
3991 chip->bbt_options |= NAND_BBT_USE_FLASH;
3992
3993 ecc_mode = of_get_nand_ecc_mode(dn);
3994 ecc_strength = of_get_nand_ecc_strength(dn);
3995 ecc_step = of_get_nand_ecc_step_size(dn);
3996
3997 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
3998 (!(ecc_step >= 0) && ecc_strength >= 0)) {
3999 pr_err("must set both strength and step size in DT\n");
4000 return -EINVAL;
4001 }
4002
4003 if (ecc_mode >= 0)
4004 chip->ecc.mode = ecc_mode;
4005
4006 if (ecc_strength >= 0)
4007 chip->ecc.strength = ecc_strength;
4008
4009 if (ecc_step > 0)
4010 chip->ecc.size = ecc_step;
4011
4012 return 0;
4013}
4014
7aa65bfd 4015/**
3b85c321 4016 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4017 * @mtd: MTD device structure
4018 * @maxchips: number of chips to scan for
4019 * @table: alternative NAND ID table
7aa65bfd 4020 *
8b6e50c9
BN		 4021 * This is the first phase of the normal nand_scan() function. It reads the
4022 * flash ID and sets up MTD fields accordingly.
7aa65bfd 4023 *
3b85c321 4024 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 4025 */
5e81e88a
DW		 4026int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4027 struct nand_flash_dev *table)
7aa65bfd 4028{
bb77082f 4029 int i, nand_maf_id, nand_dev_id;
862eba51 4030 struct nand_chip *chip = mtd_to_nand(mtd);
7aa65bfd 4031 struct nand_flash_dev *type;
5844feea
BN		 4032 int ret;
4033
7194a29a
BB		 4034 ret = nand_dt_init(chip);
4035 if (ret)
4036 return ret;
7aa65bfd 4037
f7a8e38f
BN		 4038 if (!mtd->name && mtd->dev.parent)
4039 mtd->name = dev_name(mtd->dev.parent);
4040
7aa65bfd 4041 /* Set the default functions */
bb77082f 4042 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
7aa65bfd
TG		 4043
4044 /* Read the flash type */
bb77082f
CZ		 4045 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
4046 &nand_dev_id, table);
7aa65bfd
TG		 4047
4048 if (IS_ERR(type)) {
b1c6e6db 4049 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 4050 pr_warn("No NAND device found\n");
ace4dfee 4051 chip->select_chip(mtd, -1);
7aa65bfd 4052 return PTR_ERR(type);
1da177e4
LT		 4053 }
4054
07300164
HS		 4055 chip->select_chip(mtd, -1);
4056
7aa65bfd 4057 /* Check for a chip array */
e0c7d767 4058 for (i = 1; i < maxchips; i++) {
ace4dfee 4059 chip->select_chip(mtd, i);
ef89a880
KB		 4060 /* See comment in nand_get_flash_type for reset */
4061 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 4062 /* Send the command for reading device ID */
ace4dfee 4063 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 4064 /* Read manufacturer and device IDs */
ace4dfee 4065 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 4066 nand_dev_id != chip->read_byte(mtd)) {
4067 chip->select_chip(mtd, -1);
1da177e4 4068 break;
07300164
HS		 4069 }
4070 chip->select_chip(mtd, -1);
1da177e4
LT		 4071 }
4072 if (i > 1)
20171642 4073 pr_info("%d chips detected\n", i);
61b03bd7 4074
1da177e4 4075 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 4076 chip->numchips = i;
4077 mtd->size = i * chip->chipsize;
7aa65bfd 4078
3b85c321
DW		 4079 return 0;
4080}
7351d3a5 4081EXPORT_SYMBOL(nand_scan_ident);
3b85c321 4082
67a9ad9b
EG		 4083/*
4084 * Check if the chip configuration meet the datasheet requirements.
4085
4086 * If our configuration corrects A bits per B bytes and the minimum
4087 * required correction level is X bits per Y bytes, then we must ensure
4088 * both of the following are true:
4089 *
4090 * (1) A / B >= X / Y
4091 * (2) A >= X
4092 *
4093 * Requirement (1) ensures we can correct for the required bitflip density.
4094 * Requirement (2) ensures we can correct even when all bitflips are clumped
4095 * in the same sector.
4096 */
4097static bool nand_ecc_strength_good(struct mtd_info *mtd)
4098{
862eba51 4099 struct nand_chip *chip = mtd_to_nand(mtd);
67a9ad9b
EG		 4100 struct nand_ecc_ctrl *ecc = &chip->ecc;
4101 int corr, ds_corr;
4102
4103 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4104 /* Not enough information */
4105 return true;
4106
4107 /*
4108 * We get the number of corrected bits per page to compare
4109 * the correction density.
4110 */
4111 corr = (mtd->writesize * ecc->strength) / ecc->size;
4112 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4113
4114 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4115}
3b85c321
DW		 4116
4117/**
4118 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 4119 * @mtd: MTD device structure
3b85c321 4120 *
8b6e50c9
BN		 4121 * This is the second phase of the normal nand_scan() function. It fills out
4122 * all the uninitialized function pointers with the defaults and scans for a
4123 * bad block table if appropriate.
3b85c321
DW		 4124 */
4125int nand_scan_tail(struct mtd_info *mtd)
4126{
4127 int i;
862eba51 4128 struct nand_chip *chip = mtd_to_nand(mtd);
97de79e0 4129 struct nand_ecc_ctrl *ecc = &chip->ecc;
f02ea4e6 4130 struct nand_buffers *nbuf;
3b85c321 4131
e2414f4c
BN		 4132 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4133 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4134 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4135
f02ea4e6
HS		 4136 if (!(chip->options & NAND_OWN_BUFFERS)) {
4137 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4138 + mtd->oobsize * 3, GFP_KERNEL);
4139 if (!nbuf)
4140 return -ENOMEM;
4141 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4142 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4143 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4144
4145 chip->buffers = nbuf;
4146 } else {
4147 if (!chip->buffers)
4148 return -ENOMEM;
4149 }
4bf63fcb 4150
7dcdcbef 4151 /* Set the internal oob buffer location, just after the page data */
784f4d5e 4152 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 4153
7aa65bfd 4154 /*
8b6e50c9 4155 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 4156 */
97de79e0 4157 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 4158 switch (mtd->oobsize) {
1da177e4 4159 case 8:
97de79e0 4160 ecc->layout = &nand_oob_8;
1da177e4
LT		 4161 break;
4162 case 16:
97de79e0 4163 ecc->layout = &nand_oob_16;
1da177e4
LT		 4164 break;
4165 case 64:
97de79e0 4166 ecc->layout = &nand_oob_64;
1da177e4 4167 break;
81ec5364 4168 case 128:
97de79e0 4169 ecc->layout = &nand_oob_128;
81ec5364 4170 break;
1da177e4 4171 default:
d0370219
BN		 4172 pr_warn("No oob scheme defined for oobsize %d\n",
4173 mtd->oobsize);
1da177e4
LT		 4174 BUG();
4175 }
4176 }
61b03bd7 4177
956e944c
DW		 4178 if (!chip->write_page)
4179 chip->write_page = nand_write_page;
4180
61b03bd7 4181 /*
8b6e50c9 4182 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 4183 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 4184 */
956e944c 4185
97de79e0 4186 switch (ecc->mode) {
6e0cb135
SN		 4187 case NAND_ECC_HW_OOB_FIRST:
4188 /* Similar to NAND_ECC_HW, but a separate read_page handle */
97de79e0 4189 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
2ac63d90 4190 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
6e0cb135
SN		 4191 BUG();
4192 }
97de79e0
HS		 4193 if (!ecc->read_page)
4194 ecc->read_page = nand_read_page_hwecc_oob_first;
6e0cb135 4195
6dfc6d25 4196 case NAND_ECC_HW:
8b6e50c9 4197 /* Use standard hwecc read page function? */
97de79e0
HS		 4198 if (!ecc->read_page)
4199 ecc->read_page = nand_read_page_hwecc;
4200 if (!ecc->write_page)
4201 ecc->write_page = nand_write_page_hwecc;
4202 if (!ecc->read_page_raw)
4203 ecc->read_page_raw = nand_read_page_raw;
4204 if (!ecc->write_page_raw)
4205 ecc->write_page_raw = nand_write_page_raw;
4206 if (!ecc->read_oob)
4207 ecc->read_oob = nand_read_oob_std;
4208 if (!ecc->write_oob)
4209 ecc->write_oob = nand_write_oob_std;
4210 if (!ecc->read_subpage)
4211 ecc->read_subpage = nand_read_subpage;
44991b3d 4212 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
97de79e0 4213 ecc->write_subpage = nand_write_subpage_hwecc;
f5bbdacc 4214
6dfc6d25 4215 case NAND_ECC_HW_SYNDROME:
97de79e0
HS		 4216 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4217 (!ecc->read_page ||
4218 ecc->read_page == nand_read_page_hwecc ||
4219 !ecc->write_page ||
4220 ecc->write_page == nand_write_page_hwecc)) {
2ac63d90 4221 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
6dfc6d25
TG		 4222 BUG();
4223 }
8b6e50c9 4224 /* Use standard syndrome read/write page function? */
97de79e0
HS		 4225 if (!ecc->read_page)
4226 ecc->read_page = nand_read_page_syndrome;
4227 if (!ecc->write_page)
4228 ecc->write_page = nand_write_page_syndrome;
4229 if (!ecc->read_page_raw)
4230 ecc->read_page_raw = nand_read_page_raw_syndrome;
4231 if (!ecc->write_page_raw)
4232 ecc->write_page_raw = nand_write_page_raw_syndrome;
4233 if (!ecc->read_oob)
4234 ecc->read_oob = nand_read_oob_syndrome;
4235 if (!ecc->write_oob)
4236 ecc->write_oob = nand_write_oob_syndrome;
4237
4238 if (mtd->writesize >= ecc->size) {
4239 if (!ecc->strength) {
e2788c98
MD		 4240 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4241 BUG();
4242 }
6dfc6d25 4243 break;
e2788c98 4244 }
2ac63d90
RM		 4245 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4246 ecc->size, mtd->writesize);
97de79e0 4247 ecc->mode = NAND_ECC_SOFT;
61b03bd7 4248
6dfc6d25 4249 case NAND_ECC_SOFT:
97de79e0
HS		 4250 ecc->calculate = nand_calculate_ecc;
4251 ecc->correct = nand_correct_data;
4252 ecc->read_page = nand_read_page_swecc;
4253 ecc->read_subpage = nand_read_subpage;
4254 ecc->write_page = nand_write_page_swecc;
4255 ecc->read_page_raw = nand_read_page_raw;
4256 ecc->write_page_raw = nand_write_page_raw;
4257 ecc->read_oob = nand_read_oob_std;
4258 ecc->write_oob = nand_write_oob_std;
4259 if (!ecc->size)
4260 ecc->size = 256;
4261 ecc->bytes = 3;
4262 ecc->strength = 1;
1da177e4 4263 break;
61b03bd7 4264
193bd400
ID		 4265 case NAND_ECC_SOFT_BCH:
4266 if (!mtd_nand_has_bch()) {
148256fa 4267 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
193bd400
ID		 4268 BUG();
4269 }
97de79e0
HS		 4270 ecc->calculate = nand_bch_calculate_ecc;
4271 ecc->correct = nand_bch_correct_data;
4272 ecc->read_page = nand_read_page_swecc;
4273 ecc->read_subpage = nand_read_subpage;
4274 ecc->write_page = nand_write_page_swecc;
4275 ecc->read_page_raw = nand_read_page_raw;
4276 ecc->write_page_raw = nand_write_page_raw;
4277 ecc->read_oob = nand_read_oob_std;
4278 ecc->write_oob = nand_write_oob_std;
193bd400 4279 /*
e0377cde
AS		 4280 * Board driver should supply ecc.size and ecc.strength values
4281 * to select how many bits are correctable. Otherwise, default
4282 * to 4 bits for large page devices.
193bd400 4283 */
97de79e0
HS		 4284 if (!ecc->size && (mtd->oobsize >= 64)) {
4285 ecc->size = 512;
e0377cde 4286 ecc->strength = 4;
193bd400 4287 }
e0377cde
AS		 4288
4289 /* See nand_bch_init() for details. */
4290 ecc->bytes = DIV_ROUND_UP(
4291 ecc->strength * fls(8 * ecc->size), 8);
97de79e0
HS		 4292 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4293 &ecc->layout);
4294 if (!ecc->priv) {
9a4d4d69 4295 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 4296 BUG();
4297 }
4298 break;
4299
61b03bd7 4300 case NAND_ECC_NONE:
2ac63d90 4301 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
97de79e0
HS		 4302 ecc->read_page = nand_read_page_raw;
4303 ecc->write_page = nand_write_page_raw;
4304 ecc->read_oob = nand_read_oob_std;
4305 ecc->read_page_raw = nand_read_page_raw;
4306 ecc->write_page_raw = nand_write_page_raw;
4307 ecc->write_oob = nand_write_oob_std;
4308 ecc->size = mtd->writesize;
4309 ecc->bytes = 0;
4310 ecc->strength = 0;
1da177e4 4311 break;
956e944c 4312
1da177e4 4313 default:
97de79e0 4314 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
61b03bd7 4315 BUG();
1da177e4 4316 }
61b03bd7 4317
9ce244b3 4318 /* For many systems, the standard OOB write also works for raw */
97de79e0
HS		 4319 if (!ecc->read_oob_raw)
4320 ecc->read_oob_raw = ecc->read_oob;
4321 if (!ecc->write_oob_raw)
4322 ecc->write_oob_raw = ecc->write_oob;
9ce244b3 4323
5bd34c09
TG		 4324 /*
4325 * The number of bytes available for a client to place data into
8b6e50c9 4326 * the out of band area.
5bd34c09 4327 */
97de79e0
HS		 4328 ecc->layout->oobavail = 0;
4329 for (i = 0; ecc->layout->oobfree[i].length
4330 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4331 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4332 mtd->oobavail = ecc->layout->oobavail;
5bd34c09 4333
54c39e9b
TP		 4334 /* ECC sanity check: warn if it's too weak */
4335 if (!nand_ecc_strength_good(mtd))
4336 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4337 mtd->name);
67a9ad9b 4338
7aa65bfd
TG		 4339 /*
4340 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 4341 * mode.
7aa65bfd 4342 */
97de79e0
HS		 4343 ecc->steps = mtd->writesize / ecc->size;
4344 if (ecc->steps * ecc->size != mtd->writesize) {
9a4d4d69 4345 pr_warn("Invalid ECC parameters\n");
6dfc6d25 4346 BUG();
1da177e4 4347 }
97de79e0 4348 ecc->total = ecc->steps * ecc->bytes;
61b03bd7 4349
8b6e50c9 4350 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
1d0ed69d 4351 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
97de79e0 4352 switch (ecc->steps) {
29072b96
TG		 4353 case 2:
4354 mtd->subpage_sft = 1;
4355 break;
4356 case 4:
4357 case 8:
81ec5364 4358 case 16:
29072b96
TG		 4359 mtd->subpage_sft = 2;
4360 break;
4361 }
4362 }
4363 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4364
04bbd0ea 4365 /* Initialize state */
ace4dfee 4366 chip->state = FL_READY;
1da177e4 4367
1da177e4 4368 /* Invalidate the pagebuffer reference */
ace4dfee 4369 chip->pagebuf = -1;
1da177e4 4370
a5ff4f10 4371 /* Large page NAND with SOFT_ECC should support subpage reads */
4007e2d1
RL		 4372 switch (ecc->mode) {
4373 case NAND_ECC_SOFT:
4374 case NAND_ECC_SOFT_BCH:
4375 if (chip->page_shift > 9)
4376 chip->options |= NAND_SUBPAGE_READ;
4377 break;
4378
4379 default:
4380 break;
4381 }
a5ff4f10 4382
1da177e4 4383 /* Fill in remaining MTD driver data */
963d1c28 4384 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
93edbad6
ML		 4385 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4386 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 4387 mtd->_erase = nand_erase;
4388 mtd->_point = NULL;
4389 mtd->_unpoint = NULL;
4390 mtd->_read = nand_read;
4391 mtd->_write = nand_write;
4392 mtd->_panic_write = panic_nand_write;
4393 mtd->_read_oob = nand_read_oob;
4394 mtd->_write_oob = nand_write_oob;
4395 mtd->_sync = nand_sync;
4396 mtd->_lock = NULL;
4397 mtd->_unlock = NULL;
4398 mtd->_suspend = nand_suspend;
4399 mtd->_resume = nand_resume;
72ea4036 4400 mtd->_reboot = nand_shutdown;
8471bb73 4401 mtd->_block_isreserved = nand_block_isreserved;
3c3c10bb
AB		 4402 mtd->_block_isbad = nand_block_isbad;
4403 mtd->_block_markbad = nand_block_markbad;
cbcab65a 4404 mtd->writebufsize = mtd->writesize;
1da177e4 4405
6a918bad 4406 /* propagate ecc info to mtd_info */
97de79e0
HS		 4407 mtd->ecclayout = ecc->layout;
4408 mtd->ecc_strength = ecc->strength;
4409 mtd->ecc_step_size = ecc->size;
ea3b2ea2
SL		 4410 /*
4411 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4412 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4413 * properly set.
4414 */
4415 if (!mtd->bitflip_threshold)
240181fd 4416 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
1da177e4 4417
0040bf38 4418 /* Check, if we should skip the bad block table scan */
ace4dfee 4419 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 4420 return 0;
1da177e4
LT		 4421
4422 /* Build bad block table */
ace4dfee 4423 return chip->scan_bbt(mtd);
1da177e4 4424}
7351d3a5 4425EXPORT_SYMBOL(nand_scan_tail);
1da177e4 4426
8b6e50c9
BN		 4427/*
4428 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 4429 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 4430 * to call us from in-kernel code if the core NAND support is modular.
4431 */
3b85c321
DW		 4432#ifdef MODULE
4433#define caller_is_module() (1)
4434#else
4435#define caller_is_module() \
a6e6abd5 4436 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 4437#endif
4438
4439/**
4440 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4441 * @mtd: MTD device structure
4442 * @maxchips: number of chips to scan for
3b85c321 4443 *
8b6e50c9
BN		 4444 * This fills out all the uninitialized function pointers with the defaults.
4445 * The flash ID is read and the mtd/chip structures are filled with the
4446 * appropriate values. The mtd->owner field must be set to the module of the
4447 * caller.
3b85c321
DW		 4448 */
4449int nand_scan(struct mtd_info *mtd, int maxchips)
4450{
4451 int ret;
4452
4453 /* Many callers got this wrong, so check for it for a while... */
4454 if (!mtd->owner && caller_is_module()) {
d0370219 4455 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 4456 BUG();
4457 }
4458
5e81e88a 4459 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 4460 if (!ret)
4461 ret = nand_scan_tail(mtd);
4462 return ret;
4463}
7351d3a5 4464EXPORT_SYMBOL(nand_scan);
3b85c321 4465
1da177e4 4466/**
61b03bd7 4467 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 4468 * @mtd: MTD device structure
4469 */
e0c7d767 4470void nand_release(struct mtd_info *mtd)
1da177e4 4471{
862eba51 4472 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 4473
193bd400
ID		 4474 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4475 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4476
5ffcaf3d 4477 mtd_device_unregister(mtd);
1da177e4 4478
fa671646 4479 /* Free bad block table memory */
ace4dfee 4480 kfree(chip->bbt);
4bf63fcb
DW		 4481 if (!(chip->options & NAND_OWN_BUFFERS))
4482 kfree(chip->buffers);
58373ff0
BN		 4483
4484 /* Free bad block descriptor memory */
4485 if (chip->badblock_pattern && chip->badblock_pattern->options
4486 & NAND_BBT_DYNAMICSTRUCT)
4487 kfree(chip->badblock_pattern);
1da177e4 4488}
e0c7d767 4489EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 4490
4491static int __init nand_base_init(void)
4492{
4493 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4494 return 0;
4495}
4496
4497static void __exit nand_base_exit(void)
4498{
4499 led_trigger_unregister_simple(nand_led_trigger);
4500}
4501
4502module_init(nand_base_init);
4503module_exit(nand_base_exit);
4504
e0c7d767 4505MODULE_LICENSE("GPL");
7351d3a5
FF		 4506MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4507MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 4508MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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