projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mtd: use mtd_ooblayout_xxx() helpers where appropriate
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Overview:
3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
61b03bd7 5 *
1da177e4 6 * Additional technical information is available on
8b2b403c 7 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 8 *
1da177e4 9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 11 *
ace4dfee 12 * Credits:
61b03bd7
TG		 13 * David Woodhouse for adding multichip support
14 *
1da177e4
LT		 15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
17 *
ace4dfee 18 * TODO:
1da177e4
LT		 19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 21 * if we have HW ECC support.
c0b8ba7b 22 * BBT table is not serialized, has to be fixed
1da177e4 23 *
1da177e4
LT		 24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
20171642
EG		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
552d9205 32#include <linux/module.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/errno.h>
7aa65bfd 35#include <linux/err.h>
1da177e4
LT		 36#include <linux/sched.h>
37#include <linux/slab.h>
66507c7b 38#include <linux/mm.h>
1da177e4
LT		 39#include <linux/types.h>
40#include <linux/mtd/mtd.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/nand_ecc.h>
193bd400 43#include <linux/mtd/nand_bch.h>
1da177e4
LT		 44#include <linux/interrupt.h>
45#include <linux/bitops.h>
7351d3a5 46#include <linux/io.h>
1da177e4 47#include <linux/mtd/partitions.h>
5844feea 48#include <linux/of_mtd.h>
1da177e4
LT		 49
50/* Define default oob placement schemes for large and small page devices */
5bd34c09 51static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 52 .eccbytes = 3,
53 .eccpos = {0, 1, 2},
5bd34c09
TG		 54 .oobfree = {
55 {.offset = 3,
56 .length = 2},
57 {.offset = 6,
f8ac0414 58 .length = 2} }
1da177e4
LT		 59};
60
5bd34c09 61static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 62 .eccbytes = 6,
63 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 64 .oobfree = {
65 {.offset = 8,
f8ac0414 66 . length = 8} }
1da177e4
LT		 67};
68
5bd34c09 69static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 70 .eccbytes = 24,
71 .eccpos = {
e0c7d767
DW		 72 40, 41, 42, 43, 44, 45, 46, 47,
73 48, 49, 50, 51, 52, 53, 54, 55,
74 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 75 .oobfree = {
76 {.offset = 2,
f8ac0414 77 .length = 38} }
1da177e4
LT		 78};
79
81ec5364
TG		 80static struct nand_ecclayout nand_oob_128 = {
81 .eccbytes = 48,
82 .eccpos = {
83 80, 81, 82, 83, 84, 85, 86, 87,
84 88, 89, 90, 91, 92, 93, 94, 95,
85 96, 97, 98, 99, 100, 101, 102, 103,
86 104, 105, 106, 107, 108, 109, 110, 111,
87 112, 113, 114, 115, 116, 117, 118, 119,
88 120, 121, 122, 123, 124, 125, 126, 127},
89 .oobfree = {
90 {.offset = 2,
f8ac0414 91 .length = 78} }
81ec5364
TG		 92};
93
6a8214aa 94static int nand_get_device(struct mtd_info *mtd, int new_state);
1da177e4 95
8593fbc6
TG		 96static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
97 struct mtd_oob_ops *ops);
98
6fe5a6ac
VS		 99static int check_offs_len(struct mtd_info *mtd,
100 loff_t ofs, uint64_t len)
101{
862eba51 102 struct nand_chip *chip = mtd_to_nand(mtd);
6fe5a6ac
VS		 103 int ret = 0;
104
105 /* Start address must align on block boundary */
daae74ca 106 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 107 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 108 ret = -EINVAL;
109 }
110
111 /* Length must align on block boundary */
daae74ca 112 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 113 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 114 ret = -EINVAL;
115 }
116
6fe5a6ac
VS		 117 return ret;
118}
119
1da177e4
LT		 120/**
121 * nand_release_device - [GENERIC] release chip
8b6e50c9 122 * @mtd: MTD device structure
61b03bd7 123 *
b0bb6903 124 * Release chip lock and wake up anyone waiting on the device.
1da177e4 125 */
e0c7d767 126static void nand_release_device(struct mtd_info *mtd)
1da177e4 127{
862eba51 128 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 129
a36ed299 130 /* Release the controller and the chip */
ace4dfee
TG		 131 spin_lock(&chip->controller->lock);
132 chip->controller->active = NULL;
133 chip->state = FL_READY;
134 wake_up(&chip->controller->wq);
135 spin_unlock(&chip->controller->lock);
1da177e4
LT		 136}
137
138/**
139 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 140 * @mtd: MTD device structure
1da177e4 141 *
7854d3f7 142 * Default read function for 8bit buswidth
1da177e4 143 */
58dd8f2b 144static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 145{
862eba51 146 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 147 return readb(chip->IO_ADDR_R);
1da177e4
LT		 148}
149
1da177e4 150/**
7854d3f7 151 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 152 * @mtd: MTD device structure
1da177e4 153 *
7854d3f7
BN		 154 * Default read function for 16bit buswidth with endianness conversion.
155 *
1da177e4 156 */
58dd8f2b 157static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 158{
862eba51 159 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 160 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 161}
162
1da177e4
LT		 163/**
164 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 165 * @mtd: MTD device structure
1da177e4 166 *
7854d3f7 167 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 168 */
169static u16 nand_read_word(struct mtd_info *mtd)
170{
862eba51 171 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 172 return readw(chip->IO_ADDR_R);
1da177e4
LT		 173}
174
1da177e4
LT		 175/**
176 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 177 * @mtd: MTD device structure
178 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 179 *
180 * Default select function for 1 chip devices.
181 */
ace4dfee 182static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 183{
862eba51 184 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee
TG		 185
186 switch (chipnr) {
1da177e4 187 case -1:
ace4dfee 188 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 189 break;
190 case 0:
1da177e4
LT		 191 break;
192
193 default:
194 BUG();
195 }
196}
197
05f78359
UKK		 198/**
199 * nand_write_byte - [DEFAULT] write single byte to chip
200 * @mtd: MTD device structure
201 * @byte: value to write
202 *
203 * Default function to write a byte to I/O[7:0]
204 */
205static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
206{
862eba51 207 struct nand_chip *chip = mtd_to_nand(mtd);
05f78359
UKK		 208
209 chip->write_buf(mtd, &byte, 1);
210}
211
212/**
213 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
214 * @mtd: MTD device structure
215 * @byte: value to write
216 *
217 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
218 */
219static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
220{
862eba51 221 struct nand_chip *chip = mtd_to_nand(mtd);
05f78359
UKK		 222 uint16_t word = byte;
223
224 /*
225 * It's not entirely clear what should happen to I/O[15:8] when writing
226 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
227 *
228 * When the host supports a 16-bit bus width, only data is
229 * transferred at the 16-bit width. All address and command line
230 * transfers shall use only the lower 8-bits of the data bus. During
231 * command transfers, the host may place any value on the upper
232 * 8-bits of the data bus. During address transfers, the host shall
233 * set the upper 8-bits of the data bus to 00h.
234 *
235 * One user of the write_byte callback is nand_onfi_set_features. The
236 * four parameters are specified to be written to I/O[7:0], but this is
237 * neither an address nor a command transfer. Let's assume a 0 on the
238 * upper I/O lines is OK.
239 */
240 chip->write_buf(mtd, (uint8_t *)&word, 2);
241}
242
1da177e4
LT		 243/**
244 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 245 * @mtd: MTD device structure
246 * @buf: data buffer
247 * @len: number of bytes to write
1da177e4 248 *
7854d3f7 249 * Default write function for 8bit buswidth.
1da177e4 250 */
58dd8f2b 251static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 252{
862eba51 253 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 254
76413839 255 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 256}
257
258/**
61b03bd7 259 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 260 * @mtd: MTD device structure
261 * @buf: buffer to store date
262 * @len: number of bytes to read
1da177e4 263 *
7854d3f7 264 * Default read function for 8bit buswidth.
1da177e4 265 */
58dd8f2b 266static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 267{
862eba51 268 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 269
76413839 270 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 271}
272
1da177e4
LT		 273/**
274 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 275 * @mtd: MTD device structure
276 * @buf: data buffer
277 * @len: number of bytes to write
1da177e4 278 *
7854d3f7 279 * Default write function for 16bit buswidth.
1da177e4 280 */
58dd8f2b 281static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 282{
862eba51 283 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 284 u16 *p = (u16 *) buf;
61b03bd7 285
76413839 286 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 287}
288
289/**
61b03bd7 290 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 291 * @mtd: MTD device structure
292 * @buf: buffer to store date
293 * @len: number of bytes to read
1da177e4 294 *
7854d3f7 295 * Default read function for 16bit buswidth.
1da177e4 296 */
58dd8f2b 297static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 298{
862eba51 299 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 300 u16 *p = (u16 *) buf;
1da177e4 301
76413839 302 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 303}
304
1da177e4
LT		 305/**
306 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 307 * @mtd: MTD device structure
308 * @ofs: offset from device start
1da177e4 309 *
61b03bd7 310 * Check, if the block is bad.
1da177e4 311 */
9f3e0429 312static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
1da177e4 313{
9f3e0429 314 int page, res = 0, i = 0;
862eba51 315 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4
LT		 316 u16 bad;
317
5fb1549d 318 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 319 ofs += mtd->erasesize - mtd->writesize;
320
1a12f46a
TK		 321 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
322
cdbec050
BN		 323 do {
324 if (chip->options & NAND_BUSWIDTH_16) {
325 chip->cmdfunc(mtd, NAND_CMD_READOOB,
326 chip->badblockpos & 0xFE, page);
327 bad = cpu_to_le16(chip->read_word(mtd));
328 if (chip->badblockpos & 0x1)
329 bad >>= 8;
330 else
331 bad &= 0xFF;
332 } else {
333 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
334 page);
335 bad = chip->read_byte(mtd);
336 }
337
338 if (likely(chip->badblockbits == 8))
339 res = bad != 0xFF;
e0b58d0a 340 else
cdbec050
BN		 341 res = hweight8(bad) < chip->badblockbits;
342 ofs += mtd->writesize;
343 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
344 i++;
345 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 346
1da177e4
LT		 347 return res;
348}
349
350/**
5a0edb25 351 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
8b6e50c9
BN		 352 * @mtd: MTD device structure
353 * @ofs: offset from device start
1da177e4 354 *
8b6e50c9 355 * This is the default implementation, which can be overridden by a hardware
5a0edb25
BN		 356 * specific driver. It provides the details for writing a bad block marker to a
357 * block.
358 */
359static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
360{
862eba51 361 struct nand_chip *chip = mtd_to_nand(mtd);
5a0edb25
BN		 362 struct mtd_oob_ops ops;
363 uint8_t buf[2] = { 0, 0 };
364 int ret = 0, res, i = 0;
365
0ec56dc4 366 memset(&ops, 0, sizeof(ops));
5a0edb25
BN		 367 ops.oobbuf = buf;
368 ops.ooboffs = chip->badblockpos;
369 if (chip->options & NAND_BUSWIDTH_16) {
370 ops.ooboffs &= ~0x01;
371 ops.len = ops.ooblen = 2;
372 } else {
373 ops.len = ops.ooblen = 1;
374 }
375 ops.mode = MTD_OPS_PLACE_OOB;
376
377 /* Write to first/last page(s) if necessary */
378 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
379 ofs += mtd->erasesize - mtd->writesize;
380 do {
381 res = nand_do_write_oob(mtd, ofs, &ops);
382 if (!ret)
383 ret = res;
384
385 i++;
386 ofs += mtd->writesize;
387 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
388
389 return ret;
390}
391
392/**
393 * nand_block_markbad_lowlevel - mark a block bad
394 * @mtd: MTD device structure
395 * @ofs: offset from device start
396 *
397 * This function performs the generic NAND bad block marking steps (i.e., bad
398 * block table(s) and/or marker(s)). We only allow the hardware driver to
399 * specify how to write bad block markers to OOB (chip->block_markbad).
400 *
b32843b7 401 * We try operations in the following order:
e2414f4c 402 * (1) erase the affected block, to allow OOB marker to be written cleanly
b32843b7
BN		 403 * (2) write bad block marker to OOB area of affected block (unless flag
404 * NAND_BBT_NO_OOB_BBM is present)
405 * (3) update the BBT
406 * Note that we retain the first error encountered in (2) or (3), finish the
e2414f4c 407 * procedures, and dump the error in the end.
1da177e4 408*/
5a0edb25 409static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
1da177e4 410{
862eba51 411 struct nand_chip *chip = mtd_to_nand(mtd);
b32843b7 412 int res, ret = 0;
61b03bd7 413
b32843b7 414 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
00918429
BN		 415 struct erase_info einfo;
416
417 /* Attempt erase before marking OOB */
418 memset(&einfo, 0, sizeof(einfo));
419 einfo.mtd = mtd;
420 einfo.addr = ofs;
daae74ca 421 einfo.len = 1ULL << chip->phys_erase_shift;
00918429 422 nand_erase_nand(mtd, &einfo, 0);
1da177e4 423
b32843b7 424 /* Write bad block marker to OOB */
6a8214aa 425 nand_get_device(mtd, FL_WRITING);
5a0edb25 426 ret = chip->block_markbad(mtd, ofs);
c0b8ba7b 427 nand_release_device(mtd);
f1a28c02 428 }
e2414f4c 429
b32843b7
BN		 430 /* Mark block bad in BBT */
431 if (chip->bbt) {
432 res = nand_markbad_bbt(mtd, ofs);
e2414f4c
BN		 433 if (!ret)
434 ret = res;
435 }
436
f1a28c02
TG		 437 if (!ret)
438 mtd->ecc_stats.badblocks++;
c0b8ba7b 439
f1a28c02 440 return ret;
1da177e4
LT		 441}
442
61b03bd7 443/**
1da177e4 444 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 445 * @mtd: MTD device structure
1da177e4 446 *
8b6e50c9
BN		 447 * Check, if the device is write protected. The function expects, that the
448 * device is already selected.
1da177e4 449 */
e0c7d767 450static int nand_check_wp(struct mtd_info *mtd)
1da177e4 451{
862eba51 452 struct nand_chip *chip = mtd_to_nand(mtd);
93edbad6 453
8b6e50c9 454 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 455 if (chip->options & NAND_BROKEN_XD)
456 return 0;
457
1da177e4 458 /* Check the WP bit */
ace4dfee
TG		 459 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
460 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 461}
462
8471bb73 463/**
c30e1f79 464 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
8471bb73
EG		 465 * @mtd: MTD device structure
466 * @ofs: offset from device start
467 *
c30e1f79 468 * Check if the block is marked as reserved.
8471bb73
EG		 469 */
470static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
471{
862eba51 472 struct nand_chip *chip = mtd_to_nand(mtd);
8471bb73
EG		 473
474 if (!chip->bbt)
475 return 0;
476 /* Return info from the table */
477 return nand_isreserved_bbt(mtd, ofs);
478}
479
1da177e4
LT		 480/**
481 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 482 * @mtd: MTD device structure
483 * @ofs: offset from device start
8b6e50c9 484 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 485 *
486 * Check, if the block is bad. Either by reading the bad block table or
487 * calling of the scan function.
488 */
9f3e0429 489static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
1da177e4 490{
862eba51 491 struct nand_chip *chip = mtd_to_nand(mtd);
61b03bd7 492
ace4dfee 493 if (!chip->bbt)
9f3e0429 494 return chip->block_bad(mtd, ofs);
61b03bd7 495
1da177e4 496 /* Return info from the table */
e0c7d767 497 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 498}
499
2af7c653
SK		 500/**
501 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 502 * @mtd: MTD device structure
503 * @timeo: Timeout
2af7c653
SK		 504 *
505 * Helper function for nand_wait_ready used when needing to wait in interrupt
506 * context.
507 */
508static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
509{
862eba51 510 struct nand_chip *chip = mtd_to_nand(mtd);
2af7c653
SK		 511 int i;
512
513 /* Wait for the device to get ready */
514 for (i = 0; i < timeo; i++) {
515 if (chip->dev_ready(mtd))
516 break;
517 touch_softlockup_watchdog();
518 mdelay(1);
519 }
520}
521
b70af9be
AS		 522/**
523 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
524 * @mtd: MTD device structure
525 *
526 * Wait for the ready pin after a command, and warn if a timeout occurs.
527 */
4b648b02 528void nand_wait_ready(struct mtd_info *mtd)
3b88775c 529{
862eba51 530 struct nand_chip *chip = mtd_to_nand(mtd);
b70af9be 531 unsigned long timeo = 400;
3b88775c 532
2af7c653 533 if (in_interrupt() || oops_in_progress)
b70af9be 534 return panic_nand_wait_ready(mtd, timeo);
2af7c653 535
7854d3f7 536 /* Wait until command is processed or timeout occurs */
b70af9be 537 timeo = jiffies + msecs_to_jiffies(timeo);
3b88775c 538 do {
ace4dfee 539 if (chip->dev_ready(mtd))
4c7e054f 540 return;
b70af9be 541 cond_resched();
61b03bd7 542 } while (time_before(jiffies, timeo));
b70af9be 543
9ebfdf5b
BN		 544 if (!chip->dev_ready(mtd))
545 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
3b88775c 546}
4b648b02 547EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 548
60c70d66
RQ		 549/**
550 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
551 * @mtd: MTD device structure
552 * @timeo: Timeout in ms
553 *
554 * Wait for status ready (i.e. command done) or timeout.
555 */
556static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
557{
862eba51 558 register struct nand_chip *chip = mtd_to_nand(mtd);
60c70d66
RQ		 559
560 timeo = jiffies + msecs_to_jiffies(timeo);
561 do {
562 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
563 break;
564 touch_softlockup_watchdog();
565 } while (time_before(jiffies, timeo));
566};
567
1da177e4
LT		 568/**
569 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 570 * @mtd: MTD device structure
571 * @command: the command to be sent
572 * @column: the column address for this command, -1 if none
573 * @page_addr: the page address for this command, -1 if none
1da177e4 574 *
8b6e50c9 575 * Send command to NAND device. This function is used for small page devices
51148f1f 576 * (512 Bytes per page).
1da177e4 577 */
7abd3ef9
TG		 578static void nand_command(struct mtd_info *mtd, unsigned int command,
579 int column, int page_addr)
1da177e4 580{
862eba51 581 register struct nand_chip *chip = mtd_to_nand(mtd);
7abd3ef9 582 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 583
8b6e50c9 584 /* Write out the command to the device */
1da177e4
LT		 585 if (command == NAND_CMD_SEQIN) {
586 int readcmd;
587
28318776 588 if (column >= mtd->writesize) {
1da177e4 589 /* OOB area */
28318776 590 column -= mtd->writesize;
1da177e4
LT		 591 readcmd = NAND_CMD_READOOB;
592 } else if (column < 256) {
593 /* First 256 bytes --> READ0 */
594 readcmd = NAND_CMD_READ0;
595 } else {
596 column -= 256;
597 readcmd = NAND_CMD_READ1;
598 }
ace4dfee 599 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 600 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 601 }
ace4dfee 602 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 603
8b6e50c9 604 /* Address cycle, when necessary */
7abd3ef9
TG		 605 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
606 /* Serially input address */
607 if (column != -1) {
608 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 609 if (chip->options & NAND_BUSWIDTH_16 &&
610 !nand_opcode_8bits(command))
7abd3ef9 611 column >>= 1;
ace4dfee 612 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 613 ctrl &= ~NAND_CTRL_CHANGE;
614 }
615 if (page_addr != -1) {
ace4dfee 616 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 617 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 618 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 619 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 620 if (chip->chipsize > (32 << 20))
621 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 622 }
ace4dfee 623 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 624
625 /*
8b6e50c9
BN		 626 * Program and erase have their own busy handlers status and sequential
627 * in needs no delay
e0c7d767 628 */
1da177e4 629 switch (command) {
61b03bd7 630
1da177e4
LT		 631 case NAND_CMD_PAGEPROG:
632 case NAND_CMD_ERASE1:
633 case NAND_CMD_ERASE2:
634 case NAND_CMD_SEQIN:
635 case NAND_CMD_STATUS:
636 return;
637
638 case NAND_CMD_RESET:
ace4dfee 639 if (chip->dev_ready)
1da177e4 640 break;
ace4dfee
TG		 641 udelay(chip->chip_delay);
642 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 643 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 644 chip->cmd_ctrl(mtd,
645 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 646 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
647 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 648 return;
649
e0c7d767 650 /* This applies to read commands */
1da177e4 651 default:
61b03bd7 652 /*
1da177e4
LT		 653 * If we don't have access to the busy pin, we apply the given
654 * command delay
e0c7d767 655 */
ace4dfee
TG		 656 if (!chip->dev_ready) {
657 udelay(chip->chip_delay);
1da177e4 658 return;
61b03bd7 659 }
1da177e4 660 }
8b6e50c9
BN		 661 /*
662 * Apply this short delay always to ensure that we do wait tWB in
663 * any case on any machine.
664 */
e0c7d767 665 ndelay(100);
3b88775c
TG		 666
667 nand_wait_ready(mtd);
1da177e4
LT		 668}
669
670/**
671 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 672 * @mtd: MTD device structure
673 * @command: the command to be sent
674 * @column: the column address for this command, -1 if none
675 * @page_addr: the page address for this command, -1 if none
1da177e4 676 *
7abd3ef9 677 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 678 * devices. We don't have the separate regions as we have in the small page
679 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 680 */
7abd3ef9
TG		 681static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
682 int column, int page_addr)
1da177e4 683{
862eba51 684 register struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4
LT		 685
686 /* Emulate NAND_CMD_READOOB */
687 if (command == NAND_CMD_READOOB) {
28318776 688 column += mtd->writesize;
1da177e4
LT		 689 command = NAND_CMD_READ0;
690 }
61b03bd7 691
7abd3ef9 692 /* Command latch cycle */
fb066ada 693 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 694
695 if (column != -1 || page_addr != -1) {
7abd3ef9 696 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 697
698 /* Serially input address */
699 if (column != -1) {
700 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 701 if (chip->options & NAND_BUSWIDTH_16 &&
702 !nand_opcode_8bits(command))
1da177e4 703 column >>= 1;
ace4dfee 704 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 705 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 706 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 707 }
1da177e4 708 if (page_addr != -1) {
ace4dfee
TG		 709 chip->cmd_ctrl(mtd, page_addr, ctrl);
710 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 711 NAND_NCE | NAND_ALE);
1da177e4 712 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 713 if (chip->chipsize > (128 << 20))
714 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 715 NAND_NCE | NAND_ALE);
1da177e4 716 }
1da177e4 717 }
ace4dfee 718 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 719
720 /*
8b6e50c9 721 * Program and erase have their own busy handlers status, sequential
7a442f17 722 * in and status need no delay.
30f464b7 723 */
1da177e4 724 switch (command) {
61b03bd7 725
1da177e4
LT		 726 case NAND_CMD_CACHEDPROG:
727 case NAND_CMD_PAGEPROG:
728 case NAND_CMD_ERASE1:
729 case NAND_CMD_ERASE2:
730 case NAND_CMD_SEQIN:
7bc3312b 731 case NAND_CMD_RNDIN:
1da177e4 732 case NAND_CMD_STATUS:
30f464b7 733 return;
1da177e4
LT		 734
735 case NAND_CMD_RESET:
ace4dfee 736 if (chip->dev_ready)
1da177e4 737 break;
ace4dfee 738 udelay(chip->chip_delay);
12efdde3
TG		 739 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
740 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
741 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
742 NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 743 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
744 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 745 return;
746
7bc3312b
TG		 747 case NAND_CMD_RNDOUT:
748 /* No ready / busy check necessary */
749 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
750 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
751 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
752 NAND_NCE | NAND_CTRL_CHANGE);
753 return;
754
1da177e4 755 case NAND_CMD_READ0:
12efdde3
TG		 756 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
757 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
758 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
759 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 760
e0c7d767 761 /* This applies to read commands */
1da177e4 762 default:
61b03bd7 763 /*
1da177e4 764 * If we don't have access to the busy pin, we apply the given
8b6e50c9 765 * command delay.
e0c7d767 766 */
ace4dfee
TG		 767 if (!chip->dev_ready) {
768 udelay(chip->chip_delay);
1da177e4 769 return;
61b03bd7 770 }
1da177e4 771 }
3b88775c 772
8b6e50c9
BN		 773 /*
774 * Apply this short delay always to ensure that we do wait tWB in
775 * any case on any machine.
776 */
e0c7d767 777 ndelay(100);
3b88775c
TG		 778
779 nand_wait_ready(mtd);
1da177e4
LT		 780}
781
2af7c653
SK		 782/**
783 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 784 * @chip: the nand chip descriptor
785 * @mtd: MTD device structure
786 * @new_state: the state which is requested
2af7c653
SK		 787 *
788 * Used when in panic, no locks are taken.
789 */
790static void panic_nand_get_device(struct nand_chip *chip,
791 struct mtd_info *mtd, int new_state)
792{
7854d3f7 793 /* Hardware controller shared among independent devices */
2af7c653
SK		 794 chip->controller->active = chip;
795 chip->state = new_state;
796}
797
1da177e4
LT		 798/**
799 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 800 * @mtd: MTD device structure
801 * @new_state: the state which is requested
1da177e4
LT		 802 *
803 * Get the device and lock it for exclusive access
804 */
2c0a2bed 805static int
6a8214aa 806nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 807{
862eba51 808 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee
TG		 809 spinlock_t *lock = &chip->controller->lock;
810 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 811 DECLARE_WAITQUEUE(wait, current);
7351d3a5 812retry:
0dfc6246
TG		 813 spin_lock(lock);
814
b8b3ee9a 815 /* Hardware controller shared among independent devices */
ace4dfee
TG		 816 if (!chip->controller->active)
817 chip->controller->active = chip;
a36ed299 818
ace4dfee
TG		 819 if (chip->controller->active == chip && chip->state == FL_READY) {
820 chip->state = new_state;
0dfc6246 821 spin_unlock(lock);
962034f4
VW		 822 return 0;
823 }
824 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 825 if (chip->controller->active->state == FL_PM_SUSPENDED) {
826 chip->state = FL_PM_SUSPENDED;
827 spin_unlock(lock);
828 return 0;
6b0d9a84 829 }
0dfc6246
TG		 830 }
831 set_current_state(TASK_UNINTERRUPTIBLE);
832 add_wait_queue(wq, &wait);
833 spin_unlock(lock);
834 schedule();
835 remove_wait_queue(wq, &wait);
1da177e4
LT		 836 goto retry;
837}
838
2af7c653 839/**
8b6e50c9
BN		 840 * panic_nand_wait - [GENERIC] wait until the command is done
841 * @mtd: MTD device structure
842 * @chip: NAND chip structure
843 * @timeo: timeout
2af7c653
SK		 844 *
845 * Wait for command done. This is a helper function for nand_wait used when
846 * we are in interrupt context. May happen when in panic and trying to write
b595076a 847 * an oops through mtdoops.
2af7c653
SK		 848 */
849static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
850 unsigned long timeo)
851{
852 int i;
853 for (i = 0; i < timeo; i++) {
854 if (chip->dev_ready) {
855 if (chip->dev_ready(mtd))
856 break;
857 } else {
858 if (chip->read_byte(mtd) & NAND_STATUS_READY)
859 break;
860 }
861 mdelay(1);
f8ac0414 862 }
2af7c653
SK		 863}
864
1da177e4 865/**
8b6e50c9
BN		 866 * nand_wait - [DEFAULT] wait until the command is done
867 * @mtd: MTD device structure
868 * @chip: NAND chip structure
1da177e4 869 *
b70af9be 870 * Wait for command done. This applies to erase and program only.
844d3b42 871 */
7bc3312b 872static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 873{
874
b70af9be
AS		 875 int status;
876 unsigned long timeo = 400;
1da177e4 877
8b6e50c9
BN		 878 /*
879 * Apply this short delay always to ensure that we do wait tWB in any
880 * case on any machine.
881 */
e0c7d767 882 ndelay(100);
1da177e4 883
14c65786 884 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 885
2af7c653
SK		 886 if (in_interrupt() || oops_in_progress)
887 panic_nand_wait(mtd, chip, timeo);
888 else {
6d2559f8 889 timeo = jiffies + msecs_to_jiffies(timeo);
b70af9be 890 do {
2af7c653
SK		 891 if (chip->dev_ready) {
892 if (chip->dev_ready(mtd))
893 break;
894 } else {
895 if (chip->read_byte(mtd) & NAND_STATUS_READY)
896 break;
897 }
898 cond_resched();
b70af9be 899 } while (time_before(jiffies, timeo));
1da177e4 900 }
8fe833c1 901
ace4dfee 902 status = (int)chip->read_byte(mtd);
f251b8df
MC		 903 /* This can happen if in case of timeout or buggy dev_ready */
904 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 905 return status;
906}
907
7d70f334 908/**
b6d676db 909 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 910 * @mtd: mtd info
911 * @ofs: offset to start unlock from
912 * @len: length to unlock
8b6e50c9
BN		 913 * @invert: when = 0, unlock the range of blocks within the lower and
914 * upper boundary address
915 * when = 1, unlock the range of blocks outside the boundaries
916 * of the lower and upper boundary address
7d70f334 917 *
8b6e50c9 918 * Returs unlock status.
7d70f334
VS		 919 */
920static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
921 uint64_t len, int invert)
922{
923 int ret = 0;
924 int status, page;
862eba51 925 struct nand_chip *chip = mtd_to_nand(mtd);
7d70f334
VS		 926
927 /* Submit address of first page to unlock */
928 page = ofs >> chip->page_shift;
929 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
930
931 /* Submit address of last page to unlock */
932 page = (ofs + len) >> chip->page_shift;
933 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
934 (page | invert) & chip->pagemask);
935
936 /* Call wait ready function */
937 status = chip->waitfunc(mtd, chip);
7d70f334 938 /* See if device thinks it succeeded */
74830966 939 if (status & NAND_STATUS_FAIL) {
289c0522 940 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 941 __func__, status);
942 ret = -EIO;
943 }
944
945 return ret;
946}
947
948/**
b6d676db 949 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 950 * @mtd: mtd info
951 * @ofs: offset to start unlock from
952 * @len: length to unlock
7d70f334 953 *
8b6e50c9 954 * Returns unlock status.
7d70f334
VS		 955 */
956int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
957{
958 int ret = 0;
959 int chipnr;
862eba51 960 struct nand_chip *chip = mtd_to_nand(mtd);
7d70f334 961
289c0522 962 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 963 __func__, (unsigned long long)ofs, len);
964
965 if (check_offs_len(mtd, ofs, len))
b1a2348a 966 return -EINVAL;
7d70f334
VS		 967
968 /* Align to last block address if size addresses end of the device */
969 if (ofs + len == mtd->size)
970 len -= mtd->erasesize;
971
6a8214aa 972 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 973
974 /* Shift to get chip number */
975 chipnr = ofs >> chip->chip_shift;
976
977 chip->select_chip(mtd, chipnr);
978
57d3a9a8
WD		 979 /*
980 * Reset the chip.
981 * If we want to check the WP through READ STATUS and check the bit 7
982 * we must reset the chip
983 * some operation can also clear the bit 7 of status register
984 * eg. erase/program a locked block
985 */
986 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
987
7d70f334
VS		 988 /* Check, if it is write protected */
989 if (nand_check_wp(mtd)) {
289c0522 990 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 991 __func__);
992 ret = -EIO;
993 goto out;
994 }
995
996 ret = __nand_unlock(mtd, ofs, len, 0);
997
998out:
b0bb6903 999 chip->select_chip(mtd, -1);
7d70f334
VS		 1000 nand_release_device(mtd);
1001
1002 return ret;
1003}
7351d3a5 1004EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 1005
1006/**
b6d676db 1007 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 1008 * @mtd: mtd info
1009 * @ofs: offset to start unlock from
1010 * @len: length to unlock
7d70f334 1011 *
8b6e50c9
BN		 1012 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1013 * have this feature, but it allows only to lock all blocks, not for specified
1014 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1015 * now.
7d70f334 1016 *
8b6e50c9 1017 * Returns lock status.
7d70f334
VS		 1018 */
1019int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1020{
1021 int ret = 0;
1022 int chipnr, status, page;
862eba51 1023 struct nand_chip *chip = mtd_to_nand(mtd);
7d70f334 1024
289c0522 1025 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1026 __func__, (unsigned long long)ofs, len);
1027
1028 if (check_offs_len(mtd, ofs, len))
b1a2348a 1029 return -EINVAL;
7d70f334 1030
6a8214aa 1031 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 1032
1033 /* Shift to get chip number */
1034 chipnr = ofs >> chip->chip_shift;
1035
1036 chip->select_chip(mtd, chipnr);
1037
57d3a9a8
WD		 1038 /*
1039 * Reset the chip.
1040 * If we want to check the WP through READ STATUS and check the bit 7
1041 * we must reset the chip
1042 * some operation can also clear the bit 7 of status register
1043 * eg. erase/program a locked block
1044 */
1045 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1046
7d70f334
VS		 1047 /* Check, if it is write protected */
1048 if (nand_check_wp(mtd)) {
289c0522 1049 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1050 __func__);
1051 status = MTD_ERASE_FAILED;
1052 ret = -EIO;
1053 goto out;
1054 }
1055
1056 /* Submit address of first page to lock */
1057 page = ofs >> chip->page_shift;
1058 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1059
1060 /* Call wait ready function */
1061 status = chip->waitfunc(mtd, chip);
7d70f334 1062 /* See if device thinks it succeeded */
74830966 1063 if (status & NAND_STATUS_FAIL) {
289c0522 1064 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1065 __func__, status);
1066 ret = -EIO;
1067 goto out;
1068 }
1069
1070 ret = __nand_unlock(mtd, ofs, len, 0x1);
1071
1072out:
b0bb6903 1073 chip->select_chip(mtd, -1);
7d70f334
VS		 1074 nand_release_device(mtd);
1075
1076 return ret;
1077}
7351d3a5 1078EXPORT_SYMBOL(nand_lock);
7d70f334 1079
730a43fb
BB		 1080/**
1081 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1082 * @buf: buffer to test
1083 * @len: buffer length
1084 * @bitflips_threshold: maximum number of bitflips
1085 *
1086 * Check if a buffer contains only 0xff, which means the underlying region
1087 * has been erased and is ready to be programmed.
1088 * The bitflips_threshold specify the maximum number of bitflips before
1089 * considering the region is not erased.
1090 * Note: The logic of this function has been extracted from the memweight
1091 * implementation, except that nand_check_erased_buf function exit before
1092 * testing the whole buffer if the number of bitflips exceed the
1093 * bitflips_threshold value.
1094 *
1095 * Returns a positive number of bitflips less than or equal to
1096 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1097 * threshold.
1098 */
1099static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1100{
1101 const unsigned char *bitmap = buf;
1102 int bitflips = 0;
1103 int weight;
1104
1105 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1106 len--, bitmap++) {
1107 weight = hweight8(*bitmap);
1108 bitflips += BITS_PER_BYTE - weight;
1109 if (unlikely(bitflips > bitflips_threshold))
1110 return -EBADMSG;
1111 }
1112
1113 for (; len >= sizeof(long);
1114 len -= sizeof(long), bitmap += sizeof(long)) {
1115 weight = hweight_long(*((unsigned long *)bitmap));
1116 bitflips += BITS_PER_LONG - weight;
1117 if (unlikely(bitflips > bitflips_threshold))
1118 return -EBADMSG;
1119 }
1120
1121 for (; len > 0; len--, bitmap++) {
1122 weight = hweight8(*bitmap);
1123 bitflips += BITS_PER_BYTE - weight;
1124 if (unlikely(bitflips > bitflips_threshold))
1125 return -EBADMSG;
1126 }
1127
1128 return bitflips;
1129}
1130
1131/**
1132 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1133 * 0xff data
1134 * @data: data buffer to test
1135 * @datalen: data length
1136 * @ecc: ECC buffer
1137 * @ecclen: ECC length
1138 * @extraoob: extra OOB buffer
1139 * @extraooblen: extra OOB length
1140 * @bitflips_threshold: maximum number of bitflips
1141 *
1142 * Check if a data buffer and its associated ECC and OOB data contains only
1143 * 0xff pattern, which means the underlying region has been erased and is
1144 * ready to be programmed.
1145 * The bitflips_threshold specify the maximum number of bitflips before
1146 * considering the region as not erased.
1147 *
1148 * Note:
1149 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1150 * different from the NAND page size. When fixing bitflips, ECC engines will
1151 * report the number of errors per chunk, and the NAND core infrastructure
1152 * expect you to return the maximum number of bitflips for the whole page.
1153 * This is why you should always use this function on a single chunk and
1154 * not on the whole page. After checking each chunk you should update your
1155 * max_bitflips value accordingly.
1156 * 2/ When checking for bitflips in erased pages you should not only check
1157 * the payload data but also their associated ECC data, because a user might
1158 * have programmed almost all bits to 1 but a few. In this case, we
1159 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1160 * this case.
1161 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1162 * data are protected by the ECC engine.
1163 * It could also be used if you support subpages and want to attach some
1164 * extra OOB data to an ECC chunk.
1165 *
1166 * Returns a positive number of bitflips less than or equal to
1167 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1168 * threshold. In case of success, the passed buffers are filled with 0xff.
1169 */
1170int nand_check_erased_ecc_chunk(void *data, int datalen,
1171 void *ecc, int ecclen,
1172 void *extraoob, int extraooblen,
1173 int bitflips_threshold)
1174{
1175 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1176
1177 data_bitflips = nand_check_erased_buf(data, datalen,
1178 bitflips_threshold);
1179 if (data_bitflips < 0)
1180 return data_bitflips;
1181
1182 bitflips_threshold -= data_bitflips;
1183
1184 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1185 if (ecc_bitflips < 0)
1186 return ecc_bitflips;
1187
1188 bitflips_threshold -= ecc_bitflips;
1189
1190 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1191 bitflips_threshold);
1192 if (extraoob_bitflips < 0)
1193 return extraoob_bitflips;
1194
1195 if (data_bitflips)
1196 memset(data, 0xff, datalen);
1197
1198 if (ecc_bitflips)
1199 memset(ecc, 0xff, ecclen);
1200
1201 if (extraoob_bitflips)
1202 memset(extraoob, 0xff, extraooblen);
1203
1204 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1205}
1206EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1207
8593fbc6 1208/**
7854d3f7 1209 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1210 * @mtd: mtd info structure
1211 * @chip: nand chip info structure
1212 * @buf: buffer to store read data
1fbb938d 1213 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1214 * @page: page number to read
52ff49df 1215 *
7854d3f7 1216 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1217 */
1218static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1219 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1220{
1221 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1222 if (oob_required)
1223 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1224 return 0;
1225}
1226
52ff49df 1227/**
7854d3f7 1228 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1229 * @mtd: mtd info structure
1230 * @chip: nand chip info structure
1231 * @buf: buffer to store read data
1fbb938d 1232 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1233 * @page: page number to read
52ff49df
DB		 1234 *
1235 * We need a special oob layout and handling even when OOB isn't used.
1236 */
7351d3a5 1237static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1238 struct nand_chip *chip, uint8_t *buf,
1239 int oob_required, int page)
52ff49df
DB		 1240{
1241 int eccsize = chip->ecc.size;
1242 int eccbytes = chip->ecc.bytes;
1243 uint8_t *oob = chip->oob_poi;
1244 int steps, size;
1245
1246 for (steps = chip->ecc.steps; steps > 0; steps--) {
1247 chip->read_buf(mtd, buf, eccsize);
1248 buf += eccsize;
1249
1250 if (chip->ecc.prepad) {
1251 chip->read_buf(mtd, oob, chip->ecc.prepad);
1252 oob += chip->ecc.prepad;
1253 }
1254
1255 chip->read_buf(mtd, oob, eccbytes);
1256 oob += eccbytes;
1257
1258 if (chip->ecc.postpad) {
1259 chip->read_buf(mtd, oob, chip->ecc.postpad);
1260 oob += chip->ecc.postpad;
1261 }
1262 }
1263
1264 size = mtd->oobsize - (oob - chip->oob_poi);
1265 if (size)
1266 chip->read_buf(mtd, oob, size);
1267
1268 return 0;
1269}
1270
1da177e4 1271/**
7854d3f7 1272 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1273 * @mtd: mtd info structure
1274 * @chip: nand chip info structure
1275 * @buf: buffer to store read data
1fbb938d 1276 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1277 * @page: page number to read
068e3c0a 1278 */
f5bbdacc 1279static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1280 uint8_t *buf, int oob_required, int page)
1da177e4 1281{
f5bbdacc
TG		 1282 int i, eccsize = chip->ecc.size;
1283 int eccbytes = chip->ecc.bytes;
1284 int eccsteps = chip->ecc.steps;
1285 uint8_t *p = buf;
4bf63fcb
DW		 1286 uint8_t *ecc_calc = chip->buffers->ecccalc;
1287 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1288 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1289 unsigned int max_bitflips = 0;
f5bbdacc 1290
1fbb938d 1291 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1292
1293 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1294 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1295
1296 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1297 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1298
1299 eccsteps = chip->ecc.steps;
1300 p = buf;
1301
1302 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1303 int stat;
1304
1305 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1306 if (stat < 0) {
f5bbdacc 1307 mtd->ecc_stats.failed++;
3f91e94f 1308 } else {
f5bbdacc 1309 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1310 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1311 }
f5bbdacc 1312 }
3f91e94f 1313 return max_bitflips;
22c60f5f 1314}
1da177e4 1315
3d459559 1316/**
837a6ba4 1317 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1318 * @mtd: mtd info structure
1319 * @chip: nand chip info structure
1320 * @data_offs: offset of requested data within the page
1321 * @readlen: data length
1322 * @bufpoi: buffer to store read data
e004debd 1323 * @page: page number to read
3d459559 1324 */
7351d3a5 1325static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
e004debd
HS		 1326 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1327 int page)
3d459559
AK		 1328{
1329 int start_step, end_step, num_steps;
1330 uint32_t *eccpos = chip->ecc.layout->eccpos;
1331 uint8_t *p;
1332 int data_col_addr, i, gaps = 0;
1333 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1334 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
4a4163ca 1335 int index;
3f91e94f 1336 unsigned int max_bitflips = 0;
3d459559 1337
7854d3f7 1338 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1339 start_step = data_offs / chip->ecc.size;
1340 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1341 num_steps = end_step - start_step + 1;
4a4163ca 1342 index = start_step * chip->ecc.bytes;
3d459559 1343
8b6e50c9 1344 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1345 datafrag_len = num_steps * chip->ecc.size;
1346 eccfrag_len = num_steps * chip->ecc.bytes;
1347
1348 data_col_addr = start_step * chip->ecc.size;
1349 /* If we read not a page aligned data */
1350 if (data_col_addr != 0)
1351 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1352
1353 p = bufpoi + data_col_addr;
1354 chip->read_buf(mtd, p, datafrag_len);
1355
8b6e50c9 1356 /* Calculate ECC */
3d459559
AK		 1357 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1358 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1359
8b6e50c9
BN		 1360 /*
1361 * The performance is faster if we position offsets according to
7854d3f7 1362 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1363 */
3d459559 1364 for (i = 0; i < eccfrag_len - 1; i++) {
47570bb1 1365 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
3d459559
AK		 1366 gaps = 1;
1367 break;
1368 }
1369 }
1370 if (gaps) {
1371 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1372 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1373 } else {
8b6e50c9 1374 /*
7854d3f7 1375 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1376 * about buswidth alignment in read_buf.
1377 */
7351d3a5 1378 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1379 aligned_len = eccfrag_len;
7351d3a5 1380 if (eccpos[index] & (busw - 1))
3d459559 1381 aligned_len++;
7351d3a5 1382 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1383 aligned_len++;
1384
7351d3a5
FF		 1385 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1386 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1387 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1388 }
1389
1390 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1391 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1392
1393 p = bufpoi + data_col_addr;
1394 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1395 int stat;
1396
7351d3a5
FF		 1397 stat = chip->ecc.correct(mtd, p,
1398 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
40cbe6ee
BB		 1399 if (stat == -EBADMSG &&
1400 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1401 /* check for empty pages with bitflips */
1402 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1403 &chip->buffers->ecccode[i],
1404 chip->ecc.bytes,
1405 NULL, 0,
1406 chip->ecc.strength);
1407 }
1408
3f91e94f 1409 if (stat < 0) {
3d459559 1410 mtd->ecc_stats.failed++;
3f91e94f 1411 } else {
3d459559 1412 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1413 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1414 }
3d459559 1415 }
3f91e94f 1416 return max_bitflips;
3d459559
AK		 1417}
1418
068e3c0a 1419/**
7854d3f7 1420 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1421 * @mtd: mtd info structure
1422 * @chip: nand chip info structure
1423 * @buf: buffer to store read data
1fbb938d 1424 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1425 * @page: page number to read
068e3c0a 1426 *
7854d3f7 1427 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1428 */
f5bbdacc 1429static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1430 uint8_t *buf, int oob_required, int page)
1da177e4 1431{
f5bbdacc
TG		 1432 int i, eccsize = chip->ecc.size;
1433 int eccbytes = chip->ecc.bytes;
1434 int eccsteps = chip->ecc.steps;
1435 uint8_t *p = buf;
4bf63fcb
DW		 1436 uint8_t *ecc_calc = chip->buffers->ecccalc;
1437 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1438 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1439 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1440
1441 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1442 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1443 chip->read_buf(mtd, p, eccsize);
1444 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1445 }
f75e5097 1446 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1447
f5bbdacc 1448 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1449 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1450
f5bbdacc
TG		 1451 eccsteps = chip->ecc.steps;
1452 p = buf;
61b03bd7 1453
f5bbdacc
TG		 1454 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1455 int stat;
1da177e4 1456
f5bbdacc 1457 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
40cbe6ee
BB		 1458 if (stat == -EBADMSG &&
1459 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1460 /* check for empty pages with bitflips */
1461 stat = nand_check_erased_ecc_chunk(p, eccsize,
1462 &ecc_code[i], eccbytes,
1463 NULL, 0,
1464 chip->ecc.strength);
1465 }
1466
3f91e94f 1467 if (stat < 0) {
f5bbdacc 1468 mtd->ecc_stats.failed++;
3f91e94f 1469 } else {
f5bbdacc 1470 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1471 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1472 }
f5bbdacc 1473 }
3f91e94f 1474 return max_bitflips;
f5bbdacc 1475}
1da177e4 1476
6e0cb135 1477/**
7854d3f7 1478 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1479 * @mtd: mtd info structure
1480 * @chip: nand chip info structure
1481 * @buf: buffer to store read data
1fbb938d 1482 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1483 * @page: page number to read
6e0cb135 1484 *
8b6e50c9
BN		 1485 * Hardware ECC for large page chips, require OOB to be read first. For this
1486 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1487 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1488 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1489 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1490 */
1491static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1492 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1493{
1494 int i, eccsize = chip->ecc.size;
1495 int eccbytes = chip->ecc.bytes;
1496 int eccsteps = chip->ecc.steps;
1497 uint8_t *p = buf;
1498 uint8_t *ecc_code = chip->buffers->ecccode;
1499 uint32_t *eccpos = chip->ecc.layout->eccpos;
1500 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1501 unsigned int max_bitflips = 0;
6e0cb135
SN		 1502
1503 /* Read the OOB area first */
1504 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1505 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1506 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1507
1508 for (i = 0; i < chip->ecc.total; i++)
1509 ecc_code[i] = chip->oob_poi[eccpos[i]];
1510
1511 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1512 int stat;
1513
1514 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1515 chip->read_buf(mtd, p, eccsize);
1516 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1517
1518 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
40cbe6ee
BB		 1519 if (stat == -EBADMSG &&
1520 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1521 /* check for empty pages with bitflips */
1522 stat = nand_check_erased_ecc_chunk(p, eccsize,
1523 &ecc_code[i], eccbytes,
1524 NULL, 0,
1525 chip->ecc.strength);
1526 }
1527
3f91e94f 1528 if (stat < 0) {
6e0cb135 1529 mtd->ecc_stats.failed++;
3f91e94f 1530 } else {
6e0cb135 1531 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1532 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1533 }
6e0cb135 1534 }
3f91e94f 1535 return max_bitflips;
6e0cb135
SN		 1536}
1537
f5bbdacc 1538/**
7854d3f7 1539 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1540 * @mtd: mtd info structure
1541 * @chip: nand chip info structure
1542 * @buf: buffer to store read data
1fbb938d 1543 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1544 * @page: page number to read
f5bbdacc 1545 *
8b6e50c9
BN		 1546 * The hw generator calculates the error syndrome automatically. Therefore we
1547 * need a special oob layout and handling.
f5bbdacc
TG		 1548 */
1549static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1550 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1551{
1552 int i, eccsize = chip->ecc.size;
1553 int eccbytes = chip->ecc.bytes;
1554 int eccsteps = chip->ecc.steps;
40cbe6ee 1555 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
f5bbdacc 1556 uint8_t *p = buf;
f75e5097 1557 uint8_t *oob = chip->oob_poi;
3f91e94f 1558 unsigned int max_bitflips = 0;
1da177e4 1559
f5bbdacc
TG		 1560 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1561 int stat;
61b03bd7 1562
f5bbdacc
TG		 1563 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1564 chip->read_buf(mtd, p, eccsize);
1da177e4 1565
f5bbdacc
TG		 1566 if (chip->ecc.prepad) {
1567 chip->read_buf(mtd, oob, chip->ecc.prepad);
1568 oob += chip->ecc.prepad;
1569 }
1da177e4 1570
f5bbdacc
TG		 1571 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1572 chip->read_buf(mtd, oob, eccbytes);
1573 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1574
f5bbdacc 1575 oob += eccbytes;
1da177e4 1576
f5bbdacc
TG		 1577 if (chip->ecc.postpad) {
1578 chip->read_buf(mtd, oob, chip->ecc.postpad);
1579 oob += chip->ecc.postpad;
61b03bd7 1580 }
40cbe6ee
BB		 1581
1582 if (stat == -EBADMSG &&
1583 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1584 /* check for empty pages with bitflips */
1585 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1586 oob - eccpadbytes,
1587 eccpadbytes,
1588 NULL, 0,
1589 chip->ecc.strength);
1590 }
1591
1592 if (stat < 0) {
1593 mtd->ecc_stats.failed++;
1594 } else {
1595 mtd->ecc_stats.corrected += stat;
1596 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1597 }
f5bbdacc 1598 }
1da177e4 1599
f5bbdacc 1600 /* Calculate remaining oob bytes */
7e4178f9 1601 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1602 if (i)
1603 chip->read_buf(mtd, oob, i);
61b03bd7 1604
3f91e94f 1605 return max_bitflips;
f5bbdacc 1606}
1da177e4 1607
f5bbdacc 1608/**
7854d3f7 1609 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1610 * @chip: nand chip structure
1611 * @oob: oob destination address
1612 * @ops: oob ops structure
1613 * @len: size of oob to transfer
8593fbc6
TG		 1614 */
1615static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1616 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1617{
f8ac0414 1618 switch (ops->mode) {
8593fbc6 1619
0612b9dd
BN		 1620 case MTD_OPS_PLACE_OOB:
1621 case MTD_OPS_RAW:
8593fbc6
TG		 1622 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1623 return oob + len;
1624
0612b9dd 1625 case MTD_OPS_AUTO_OOB: {
8593fbc6 1626 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1627 uint32_t boffs = 0, roffs = ops->ooboffs;
1628 size_t bytes = 0;
8593fbc6 1629
f8ac0414 1630 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1631 /* Read request not from offset 0? */
7bc3312b
TG		 1632 if (unlikely(roffs)) {
1633 if (roffs >= free->length) {
1634 roffs -= free->length;
1635 continue;
1636 }
1637 boffs = free->offset + roffs;
1638 bytes = min_t(size_t, len,
1639 (free->length - roffs));
1640 roffs = 0;
1641 } else {
1642 bytes = min_t(size_t, len, free->length);
1643 boffs = free->offset;
1644 }
1645 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1646 oob += bytes;
1647 }
1648 return oob;
1649 }
1650 default:
1651 BUG();
1652 }
1653 return NULL;
1654}
1655
ba84fb59
BN		 1656/**
1657 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1658 * @mtd: MTD device structure
1659 * @retry_mode: the retry mode to use
1660 *
1661 * Some vendors supply a special command to shift the Vt threshold, to be used
1662 * when there are too many bitflips in a page (i.e., ECC error). After setting
1663 * a new threshold, the host should retry reading the page.
1664 */
1665static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1666{
862eba51 1667 struct nand_chip *chip = mtd_to_nand(mtd);
ba84fb59
BN		 1668
1669 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1670
1671 if (retry_mode >= chip->read_retries)
1672 return -EINVAL;
1673
1674 if (!chip->setup_read_retry)
1675 return -EOPNOTSUPP;
1676
1677 return chip->setup_read_retry(mtd, retry_mode);
1678}
1679
8593fbc6 1680/**
7854d3f7 1681 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1682 * @mtd: MTD device structure
1683 * @from: offset to read from
1684 * @ops: oob ops structure
f5bbdacc
TG		 1685 *
1686 * Internal function. Called with chip held.
1687 */
8593fbc6
TG		 1688static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1689 struct mtd_oob_ops *ops)
f5bbdacc 1690{
e47f3db4 1691 int chipnr, page, realpage, col, bytes, aligned, oob_required;
862eba51 1692 struct nand_chip *chip = mtd_to_nand(mtd);
f5bbdacc 1693 int ret = 0;
8593fbc6 1694 uint32_t readlen = ops->len;
7014568b 1695 uint32_t oobreadlen = ops->ooblen;
29f1058a 1696 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
9aca334e 1697
8593fbc6 1698 uint8_t *bufpoi, *oob, *buf;
66507c7b 1699 int use_bufpoi;
edbc4540 1700 unsigned int max_bitflips = 0;
ba84fb59 1701 int retry_mode = 0;
b72f3dfb 1702 bool ecc_fail = false;
1da177e4 1703
f5bbdacc
TG		 1704 chipnr = (int)(from >> chip->chip_shift);
1705 chip->select_chip(mtd, chipnr);
61b03bd7 1706
f5bbdacc
TG		 1707 realpage = (int)(from >> chip->page_shift);
1708 page = realpage & chip->pagemask;
1da177e4 1709
f5bbdacc 1710 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1711
8593fbc6
TG		 1712 buf = ops->datbuf;
1713 oob = ops->oobbuf;
e47f3db4 1714 oob_required = oob ? 1 : 0;
8593fbc6 1715
f8ac0414 1716 while (1) {
b72f3dfb
BN		 1717 unsigned int ecc_failures = mtd->ecc_stats.failed;
1718
f5bbdacc
TG		 1719 bytes = min(mtd->writesize - col, readlen);
1720 aligned = (bytes == mtd->writesize);
61b03bd7 1721
66507c7b
KD		 1722 if (!aligned)
1723 use_bufpoi = 1;
1724 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1725 use_bufpoi = !virt_addr_valid(buf);
1726 else
1727 use_bufpoi = 0;
1728
8b6e50c9 1729 /* Is the current page in the buffer? */
8593fbc6 1730 if (realpage != chip->pagebuf || oob) {
66507c7b
KD		 1731 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1732
1733 if (use_bufpoi && aligned)
1734 pr_debug("%s: using read bounce buffer for buf@%p\n",
1735 __func__, buf);
61b03bd7 1736
ba84fb59 1737read_retry:
c00a0991 1738 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1739
edbc4540
MD		 1740 /*
1741 * Now read the page into the buffer. Absent an error,
1742 * the read methods return max bitflips per ecc step.
1743 */
0612b9dd 1744 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1745 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1746 oob_required,
1747 page);
a5ff4f10
JW		 1748 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1749 !oob)
7351d3a5 1750 ret = chip->ecc.read_subpage(mtd, chip,
e004debd
HS		 1751 col, bytes, bufpoi,
1752 page);
956e944c 1753 else
46a8cf2d 1754 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1755 oob_required, page);
6d77b9d0 1756 if (ret < 0) {
66507c7b 1757 if (use_bufpoi)
6d77b9d0
BN		 1758 /* Invalidate page cache */
1759 chip->pagebuf = -1;
1da177e4 1760 break;
6d77b9d0 1761 }
f5bbdacc 1762
edbc4540
MD		 1763 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1764
f5bbdacc 1765 /* Transfer not aligned data */
66507c7b 1766 if (use_bufpoi) {
a5ff4f10 1767 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
b72f3dfb 1768 !(mtd->ecc_stats.failed - ecc_failures) &&
edbc4540 1769 (ops->mode != MTD_OPS_RAW)) {
3d459559 1770 chip->pagebuf = realpage;
edbc4540
MD		 1771 chip->pagebuf_bitflips = ret;
1772 } else {
6d77b9d0
BN		 1773 /* Invalidate page cache */
1774 chip->pagebuf = -1;
edbc4540 1775 }
4bf63fcb 1776 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1777 }
1778
8593fbc6 1779 if (unlikely(oob)) {
b64d39d8
ML		 1780 int toread = min(oobreadlen, max_oobsize);
1781
1782 if (toread) {
1783 oob = nand_transfer_oob(chip,
1784 oob, ops, toread);
1785 oobreadlen -= toread;
1786 }
8593fbc6 1787 }
5bc7c33c
BN		 1788
1789 if (chip->options & NAND_NEED_READRDY) {
1790 /* Apply delay or wait for ready/busy pin */
1791 if (!chip->dev_ready)
1792 udelay(chip->chip_delay);
1793 else
1794 nand_wait_ready(mtd);
1795 }
b72f3dfb 1796
ba84fb59 1797 if (mtd->ecc_stats.failed - ecc_failures) {
28fa65e6 1798 if (retry_mode + 1 < chip->read_retries) {
ba84fb59
BN		 1799 retry_mode++;
1800 ret = nand_setup_read_retry(mtd,
1801 retry_mode);
1802 if (ret < 0)
1803 break;
1804
1805 /* Reset failures; retry */
1806 mtd->ecc_stats.failed = ecc_failures;
1807 goto read_retry;
1808 } else {
1809 /* No more retry modes; real failure */
1810 ecc_fail = true;
1811 }
1812 }
1813
1814 buf += bytes;
8593fbc6 1815 } else {
4bf63fcb 1816 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1817 buf += bytes;
edbc4540
MD		 1818 max_bitflips = max_t(unsigned int, max_bitflips,
1819 chip->pagebuf_bitflips);
8593fbc6 1820 }
1da177e4 1821
f5bbdacc 1822 readlen -= bytes;
61b03bd7 1823
ba84fb59
BN		 1824 /* Reset to retry mode 0 */
1825 if (retry_mode) {
1826 ret = nand_setup_read_retry(mtd, 0);
1827 if (ret < 0)
1828 break;
1829 retry_mode = 0;
1830 }
1831
f5bbdacc 1832 if (!readlen)
61b03bd7 1833 break;
1da177e4 1834
8b6e50c9 1835 /* For subsequent reads align to page boundary */
1da177e4
LT		 1836 col = 0;
1837 /* Increment page address */
1838 realpage++;
1839
ace4dfee 1840 page = realpage & chip->pagemask;
1da177e4
LT		 1841 /* Check, if we cross a chip boundary */
1842 if (!page) {
1843 chipnr++;
ace4dfee
TG		 1844 chip->select_chip(mtd, -1);
1845 chip->select_chip(mtd, chipnr);
1da177e4 1846 }
1da177e4 1847 }
b0bb6903 1848 chip->select_chip(mtd, -1);
1da177e4 1849
8593fbc6 1850 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1851 if (oob)
1852 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1853
3f91e94f 1854 if (ret < 0)
f5bbdacc
TG		 1855 return ret;
1856
b72f3dfb 1857 if (ecc_fail)
9a1fcdfd
TG		 1858 return -EBADMSG;
1859
edbc4540 1860 return max_bitflips;
f5bbdacc
TG		 1861}
1862
1863/**
25985edc 1864 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1865 * @mtd: MTD device structure
1866 * @from: offset to read from
1867 * @len: number of bytes to read
1868 * @retlen: pointer to variable to store the number of read bytes
1869 * @buf: the databuffer to put data
f5bbdacc 1870 *
8b6e50c9 1871 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1872 */
1873static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1874 size_t *retlen, uint8_t *buf)
1875{
4a89ff88 1876 struct mtd_oob_ops ops;
f5bbdacc
TG		 1877 int ret;
1878
6a8214aa 1879 nand_get_device(mtd, FL_READING);
0ec56dc4 1880 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 1881 ops.len = len;
1882 ops.datbuf = buf;
11041ae6 1883 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1884 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1885 *retlen = ops.retlen;
f5bbdacc 1886 nand_release_device(mtd);
f5bbdacc 1887 return ret;
1da177e4
LT		 1888}
1889
7bc3312b 1890/**
7854d3f7 1891 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1892 * @mtd: mtd info structure
1893 * @chip: nand chip info structure
1894 * @page: page number to read
7bc3312b 1895 */
9d02fc2a 1896int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
7bc3312b 1897{
5c2ffb11 1898 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1899 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1900 return 0;
7bc3312b 1901}
9d02fc2a 1902EXPORT_SYMBOL(nand_read_oob_std);
7bc3312b
TG		 1903
1904/**
7854d3f7 1905 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1906 * with syndromes
8b6e50c9
BN		 1907 * @mtd: mtd info structure
1908 * @chip: nand chip info structure
1909 * @page: page number to read
7bc3312b 1910 */
9d02fc2a
BB		 1911int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1912 int page)
7bc3312b 1913{
7bc3312b
TG		 1914 int length = mtd->oobsize;
1915 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1916 int eccsize = chip->ecc.size;
2ea69d21 1917 uint8_t *bufpoi = chip->oob_poi;
7bc3312b
TG		 1918 int i, toread, sndrnd = 0, pos;
1919
1920 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1921 for (i = 0; i < chip->ecc.steps; i++) {
1922 if (sndrnd) {
1923 pos = eccsize + i * (eccsize + chunk);
1924 if (mtd->writesize > 512)
1925 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1926 else
1927 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1928 } else
1929 sndrnd = 1;
1930 toread = min_t(int, length, chunk);
1931 chip->read_buf(mtd, bufpoi, toread);
1932 bufpoi += toread;
1933 length -= toread;
1934 }
1935 if (length > 0)
1936 chip->read_buf(mtd, bufpoi, length);
1937
5c2ffb11 1938 return 0;
7bc3312b 1939}
9d02fc2a 1940EXPORT_SYMBOL(nand_read_oob_syndrome);
7bc3312b
TG		 1941
1942/**
7854d3f7 1943 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1944 * @mtd: mtd info structure
1945 * @chip: nand chip info structure
1946 * @page: page number to write
7bc3312b 1947 */
9d02fc2a 1948int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
7bc3312b
TG		 1949{
1950 int status = 0;
1951 const uint8_t *buf = chip->oob_poi;
1952 int length = mtd->oobsize;
1953
1954 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1955 chip->write_buf(mtd, buf, length);
1956 /* Send command to program the OOB data */
1957 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1958
1959 status = chip->waitfunc(mtd, chip);
1960
0d420f9d 1961 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b 1962}
9d02fc2a 1963EXPORT_SYMBOL(nand_write_oob_std);
7bc3312b
TG		 1964
1965/**
7854d3f7 1966 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1967 * with syndrome - only for large page flash
1968 * @mtd: mtd info structure
1969 * @chip: nand chip info structure
1970 * @page: page number to write
7bc3312b 1971 */
9d02fc2a
BB		 1972int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1973 int page)
7bc3312b
TG		 1974{
1975 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1976 int eccsize = chip->ecc.size, length = mtd->oobsize;
1977 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1978 const uint8_t *bufpoi = chip->oob_poi;
1979
1980 /*
1981 * data-ecc-data-ecc ... ecc-oob
1982 * or
1983 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1984 */
1985 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1986 pos = steps * (eccsize + chunk);
1987 steps = 0;
1988 } else
8b0036ee 1989 pos = eccsize;
7bc3312b
TG		 1990
1991 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1992 for (i = 0; i < steps; i++) {
1993 if (sndcmd) {
1994 if (mtd->writesize <= 512) {
1995 uint32_t fill = 0xFFFFFFFF;
1996
1997 len = eccsize;
1998 while (len > 0) {
1999 int num = min_t(int, len, 4);
2000 chip->write_buf(mtd, (uint8_t *)&fill,
2001 num);
2002 len -= num;
2003 }
2004 } else {
2005 pos = eccsize + i * (eccsize + chunk);
2006 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2007 }
2008 } else
2009 sndcmd = 1;
2010 len = min_t(int, length, chunk);
2011 chip->write_buf(mtd, bufpoi, len);
2012 bufpoi += len;
2013 length -= len;
2014 }
2015 if (length > 0)
2016 chip->write_buf(mtd, bufpoi, length);
2017
2018 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2019 status = chip->waitfunc(mtd, chip);
2020
2021 return status & NAND_STATUS_FAIL ? -EIO : 0;
2022}
9d02fc2a 2023EXPORT_SYMBOL(nand_write_oob_syndrome);
7bc3312b 2024
1da177e4 2025/**
7854d3f7 2026 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 2027 * @mtd: MTD device structure
2028 * @from: offset to read from
2029 * @ops: oob operations description structure
1da177e4 2030 *
8b6e50c9 2031 * NAND read out-of-band data from the spare area.
1da177e4 2032 */
8593fbc6
TG		 2033static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2034 struct mtd_oob_ops *ops)
1da177e4 2035{
c00a0991 2036 int page, realpage, chipnr;
862eba51 2037 struct nand_chip *chip = mtd_to_nand(mtd);
041e4575 2038 struct mtd_ecc_stats stats;
7014568b
VW		 2039 int readlen = ops->ooblen;
2040 int len;
7bc3312b 2041 uint8_t *buf = ops->oobbuf;
1951f2f7 2042 int ret = 0;
61b03bd7 2043
289c0522 2044 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 2045 __func__, (unsigned long long)from, readlen);
1da177e4 2046
041e4575
BN		 2047 stats = mtd->ecc_stats;
2048
29f1058a 2049 len = mtd_oobavail(mtd, ops);
03736155
AH		 2050
2051 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2052 pr_debug("%s: attempt to start read outside oob\n",
2053 __func__);
03736155
AH		 2054 return -EINVAL;
2055 }
2056
2057 /* Do not allow reads past end of device */
2058 if (unlikely(from >= mtd->size ||
2059 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2060 (from >> chip->page_shift)) * len)) {
289c0522
BN		 2061 pr_debug("%s: attempt to read beyond end of device\n",
2062 __func__);
03736155
AH		 2063 return -EINVAL;
2064 }
7014568b 2065
7314e9e7 2066 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 2067 chip->select_chip(mtd, chipnr);
1da177e4 2068
7314e9e7
TG		 2069 /* Shift to get page */
2070 realpage = (int)(from >> chip->page_shift);
2071 page = realpage & chip->pagemask;
1da177e4 2072
f8ac0414 2073 while (1) {
0612b9dd 2074 if (ops->mode == MTD_OPS_RAW)
1951f2f7 2075 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 2076 else
1951f2f7
SL		 2077 ret = chip->ecc.read_oob(mtd, chip, page);
2078
2079 if (ret < 0)
2080 break;
7014568b
VW		 2081
2082 len = min(len, readlen);
2083 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 2084
5bc7c33c
BN		 2085 if (chip->options & NAND_NEED_READRDY) {
2086 /* Apply delay or wait for ready/busy pin */
2087 if (!chip->dev_ready)
2088 udelay(chip->chip_delay);
2089 else
2090 nand_wait_ready(mtd);
2091 }
2092
7014568b 2093 readlen -= len;
0d420f9d
SZ		 2094 if (!readlen)
2095 break;
2096
7314e9e7
TG		 2097 /* Increment page address */
2098 realpage++;
2099
2100 page = realpage & chip->pagemask;
2101 /* Check, if we cross a chip boundary */
2102 if (!page) {
2103 chipnr++;
2104 chip->select_chip(mtd, -1);
2105 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2106 }
2107 }
b0bb6903 2108 chip->select_chip(mtd, -1);
1da177e4 2109
1951f2f7
SL		 2110 ops->oobretlen = ops->ooblen - readlen;
2111
2112 if (ret < 0)
2113 return ret;
041e4575
BN		 2114
2115 if (mtd->ecc_stats.failed - stats.failed)
2116 return -EBADMSG;
2117
2118 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 2119}
2120
2121/**
8593fbc6 2122 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 2123 * @mtd: MTD device structure
2124 * @from: offset to read from
2125 * @ops: oob operation description structure
1da177e4 2126 *
8b6e50c9 2127 * NAND read data and/or out-of-band data.
1da177e4 2128 */
8593fbc6
TG		 2129static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2130 struct mtd_oob_ops *ops)
1da177e4 2131{
8593fbc6
TG		 2132 int ret = -ENOTSUPP;
2133
2134 ops->retlen = 0;
1da177e4
LT		 2135
2136 /* Do not allow reads past end of device */
7014568b 2137 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 2138 pr_debug("%s: attempt to read beyond end of device\n",
2139 __func__);
1da177e4
LT		 2140 return -EINVAL;
2141 }
2142
6a8214aa 2143 nand_get_device(mtd, FL_READING);
1da177e4 2144
f8ac0414 2145 switch (ops->mode) {
0612b9dd
BN		 2146 case MTD_OPS_PLACE_OOB:
2147 case MTD_OPS_AUTO_OOB:
2148 case MTD_OPS_RAW:
8593fbc6 2149 break;
1da177e4 2150
8593fbc6
TG		 2151 default:
2152 goto out;
2153 }
1da177e4 2154
8593fbc6
TG		 2155 if (!ops->datbuf)
2156 ret = nand_do_read_oob(mtd, from, ops);
2157 else
2158 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 2159
7351d3a5 2160out:
8593fbc6
TG		 2161 nand_release_device(mtd);
2162 return ret;
2163}
61b03bd7 2164
1da177e4 2165
8593fbc6 2166/**
7854d3f7 2167 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 2168 * @mtd: mtd info structure
2169 * @chip: nand chip info structure
2170 * @buf: data buffer
1fbb938d 2171 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2172 * @page: page number to write
52ff49df 2173 *
7854d3f7 2174 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 2175 */
fdbad98d 2176static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9 2177 const uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 2178{
2179 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 2180 if (oob_required)
2181 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2182
2183 return 0;
1da177e4
LT		 2184}
2185
52ff49df 2186/**
7854d3f7 2187 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 2188 * @mtd: mtd info structure
2189 * @chip: nand chip info structure
2190 * @buf: data buffer
1fbb938d 2191 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2192 * @page: page number to write
52ff49df
DB		 2193 *
2194 * We need a special oob layout and handling even when ECC isn't checked.
2195 */
fdbad98d 2196static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 2197 struct nand_chip *chip,
45aaeff9
BB		 2198 const uint8_t *buf, int oob_required,
2199 int page)
52ff49df
DB		 2200{
2201 int eccsize = chip->ecc.size;
2202 int eccbytes = chip->ecc.bytes;
2203 uint8_t *oob = chip->oob_poi;
2204 int steps, size;
2205
2206 for (steps = chip->ecc.steps; steps > 0; steps--) {
2207 chip->write_buf(mtd, buf, eccsize);
2208 buf += eccsize;
2209
2210 if (chip->ecc.prepad) {
2211 chip->write_buf(mtd, oob, chip->ecc.prepad);
2212 oob += chip->ecc.prepad;
2213 }
2214
60c3bc1f 2215 chip->write_buf(mtd, oob, eccbytes);
52ff49df
DB		 2216 oob += eccbytes;
2217
2218 if (chip->ecc.postpad) {
2219 chip->write_buf(mtd, oob, chip->ecc.postpad);
2220 oob += chip->ecc.postpad;
2221 }
2222 }
2223
2224 size = mtd->oobsize - (oob - chip->oob_poi);
2225 if (size)
2226 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 2227
2228 return 0;
52ff49df 2229}
9223a456 2230/**
7854d3f7 2231 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 2232 * @mtd: mtd info structure
2233 * @chip: nand chip info structure
2234 * @buf: data buffer
1fbb938d 2235 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2236 * @page: page number to write
9223a456 2237 */
fdbad98d 2238static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9
BB		 2239 const uint8_t *buf, int oob_required,
2240 int page)
9223a456 2241{
f75e5097
TG		 2242 int i, eccsize = chip->ecc.size;
2243 int eccbytes = chip->ecc.bytes;
2244 int eccsteps = chip->ecc.steps;
4bf63fcb 2245 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2246 const uint8_t *p = buf;
8b099a39 2247 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2248
7854d3f7 2249 /* Software ECC calculation */
8593fbc6
TG		 2250 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2251 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 2252
8593fbc6
TG		 2253 for (i = 0; i < chip->ecc.total; i++)
2254 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 2255
45aaeff9 2256 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
f75e5097 2257}
9223a456 2258
f75e5097 2259/**
7854d3f7 2260 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2261 * @mtd: mtd info structure
2262 * @chip: nand chip info structure
2263 * @buf: data buffer
1fbb938d 2264 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2265 * @page: page number to write
f75e5097 2266 */
fdbad98d 2267static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9
BB		 2268 const uint8_t *buf, int oob_required,
2269 int page)
f75e5097
TG		 2270{
2271 int i, eccsize = chip->ecc.size;
2272 int eccbytes = chip->ecc.bytes;
2273 int eccsteps = chip->ecc.steps;
4bf63fcb 2274 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2275 const uint8_t *p = buf;
8b099a39 2276 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2277
f75e5097
TG		 2278 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2279 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2280 chip->write_buf(mtd, p, eccsize);
f75e5097 2281 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2282 }
2283
f75e5097
TG		 2284 for (i = 0; i < chip->ecc.total; i++)
2285 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2286
2287 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2288
2289 return 0;
9223a456
TG		 2290}
2291
837a6ba4
GP		 2292
2293/**
73c8aaf4 2294 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
837a6ba4
GP		 2295 * @mtd: mtd info structure
2296 * @chip: nand chip info structure
d6a95080 2297 * @offset: column address of subpage within the page
837a6ba4 2298 * @data_len: data length
d6a95080 2299 * @buf: data buffer
837a6ba4 2300 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2301 * @page: page number to write
837a6ba4
GP		 2302 */
2303static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2304 struct nand_chip *chip, uint32_t offset,
d6a95080 2305 uint32_t data_len, const uint8_t *buf,
45aaeff9 2306 int oob_required, int page)
837a6ba4
GP		 2307{
2308 uint8_t *oob_buf = chip->oob_poi;
2309 uint8_t *ecc_calc = chip->buffers->ecccalc;
2310 int ecc_size = chip->ecc.size;
2311 int ecc_bytes = chip->ecc.bytes;
2312 int ecc_steps = chip->ecc.steps;
2313 uint32_t *eccpos = chip->ecc.layout->eccpos;
2314 uint32_t start_step = offset / ecc_size;
2315 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2316 int oob_bytes = mtd->oobsize / ecc_steps;
2317 int step, i;
2318
2319 for (step = 0; step < ecc_steps; step++) {
2320 /* configure controller for WRITE access */
2321 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2322
2323 /* write data (untouched subpages already masked by 0xFF) */
d6a95080 2324 chip->write_buf(mtd, buf, ecc_size);
837a6ba4
GP		 2325
2326 /* mask ECC of un-touched subpages by padding 0xFF */
2327 if ((step < start_step) || (step > end_step))
2328 memset(ecc_calc, 0xff, ecc_bytes);
2329 else
d6a95080 2330 chip->ecc.calculate(mtd, buf, ecc_calc);
837a6ba4
GP		 2331
2332 /* mask OOB of un-touched subpages by padding 0xFF */
2333 /* if oob_required, preserve OOB metadata of written subpage */
2334 if (!oob_required || (step < start_step) || (step > end_step))
2335 memset(oob_buf, 0xff, oob_bytes);
2336
d6a95080 2337 buf += ecc_size;
837a6ba4
GP		 2338 ecc_calc += ecc_bytes;
2339 oob_buf += oob_bytes;
2340 }
2341
2342 /* copy calculated ECC for whole page to chip->buffer->oob */
2343 /* this include masked-value(0xFF) for unwritten subpages */
2344 ecc_calc = chip->buffers->ecccalc;
2345 for (i = 0; i < chip->ecc.total; i++)
2346 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2347
2348 /* write OOB buffer to NAND device */
2349 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2350
2351 return 0;
2352}
2353
2354
61b03bd7 2355/**
7854d3f7 2356 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2357 * @mtd: mtd info structure
2358 * @chip: nand chip info structure
2359 * @buf: data buffer
1fbb938d 2360 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2361 * @page: page number to write
1da177e4 2362 *
8b6e50c9
BN		 2363 * The hw generator calculates the error syndrome automatically. Therefore we
2364 * need a special oob layout and handling.
f75e5097 2365 */
fdbad98d 2366static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d 2367 struct nand_chip *chip,
45aaeff9
BB		 2368 const uint8_t *buf, int oob_required,
2369 int page)
1da177e4 2370{
f75e5097
TG		 2371 int i, eccsize = chip->ecc.size;
2372 int eccbytes = chip->ecc.bytes;
2373 int eccsteps = chip->ecc.steps;
2374 const uint8_t *p = buf;
2375 uint8_t *oob = chip->oob_poi;
1da177e4 2376
f75e5097 2377 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2378
f75e5097
TG		 2379 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2380 chip->write_buf(mtd, p, eccsize);
61b03bd7 2381
f75e5097
TG		 2382 if (chip->ecc.prepad) {
2383 chip->write_buf(mtd, oob, chip->ecc.prepad);
2384 oob += chip->ecc.prepad;
2385 }
2386
2387 chip->ecc.calculate(mtd, p, oob);
2388 chip->write_buf(mtd, oob, eccbytes);
2389 oob += eccbytes;
2390
2391 if (chip->ecc.postpad) {
2392 chip->write_buf(mtd, oob, chip->ecc.postpad);
2393 oob += chip->ecc.postpad;
1da177e4 2394 }
1da177e4 2395 }
f75e5097
TG		 2396
2397 /* Calculate remaining oob bytes */
7e4178f9 2398 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2399 if (i)
2400 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2401
2402 return 0;
f75e5097
TG		 2403}
2404
2405/**
956e944c 2406 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2407 * @mtd: MTD device structure
2408 * @chip: NAND chip descriptor
837a6ba4
GP		 2409 * @offset: address offset within the page
2410 * @data_len: length of actual data to be written
8b6e50c9 2411 * @buf: the data to write
1fbb938d 2412 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2413 * @page: page number to write
2414 * @cached: cached programming
2415 * @raw: use _raw version of write_page
f75e5097
TG		 2416 */
2417static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4
GP		 2418 uint32_t offset, int data_len, const uint8_t *buf,
2419 int oob_required, int page, int cached, int raw)
f75e5097 2420{
837a6ba4
GP		 2421 int status, subpage;
2422
2423 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2424 chip->ecc.write_subpage)
2425 subpage = offset || (data_len < mtd->writesize);
2426 else
2427 subpage = 0;
f75e5097
TG		 2428
2429 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2430
956e944c 2431 if (unlikely(raw))
837a6ba4 2432 status = chip->ecc.write_page_raw(mtd, chip, buf,
45aaeff9 2433 oob_required, page);
837a6ba4
GP		 2434 else if (subpage)
2435 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
45aaeff9 2436 buf, oob_required, page);
956e944c 2437 else
45aaeff9
BB		 2438 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2439 page);
fdbad98d
JW		 2440
2441 if (status < 0)
2442 return status;
f75e5097
TG		 2443
2444 /*
7854d3f7 2445 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2446 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2447 */
2448 cached = 0;
2449
3239a6cd 2450 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2451
2452 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2453 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2454 /*
2455 * See if operation failed and additional status checks are
8b6e50c9 2456 * available.
f75e5097
TG		 2457 */
2458 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2459 status = chip->errstat(mtd, chip, FL_WRITING, status,
2460 page);
2461
2462 if (status & NAND_STATUS_FAIL)
2463 return -EIO;
2464 } else {
2465 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2466 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2467 }
2468
f75e5097 2469 return 0;
1da177e4
LT		 2470}
2471
8593fbc6 2472/**
7854d3f7 2473 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2474 * @mtd: MTD device structure
8b6e50c9
BN		 2475 * @oob: oob data buffer
2476 * @len: oob data write length
2477 * @ops: oob ops structure
8593fbc6 2478 */
f722013e
TAA		 2479static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2480 struct mtd_oob_ops *ops)
8593fbc6 2481{
862eba51 2482 struct nand_chip *chip = mtd_to_nand(mtd);
f722013e
TAA		 2483
2484 /*
2485 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2486 * data from a previous OOB read.
2487 */
2488 memset(chip->oob_poi, 0xff, mtd->oobsize);
2489
f8ac0414 2490 switch (ops->mode) {
8593fbc6 2491
0612b9dd
BN		 2492 case MTD_OPS_PLACE_OOB:
2493 case MTD_OPS_RAW:
8593fbc6
TG		 2494 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2495 return oob + len;
2496
0612b9dd 2497 case MTD_OPS_AUTO_OOB: {
8593fbc6 2498 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2499 uint32_t boffs = 0, woffs = ops->ooboffs;
2500 size_t bytes = 0;
8593fbc6 2501
f8ac0414 2502 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2503 /* Write request not from offset 0? */
7bc3312b
TG		 2504 if (unlikely(woffs)) {
2505 if (woffs >= free->length) {
2506 woffs -= free->length;
2507 continue;
2508 }
2509 boffs = free->offset + woffs;
2510 bytes = min_t(size_t, len,
2511 (free->length - woffs));
2512 woffs = 0;
2513 } else {
2514 bytes = min_t(size_t, len, free->length);
2515 boffs = free->offset;
2516 }
8b0036ee 2517 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2518 oob += bytes;
2519 }
2520 return oob;
2521 }
2522 default:
2523 BUG();
2524 }
2525 return NULL;
2526}
2527
f8ac0414 2528#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2529
2530/**
7854d3f7 2531 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2532 * @mtd: MTD device structure
2533 * @to: offset to write to
2534 * @ops: oob operations description structure
1da177e4 2535 *
8b6e50c9 2536 * NAND write with ECC.
1da177e4 2537 */
8593fbc6
TG		 2538static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2539 struct mtd_oob_ops *ops)
1da177e4 2540{
29072b96 2541 int chipnr, realpage, page, blockmask, column;
862eba51 2542 struct nand_chip *chip = mtd_to_nand(mtd);
8593fbc6 2543 uint32_t writelen = ops->len;
782ce79a
ML		 2544
2545 uint32_t oobwritelen = ops->ooblen;
29f1058a 2546 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
782ce79a 2547
8593fbc6
TG		 2548 uint8_t *oob = ops->oobbuf;
2549 uint8_t *buf = ops->datbuf;
837a6ba4 2550 int ret;
e47f3db4 2551 int oob_required = oob ? 1 : 0;
1da177e4 2552
8593fbc6 2553 ops->retlen = 0;
29072b96
TG		 2554 if (!writelen)
2555 return 0;
1da177e4 2556
8b6e50c9 2557 /* Reject writes, which are not page aligned */
8593fbc6 2558 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2559 pr_notice("%s: attempt to write non page aligned data\n",
2560 __func__);
1da177e4
LT		 2561 return -EINVAL;
2562 }
2563
29072b96 2564 column = to & (mtd->writesize - 1);
1da177e4 2565
6a930961
TG		 2566 chipnr = (int)(to >> chip->chip_shift);
2567 chip->select_chip(mtd, chipnr);
2568
1da177e4 2569 /* Check, if it is write protected */
b0bb6903
HS		 2570 if (nand_check_wp(mtd)) {
2571 ret = -EIO;
2572 goto err_out;
2573 }
1da177e4 2574
f75e5097
TG		 2575 realpage = (int)(to >> chip->page_shift);
2576 page = realpage & chip->pagemask;
2577 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2578
2579 /* Invalidate the page cache, when we write to the cached page */
537ab1bd
BN		 2580 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2581 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2582 chip->pagebuf = -1;
61b03bd7 2583
782ce79a 2584 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2585 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2586 ret = -EINVAL;
2587 goto err_out;
2588 }
782ce79a 2589
f8ac0414 2590 while (1) {
29072b96 2591 int bytes = mtd->writesize;
f75e5097 2592 int cached = writelen > bytes && page != blockmask;
29072b96 2593 uint8_t *wbuf = buf;
66507c7b
KD		 2594 int use_bufpoi;
2595 int part_pagewr = (column || writelen < (mtd->writesize - 1));
2596
2597 if (part_pagewr)
2598 use_bufpoi = 1;
2599 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2600 use_bufpoi = !virt_addr_valid(buf);
2601 else
2602 use_bufpoi = 0;
29072b96 2603
66507c7b
KD		 2604 /* Partial page write?, or need to use bounce buffer */
2605 if (use_bufpoi) {
2606 pr_debug("%s: using write bounce buffer for buf@%p\n",
2607 __func__, buf);
29072b96 2608 cached = 0;
66507c7b
KD		 2609 if (part_pagewr)
2610 bytes = min_t(int, bytes - column, writelen);
29072b96
TG		 2611 chip->pagebuf = -1;
2612 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2613 memcpy(&chip->buffers->databuf[column], buf, bytes);
2614 wbuf = chip->buffers->databuf;
2615 }
1da177e4 2616
782ce79a
ML		 2617 if (unlikely(oob)) {
2618 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2619 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2620 oobwritelen -= len;
f722013e
TAA		 2621 } else {
2622 /* We still need to erase leftover OOB data */
2623 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2624 }
837a6ba4
GP		 2625 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2626 oob_required, page, cached,
2627 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2628 if (ret)
2629 break;
2630
2631 writelen -= bytes;
2632 if (!writelen)
2633 break;
2634
29072b96 2635 column = 0;
f75e5097
TG		 2636 buf += bytes;
2637 realpage++;
2638
2639 page = realpage & chip->pagemask;
2640 /* Check, if we cross a chip boundary */
2641 if (!page) {
2642 chipnr++;
2643 chip->select_chip(mtd, -1);
2644 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2645 }
2646 }
8593fbc6 2647
8593fbc6 2648 ops->retlen = ops->len - writelen;
7014568b
VW		 2649 if (unlikely(oob))
2650 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2651
2652err_out:
2653 chip->select_chip(mtd, -1);
1da177e4
LT		 2654 return ret;
2655}
2656
2af7c653
SK		 2657/**
2658 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2659 * @mtd: MTD device structure
2660 * @to: offset to write to
2661 * @len: number of bytes to write
2662 * @retlen: pointer to variable to store the number of written bytes
2663 * @buf: the data to write
2af7c653
SK		 2664 *
2665 * NAND write with ECC. Used when performing writes in interrupt context, this
2666 * may for example be called by mtdoops when writing an oops while in panic.
2667 */
2668static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2669 size_t *retlen, const uint8_t *buf)
2670{
862eba51 2671 struct nand_chip *chip = mtd_to_nand(mtd);
4a89ff88 2672 struct mtd_oob_ops ops;
2af7c653
SK		 2673 int ret;
2674
8b6e50c9 2675 /* Wait for the device to get ready */
2af7c653
SK		 2676 panic_nand_wait(mtd, chip, 400);
2677
8b6e50c9 2678 /* Grab the device */
2af7c653
SK		 2679 panic_nand_get_device(chip, mtd, FL_WRITING);
2680
0ec56dc4 2681 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2682 ops.len = len;
2683 ops.datbuf = (uint8_t *)buf;
11041ae6 2684 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2685
4a89ff88 2686 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2687
4a89ff88 2688 *retlen = ops.retlen;
2af7c653
SK		 2689 return ret;
2690}
2691
f75e5097 2692/**
8593fbc6 2693 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2694 * @mtd: MTD device structure
2695 * @to: offset to write to
2696 * @len: number of bytes to write
2697 * @retlen: pointer to variable to store the number of written bytes
2698 * @buf: the data to write
f75e5097 2699 *
8b6e50c9 2700 * NAND write with ECC.
f75e5097 2701 */
8593fbc6
TG		 2702static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2703 size_t *retlen, const uint8_t *buf)
f75e5097 2704{
4a89ff88 2705 struct mtd_oob_ops ops;
f75e5097
TG		 2706 int ret;
2707
6a8214aa 2708 nand_get_device(mtd, FL_WRITING);
0ec56dc4 2709 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2710 ops.len = len;
2711 ops.datbuf = (uint8_t *)buf;
11041ae6 2712 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2713 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2714 *retlen = ops.retlen;
f75e5097 2715 nand_release_device(mtd);
8593fbc6 2716 return ret;
f75e5097 2717}
7314e9e7 2718
1da177e4 2719/**
8593fbc6 2720 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2721 * @mtd: MTD device structure
2722 * @to: offset to write to
2723 * @ops: oob operation description structure
1da177e4 2724 *
8b6e50c9 2725 * NAND write out-of-band.
1da177e4 2726 */
8593fbc6
TG		 2727static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2728 struct mtd_oob_ops *ops)
1da177e4 2729{
03736155 2730 int chipnr, page, status, len;
862eba51 2731 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 2732
289c0522 2733 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2734 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2735
29f1058a 2736 len = mtd_oobavail(mtd, ops);
03736155 2737
1da177e4 2738 /* Do not allow write past end of page */
03736155 2739 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2740 pr_debug("%s: attempt to write past end of page\n",
2741 __func__);
1da177e4
LT		 2742 return -EINVAL;
2743 }
2744
03736155 2745 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2746 pr_debug("%s: attempt to start write outside oob\n",
2747 __func__);
03736155
AH		 2748 return -EINVAL;
2749 }
2750
775adc3d 2751 /* Do not allow write past end of device */
03736155
AH		 2752 if (unlikely(to >= mtd->size ||
2753 ops->ooboffs + ops->ooblen >
2754 ((mtd->size >> chip->page_shift) -
2755 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2756 pr_debug("%s: attempt to write beyond end of device\n",
2757 __func__);
03736155
AH		 2758 return -EINVAL;
2759 }
2760
7314e9e7 2761 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2762 chip->select_chip(mtd, chipnr);
1da177e4 2763
7314e9e7
TG		 2764 /* Shift to get page */
2765 page = (int)(to >> chip->page_shift);
2766
2767 /*
2768 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2769 * of my DiskOnChip 2000 test units) will clear the whole data page too
2770 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2771 * it in the doc2000 driver in August 1999. dwmw2.
2772 */
ace4dfee 2773 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2774
2775 /* Check, if it is write protected */
b0bb6903
HS		 2776 if (nand_check_wp(mtd)) {
2777 chip->select_chip(mtd, -1);
8593fbc6 2778 return -EROFS;
b0bb6903 2779 }
61b03bd7 2780
1da177e4 2781 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2782 if (page == chip->pagebuf)
2783 chip->pagebuf = -1;
1da177e4 2784
f722013e 2785 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2786
0612b9dd 2787 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2788 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2789 else
2790 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2791
b0bb6903
HS		 2792 chip->select_chip(mtd, -1);
2793
7bc3312b
TG		 2794 if (status)
2795 return status;
1da177e4 2796
7014568b 2797 ops->oobretlen = ops->ooblen;
1da177e4 2798
7bc3312b 2799 return 0;
8593fbc6
TG		 2800}
2801
2802/**
2803 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2804 * @mtd: MTD device structure
2805 * @to: offset to write to
2806 * @ops: oob operation description structure
8593fbc6
TG		 2807 */
2808static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2809 struct mtd_oob_ops *ops)
2810{
8593fbc6
TG		 2811 int ret = -ENOTSUPP;
2812
2813 ops->retlen = 0;
2814
2815 /* Do not allow writes past end of device */
7014568b 2816 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2817 pr_debug("%s: attempt to write beyond end of device\n",
2818 __func__);
8593fbc6
TG		 2819 return -EINVAL;
2820 }
2821
6a8214aa 2822 nand_get_device(mtd, FL_WRITING);
8593fbc6 2823
f8ac0414 2824 switch (ops->mode) {
0612b9dd
BN		 2825 case MTD_OPS_PLACE_OOB:
2826 case MTD_OPS_AUTO_OOB:
2827 case MTD_OPS_RAW:
8593fbc6
TG		 2828 break;
2829
2830 default:
2831 goto out;
2832 }
2833
2834 if (!ops->datbuf)
2835 ret = nand_do_write_oob(mtd, to, ops);
2836 else
2837 ret = nand_do_write_ops(mtd, to, ops);
2838
7351d3a5 2839out:
1da177e4 2840 nand_release_device(mtd);
1da177e4
LT		 2841 return ret;
2842}
2843
1da177e4 2844/**
49c50b97 2845 * single_erase - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2846 * @mtd: MTD device structure
2847 * @page: the page address of the block which will be erased
1da177e4 2848 *
49c50b97 2849 * Standard erase command for NAND chips. Returns NAND status.
1da177e4 2850 */
49c50b97 2851static int single_erase(struct mtd_info *mtd, int page)
1da177e4 2852{
862eba51 2853 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 2854 /* Send commands to erase a block */
ace4dfee
TG		 2855 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2856 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
49c50b97
BN		 2857
2858 return chip->waitfunc(mtd, chip);
1da177e4
LT		 2859}
2860
1da177e4
LT		 2861/**
2862 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2863 * @mtd: MTD device structure
2864 * @instr: erase instruction
1da177e4 2865 *
8b6e50c9 2866 * Erase one ore more blocks.
1da177e4 2867 */
e0c7d767 2868static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2869{
e0c7d767 2870 return nand_erase_nand(mtd, instr, 0);
1da177e4 2871}
61b03bd7 2872
1da177e4 2873/**
7854d3f7 2874 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2875 * @mtd: MTD device structure
2876 * @instr: erase instruction
2877 * @allowbbt: allow erasing the bbt area
1da177e4 2878 *
8b6e50c9 2879 * Erase one ore more blocks.
1da177e4 2880 */
ace4dfee
TG		 2881int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2882 int allowbbt)
1da177e4 2883{
69423d99 2884 int page, status, pages_per_block, ret, chipnr;
862eba51 2885 struct nand_chip *chip = mtd_to_nand(mtd);
69423d99 2886 loff_t len;
1da177e4 2887
289c0522
BN		 2888 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2889 __func__, (unsigned long long)instr->addr,
2890 (unsigned long long)instr->len);
1da177e4 2891
6fe5a6ac 2892 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2893 return -EINVAL;
1da177e4 2894
1da177e4 2895 /* Grab the lock and see if the device is available */
6a8214aa 2896 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 2897
2898 /* Shift to get first page */
ace4dfee
TG		 2899 page = (int)(instr->addr >> chip->page_shift);
2900 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2901
2902 /* Calculate pages in each block */
ace4dfee 2903 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2904
2905 /* Select the NAND device */
ace4dfee 2906 chip->select_chip(mtd, chipnr);
1da177e4 2907
1da177e4
LT		 2908 /* Check, if it is write protected */
2909 if (nand_check_wp(mtd)) {
289c0522
BN		 2910 pr_debug("%s: device is write protected!\n",
2911 __func__);
1da177e4
LT		 2912 instr->state = MTD_ERASE_FAILED;
2913 goto erase_exit;
2914 }
2915
2916 /* Loop through the pages */
2917 len = instr->len;
2918
2919 instr->state = MTD_ERASING;
2920
2921 while (len) {
12183a20 2922 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee 2923 if (nand_block_checkbad(mtd, ((loff_t) page) <<
9f3e0429 2924 chip->page_shift, allowbbt)) {
d0370219
BN		 2925 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2926 __func__, page);
1da177e4
LT		 2927 instr->state = MTD_ERASE_FAILED;
2928 goto erase_exit;
2929 }
61b03bd7 2930
ace4dfee
TG		 2931 /*
2932 * Invalidate the page cache, if we erase the block which
8b6e50c9 2933 * contains the current cached page.
ace4dfee
TG		 2934 */
2935 if (page <= chip->pagebuf && chip->pagebuf <
2936 (page + pages_per_block))
2937 chip->pagebuf = -1;
1da177e4 2938
49c50b97 2939 status = chip->erase(mtd, page & chip->pagemask);
1da177e4 2940
ace4dfee
TG		 2941 /*
2942 * See if operation failed and additional status checks are
2943 * available
2944 */
2945 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2946 status = chip->errstat(mtd, chip, FL_ERASING,
2947 status, page);
068e3c0a 2948
1da177e4 2949 /* See if block erase succeeded */
a4ab4c5d 2950 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2951 pr_debug("%s: failed erase, page 0x%08x\n",
2952 __func__, page);
1da177e4 2953 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2954 instr->fail_addr =
2955 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2956 goto erase_exit;
2957 }
30f464b7 2958
1da177e4 2959 /* Increment page address and decrement length */
daae74ca 2960 len -= (1ULL << chip->phys_erase_shift);
1da177e4
LT		 2961 page += pages_per_block;
2962
2963 /* Check, if we cross a chip boundary */
ace4dfee 2964 if (len && !(page & chip->pagemask)) {
1da177e4 2965 chipnr++;
ace4dfee
TG		 2966 chip->select_chip(mtd, -1);
2967 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2968 }
2969 }
2970 instr->state = MTD_ERASE_DONE;
2971
7351d3a5 2972erase_exit:
1da177e4
LT		 2973
2974 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2975
2976 /* Deselect and wake up anyone waiting on the device */
b0bb6903 2977 chip->select_chip(mtd, -1);
1da177e4
LT		 2978 nand_release_device(mtd);
2979
49defc01
DW		 2980 /* Do call back function */
2981 if (!ret)
2982 mtd_erase_callback(instr);
2983
1da177e4
LT		 2984 /* Return more or less happy */
2985 return ret;
2986}
2987
2988/**
2989 * nand_sync - [MTD Interface] sync
8b6e50c9 2990 * @mtd: MTD device structure
1da177e4 2991 *
8b6e50c9 2992 * Sync is actually a wait for chip ready function.
1da177e4 2993 */
e0c7d767 2994static void nand_sync(struct mtd_info *mtd)
1da177e4 2995{
289c0522 2996 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2997
2998 /* Grab the lock and see if the device is available */
6a8214aa 2999 nand_get_device(mtd, FL_SYNCING);
1da177e4 3000 /* Release it and go back */
e0c7d767 3001 nand_release_device(mtd);
1da177e4
LT		 3002}
3003
1da177e4 3004/**
ace4dfee 3005 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 3006 * @mtd: MTD device structure
3007 * @offs: offset relative to mtd start
1da177e4 3008 */
ace4dfee 3009static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 3010{
9f3e0429
AT		 3011 struct nand_chip *chip = mtd_to_nand(mtd);
3012 int chipnr = (int)(offs >> chip->chip_shift);
3013 int ret;
3014
3015 /* Select the NAND device */
3016 nand_get_device(mtd, FL_READING);
3017 chip->select_chip(mtd, chipnr);
3018
3019 ret = nand_block_checkbad(mtd, offs, 0);
3020
3021 chip->select_chip(mtd, -1);
3022 nand_release_device(mtd);
3023
3024 return ret;
1da177e4
LT		 3025}
3026
3027/**
ace4dfee 3028 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 3029 * @mtd: MTD device structure
3030 * @ofs: offset relative to mtd start
1da177e4 3031 */
e0c7d767 3032static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 3033{
1da177e4
LT		 3034 int ret;
3035
f8ac0414
FF		 3036 ret = nand_block_isbad(mtd, ofs);
3037 if (ret) {
8b6e50c9 3038 /* If it was bad already, return success and do nothing */
1da177e4
LT		 3039 if (ret > 0)
3040 return 0;
e0c7d767
DW		 3041 return ret;
3042 }
1da177e4 3043
5a0edb25 3044 return nand_block_markbad_lowlevel(mtd, ofs);
1da177e4
LT		 3045}
3046
7db03ecc
HS		 3047/**
3048 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3049 * @mtd: MTD device structure
3050 * @chip: nand chip info structure
3051 * @addr: feature address.
3052 * @subfeature_param: the subfeature parameters, a four bytes array.
3053 */
3054static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3055 int addr, uint8_t *subfeature_param)
3056{
3057 int status;
05f78359 3058 int i;
7db03ecc 3059
d914c932
DM		 3060 if (!chip->onfi_version ||
3061 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3062 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 3063 return -EINVAL;
3064
3065 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
05f78359
UKK		 3066 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3067 chip->write_byte(mtd, subfeature_param[i]);
3068
7db03ecc
HS		 3069 status = chip->waitfunc(mtd, chip);
3070 if (status & NAND_STATUS_FAIL)
3071 return -EIO;
3072 return 0;
3073}
3074
3075/**
3076 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3077 * @mtd: MTD device structure
3078 * @chip: nand chip info structure
3079 * @addr: feature address.
3080 * @subfeature_param: the subfeature parameters, a four bytes array.
3081 */
3082static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3083 int addr, uint8_t *subfeature_param)
3084{
05f78359
UKK		 3085 int i;
3086
d914c932
DM		 3087 if (!chip->onfi_version ||
3088 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3089 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 3090 return -EINVAL;
3091
7db03ecc 3092 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
05f78359
UKK		 3093 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3094 *subfeature_param++ = chip->read_byte(mtd);
7db03ecc
HS		 3095 return 0;
3096}
3097
962034f4
VW		 3098/**
3099 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 3100 * @mtd: MTD device structure
962034f4
VW		 3101 */
3102static int nand_suspend(struct mtd_info *mtd)
3103{
6a8214aa 3104 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 3105}
3106
3107/**
3108 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 3109 * @mtd: MTD device structure
962034f4
VW		 3110 */
3111static void nand_resume(struct mtd_info *mtd)
3112{
862eba51 3113 struct nand_chip *chip = mtd_to_nand(mtd);
962034f4 3114
ace4dfee 3115 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 3116 nand_release_device(mtd);
3117 else
d0370219
BN		 3118 pr_err("%s called for a chip which is not in suspended state\n",
3119 __func__);
962034f4
VW		 3120}
3121
72ea4036
SB		 3122/**
3123 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3124 * prevent further operations
3125 * @mtd: MTD device structure
3126 */
3127static void nand_shutdown(struct mtd_info *mtd)
3128{
9ca641b0 3129 nand_get_device(mtd, FL_PM_SUSPENDED);
72ea4036
SB		 3130}
3131
8b6e50c9 3132/* Set default functions */
ace4dfee 3133static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 3134{
1da177e4 3135 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 3136 if (!chip->chip_delay)
3137 chip->chip_delay = 20;
1da177e4
LT		 3138
3139 /* check, if a user supplied command function given */
ace4dfee
TG		 3140 if (chip->cmdfunc == NULL)
3141 chip->cmdfunc = nand_command;
1da177e4
LT		 3142
3143 /* check, if a user supplied wait function given */
ace4dfee
TG		 3144 if (chip->waitfunc == NULL)
3145 chip->waitfunc = nand_wait;
3146
3147 if (!chip->select_chip)
3148 chip->select_chip = nand_select_chip;
68e80780 3149
4204cccd
HS		 3150 /* set for ONFI nand */
3151 if (!chip->onfi_set_features)
3152 chip->onfi_set_features = nand_onfi_set_features;
3153 if (!chip->onfi_get_features)
3154 chip->onfi_get_features = nand_onfi_get_features;
3155
68e80780
BN		 3156 /* If called twice, pointers that depend on busw may need to be reset */
3157 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 3158 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3159 if (!chip->read_word)
3160 chip->read_word = nand_read_word;
3161 if (!chip->block_bad)
3162 chip->block_bad = nand_block_bad;
3163 if (!chip->block_markbad)
3164 chip->block_markbad = nand_default_block_markbad;
68e80780 3165 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 3166 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
05f78359
UKK		 3167 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3168 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
68e80780 3169 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 3170 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 3171 if (!chip->scan_bbt)
3172 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 3173
3174 if (!chip->controller) {
3175 chip->controller = &chip->hwcontrol;
3176 spin_lock_init(&chip->controller->lock);
3177 init_waitqueue_head(&chip->controller->wq);
3178 }
3179
7aa65bfd
TG		 3180}
3181
8b6e50c9 3182/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 3183static void sanitize_string(uint8_t *s, size_t len)
3184{
3185 ssize_t i;
3186
8b6e50c9 3187 /* Null terminate */
d1e1f4e4
FF		 3188 s[len - 1] = 0;
3189
8b6e50c9 3190 /* Remove non printable chars */
d1e1f4e4
FF		 3191 for (i = 0; i < len - 1; i++) {
3192 if (s[i] < ' ' || s[i] > 127)
3193 s[i] = '?';
3194 }
3195
8b6e50c9 3196 /* Remove trailing spaces */
d1e1f4e4
FF		 3197 strim(s);
3198}
3199
3200static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3201{
3202 int i;
3203 while (len--) {
3204 crc ^= *p++ << 8;
3205 for (i = 0; i < 8; i++)
3206 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3207 }
3208
3209 return crc;
3210}
3211
6dcbe0cd
HS		 3212/* Parse the Extended Parameter Page. */
3213static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3214 struct nand_chip *chip, struct nand_onfi_params *p)
3215{
3216 struct onfi_ext_param_page *ep;
3217 struct onfi_ext_section *s;
3218 struct onfi_ext_ecc_info *ecc;
3219 uint8_t *cursor;
3220 int ret = -EINVAL;
3221 int len;
3222 int i;
3223
3224 len = le16_to_cpu(p->ext_param_page_length) * 16;
3225 ep = kmalloc(len, GFP_KERNEL);
5cb13271
BN		 3226 if (!ep)
3227 return -ENOMEM;
6dcbe0cd
HS		 3228
3229 /* Send our own NAND_CMD_PARAM. */
3230 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3231
3232 /* Use the Change Read Column command to skip the ONFI param pages. */
3233 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3234 sizeof(*p) * p->num_of_param_pages , -1);
3235
3236 /* Read out the Extended Parameter Page. */
3237 chip->read_buf(mtd, (uint8_t *)ep, len);
3238 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3239 != le16_to_cpu(ep->crc))) {
3240 pr_debug("fail in the CRC.\n");
3241 goto ext_out;
3242 }
3243
3244 /*
3245 * Check the signature.
3246 * Do not strictly follow the ONFI spec, maybe changed in future.
3247 */
3248 if (strncmp(ep->sig, "EPPS", 4)) {
3249 pr_debug("The signature is invalid.\n");
3250 goto ext_out;
3251 }
3252
3253 /* find the ECC section. */
3254 cursor = (uint8_t *)(ep + 1);
3255 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3256 s = ep->sections + i;
3257 if (s->type == ONFI_SECTION_TYPE_2)
3258 break;
3259 cursor += s->length * 16;
3260 }
3261 if (i == ONFI_EXT_SECTION_MAX) {
3262 pr_debug("We can not find the ECC section.\n");
3263 goto ext_out;
3264 }
3265
3266 /* get the info we want. */
3267 ecc = (struct onfi_ext_ecc_info *)cursor;
3268
4ae7d228
BN		 3269 if (!ecc->codeword_size) {
3270 pr_debug("Invalid codeword size\n");
3271 goto ext_out;
6dcbe0cd
HS		 3272 }
3273
4ae7d228
BN		 3274 chip->ecc_strength_ds = ecc->ecc_bits;
3275 chip->ecc_step_ds = 1 << ecc->codeword_size;
5cb13271 3276 ret = 0;
6dcbe0cd
HS		 3277
3278ext_out:
3279 kfree(ep);
3280 return ret;
3281}
3282
8429bb39
BN		 3283static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3284{
862eba51 3285 struct nand_chip *chip = mtd_to_nand(mtd);
8429bb39
BN		 3286 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3287
3288 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3289 feature);
3290}
3291
3292/*
3293 * Configure chip properties from Micron vendor-specific ONFI table
3294 */
3295static void nand_onfi_detect_micron(struct nand_chip *chip,
3296 struct nand_onfi_params *p)
3297{
3298 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3299
3300 if (le16_to_cpu(p->vendor_revision) < 1)
3301 return;
3302
3303 chip->read_retries = micron->read_retry_options;
3304 chip->setup_read_retry = nand_setup_read_retry_micron;
3305}
3306
6fb277ba 3307/*
8b6e50c9 3308 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 3309 */
3310static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 3311 int *busw)
6fb277ba
FF		 3312{
3313 struct nand_onfi_params *p = &chip->onfi_params;
bd9c6e99 3314 int i, j;
6fb277ba
FF		 3315 int val;
3316
7854d3f7 3317 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 3318 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3319 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3320 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3321 return 0;
3322
6fb277ba
FF		 3323 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3324 for (i = 0; i < 3; i++) {
bd9c6e99
BN		 3325 for (j = 0; j < sizeof(*p); j++)
3326 ((uint8_t *)p)[j] = chip->read_byte(mtd);
6fb277ba
FF		 3327 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3328 le16_to_cpu(p->crc)) {
6fb277ba
FF		 3329 break;
3330 }
3331 }
3332
c7f23a70
BN		 3333 if (i == 3) {
3334 pr_err("Could not find valid ONFI parameter page; aborting\n");
6fb277ba 3335 return 0;
c7f23a70 3336 }
6fb277ba 3337
8b6e50c9 3338 /* Check version */
6fb277ba 3339 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 3340 if (val & (1 << 5))
3341 chip->onfi_version = 23;
3342 else if (val & (1 << 4))
6fb277ba
FF		 3343 chip->onfi_version = 22;
3344 else if (val & (1 << 3))
3345 chip->onfi_version = 21;
3346 else if (val & (1 << 2))
3347 chip->onfi_version = 20;
b7b1a29d 3348 else if (val & (1 << 1))
6fb277ba 3349 chip->onfi_version = 10;
b7b1a29d
BN		 3350
3351 if (!chip->onfi_version) {
20171642 3352 pr_info("unsupported ONFI version: %d\n", val);
b7b1a29d
BN		 3353 return 0;
3354 }
6fb277ba
FF		 3355
3356 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3357 sanitize_string(p->model, sizeof(p->model));
3358 if (!mtd->name)
3359 mtd->name = p->model;
4355b70c 3360
6fb277ba 3361 mtd->writesize = le32_to_cpu(p->byte_per_page);
4355b70c
BN		 3362
3363 /*
3364 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3365 * (don't ask me who thought of this...). MTD assumes that these
3366 * dimensions will be power-of-2, so just truncate the remaining area.
3367 */
3368 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3369 mtd->erasesize *= mtd->writesize;
3370
6fb277ba 3371 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4355b70c
BN		 3372
3373 /* See erasesize comment */
3374 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3375 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
13fbd179 3376 chip->bits_per_cell = p->bits_per_cell;
e2985fc1
HS		 3377
3378 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
08c248fb 3379 *busw = NAND_BUSWIDTH_16;
e2985fc1
HS		 3380 else
3381 *busw = 0;
6fb277ba 3382
10c86bab
HS		 3383 if (p->ecc_bits != 0xff) {
3384 chip->ecc_strength_ds = p->ecc_bits;
3385 chip->ecc_step_ds = 512;
6dcbe0cd
HS		 3386 } else if (chip->onfi_version >= 21 &&
3387 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3388
3389 /*
3390 * The nand_flash_detect_ext_param_page() uses the
3391 * Change Read Column command which maybe not supported
3392 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3393 * now. We do not replace user supplied command function.
3394 */
3395 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3396 chip->cmdfunc = nand_command_lp;
3397
3398 /* The Extended Parameter Page is supported since ONFI 2.1. */
3399 if (nand_flash_detect_ext_param_page(mtd, chip, p))
c7f23a70
BN		 3400 pr_warn("Failed to detect ONFI extended param page\n");
3401 } else {
3402 pr_warn("Could not retrieve ONFI ECC requirements\n");
10c86bab
HS		 3403 }
3404
8429bb39
BN		 3405 if (p->jedec_id == NAND_MFR_MICRON)
3406 nand_onfi_detect_micron(chip, p);
3407
6fb277ba
FF		 3408 return 1;
3409}
3410
91361818
HS		 3411/*
3412 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3413 */
3414static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3415 int *busw)
3416{
3417 struct nand_jedec_params *p = &chip->jedec_params;
3418 struct jedec_ecc_info *ecc;
3419 int val;
3420 int i, j;
3421
3422 /* Try JEDEC for unknown chip or LP */
3423 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3424 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3425 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3426 chip->read_byte(mtd) != 'C')
3427 return 0;
3428
3429 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3430 for (i = 0; i < 3; i++) {
3431 for (j = 0; j < sizeof(*p); j++)
3432 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3433
3434 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3435 le16_to_cpu(p->crc))
3436 break;
3437 }
3438
3439 if (i == 3) {
3440 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3441 return 0;
3442 }
3443
3444 /* Check version */
3445 val = le16_to_cpu(p->revision);
3446 if (val & (1 << 2))
3447 chip->jedec_version = 10;
3448 else if (val & (1 << 1))
3449 chip->jedec_version = 1; /* vendor specific version */
3450
3451 if (!chip->jedec_version) {
3452 pr_info("unsupported JEDEC version: %d\n", val);
3453 return 0;
3454 }
3455
3456 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3457 sanitize_string(p->model, sizeof(p->model));
3458 if (!mtd->name)
3459 mtd->name = p->model;
3460
3461 mtd->writesize = le32_to_cpu(p->byte_per_page);
3462
3463 /* Please reference to the comment for nand_flash_detect_onfi. */
3464 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3465 mtd->erasesize *= mtd->writesize;
3466
3467 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3468
3469 /* Please reference to the comment for nand_flash_detect_onfi. */
3470 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3471 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3472 chip->bits_per_cell = p->bits_per_cell;
3473
3474 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3475 *busw = NAND_BUSWIDTH_16;
3476 else
3477 *busw = 0;
3478
3479 /* ECC info */
3480 ecc = &p->ecc_info[0];
3481
3482 if (ecc->codeword_size >= 9) {
3483 chip->ecc_strength_ds = ecc->ecc_bits;
3484 chip->ecc_step_ds = 1 << ecc->codeword_size;
3485 } else {
3486 pr_warn("Invalid codeword size\n");
3487 }
3488
3489 return 1;
3490}
3491
e3b88bd6
BN		 3492/*
3493 * nand_id_has_period - Check if an ID string has a given wraparound period
3494 * @id_data: the ID string
3495 * @arrlen: the length of the @id_data array
3496 * @period: the period of repitition
3497 *
3498 * Check if an ID string is repeated within a given sequence of bytes at
3499 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3500 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3501 * if the repetition has a period of @period; otherwise, returns zero.
3502 */
3503static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3504{
3505 int i, j;
3506 for (i = 0; i < period; i++)
3507 for (j = i + period; j < arrlen; j += period)
3508 if (id_data[i] != id_data[j])
3509 return 0;
3510 return 1;
3511}
3512
3513/*
3514 * nand_id_len - Get the length of an ID string returned by CMD_READID
3515 * @id_data: the ID string
3516 * @arrlen: the length of the @id_data array
3517
3518 * Returns the length of the ID string, according to known wraparound/trailing
3519 * zero patterns. If no pattern exists, returns the length of the array.
3520 */
3521static int nand_id_len(u8 *id_data, int arrlen)
3522{
3523 int last_nonzero, period;
3524
3525 /* Find last non-zero byte */
3526 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3527 if (id_data[last_nonzero])
3528 break;
3529
3530 /* All zeros */
3531 if (last_nonzero < 0)
3532 return 0;
3533
3534 /* Calculate wraparound period */
3535 for (period = 1; period < arrlen; period++)
3536 if (nand_id_has_period(id_data, arrlen, period))
3537 break;
3538
3539 /* There's a repeated pattern */
3540 if (period < arrlen)
3541 return period;
3542
3543 /* There are trailing zeros */
3544 if (last_nonzero < arrlen - 1)
3545 return last_nonzero + 1;
3546
3547 /* No pattern detected */
3548 return arrlen;
3549}
3550
7db906b7
HS		 3551/* Extract the bits of per cell from the 3rd byte of the extended ID */
3552static int nand_get_bits_per_cell(u8 cellinfo)
3553{
3554 int bits;
3555
3556 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3557 bits >>= NAND_CI_CELLTYPE_SHIFT;
3558 return bits + 1;
3559}
3560
fc09bbc0
BN		 3561/*
3562 * Many new NAND share similar device ID codes, which represent the size of the
3563 * chip. The rest of the parameters must be decoded according to generic or
3564 * manufacturer-specific "extended ID" decoding patterns.
3565 */
3566static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3567 u8 id_data[8], int *busw)
3568{
e3b88bd6 3569 int extid, id_len;
fc09bbc0 3570 /* The 3rd id byte holds MLC / multichip data */
7db906b7 3571 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
fc09bbc0
BN		 3572 /* The 4th id byte is the important one */
3573 extid = id_data[3];
3574
e3b88bd6
BN		 3575 id_len = nand_id_len(id_data, 8);
3576
fc09bbc0
BN		 3577 /*
3578 * Field definitions are in the following datasheets:
3579 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 3580 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 3581 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 3582 *
af451af4
BN		 3583 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3584 * ID to decide what to do.
fc09bbc0 3585 */
af451af4 3586 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
1d0ed69d 3587 !nand_is_slc(chip) && id_data[5] != 0x00) {
fc09bbc0
BN		 3588 /* Calc pagesize */
3589 mtd->writesize = 2048 << (extid & 0x03);
3590 extid >>= 2;
3591 /* Calc oobsize */
e2d3a35e 3592 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 3593 case 1:
3594 mtd->oobsize = 128;
3595 break;
3596 case 2:
3597 mtd->oobsize = 218;
3598 break;
3599 case 3:
3600 mtd->oobsize = 400;
3601 break;
e2d3a35e 3602 case 4:
fc09bbc0
BN		 3603 mtd->oobsize = 436;
3604 break;
e2d3a35e
BN		 3605 case 5:
3606 mtd->oobsize = 512;
3607 break;
3608 case 6:
e2d3a35e
BN		 3609 mtd->oobsize = 640;
3610 break;
94d04e82
HS		 3611 case 7:
3612 default: /* Other cases are "reserved" (unknown) */
3613 mtd->oobsize = 1024;
3614 break;
fc09bbc0
BN		 3615 }
3616 extid >>= 2;
3617 /* Calc blocksize */
3618 mtd->erasesize = (128 * 1024) <<
3619 (((extid >> 1) & 0x04) | (extid & 0x03));
3620 *busw = 0;
73ca392f 3621 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
1d0ed69d 3622 !nand_is_slc(chip)) {
73ca392f
BN		 3623 unsigned int tmp;
3624
3625 /* Calc pagesize */
3626 mtd->writesize = 2048 << (extid & 0x03);
3627 extid >>= 2;
3628 /* Calc oobsize */
3629 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3630 case 0:
3631 mtd->oobsize = 128;
3632 break;
3633 case 1:
3634 mtd->oobsize = 224;
3635 break;
3636 case 2:
3637 mtd->oobsize = 448;
3638 break;
3639 case 3:
3640 mtd->oobsize = 64;
3641 break;
3642 case 4:
3643 mtd->oobsize = 32;
3644 break;
3645 case 5:
3646 mtd->oobsize = 16;
3647 break;
3648 default:
3649 mtd->oobsize = 640;
3650 break;
3651 }
3652 extid >>= 2;
3653 /* Calc blocksize */
3654 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3655 if (tmp < 0x03)
3656 mtd->erasesize = (128 * 1024) << tmp;
3657 else if (tmp == 0x03)
3658 mtd->erasesize = 768 * 1024;
3659 else
3660 mtd->erasesize = (64 * 1024) << tmp;
3661 *busw = 0;
fc09bbc0
BN		 3662 } else {
3663 /* Calc pagesize */
3664 mtd->writesize = 1024 << (extid & 0x03);
3665 extid >>= 2;
3666 /* Calc oobsize */
3667 mtd->oobsize = (8 << (extid & 0x01)) *
3668 (mtd->writesize >> 9);
3669 extid >>= 2;
3670 /* Calc blocksize. Blocksize is multiples of 64KiB */
3671 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3672 extid >>= 2;
3673 /* Get buswidth information */
3674 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
60c67382
BN		 3675
3676 /*
3677 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3678 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3679 * follows:
3680 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3681 * 110b -> 24nm
3682 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3683 */
3684 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
1d0ed69d 3685 nand_is_slc(chip) &&
60c67382
BN		 3686 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3687 !(id_data[4] & 0x80) /* !BENAND */) {
3688 mtd->oobsize = 32 * mtd->writesize >> 9;
3689 }
3690
fc09bbc0
BN		 3691 }
3692}
3693
f23a481c
BN		 3694/*
3695 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3696 * decodes a matching ID table entry and assigns the MTD size parameters for
3697 * the chip.
3698 */
3699static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3700 struct nand_flash_dev *type, u8 id_data[8],
3701 int *busw)
3702{
3703 int maf_id = id_data[0];
3704
3705 mtd->erasesize = type->erasesize;
3706 mtd->writesize = type->pagesize;
3707 mtd->oobsize = mtd->writesize / 32;
3708 *busw = type->options & NAND_BUSWIDTH_16;
3709
1c195e90
HS		 3710 /* All legacy ID NAND are small-page, SLC */
3711 chip->bits_per_cell = 1;
3712
f23a481c
BN		 3713 /*
3714 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3715 * some Spansion chips have erasesize that conflicts with size
3716 * listed in nand_ids table.
3717 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3718 */
3719 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3720 && id_data[6] == 0x00 && id_data[7] == 0x00
3721 && mtd->writesize == 512) {
3722 mtd->erasesize = 128 * 1024;
3723 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3724 }
3725}
3726
7e74c2d7
BN		 3727/*
3728 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3729 * heuristic patterns using various detected parameters (e.g., manufacturer,
3730 * page size, cell-type information).
3731 */
3732static void nand_decode_bbm_options(struct mtd_info *mtd,
3733 struct nand_chip *chip, u8 id_data[8])
3734{
3735 int maf_id = id_data[0];
3736
3737 /* Set the bad block position */
3738 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3739 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3740 else
3741 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3742
3743 /*
3744 * Bad block marker is stored in the last page of each block on Samsung
3745 * and Hynix MLC devices; stored in first two pages of each block on
3746 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3747 * AMD/Spansion, and Macronix. All others scan only the first page.
3748 */
1d0ed69d 3749 if (!nand_is_slc(chip) &&
7e74c2d7
BN		 3750 (maf_id == NAND_MFR_SAMSUNG ||
3751 maf_id == NAND_MFR_HYNIX))
3752 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
1d0ed69d 3753 else if ((nand_is_slc(chip) &&
7e74c2d7
BN		 3754 (maf_id == NAND_MFR_SAMSUNG ||
3755 maf_id == NAND_MFR_HYNIX ||
3756 maf_id == NAND_MFR_TOSHIBA ||
3757 maf_id == NAND_MFR_AMD ||
3758 maf_id == NAND_MFR_MACRONIX)) ||
3759 (mtd->writesize == 2048 &&
3760 maf_id == NAND_MFR_MICRON))
3761 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3762}
3763
ec6e87e3
HS		 3764static inline bool is_full_id_nand(struct nand_flash_dev *type)
3765{
3766 return type->id_len;
3767}
3768
3769static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3770 struct nand_flash_dev *type, u8 *id_data, int *busw)
3771{
3772 if (!strncmp(type->id, id_data, type->id_len)) {
3773 mtd->writesize = type->pagesize;
3774 mtd->erasesize = type->erasesize;
3775 mtd->oobsize = type->oobsize;
3776
7db906b7 3777 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
ec6e87e3
HS		 3778 chip->chipsize = (uint64_t)type->chipsize << 20;
3779 chip->options |= type->options;
57219342
HS		 3780 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3781 chip->ecc_step_ds = NAND_ECC_STEP(type);
57a94e24
BB		 3782 chip->onfi_timing_mode_default =
3783 type->onfi_timing_mode_default;
ec6e87e3
HS		 3784
3785 *busw = type->options & NAND_BUSWIDTH_16;
3786
092b6a1d
CZ		 3787 if (!mtd->name)
3788 mtd->name = type->name;
3789
ec6e87e3
HS		 3790 return true;
3791 }
3792 return false;
3793}
3794
7aa65bfd 3795/*
8b6e50c9 3796 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3797 */
3798static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3799 struct nand_chip *chip,
7351d3a5 3800 int *maf_id, int *dev_id,
5e81e88a 3801 struct nand_flash_dev *type)
7aa65bfd 3802{
bb77082f 3803 int busw;
d1e1f4e4 3804 int i, maf_idx;
426c457a 3805 u8 id_data[8];
1da177e4
LT		 3806
3807 /* Select the device */
ace4dfee 3808 chip->select_chip(mtd, 0);
1da177e4 3809
ef89a880
KB		 3810 /*
3811 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3812 * after power-up.
ef89a880
KB		 3813 */
3814 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3815
1da177e4 3816 /* Send the command for reading device ID */
ace4dfee 3817 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3818
3819 /* Read manufacturer and device IDs */
ace4dfee 3820 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3821 *dev_id = chip->read_byte(mtd);
1da177e4 3822
8b6e50c9
BN		 3823 /*
3824 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3825 * interface concerns can cause random data which looks like a
3826 * possibly credible NAND flash to appear. If the two results do
3827 * not match, ignore the device completely.
3828 */
3829
3830 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3831
4aef9b78
BN		 3832 /* Read entire ID string */
3833 for (i = 0; i < 8; i++)
426c457a 3834 id_data[i] = chip->read_byte(mtd);
ed8165c7 3835
d1e1f4e4 3836 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
20171642 3837 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
d0370219 3838 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3839 return ERR_PTR(-ENODEV);
3840 }
3841
7aa65bfd 3842 if (!type)
5e81e88a
DW		 3843 type = nand_flash_ids;
3844
ec6e87e3
HS		 3845 for (; type->name != NULL; type++) {
3846 if (is_full_id_nand(type)) {
3847 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3848 goto ident_done;
3849 } else if (*dev_id == type->dev_id) {
db5b09f6 3850 break;
ec6e87e3
HS		 3851 }
3852 }
5e81e88a 3853
d1e1f4e4
FF		 3854 chip->onfi_version = 0;
3855 if (!type->name || !type->pagesize) {
35fc5195 3856 /* Check if the chip is ONFI compliant */
47450b35 3857 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3858 goto ident_done;
91361818
HS		 3859
3860 /* Check if the chip is JEDEC compliant */
3861 if (nand_flash_detect_jedec(mtd, chip, &busw))
3862 goto ident_done;
d1e1f4e4
FF		 3863 }
3864
5e81e88a 3865 if (!type->name)
7aa65bfd
TG		 3866 return ERR_PTR(-ENODEV);
3867
ba0251fe
TG		 3868 if (!mtd->name)
3869 mtd->name = type->name;
3870
69423d99 3871 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3872
a7f5ba40 3873 if (!type->pagesize) {
fc09bbc0
BN		 3874 /* Decode parameters from extended ID */
3875 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3876 } else {
f23a481c 3877 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3878 }
bf7a01bf
BN		 3879 /* Get chip options */
3880 chip->options |= type->options;
d1e1f4e4 3881
8b6e50c9
BN		 3882 /*
3883 * Check if chip is not a Samsung device. Do not clear the
3884 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3885 */
3886 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3887 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3888ident_done:
3889
7aa65bfd 3890 /* Try to identify manufacturer */
9a909867 3891 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3892 if (nand_manuf_ids[maf_idx].id == *maf_id)
3893 break;
3894 }
0ea4a755 3895
64b37b2a
MC		 3896 if (chip->options & NAND_BUSWIDTH_AUTO) {
3897 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3898 chip->options |= busw;
3899 nand_set_defaults(chip, busw);
3900 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3901 /*
3902 * Check, if buswidth is correct. Hardware drivers should set
3903 * chip correct!
3904 */
20171642
EG		 3905 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3906 *maf_id, *dev_id);
3907 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3908 pr_warn("bus width %d instead %d bit\n",
d0370219
BN		 3909 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3910 busw ? 16 : 8);
7aa65bfd
TG		 3911 return ERR_PTR(-EINVAL);
3912 }
61b03bd7 3913
7e74c2d7
BN		 3914 nand_decode_bbm_options(mtd, chip, id_data);
3915
7aa65bfd 3916 /* Calculate the address shift from the page size */
ace4dfee 3917 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3918 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3919 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3920
ace4dfee 3921 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3922 ffs(mtd->erasesize) - 1;
69423d99
AH		 3923 if (chip->chipsize & 0xffffffff)
3924 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3925 else {
3926 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3927 chip->chip_shift += 32 - 1;
3928 }
1da177e4 3929
26d9be11 3930 chip->badblockbits = 8;
49c50b97 3931 chip->erase = single_erase;
7aa65bfd 3932
8b6e50c9 3933 /* Do not replace user supplied command function! */
ace4dfee
TG		 3934 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3935 chip->cmdfunc = nand_command_lp;
7aa65bfd 3936
20171642
EG		 3937 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3938 *maf_id, *dev_id);
ffdac6cd
HS		 3939
3940 if (chip->onfi_version)
3941 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3942 chip->onfi_params.model);
3943 else if (chip->jedec_version)
3944 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3945 chip->jedec_params.model);
3946 else
3947 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3948 type->name);
3949
3755a991 3950 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3723e93c 3951 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3755a991 3952 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3953 return type;
3954}
3955
7194a29a 3956static int nand_dt_init(struct nand_chip *chip)
5844feea 3957{
7194a29a 3958 struct device_node *dn = nand_get_flash_node(chip);
79082457 3959 int ecc_mode, ecc_algo, ecc_strength, ecc_step;
5844feea 3960
7194a29a
BB		 3961 if (!dn)
3962 return 0;
3963
5844feea
BN		 3964 if (of_get_nand_bus_width(dn) == 16)
3965 chip->options |= NAND_BUSWIDTH_16;
3966
3967 if (of_get_nand_on_flash_bbt(dn))
3968 chip->bbt_options |= NAND_BBT_USE_FLASH;
3969
3970 ecc_mode = of_get_nand_ecc_mode(dn);
79082457 3971 ecc_algo = of_get_nand_ecc_algo(dn);
5844feea
BN		 3972 ecc_strength = of_get_nand_ecc_strength(dn);
3973 ecc_step = of_get_nand_ecc_step_size(dn);
3974
3975 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
3976 (!(ecc_step >= 0) && ecc_strength >= 0)) {
3977 pr_err("must set both strength and step size in DT\n");
3978 return -EINVAL;
3979 }
3980
3981 if (ecc_mode >= 0)
3982 chip->ecc.mode = ecc_mode;
3983
79082457
RM		 3984 if (ecc_algo >= 0)
3985 chip->ecc.algo = ecc_algo;
3986
5844feea
BN		 3987 if (ecc_strength >= 0)
3988 chip->ecc.strength = ecc_strength;
3989
3990 if (ecc_step > 0)
3991 chip->ecc.size = ecc_step;
3992
3993 return 0;
3994}
3995
7aa65bfd 3996/**
3b85c321 3997 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3998 * @mtd: MTD device structure
3999 * @maxchips: number of chips to scan for
4000 * @table: alternative NAND ID table
7aa65bfd 4001 *
8b6e50c9
BN		 4002 * This is the first phase of the normal nand_scan() function. It reads the
4003 * flash ID and sets up MTD fields accordingly.
7aa65bfd 4004 *
3b85c321 4005 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 4006 */
5e81e88a
DW		 4007int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4008 struct nand_flash_dev *table)
7aa65bfd 4009{
bb77082f 4010 int i, nand_maf_id, nand_dev_id;
862eba51 4011 struct nand_chip *chip = mtd_to_nand(mtd);
7aa65bfd 4012 struct nand_flash_dev *type;
5844feea
BN		 4013 int ret;
4014
7194a29a
BB		 4015 ret = nand_dt_init(chip);
4016 if (ret)
4017 return ret;
7aa65bfd 4018
f7a8e38f
BN		 4019 if (!mtd->name && mtd->dev.parent)
4020 mtd->name = dev_name(mtd->dev.parent);
4021
7aa65bfd 4022 /* Set the default functions */
bb77082f 4023 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
7aa65bfd
TG		 4024
4025 /* Read the flash type */
bb77082f
CZ		 4026 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
4027 &nand_dev_id, table);
7aa65bfd
TG		 4028
4029 if (IS_ERR(type)) {
b1c6e6db 4030 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 4031 pr_warn("No NAND device found\n");
ace4dfee 4032 chip->select_chip(mtd, -1);
7aa65bfd 4033 return PTR_ERR(type);
1da177e4
LT		 4034 }
4035
07300164
HS		 4036 chip->select_chip(mtd, -1);
4037
7aa65bfd 4038 /* Check for a chip array */
e0c7d767 4039 for (i = 1; i < maxchips; i++) {
ace4dfee 4040 chip->select_chip(mtd, i);
ef89a880
KB		 4041 /* See comment in nand_get_flash_type for reset */
4042 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 4043 /* Send the command for reading device ID */
ace4dfee 4044 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 4045 /* Read manufacturer and device IDs */
ace4dfee 4046 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 4047 nand_dev_id != chip->read_byte(mtd)) {
4048 chip->select_chip(mtd, -1);
1da177e4 4049 break;
07300164
HS		 4050 }
4051 chip->select_chip(mtd, -1);
1da177e4
LT		 4052 }
4053 if (i > 1)
20171642 4054 pr_info("%d chips detected\n", i);
61b03bd7 4055
1da177e4 4056 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 4057 chip->numchips = i;
4058 mtd->size = i * chip->chipsize;
7aa65bfd 4059
3b85c321
DW		 4060 return 0;
4061}
7351d3a5 4062EXPORT_SYMBOL(nand_scan_ident);
3b85c321 4063
67a9ad9b
EG		 4064/*
4065 * Check if the chip configuration meet the datasheet requirements.
4066
4067 * If our configuration corrects A bits per B bytes and the minimum
4068 * required correction level is X bits per Y bytes, then we must ensure
4069 * both of the following are true:
4070 *
4071 * (1) A / B >= X / Y
4072 * (2) A >= X
4073 *
4074 * Requirement (1) ensures we can correct for the required bitflip density.
4075 * Requirement (2) ensures we can correct even when all bitflips are clumped
4076 * in the same sector.
4077 */
4078static bool nand_ecc_strength_good(struct mtd_info *mtd)
4079{
862eba51 4080 struct nand_chip *chip = mtd_to_nand(mtd);
67a9ad9b
EG		 4081 struct nand_ecc_ctrl *ecc = &chip->ecc;
4082 int corr, ds_corr;
4083
4084 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4085 /* Not enough information */
4086 return true;
4087
4088 /*
4089 * We get the number of corrected bits per page to compare
4090 * the correction density.
4091 */
4092 corr = (mtd->writesize * ecc->strength) / ecc->size;
4093 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4094
4095 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4096}
3b85c321
DW		 4097
4098/**
4099 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 4100 * @mtd: MTD device structure
3b85c321 4101 *
8b6e50c9
BN		 4102 * This is the second phase of the normal nand_scan() function. It fills out
4103 * all the uninitialized function pointers with the defaults and scans for a
4104 * bad block table if appropriate.
3b85c321
DW		 4105 */
4106int nand_scan_tail(struct mtd_info *mtd)
4107{
4108 int i;
862eba51 4109 struct nand_chip *chip = mtd_to_nand(mtd);
97de79e0 4110 struct nand_ecc_ctrl *ecc = &chip->ecc;
f02ea4e6 4111 struct nand_buffers *nbuf;
11eaf6df 4112 int ret;
3b85c321 4113
e2414f4c 4114 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
11eaf6df
EG		 4115 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4116 !(chip->bbt_options & NAND_BBT_USE_FLASH)))
4117 return -EINVAL;
e2414f4c 4118
f02ea4e6
HS		 4119 if (!(chip->options & NAND_OWN_BUFFERS)) {
4120 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4121 + mtd->oobsize * 3, GFP_KERNEL);
4122 if (!nbuf)
4123 return -ENOMEM;
4124 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4125 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4126 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4127
4128 chip->buffers = nbuf;
4129 } else {
4130 if (!chip->buffers)
4131 return -ENOMEM;
4132 }
4bf63fcb 4133
7dcdcbef 4134 /* Set the internal oob buffer location, just after the page data */
784f4d5e 4135 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 4136
7aa65bfd 4137 /*
8b6e50c9 4138 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 4139 */
97de79e0 4140 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 4141 switch (mtd->oobsize) {
1da177e4 4142 case 8:
97de79e0 4143 ecc->layout = &nand_oob_8;
1da177e4
LT		 4144 break;
4145 case 16:
97de79e0 4146 ecc->layout = &nand_oob_16;
1da177e4
LT		 4147 break;
4148 case 64:
97de79e0 4149 ecc->layout = &nand_oob_64;
1da177e4 4150 break;
81ec5364 4151 case 128:
97de79e0 4152 ecc->layout = &nand_oob_128;
81ec5364 4153 break;
1da177e4 4154 default:
11eaf6df
EG		 4155 WARN(1, "No oob scheme defined for oobsize %d\n",
4156 mtd->oobsize);
4157 ret = -EINVAL;
4158 goto err_free;
1da177e4
LT		 4159 }
4160 }
61b03bd7 4161
956e944c
DW		 4162 if (!chip->write_page)
4163 chip->write_page = nand_write_page;
4164
61b03bd7 4165 /*
8b6e50c9 4166 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 4167 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 4168 */
956e944c 4169
97de79e0 4170 switch (ecc->mode) {
6e0cb135
SN		 4171 case NAND_ECC_HW_OOB_FIRST:
4172 /* Similar to NAND_ECC_HW, but a separate read_page handle */
97de79e0 4173 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
11eaf6df
EG		 4174 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4175 ret = -EINVAL;
4176 goto err_free;
6e0cb135 4177 }
97de79e0
HS		 4178 if (!ecc->read_page)
4179 ecc->read_page = nand_read_page_hwecc_oob_first;
6e0cb135 4180
6dfc6d25 4181 case NAND_ECC_HW:
8b6e50c9 4182 /* Use standard hwecc read page function? */
97de79e0
HS		 4183 if (!ecc->read_page)
4184 ecc->read_page = nand_read_page_hwecc;
4185 if (!ecc->write_page)
4186 ecc->write_page = nand_write_page_hwecc;
4187 if (!ecc->read_page_raw)
4188 ecc->read_page_raw = nand_read_page_raw;
4189 if (!ecc->write_page_raw)
4190 ecc->write_page_raw = nand_write_page_raw;
4191 if (!ecc->read_oob)
4192 ecc->read_oob = nand_read_oob_std;
4193 if (!ecc->write_oob)
4194 ecc->write_oob = nand_write_oob_std;
4195 if (!ecc->read_subpage)
4196 ecc->read_subpage = nand_read_subpage;
44991b3d 4197 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
97de79e0 4198 ecc->write_subpage = nand_write_subpage_hwecc;
f5bbdacc 4199
6dfc6d25 4200 case NAND_ECC_HW_SYNDROME:
97de79e0
HS		 4201 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4202 (!ecc->read_page ||
4203 ecc->read_page == nand_read_page_hwecc ||
4204 !ecc->write_page ||
4205 ecc->write_page == nand_write_page_hwecc)) {
11eaf6df
EG		 4206 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4207 ret = -EINVAL;
4208 goto err_free;
6dfc6d25 4209 }
8b6e50c9 4210 /* Use standard syndrome read/write page function? */
97de79e0
HS		 4211 if (!ecc->read_page)
4212 ecc->read_page = nand_read_page_syndrome;
4213 if (!ecc->write_page)
4214 ecc->write_page = nand_write_page_syndrome;
4215 if (!ecc->read_page_raw)
4216 ecc->read_page_raw = nand_read_page_raw_syndrome;
4217 if (!ecc->write_page_raw)
4218 ecc->write_page_raw = nand_write_page_raw_syndrome;
4219 if (!ecc->read_oob)
4220 ecc->read_oob = nand_read_oob_syndrome;
4221 if (!ecc->write_oob)
4222 ecc->write_oob = nand_write_oob_syndrome;
4223
4224 if (mtd->writesize >= ecc->size) {
4225 if (!ecc->strength) {
11eaf6df
EG		 4226 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4227 ret = -EINVAL;
4228 goto err_free;
e2788c98 4229 }
6dfc6d25 4230 break;
e2788c98 4231 }
2ac63d90
RM		 4232 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4233 ecc->size, mtd->writesize);
97de79e0 4234 ecc->mode = NAND_ECC_SOFT;
61b03bd7 4235
6dfc6d25 4236 case NAND_ECC_SOFT:
97de79e0
HS		 4237 ecc->calculate = nand_calculate_ecc;
4238 ecc->correct = nand_correct_data;
4239 ecc->read_page = nand_read_page_swecc;
4240 ecc->read_subpage = nand_read_subpage;
4241 ecc->write_page = nand_write_page_swecc;
4242 ecc->read_page_raw = nand_read_page_raw;
4243 ecc->write_page_raw = nand_write_page_raw;
4244 ecc->read_oob = nand_read_oob_std;
4245 ecc->write_oob = nand_write_oob_std;
4246 if (!ecc->size)
4247 ecc->size = 256;
4248 ecc->bytes = 3;
4249 ecc->strength = 1;
1da177e4 4250 break;
61b03bd7 4251
193bd400
ID		 4252 case NAND_ECC_SOFT_BCH:
4253 if (!mtd_nand_has_bch()) {
11eaf6df
EG		 4254 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4255 ret = -EINVAL;
4256 goto err_free;
193bd400 4257 }
97de79e0
HS		 4258 ecc->calculate = nand_bch_calculate_ecc;
4259 ecc->correct = nand_bch_correct_data;
4260 ecc->read_page = nand_read_page_swecc;
4261 ecc->read_subpage = nand_read_subpage;
4262 ecc->write_page = nand_write_page_swecc;
4263 ecc->read_page_raw = nand_read_page_raw;
4264 ecc->write_page_raw = nand_write_page_raw;
4265 ecc->read_oob = nand_read_oob_std;
4266 ecc->write_oob = nand_write_oob_std;
193bd400 4267 /*
e0377cde
AS		 4268 * Board driver should supply ecc.size and ecc.strength values
4269 * to select how many bits are correctable. Otherwise, default
4270 * to 4 bits for large page devices.
193bd400 4271 */
97de79e0
HS		 4272 if (!ecc->size && (mtd->oobsize >= 64)) {
4273 ecc->size = 512;
e0377cde 4274 ecc->strength = 4;
193bd400 4275 }
e0377cde
AS		 4276
4277 /* See nand_bch_init() for details. */
a8c65d50
BB		 4278 ecc->bytes = 0;
4279 ecc->priv = nand_bch_init(mtd);
97de79e0 4280 if (!ecc->priv) {
11eaf6df
EG		 4281 WARN(1, "BCH ECC initialization failed!\n");
4282 ret = -EINVAL;
4283 goto err_free;
193bd400
ID		 4284 }
4285 break;
4286
61b03bd7 4287 case NAND_ECC_NONE:
2ac63d90 4288 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
97de79e0
HS		 4289 ecc->read_page = nand_read_page_raw;
4290 ecc->write_page = nand_write_page_raw;
4291 ecc->read_oob = nand_read_oob_std;
4292 ecc->read_page_raw = nand_read_page_raw;
4293 ecc->write_page_raw = nand_write_page_raw;
4294 ecc->write_oob = nand_write_oob_std;
4295 ecc->size = mtd->writesize;
4296 ecc->bytes = 0;
4297 ecc->strength = 0;
1da177e4 4298 break;
956e944c 4299
1da177e4 4300 default:
11eaf6df
EG		 4301 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
4302 ret = -EINVAL;
4303 goto err_free;
1da177e4 4304 }
61b03bd7 4305
9ce244b3 4306 /* For many systems, the standard OOB write also works for raw */
97de79e0
HS		 4307 if (!ecc->read_oob_raw)
4308 ecc->read_oob_raw = ecc->read_oob;
4309 if (!ecc->write_oob_raw)
4310 ecc->write_oob_raw = ecc->write_oob;
9ce244b3 4311
5bd34c09
TG		 4312 /*
4313 * The number of bytes available for a client to place data into
8b6e50c9 4314 * the out of band area.
5bd34c09 4315 */
f5b8aa78
BB		 4316 mtd->oobavail = 0;
4317 if (ecc->layout) {
4318 for (i = 0; ecc->layout->oobfree[i].length; i++)
4319 mtd->oobavail += ecc->layout->oobfree[i].length;
4320 }
5bd34c09 4321
54c39e9b
TP		 4322 /* ECC sanity check: warn if it's too weak */
4323 if (!nand_ecc_strength_good(mtd))
4324 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4325 mtd->name);
67a9ad9b 4326
7aa65bfd
TG		 4327 /*
4328 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 4329 * mode.
7aa65bfd 4330 */
97de79e0
HS		 4331 ecc->steps = mtd->writesize / ecc->size;
4332 if (ecc->steps * ecc->size != mtd->writesize) {
11eaf6df
EG		 4333 WARN(1, "Invalid ECC parameters\n");
4334 ret = -EINVAL;
4335 goto err_free;
1da177e4 4336 }
97de79e0 4337 ecc->total = ecc->steps * ecc->bytes;
61b03bd7 4338
8b6e50c9 4339 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
1d0ed69d 4340 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
97de79e0 4341 switch (ecc->steps) {
29072b96
TG		 4342 case 2:
4343 mtd->subpage_sft = 1;
4344 break;
4345 case 4:
4346 case 8:
81ec5364 4347 case 16:
29072b96
TG		 4348 mtd->subpage_sft = 2;
4349 break;
4350 }
4351 }
4352 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4353
04bbd0ea 4354 /* Initialize state */
ace4dfee 4355 chip->state = FL_READY;
1da177e4 4356
1da177e4 4357 /* Invalidate the pagebuffer reference */
ace4dfee 4358 chip->pagebuf = -1;
1da177e4 4359
a5ff4f10 4360 /* Large page NAND with SOFT_ECC should support subpage reads */
4007e2d1
RL		 4361 switch (ecc->mode) {
4362 case NAND_ECC_SOFT:
4363 case NAND_ECC_SOFT_BCH:
4364 if (chip->page_shift > 9)
4365 chip->options |= NAND_SUBPAGE_READ;
4366 break;
4367
4368 default:
4369 break;
4370 }
a5ff4f10 4371
1da177e4 4372 /* Fill in remaining MTD driver data */
963d1c28 4373 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
93edbad6
ML		 4374 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4375 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 4376 mtd->_erase = nand_erase;
4377 mtd->_point = NULL;
4378 mtd->_unpoint = NULL;
4379 mtd->_read = nand_read;
4380 mtd->_write = nand_write;
4381 mtd->_panic_write = panic_nand_write;
4382 mtd->_read_oob = nand_read_oob;
4383 mtd->_write_oob = nand_write_oob;
4384 mtd->_sync = nand_sync;
4385 mtd->_lock = NULL;
4386 mtd->_unlock = NULL;
4387 mtd->_suspend = nand_suspend;
4388 mtd->_resume = nand_resume;
72ea4036 4389 mtd->_reboot = nand_shutdown;
8471bb73 4390 mtd->_block_isreserved = nand_block_isreserved;
3c3c10bb
AB		 4391 mtd->_block_isbad = nand_block_isbad;
4392 mtd->_block_markbad = nand_block_markbad;
cbcab65a 4393 mtd->writebufsize = mtd->writesize;
1da177e4 4394
6a918bad 4395 /* propagate ecc info to mtd_info */
97de79e0
HS		 4396 mtd->ecclayout = ecc->layout;
4397 mtd->ecc_strength = ecc->strength;
4398 mtd->ecc_step_size = ecc->size;
ea3b2ea2
SL		 4399 /*
4400 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4401 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4402 * properly set.
4403 */
4404 if (!mtd->bitflip_threshold)
240181fd 4405 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
1da177e4 4406
0040bf38 4407 /* Check, if we should skip the bad block table scan */
ace4dfee 4408 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 4409 return 0;
1da177e4
LT		 4410
4411 /* Build bad block table */
ace4dfee 4412 return chip->scan_bbt(mtd);
11eaf6df
EG		 4413err_free:
4414 if (!(chip->options & NAND_OWN_BUFFERS))
4415 kfree(chip->buffers);
4416 return ret;
1da177e4 4417}
7351d3a5 4418EXPORT_SYMBOL(nand_scan_tail);
1da177e4 4419
8b6e50c9
BN		 4420/*
4421 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 4422 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 4423 * to call us from in-kernel code if the core NAND support is modular.
4424 */
3b85c321
DW		 4425#ifdef MODULE
4426#define caller_is_module() (1)
4427#else
4428#define caller_is_module() \
a6e6abd5 4429 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 4430#endif
4431
4432/**
4433 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4434 * @mtd: MTD device structure
4435 * @maxchips: number of chips to scan for
3b85c321 4436 *
8b6e50c9
BN		 4437 * This fills out all the uninitialized function pointers with the defaults.
4438 * The flash ID is read and the mtd/chip structures are filled with the
4439 * appropriate values. The mtd->owner field must be set to the module of the
4440 * caller.
3b85c321
DW		 4441 */
4442int nand_scan(struct mtd_info *mtd, int maxchips)
4443{
4444 int ret;
4445
4446 /* Many callers got this wrong, so check for it for a while... */
4447 if (!mtd->owner && caller_is_module()) {
d0370219 4448 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 4449 BUG();
4450 }
4451
5e81e88a 4452 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 4453 if (!ret)
4454 ret = nand_scan_tail(mtd);
4455 return ret;
4456}
7351d3a5 4457EXPORT_SYMBOL(nand_scan);
3b85c321 4458
1da177e4 4459/**
61b03bd7 4460 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 4461 * @mtd: MTD device structure
4462 */
e0c7d767 4463void nand_release(struct mtd_info *mtd)
1da177e4 4464{
862eba51 4465 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 4466
193bd400
ID		 4467 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4468 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4469
5ffcaf3d 4470 mtd_device_unregister(mtd);
1da177e4 4471
fa671646 4472 /* Free bad block table memory */
ace4dfee 4473 kfree(chip->bbt);
4bf63fcb
DW		 4474 if (!(chip->options & NAND_OWN_BUFFERS))
4475 kfree(chip->buffers);
58373ff0
BN		 4476
4477 /* Free bad block descriptor memory */
4478 if (chip->badblock_pattern && chip->badblock_pattern->options
4479 & NAND_BBT_DYNAMICSTRUCT)
4480 kfree(chip->badblock_pattern);
1da177e4 4481}
e0c7d767 4482EXPORT_SYMBOL_GPL(nand_release);
8fe833c1 4483
e0c7d767 4484MODULE_LICENSE("GPL");
7351d3a5
FF		 4485MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4486MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 4487MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
This page took 1.104186 seconds and 5 git commands to generate.