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Merge branch 'clk/mxs-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6...
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 24 * if we have HW ECC support.
1da177e4
LT		 25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4 50#include <linux/mtd/partitions.h>
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
ace4dfee 96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 97 int new_state);
1da177e4 98
8593fbc6
TG		 99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
d470a97c 102/*
8e87d782 103 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
6fe5a6ac
VS		 108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 116 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 122 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 123 ret = -EINVAL;
124 }
125
6fe5a6ac
VS		 126 return ret;
127}
128
1da177e4
LT		 129/**
130 * nand_release_device - [GENERIC] release chip
8b6e50c9 131 * @mtd: MTD device structure
61b03bd7 132 *
8b6e50c9 133 * Deselect, release chip lock and wake up anyone waiting on the device.
1da177e4 134 */
e0c7d767 135static void nand_release_device(struct mtd_info *mtd)
1da177e4 136{
ace4dfee 137 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 138
139 /* De-select the NAND device */
ace4dfee 140 chip->select_chip(mtd, -1);
0dfc6246 141
a36ed299 142 /* Release the controller and the chip */
ace4dfee
TG		 143 spin_lock(&chip->controller->lock);
144 chip->controller->active = NULL;
145 chip->state = FL_READY;
146 wake_up(&chip->controller->wq);
147 spin_unlock(&chip->controller->lock);
1da177e4
LT		 148}
149
150/**
151 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 152 * @mtd: MTD device structure
1da177e4 153 *
7854d3f7 154 * Default read function for 8bit buswidth
1da177e4 155 */
58dd8f2b 156static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 157{
ace4dfee
TG		 158 struct nand_chip *chip = mtd->priv;
159 return readb(chip->IO_ADDR_R);
1da177e4
LT		 160}
161
1da177e4
LT		 162/**
163 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
7854d3f7 164 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 165 * @mtd: MTD device structure
1da177e4 166 *
7854d3f7
BN		 167 * Default read function for 16bit buswidth with endianness conversion.
168 *
1da177e4 169 */
58dd8f2b 170static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 171{
ace4dfee
TG		 172 struct nand_chip *chip = mtd->priv;
173 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 174}
175
1da177e4
LT		 176/**
177 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 178 * @mtd: MTD device structure
1da177e4 179 *
7854d3f7 180 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 181 */
182static u16 nand_read_word(struct mtd_info *mtd)
183{
ace4dfee
TG		 184 struct nand_chip *chip = mtd->priv;
185 return readw(chip->IO_ADDR_R);
1da177e4
LT		 186}
187
1da177e4
LT		 188/**
189 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 190 * @mtd: MTD device structure
191 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 192 *
193 * Default select function for 1 chip devices.
194 */
ace4dfee 195static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 196{
ace4dfee
TG		 197 struct nand_chip *chip = mtd->priv;
198
199 switch (chipnr) {
1da177e4 200 case -1:
ace4dfee 201 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 202 break;
203 case 0:
1da177e4
LT		 204 break;
205
206 default:
207 BUG();
208 }
209}
210
211/**
212 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 213 * @mtd: MTD device structure
214 * @buf: data buffer
215 * @len: number of bytes to write
1da177e4 216 *
7854d3f7 217 * Default write function for 8bit buswidth.
1da177e4 218 */
58dd8f2b 219static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 220{
221 int i;
ace4dfee 222 struct nand_chip *chip = mtd->priv;
1da177e4 223
e0c7d767 224 for (i = 0; i < len; i++)
ace4dfee 225 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 226}
227
228/**
61b03bd7 229 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
1da177e4 233 *
7854d3f7 234 * Default read function for 8bit buswidth.
1da177e4 235 */
58dd8f2b 236static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 237{
238 int i;
ace4dfee 239 struct nand_chip *chip = mtd->priv;
1da177e4 240
e0c7d767 241 for (i = 0; i < len; i++)
ace4dfee 242 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 243}
244
245/**
61b03bd7 246 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 247 * @mtd: MTD device structure
248 * @buf: buffer containing the data to compare
249 * @len: number of bytes to compare
1da177e4 250 *
7854d3f7 251 * Default verify function for 8bit buswidth.
1da177e4 252 */
58dd8f2b 253static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 254{
255 int i;
ace4dfee 256 struct nand_chip *chip = mtd->priv;
1da177e4 257
e0c7d767 258 for (i = 0; i < len; i++)
ace4dfee 259 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 260 return -EFAULT;
1da177e4
LT		 261 return 0;
262}
263
264/**
265 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 266 * @mtd: MTD device structure
267 * @buf: data buffer
268 * @len: number of bytes to write
1da177e4 269 *
7854d3f7 270 * Default write function for 16bit buswidth.
1da177e4 271 */
58dd8f2b 272static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 273{
274 int i;
ace4dfee 275 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 276 u16 *p = (u16 *) buf;
277 len >>= 1;
61b03bd7 278
e0c7d767 279 for (i = 0; i < len; i++)
ace4dfee 280 writew(p[i], chip->IO_ADDR_W);
61b03bd7 281
1da177e4
LT		 282}
283
284/**
61b03bd7 285 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 286 * @mtd: MTD device structure
287 * @buf: buffer to store date
288 * @len: number of bytes to read
1da177e4 289 *
7854d3f7 290 * Default read function for 16bit buswidth.
1da177e4 291 */
58dd8f2b 292static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 293{
294 int i;
ace4dfee 295 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 296 u16 *p = (u16 *) buf;
297 len >>= 1;
298
e0c7d767 299 for (i = 0; i < len; i++)
ace4dfee 300 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 301}
302
303/**
61b03bd7 304 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 305 * @mtd: MTD device structure
306 * @buf: buffer containing the data to compare
307 * @len: number of bytes to compare
1da177e4 308 *
7854d3f7 309 * Default verify function for 16bit buswidth.
1da177e4 310 */
58dd8f2b 311static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 312{
313 int i;
ace4dfee 314 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 315 u16 *p = (u16 *) buf;
316 len >>= 1;
317
e0c7d767 318 for (i = 0; i < len; i++)
ace4dfee 319 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 320 return -EFAULT;
321
322 return 0;
323}
324
325/**
326 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 327 * @mtd: MTD device structure
328 * @ofs: offset from device start
329 * @getchip: 0, if the chip is already selected
1da177e4 330 *
61b03bd7 331 * Check, if the block is bad.
1da177e4
LT		 332 */
333static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
334{
cdbec050 335 int page, chipnr, res = 0, i = 0;
ace4dfee 336 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 337 u16 bad;
338
5fb1549d 339 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 340 ofs += mtd->erasesize - mtd->writesize;
341
1a12f46a
TK		 342 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
343
1da177e4 344 if (getchip) {
ace4dfee 345 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 346
ace4dfee 347 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 348
349 /* Select the NAND device */
ace4dfee 350 chip->select_chip(mtd, chipnr);
1a12f46a 351 }
1da177e4 352
cdbec050
BN		 353 do {
354 if (chip->options & NAND_BUSWIDTH_16) {
355 chip->cmdfunc(mtd, NAND_CMD_READOOB,
356 chip->badblockpos & 0xFE, page);
357 bad = cpu_to_le16(chip->read_word(mtd));
358 if (chip->badblockpos & 0x1)
359 bad >>= 8;
360 else
361 bad &= 0xFF;
362 } else {
363 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
364 page);
365 bad = chip->read_byte(mtd);
366 }
367
368 if (likely(chip->badblockbits == 8))
369 res = bad != 0xFF;
e0b58d0a 370 else
cdbec050
BN		 371 res = hweight8(bad) < chip->badblockbits;
372 ofs += mtd->writesize;
373 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
374 i++;
375 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 376
ace4dfee 377 if (getchip)
1da177e4 378 nand_release_device(mtd);
61b03bd7 379
1da177e4
LT		 380 return res;
381}
382
383/**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 385 * @mtd: MTD device structure
386 * @ofs: offset from device start
1da177e4 387 *
8b6e50c9 388 * This is the default implementation, which can be overridden by a hardware
e2414f4c
BN		 389 * specific driver. We try operations in the following order, according to our
390 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
391 * (1) erase the affected block, to allow OOB marker to be written cleanly
392 * (2) update in-memory BBT
393 * (3) write bad block marker to OOB area of affected block
394 * (4) update flash-based BBT
395 * Note that we retain the first error encountered in (3) or (4), finish the
396 * procedures, and dump the error in the end.
1da177e4
LT		 397*/
398static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
399{
ace4dfee 400 struct nand_chip *chip = mtd->priv;
58dd8f2b 401 uint8_t buf[2] = { 0, 0 };
e2414f4c
BN		 402 int block, res, ret = 0, i = 0;
403 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
61b03bd7 404
e2414f4c 405 if (write_oob) {
00918429
BN		 406 struct erase_info einfo;
407
408 /* Attempt erase before marking OOB */
409 memset(&einfo, 0, sizeof(einfo));
410 einfo.mtd = mtd;
411 einfo.addr = ofs;
412 einfo.len = 1 << chip->phys_erase_shift;
413 nand_erase_nand(mtd, &einfo, 0);
414 }
415
1da177e4 416 /* Get block number */
4226b510 417 block = (int)(ofs >> chip->bbt_erase_shift);
e2414f4c 418 /* Mark block bad in memory-based BBT */
ace4dfee
TG		 419 if (chip->bbt)
420 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 421
e2414f4c
BN		 422 /* Write bad block marker to OOB */
423 if (write_oob) {
4a89ff88 424 struct mtd_oob_ops ops;
df698621 425 loff_t wr_ofs = ofs;
4a89ff88 426
c0b8ba7b 427 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 428
4a89ff88
BN		 429 ops.datbuf = NULL;
430 ops.oobbuf = buf;
85443319
BN		 431 ops.ooboffs = chip->badblockpos;
432 if (chip->options & NAND_BUSWIDTH_16) {
433 ops.ooboffs &= ~0x01;
434 ops.len = ops.ooblen = 2;
435 } else {
436 ops.len = ops.ooblen = 1;
437 }
23b1a99b 438 ops.mode = MTD_OPS_PLACE_OOB;
df698621 439
e2414f4c 440 /* Write to first/last page(s) if necessary */
df698621
BN		 441 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
442 wr_ofs += mtd->erasesize - mtd->writesize;
02ed70bb 443 do {
e2414f4c
BN		 444 res = nand_do_write_oob(mtd, wr_ofs, &ops);
445 if (!ret)
446 ret = res;
02ed70bb 447
02ed70bb 448 i++;
df698621 449 wr_ofs += mtd->writesize;
e2414f4c 450 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
02ed70bb 451
c0b8ba7b 452 nand_release_device(mtd);
f1a28c02 453 }
e2414f4c
BN		 454
455 /* Update flash-based bad block table */
456 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
457 res = nand_update_bbt(mtd, ofs);
458 if (!ret)
459 ret = res;
460 }
461
f1a28c02
TG		 462 if (!ret)
463 mtd->ecc_stats.badblocks++;
c0b8ba7b 464
f1a28c02 465 return ret;
1da177e4
LT		 466}
467
61b03bd7 468/**
1da177e4 469 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 470 * @mtd: MTD device structure
1da177e4 471 *
8b6e50c9
BN		 472 * Check, if the device is write protected. The function expects, that the
473 * device is already selected.
1da177e4 474 */
e0c7d767 475static int nand_check_wp(struct mtd_info *mtd)
1da177e4 476{
ace4dfee 477 struct nand_chip *chip = mtd->priv;
93edbad6 478
8b6e50c9 479 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 480 if (chip->options & NAND_BROKEN_XD)
481 return 0;
482
1da177e4 483 /* Check the WP bit */
ace4dfee
TG		 484 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
485 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 486}
487
488/**
489 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 490 * @mtd: MTD device structure
491 * @ofs: offset from device start
492 * @getchip: 0, if the chip is already selected
493 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 494 *
495 * Check, if the block is bad. Either by reading the bad block table or
496 * calling of the scan function.
497 */
2c0a2bed
TG		 498static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
499 int allowbbt)
1da177e4 500{
ace4dfee 501 struct nand_chip *chip = mtd->priv;
61b03bd7 502
ace4dfee
TG		 503 if (!chip->bbt)
504 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 505
1da177e4 506 /* Return info from the table */
e0c7d767 507 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 508}
509
2af7c653
SK		 510/**
511 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 512 * @mtd: MTD device structure
513 * @timeo: Timeout
2af7c653
SK		 514 *
515 * Helper function for nand_wait_ready used when needing to wait in interrupt
516 * context.
517 */
518static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
519{
520 struct nand_chip *chip = mtd->priv;
521 int i;
522
523 /* Wait for the device to get ready */
524 for (i = 0; i < timeo; i++) {
525 if (chip->dev_ready(mtd))
526 break;
527 touch_softlockup_watchdog();
528 mdelay(1);
529 }
530}
531
7854d3f7 532/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 533void nand_wait_ready(struct mtd_info *mtd)
3b88775c 534{
ace4dfee 535 struct nand_chip *chip = mtd->priv;
e0c7d767 536 unsigned long timeo = jiffies + 2;
3b88775c 537
2af7c653
SK		 538 /* 400ms timeout */
539 if (in_interrupt() || oops_in_progress)
540 return panic_nand_wait_ready(mtd, 400);
541
8fe833c1 542 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 543 /* Wait until command is processed or timeout occurs */
3b88775c 544 do {
ace4dfee 545 if (chip->dev_ready(mtd))
8fe833c1 546 break;
8446f1d3 547 touch_softlockup_watchdog();
61b03bd7 548 } while (time_before(jiffies, timeo));
8fe833c1 549 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 550}
4b648b02 551EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 552
1da177e4
LT		 553/**
554 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 555 * @mtd: MTD device structure
556 * @command: the command to be sent
557 * @column: the column address for this command, -1 if none
558 * @page_addr: the page address for this command, -1 if none
1da177e4 559 *
8b6e50c9
BN		 560 * Send command to NAND device. This function is used for small page devices
561 * (256/512 Bytes per page).
1da177e4 562 */
7abd3ef9
TG		 563static void nand_command(struct mtd_info *mtd, unsigned int command,
564 int column, int page_addr)
1da177e4 565{
ace4dfee 566 register struct nand_chip *chip = mtd->priv;
7abd3ef9 567 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 568
8b6e50c9 569 /* Write out the command to the device */
1da177e4
LT		 570 if (command == NAND_CMD_SEQIN) {
571 int readcmd;
572
28318776 573 if (column >= mtd->writesize) {
1da177e4 574 /* OOB area */
28318776 575 column -= mtd->writesize;
1da177e4
LT		 576 readcmd = NAND_CMD_READOOB;
577 } else if (column < 256) {
578 /* First 256 bytes --> READ0 */
579 readcmd = NAND_CMD_READ0;
580 } else {
581 column -= 256;
582 readcmd = NAND_CMD_READ1;
583 }
ace4dfee 584 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 585 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 586 }
ace4dfee 587 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 588
8b6e50c9 589 /* Address cycle, when necessary */
7abd3ef9
TG		 590 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
591 /* Serially input address */
592 if (column != -1) {
593 /* Adjust columns for 16 bit buswidth */
ace4dfee 594 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 595 column >>= 1;
ace4dfee 596 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 597 ctrl &= ~NAND_CTRL_CHANGE;
598 }
599 if (page_addr != -1) {
ace4dfee 600 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 601 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 602 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 603 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 604 if (chip->chipsize > (32 << 20))
605 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 606 }
ace4dfee 607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 608
609 /*
8b6e50c9
BN		 610 * Program and erase have their own busy handlers status and sequential
611 * in needs no delay
e0c7d767 612 */
1da177e4 613 switch (command) {
61b03bd7 614
1da177e4
LT		 615 case NAND_CMD_PAGEPROG:
616 case NAND_CMD_ERASE1:
617 case NAND_CMD_ERASE2:
618 case NAND_CMD_SEQIN:
619 case NAND_CMD_STATUS:
620 return;
621
622 case NAND_CMD_RESET:
ace4dfee 623 if (chip->dev_ready)
1da177e4 624 break;
ace4dfee
TG		 625 udelay(chip->chip_delay);
626 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 627 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 628 chip->cmd_ctrl(mtd,
629 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 630 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
631 ;
1da177e4
LT		 632 return;
633
e0c7d767 634 /* This applies to read commands */
1da177e4 635 default:
61b03bd7 636 /*
1da177e4
LT		 637 * If we don't have access to the busy pin, we apply the given
638 * command delay
e0c7d767 639 */
ace4dfee
TG		 640 if (!chip->dev_ready) {
641 udelay(chip->chip_delay);
1da177e4 642 return;
61b03bd7 643 }
1da177e4 644 }
8b6e50c9
BN		 645 /*
646 * Apply this short delay always to ensure that we do wait tWB in
647 * any case on any machine.
648 */
e0c7d767 649 ndelay(100);
3b88775c
TG		 650
651 nand_wait_ready(mtd);
1da177e4
LT		 652}
653
654/**
655 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 656 * @mtd: MTD device structure
657 * @command: the command to be sent
658 * @column: the column address for this command, -1 if none
659 * @page_addr: the page address for this command, -1 if none
1da177e4 660 *
7abd3ef9 661 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 662 * devices. We don't have the separate regions as we have in the small page
663 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 664 */
7abd3ef9
TG		 665static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
666 int column, int page_addr)
1da177e4 667{
ace4dfee 668 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 669
670 /* Emulate NAND_CMD_READOOB */
671 if (command == NAND_CMD_READOOB) {
28318776 672 column += mtd->writesize;
1da177e4
LT		 673 command = NAND_CMD_READ0;
674 }
61b03bd7 675
7abd3ef9 676 /* Command latch cycle */
ace4dfee 677 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 678 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 679
680 if (column != -1 || page_addr != -1) {
7abd3ef9 681 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 682
683 /* Serially input address */
684 if (column != -1) {
685 /* Adjust columns for 16 bit buswidth */
ace4dfee 686 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 687 column >>= 1;
ace4dfee 688 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 689 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 690 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 691 }
1da177e4 692 if (page_addr != -1) {
ace4dfee
TG		 693 chip->cmd_ctrl(mtd, page_addr, ctrl);
694 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 695 NAND_NCE | NAND_ALE);
1da177e4 696 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 697 if (chip->chipsize > (128 << 20))
698 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 699 NAND_NCE | NAND_ALE);
1da177e4 700 }
1da177e4 701 }
ace4dfee 702 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 703
704 /*
8b6e50c9
BN		 705 * Program and erase have their own busy handlers status, sequential
706 * in, and deplete1 need no delay.
30f464b7 707 */
1da177e4 708 switch (command) {
61b03bd7 709
1da177e4
LT		 710 case NAND_CMD_CACHEDPROG:
711 case NAND_CMD_PAGEPROG:
712 case NAND_CMD_ERASE1:
713 case NAND_CMD_ERASE2:
714 case NAND_CMD_SEQIN:
7bc3312b 715 case NAND_CMD_RNDIN:
1da177e4 716 case NAND_CMD_STATUS:
30f464b7 717 case NAND_CMD_DEPLETE1:
1da177e4
LT		 718 return;
719
30f464b7
DM		 720 case NAND_CMD_STATUS_ERROR:
721 case NAND_CMD_STATUS_ERROR0:
722 case NAND_CMD_STATUS_ERROR1:
723 case NAND_CMD_STATUS_ERROR2:
724 case NAND_CMD_STATUS_ERROR3:
8b6e50c9 725 /* Read error status commands require only a short delay */
ace4dfee 726 udelay(chip->chip_delay);
30f464b7 727 return;
1da177e4
LT		 728
729 case NAND_CMD_RESET:
ace4dfee 730 if (chip->dev_ready)
1da177e4 731 break;
ace4dfee 732 udelay(chip->chip_delay);
12efdde3
TG		 733 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
735 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
736 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 737 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
738 ;
1da177e4
LT		 739 return;
740
7bc3312b
TG		 741 case NAND_CMD_RNDOUT:
742 /* No ready / busy check necessary */
743 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
744 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
745 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
746 NAND_NCE | NAND_CTRL_CHANGE);
747 return;
748
1da177e4 749 case NAND_CMD_READ0:
12efdde3
TG		 750 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
751 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
752 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
753 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 754
e0c7d767 755 /* This applies to read commands */
1da177e4 756 default:
61b03bd7 757 /*
1da177e4 758 * If we don't have access to the busy pin, we apply the given
8b6e50c9 759 * command delay.
e0c7d767 760 */
ace4dfee
TG		 761 if (!chip->dev_ready) {
762 udelay(chip->chip_delay);
1da177e4 763 return;
61b03bd7 764 }
1da177e4 765 }
3b88775c 766
8b6e50c9
BN		 767 /*
768 * Apply this short delay always to ensure that we do wait tWB in
769 * any case on any machine.
770 */
e0c7d767 771 ndelay(100);
3b88775c
TG		 772
773 nand_wait_ready(mtd);
1da177e4
LT		 774}
775
2af7c653
SK		 776/**
777 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 778 * @chip: the nand chip descriptor
779 * @mtd: MTD device structure
780 * @new_state: the state which is requested
2af7c653
SK		 781 *
782 * Used when in panic, no locks are taken.
783 */
784static void panic_nand_get_device(struct nand_chip *chip,
785 struct mtd_info *mtd, int new_state)
786{
7854d3f7 787 /* Hardware controller shared among independent devices */
2af7c653
SK		 788 chip->controller->active = chip;
789 chip->state = new_state;
790}
791
1da177e4
LT		 792/**
793 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 794 * @chip: the nand chip descriptor
795 * @mtd: MTD device structure
796 * @new_state: the state which is requested
1da177e4
LT		 797 *
798 * Get the device and lock it for exclusive access
799 */
2c0a2bed 800static int
ace4dfee 801nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 802{
ace4dfee
TG		 803 spinlock_t *lock = &chip->controller->lock;
804 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 805 DECLARE_WAITQUEUE(wait, current);
7351d3a5 806retry:
0dfc6246
TG		 807 spin_lock(lock);
808
b8b3ee9a 809 /* Hardware controller shared among independent devices */
ace4dfee
TG		 810 if (!chip->controller->active)
811 chip->controller->active = chip;
a36ed299 812
ace4dfee
TG		 813 if (chip->controller->active == chip && chip->state == FL_READY) {
814 chip->state = new_state;
0dfc6246 815 spin_unlock(lock);
962034f4
VW		 816 return 0;
817 }
818 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 819 if (chip->controller->active->state == FL_PM_SUSPENDED) {
820 chip->state = FL_PM_SUSPENDED;
821 spin_unlock(lock);
822 return 0;
6b0d9a84 823 }
0dfc6246
TG		 824 }
825 set_current_state(TASK_UNINTERRUPTIBLE);
826 add_wait_queue(wq, &wait);
827 spin_unlock(lock);
828 schedule();
829 remove_wait_queue(wq, &wait);
1da177e4
LT		 830 goto retry;
831}
832
2af7c653 833/**
8b6e50c9
BN		 834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
837 * @timeo: timeout
2af7c653
SK		 838 *
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
b595076a 841 * an oops through mtdoops.
2af7c653
SK		 842 */
843static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
844 unsigned long timeo)
845{
846 int i;
847 for (i = 0; i < timeo; i++) {
848 if (chip->dev_ready) {
849 if (chip->dev_ready(mtd))
850 break;
851 } else {
852 if (chip->read_byte(mtd) & NAND_STATUS_READY)
853 break;
854 }
855 mdelay(1);
f8ac0414 856 }
2af7c653
SK		 857}
858
1da177e4 859/**
8b6e50c9
BN		 860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
1da177e4 863 *
8b6e50c9
BN		 864 * Wait for command done. This applies to erase and program only. Erase can
865 * take up to 400ms and program up to 20ms according to general NAND and
866 * SmartMedia specs.
844d3b42 867 */
7bc3312b 868static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 869{
870
e0c7d767 871 unsigned long timeo = jiffies;
7bc3312b 872 int status, state = chip->state;
61b03bd7 873
1da177e4 874 if (state == FL_ERASING)
e0c7d767 875 timeo += (HZ * 400) / 1000;
1da177e4 876 else
e0c7d767 877 timeo += (HZ * 20) / 1000;
1da177e4 878
8fe833c1
RP		 879 led_trigger_event(nand_led_trigger, LED_FULL);
880
8b6e50c9
BN		 881 /*
882 * Apply this short delay always to ensure that we do wait tWB in any
883 * case on any machine.
884 */
e0c7d767 885 ndelay(100);
1da177e4 886
ace4dfee
TG		 887 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
888 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 889 else
ace4dfee 890 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 891
2af7c653
SK		 892 if (in_interrupt() || oops_in_progress)
893 panic_nand_wait(mtd, chip, timeo);
894 else {
895 while (time_before(jiffies, timeo)) {
896 if (chip->dev_ready) {
897 if (chip->dev_ready(mtd))
898 break;
899 } else {
900 if (chip->read_byte(mtd) & NAND_STATUS_READY)
901 break;
902 }
903 cond_resched();
1da177e4 904 }
1da177e4 905 }
8fe833c1
RP		 906 led_trigger_event(nand_led_trigger, LED_OFF);
907
ace4dfee 908 status = (int)chip->read_byte(mtd);
1da177e4
LT		 909 return status;
910}
911
7d70f334 912/**
b6d676db 913 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 914 * @mtd: mtd info
915 * @ofs: offset to start unlock from
916 * @len: length to unlock
8b6e50c9
BN		 917 * @invert: when = 0, unlock the range of blocks within the lower and
918 * upper boundary address
919 * when = 1, unlock the range of blocks outside the boundaries
920 * of the lower and upper boundary address
7d70f334 921 *
8b6e50c9 922 * Returs unlock status.
7d70f334
VS		 923 */
924static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
925 uint64_t len, int invert)
926{
927 int ret = 0;
928 int status, page;
929 struct nand_chip *chip = mtd->priv;
930
931 /* Submit address of first page to unlock */
932 page = ofs >> chip->page_shift;
933 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
934
935 /* Submit address of last page to unlock */
936 page = (ofs + len) >> chip->page_shift;
937 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
938 (page | invert) & chip->pagemask);
939
940 /* Call wait ready function */
941 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 942 /* See if device thinks it succeeded */
943 if (status & 0x01) {
289c0522 944 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 945 __func__, status);
946 ret = -EIO;
947 }
948
949 return ret;
950}
951
952/**
b6d676db 953 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 954 * @mtd: mtd info
955 * @ofs: offset to start unlock from
956 * @len: length to unlock
7d70f334 957 *
8b6e50c9 958 * Returns unlock status.
7d70f334
VS		 959 */
960int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
961{
962 int ret = 0;
963 int chipnr;
964 struct nand_chip *chip = mtd->priv;
965
289c0522 966 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 967 __func__, (unsigned long long)ofs, len);
968
969 if (check_offs_len(mtd, ofs, len))
970 ret = -EINVAL;
971
972 /* Align to last block address if size addresses end of the device */
973 if (ofs + len == mtd->size)
974 len -= mtd->erasesize;
975
976 nand_get_device(chip, mtd, FL_UNLOCKING);
977
978 /* Shift to get chip number */
979 chipnr = ofs >> chip->chip_shift;
980
981 chip->select_chip(mtd, chipnr);
982
983 /* Check, if it is write protected */
984 if (nand_check_wp(mtd)) {
289c0522 985 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 986 __func__);
987 ret = -EIO;
988 goto out;
989 }
990
991 ret = __nand_unlock(mtd, ofs, len, 0);
992
993out:
7d70f334
VS		 994 nand_release_device(mtd);
995
996 return ret;
997}
7351d3a5 998EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 999
1000/**
b6d676db 1001 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 1002 * @mtd: mtd info
1003 * @ofs: offset to start unlock from
1004 * @len: length to unlock
7d70f334 1005 *
8b6e50c9
BN		 1006 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1007 * have this feature, but it allows only to lock all blocks, not for specified
1008 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1009 * now.
7d70f334 1010 *
8b6e50c9 1011 * Returns lock status.
7d70f334
VS		 1012 */
1013int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1014{
1015 int ret = 0;
1016 int chipnr, status, page;
1017 struct nand_chip *chip = mtd->priv;
1018
289c0522 1019 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1020 __func__, (unsigned long long)ofs, len);
1021
1022 if (check_offs_len(mtd, ofs, len))
1023 ret = -EINVAL;
1024
1025 nand_get_device(chip, mtd, FL_LOCKING);
1026
1027 /* Shift to get chip number */
1028 chipnr = ofs >> chip->chip_shift;
1029
1030 chip->select_chip(mtd, chipnr);
1031
1032 /* Check, if it is write protected */
1033 if (nand_check_wp(mtd)) {
289c0522 1034 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1035 __func__);
1036 status = MTD_ERASE_FAILED;
1037 ret = -EIO;
1038 goto out;
1039 }
1040
1041 /* Submit address of first page to lock */
1042 page = ofs >> chip->page_shift;
1043 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1044
1045 /* Call wait ready function */
1046 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 1047 /* See if device thinks it succeeded */
1048 if (status & 0x01) {
289c0522 1049 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1050 __func__, status);
1051 ret = -EIO;
1052 goto out;
1053 }
1054
1055 ret = __nand_unlock(mtd, ofs, len, 0x1);
1056
1057out:
7d70f334
VS		 1058 nand_release_device(mtd);
1059
1060 return ret;
1061}
7351d3a5 1062EXPORT_SYMBOL(nand_lock);
7d70f334 1063
8593fbc6 1064/**
7854d3f7 1065 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1fbb938d 1069 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1070 * @page: page number to read
52ff49df 1071 *
7854d3f7 1072 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1073 */
1074static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1075 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1076{
1077 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1078 if (oob_required)
1079 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1080 return 0;
1081}
1082
52ff49df 1083/**
7854d3f7 1084 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1085 * @mtd: mtd info structure
1086 * @chip: nand chip info structure
1087 * @buf: buffer to store read data
1fbb938d 1088 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1089 * @page: page number to read
52ff49df
DB		 1090 *
1091 * We need a special oob layout and handling even when OOB isn't used.
1092 */
7351d3a5 1093static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1094 struct nand_chip *chip, uint8_t *buf,
1095 int oob_required, int page)
52ff49df
DB		 1096{
1097 int eccsize = chip->ecc.size;
1098 int eccbytes = chip->ecc.bytes;
1099 uint8_t *oob = chip->oob_poi;
1100 int steps, size;
1101
1102 for (steps = chip->ecc.steps; steps > 0; steps--) {
1103 chip->read_buf(mtd, buf, eccsize);
1104 buf += eccsize;
1105
1106 if (chip->ecc.prepad) {
1107 chip->read_buf(mtd, oob, chip->ecc.prepad);
1108 oob += chip->ecc.prepad;
1109 }
1110
1111 chip->read_buf(mtd, oob, eccbytes);
1112 oob += eccbytes;
1113
1114 if (chip->ecc.postpad) {
1115 chip->read_buf(mtd, oob, chip->ecc.postpad);
1116 oob += chip->ecc.postpad;
1117 }
1118 }
1119
1120 size = mtd->oobsize - (oob - chip->oob_poi);
1121 if (size)
1122 chip->read_buf(mtd, oob, size);
1123
1124 return 0;
1125}
1126
1da177e4 1127/**
7854d3f7 1128 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1129 * @mtd: mtd info structure
1130 * @chip: nand chip info structure
1131 * @buf: buffer to store read data
1fbb938d 1132 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1133 * @page: page number to read
068e3c0a 1134 */
f5bbdacc 1135static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1136 uint8_t *buf, int oob_required, int page)
1da177e4 1137{
f5bbdacc
TG		 1138 int i, eccsize = chip->ecc.size;
1139 int eccbytes = chip->ecc.bytes;
1140 int eccsteps = chip->ecc.steps;
1141 uint8_t *p = buf;
4bf63fcb
DW		 1142 uint8_t *ecc_calc = chip->buffers->ecccalc;
1143 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1144 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1145 unsigned int max_bitflips = 0;
f5bbdacc 1146
1fbb938d 1147 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1148
1149 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1150 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1151
1152 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1153 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1154
1155 eccsteps = chip->ecc.steps;
1156 p = buf;
1157
1158 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1159 int stat;
1160
1161 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1162 if (stat < 0) {
f5bbdacc 1163 mtd->ecc_stats.failed++;
3f91e94f 1164 } else {
f5bbdacc 1165 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1166 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1167 }
f5bbdacc 1168 }
3f91e94f 1169 return max_bitflips;
22c60f5f 1170}
1da177e4 1171
3d459559 1172/**
7854d3f7 1173 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
8b6e50c9
BN		 1174 * @mtd: mtd info structure
1175 * @chip: nand chip info structure
1176 * @data_offs: offset of requested data within the page
1177 * @readlen: data length
1178 * @bufpoi: buffer to store read data
3d459559 1179 */
7351d3a5
FF		 1180static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1181 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1182{
1183 int start_step, end_step, num_steps;
1184 uint32_t *eccpos = chip->ecc.layout->eccpos;
1185 uint8_t *p;
1186 int data_col_addr, i, gaps = 0;
1187 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1188 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1189 int index = 0;
3f91e94f 1190 unsigned int max_bitflips = 0;
3d459559 1191
7854d3f7 1192 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1193 start_step = data_offs / chip->ecc.size;
1194 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1195 num_steps = end_step - start_step + 1;
1196
8b6e50c9 1197 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1198 datafrag_len = num_steps * chip->ecc.size;
1199 eccfrag_len = num_steps * chip->ecc.bytes;
1200
1201 data_col_addr = start_step * chip->ecc.size;
1202 /* If we read not a page aligned data */
1203 if (data_col_addr != 0)
1204 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1205
1206 p = bufpoi + data_col_addr;
1207 chip->read_buf(mtd, p, datafrag_len);
1208
8b6e50c9 1209 /* Calculate ECC */
3d459559
AK		 1210 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1211 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1212
8b6e50c9
BN		 1213 /*
1214 * The performance is faster if we position offsets according to
7854d3f7 1215 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1216 */
3d459559
AK		 1217 for (i = 0; i < eccfrag_len - 1; i++) {
1218 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1219 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1220 gaps = 1;
1221 break;
1222 }
1223 }
1224 if (gaps) {
1225 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1226 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1227 } else {
8b6e50c9 1228 /*
7854d3f7 1229 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1230 * about buswidth alignment in read_buf.
1231 */
7351d3a5
FF		 1232 index = start_step * chip->ecc.bytes;
1233
1234 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1235 aligned_len = eccfrag_len;
7351d3a5 1236 if (eccpos[index] & (busw - 1))
3d459559 1237 aligned_len++;
7351d3a5 1238 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1239 aligned_len++;
1240
7351d3a5
FF		 1241 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1242 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1243 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1244 }
1245
1246 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1247 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1248
1249 p = bufpoi + data_col_addr;
1250 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1251 int stat;
1252
7351d3a5
FF		 1253 stat = chip->ecc.correct(mtd, p,
1254 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1255 if (stat < 0) {
3d459559 1256 mtd->ecc_stats.failed++;
3f91e94f 1257 } else {
3d459559 1258 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1259 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1260 }
3d459559 1261 }
3f91e94f 1262 return max_bitflips;
3d459559
AK		 1263}
1264
068e3c0a 1265/**
7854d3f7 1266 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1267 * @mtd: mtd info structure
1268 * @chip: nand chip info structure
1269 * @buf: buffer to store read data
1fbb938d 1270 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1271 * @page: page number to read
068e3c0a 1272 *
7854d3f7 1273 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1274 */
f5bbdacc 1275static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1276 uint8_t *buf, int oob_required, int page)
1da177e4 1277{
f5bbdacc
TG		 1278 int i, eccsize = chip->ecc.size;
1279 int eccbytes = chip->ecc.bytes;
1280 int eccsteps = chip->ecc.steps;
1281 uint8_t *p = buf;
4bf63fcb
DW		 1282 uint8_t *ecc_calc = chip->buffers->ecccalc;
1283 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1284 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1285 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1286
1287 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1288 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1289 chip->read_buf(mtd, p, eccsize);
1290 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1291 }
f75e5097 1292 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1293
f5bbdacc 1294 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1295 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1296
f5bbdacc
TG		 1297 eccsteps = chip->ecc.steps;
1298 p = buf;
61b03bd7 1299
f5bbdacc
TG		 1300 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1301 int stat;
1da177e4 1302
f5bbdacc 1303 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1304 if (stat < 0) {
f5bbdacc 1305 mtd->ecc_stats.failed++;
3f91e94f 1306 } else {
f5bbdacc 1307 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1308 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1309 }
f5bbdacc 1310 }
3f91e94f 1311 return max_bitflips;
f5bbdacc 1312}
1da177e4 1313
6e0cb135 1314/**
7854d3f7 1315 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1316 * @mtd: mtd info structure
1317 * @chip: nand chip info structure
1318 * @buf: buffer to store read data
1fbb938d 1319 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1320 * @page: page number to read
6e0cb135 1321 *
8b6e50c9
BN		 1322 * Hardware ECC for large page chips, require OOB to be read first. For this
1323 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1324 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1325 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1326 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1327 */
1328static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1329 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1330{
1331 int i, eccsize = chip->ecc.size;
1332 int eccbytes = chip->ecc.bytes;
1333 int eccsteps = chip->ecc.steps;
1334 uint8_t *p = buf;
1335 uint8_t *ecc_code = chip->buffers->ecccode;
1336 uint32_t *eccpos = chip->ecc.layout->eccpos;
1337 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1338 unsigned int max_bitflips = 0;
6e0cb135
SN		 1339
1340 /* Read the OOB area first */
1341 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1342 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1343 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1344
1345 for (i = 0; i < chip->ecc.total; i++)
1346 ecc_code[i] = chip->oob_poi[eccpos[i]];
1347
1348 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1349 int stat;
1350
1351 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1352 chip->read_buf(mtd, p, eccsize);
1353 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1354
1355 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1356 if (stat < 0) {
6e0cb135 1357 mtd->ecc_stats.failed++;
3f91e94f 1358 } else {
6e0cb135 1359 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1360 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1361 }
6e0cb135 1362 }
3f91e94f 1363 return max_bitflips;
6e0cb135
SN		 1364}
1365
f5bbdacc 1366/**
7854d3f7 1367 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1368 * @mtd: mtd info structure
1369 * @chip: nand chip info structure
1370 * @buf: buffer to store read data
1fbb938d 1371 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1372 * @page: page number to read
f5bbdacc 1373 *
8b6e50c9
BN		 1374 * The hw generator calculates the error syndrome automatically. Therefore we
1375 * need a special oob layout and handling.
f5bbdacc
TG		 1376 */
1377static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1378 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1379{
1380 int i, eccsize = chip->ecc.size;
1381 int eccbytes = chip->ecc.bytes;
1382 int eccsteps = chip->ecc.steps;
1383 uint8_t *p = buf;
f75e5097 1384 uint8_t *oob = chip->oob_poi;
3f91e94f 1385 unsigned int max_bitflips = 0;
1da177e4 1386
f5bbdacc
TG		 1387 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1388 int stat;
61b03bd7 1389
f5bbdacc
TG		 1390 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1391 chip->read_buf(mtd, p, eccsize);
1da177e4 1392
f5bbdacc
TG		 1393 if (chip->ecc.prepad) {
1394 chip->read_buf(mtd, oob, chip->ecc.prepad);
1395 oob += chip->ecc.prepad;
1396 }
1da177e4 1397
f5bbdacc
TG		 1398 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1399 chip->read_buf(mtd, oob, eccbytes);
1400 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1401
3f91e94f 1402 if (stat < 0) {
f5bbdacc 1403 mtd->ecc_stats.failed++;
3f91e94f 1404 } else {
f5bbdacc 1405 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1406 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1407 }
61b03bd7 1408
f5bbdacc 1409 oob += eccbytes;
1da177e4 1410
f5bbdacc
TG		 1411 if (chip->ecc.postpad) {
1412 chip->read_buf(mtd, oob, chip->ecc.postpad);
1413 oob += chip->ecc.postpad;
61b03bd7 1414 }
f5bbdacc 1415 }
1da177e4 1416
f5bbdacc 1417 /* Calculate remaining oob bytes */
7e4178f9 1418 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1419 if (i)
1420 chip->read_buf(mtd, oob, i);
61b03bd7 1421
3f91e94f 1422 return max_bitflips;
f5bbdacc 1423}
1da177e4 1424
f5bbdacc 1425/**
7854d3f7 1426 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1427 * @chip: nand chip structure
1428 * @oob: oob destination address
1429 * @ops: oob ops structure
1430 * @len: size of oob to transfer
8593fbc6
TG		 1431 */
1432static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1433 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1434{
f8ac0414 1435 switch (ops->mode) {
8593fbc6 1436
0612b9dd
BN		 1437 case MTD_OPS_PLACE_OOB:
1438 case MTD_OPS_RAW:
8593fbc6
TG		 1439 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1440 return oob + len;
1441
0612b9dd 1442 case MTD_OPS_AUTO_OOB: {
8593fbc6 1443 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1444 uint32_t boffs = 0, roffs = ops->ooboffs;
1445 size_t bytes = 0;
8593fbc6 1446
f8ac0414 1447 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1448 /* Read request not from offset 0? */
7bc3312b
TG		 1449 if (unlikely(roffs)) {
1450 if (roffs >= free->length) {
1451 roffs -= free->length;
1452 continue;
1453 }
1454 boffs = free->offset + roffs;
1455 bytes = min_t(size_t, len,
1456 (free->length - roffs));
1457 roffs = 0;
1458 } else {
1459 bytes = min_t(size_t, len, free->length);
1460 boffs = free->offset;
1461 }
1462 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1463 oob += bytes;
1464 }
1465 return oob;
1466 }
1467 default:
1468 BUG();
1469 }
1470 return NULL;
1471}
1472
1473/**
7854d3f7 1474 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1475 * @mtd: MTD device structure
1476 * @from: offset to read from
1477 * @ops: oob ops structure
f5bbdacc
TG		 1478 *
1479 * Internal function. Called with chip held.
1480 */
8593fbc6
TG		 1481static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1482 struct mtd_oob_ops *ops)
f5bbdacc 1483{
e47f3db4 1484 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc
TG		 1485 struct nand_chip *chip = mtd->priv;
1486 struct mtd_ecc_stats stats;
f5bbdacc 1487 int ret = 0;
8593fbc6 1488 uint32_t readlen = ops->len;
7014568b 1489 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1490 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1491 mtd->oobavail : mtd->oobsize;
1492
8593fbc6 1493 uint8_t *bufpoi, *oob, *buf;
edbc4540 1494 unsigned int max_bitflips = 0;
1da177e4 1495
f5bbdacc 1496 stats = mtd->ecc_stats;
1da177e4 1497
f5bbdacc
TG		 1498 chipnr = (int)(from >> chip->chip_shift);
1499 chip->select_chip(mtd, chipnr);
61b03bd7 1500
f5bbdacc
TG		 1501 realpage = (int)(from >> chip->page_shift);
1502 page = realpage & chip->pagemask;
1da177e4 1503
f5bbdacc 1504 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1505
8593fbc6
TG		 1506 buf = ops->datbuf;
1507 oob = ops->oobbuf;
e47f3db4 1508 oob_required = oob ? 1 : 0;
8593fbc6 1509
f8ac0414 1510 while (1) {
f5bbdacc
TG		 1511 bytes = min(mtd->writesize - col, readlen);
1512 aligned = (bytes == mtd->writesize);
61b03bd7 1513
8b6e50c9 1514 /* Is the current page in the buffer? */
8593fbc6 1515 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1516 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1517
c00a0991 1518 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1519
edbc4540
MD		 1520 /*
1521 * Now read the page into the buffer. Absent an error,
1522 * the read methods return max bitflips per ecc step.
1523 */
0612b9dd 1524 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1525 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1526 oob_required,
1527 page);
3d459559 1528 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1529 ret = chip->ecc.read_subpage(mtd, chip,
1530 col, bytes, bufpoi);
956e944c 1531 else
46a8cf2d 1532 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1533 oob_required, page);
6d77b9d0
BN		 1534 if (ret < 0) {
1535 if (!aligned)
1536 /* Invalidate page cache */
1537 chip->pagebuf = -1;
1da177e4 1538 break;
6d77b9d0 1539 }
f5bbdacc 1540
edbc4540
MD		 1541 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1542
f5bbdacc
TG		 1543 /* Transfer not aligned data */
1544 if (!aligned) {
c1194c79 1545 if (!NAND_SUBPAGE_READ(chip) && !oob &&
6d77b9d0 1546 !(mtd->ecc_stats.failed - stats.failed) &&
edbc4540 1547 (ops->mode != MTD_OPS_RAW)) {
3d459559 1548 chip->pagebuf = realpage;
edbc4540
MD		 1549 chip->pagebuf_bitflips = ret;
1550 } else {
6d77b9d0
BN		 1551 /* Invalidate page cache */
1552 chip->pagebuf = -1;
edbc4540 1553 }
4bf63fcb 1554 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1555 }
1556
8593fbc6
TG		 1557 buf += bytes;
1558
1559 if (unlikely(oob)) {
b64d39d8
ML		 1560 int toread = min(oobreadlen, max_oobsize);
1561
1562 if (toread) {
1563 oob = nand_transfer_oob(chip,
1564 oob, ops, toread);
1565 oobreadlen -= toread;
1566 }
8593fbc6
TG		 1567 }
1568
f5bbdacc 1569 if (!(chip->options & NAND_NO_READRDY)) {
c00a0991 1570 /* Apply delay or wait for ready/busy pin */
f5bbdacc
TG		 1571 if (!chip->dev_ready)
1572 udelay(chip->chip_delay);
1573 else
1574 nand_wait_ready(mtd);
1da177e4 1575 }
8593fbc6 1576 } else {
4bf63fcb 1577 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1578 buf += bytes;
edbc4540
MD		 1579 max_bitflips = max_t(unsigned int, max_bitflips,
1580 chip->pagebuf_bitflips);
8593fbc6 1581 }
1da177e4 1582
f5bbdacc 1583 readlen -= bytes;
61b03bd7 1584
f5bbdacc 1585 if (!readlen)
61b03bd7 1586 break;
1da177e4 1587
8b6e50c9 1588 /* For subsequent reads align to page boundary */
1da177e4
LT		 1589 col = 0;
1590 /* Increment page address */
1591 realpage++;
1592
ace4dfee 1593 page = realpage & chip->pagemask;
1da177e4
LT		 1594 /* Check, if we cross a chip boundary */
1595 if (!page) {
1596 chipnr++;
ace4dfee
TG		 1597 chip->select_chip(mtd, -1);
1598 chip->select_chip(mtd, chipnr);
1da177e4 1599 }
1da177e4
LT		 1600 }
1601
8593fbc6 1602 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1603 if (oob)
1604 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1605
3f91e94f 1606 if (ret < 0)
f5bbdacc
TG		 1607 return ret;
1608
9a1fcdfd
TG		 1609 if (mtd->ecc_stats.failed - stats.failed)
1610 return -EBADMSG;
1611
edbc4540 1612 return max_bitflips;
f5bbdacc
TG		 1613}
1614
1615/**
25985edc 1616 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1617 * @mtd: MTD device structure
1618 * @from: offset to read from
1619 * @len: number of bytes to read
1620 * @retlen: pointer to variable to store the number of read bytes
1621 * @buf: the databuffer to put data
f5bbdacc 1622 *
8b6e50c9 1623 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1624 */
1625static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1626 size_t *retlen, uint8_t *buf)
1627{
8593fbc6 1628 struct nand_chip *chip = mtd->priv;
4a89ff88 1629 struct mtd_oob_ops ops;
f5bbdacc
TG		 1630 int ret;
1631
8593fbc6 1632 nand_get_device(chip, mtd, FL_READING);
4a89ff88
BN		 1633 ops.len = len;
1634 ops.datbuf = buf;
1635 ops.oobbuf = NULL;
23b1a99b 1636 ops.mode = 0;
4a89ff88 1637 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1638 *retlen = ops.retlen;
f5bbdacc 1639 nand_release_device(mtd);
f5bbdacc 1640 return ret;
1da177e4
LT		 1641}
1642
7bc3312b 1643/**
7854d3f7 1644 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1645 * @mtd: mtd info structure
1646 * @chip: nand chip info structure
1647 * @page: page number to read
7bc3312b
TG		 1648 */
1649static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1650 int page)
7bc3312b 1651{
5c2ffb11 1652 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1653 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1654 return 0;
7bc3312b
TG		 1655}
1656
1657/**
7854d3f7 1658 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1659 * with syndromes
8b6e50c9
BN		 1660 * @mtd: mtd info structure
1661 * @chip: nand chip info structure
1662 * @page: page number to read
7bc3312b
TG		 1663 */
1664static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1665 int page)
7bc3312b
TG		 1666{
1667 uint8_t *buf = chip->oob_poi;
1668 int length = mtd->oobsize;
1669 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1670 int eccsize = chip->ecc.size;
1671 uint8_t *bufpoi = buf;
1672 int i, toread, sndrnd = 0, pos;
1673
1674 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1675 for (i = 0; i < chip->ecc.steps; i++) {
1676 if (sndrnd) {
1677 pos = eccsize + i * (eccsize + chunk);
1678 if (mtd->writesize > 512)
1679 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1680 else
1681 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1682 } else
1683 sndrnd = 1;
1684 toread = min_t(int, length, chunk);
1685 chip->read_buf(mtd, bufpoi, toread);
1686 bufpoi += toread;
1687 length -= toread;
1688 }
1689 if (length > 0)
1690 chip->read_buf(mtd, bufpoi, length);
1691
5c2ffb11 1692 return 0;
7bc3312b
TG		 1693}
1694
1695/**
7854d3f7 1696 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1697 * @mtd: mtd info structure
1698 * @chip: nand chip info structure
1699 * @page: page number to write
7bc3312b
TG		 1700 */
1701static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1702 int page)
1703{
1704 int status = 0;
1705 const uint8_t *buf = chip->oob_poi;
1706 int length = mtd->oobsize;
1707
1708 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1709 chip->write_buf(mtd, buf, length);
1710 /* Send command to program the OOB data */
1711 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1712
1713 status = chip->waitfunc(mtd, chip);
1714
0d420f9d 1715 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1716}
1717
1718/**
7854d3f7 1719 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1720 * with syndrome - only for large page flash
1721 * @mtd: mtd info structure
1722 * @chip: nand chip info structure
1723 * @page: page number to write
7bc3312b
TG		 1724 */
1725static int nand_write_oob_syndrome(struct mtd_info *mtd,
1726 struct nand_chip *chip, int page)
1727{
1728 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1729 int eccsize = chip->ecc.size, length = mtd->oobsize;
1730 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1731 const uint8_t *bufpoi = chip->oob_poi;
1732
1733 /*
1734 * data-ecc-data-ecc ... ecc-oob
1735 * or
1736 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1737 */
1738 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1739 pos = steps * (eccsize + chunk);
1740 steps = 0;
1741 } else
8b0036ee 1742 pos = eccsize;
7bc3312b
TG		 1743
1744 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1745 for (i = 0; i < steps; i++) {
1746 if (sndcmd) {
1747 if (mtd->writesize <= 512) {
1748 uint32_t fill = 0xFFFFFFFF;
1749
1750 len = eccsize;
1751 while (len > 0) {
1752 int num = min_t(int, len, 4);
1753 chip->write_buf(mtd, (uint8_t *)&fill,
1754 num);
1755 len -= num;
1756 }
1757 } else {
1758 pos = eccsize + i * (eccsize + chunk);
1759 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1760 }
1761 } else
1762 sndcmd = 1;
1763 len = min_t(int, length, chunk);
1764 chip->write_buf(mtd, bufpoi, len);
1765 bufpoi += len;
1766 length -= len;
1767 }
1768 if (length > 0)
1769 chip->write_buf(mtd, bufpoi, length);
1770
1771 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1772 status = chip->waitfunc(mtd, chip);
1773
1774 return status & NAND_STATUS_FAIL ? -EIO : 0;
1775}
1776
1da177e4 1777/**
7854d3f7 1778 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1779 * @mtd: MTD device structure
1780 * @from: offset to read from
1781 * @ops: oob operations description structure
1da177e4 1782 *
8b6e50c9 1783 * NAND read out-of-band data from the spare area.
1da177e4 1784 */
8593fbc6
TG		 1785static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1786 struct mtd_oob_ops *ops)
1da177e4 1787{
c00a0991 1788 int page, realpage, chipnr;
ace4dfee 1789 struct nand_chip *chip = mtd->priv;
041e4575 1790 struct mtd_ecc_stats stats;
7014568b
VW		 1791 int readlen = ops->ooblen;
1792 int len;
7bc3312b 1793 uint8_t *buf = ops->oobbuf;
1951f2f7 1794 int ret = 0;
61b03bd7 1795
289c0522 1796 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1797 __func__, (unsigned long long)from, readlen);
1da177e4 1798
041e4575
BN		 1799 stats = mtd->ecc_stats;
1800
0612b9dd 1801 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1802 len = chip->ecc.layout->oobavail;
03736155
AH		 1803 else
1804 len = mtd->oobsize;
1805
1806 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1807 pr_debug("%s: attempt to start read outside oob\n",
1808 __func__);
03736155
AH		 1809 return -EINVAL;
1810 }
1811
1812 /* Do not allow reads past end of device */
1813 if (unlikely(from >= mtd->size ||
1814 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1815 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1816 pr_debug("%s: attempt to read beyond end of device\n",
1817 __func__);
03736155
AH		 1818 return -EINVAL;
1819 }
7014568b 1820
7314e9e7 1821 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1822 chip->select_chip(mtd, chipnr);
1da177e4 1823
7314e9e7
TG		 1824 /* Shift to get page */
1825 realpage = (int)(from >> chip->page_shift);
1826 page = realpage & chip->pagemask;
1da177e4 1827
f8ac0414 1828 while (1) {
0612b9dd 1829 if (ops->mode == MTD_OPS_RAW)
1951f2f7 1830 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 1831 else
1951f2f7
SL		 1832 ret = chip->ecc.read_oob(mtd, chip, page);
1833
1834 if (ret < 0)
1835 break;
7014568b
VW		 1836
1837 len = min(len, readlen);
1838 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1839
7314e9e7 1840 if (!(chip->options & NAND_NO_READRDY)) {
c00a0991 1841 /* Apply delay or wait for ready/busy pin */
ace4dfee
TG		 1842 if (!chip->dev_ready)
1843 udelay(chip->chip_delay);
19870da7
TG		 1844 else
1845 nand_wait_ready(mtd);
7314e9e7 1846 }
19870da7 1847
7014568b 1848 readlen -= len;
0d420f9d
SZ		 1849 if (!readlen)
1850 break;
1851
7314e9e7
TG		 1852 /* Increment page address */
1853 realpage++;
1854
1855 page = realpage & chip->pagemask;
1856 /* Check, if we cross a chip boundary */
1857 if (!page) {
1858 chipnr++;
1859 chip->select_chip(mtd, -1);
1860 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1861 }
1862 }
1863
1951f2f7
SL		 1864 ops->oobretlen = ops->ooblen - readlen;
1865
1866 if (ret < 0)
1867 return ret;
041e4575
BN		 1868
1869 if (mtd->ecc_stats.failed - stats.failed)
1870 return -EBADMSG;
1871
1872 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1873}
1874
1875/**
8593fbc6 1876 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1877 * @mtd: MTD device structure
1878 * @from: offset to read from
1879 * @ops: oob operation description structure
1da177e4 1880 *
8b6e50c9 1881 * NAND read data and/or out-of-band data.
1da177e4 1882 */
8593fbc6
TG		 1883static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1884 struct mtd_oob_ops *ops)
1da177e4 1885{
ace4dfee 1886 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1887 int ret = -ENOTSUPP;
1888
1889 ops->retlen = 0;
1da177e4
LT		 1890
1891 /* Do not allow reads past end of device */
7014568b 1892 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1893 pr_debug("%s: attempt to read beyond end of device\n",
1894 __func__);
1da177e4
LT		 1895 return -EINVAL;
1896 }
1897
ace4dfee 1898 nand_get_device(chip, mtd, FL_READING);
1da177e4 1899
f8ac0414 1900 switch (ops->mode) {
0612b9dd
BN		 1901 case MTD_OPS_PLACE_OOB:
1902 case MTD_OPS_AUTO_OOB:
1903 case MTD_OPS_RAW:
8593fbc6 1904 break;
1da177e4 1905
8593fbc6
TG		 1906 default:
1907 goto out;
1908 }
1da177e4 1909
8593fbc6
TG		 1910 if (!ops->datbuf)
1911 ret = nand_do_read_oob(mtd, from, ops);
1912 else
1913 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1914
7351d3a5 1915out:
8593fbc6
TG		 1916 nand_release_device(mtd);
1917 return ret;
1918}
61b03bd7 1919
1da177e4 1920
8593fbc6 1921/**
7854d3f7 1922 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1923 * @mtd: mtd info structure
1924 * @chip: nand chip info structure
1925 * @buf: data buffer
1fbb938d 1926 * @oob_required: must write chip->oob_poi to OOB
52ff49df 1927 *
7854d3f7 1928 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1929 */
1930static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1931 const uint8_t *buf, int oob_required)
8593fbc6
TG		 1932{
1933 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1934 if (oob_required)
1935 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1936}
1937
52ff49df 1938/**
7854d3f7 1939 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1940 * @mtd: mtd info structure
1941 * @chip: nand chip info structure
1942 * @buf: data buffer
1fbb938d 1943 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 1944 *
1945 * We need a special oob layout and handling even when ECC isn't checked.
1946 */
7351d3a5
FF		 1947static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1948 struct nand_chip *chip,
1fbb938d 1949 const uint8_t *buf, int oob_required)
52ff49df
DB		 1950{
1951 int eccsize = chip->ecc.size;
1952 int eccbytes = chip->ecc.bytes;
1953 uint8_t *oob = chip->oob_poi;
1954 int steps, size;
1955
1956 for (steps = chip->ecc.steps; steps > 0; steps--) {
1957 chip->write_buf(mtd, buf, eccsize);
1958 buf += eccsize;
1959
1960 if (chip->ecc.prepad) {
1961 chip->write_buf(mtd, oob, chip->ecc.prepad);
1962 oob += chip->ecc.prepad;
1963 }
1964
1965 chip->read_buf(mtd, oob, eccbytes);
1966 oob += eccbytes;
1967
1968 if (chip->ecc.postpad) {
1969 chip->write_buf(mtd, oob, chip->ecc.postpad);
1970 oob += chip->ecc.postpad;
1971 }
1972 }
1973
1974 size = mtd->oobsize - (oob - chip->oob_poi);
1975 if (size)
1976 chip->write_buf(mtd, oob, size);
1977}
9223a456 1978/**
7854d3f7 1979 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1980 * @mtd: mtd info structure
1981 * @chip: nand chip info structure
1982 * @buf: data buffer
1fbb938d 1983 * @oob_required: must write chip->oob_poi to OOB
9223a456 1984 */
f75e5097 1985static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1986 const uint8_t *buf, int oob_required)
9223a456 1987{
f75e5097
TG		 1988 int i, eccsize = chip->ecc.size;
1989 int eccbytes = chip->ecc.bytes;
1990 int eccsteps = chip->ecc.steps;
4bf63fcb 1991 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1992 const uint8_t *p = buf;
8b099a39 1993 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1994
7854d3f7 1995 /* Software ECC calculation */
8593fbc6
TG		 1996 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1997 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1998
8593fbc6
TG		 1999 for (i = 0; i < chip->ecc.total; i++)
2000 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 2001
1fbb938d 2002 chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 2003}
9223a456 2004
f75e5097 2005/**
7854d3f7 2006 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2007 * @mtd: mtd info structure
2008 * @chip: nand chip info structure
2009 * @buf: data buffer
1fbb938d 2010 * @oob_required: must write chip->oob_poi to OOB
f75e5097
TG		 2011 */
2012static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2013 const uint8_t *buf, int oob_required)
f75e5097
TG		 2014{
2015 int i, eccsize = chip->ecc.size;
2016 int eccbytes = chip->ecc.bytes;
2017 int eccsteps = chip->ecc.steps;
4bf63fcb 2018 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2019 const uint8_t *p = buf;
8b099a39 2020 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2021
f75e5097
TG		 2022 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2023 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2024 chip->write_buf(mtd, p, eccsize);
f75e5097 2025 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2026 }
2027
f75e5097
TG		 2028 for (i = 0; i < chip->ecc.total; i++)
2029 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2030
2031 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 2032}
2033
61b03bd7 2034/**
7854d3f7 2035 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2036 * @mtd: mtd info structure
2037 * @chip: nand chip info structure
2038 * @buf: data buffer
1fbb938d 2039 * @oob_required: must write chip->oob_poi to OOB
1da177e4 2040 *
8b6e50c9
BN		 2041 * The hw generator calculates the error syndrome automatically. Therefore we
2042 * need a special oob layout and handling.
f75e5097
TG		 2043 */
2044static void nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 2045 struct nand_chip *chip,
2046 const uint8_t *buf, int oob_required)
1da177e4 2047{
f75e5097
TG		 2048 int i, eccsize = chip->ecc.size;
2049 int eccbytes = chip->ecc.bytes;
2050 int eccsteps = chip->ecc.steps;
2051 const uint8_t *p = buf;
2052 uint8_t *oob = chip->oob_poi;
1da177e4 2053
f75e5097 2054 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2055
f75e5097
TG		 2056 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2057 chip->write_buf(mtd, p, eccsize);
61b03bd7 2058
f75e5097
TG		 2059 if (chip->ecc.prepad) {
2060 chip->write_buf(mtd, oob, chip->ecc.prepad);
2061 oob += chip->ecc.prepad;
2062 }
2063
2064 chip->ecc.calculate(mtd, p, oob);
2065 chip->write_buf(mtd, oob, eccbytes);
2066 oob += eccbytes;
2067
2068 if (chip->ecc.postpad) {
2069 chip->write_buf(mtd, oob, chip->ecc.postpad);
2070 oob += chip->ecc.postpad;
1da177e4 2071 }
1da177e4 2072 }
f75e5097
TG		 2073
2074 /* Calculate remaining oob bytes */
7e4178f9 2075 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2076 if (i)
2077 chip->write_buf(mtd, oob, i);
2078}
2079
2080/**
956e944c 2081 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2082 * @mtd: MTD device structure
2083 * @chip: NAND chip descriptor
2084 * @buf: the data to write
1fbb938d 2085 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2086 * @page: page number to write
2087 * @cached: cached programming
2088 * @raw: use _raw version of write_page
f75e5097
TG		 2089 */
2090static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d
BN		 2091 const uint8_t *buf, int oob_required, int page,
2092 int cached, int raw)
f75e5097
TG		 2093{
2094 int status;
2095
2096 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2097
956e944c 2098 if (unlikely(raw))
1fbb938d 2099 chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
956e944c 2100 else
1fbb938d 2101 chip->ecc.write_page(mtd, chip, buf, oob_required);
f75e5097
TG		 2102
2103 /*
7854d3f7 2104 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2105 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2106 */
2107 cached = 0;
2108
2109 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2110
2111 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2112 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2113 /*
2114 * See if operation failed and additional status checks are
8b6e50c9 2115 * available.
f75e5097
TG		 2116 */
2117 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2118 status = chip->errstat(mtd, chip, FL_WRITING, status,
2119 page);
2120
2121 if (status & NAND_STATUS_FAIL)
2122 return -EIO;
2123 } else {
2124 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2125 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2126 }
2127
2128#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2129 /* Send command to read back the data */
2130 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2131
2132 if (chip->verify_buf(mtd, buf, mtd->writesize))
2133 return -EIO;
09cbe581
BH		 2134
2135 /* Make sure the next page prog is preceded by a status read */
2136 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
f75e5097
TG		 2137#endif
2138 return 0;
1da177e4
LT		 2139}
2140
8593fbc6 2141/**
7854d3f7 2142 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2143 * @mtd: MTD device structure
8b6e50c9
BN		 2144 * @oob: oob data buffer
2145 * @len: oob data write length
2146 * @ops: oob ops structure
8593fbc6 2147 */
f722013e
TAA		 2148static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2149 struct mtd_oob_ops *ops)
8593fbc6 2150{
f722013e
TAA		 2151 struct nand_chip *chip = mtd->priv;
2152
2153 /*
2154 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2155 * data from a previous OOB read.
2156 */
2157 memset(chip->oob_poi, 0xff, mtd->oobsize);
2158
f8ac0414 2159 switch (ops->mode) {
8593fbc6 2160
0612b9dd
BN		 2161 case MTD_OPS_PLACE_OOB:
2162 case MTD_OPS_RAW:
8593fbc6
TG		 2163 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2164 return oob + len;
2165
0612b9dd 2166 case MTD_OPS_AUTO_OOB: {
8593fbc6 2167 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2168 uint32_t boffs = 0, woffs = ops->ooboffs;
2169 size_t bytes = 0;
8593fbc6 2170
f8ac0414 2171 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2172 /* Write request not from offset 0? */
7bc3312b
TG		 2173 if (unlikely(woffs)) {
2174 if (woffs >= free->length) {
2175 woffs -= free->length;
2176 continue;
2177 }
2178 boffs = free->offset + woffs;
2179 bytes = min_t(size_t, len,
2180 (free->length - woffs));
2181 woffs = 0;
2182 } else {
2183 bytes = min_t(size_t, len, free->length);
2184 boffs = free->offset;
2185 }
8b0036ee 2186 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2187 oob += bytes;
2188 }
2189 return oob;
2190 }
2191 default:
2192 BUG();
2193 }
2194 return NULL;
2195}
2196
f8ac0414 2197#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2198
2199/**
7854d3f7 2200 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2201 * @mtd: MTD device structure
2202 * @to: offset to write to
2203 * @ops: oob operations description structure
1da177e4 2204 *
8b6e50c9 2205 * NAND write with ECC.
1da177e4 2206 */
8593fbc6
TG		 2207static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2208 struct mtd_oob_ops *ops)
1da177e4 2209{
29072b96 2210 int chipnr, realpage, page, blockmask, column;
ace4dfee 2211 struct nand_chip *chip = mtd->priv;
8593fbc6 2212 uint32_t writelen = ops->len;
782ce79a
ML		 2213
2214 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2215 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2216 mtd->oobavail : mtd->oobsize;
2217
8593fbc6
TG		 2218 uint8_t *oob = ops->oobbuf;
2219 uint8_t *buf = ops->datbuf;
29072b96 2220 int ret, subpage;
e47f3db4 2221 int oob_required = oob ? 1 : 0;
1da177e4 2222
8593fbc6 2223 ops->retlen = 0;
29072b96
TG		 2224 if (!writelen)
2225 return 0;
1da177e4 2226
8b6e50c9 2227 /* Reject writes, which are not page aligned */
8593fbc6 2228 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2229 pr_notice("%s: attempt to write non page aligned data\n",
2230 __func__);
1da177e4
LT		 2231 return -EINVAL;
2232 }
2233
29072b96
TG		 2234 column = to & (mtd->writesize - 1);
2235 subpage = column || (writelen & (mtd->writesize - 1));
2236
2237 if (subpage && oob)
2238 return -EINVAL;
1da177e4 2239
6a930961
TG		 2240 chipnr = (int)(to >> chip->chip_shift);
2241 chip->select_chip(mtd, chipnr);
2242
1da177e4
LT		 2243 /* Check, if it is write protected */
2244 if (nand_check_wp(mtd))
8593fbc6 2245 return -EIO;
1da177e4 2246
f75e5097
TG		 2247 realpage = (int)(to >> chip->page_shift);
2248 page = realpage & chip->pagemask;
2249 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2250
2251 /* Invalidate the page cache, when we write to the cached page */
2252 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2253 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2254 chip->pagebuf = -1;
61b03bd7 2255
782ce79a 2256 /* Don't allow multipage oob writes with offset */
cdcf12b2 2257 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2258 return -EINVAL;
2259
f8ac0414 2260 while (1) {
29072b96 2261 int bytes = mtd->writesize;
f75e5097 2262 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2263 uint8_t *wbuf = buf;
2264
8b6e50c9 2265 /* Partial page write? */
29072b96
TG		 2266 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2267 cached = 0;
2268 bytes = min_t(int, bytes - column, (int) writelen);
2269 chip->pagebuf = -1;
2270 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2271 memcpy(&chip->buffers->databuf[column], buf, bytes);
2272 wbuf = chip->buffers->databuf;
2273 }
1da177e4 2274
782ce79a
ML		 2275 if (unlikely(oob)) {
2276 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2277 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2278 oobwritelen -= len;
f722013e
TAA		 2279 } else {
2280 /* We still need to erase leftover OOB data */
2281 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2282 }
8593fbc6 2283
e47f3db4
BN		 2284 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2285 cached, (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2286 if (ret)
2287 break;
2288
2289 writelen -= bytes;
2290 if (!writelen)
2291 break;
2292
29072b96 2293 column = 0;
f75e5097
TG		 2294 buf += bytes;
2295 realpage++;
2296
2297 page = realpage & chip->pagemask;
2298 /* Check, if we cross a chip boundary */
2299 if (!page) {
2300 chipnr++;
2301 chip->select_chip(mtd, -1);
2302 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2303 }
2304 }
8593fbc6 2305
8593fbc6 2306 ops->retlen = ops->len - writelen;
7014568b
VW		 2307 if (unlikely(oob))
2308 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2309 return ret;
2310}
2311
2af7c653
SK		 2312/**
2313 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2314 * @mtd: MTD device structure
2315 * @to: offset to write to
2316 * @len: number of bytes to write
2317 * @retlen: pointer to variable to store the number of written bytes
2318 * @buf: the data to write
2af7c653
SK		 2319 *
2320 * NAND write with ECC. Used when performing writes in interrupt context, this
2321 * may for example be called by mtdoops when writing an oops while in panic.
2322 */
2323static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2324 size_t *retlen, const uint8_t *buf)
2325{
2326 struct nand_chip *chip = mtd->priv;
4a89ff88 2327 struct mtd_oob_ops ops;
2af7c653
SK		 2328 int ret;
2329
8b6e50c9 2330 /* Wait for the device to get ready */
2af7c653
SK		 2331 panic_nand_wait(mtd, chip, 400);
2332
8b6e50c9 2333 /* Grab the device */
2af7c653
SK		 2334 panic_nand_get_device(chip, mtd, FL_WRITING);
2335
4a89ff88
BN		 2336 ops.len = len;
2337 ops.datbuf = (uint8_t *)buf;
2338 ops.oobbuf = NULL;
23b1a99b 2339 ops.mode = 0;
2af7c653 2340
4a89ff88 2341 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2342
4a89ff88 2343 *retlen = ops.retlen;
2af7c653
SK		 2344 return ret;
2345}
2346
f75e5097 2347/**
8593fbc6 2348 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2349 * @mtd: MTD device structure
2350 * @to: offset to write to
2351 * @len: number of bytes to write
2352 * @retlen: pointer to variable to store the number of written bytes
2353 * @buf: the data to write
f75e5097 2354 *
8b6e50c9 2355 * NAND write with ECC.
f75e5097 2356 */
8593fbc6
TG		 2357static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2358 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2359{
2360 struct nand_chip *chip = mtd->priv;
4a89ff88 2361 struct mtd_oob_ops ops;
f75e5097
TG		 2362 int ret;
2363
7bc3312b 2364 nand_get_device(chip, mtd, FL_WRITING);
4a89ff88
BN		 2365 ops.len = len;
2366 ops.datbuf = (uint8_t *)buf;
2367 ops.oobbuf = NULL;
23b1a99b 2368 ops.mode = 0;
4a89ff88 2369 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2370 *retlen = ops.retlen;
f75e5097 2371 nand_release_device(mtd);
8593fbc6 2372 return ret;
f75e5097 2373}
7314e9e7 2374
1da177e4 2375/**
8593fbc6 2376 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2377 * @mtd: MTD device structure
2378 * @to: offset to write to
2379 * @ops: oob operation description structure
1da177e4 2380 *
8b6e50c9 2381 * NAND write out-of-band.
1da177e4 2382 */
8593fbc6
TG		 2383static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2384 struct mtd_oob_ops *ops)
1da177e4 2385{
03736155 2386 int chipnr, page, status, len;
ace4dfee 2387 struct nand_chip *chip = mtd->priv;
1da177e4 2388
289c0522 2389 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2390 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2391
0612b9dd 2392 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2393 len = chip->ecc.layout->oobavail;
2394 else
2395 len = mtd->oobsize;
2396
1da177e4 2397 /* Do not allow write past end of page */
03736155 2398 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2399 pr_debug("%s: attempt to write past end of page\n",
2400 __func__);
1da177e4
LT		 2401 return -EINVAL;
2402 }
2403
03736155 2404 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2405 pr_debug("%s: attempt to start write outside oob\n",
2406 __func__);
03736155
AH		 2407 return -EINVAL;
2408 }
2409
775adc3d 2410 /* Do not allow write past end of device */
03736155
AH		 2411 if (unlikely(to >= mtd->size ||
2412 ops->ooboffs + ops->ooblen >
2413 ((mtd->size >> chip->page_shift) -
2414 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2415 pr_debug("%s: attempt to write beyond end of device\n",
2416 __func__);
03736155
AH		 2417 return -EINVAL;
2418 }
2419
7314e9e7 2420 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2421 chip->select_chip(mtd, chipnr);
1da177e4 2422
7314e9e7
TG		 2423 /* Shift to get page */
2424 page = (int)(to >> chip->page_shift);
2425
2426 /*
2427 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2428 * of my DiskOnChip 2000 test units) will clear the whole data page too
2429 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2430 * it in the doc2000 driver in August 1999. dwmw2.
2431 */
ace4dfee 2432 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2433
2434 /* Check, if it is write protected */
2435 if (nand_check_wp(mtd))
8593fbc6 2436 return -EROFS;
61b03bd7 2437
1da177e4 2438 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2439 if (page == chip->pagebuf)
2440 chip->pagebuf = -1;
1da177e4 2441
f722013e 2442 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2443
0612b9dd 2444 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2445 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2446 else
2447 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2448
7bc3312b
TG		 2449 if (status)
2450 return status;
1da177e4 2451
7014568b 2452 ops->oobretlen = ops->ooblen;
1da177e4 2453
7bc3312b 2454 return 0;
8593fbc6
TG		 2455}
2456
2457/**
2458 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2459 * @mtd: MTD device structure
2460 * @to: offset to write to
2461 * @ops: oob operation description structure
8593fbc6
TG		 2462 */
2463static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2464 struct mtd_oob_ops *ops)
2465{
8593fbc6
TG		 2466 struct nand_chip *chip = mtd->priv;
2467 int ret = -ENOTSUPP;
2468
2469 ops->retlen = 0;
2470
2471 /* Do not allow writes past end of device */
7014568b 2472 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2473 pr_debug("%s: attempt to write beyond end of device\n",
2474 __func__);
8593fbc6
TG		 2475 return -EINVAL;
2476 }
2477
7bc3312b 2478 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2479
f8ac0414 2480 switch (ops->mode) {
0612b9dd
BN		 2481 case MTD_OPS_PLACE_OOB:
2482 case MTD_OPS_AUTO_OOB:
2483 case MTD_OPS_RAW:
8593fbc6
TG		 2484 break;
2485
2486 default:
2487 goto out;
2488 }
2489
2490 if (!ops->datbuf)
2491 ret = nand_do_write_oob(mtd, to, ops);
2492 else
2493 ret = nand_do_write_ops(mtd, to, ops);
2494
7351d3a5 2495out:
1da177e4 2496 nand_release_device(mtd);
1da177e4
LT		 2497 return ret;
2498}
2499
1da177e4 2500/**
7854d3f7 2501 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2502 * @mtd: MTD device structure
2503 * @page: the page address of the block which will be erased
1da177e4 2504 *
8b6e50c9 2505 * Standard erase command for NAND chips.
1da177e4 2506 */
e0c7d767 2507static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2508{
ace4dfee 2509 struct nand_chip *chip = mtd->priv;
1da177e4 2510 /* Send commands to erase a block */
ace4dfee
TG		 2511 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2512 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2513}
2514
2515/**
7854d3f7 2516 * multi_erase_cmd - [GENERIC] AND specific block erase command function
8b6e50c9
BN		 2517 * @mtd: MTD device structure
2518 * @page: the page address of the block which will be erased
1da177e4 2519 *
8b6e50c9 2520 * AND multi block erase command function. Erase 4 consecutive blocks.
1da177e4 2521 */
e0c7d767 2522static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2523{
ace4dfee 2524 struct nand_chip *chip = mtd->priv;
1da177e4 2525 /* Send commands to erase a block */
ace4dfee
TG		 2526 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2527 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2528 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2529 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2530 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2531}
2532
2533/**
2534 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2535 * @mtd: MTD device structure
2536 * @instr: erase instruction
1da177e4 2537 *
8b6e50c9 2538 * Erase one ore more blocks.
1da177e4 2539 */
e0c7d767 2540static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2541{
e0c7d767 2542 return nand_erase_nand(mtd, instr, 0);
1da177e4 2543}
61b03bd7 2544
30f464b7 2545#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2546/**
7854d3f7 2547 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2548 * @mtd: MTD device structure
2549 * @instr: erase instruction
2550 * @allowbbt: allow erasing the bbt area
1da177e4 2551 *
8b6e50c9 2552 * Erase one ore more blocks.
1da177e4 2553 */
ace4dfee
TG		 2554int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2555 int allowbbt)
1da177e4 2556{
69423d99 2557 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2558 struct nand_chip *chip = mtd->priv;
f8ac0414 2559 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2560 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2561 loff_t len;
1da177e4 2562
289c0522
BN		 2563 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2564 __func__, (unsigned long long)instr->addr,
2565 (unsigned long long)instr->len);
1da177e4 2566
6fe5a6ac 2567 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2568 return -EINVAL;
1da177e4 2569
1da177e4 2570 /* Grab the lock and see if the device is available */
ace4dfee 2571 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2572
2573 /* Shift to get first page */
ace4dfee
TG		 2574 page = (int)(instr->addr >> chip->page_shift);
2575 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2576
2577 /* Calculate pages in each block */
ace4dfee 2578 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2579
2580 /* Select the NAND device */
ace4dfee 2581 chip->select_chip(mtd, chipnr);
1da177e4 2582
1da177e4
LT		 2583 /* Check, if it is write protected */
2584 if (nand_check_wp(mtd)) {
289c0522
BN		 2585 pr_debug("%s: device is write protected!\n",
2586 __func__);
1da177e4
LT		 2587 instr->state = MTD_ERASE_FAILED;
2588 goto erase_exit;
2589 }
2590
ace4dfee
TG		 2591 /*
2592 * If BBT requires refresh, set the BBT page mask to see if the BBT
2593 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2594 * can not be matched. This is also done when the bbt is actually
7854d3f7 2595 * erased to avoid recursive updates.
ace4dfee
TG		 2596 */
2597 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2598 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2599
1da177e4
LT		 2600 /* Loop through the pages */
2601 len = instr->len;
2602
2603 instr->state = MTD_ERASING;
2604
2605 while (len) {
12183a20 2606 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2607 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2608 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2609 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2610 __func__, page);
1da177e4
LT		 2611 instr->state = MTD_ERASE_FAILED;
2612 goto erase_exit;
2613 }
61b03bd7 2614
ace4dfee
TG		 2615 /*
2616 * Invalidate the page cache, if we erase the block which
8b6e50c9 2617 * contains the current cached page.
ace4dfee
TG		 2618 */
2619 if (page <= chip->pagebuf && chip->pagebuf <
2620 (page + pages_per_block))
2621 chip->pagebuf = -1;
1da177e4 2622
ace4dfee 2623 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2624
7bc3312b 2625 status = chip->waitfunc(mtd, chip);
1da177e4 2626
ace4dfee
TG		 2627 /*
2628 * See if operation failed and additional status checks are
2629 * available
2630 */
2631 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2632 status = chip->errstat(mtd, chip, FL_ERASING,
2633 status, page);
068e3c0a 2634
1da177e4 2635 /* See if block erase succeeded */
a4ab4c5d 2636 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2637 pr_debug("%s: failed erase, page 0x%08x\n",
2638 __func__, page);
1da177e4 2639 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2640 instr->fail_addr =
2641 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2642 goto erase_exit;
2643 }
30f464b7 2644
ace4dfee
TG		 2645 /*
2646 * If BBT requires refresh, set the BBT rewrite flag to the
8b6e50c9 2647 * page being erased.
ace4dfee
TG		 2648 */
2649 if (bbt_masked_page != 0xffffffff &&
2650 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2651 rewrite_bbt[chipnr] =
2652 ((loff_t)page << chip->page_shift);
61b03bd7 2653
1da177e4 2654 /* Increment page address and decrement length */
ace4dfee 2655 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2656 page += pages_per_block;
2657
2658 /* Check, if we cross a chip boundary */
ace4dfee 2659 if (len && !(page & chip->pagemask)) {
1da177e4 2660 chipnr++;
ace4dfee
TG		 2661 chip->select_chip(mtd, -1);
2662 chip->select_chip(mtd, chipnr);
30f464b7 2663
ace4dfee
TG		 2664 /*
2665 * If BBT requires refresh and BBT-PERCHIP, set the BBT
8b6e50c9 2666 * page mask to see if this BBT should be rewritten.
ace4dfee
TG		 2667 */
2668 if (bbt_masked_page != 0xffffffff &&
2669 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2670 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2671 BBT_PAGE_MASK;
1da177e4
LT		 2672 }
2673 }
2674 instr->state = MTD_ERASE_DONE;
2675
7351d3a5 2676erase_exit:
1da177e4
LT		 2677
2678 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2679
2680 /* Deselect and wake up anyone waiting on the device */
2681 nand_release_device(mtd);
2682
49defc01
DW		 2683 /* Do call back function */
2684 if (!ret)
2685 mtd_erase_callback(instr);
2686
ace4dfee
TG		 2687 /*
2688 * If BBT requires refresh and erase was successful, rewrite any
8b6e50c9 2689 * selected bad block tables.
ace4dfee
TG		 2690 */
2691 if (bbt_masked_page == 0xffffffff || ret)
2692 return ret;
2693
2694 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2695 if (!rewrite_bbt[chipnr])
2696 continue;
8b6e50c9 2697 /* Update the BBT for chip */
289c0522
BN		 2698 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2699 __func__, chipnr, rewrite_bbt[chipnr],
2700 chip->bbt_td->pages[chipnr]);
ace4dfee 2701 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2702 }
2703
1da177e4
LT		 2704 /* Return more or less happy */
2705 return ret;
2706}
2707
2708/**
2709 * nand_sync - [MTD Interface] sync
8b6e50c9 2710 * @mtd: MTD device structure
1da177e4 2711 *
8b6e50c9 2712 * Sync is actually a wait for chip ready function.
1da177e4 2713 */
e0c7d767 2714static void nand_sync(struct mtd_info *mtd)
1da177e4 2715{
ace4dfee 2716 struct nand_chip *chip = mtd->priv;
1da177e4 2717
289c0522 2718 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2719
2720 /* Grab the lock and see if the device is available */
ace4dfee 2721 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2722 /* Release it and go back */
e0c7d767 2723 nand_release_device(mtd);
1da177e4
LT		 2724}
2725
1da177e4 2726/**
ace4dfee 2727 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2728 * @mtd: MTD device structure
2729 * @offs: offset relative to mtd start
1da177e4 2730 */
ace4dfee 2731static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2732{
ace4dfee 2733 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2734}
2735
2736/**
ace4dfee 2737 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2738 * @mtd: MTD device structure
2739 * @ofs: offset relative to mtd start
1da177e4 2740 */
e0c7d767 2741static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2742{
ace4dfee 2743 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2744 int ret;
2745
f8ac0414
FF		 2746 ret = nand_block_isbad(mtd, ofs);
2747 if (ret) {
8b6e50c9 2748 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2749 if (ret > 0)
2750 return 0;
e0c7d767
DW		 2751 return ret;
2752 }
1da177e4 2753
ace4dfee 2754 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2755}
2756
962034f4
VW		 2757/**
2758 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2759 * @mtd: MTD device structure
962034f4
VW		 2760 */
2761static int nand_suspend(struct mtd_info *mtd)
2762{
ace4dfee 2763 struct nand_chip *chip = mtd->priv;
962034f4 2764
ace4dfee 2765 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2766}
2767
2768/**
2769 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2770 * @mtd: MTD device structure
962034f4
VW		 2771 */
2772static void nand_resume(struct mtd_info *mtd)
2773{
ace4dfee 2774 struct nand_chip *chip = mtd->priv;
962034f4 2775
ace4dfee 2776 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2777 nand_release_device(mtd);
2778 else
d0370219
BN		 2779 pr_err("%s called for a chip which is not in suspended state\n",
2780 __func__);
962034f4
VW		 2781}
2782
8b6e50c9 2783/* Set default functions */
ace4dfee 2784static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2785{
1da177e4 2786 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2787 if (!chip->chip_delay)
2788 chip->chip_delay = 20;
1da177e4
LT		 2789
2790 /* check, if a user supplied command function given */
ace4dfee
TG		 2791 if (chip->cmdfunc == NULL)
2792 chip->cmdfunc = nand_command;
1da177e4
LT		 2793
2794 /* check, if a user supplied wait function given */
ace4dfee
TG		 2795 if (chip->waitfunc == NULL)
2796 chip->waitfunc = nand_wait;
2797
2798 if (!chip->select_chip)
2799 chip->select_chip = nand_select_chip;
2800 if (!chip->read_byte)
2801 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2802 if (!chip->read_word)
2803 chip->read_word = nand_read_word;
2804 if (!chip->block_bad)
2805 chip->block_bad = nand_block_bad;
2806 if (!chip->block_markbad)
2807 chip->block_markbad = nand_default_block_markbad;
2808 if (!chip->write_buf)
2809 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2810 if (!chip->read_buf)
2811 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2812 if (!chip->verify_buf)
2813 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2814 if (!chip->scan_bbt)
2815 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2816
2817 if (!chip->controller) {
2818 chip->controller = &chip->hwcontrol;
2819 spin_lock_init(&chip->controller->lock);
2820 init_waitqueue_head(&chip->controller->wq);
2821 }
2822
7aa65bfd
TG		 2823}
2824
8b6e50c9 2825/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2826static void sanitize_string(uint8_t *s, size_t len)
2827{
2828 ssize_t i;
2829
8b6e50c9 2830 /* Null terminate */
d1e1f4e4
FF		 2831 s[len - 1] = 0;
2832
8b6e50c9 2833 /* Remove non printable chars */
d1e1f4e4
FF		 2834 for (i = 0; i < len - 1; i++) {
2835 if (s[i] < ' ' || s[i] > 127)
2836 s[i] = '?';
2837 }
2838
8b6e50c9 2839 /* Remove trailing spaces */
d1e1f4e4
FF		 2840 strim(s);
2841}
2842
2843static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2844{
2845 int i;
2846 while (len--) {
2847 crc ^= *p++ << 8;
2848 for (i = 0; i < 8; i++)
2849 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2850 }
2851
2852 return crc;
2853}
2854
6fb277ba 2855/*
8b6e50c9 2856 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2857 */
2858static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2859 int *busw)
6fb277ba
FF		 2860{
2861 struct nand_onfi_params *p = &chip->onfi_params;
2862 int i;
2863 int val;
2864
7854d3f7 2865 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2866 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2867 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2868 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2869 return 0;
2870
6fb277ba
FF		 2871 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2872 for (i = 0; i < 3; i++) {
2873 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2874 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2875 le16_to_cpu(p->crc)) {
9a4d4d69 2876 pr_info("ONFI param page %d valid\n", i);
6fb277ba
FF		 2877 break;
2878 }
2879 }
2880
2881 if (i == 3)
2882 return 0;
2883
8b6e50c9 2884 /* Check version */
6fb277ba 2885 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2886 if (val & (1 << 5))
2887 chip->onfi_version = 23;
2888 else if (val & (1 << 4))
6fb277ba
FF		 2889 chip->onfi_version = 22;
2890 else if (val & (1 << 3))
2891 chip->onfi_version = 21;
2892 else if (val & (1 << 2))
2893 chip->onfi_version = 20;
b7b1a29d 2894 else if (val & (1 << 1))
6fb277ba 2895 chip->onfi_version = 10;
b7b1a29d
BN		 2896 else
2897 chip->onfi_version = 0;
2898
2899 if (!chip->onfi_version) {
d0370219 2900 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 2901 return 0;
2902 }
6fb277ba
FF		 2903
2904 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2905 sanitize_string(p->model, sizeof(p->model));
2906 if (!mtd->name)
2907 mtd->name = p->model;
2908 mtd->writesize = le32_to_cpu(p->byte_per_page);
2909 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2910 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
63795755
MC		 2911 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2912 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
08c248fb 2913 *busw = 0;
6fb277ba 2914 if (le16_to_cpu(p->features) & 1)
08c248fb 2915 *busw = NAND_BUSWIDTH_16;
6fb277ba
FF		 2916
2917 chip->options &= ~NAND_CHIPOPTIONS_MSK;
1826dbcc 2918 chip->options |= NAND_NO_READRDY & NAND_CHIPOPTIONS_MSK;
6fb277ba 2919
d42b5de3 2920 pr_info("ONFI flash detected\n");
6fb277ba
FF		 2921 return 1;
2922}
2923
7aa65bfd 2924/*
8b6e50c9 2925 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 2926 */
2927static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2928 struct nand_chip *chip,
7351d3a5
FF		 2929 int busw,
2930 int *maf_id, int *dev_id,
5e81e88a 2931 struct nand_flash_dev *type)
7aa65bfd 2932{
d1e1f4e4 2933 int i, maf_idx;
426c457a 2934 u8 id_data[8];
6fb277ba 2935 int ret;
1da177e4
LT		 2936
2937 /* Select the device */
ace4dfee 2938 chip->select_chip(mtd, 0);
1da177e4 2939
ef89a880
KB		 2940 /*
2941 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 2942 * after power-up.
ef89a880
KB		 2943 */
2944 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2945
1da177e4 2946 /* Send the command for reading device ID */
ace4dfee 2947 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2948
2949 /* Read manufacturer and device IDs */
ace4dfee 2950 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2951 *dev_id = chip->read_byte(mtd);
1da177e4 2952
8b6e50c9
BN		 2953 /*
2954 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 2955 * interface concerns can cause random data which looks like a
2956 * possibly credible NAND flash to appear. If the two results do
2957 * not match, ignore the device completely.
2958 */
2959
2960 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2961
d1e1f4e4 2962 for (i = 0; i < 2; i++)
426c457a 2963 id_data[i] = chip->read_byte(mtd);
ed8165c7 2964
d1e1f4e4 2965 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 2966 pr_info("%s: second ID read did not match "
d0370219
BN		 2967 "%02x,%02x against %02x,%02x\n", __func__,
2968 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2969 return ERR_PTR(-ENODEV);
2970 }
2971
7aa65bfd 2972 if (!type)
5e81e88a
DW		 2973 type = nand_flash_ids;
2974
2975 for (; type->name != NULL; type++)
d1e1f4e4 2976 if (*dev_id == type->id)
f8ac0414 2977 break;
5e81e88a 2978
d1e1f4e4
FF		 2979 chip->onfi_version = 0;
2980 if (!type->name || !type->pagesize) {
6fb277ba 2981 /* Check is chip is ONFI compliant */
08c248fb 2982 ret = nand_flash_detect_onfi(mtd, chip, &busw);
6fb277ba
FF		 2983 if (ret)
2984 goto ident_done;
d1e1f4e4
FF		 2985 }
2986
2987 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2988
2989 /* Read entire ID string */
2990
2991 for (i = 0; i < 8; i++)
2992 id_data[i] = chip->read_byte(mtd);
2993
5e81e88a 2994 if (!type->name)
7aa65bfd
TG		 2995 return ERR_PTR(-ENODEV);
2996
ba0251fe
TG		 2997 if (!mtd->name)
2998 mtd->name = type->name;
2999
69423d99 3000 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3001
12a40a57 3002 if (!type->pagesize && chip->init_size) {
8b6e50c9 3003 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3004 busw = chip->init_size(mtd, chip, id_data);
3005 } else if (!type->pagesize) {
7aa65bfd 3006 int extid;
29072b96 3007 /* The 3rd id byte holds MLC / multichip data */
426c457a 3008 chip->cellinfo = id_data[2];
7aa65bfd 3009 /* The 4th id byte is the important one */
426c457a 3010 extid = id_data[3];
61b03bd7 3011
426c457a
KC		 3012 /*
3013 * Field definitions are in the following datasheets:
3014 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 3015 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 3016 *
3017 * Check for wraparound + Samsung ID + nonzero 6th byte
3018 * to decide what to do.
3019 */
3020 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3021 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 3022 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 3023 id_data[5] != 0x00) {
3024 /* Calc pagesize */
3025 mtd->writesize = 2048 << (extid & 0x03);
3026 extid >>= 2;
3027 /* Calc oobsize */
34c5bf6c
BN		 3028 switch (extid & 0x03) {
3029 case 1:
3030 mtd->oobsize = 128;
3031 break;
3032 case 2:
3033 mtd->oobsize = 218;
3034 break;
3035 case 3:
3036 mtd->oobsize = 400;
3037 break;
3038 default:
3039 mtd->oobsize = 436;
3040 break;
3041 }
426c457a
KC		 3042 extid >>= 2;
3043 /* Calc blocksize */
3044 mtd->erasesize = (128 * 1024) <<
3045 (((extid >> 1) & 0x04) | (extid & 0x03));
3046 busw = 0;
3047 } else {
3048 /* Calc pagesize */
3049 mtd->writesize = 1024 << (extid & 0x03);
3050 extid >>= 2;
3051 /* Calc oobsize */
3052 mtd->oobsize = (8 << (extid & 0x01)) *
3053 (mtd->writesize >> 9);
3054 extid >>= 2;
3055 /* Calc blocksize. Blocksize is multiples of 64KiB */
3056 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3057 extid >>= 2;
3058 /* Get buswidth information */
3059 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3060 }
7aa65bfd
TG		 3061 } else {
3062 /*
8b6e50c9 3063 * Old devices have chip data hardcoded in the device id table.
7aa65bfd 3064 */
ba0251fe
TG		 3065 mtd->erasesize = type->erasesize;
3066 mtd->writesize = type->pagesize;
4cbb9b80 3067 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3068 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3069
3070 /*
3071 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3072 * some Spansion chips have erasesize that conflicts with size
8b6e50c9 3073 * listed in nand_ids table.
2173bae8
BN		 3074 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3075 */
3076 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3077 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3078 id_data[7] == 0x00 && mtd->writesize == 512) {
3079 mtd->erasesize = 128 * 1024;
3080 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3081 }
7aa65bfd 3082 }
d1e1f4e4
FF		 3083 /* Get chip options, preserve non chip based options */
3084 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3085 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3086
8b6e50c9
BN		 3087 /*
3088 * Check if chip is not a Samsung device. Do not clear the
3089 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3090 */
3091 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3092 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3093ident_done:
3094
7aa65bfd 3095 /* Try to identify manufacturer */
9a909867 3096 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3097 if (nand_manuf_ids[maf_idx].id == *maf_id)
3098 break;
3099 }
0ea4a755 3100
7aa65bfd
TG		 3101 /*
3102 * Check, if buswidth is correct. Hardware drivers should set
8b6e50c9 3103 * chip correct!
7aa65bfd 3104 */
ace4dfee 3105 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
9a4d4d69 3106 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 3107 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3108 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 3109 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 3110 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3111 busw ? 16 : 8);
7aa65bfd
TG		 3112 return ERR_PTR(-EINVAL);
3113 }
61b03bd7 3114
7aa65bfd 3115 /* Calculate the address shift from the page size */
ace4dfee 3116 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3117 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3118 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3119
ace4dfee 3120 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3121 ffs(mtd->erasesize) - 1;
69423d99
AH		 3122 if (chip->chipsize & 0xffffffff)
3123 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3124 else {
3125 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3126 chip->chip_shift += 32 - 1;
3127 }
1da177e4 3128
26d9be11
AB		 3129 chip->badblockbits = 8;
3130
7aa65bfd 3131 /* Set the bad block position */
065a1ed8 3132 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3133 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3134 else
3135 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3136
b60b08b0
KC		 3137 /*
3138 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3139 * on Samsung and Hynix MLC devices; stored in first two pages
3140 * of each block on Micron devices with 2KiB pages and on
8c342335
BN		 3141 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
3142 * All others scan only the first page.
b60b08b0
KC		 3143 */
3144 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3145 (*maf_id == NAND_MFR_SAMSUNG ||
3146 *maf_id == NAND_MFR_HYNIX))
5fb1549d 3147 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3148 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3149 (*maf_id == NAND_MFR_SAMSUNG ||
3150 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3151 *maf_id == NAND_MFR_TOSHIBA ||
8c342335
BN		 3152 *maf_id == NAND_MFR_AMD ||
3153 *maf_id == NAND_MFR_MACRONIX)) ||
c7b28e25
BN		 3154 (mtd->writesize == 2048 &&
3155 *maf_id == NAND_MFR_MICRON))
5fb1549d 3156 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
c7b28e25 3157
7aa65bfd 3158 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3159 if (chip->options & NAND_4PAGE_ARRAY)
3160 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3161 else
ace4dfee 3162 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3163
8b6e50c9 3164 /* Do not replace user supplied command function! */
ace4dfee
TG		 3165 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3166 chip->cmdfunc = nand_command_lp;
7aa65bfd 3167
886bd33d
HS		 3168 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3169 " page size: %d, OOB size: %d\n",
3170 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3171 chip->onfi_version ? chip->onfi_params.model : type->name,
3172 mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3173
3174 return type;
3175}
3176
7aa65bfd 3177/**
3b85c321 3178 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3179 * @mtd: MTD device structure
3180 * @maxchips: number of chips to scan for
3181 * @table: alternative NAND ID table
7aa65bfd 3182 *
8b6e50c9
BN		 3183 * This is the first phase of the normal nand_scan() function. It reads the
3184 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3185 *
3b85c321 3186 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3187 */
5e81e88a
DW		 3188int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3189 struct nand_flash_dev *table)
7aa65bfd 3190{
d1e1f4e4 3191 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3192 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3193 struct nand_flash_dev *type;
3194
7aa65bfd 3195 /* Get buswidth to select the correct functions */
ace4dfee 3196 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3197 /* Set the default functions */
ace4dfee 3198 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3199
3200 /* Read the flash type */
7351d3a5
FF		 3201 type = nand_get_flash_type(mtd, chip, busw,
3202 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3203
3204 if (IS_ERR(type)) {
b1c6e6db 3205 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3206 pr_warn("No NAND device found\n");
ace4dfee 3207 chip->select_chip(mtd, -1);
7aa65bfd 3208 return PTR_ERR(type);
1da177e4
LT		 3209 }
3210
7aa65bfd 3211 /* Check for a chip array */
e0c7d767 3212 for (i = 1; i < maxchips; i++) {
ace4dfee 3213 chip->select_chip(mtd, i);
ef89a880
KB		 3214 /* See comment in nand_get_flash_type for reset */
3215 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3216 /* Send the command for reading device ID */
ace4dfee 3217 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3218 /* Read manufacturer and device IDs */
ace4dfee 3219 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3220 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3221 break;
3222 }
3223 if (i > 1)
9a4d4d69 3224 pr_info("%d NAND chips detected\n", i);
61b03bd7 3225
1da177e4 3226 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3227 chip->numchips = i;
3228 mtd->size = i * chip->chipsize;
7aa65bfd 3229
3b85c321
DW		 3230 return 0;
3231}
7351d3a5 3232EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3233
3234
3235/**
3236 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3237 * @mtd: MTD device structure
3b85c321 3238 *
8b6e50c9
BN		 3239 * This is the second phase of the normal nand_scan() function. It fills out
3240 * all the uninitialized function pointers with the defaults and scans for a
3241 * bad block table if appropriate.
3b85c321
DW		 3242 */
3243int nand_scan_tail(struct mtd_info *mtd)
3244{
3245 int i;
3246 struct nand_chip *chip = mtd->priv;
3247
e2414f4c
BN		 3248 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3249 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3250 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3251
4bf63fcb
DW		 3252 if (!(chip->options & NAND_OWN_BUFFERS))
3253 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3254 if (!chip->buffers)
3255 return -ENOMEM;
3256
7dcdcbef 3257 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3258 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3259
7aa65bfd 3260 /*
8b6e50c9 3261 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3262 */
193bd400 3263 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3264 switch (mtd->oobsize) {
1da177e4 3265 case 8:
5bd34c09 3266 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3267 break;
3268 case 16:
5bd34c09 3269 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3270 break;
3271 case 64:
5bd34c09 3272 chip->ecc.layout = &nand_oob_64;
1da177e4 3273 break;
81ec5364
TG		 3274 case 128:
3275 chip->ecc.layout = &nand_oob_128;
3276 break;
1da177e4 3277 default:
d0370219
BN		 3278 pr_warn("No oob scheme defined for oobsize %d\n",
3279 mtd->oobsize);
1da177e4
LT		 3280 BUG();
3281 }
3282 }
61b03bd7 3283
956e944c
DW		 3284 if (!chip->write_page)
3285 chip->write_page = nand_write_page;
3286
61b03bd7 3287 /*
8b6e50c9 3288 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3289 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3290 */
956e944c 3291
ace4dfee 3292 switch (chip->ecc.mode) {
6e0cb135
SN		 3293 case NAND_ECC_HW_OOB_FIRST:
3294 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3295 if (!chip->ecc.calculate || !chip->ecc.correct ||
3296 !chip->ecc.hwctl) {
9a4d4d69 3297 pr_warn("No ECC functions supplied; "
d0370219 3298 "hardware ECC not possible\n");
6e0cb135
SN		 3299 BUG();
3300 }
3301 if (!chip->ecc.read_page)
3302 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3303
6dfc6d25 3304 case NAND_ECC_HW:
8b6e50c9 3305 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3306 if (!chip->ecc.read_page)
3307 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3308 if (!chip->ecc.write_page)
3309 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3310 if (!chip->ecc.read_page_raw)
3311 chip->ecc.read_page_raw = nand_read_page_raw;
3312 if (!chip->ecc.write_page_raw)
3313 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3314 if (!chip->ecc.read_oob)
3315 chip->ecc.read_oob = nand_read_oob_std;
3316 if (!chip->ecc.write_oob)
3317 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3318
6dfc6d25 3319 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3320 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3321 !chip->ecc.hwctl) &&
3322 (!chip->ecc.read_page ||
1c45f604 3323 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3324 !chip->ecc.write_page ||
1c45f604 3325 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 3326 pr_warn("No ECC functions supplied; "
d0370219 3327 "hardware ECC not possible\n");
6dfc6d25
TG		 3328 BUG();
3329 }
8b6e50c9 3330 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3331 if (!chip->ecc.read_page)
3332 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3333 if (!chip->ecc.write_page)
3334 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3335 if (!chip->ecc.read_page_raw)
3336 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3337 if (!chip->ecc.write_page_raw)
3338 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3339 if (!chip->ecc.read_oob)
3340 chip->ecc.read_oob = nand_read_oob_syndrome;
3341 if (!chip->ecc.write_oob)
3342 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3343
e2788c98
MD		 3344 if (mtd->writesize >= chip->ecc.size) {
3345 if (!chip->ecc.strength) {
3346 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3347 BUG();
3348 }
6dfc6d25 3349 break;
e2788c98 3350 }
9a4d4d69 3351 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 3352 "%d byte page size, fallback to SW ECC\n",
3353 chip->ecc.size, mtd->writesize);
ace4dfee 3354 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3355
6dfc6d25 3356 case NAND_ECC_SOFT:
ace4dfee
TG		 3357 chip->ecc.calculate = nand_calculate_ecc;
3358 chip->ecc.correct = nand_correct_data;
f5bbdacc 3359 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3360 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3361 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3362 chip->ecc.read_page_raw = nand_read_page_raw;
3363 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3364 chip->ecc.read_oob = nand_read_oob_std;
3365 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3366 if (!chip->ecc.size)
3367 chip->ecc.size = 256;
ace4dfee 3368 chip->ecc.bytes = 3;
6a918bad 3369 chip->ecc.strength = 1;
1da177e4 3370 break;
61b03bd7 3371
193bd400
ID		 3372 case NAND_ECC_SOFT_BCH:
3373 if (!mtd_nand_has_bch()) {
9a4d4d69 3374 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3375 BUG();
3376 }
3377 chip->ecc.calculate = nand_bch_calculate_ecc;
3378 chip->ecc.correct = nand_bch_correct_data;
3379 chip->ecc.read_page = nand_read_page_swecc;
3380 chip->ecc.read_subpage = nand_read_subpage;
3381 chip->ecc.write_page = nand_write_page_swecc;
3382 chip->ecc.read_page_raw = nand_read_page_raw;
3383 chip->ecc.write_page_raw = nand_write_page_raw;
3384 chip->ecc.read_oob = nand_read_oob_std;
3385 chip->ecc.write_oob = nand_write_oob_std;
3386 /*
3387 * Board driver should supply ecc.size and ecc.bytes values to
3388 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3389 * for details. Otherwise, default to 4 bits for large page
3390 * devices.
193bd400
ID		 3391 */
3392 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3393 chip->ecc.size = 512;
3394 chip->ecc.bytes = 7;
3395 }
3396 chip->ecc.priv = nand_bch_init(mtd,
3397 chip->ecc.size,
3398 chip->ecc.bytes,
3399 &chip->ecc.layout);
3400 if (!chip->ecc.priv) {
9a4d4d69 3401 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3402 BUG();
3403 }
6a918bad 3404 chip->ecc.strength =
e2788c98 3405 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
193bd400
ID		 3406 break;
3407
61b03bd7 3408 case NAND_ECC_NONE:
9a4d4d69 3409 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3410 "This is not recommended!\n");
8593fbc6
TG		 3411 chip->ecc.read_page = nand_read_page_raw;
3412 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3413 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3414 chip->ecc.read_page_raw = nand_read_page_raw;
3415 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3416 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3417 chip->ecc.size = mtd->writesize;
3418 chip->ecc.bytes = 0;
6a918bad 3419 chip->ecc.strength = 0;
1da177e4 3420 break;
956e944c 3421
1da177e4 3422 default:
d0370219 3423 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 3424 BUG();
1da177e4 3425 }
61b03bd7 3426
9ce244b3 3427 /* For many systems, the standard OOB write also works for raw */
c46f6483
BN		 3428 if (!chip->ecc.read_oob_raw)
3429 chip->ecc.read_oob_raw = chip->ecc.read_oob;
9ce244b3
BN		 3430 if (!chip->ecc.write_oob_raw)
3431 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3432
5bd34c09
TG		 3433 /*
3434 * The number of bytes available for a client to place data into
8b6e50c9 3435 * the out of band area.
5bd34c09
TG		 3436 */
3437 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3438 for (i = 0; chip->ecc.layout->oobfree[i].length
3439 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3440 chip->ecc.layout->oobavail +=
3441 chip->ecc.layout->oobfree[i].length;
1f92267c 3442 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3443
7aa65bfd
TG		 3444 /*
3445 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3446 * mode.
7aa65bfd 3447 */
ace4dfee 3448 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3449 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 3450 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3451 BUG();
1da177e4 3452 }
f5bbdacc 3453 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3454
8b6e50c9 3455 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 3456 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3457 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3458 switch (chip->ecc.steps) {
29072b96
TG		 3459 case 2:
3460 mtd->subpage_sft = 1;
3461 break;
3462 case 4:
3463 case 8:
81ec5364 3464 case 16:
29072b96
TG		 3465 mtd->subpage_sft = 2;
3466 break;
3467 }
3468 }
3469 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3470
04bbd0ea 3471 /* Initialize state */
ace4dfee 3472 chip->state = FL_READY;
1da177e4
LT		 3473
3474 /* De-select the device */
ace4dfee 3475 chip->select_chip(mtd, -1);
1da177e4
LT		 3476
3477 /* Invalidate the pagebuffer reference */
ace4dfee 3478 chip->pagebuf = -1;
1da177e4
LT		 3479
3480 /* Fill in remaining MTD driver data */
3481 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3482 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3483 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 3484 mtd->_erase = nand_erase;
3485 mtd->_point = NULL;
3486 mtd->_unpoint = NULL;
3487 mtd->_read = nand_read;
3488 mtd->_write = nand_write;
3489 mtd->_panic_write = panic_nand_write;
3490 mtd->_read_oob = nand_read_oob;
3491 mtd->_write_oob = nand_write_oob;
3492 mtd->_sync = nand_sync;
3493 mtd->_lock = NULL;
3494 mtd->_unlock = NULL;
3495 mtd->_suspend = nand_suspend;
3496 mtd->_resume = nand_resume;
3497 mtd->_block_isbad = nand_block_isbad;
3498 mtd->_block_markbad = nand_block_markbad;
cbcab65a 3499 mtd->writebufsize = mtd->writesize;
1da177e4 3500
6a918bad 3501 /* propagate ecc info to mtd_info */
5bd34c09 3502 mtd->ecclayout = chip->ecc.layout;
86c2072b 3503 mtd->ecc_strength = chip->ecc.strength;
ea3b2ea2
SL		 3504 /*
3505 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3506 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3507 * properly set.
3508 */
3509 if (!mtd->bitflip_threshold)
3510 mtd->bitflip_threshold = mtd->ecc_strength;
1da177e4 3511
0040bf38 3512 /* Check, if we should skip the bad block table scan */
ace4dfee 3513 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3514 return 0;
1da177e4
LT		 3515
3516 /* Build bad block table */
ace4dfee 3517 return chip->scan_bbt(mtd);
1da177e4 3518}
7351d3a5 3519EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3520
8b6e50c9
BN		 3521/*
3522 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3523 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3524 * to call us from in-kernel code if the core NAND support is modular.
3525 */
3b85c321
DW		 3526#ifdef MODULE
3527#define caller_is_module() (1)
3528#else
3529#define caller_is_module() \
a6e6abd5 3530 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3531#endif
3532
3533/**
3534 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3535 * @mtd: MTD device structure
3536 * @maxchips: number of chips to scan for
3b85c321 3537 *
8b6e50c9
BN		 3538 * This fills out all the uninitialized function pointers with the defaults.
3539 * The flash ID is read and the mtd/chip structures are filled with the
3540 * appropriate values. The mtd->owner field must be set to the module of the
3541 * caller.
3b85c321
DW		 3542 */
3543int nand_scan(struct mtd_info *mtd, int maxchips)
3544{
3545 int ret;
3546
3547 /* Many callers got this wrong, so check for it for a while... */
3548 if (!mtd->owner && caller_is_module()) {
d0370219 3549 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3550 BUG();
3551 }
3552
5e81e88a 3553 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3554 if (!ret)
3555 ret = nand_scan_tail(mtd);
3556 return ret;
3557}
7351d3a5 3558EXPORT_SYMBOL(nand_scan);
3b85c321 3559
1da177e4 3560/**
61b03bd7 3561 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3562 * @mtd: MTD device structure
3563 */
e0c7d767 3564void nand_release(struct mtd_info *mtd)
1da177e4 3565{
ace4dfee 3566 struct nand_chip *chip = mtd->priv;
1da177e4 3567
193bd400
ID		 3568 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3569 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3570
5ffcaf3d 3571 mtd_device_unregister(mtd);
1da177e4 3572
fa671646 3573 /* Free bad block table memory */
ace4dfee 3574 kfree(chip->bbt);
4bf63fcb
DW		 3575 if (!(chip->options & NAND_OWN_BUFFERS))
3576 kfree(chip->buffers);
58373ff0
BN		 3577
3578 /* Free bad block descriptor memory */
3579 if (chip->badblock_pattern && chip->badblock_pattern->options
3580 & NAND_BBT_DYNAMICSTRUCT)
3581 kfree(chip->badblock_pattern);
1da177e4 3582}
e0c7d767 3583EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3584
3585static int __init nand_base_init(void)
3586{
3587 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3588 return 0;
3589}
3590
3591static void __exit nand_base_exit(void)
3592{
3593 led_trigger_unregister_simple(nand_led_trigger);
3594}
3595
3596module_init(nand_base_init);
3597module_exit(nand_base_exit);
3598
e0c7d767 3599MODULE_LICENSE("GPL");
7351d3a5
FF		 3600MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3601MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3602MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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