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mtd: blkdevs: remove dead code
[deliverable/linux.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
61b03bd7 7 *
1da177e4 8 * Additional technical information is available on
8b2b403c 9 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 10 *
1da177e4 11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 13 *
ace4dfee 14 * Credits:
61b03bd7
TG		 15 * David Woodhouse for adding multichip support
16 *
1da177e4
LT		 17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
19 *
ace4dfee 20 * TODO:
1da177e4
LT		 21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 23 * if we have HW ECC support.
c0b8ba7b 24 * BBT table is not serialized, has to be fixed
1da177e4 25 *
1da177e4
LT		 26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
29 *
30 */
31
20171642
EG		 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
552d9205 34#include <linux/module.h>
1da177e4
LT		 35#include <linux/delay.h>
36#include <linux/errno.h>
7aa65bfd 37#include <linux/err.h>
1da177e4
LT		 38#include <linux/sched.h>
39#include <linux/slab.h>
66507c7b 40#include <linux/mm.h>
1da177e4
LT		 41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4 50#include <linux/mtd/partitions.h>
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
6a8214aa 96static int nand_get_device(struct mtd_info *mtd, int new_state);
1da177e4 97
8593fbc6
TG		 98static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
99 struct mtd_oob_ops *ops);
100
d470a97c 101/*
8e87d782 102 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 103 * compiled away when LED support is disabled.
104 */
105DEFINE_LED_TRIGGER(nand_led_trigger);
106
6fe5a6ac
VS		 107static int check_offs_len(struct mtd_info *mtd,
108 loff_t ofs, uint64_t len)
109{
110 struct nand_chip *chip = mtd->priv;
111 int ret = 0;
112
113 /* Start address must align on block boundary */
daae74ca 114 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 115 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 116 ret = -EINVAL;
117 }
118
119 /* Length must align on block boundary */
daae74ca 120 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 121 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 122 ret = -EINVAL;
123 }
124
6fe5a6ac
VS		 125 return ret;
126}
127
1da177e4
LT		 128/**
129 * nand_release_device - [GENERIC] release chip
8b6e50c9 130 * @mtd: MTD device structure
61b03bd7 131 *
b0bb6903 132 * Release chip lock and wake up anyone waiting on the device.
1da177e4 133 */
e0c7d767 134static void nand_release_device(struct mtd_info *mtd)
1da177e4 135{
ace4dfee 136 struct nand_chip *chip = mtd->priv;
1da177e4 137
a36ed299 138 /* Release the controller and the chip */
ace4dfee
TG		 139 spin_lock(&chip->controller->lock);
140 chip->controller->active = NULL;
141 chip->state = FL_READY;
142 wake_up(&chip->controller->wq);
143 spin_unlock(&chip->controller->lock);
1da177e4
LT		 144}
145
146/**
147 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 148 * @mtd: MTD device structure
1da177e4 149 *
7854d3f7 150 * Default read function for 8bit buswidth
1da177e4 151 */
58dd8f2b 152static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 153{
ace4dfee
TG		 154 struct nand_chip *chip = mtd->priv;
155 return readb(chip->IO_ADDR_R);
1da177e4
LT		 156}
157
1da177e4 158/**
7854d3f7 159 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 160 * @mtd: MTD device structure
1da177e4 161 *
7854d3f7
BN		 162 * Default read function for 16bit buswidth with endianness conversion.
163 *
1da177e4 164 */
58dd8f2b 165static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 166{
ace4dfee
TG		 167 struct nand_chip *chip = mtd->priv;
168 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 169}
170
1da177e4
LT		 171/**
172 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 173 * @mtd: MTD device structure
1da177e4 174 *
7854d3f7 175 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 176 */
177static u16 nand_read_word(struct mtd_info *mtd)
178{
ace4dfee
TG		 179 struct nand_chip *chip = mtd->priv;
180 return readw(chip->IO_ADDR_R);
1da177e4
LT		 181}
182
1da177e4
LT		 183/**
184 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 185 * @mtd: MTD device structure
186 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 187 *
188 * Default select function for 1 chip devices.
189 */
ace4dfee 190static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 191{
ace4dfee
TG		 192 struct nand_chip *chip = mtd->priv;
193
194 switch (chipnr) {
1da177e4 195 case -1:
ace4dfee 196 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 197 break;
198 case 0:
1da177e4
LT		 199 break;
200
201 default:
202 BUG();
203 }
204}
205
05f78359
UKK		 206/**
207 * nand_write_byte - [DEFAULT] write single byte to chip
208 * @mtd: MTD device structure
209 * @byte: value to write
210 *
211 * Default function to write a byte to I/O[7:0]
212 */
213static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
214{
215 struct nand_chip *chip = mtd->priv;
216
217 chip->write_buf(mtd, &byte, 1);
218}
219
220/**
221 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
222 * @mtd: MTD device structure
223 * @byte: value to write
224 *
225 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
226 */
227static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
228{
229 struct nand_chip *chip = mtd->priv;
230 uint16_t word = byte;
231
232 /*
233 * It's not entirely clear what should happen to I/O[15:8] when writing
234 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
235 *
236 * When the host supports a 16-bit bus width, only data is
237 * transferred at the 16-bit width. All address and command line
238 * transfers shall use only the lower 8-bits of the data bus. During
239 * command transfers, the host may place any value on the upper
240 * 8-bits of the data bus. During address transfers, the host shall
241 * set the upper 8-bits of the data bus to 00h.
242 *
243 * One user of the write_byte callback is nand_onfi_set_features. The
244 * four parameters are specified to be written to I/O[7:0], but this is
245 * neither an address nor a command transfer. Let's assume a 0 on the
246 * upper I/O lines is OK.
247 */
248 chip->write_buf(mtd, (uint8_t *)&word, 2);
249}
250
1da177e4
LT		 251/**
252 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 253 * @mtd: MTD device structure
254 * @buf: data buffer
255 * @len: number of bytes to write
1da177e4 256 *
7854d3f7 257 * Default write function for 8bit buswidth.
1da177e4 258 */
58dd8f2b 259static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 260{
ace4dfee 261 struct nand_chip *chip = mtd->priv;
1da177e4 262
76413839 263 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 264}
265
266/**
61b03bd7 267 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 268 * @mtd: MTD device structure
269 * @buf: buffer to store date
270 * @len: number of bytes to read
1da177e4 271 *
7854d3f7 272 * Default read function for 8bit buswidth.
1da177e4 273 */
58dd8f2b 274static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 275{
ace4dfee 276 struct nand_chip *chip = mtd->priv;
1da177e4 277
76413839 278 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 279}
280
1da177e4
LT		 281/**
282 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 283 * @mtd: MTD device structure
284 * @buf: data buffer
285 * @len: number of bytes to write
1da177e4 286 *
7854d3f7 287 * Default write function for 16bit buswidth.
1da177e4 288 */
58dd8f2b 289static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 290{
ace4dfee 291 struct nand_chip *chip = mtd->priv;
1da177e4 292 u16 *p = (u16 *) buf;
61b03bd7 293
76413839 294 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 295}
296
297/**
61b03bd7 298 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 299 * @mtd: MTD device structure
300 * @buf: buffer to store date
301 * @len: number of bytes to read
1da177e4 302 *
7854d3f7 303 * Default read function for 16bit buswidth.
1da177e4 304 */
58dd8f2b 305static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 306{
ace4dfee 307 struct nand_chip *chip = mtd->priv;
1da177e4 308 u16 *p = (u16 *) buf;
1da177e4 309
76413839 310 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 311}
312
1da177e4
LT		 313/**
314 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 315 * @mtd: MTD device structure
316 * @ofs: offset from device start
317 * @getchip: 0, if the chip is already selected
1da177e4 318 *
61b03bd7 319 * Check, if the block is bad.
1da177e4
LT		 320 */
321static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
322{
cdbec050 323 int page, chipnr, res = 0, i = 0;
ace4dfee 324 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 325 u16 bad;
326
5fb1549d 327 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 328 ofs += mtd->erasesize - mtd->writesize;
329
1a12f46a
TK		 330 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
331
1da177e4 332 if (getchip) {
ace4dfee 333 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 334
6a8214aa 335 nand_get_device(mtd, FL_READING);
1da177e4
LT		 336
337 /* Select the NAND device */
ace4dfee 338 chip->select_chip(mtd, chipnr);
1a12f46a 339 }
1da177e4 340
cdbec050
BN		 341 do {
342 if (chip->options & NAND_BUSWIDTH_16) {
343 chip->cmdfunc(mtd, NAND_CMD_READOOB,
344 chip->badblockpos & 0xFE, page);
345 bad = cpu_to_le16(chip->read_word(mtd));
346 if (chip->badblockpos & 0x1)
347 bad >>= 8;
348 else
349 bad &= 0xFF;
350 } else {
351 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
352 page);
353 bad = chip->read_byte(mtd);
354 }
355
356 if (likely(chip->badblockbits == 8))
357 res = bad != 0xFF;
e0b58d0a 358 else
cdbec050
BN		 359 res = hweight8(bad) < chip->badblockbits;
360 ofs += mtd->writesize;
361 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
362 i++;
363 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 364
b0bb6903
HS		 365 if (getchip) {
366 chip->select_chip(mtd, -1);
1da177e4 367 nand_release_device(mtd);
b0bb6903 368 }
61b03bd7 369
1da177e4
LT		 370 return res;
371}
372
373/**
5a0edb25 374 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
8b6e50c9
BN		 375 * @mtd: MTD device structure
376 * @ofs: offset from device start
1da177e4 377 *
8b6e50c9 378 * This is the default implementation, which can be overridden by a hardware
5a0edb25
BN		 379 * specific driver. It provides the details for writing a bad block marker to a
380 * block.
381 */
382static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
383{
384 struct nand_chip *chip = mtd->priv;
385 struct mtd_oob_ops ops;
386 uint8_t buf[2] = { 0, 0 };
387 int ret = 0, res, i = 0;
388
389 ops.datbuf = NULL;
390 ops.oobbuf = buf;
391 ops.ooboffs = chip->badblockpos;
392 if (chip->options & NAND_BUSWIDTH_16) {
393 ops.ooboffs &= ~0x01;
394 ops.len = ops.ooblen = 2;
395 } else {
396 ops.len = ops.ooblen = 1;
397 }
398 ops.mode = MTD_OPS_PLACE_OOB;
399
400 /* Write to first/last page(s) if necessary */
401 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
402 ofs += mtd->erasesize - mtd->writesize;
403 do {
404 res = nand_do_write_oob(mtd, ofs, &ops);
405 if (!ret)
406 ret = res;
407
408 i++;
409 ofs += mtd->writesize;
410 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
411
412 return ret;
413}
414
415/**
416 * nand_block_markbad_lowlevel - mark a block bad
417 * @mtd: MTD device structure
418 * @ofs: offset from device start
419 *
420 * This function performs the generic NAND bad block marking steps (i.e., bad
421 * block table(s) and/or marker(s)). We only allow the hardware driver to
422 * specify how to write bad block markers to OOB (chip->block_markbad).
423 *
b32843b7 424 * We try operations in the following order:
e2414f4c 425 * (1) erase the affected block, to allow OOB marker to be written cleanly
b32843b7
BN		 426 * (2) write bad block marker to OOB area of affected block (unless flag
427 * NAND_BBT_NO_OOB_BBM is present)
428 * (3) update the BBT
429 * Note that we retain the first error encountered in (2) or (3), finish the
e2414f4c 430 * procedures, and dump the error in the end.
1da177e4 431*/
5a0edb25 432static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
1da177e4 433{
ace4dfee 434 struct nand_chip *chip = mtd->priv;
b32843b7 435 int res, ret = 0;
61b03bd7 436
b32843b7 437 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
00918429
BN		 438 struct erase_info einfo;
439
440 /* Attempt erase before marking OOB */
441 memset(&einfo, 0, sizeof(einfo));
442 einfo.mtd = mtd;
443 einfo.addr = ofs;
daae74ca 444 einfo.len = 1ULL << chip->phys_erase_shift;
00918429 445 nand_erase_nand(mtd, &einfo, 0);
1da177e4 446
b32843b7 447 /* Write bad block marker to OOB */
6a8214aa 448 nand_get_device(mtd, FL_WRITING);
5a0edb25 449 ret = chip->block_markbad(mtd, ofs);
c0b8ba7b 450 nand_release_device(mtd);
f1a28c02 451 }
e2414f4c 452
b32843b7
BN		 453 /* Mark block bad in BBT */
454 if (chip->bbt) {
455 res = nand_markbad_bbt(mtd, ofs);
e2414f4c
BN		 456 if (!ret)
457 ret = res;
458 }
459
f1a28c02
TG		 460 if (!ret)
461 mtd->ecc_stats.badblocks++;
c0b8ba7b 462
f1a28c02 463 return ret;
1da177e4
LT		 464}
465
61b03bd7 466/**
1da177e4 467 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 468 * @mtd: MTD device structure
1da177e4 469 *
8b6e50c9
BN		 470 * Check, if the device is write protected. The function expects, that the
471 * device is already selected.
1da177e4 472 */
e0c7d767 473static int nand_check_wp(struct mtd_info *mtd)
1da177e4 474{
ace4dfee 475 struct nand_chip *chip = mtd->priv;
93edbad6 476
8b6e50c9 477 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 478 if (chip->options & NAND_BROKEN_XD)
479 return 0;
480
1da177e4 481 /* Check the WP bit */
ace4dfee
TG		 482 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
483 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 484}
485
8471bb73 486/**
c30e1f79 487 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
8471bb73
EG		 488 * @mtd: MTD device structure
489 * @ofs: offset from device start
490 *
c30e1f79 491 * Check if the block is marked as reserved.
8471bb73
EG		 492 */
493static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
494{
495 struct nand_chip *chip = mtd->priv;
496
497 if (!chip->bbt)
498 return 0;
499 /* Return info from the table */
500 return nand_isreserved_bbt(mtd, ofs);
501}
502
1da177e4
LT		 503/**
504 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 505 * @mtd: MTD device structure
506 * @ofs: offset from device start
507 * @getchip: 0, if the chip is already selected
508 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 509 *
510 * Check, if the block is bad. Either by reading the bad block table or
511 * calling of the scan function.
512 */
2c0a2bed
TG		 513static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
514 int allowbbt)
1da177e4 515{
ace4dfee 516 struct nand_chip *chip = mtd->priv;
61b03bd7 517
ace4dfee
TG		 518 if (!chip->bbt)
519 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 520
1da177e4 521 /* Return info from the table */
e0c7d767 522 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 523}
524
2af7c653
SK		 525/**
526 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 527 * @mtd: MTD device structure
528 * @timeo: Timeout
2af7c653
SK		 529 *
530 * Helper function for nand_wait_ready used when needing to wait in interrupt
531 * context.
532 */
533static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
534{
535 struct nand_chip *chip = mtd->priv;
536 int i;
537
538 /* Wait for the device to get ready */
539 for (i = 0; i < timeo; i++) {
540 if (chip->dev_ready(mtd))
541 break;
542 touch_softlockup_watchdog();
543 mdelay(1);
544 }
545}
546
7854d3f7 547/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 548void nand_wait_ready(struct mtd_info *mtd)
3b88775c 549{
ace4dfee 550 struct nand_chip *chip = mtd->priv;
ca6a2489 551 unsigned long timeo = jiffies + msecs_to_jiffies(20);
3b88775c 552
2af7c653
SK		 553 /* 400ms timeout */
554 if (in_interrupt() || oops_in_progress)
555 return panic_nand_wait_ready(mtd, 400);
556
8fe833c1 557 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 558 /* Wait until command is processed or timeout occurs */
3b88775c 559 do {
ace4dfee 560 if (chip->dev_ready(mtd))
8fe833c1 561 break;
8446f1d3 562 touch_softlockup_watchdog();
61b03bd7 563 } while (time_before(jiffies, timeo));
8fe833c1 564 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 565}
4b648b02 566EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 567
1da177e4
LT		 568/**
569 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 570 * @mtd: MTD device structure
571 * @command: the command to be sent
572 * @column: the column address for this command, -1 if none
573 * @page_addr: the page address for this command, -1 if none
1da177e4 574 *
8b6e50c9 575 * Send command to NAND device. This function is used for small page devices
51148f1f 576 * (512 Bytes per page).
1da177e4 577 */
7abd3ef9
TG		 578static void nand_command(struct mtd_info *mtd, unsigned int command,
579 int column, int page_addr)
1da177e4 580{
ace4dfee 581 register struct nand_chip *chip = mtd->priv;
7abd3ef9 582 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 583
8b6e50c9 584 /* Write out the command to the device */
1da177e4
LT		 585 if (command == NAND_CMD_SEQIN) {
586 int readcmd;
587
28318776 588 if (column >= mtd->writesize) {
1da177e4 589 /* OOB area */
28318776 590 column -= mtd->writesize;
1da177e4
LT		 591 readcmd = NAND_CMD_READOOB;
592 } else if (column < 256) {
593 /* First 256 bytes --> READ0 */
594 readcmd = NAND_CMD_READ0;
595 } else {
596 column -= 256;
597 readcmd = NAND_CMD_READ1;
598 }
ace4dfee 599 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 600 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 601 }
ace4dfee 602 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 603
8b6e50c9 604 /* Address cycle, when necessary */
7abd3ef9
TG		 605 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
606 /* Serially input address */
607 if (column != -1) {
608 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 609 if (chip->options & NAND_BUSWIDTH_16 &&
610 !nand_opcode_8bits(command))
7abd3ef9 611 column >>= 1;
ace4dfee 612 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 613 ctrl &= ~NAND_CTRL_CHANGE;
614 }
615 if (page_addr != -1) {
ace4dfee 616 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 617 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 618 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 619 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 620 if (chip->chipsize > (32 << 20))
621 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 622 }
ace4dfee 623 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 624
625 /*
8b6e50c9
BN		 626 * Program and erase have their own busy handlers status and sequential
627 * in needs no delay
e0c7d767 628 */
1da177e4 629 switch (command) {
61b03bd7 630
1da177e4
LT		 631 case NAND_CMD_PAGEPROG:
632 case NAND_CMD_ERASE1:
633 case NAND_CMD_ERASE2:
634 case NAND_CMD_SEQIN:
635 case NAND_CMD_STATUS:
636 return;
637
638 case NAND_CMD_RESET:
ace4dfee 639 if (chip->dev_ready)
1da177e4 640 break;
ace4dfee
TG		 641 udelay(chip->chip_delay);
642 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 643 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 644 chip->cmd_ctrl(mtd,
645 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 646 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
647 ;
1da177e4
LT		 648 return;
649
e0c7d767 650 /* This applies to read commands */
1da177e4 651 default:
61b03bd7 652 /*
1da177e4
LT		 653 * If we don't have access to the busy pin, we apply the given
654 * command delay
e0c7d767 655 */
ace4dfee
TG		 656 if (!chip->dev_ready) {
657 udelay(chip->chip_delay);
1da177e4 658 return;
61b03bd7 659 }
1da177e4 660 }
8b6e50c9
BN		 661 /*
662 * Apply this short delay always to ensure that we do wait tWB in
663 * any case on any machine.
664 */
e0c7d767 665 ndelay(100);
3b88775c
TG		 666
667 nand_wait_ready(mtd);
1da177e4
LT		 668}
669
670/**
671 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 672 * @mtd: MTD device structure
673 * @command: the command to be sent
674 * @column: the column address for this command, -1 if none
675 * @page_addr: the page address for this command, -1 if none
1da177e4 676 *
7abd3ef9 677 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 678 * devices. We don't have the separate regions as we have in the small page
679 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 680 */
7abd3ef9
TG		 681static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
682 int column, int page_addr)
1da177e4 683{
ace4dfee 684 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 685
686 /* Emulate NAND_CMD_READOOB */
687 if (command == NAND_CMD_READOOB) {
28318776 688 column += mtd->writesize;
1da177e4
LT		 689 command = NAND_CMD_READ0;
690 }
61b03bd7 691
7abd3ef9 692 /* Command latch cycle */
fb066ada 693 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 694
695 if (column != -1 || page_addr != -1) {
7abd3ef9 696 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 697
698 /* Serially input address */
699 if (column != -1) {
700 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 701 if (chip->options & NAND_BUSWIDTH_16 &&
702 !nand_opcode_8bits(command))
1da177e4 703 column >>= 1;
ace4dfee 704 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 705 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 706 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 707 }
1da177e4 708 if (page_addr != -1) {
ace4dfee
TG		 709 chip->cmd_ctrl(mtd, page_addr, ctrl);
710 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 711 NAND_NCE | NAND_ALE);
1da177e4 712 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 713 if (chip->chipsize > (128 << 20))
714 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 715 NAND_NCE | NAND_ALE);
1da177e4 716 }
1da177e4 717 }
ace4dfee 718 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 719
720 /*
8b6e50c9 721 * Program and erase have their own busy handlers status, sequential
7a442f17 722 * in and status need no delay.
30f464b7 723 */
1da177e4 724 switch (command) {
61b03bd7 725
1da177e4
LT		 726 case NAND_CMD_CACHEDPROG:
727 case NAND_CMD_PAGEPROG:
728 case NAND_CMD_ERASE1:
729 case NAND_CMD_ERASE2:
730 case NAND_CMD_SEQIN:
7bc3312b 731 case NAND_CMD_RNDIN:
1da177e4 732 case NAND_CMD_STATUS:
30f464b7 733 return;
1da177e4
LT		 734
735 case NAND_CMD_RESET:
ace4dfee 736 if (chip->dev_ready)
1da177e4 737 break;
ace4dfee 738 udelay(chip->chip_delay);
12efdde3
TG		 739 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
740 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
741 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
742 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 743 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
744 ;
1da177e4
LT		 745 return;
746
7bc3312b
TG		 747 case NAND_CMD_RNDOUT:
748 /* No ready / busy check necessary */
749 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
750 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
751 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
752 NAND_NCE | NAND_CTRL_CHANGE);
753 return;
754
1da177e4 755 case NAND_CMD_READ0:
12efdde3
TG		 756 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
757 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
758 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
759 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 760
e0c7d767 761 /* This applies to read commands */
1da177e4 762 default:
61b03bd7 763 /*
1da177e4 764 * If we don't have access to the busy pin, we apply the given
8b6e50c9 765 * command delay.
e0c7d767 766 */
ace4dfee
TG		 767 if (!chip->dev_ready) {
768 udelay(chip->chip_delay);
1da177e4 769 return;
61b03bd7 770 }
1da177e4 771 }
3b88775c 772
8b6e50c9
BN		 773 /*
774 * Apply this short delay always to ensure that we do wait tWB in
775 * any case on any machine.
776 */
e0c7d767 777 ndelay(100);
3b88775c
TG		 778
779 nand_wait_ready(mtd);
1da177e4
LT		 780}
781
2af7c653
SK		 782/**
783 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 784 * @chip: the nand chip descriptor
785 * @mtd: MTD device structure
786 * @new_state: the state which is requested
2af7c653
SK		 787 *
788 * Used when in panic, no locks are taken.
789 */
790static void panic_nand_get_device(struct nand_chip *chip,
791 struct mtd_info *mtd, int new_state)
792{
7854d3f7 793 /* Hardware controller shared among independent devices */
2af7c653
SK		 794 chip->controller->active = chip;
795 chip->state = new_state;
796}
797
1da177e4
LT		 798/**
799 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 800 * @mtd: MTD device structure
801 * @new_state: the state which is requested
1da177e4
LT		 802 *
803 * Get the device and lock it for exclusive access
804 */
2c0a2bed 805static int
6a8214aa 806nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 807{
6a8214aa 808 struct nand_chip *chip = mtd->priv;
ace4dfee
TG		 809 spinlock_t *lock = &chip->controller->lock;
810 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 811 DECLARE_WAITQUEUE(wait, current);
7351d3a5 812retry:
0dfc6246
TG		 813 spin_lock(lock);
814
b8b3ee9a 815 /* Hardware controller shared among independent devices */
ace4dfee
TG		 816 if (!chip->controller->active)
817 chip->controller->active = chip;
a36ed299 818
ace4dfee
TG		 819 if (chip->controller->active == chip && chip->state == FL_READY) {
820 chip->state = new_state;
0dfc6246 821 spin_unlock(lock);
962034f4
VW		 822 return 0;
823 }
824 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 825 if (chip->controller->active->state == FL_PM_SUSPENDED) {
826 chip->state = FL_PM_SUSPENDED;
827 spin_unlock(lock);
828 return 0;
6b0d9a84 829 }
0dfc6246
TG		 830 }
831 set_current_state(TASK_UNINTERRUPTIBLE);
832 add_wait_queue(wq, &wait);
833 spin_unlock(lock);
834 schedule();
835 remove_wait_queue(wq, &wait);
1da177e4
LT		 836 goto retry;
837}
838
2af7c653 839/**
8b6e50c9
BN		 840 * panic_nand_wait - [GENERIC] wait until the command is done
841 * @mtd: MTD device structure
842 * @chip: NAND chip structure
843 * @timeo: timeout
2af7c653
SK		 844 *
845 * Wait for command done. This is a helper function for nand_wait used when
846 * we are in interrupt context. May happen when in panic and trying to write
b595076a 847 * an oops through mtdoops.
2af7c653
SK		 848 */
849static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
850 unsigned long timeo)
851{
852 int i;
853 for (i = 0; i < timeo; i++) {
854 if (chip->dev_ready) {
855 if (chip->dev_ready(mtd))
856 break;
857 } else {
858 if (chip->read_byte(mtd) & NAND_STATUS_READY)
859 break;
860 }
861 mdelay(1);
f8ac0414 862 }
2af7c653
SK		 863}
864
1da177e4 865/**
8b6e50c9
BN		 866 * nand_wait - [DEFAULT] wait until the command is done
867 * @mtd: MTD device structure
868 * @chip: NAND chip structure
1da177e4 869 *
8b6e50c9
BN		 870 * Wait for command done. This applies to erase and program only. Erase can
871 * take up to 400ms and program up to 20ms according to general NAND and
872 * SmartMedia specs.
844d3b42 873 */
7bc3312b 874static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 875{
876
7bc3312b 877 int status, state = chip->state;
6d2559f8 878 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1da177e4 879
8fe833c1
RP		 880 led_trigger_event(nand_led_trigger, LED_FULL);
881
8b6e50c9
BN		 882 /*
883 * Apply this short delay always to ensure that we do wait tWB in any
884 * case on any machine.
885 */
e0c7d767 886 ndelay(100);
1da177e4 887
14c65786 888 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 889
2af7c653
SK		 890 if (in_interrupt() || oops_in_progress)
891 panic_nand_wait(mtd, chip, timeo);
892 else {
6d2559f8 893 timeo = jiffies + msecs_to_jiffies(timeo);
2af7c653
SK		 894 while (time_before(jiffies, timeo)) {
895 if (chip->dev_ready) {
896 if (chip->dev_ready(mtd))
897 break;
898 } else {
899 if (chip->read_byte(mtd) & NAND_STATUS_READY)
900 break;
901 }
902 cond_resched();
1da177e4 903 }
1da177e4 904 }
8fe833c1
RP		 905 led_trigger_event(nand_led_trigger, LED_OFF);
906
ace4dfee 907 status = (int)chip->read_byte(mtd);
f251b8df
MC		 908 /* This can happen if in case of timeout or buggy dev_ready */
909 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 910 return status;
911}
912
7d70f334 913/**
b6d676db 914 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 915 * @mtd: mtd info
916 * @ofs: offset to start unlock from
917 * @len: length to unlock
8b6e50c9
BN		 918 * @invert: when = 0, unlock the range of blocks within the lower and
919 * upper boundary address
920 * when = 1, unlock the range of blocks outside the boundaries
921 * of the lower and upper boundary address
7d70f334 922 *
8b6e50c9 923 * Returs unlock status.
7d70f334
VS		 924 */
925static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
926 uint64_t len, int invert)
927{
928 int ret = 0;
929 int status, page;
930 struct nand_chip *chip = mtd->priv;
931
932 /* Submit address of first page to unlock */
933 page = ofs >> chip->page_shift;
934 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
935
936 /* Submit address of last page to unlock */
937 page = (ofs + len) >> chip->page_shift;
938 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
939 (page | invert) & chip->pagemask);
940
941 /* Call wait ready function */
942 status = chip->waitfunc(mtd, chip);
7d70f334 943 /* See if device thinks it succeeded */
74830966 944 if (status & NAND_STATUS_FAIL) {
289c0522 945 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 946 __func__, status);
947 ret = -EIO;
948 }
949
950 return ret;
951}
952
953/**
b6d676db 954 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 955 * @mtd: mtd info
956 * @ofs: offset to start unlock from
957 * @len: length to unlock
7d70f334 958 *
8b6e50c9 959 * Returns unlock status.
7d70f334
VS		 960 */
961int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
962{
963 int ret = 0;
964 int chipnr;
965 struct nand_chip *chip = mtd->priv;
966
289c0522 967 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 968 __func__, (unsigned long long)ofs, len);
969
970 if (check_offs_len(mtd, ofs, len))
b1a2348a 971 return -EINVAL;
7d70f334
VS		 972
973 /* Align to last block address if size addresses end of the device */
974 if (ofs + len == mtd->size)
975 len -= mtd->erasesize;
976
6a8214aa 977 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 978
979 /* Shift to get chip number */
980 chipnr = ofs >> chip->chip_shift;
981
982 chip->select_chip(mtd, chipnr);
983
57d3a9a8
WD		 984 /*
985 * Reset the chip.
986 * If we want to check the WP through READ STATUS and check the bit 7
987 * we must reset the chip
988 * some operation can also clear the bit 7 of status register
989 * eg. erase/program a locked block
990 */
991 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
992
7d70f334
VS		 993 /* Check, if it is write protected */
994 if (nand_check_wp(mtd)) {
289c0522 995 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 996 __func__);
997 ret = -EIO;
998 goto out;
999 }
1000
1001 ret = __nand_unlock(mtd, ofs, len, 0);
1002
1003out:
b0bb6903 1004 chip->select_chip(mtd, -1);
7d70f334
VS		 1005 nand_release_device(mtd);
1006
1007 return ret;
1008}
7351d3a5 1009EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 1010
1011/**
b6d676db 1012 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 1013 * @mtd: mtd info
1014 * @ofs: offset to start unlock from
1015 * @len: length to unlock
7d70f334 1016 *
8b6e50c9
BN		 1017 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1018 * have this feature, but it allows only to lock all blocks, not for specified
1019 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1020 * now.
7d70f334 1021 *
8b6e50c9 1022 * Returns lock status.
7d70f334
VS		 1023 */
1024int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1025{
1026 int ret = 0;
1027 int chipnr, status, page;
1028 struct nand_chip *chip = mtd->priv;
1029
289c0522 1030 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1031 __func__, (unsigned long long)ofs, len);
1032
1033 if (check_offs_len(mtd, ofs, len))
b1a2348a 1034 return -EINVAL;
7d70f334 1035
6a8214aa 1036 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 1037
1038 /* Shift to get chip number */
1039 chipnr = ofs >> chip->chip_shift;
1040
1041 chip->select_chip(mtd, chipnr);
1042
57d3a9a8
WD		 1043 /*
1044 * Reset the chip.
1045 * If we want to check the WP through READ STATUS and check the bit 7
1046 * we must reset the chip
1047 * some operation can also clear the bit 7 of status register
1048 * eg. erase/program a locked block
1049 */
1050 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1051
7d70f334
VS		 1052 /* Check, if it is write protected */
1053 if (nand_check_wp(mtd)) {
289c0522 1054 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1055 __func__);
1056 status = MTD_ERASE_FAILED;
1057 ret = -EIO;
1058 goto out;
1059 }
1060
1061 /* Submit address of first page to lock */
1062 page = ofs >> chip->page_shift;
1063 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1064
1065 /* Call wait ready function */
1066 status = chip->waitfunc(mtd, chip);
7d70f334 1067 /* See if device thinks it succeeded */
74830966 1068 if (status & NAND_STATUS_FAIL) {
289c0522 1069 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1070 __func__, status);
1071 ret = -EIO;
1072 goto out;
1073 }
1074
1075 ret = __nand_unlock(mtd, ofs, len, 0x1);
1076
1077out:
b0bb6903 1078 chip->select_chip(mtd, -1);
7d70f334
VS		 1079 nand_release_device(mtd);
1080
1081 return ret;
1082}
7351d3a5 1083EXPORT_SYMBOL(nand_lock);
7d70f334 1084
8593fbc6 1085/**
7854d3f7 1086 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1087 * @mtd: mtd info structure
1088 * @chip: nand chip info structure
1089 * @buf: buffer to store read data
1fbb938d 1090 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1091 * @page: page number to read
52ff49df 1092 *
7854d3f7 1093 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1094 */
1095static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1096 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1097{
1098 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1099 if (oob_required)
1100 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1101 return 0;
1102}
1103
52ff49df 1104/**
7854d3f7 1105 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1106 * @mtd: mtd info structure
1107 * @chip: nand chip info structure
1108 * @buf: buffer to store read data
1fbb938d 1109 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1110 * @page: page number to read
52ff49df
DB		 1111 *
1112 * We need a special oob layout and handling even when OOB isn't used.
1113 */
7351d3a5 1114static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1115 struct nand_chip *chip, uint8_t *buf,
1116 int oob_required, int page)
52ff49df
DB		 1117{
1118 int eccsize = chip->ecc.size;
1119 int eccbytes = chip->ecc.bytes;
1120 uint8_t *oob = chip->oob_poi;
1121 int steps, size;
1122
1123 for (steps = chip->ecc.steps; steps > 0; steps--) {
1124 chip->read_buf(mtd, buf, eccsize);
1125 buf += eccsize;
1126
1127 if (chip->ecc.prepad) {
1128 chip->read_buf(mtd, oob, chip->ecc.prepad);
1129 oob += chip->ecc.prepad;
1130 }
1131
1132 chip->read_buf(mtd, oob, eccbytes);
1133 oob += eccbytes;
1134
1135 if (chip->ecc.postpad) {
1136 chip->read_buf(mtd, oob, chip->ecc.postpad);
1137 oob += chip->ecc.postpad;
1138 }
1139 }
1140
1141 size = mtd->oobsize - (oob - chip->oob_poi);
1142 if (size)
1143 chip->read_buf(mtd, oob, size);
1144
1145 return 0;
1146}
1147
1da177e4 1148/**
7854d3f7 1149 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1150 * @mtd: mtd info structure
1151 * @chip: nand chip info structure
1152 * @buf: buffer to store read data
1fbb938d 1153 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1154 * @page: page number to read
068e3c0a 1155 */
f5bbdacc 1156static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1157 uint8_t *buf, int oob_required, int page)
1da177e4 1158{
f5bbdacc
TG		 1159 int i, eccsize = chip->ecc.size;
1160 int eccbytes = chip->ecc.bytes;
1161 int eccsteps = chip->ecc.steps;
1162 uint8_t *p = buf;
4bf63fcb
DW		 1163 uint8_t *ecc_calc = chip->buffers->ecccalc;
1164 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1165 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1166 unsigned int max_bitflips = 0;
f5bbdacc 1167
1fbb938d 1168 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1169
1170 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1171 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1172
1173 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1174 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1175
1176 eccsteps = chip->ecc.steps;
1177 p = buf;
1178
1179 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1180 int stat;
1181
1182 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1183 if (stat < 0) {
f5bbdacc 1184 mtd->ecc_stats.failed++;
3f91e94f 1185 } else {
f5bbdacc 1186 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1187 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1188 }
f5bbdacc 1189 }
3f91e94f 1190 return max_bitflips;
22c60f5f 1191}
1da177e4 1192
3d459559 1193/**
837a6ba4 1194 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1195 * @mtd: mtd info structure
1196 * @chip: nand chip info structure
1197 * @data_offs: offset of requested data within the page
1198 * @readlen: data length
1199 * @bufpoi: buffer to store read data
e004debd 1200 * @page: page number to read
3d459559 1201 */
7351d3a5 1202static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
e004debd
HS		 1203 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1204 int page)
3d459559
AK		 1205{
1206 int start_step, end_step, num_steps;
1207 uint32_t *eccpos = chip->ecc.layout->eccpos;
1208 uint8_t *p;
1209 int data_col_addr, i, gaps = 0;
1210 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1211 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
4a4163ca 1212 int index;
3f91e94f 1213 unsigned int max_bitflips = 0;
3d459559 1214
7854d3f7 1215 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1216 start_step = data_offs / chip->ecc.size;
1217 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1218 num_steps = end_step - start_step + 1;
4a4163ca 1219 index = start_step * chip->ecc.bytes;
3d459559 1220
8b6e50c9 1221 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1222 datafrag_len = num_steps * chip->ecc.size;
1223 eccfrag_len = num_steps * chip->ecc.bytes;
1224
1225 data_col_addr = start_step * chip->ecc.size;
1226 /* If we read not a page aligned data */
1227 if (data_col_addr != 0)
1228 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1229
1230 p = bufpoi + data_col_addr;
1231 chip->read_buf(mtd, p, datafrag_len);
1232
8b6e50c9 1233 /* Calculate ECC */
3d459559
AK		 1234 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1235 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1236
8b6e50c9
BN		 1237 /*
1238 * The performance is faster if we position offsets according to
7854d3f7 1239 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1240 */
3d459559 1241 for (i = 0; i < eccfrag_len - 1; i++) {
47570bb1 1242 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
3d459559
AK		 1243 gaps = 1;
1244 break;
1245 }
1246 }
1247 if (gaps) {
1248 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1249 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1250 } else {
8b6e50c9 1251 /*
7854d3f7 1252 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1253 * about buswidth alignment in read_buf.
1254 */
7351d3a5 1255 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1256 aligned_len = eccfrag_len;
7351d3a5 1257 if (eccpos[index] & (busw - 1))
3d459559 1258 aligned_len++;
7351d3a5 1259 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1260 aligned_len++;
1261
7351d3a5
FF		 1262 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1263 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1264 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1265 }
1266
1267 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1268 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1269
1270 p = bufpoi + data_col_addr;
1271 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1272 int stat;
1273
7351d3a5
FF		 1274 stat = chip->ecc.correct(mtd, p,
1275 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1276 if (stat < 0) {
3d459559 1277 mtd->ecc_stats.failed++;
3f91e94f 1278 } else {
3d459559 1279 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1280 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1281 }
3d459559 1282 }
3f91e94f 1283 return max_bitflips;
3d459559
AK		 1284}
1285
068e3c0a 1286/**
7854d3f7 1287 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1288 * @mtd: mtd info structure
1289 * @chip: nand chip info structure
1290 * @buf: buffer to store read data
1fbb938d 1291 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1292 * @page: page number to read
068e3c0a 1293 *
7854d3f7 1294 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1295 */
f5bbdacc 1296static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1297 uint8_t *buf, int oob_required, int page)
1da177e4 1298{
f5bbdacc
TG		 1299 int i, eccsize = chip->ecc.size;
1300 int eccbytes = chip->ecc.bytes;
1301 int eccsteps = chip->ecc.steps;
1302 uint8_t *p = buf;
4bf63fcb
DW		 1303 uint8_t *ecc_calc = chip->buffers->ecccalc;
1304 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1305 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1306 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1307
1308 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1309 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1310 chip->read_buf(mtd, p, eccsize);
1311 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1312 }
f75e5097 1313 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1314
f5bbdacc 1315 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1316 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1317
f5bbdacc
TG		 1318 eccsteps = chip->ecc.steps;
1319 p = buf;
61b03bd7 1320
f5bbdacc
TG		 1321 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1322 int stat;
1da177e4 1323
f5bbdacc 1324 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1325 if (stat < 0) {
f5bbdacc 1326 mtd->ecc_stats.failed++;
3f91e94f 1327 } else {
f5bbdacc 1328 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1329 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1330 }
f5bbdacc 1331 }
3f91e94f 1332 return max_bitflips;
f5bbdacc 1333}
1da177e4 1334
6e0cb135 1335/**
7854d3f7 1336 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1337 * @mtd: mtd info structure
1338 * @chip: nand chip info structure
1339 * @buf: buffer to store read data
1fbb938d 1340 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1341 * @page: page number to read
6e0cb135 1342 *
8b6e50c9
BN		 1343 * Hardware ECC for large page chips, require OOB to be read first. For this
1344 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1345 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1346 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1347 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1348 */
1349static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1350 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1351{
1352 int i, eccsize = chip->ecc.size;
1353 int eccbytes = chip->ecc.bytes;
1354 int eccsteps = chip->ecc.steps;
1355 uint8_t *p = buf;
1356 uint8_t *ecc_code = chip->buffers->ecccode;
1357 uint32_t *eccpos = chip->ecc.layout->eccpos;
1358 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1359 unsigned int max_bitflips = 0;
6e0cb135
SN		 1360
1361 /* Read the OOB area first */
1362 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1363 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1364 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1365
1366 for (i = 0; i < chip->ecc.total; i++)
1367 ecc_code[i] = chip->oob_poi[eccpos[i]];
1368
1369 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1370 int stat;
1371
1372 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1373 chip->read_buf(mtd, p, eccsize);
1374 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1375
1376 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1377 if (stat < 0) {
6e0cb135 1378 mtd->ecc_stats.failed++;
3f91e94f 1379 } else {
6e0cb135 1380 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1381 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1382 }
6e0cb135 1383 }
3f91e94f 1384 return max_bitflips;
6e0cb135
SN		 1385}
1386
f5bbdacc 1387/**
7854d3f7 1388 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1389 * @mtd: mtd info structure
1390 * @chip: nand chip info structure
1391 * @buf: buffer to store read data
1fbb938d 1392 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1393 * @page: page number to read
f5bbdacc 1394 *
8b6e50c9
BN		 1395 * The hw generator calculates the error syndrome automatically. Therefore we
1396 * need a special oob layout and handling.
f5bbdacc
TG		 1397 */
1398static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1399 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1400{
1401 int i, eccsize = chip->ecc.size;
1402 int eccbytes = chip->ecc.bytes;
1403 int eccsteps = chip->ecc.steps;
1404 uint8_t *p = buf;
f75e5097 1405 uint8_t *oob = chip->oob_poi;
3f91e94f 1406 unsigned int max_bitflips = 0;
1da177e4 1407
f5bbdacc
TG		 1408 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1409 int stat;
61b03bd7 1410
f5bbdacc
TG		 1411 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1412 chip->read_buf(mtd, p, eccsize);
1da177e4 1413
f5bbdacc
TG		 1414 if (chip->ecc.prepad) {
1415 chip->read_buf(mtd, oob, chip->ecc.prepad);
1416 oob += chip->ecc.prepad;
1417 }
1da177e4 1418
f5bbdacc
TG		 1419 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1420 chip->read_buf(mtd, oob, eccbytes);
1421 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1422
3f91e94f 1423 if (stat < 0) {
f5bbdacc 1424 mtd->ecc_stats.failed++;
3f91e94f 1425 } else {
f5bbdacc 1426 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1427 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1428 }
61b03bd7 1429
f5bbdacc 1430 oob += eccbytes;
1da177e4 1431
f5bbdacc
TG		 1432 if (chip->ecc.postpad) {
1433 chip->read_buf(mtd, oob, chip->ecc.postpad);
1434 oob += chip->ecc.postpad;
61b03bd7 1435 }
f5bbdacc 1436 }
1da177e4 1437
f5bbdacc 1438 /* Calculate remaining oob bytes */
7e4178f9 1439 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1440 if (i)
1441 chip->read_buf(mtd, oob, i);
61b03bd7 1442
3f91e94f 1443 return max_bitflips;
f5bbdacc 1444}
1da177e4 1445
f5bbdacc 1446/**
7854d3f7 1447 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1448 * @chip: nand chip structure
1449 * @oob: oob destination address
1450 * @ops: oob ops structure
1451 * @len: size of oob to transfer
8593fbc6
TG		 1452 */
1453static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1454 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1455{
f8ac0414 1456 switch (ops->mode) {
8593fbc6 1457
0612b9dd
BN		 1458 case MTD_OPS_PLACE_OOB:
1459 case MTD_OPS_RAW:
8593fbc6
TG		 1460 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1461 return oob + len;
1462
0612b9dd 1463 case MTD_OPS_AUTO_OOB: {
8593fbc6 1464 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1465 uint32_t boffs = 0, roffs = ops->ooboffs;
1466 size_t bytes = 0;
8593fbc6 1467
f8ac0414 1468 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1469 /* Read request not from offset 0? */
7bc3312b
TG		 1470 if (unlikely(roffs)) {
1471 if (roffs >= free->length) {
1472 roffs -= free->length;
1473 continue;
1474 }
1475 boffs = free->offset + roffs;
1476 bytes = min_t(size_t, len,
1477 (free->length - roffs));
1478 roffs = 0;
1479 } else {
1480 bytes = min_t(size_t, len, free->length);
1481 boffs = free->offset;
1482 }
1483 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1484 oob += bytes;
1485 }
1486 return oob;
1487 }
1488 default:
1489 BUG();
1490 }
1491 return NULL;
1492}
1493
ba84fb59
BN		 1494/**
1495 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1496 * @mtd: MTD device structure
1497 * @retry_mode: the retry mode to use
1498 *
1499 * Some vendors supply a special command to shift the Vt threshold, to be used
1500 * when there are too many bitflips in a page (i.e., ECC error). After setting
1501 * a new threshold, the host should retry reading the page.
1502 */
1503static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1504{
1505 struct nand_chip *chip = mtd->priv;
1506
1507 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1508
1509 if (retry_mode >= chip->read_retries)
1510 return -EINVAL;
1511
1512 if (!chip->setup_read_retry)
1513 return -EOPNOTSUPP;
1514
1515 return chip->setup_read_retry(mtd, retry_mode);
1516}
1517
8593fbc6 1518/**
7854d3f7 1519 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1520 * @mtd: MTD device structure
1521 * @from: offset to read from
1522 * @ops: oob ops structure
f5bbdacc
TG		 1523 *
1524 * Internal function. Called with chip held.
1525 */
8593fbc6
TG		 1526static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1527 struct mtd_oob_ops *ops)
f5bbdacc 1528{
e47f3db4 1529 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc 1530 struct nand_chip *chip = mtd->priv;
f5bbdacc 1531 int ret = 0;
8593fbc6 1532 uint32_t readlen = ops->len;
7014568b 1533 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1534 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1535 mtd->oobavail : mtd->oobsize;
1536
8593fbc6 1537 uint8_t *bufpoi, *oob, *buf;
66507c7b 1538 int use_bufpoi;
edbc4540 1539 unsigned int max_bitflips = 0;
ba84fb59 1540 int retry_mode = 0;
b72f3dfb 1541 bool ecc_fail = false;
1da177e4 1542
f5bbdacc
TG		 1543 chipnr = (int)(from >> chip->chip_shift);
1544 chip->select_chip(mtd, chipnr);
61b03bd7 1545
f5bbdacc
TG		 1546 realpage = (int)(from >> chip->page_shift);
1547 page = realpage & chip->pagemask;
1da177e4 1548
f5bbdacc 1549 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1550
8593fbc6
TG		 1551 buf = ops->datbuf;
1552 oob = ops->oobbuf;
e47f3db4 1553 oob_required = oob ? 1 : 0;
8593fbc6 1554
f8ac0414 1555 while (1) {
b72f3dfb
BN		 1556 unsigned int ecc_failures = mtd->ecc_stats.failed;
1557
f5bbdacc
TG		 1558 bytes = min(mtd->writesize - col, readlen);
1559 aligned = (bytes == mtd->writesize);
61b03bd7 1560
66507c7b
KD		 1561 if (!aligned)
1562 use_bufpoi = 1;
1563 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1564 use_bufpoi = !virt_addr_valid(buf);
1565 else
1566 use_bufpoi = 0;
1567
8b6e50c9 1568 /* Is the current page in the buffer? */
8593fbc6 1569 if (realpage != chip->pagebuf || oob) {
66507c7b
KD		 1570 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1571
1572 if (use_bufpoi && aligned)
1573 pr_debug("%s: using read bounce buffer for buf@%p\n",
1574 __func__, buf);
61b03bd7 1575
ba84fb59 1576read_retry:
c00a0991 1577 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1578
edbc4540
MD		 1579 /*
1580 * Now read the page into the buffer. Absent an error,
1581 * the read methods return max bitflips per ecc step.
1582 */
0612b9dd 1583 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1584 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1585 oob_required,
1586 page);
a5ff4f10
JW		 1587 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1588 !oob)
7351d3a5 1589 ret = chip->ecc.read_subpage(mtd, chip,
e004debd
HS		 1590 col, bytes, bufpoi,
1591 page);
956e944c 1592 else
46a8cf2d 1593 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1594 oob_required, page);
6d77b9d0 1595 if (ret < 0) {
66507c7b 1596 if (use_bufpoi)
6d77b9d0
BN		 1597 /* Invalidate page cache */
1598 chip->pagebuf = -1;
1da177e4 1599 break;
6d77b9d0 1600 }
f5bbdacc 1601
edbc4540
MD		 1602 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1603
f5bbdacc 1604 /* Transfer not aligned data */
66507c7b 1605 if (use_bufpoi) {
a5ff4f10 1606 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
b72f3dfb 1607 !(mtd->ecc_stats.failed - ecc_failures) &&
edbc4540 1608 (ops->mode != MTD_OPS_RAW)) {
3d459559 1609 chip->pagebuf = realpage;
edbc4540
MD		 1610 chip->pagebuf_bitflips = ret;
1611 } else {
6d77b9d0
BN		 1612 /* Invalidate page cache */
1613 chip->pagebuf = -1;
edbc4540 1614 }
4bf63fcb 1615 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1616 }
1617
8593fbc6 1618 if (unlikely(oob)) {
b64d39d8
ML		 1619 int toread = min(oobreadlen, max_oobsize);
1620
1621 if (toread) {
1622 oob = nand_transfer_oob(chip,
1623 oob, ops, toread);
1624 oobreadlen -= toread;
1625 }
8593fbc6 1626 }
5bc7c33c
BN		 1627
1628 if (chip->options & NAND_NEED_READRDY) {
1629 /* Apply delay or wait for ready/busy pin */
1630 if (!chip->dev_ready)
1631 udelay(chip->chip_delay);
1632 else
1633 nand_wait_ready(mtd);
1634 }
b72f3dfb 1635
ba84fb59 1636 if (mtd->ecc_stats.failed - ecc_failures) {
28fa65e6 1637 if (retry_mode + 1 < chip->read_retries) {
ba84fb59
BN		 1638 retry_mode++;
1639 ret = nand_setup_read_retry(mtd,
1640 retry_mode);
1641 if (ret < 0)
1642 break;
1643
1644 /* Reset failures; retry */
1645 mtd->ecc_stats.failed = ecc_failures;
1646 goto read_retry;
1647 } else {
1648 /* No more retry modes; real failure */
1649 ecc_fail = true;
1650 }
1651 }
1652
1653 buf += bytes;
8593fbc6 1654 } else {
4bf63fcb 1655 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1656 buf += bytes;
edbc4540
MD		 1657 max_bitflips = max_t(unsigned int, max_bitflips,
1658 chip->pagebuf_bitflips);
8593fbc6 1659 }
1da177e4 1660
f5bbdacc 1661 readlen -= bytes;
61b03bd7 1662
ba84fb59
BN		 1663 /* Reset to retry mode 0 */
1664 if (retry_mode) {
1665 ret = nand_setup_read_retry(mtd, 0);
1666 if (ret < 0)
1667 break;
1668 retry_mode = 0;
1669 }
1670
f5bbdacc 1671 if (!readlen)
61b03bd7 1672 break;
1da177e4 1673
8b6e50c9 1674 /* For subsequent reads align to page boundary */
1da177e4
LT		 1675 col = 0;
1676 /* Increment page address */
1677 realpage++;
1678
ace4dfee 1679 page = realpage & chip->pagemask;
1da177e4
LT		 1680 /* Check, if we cross a chip boundary */
1681 if (!page) {
1682 chipnr++;
ace4dfee
TG		 1683 chip->select_chip(mtd, -1);
1684 chip->select_chip(mtd, chipnr);
1da177e4 1685 }
1da177e4 1686 }
b0bb6903 1687 chip->select_chip(mtd, -1);
1da177e4 1688
8593fbc6 1689 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1690 if (oob)
1691 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1692
3f91e94f 1693 if (ret < 0)
f5bbdacc
TG		 1694 return ret;
1695
b72f3dfb 1696 if (ecc_fail)
9a1fcdfd
TG		 1697 return -EBADMSG;
1698
edbc4540 1699 return max_bitflips;
f5bbdacc
TG		 1700}
1701
1702/**
25985edc 1703 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1704 * @mtd: MTD device structure
1705 * @from: offset to read from
1706 * @len: number of bytes to read
1707 * @retlen: pointer to variable to store the number of read bytes
1708 * @buf: the databuffer to put data
f5bbdacc 1709 *
8b6e50c9 1710 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1711 */
1712static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1713 size_t *retlen, uint8_t *buf)
1714{
4a89ff88 1715 struct mtd_oob_ops ops;
f5bbdacc
TG		 1716 int ret;
1717
6a8214aa 1718 nand_get_device(mtd, FL_READING);
4a89ff88
BN		 1719 ops.len = len;
1720 ops.datbuf = buf;
1721 ops.oobbuf = NULL;
11041ae6 1722 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1723 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1724 *retlen = ops.retlen;
f5bbdacc 1725 nand_release_device(mtd);
f5bbdacc 1726 return ret;
1da177e4
LT		 1727}
1728
7bc3312b 1729/**
7854d3f7 1730 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1731 * @mtd: mtd info structure
1732 * @chip: nand chip info structure
1733 * @page: page number to read
7bc3312b
TG		 1734 */
1735static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1736 int page)
7bc3312b 1737{
5c2ffb11 1738 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1739 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1740 return 0;
7bc3312b
TG		 1741}
1742
1743/**
7854d3f7 1744 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1745 * with syndromes
8b6e50c9
BN		 1746 * @mtd: mtd info structure
1747 * @chip: nand chip info structure
1748 * @page: page number to read
7bc3312b
TG		 1749 */
1750static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1751 int page)
7bc3312b 1752{
7bc3312b
TG		 1753 int length = mtd->oobsize;
1754 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1755 int eccsize = chip->ecc.size;
2ea69d21 1756 uint8_t *bufpoi = chip->oob_poi;
7bc3312b
TG		 1757 int i, toread, sndrnd = 0, pos;
1758
1759 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1760 for (i = 0; i < chip->ecc.steps; i++) {
1761 if (sndrnd) {
1762 pos = eccsize + i * (eccsize + chunk);
1763 if (mtd->writesize > 512)
1764 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1765 else
1766 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1767 } else
1768 sndrnd = 1;
1769 toread = min_t(int, length, chunk);
1770 chip->read_buf(mtd, bufpoi, toread);
1771 bufpoi += toread;
1772 length -= toread;
1773 }
1774 if (length > 0)
1775 chip->read_buf(mtd, bufpoi, length);
1776
5c2ffb11 1777 return 0;
7bc3312b
TG		 1778}
1779
1780/**
7854d3f7 1781 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1782 * @mtd: mtd info structure
1783 * @chip: nand chip info structure
1784 * @page: page number to write
7bc3312b
TG		 1785 */
1786static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1787 int page)
1788{
1789 int status = 0;
1790 const uint8_t *buf = chip->oob_poi;
1791 int length = mtd->oobsize;
1792
1793 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1794 chip->write_buf(mtd, buf, length);
1795 /* Send command to program the OOB data */
1796 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1797
1798 status = chip->waitfunc(mtd, chip);
1799
0d420f9d 1800 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1801}
1802
1803/**
7854d3f7 1804 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1805 * with syndrome - only for large page flash
1806 * @mtd: mtd info structure
1807 * @chip: nand chip info structure
1808 * @page: page number to write
7bc3312b
TG		 1809 */
1810static int nand_write_oob_syndrome(struct mtd_info *mtd,
1811 struct nand_chip *chip, int page)
1812{
1813 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1814 int eccsize = chip->ecc.size, length = mtd->oobsize;
1815 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1816 const uint8_t *bufpoi = chip->oob_poi;
1817
1818 /*
1819 * data-ecc-data-ecc ... ecc-oob
1820 * or
1821 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1822 */
1823 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1824 pos = steps * (eccsize + chunk);
1825 steps = 0;
1826 } else
8b0036ee 1827 pos = eccsize;
7bc3312b
TG		 1828
1829 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1830 for (i = 0; i < steps; i++) {
1831 if (sndcmd) {
1832 if (mtd->writesize <= 512) {
1833 uint32_t fill = 0xFFFFFFFF;
1834
1835 len = eccsize;
1836 while (len > 0) {
1837 int num = min_t(int, len, 4);
1838 chip->write_buf(mtd, (uint8_t *)&fill,
1839 num);
1840 len -= num;
1841 }
1842 } else {
1843 pos = eccsize + i * (eccsize + chunk);
1844 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1845 }
1846 } else
1847 sndcmd = 1;
1848 len = min_t(int, length, chunk);
1849 chip->write_buf(mtd, bufpoi, len);
1850 bufpoi += len;
1851 length -= len;
1852 }
1853 if (length > 0)
1854 chip->write_buf(mtd, bufpoi, length);
1855
1856 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1857 status = chip->waitfunc(mtd, chip);
1858
1859 return status & NAND_STATUS_FAIL ? -EIO : 0;
1860}
1861
1da177e4 1862/**
7854d3f7 1863 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1864 * @mtd: MTD device structure
1865 * @from: offset to read from
1866 * @ops: oob operations description structure
1da177e4 1867 *
8b6e50c9 1868 * NAND read out-of-band data from the spare area.
1da177e4 1869 */
8593fbc6
TG		 1870static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1871 struct mtd_oob_ops *ops)
1da177e4 1872{
c00a0991 1873 int page, realpage, chipnr;
ace4dfee 1874 struct nand_chip *chip = mtd->priv;
041e4575 1875 struct mtd_ecc_stats stats;
7014568b
VW		 1876 int readlen = ops->ooblen;
1877 int len;
7bc3312b 1878 uint8_t *buf = ops->oobbuf;
1951f2f7 1879 int ret = 0;
61b03bd7 1880
289c0522 1881 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1882 __func__, (unsigned long long)from, readlen);
1da177e4 1883
041e4575
BN		 1884 stats = mtd->ecc_stats;
1885
0612b9dd 1886 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1887 len = chip->ecc.layout->oobavail;
03736155
AH		 1888 else
1889 len = mtd->oobsize;
1890
1891 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1892 pr_debug("%s: attempt to start read outside oob\n",
1893 __func__);
03736155
AH		 1894 return -EINVAL;
1895 }
1896
1897 /* Do not allow reads past end of device */
1898 if (unlikely(from >= mtd->size ||
1899 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1900 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1901 pr_debug("%s: attempt to read beyond end of device\n",
1902 __func__);
03736155
AH		 1903 return -EINVAL;
1904 }
7014568b 1905
7314e9e7 1906 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1907 chip->select_chip(mtd, chipnr);
1da177e4 1908
7314e9e7
TG		 1909 /* Shift to get page */
1910 realpage = (int)(from >> chip->page_shift);
1911 page = realpage & chip->pagemask;
1da177e4 1912
f8ac0414 1913 while (1) {
0612b9dd 1914 if (ops->mode == MTD_OPS_RAW)
1951f2f7 1915 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 1916 else
1951f2f7
SL		 1917 ret = chip->ecc.read_oob(mtd, chip, page);
1918
1919 if (ret < 0)
1920 break;
7014568b
VW		 1921
1922 len = min(len, readlen);
1923 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1924
5bc7c33c
BN		 1925 if (chip->options & NAND_NEED_READRDY) {
1926 /* Apply delay or wait for ready/busy pin */
1927 if (!chip->dev_ready)
1928 udelay(chip->chip_delay);
1929 else
1930 nand_wait_ready(mtd);
1931 }
1932
7014568b 1933 readlen -= len;
0d420f9d
SZ		 1934 if (!readlen)
1935 break;
1936
7314e9e7
TG		 1937 /* Increment page address */
1938 realpage++;
1939
1940 page = realpage & chip->pagemask;
1941 /* Check, if we cross a chip boundary */
1942 if (!page) {
1943 chipnr++;
1944 chip->select_chip(mtd, -1);
1945 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1946 }
1947 }
b0bb6903 1948 chip->select_chip(mtd, -1);
1da177e4 1949
1951f2f7
SL		 1950 ops->oobretlen = ops->ooblen - readlen;
1951
1952 if (ret < 0)
1953 return ret;
041e4575
BN		 1954
1955 if (mtd->ecc_stats.failed - stats.failed)
1956 return -EBADMSG;
1957
1958 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1959}
1960
1961/**
8593fbc6 1962 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1963 * @mtd: MTD device structure
1964 * @from: offset to read from
1965 * @ops: oob operation description structure
1da177e4 1966 *
8b6e50c9 1967 * NAND read data and/or out-of-band data.
1da177e4 1968 */
8593fbc6
TG		 1969static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1970 struct mtd_oob_ops *ops)
1da177e4 1971{
8593fbc6
TG		 1972 int ret = -ENOTSUPP;
1973
1974 ops->retlen = 0;
1da177e4
LT		 1975
1976 /* Do not allow reads past end of device */
7014568b 1977 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1978 pr_debug("%s: attempt to read beyond end of device\n",
1979 __func__);
1da177e4
LT		 1980 return -EINVAL;
1981 }
1982
6a8214aa 1983 nand_get_device(mtd, FL_READING);
1da177e4 1984
f8ac0414 1985 switch (ops->mode) {
0612b9dd
BN		 1986 case MTD_OPS_PLACE_OOB:
1987 case MTD_OPS_AUTO_OOB:
1988 case MTD_OPS_RAW:
8593fbc6 1989 break;
1da177e4 1990
8593fbc6
TG		 1991 default:
1992 goto out;
1993 }
1da177e4 1994
8593fbc6
TG		 1995 if (!ops->datbuf)
1996 ret = nand_do_read_oob(mtd, from, ops);
1997 else
1998 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1999
7351d3a5 2000out:
8593fbc6
TG		 2001 nand_release_device(mtd);
2002 return ret;
2003}
61b03bd7 2004
1da177e4 2005
8593fbc6 2006/**
7854d3f7 2007 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 2008 * @mtd: mtd info structure
2009 * @chip: nand chip info structure
2010 * @buf: data buffer
1fbb938d 2011 * @oob_required: must write chip->oob_poi to OOB
52ff49df 2012 *
7854d3f7 2013 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 2014 */
fdbad98d 2015static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2016 const uint8_t *buf, int oob_required)
8593fbc6
TG		 2017{
2018 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 2019 if (oob_required)
2020 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2021
2022 return 0;
1da177e4
LT		 2023}
2024
52ff49df 2025/**
7854d3f7 2026 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 2027 * @mtd: mtd info structure
2028 * @chip: nand chip info structure
2029 * @buf: data buffer
1fbb938d 2030 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 2031 *
2032 * We need a special oob layout and handling even when ECC isn't checked.
2033 */
fdbad98d 2034static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 2035 struct nand_chip *chip,
1fbb938d 2036 const uint8_t *buf, int oob_required)
52ff49df
DB		 2037{
2038 int eccsize = chip->ecc.size;
2039 int eccbytes = chip->ecc.bytes;
2040 uint8_t *oob = chip->oob_poi;
2041 int steps, size;
2042
2043 for (steps = chip->ecc.steps; steps > 0; steps--) {
2044 chip->write_buf(mtd, buf, eccsize);
2045 buf += eccsize;
2046
2047 if (chip->ecc.prepad) {
2048 chip->write_buf(mtd, oob, chip->ecc.prepad);
2049 oob += chip->ecc.prepad;
2050 }
2051
60c3bc1f 2052 chip->write_buf(mtd, oob, eccbytes);
52ff49df
DB		 2053 oob += eccbytes;
2054
2055 if (chip->ecc.postpad) {
2056 chip->write_buf(mtd, oob, chip->ecc.postpad);
2057 oob += chip->ecc.postpad;
2058 }
2059 }
2060
2061 size = mtd->oobsize - (oob - chip->oob_poi);
2062 if (size)
2063 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 2064
2065 return 0;
52ff49df 2066}
9223a456 2067/**
7854d3f7 2068 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 2069 * @mtd: mtd info structure
2070 * @chip: nand chip info structure
2071 * @buf: data buffer
1fbb938d 2072 * @oob_required: must write chip->oob_poi to OOB
9223a456 2073 */
fdbad98d 2074static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2075 const uint8_t *buf, int oob_required)
9223a456 2076{
f75e5097
TG		 2077 int i, eccsize = chip->ecc.size;
2078 int eccbytes = chip->ecc.bytes;
2079 int eccsteps = chip->ecc.steps;
4bf63fcb 2080 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2081 const uint8_t *p = buf;
8b099a39 2082 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2083
7854d3f7 2084 /* Software ECC calculation */
8593fbc6
TG		 2085 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2086 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 2087
8593fbc6
TG		 2088 for (i = 0; i < chip->ecc.total; i++)
2089 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 2090
fdbad98d 2091 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 2092}
9223a456 2093
f75e5097 2094/**
7854d3f7 2095 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2096 * @mtd: mtd info structure
2097 * @chip: nand chip info structure
2098 * @buf: data buffer
1fbb938d 2099 * @oob_required: must write chip->oob_poi to OOB
f75e5097 2100 */
fdbad98d 2101static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2102 const uint8_t *buf, int oob_required)
f75e5097
TG		 2103{
2104 int i, eccsize = chip->ecc.size;
2105 int eccbytes = chip->ecc.bytes;
2106 int eccsteps = chip->ecc.steps;
4bf63fcb 2107 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2108 const uint8_t *p = buf;
8b099a39 2109 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2110
f75e5097
TG		 2111 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2112 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2113 chip->write_buf(mtd, p, eccsize);
f75e5097 2114 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2115 }
2116
f75e5097
TG		 2117 for (i = 0; i < chip->ecc.total; i++)
2118 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2119
2120 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2121
2122 return 0;
9223a456
TG		 2123}
2124
837a6ba4
GP		 2125
2126/**
2127 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2128 * @mtd: mtd info structure
2129 * @chip: nand chip info structure
d6a95080 2130 * @offset: column address of subpage within the page
837a6ba4 2131 * @data_len: data length
d6a95080 2132 * @buf: data buffer
837a6ba4
GP		 2133 * @oob_required: must write chip->oob_poi to OOB
2134 */
2135static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2136 struct nand_chip *chip, uint32_t offset,
d6a95080 2137 uint32_t data_len, const uint8_t *buf,
837a6ba4
GP		 2138 int oob_required)
2139{
2140 uint8_t *oob_buf = chip->oob_poi;
2141 uint8_t *ecc_calc = chip->buffers->ecccalc;
2142 int ecc_size = chip->ecc.size;
2143 int ecc_bytes = chip->ecc.bytes;
2144 int ecc_steps = chip->ecc.steps;
2145 uint32_t *eccpos = chip->ecc.layout->eccpos;
2146 uint32_t start_step = offset / ecc_size;
2147 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2148 int oob_bytes = mtd->oobsize / ecc_steps;
2149 int step, i;
2150
2151 for (step = 0; step < ecc_steps; step++) {
2152 /* configure controller for WRITE access */
2153 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2154
2155 /* write data (untouched subpages already masked by 0xFF) */
d6a95080 2156 chip->write_buf(mtd, buf, ecc_size);
837a6ba4
GP		 2157
2158 /* mask ECC of un-touched subpages by padding 0xFF */
2159 if ((step < start_step) || (step > end_step))
2160 memset(ecc_calc, 0xff, ecc_bytes);
2161 else
d6a95080 2162 chip->ecc.calculate(mtd, buf, ecc_calc);
837a6ba4
GP		 2163
2164 /* mask OOB of un-touched subpages by padding 0xFF */
2165 /* if oob_required, preserve OOB metadata of written subpage */
2166 if (!oob_required || (step < start_step) || (step > end_step))
2167 memset(oob_buf, 0xff, oob_bytes);
2168
d6a95080 2169 buf += ecc_size;
837a6ba4
GP		 2170 ecc_calc += ecc_bytes;
2171 oob_buf += oob_bytes;
2172 }
2173
2174 /* copy calculated ECC for whole page to chip->buffer->oob */
2175 /* this include masked-value(0xFF) for unwritten subpages */
2176 ecc_calc = chip->buffers->ecccalc;
2177 for (i = 0; i < chip->ecc.total; i++)
2178 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2179
2180 /* write OOB buffer to NAND device */
2181 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2182
2183 return 0;
2184}
2185
2186
61b03bd7 2187/**
7854d3f7 2188 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2189 * @mtd: mtd info structure
2190 * @chip: nand chip info structure
2191 * @buf: data buffer
1fbb938d 2192 * @oob_required: must write chip->oob_poi to OOB
1da177e4 2193 *
8b6e50c9
BN		 2194 * The hw generator calculates the error syndrome automatically. Therefore we
2195 * need a special oob layout and handling.
f75e5097 2196 */
fdbad98d 2197static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 2198 struct nand_chip *chip,
2199 const uint8_t *buf, int oob_required)
1da177e4 2200{
f75e5097
TG		 2201 int i, eccsize = chip->ecc.size;
2202 int eccbytes = chip->ecc.bytes;
2203 int eccsteps = chip->ecc.steps;
2204 const uint8_t *p = buf;
2205 uint8_t *oob = chip->oob_poi;
1da177e4 2206
f75e5097 2207 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2208
f75e5097
TG		 2209 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2210 chip->write_buf(mtd, p, eccsize);
61b03bd7 2211
f75e5097
TG		 2212 if (chip->ecc.prepad) {
2213 chip->write_buf(mtd, oob, chip->ecc.prepad);
2214 oob += chip->ecc.prepad;
2215 }
2216
2217 chip->ecc.calculate(mtd, p, oob);
2218 chip->write_buf(mtd, oob, eccbytes);
2219 oob += eccbytes;
2220
2221 if (chip->ecc.postpad) {
2222 chip->write_buf(mtd, oob, chip->ecc.postpad);
2223 oob += chip->ecc.postpad;
1da177e4 2224 }
1da177e4 2225 }
f75e5097
TG		 2226
2227 /* Calculate remaining oob bytes */
7e4178f9 2228 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2229 if (i)
2230 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2231
2232 return 0;
f75e5097
TG		 2233}
2234
2235/**
956e944c 2236 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2237 * @mtd: MTD device structure
2238 * @chip: NAND chip descriptor
837a6ba4
GP		 2239 * @offset: address offset within the page
2240 * @data_len: length of actual data to be written
8b6e50c9 2241 * @buf: the data to write
1fbb938d 2242 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2243 * @page: page number to write
2244 * @cached: cached programming
2245 * @raw: use _raw version of write_page
f75e5097
TG		 2246 */
2247static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4
GP		 2248 uint32_t offset, int data_len, const uint8_t *buf,
2249 int oob_required, int page, int cached, int raw)
f75e5097 2250{
837a6ba4
GP		 2251 int status, subpage;
2252
2253 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2254 chip->ecc.write_subpage)
2255 subpage = offset || (data_len < mtd->writesize);
2256 else
2257 subpage = 0;
f75e5097
TG		 2258
2259 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2260
956e944c 2261 if (unlikely(raw))
837a6ba4
GP		 2262 status = chip->ecc.write_page_raw(mtd, chip, buf,
2263 oob_required);
2264 else if (subpage)
2265 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2266 buf, oob_required);
956e944c 2267 else
fdbad98d
JW		 2268 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2269
2270 if (status < 0)
2271 return status;
f75e5097
TG		 2272
2273 /*
7854d3f7 2274 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2275 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2276 */
2277 cached = 0;
2278
3239a6cd 2279 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2280
2281 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2282 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2283 /*
2284 * See if operation failed and additional status checks are
8b6e50c9 2285 * available.
f75e5097
TG		 2286 */
2287 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2288 status = chip->errstat(mtd, chip, FL_WRITING, status,
2289 page);
2290
2291 if (status & NAND_STATUS_FAIL)
2292 return -EIO;
2293 } else {
2294 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2295 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2296 }
2297
f75e5097 2298 return 0;
1da177e4
LT		 2299}
2300
8593fbc6 2301/**
7854d3f7 2302 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2303 * @mtd: MTD device structure
8b6e50c9
BN		 2304 * @oob: oob data buffer
2305 * @len: oob data write length
2306 * @ops: oob ops structure
8593fbc6 2307 */
f722013e
TAA		 2308static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2309 struct mtd_oob_ops *ops)
8593fbc6 2310{
f722013e
TAA		 2311 struct nand_chip *chip = mtd->priv;
2312
2313 /*
2314 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2315 * data from a previous OOB read.
2316 */
2317 memset(chip->oob_poi, 0xff, mtd->oobsize);
2318
f8ac0414 2319 switch (ops->mode) {
8593fbc6 2320
0612b9dd
BN		 2321 case MTD_OPS_PLACE_OOB:
2322 case MTD_OPS_RAW:
8593fbc6
TG		 2323 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2324 return oob + len;
2325
0612b9dd 2326 case MTD_OPS_AUTO_OOB: {
8593fbc6 2327 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2328 uint32_t boffs = 0, woffs = ops->ooboffs;
2329 size_t bytes = 0;
8593fbc6 2330
f8ac0414 2331 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2332 /* Write request not from offset 0? */
7bc3312b
TG		 2333 if (unlikely(woffs)) {
2334 if (woffs >= free->length) {
2335 woffs -= free->length;
2336 continue;
2337 }
2338 boffs = free->offset + woffs;
2339 bytes = min_t(size_t, len,
2340 (free->length - woffs));
2341 woffs = 0;
2342 } else {
2343 bytes = min_t(size_t, len, free->length);
2344 boffs = free->offset;
2345 }
8b0036ee 2346 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2347 oob += bytes;
2348 }
2349 return oob;
2350 }
2351 default:
2352 BUG();
2353 }
2354 return NULL;
2355}
2356
f8ac0414 2357#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2358
2359/**
7854d3f7 2360 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2361 * @mtd: MTD device structure
2362 * @to: offset to write to
2363 * @ops: oob operations description structure
1da177e4 2364 *
8b6e50c9 2365 * NAND write with ECC.
1da177e4 2366 */
8593fbc6
TG		 2367static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2368 struct mtd_oob_ops *ops)
1da177e4 2369{
29072b96 2370 int chipnr, realpage, page, blockmask, column;
ace4dfee 2371 struct nand_chip *chip = mtd->priv;
8593fbc6 2372 uint32_t writelen = ops->len;
782ce79a
ML		 2373
2374 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2375 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2376 mtd->oobavail : mtd->oobsize;
2377
8593fbc6
TG		 2378 uint8_t *oob = ops->oobbuf;
2379 uint8_t *buf = ops->datbuf;
837a6ba4 2380 int ret;
e47f3db4 2381 int oob_required = oob ? 1 : 0;
1da177e4 2382
8593fbc6 2383 ops->retlen = 0;
29072b96
TG		 2384 if (!writelen)
2385 return 0;
1da177e4 2386
8b6e50c9 2387 /* Reject writes, which are not page aligned */
8593fbc6 2388 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2389 pr_notice("%s: attempt to write non page aligned data\n",
2390 __func__);
1da177e4
LT		 2391 return -EINVAL;
2392 }
2393
29072b96 2394 column = to & (mtd->writesize - 1);
1da177e4 2395
6a930961
TG		 2396 chipnr = (int)(to >> chip->chip_shift);
2397 chip->select_chip(mtd, chipnr);
2398
1da177e4 2399 /* Check, if it is write protected */
b0bb6903
HS		 2400 if (nand_check_wp(mtd)) {
2401 ret = -EIO;
2402 goto err_out;
2403 }
1da177e4 2404
f75e5097
TG		 2405 realpage = (int)(to >> chip->page_shift);
2406 page = realpage & chip->pagemask;
2407 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2408
2409 /* Invalidate the page cache, when we write to the cached page */
537ab1bd
BN		 2410 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2411 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2412 chip->pagebuf = -1;
61b03bd7 2413
782ce79a 2414 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2415 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2416 ret = -EINVAL;
2417 goto err_out;
2418 }
782ce79a 2419
f8ac0414 2420 while (1) {
29072b96 2421 int bytes = mtd->writesize;
f75e5097 2422 int cached = writelen > bytes && page != blockmask;
29072b96 2423 uint8_t *wbuf = buf;
66507c7b
KD		 2424 int use_bufpoi;
2425 int part_pagewr = (column || writelen < (mtd->writesize - 1));
2426
2427 if (part_pagewr)
2428 use_bufpoi = 1;
2429 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2430 use_bufpoi = !virt_addr_valid(buf);
2431 else
2432 use_bufpoi = 0;
29072b96 2433
66507c7b
KD		 2434 /* Partial page write?, or need to use bounce buffer */
2435 if (use_bufpoi) {
2436 pr_debug("%s: using write bounce buffer for buf@%p\n",
2437 __func__, buf);
29072b96 2438 cached = 0;
66507c7b
KD		 2439 if (part_pagewr)
2440 bytes = min_t(int, bytes - column, writelen);
29072b96
TG		 2441 chip->pagebuf = -1;
2442 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2443 memcpy(&chip->buffers->databuf[column], buf, bytes);
2444 wbuf = chip->buffers->databuf;
2445 }
1da177e4 2446
782ce79a
ML		 2447 if (unlikely(oob)) {
2448 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2449 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2450 oobwritelen -= len;
f722013e
TAA		 2451 } else {
2452 /* We still need to erase leftover OOB data */
2453 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2454 }
837a6ba4
GP		 2455 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2456 oob_required, page, cached,
2457 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2458 if (ret)
2459 break;
2460
2461 writelen -= bytes;
2462 if (!writelen)
2463 break;
2464
29072b96 2465 column = 0;
f75e5097
TG		 2466 buf += bytes;
2467 realpage++;
2468
2469 page = realpage & chip->pagemask;
2470 /* Check, if we cross a chip boundary */
2471 if (!page) {
2472 chipnr++;
2473 chip->select_chip(mtd, -1);
2474 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2475 }
2476 }
8593fbc6 2477
8593fbc6 2478 ops->retlen = ops->len - writelen;
7014568b
VW		 2479 if (unlikely(oob))
2480 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2481
2482err_out:
2483 chip->select_chip(mtd, -1);
1da177e4
LT		 2484 return ret;
2485}
2486
2af7c653
SK		 2487/**
2488 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2489 * @mtd: MTD device structure
2490 * @to: offset to write to
2491 * @len: number of bytes to write
2492 * @retlen: pointer to variable to store the number of written bytes
2493 * @buf: the data to write
2af7c653
SK		 2494 *
2495 * NAND write with ECC. Used when performing writes in interrupt context, this
2496 * may for example be called by mtdoops when writing an oops while in panic.
2497 */
2498static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2499 size_t *retlen, const uint8_t *buf)
2500{
2501 struct nand_chip *chip = mtd->priv;
4a89ff88 2502 struct mtd_oob_ops ops;
2af7c653
SK		 2503 int ret;
2504
8b6e50c9 2505 /* Wait for the device to get ready */
2af7c653
SK		 2506 panic_nand_wait(mtd, chip, 400);
2507
8b6e50c9 2508 /* Grab the device */
2af7c653
SK		 2509 panic_nand_get_device(chip, mtd, FL_WRITING);
2510
4a89ff88
BN		 2511 ops.len = len;
2512 ops.datbuf = (uint8_t *)buf;
2513 ops.oobbuf = NULL;
11041ae6 2514 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2515
4a89ff88 2516 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2517
4a89ff88 2518 *retlen = ops.retlen;
2af7c653
SK		 2519 return ret;
2520}
2521
f75e5097 2522/**
8593fbc6 2523 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2524 * @mtd: MTD device structure
2525 * @to: offset to write to
2526 * @len: number of bytes to write
2527 * @retlen: pointer to variable to store the number of written bytes
2528 * @buf: the data to write
f75e5097 2529 *
8b6e50c9 2530 * NAND write with ECC.
f75e5097 2531 */
8593fbc6
TG		 2532static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2533 size_t *retlen, const uint8_t *buf)
f75e5097 2534{
4a89ff88 2535 struct mtd_oob_ops ops;
f75e5097
TG		 2536 int ret;
2537
6a8214aa 2538 nand_get_device(mtd, FL_WRITING);
4a89ff88
BN		 2539 ops.len = len;
2540 ops.datbuf = (uint8_t *)buf;
2541 ops.oobbuf = NULL;
11041ae6 2542 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2543 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2544 *retlen = ops.retlen;
f75e5097 2545 nand_release_device(mtd);
8593fbc6 2546 return ret;
f75e5097 2547}
7314e9e7 2548
1da177e4 2549/**
8593fbc6 2550 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2551 * @mtd: MTD device structure
2552 * @to: offset to write to
2553 * @ops: oob operation description structure
1da177e4 2554 *
8b6e50c9 2555 * NAND write out-of-band.
1da177e4 2556 */
8593fbc6
TG		 2557static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2558 struct mtd_oob_ops *ops)
1da177e4 2559{
03736155 2560 int chipnr, page, status, len;
ace4dfee 2561 struct nand_chip *chip = mtd->priv;
1da177e4 2562
289c0522 2563 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2564 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2565
0612b9dd 2566 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2567 len = chip->ecc.layout->oobavail;
2568 else
2569 len = mtd->oobsize;
2570
1da177e4 2571 /* Do not allow write past end of page */
03736155 2572 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2573 pr_debug("%s: attempt to write past end of page\n",
2574 __func__);
1da177e4
LT		 2575 return -EINVAL;
2576 }
2577
03736155 2578 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2579 pr_debug("%s: attempt to start write outside oob\n",
2580 __func__);
03736155
AH		 2581 return -EINVAL;
2582 }
2583
775adc3d 2584 /* Do not allow write past end of device */
03736155
AH		 2585 if (unlikely(to >= mtd->size ||
2586 ops->ooboffs + ops->ooblen >
2587 ((mtd->size >> chip->page_shift) -
2588 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2589 pr_debug("%s: attempt to write beyond end of device\n",
2590 __func__);
03736155
AH		 2591 return -EINVAL;
2592 }
2593
7314e9e7 2594 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2595 chip->select_chip(mtd, chipnr);
1da177e4 2596
7314e9e7
TG		 2597 /* Shift to get page */
2598 page = (int)(to >> chip->page_shift);
2599
2600 /*
2601 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2602 * of my DiskOnChip 2000 test units) will clear the whole data page too
2603 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2604 * it in the doc2000 driver in August 1999. dwmw2.
2605 */
ace4dfee 2606 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2607
2608 /* Check, if it is write protected */
b0bb6903
HS		 2609 if (nand_check_wp(mtd)) {
2610 chip->select_chip(mtd, -1);
8593fbc6 2611 return -EROFS;
b0bb6903 2612 }
61b03bd7 2613
1da177e4 2614 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2615 if (page == chip->pagebuf)
2616 chip->pagebuf = -1;
1da177e4 2617
f722013e 2618 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2619
0612b9dd 2620 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2621 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2622 else
2623 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2624
b0bb6903
HS		 2625 chip->select_chip(mtd, -1);
2626
7bc3312b
TG		 2627 if (status)
2628 return status;
1da177e4 2629
7014568b 2630 ops->oobretlen = ops->ooblen;
1da177e4 2631
7bc3312b 2632 return 0;
8593fbc6
TG		 2633}
2634
2635/**
2636 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2637 * @mtd: MTD device structure
2638 * @to: offset to write to
2639 * @ops: oob operation description structure
8593fbc6
TG		 2640 */
2641static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2642 struct mtd_oob_ops *ops)
2643{
8593fbc6
TG		 2644 int ret = -ENOTSUPP;
2645
2646 ops->retlen = 0;
2647
2648 /* Do not allow writes past end of device */
7014568b 2649 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2650 pr_debug("%s: attempt to write beyond end of device\n",
2651 __func__);
8593fbc6
TG		 2652 return -EINVAL;
2653 }
2654
6a8214aa 2655 nand_get_device(mtd, FL_WRITING);
8593fbc6 2656
f8ac0414 2657 switch (ops->mode) {
0612b9dd
BN		 2658 case MTD_OPS_PLACE_OOB:
2659 case MTD_OPS_AUTO_OOB:
2660 case MTD_OPS_RAW:
8593fbc6
TG		 2661 break;
2662
2663 default:
2664 goto out;
2665 }
2666
2667 if (!ops->datbuf)
2668 ret = nand_do_write_oob(mtd, to, ops);
2669 else
2670 ret = nand_do_write_ops(mtd, to, ops);
2671
7351d3a5 2672out:
1da177e4 2673 nand_release_device(mtd);
1da177e4
LT		 2674 return ret;
2675}
2676
1da177e4 2677/**
49c50b97 2678 * single_erase - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2679 * @mtd: MTD device structure
2680 * @page: the page address of the block which will be erased
1da177e4 2681 *
49c50b97 2682 * Standard erase command for NAND chips. Returns NAND status.
1da177e4 2683 */
49c50b97 2684static int single_erase(struct mtd_info *mtd, int page)
1da177e4 2685{
ace4dfee 2686 struct nand_chip *chip = mtd->priv;
1da177e4 2687 /* Send commands to erase a block */
ace4dfee
TG		 2688 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2689 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
49c50b97
BN		 2690
2691 return chip->waitfunc(mtd, chip);
1da177e4
LT		 2692}
2693
1da177e4
LT		 2694/**
2695 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2696 * @mtd: MTD device structure
2697 * @instr: erase instruction
1da177e4 2698 *
8b6e50c9 2699 * Erase one ore more blocks.
1da177e4 2700 */
e0c7d767 2701static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2702{
e0c7d767 2703 return nand_erase_nand(mtd, instr, 0);
1da177e4 2704}
61b03bd7 2705
1da177e4 2706/**
7854d3f7 2707 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2708 * @mtd: MTD device structure
2709 * @instr: erase instruction
2710 * @allowbbt: allow erasing the bbt area
1da177e4 2711 *
8b6e50c9 2712 * Erase one ore more blocks.
1da177e4 2713 */
ace4dfee
TG		 2714int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2715 int allowbbt)
1da177e4 2716{
69423d99 2717 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2718 struct nand_chip *chip = mtd->priv;
69423d99 2719 loff_t len;
1da177e4 2720
289c0522
BN		 2721 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2722 __func__, (unsigned long long)instr->addr,
2723 (unsigned long long)instr->len);
1da177e4 2724
6fe5a6ac 2725 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2726 return -EINVAL;
1da177e4 2727
1da177e4 2728 /* Grab the lock and see if the device is available */
6a8214aa 2729 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 2730
2731 /* Shift to get first page */
ace4dfee
TG		 2732 page = (int)(instr->addr >> chip->page_shift);
2733 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2734
2735 /* Calculate pages in each block */
ace4dfee 2736 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2737
2738 /* Select the NAND device */
ace4dfee 2739 chip->select_chip(mtd, chipnr);
1da177e4 2740
1da177e4
LT		 2741 /* Check, if it is write protected */
2742 if (nand_check_wp(mtd)) {
289c0522
BN		 2743 pr_debug("%s: device is write protected!\n",
2744 __func__);
1da177e4
LT		 2745 instr->state = MTD_ERASE_FAILED;
2746 goto erase_exit;
2747 }
2748
2749 /* Loop through the pages */
2750 len = instr->len;
2751
2752 instr->state = MTD_ERASING;
2753
2754 while (len) {
12183a20 2755 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2756 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2757 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2758 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2759 __func__, page);
1da177e4
LT		 2760 instr->state = MTD_ERASE_FAILED;
2761 goto erase_exit;
2762 }
61b03bd7 2763
ace4dfee
TG		 2764 /*
2765 * Invalidate the page cache, if we erase the block which
8b6e50c9 2766 * contains the current cached page.
ace4dfee
TG		 2767 */
2768 if (page <= chip->pagebuf && chip->pagebuf <
2769 (page + pages_per_block))
2770 chip->pagebuf = -1;
1da177e4 2771
49c50b97 2772 status = chip->erase(mtd, page & chip->pagemask);
1da177e4 2773
ace4dfee
TG		 2774 /*
2775 * See if operation failed and additional status checks are
2776 * available
2777 */
2778 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2779 status = chip->errstat(mtd, chip, FL_ERASING,
2780 status, page);
068e3c0a 2781
1da177e4 2782 /* See if block erase succeeded */
a4ab4c5d 2783 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2784 pr_debug("%s: failed erase, page 0x%08x\n",
2785 __func__, page);
1da177e4 2786 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2787 instr->fail_addr =
2788 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2789 goto erase_exit;
2790 }
30f464b7 2791
1da177e4 2792 /* Increment page address and decrement length */
daae74ca 2793 len -= (1ULL << chip->phys_erase_shift);
1da177e4
LT		 2794 page += pages_per_block;
2795
2796 /* Check, if we cross a chip boundary */
ace4dfee 2797 if (len && !(page & chip->pagemask)) {
1da177e4 2798 chipnr++;
ace4dfee
TG		 2799 chip->select_chip(mtd, -1);
2800 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2801 }
2802 }
2803 instr->state = MTD_ERASE_DONE;
2804
7351d3a5 2805erase_exit:
1da177e4
LT		 2806
2807 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2808
2809 /* Deselect and wake up anyone waiting on the device */
b0bb6903 2810 chip->select_chip(mtd, -1);
1da177e4
LT		 2811 nand_release_device(mtd);
2812
49defc01
DW		 2813 /* Do call back function */
2814 if (!ret)
2815 mtd_erase_callback(instr);
2816
1da177e4
LT		 2817 /* Return more or less happy */
2818 return ret;
2819}
2820
2821/**
2822 * nand_sync - [MTD Interface] sync
8b6e50c9 2823 * @mtd: MTD device structure
1da177e4 2824 *
8b6e50c9 2825 * Sync is actually a wait for chip ready function.
1da177e4 2826 */
e0c7d767 2827static void nand_sync(struct mtd_info *mtd)
1da177e4 2828{
289c0522 2829 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2830
2831 /* Grab the lock and see if the device is available */
6a8214aa 2832 nand_get_device(mtd, FL_SYNCING);
1da177e4 2833 /* Release it and go back */
e0c7d767 2834 nand_release_device(mtd);
1da177e4
LT		 2835}
2836
1da177e4 2837/**
ace4dfee 2838 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2839 * @mtd: MTD device structure
2840 * @offs: offset relative to mtd start
1da177e4 2841 */
ace4dfee 2842static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2843{
ace4dfee 2844 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2845}
2846
2847/**
ace4dfee 2848 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2849 * @mtd: MTD device structure
2850 * @ofs: offset relative to mtd start
1da177e4 2851 */
e0c7d767 2852static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2853{
1da177e4
LT		 2854 int ret;
2855
f8ac0414
FF		 2856 ret = nand_block_isbad(mtd, ofs);
2857 if (ret) {
8b6e50c9 2858 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2859 if (ret > 0)
2860 return 0;
e0c7d767
DW		 2861 return ret;
2862 }
1da177e4 2863
5a0edb25 2864 return nand_block_markbad_lowlevel(mtd, ofs);
1da177e4
LT		 2865}
2866
7db03ecc
HS		 2867/**
2868 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2869 * @mtd: MTD device structure
2870 * @chip: nand chip info structure
2871 * @addr: feature address.
2872 * @subfeature_param: the subfeature parameters, a four bytes array.
2873 */
2874static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2875 int addr, uint8_t *subfeature_param)
2876{
2877 int status;
05f78359 2878 int i;
7db03ecc 2879
d914c932
DM		 2880 if (!chip->onfi_version ||
2881 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2882 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 2883 return -EINVAL;
2884
2885 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
05f78359
UKK		 2886 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2887 chip->write_byte(mtd, subfeature_param[i]);
2888
7db03ecc
HS		 2889 status = chip->waitfunc(mtd, chip);
2890 if (status & NAND_STATUS_FAIL)
2891 return -EIO;
2892 return 0;
2893}
2894
2895/**
2896 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2897 * @mtd: MTD device structure
2898 * @chip: nand chip info structure
2899 * @addr: feature address.
2900 * @subfeature_param: the subfeature parameters, a four bytes array.
2901 */
2902static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2903 int addr, uint8_t *subfeature_param)
2904{
05f78359
UKK		 2905 int i;
2906
d914c932
DM		 2907 if (!chip->onfi_version ||
2908 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2909 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 2910 return -EINVAL;
2911
2912 /* clear the sub feature parameters */
2913 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2914
2915 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
05f78359
UKK		 2916 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2917 *subfeature_param++ = chip->read_byte(mtd);
7db03ecc
HS		 2918 return 0;
2919}
2920
962034f4
VW		 2921/**
2922 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2923 * @mtd: MTD device structure
962034f4
VW		 2924 */
2925static int nand_suspend(struct mtd_info *mtd)
2926{
6a8214aa 2927 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 2928}
2929
2930/**
2931 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2932 * @mtd: MTD device structure
962034f4
VW		 2933 */
2934static void nand_resume(struct mtd_info *mtd)
2935{
ace4dfee 2936 struct nand_chip *chip = mtd->priv;
962034f4 2937
ace4dfee 2938 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2939 nand_release_device(mtd);
2940 else
d0370219
BN		 2941 pr_err("%s called for a chip which is not in suspended state\n",
2942 __func__);
962034f4
VW		 2943}
2944
72ea4036
SB		 2945/**
2946 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
2947 * prevent further operations
2948 * @mtd: MTD device structure
2949 */
2950static void nand_shutdown(struct mtd_info *mtd)
2951{
2952 nand_get_device(mtd, FL_SHUTDOWN);
2953}
2954
8b6e50c9 2955/* Set default functions */
ace4dfee 2956static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2957{
1da177e4 2958 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2959 if (!chip->chip_delay)
2960 chip->chip_delay = 20;
1da177e4
LT		 2961
2962 /* check, if a user supplied command function given */
ace4dfee
TG		 2963 if (chip->cmdfunc == NULL)
2964 chip->cmdfunc = nand_command;
1da177e4
LT		 2965
2966 /* check, if a user supplied wait function given */
ace4dfee
TG		 2967 if (chip->waitfunc == NULL)
2968 chip->waitfunc = nand_wait;
2969
2970 if (!chip->select_chip)
2971 chip->select_chip = nand_select_chip;
68e80780 2972
4204cccd
HS		 2973 /* set for ONFI nand */
2974 if (!chip->onfi_set_features)
2975 chip->onfi_set_features = nand_onfi_set_features;
2976 if (!chip->onfi_get_features)
2977 chip->onfi_get_features = nand_onfi_get_features;
2978
68e80780
BN		 2979 /* If called twice, pointers that depend on busw may need to be reset */
2980 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 2981 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2982 if (!chip->read_word)
2983 chip->read_word = nand_read_word;
2984 if (!chip->block_bad)
2985 chip->block_bad = nand_block_bad;
2986 if (!chip->block_markbad)
2987 chip->block_markbad = nand_default_block_markbad;
68e80780 2988 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 2989 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
05f78359
UKK		 2990 if (!chip->write_byte || chip->write_byte == nand_write_byte)
2991 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
68e80780 2992 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 2993 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 2994 if (!chip->scan_bbt)
2995 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2996
2997 if (!chip->controller) {
2998 chip->controller = &chip->hwcontrol;
2999 spin_lock_init(&chip->controller->lock);
3000 init_waitqueue_head(&chip->controller->wq);
3001 }
3002
7aa65bfd
TG		 3003}
3004
8b6e50c9 3005/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 3006static void sanitize_string(uint8_t *s, size_t len)
3007{
3008 ssize_t i;
3009
8b6e50c9 3010 /* Null terminate */
d1e1f4e4
FF		 3011 s[len - 1] = 0;
3012
8b6e50c9 3013 /* Remove non printable chars */
d1e1f4e4
FF		 3014 for (i = 0; i < len - 1; i++) {
3015 if (s[i] < ' ' || s[i] > 127)
3016 s[i] = '?';
3017 }
3018
8b6e50c9 3019 /* Remove trailing spaces */
d1e1f4e4
FF		 3020 strim(s);
3021}
3022
3023static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3024{
3025 int i;
3026 while (len--) {
3027 crc ^= *p++ << 8;
3028 for (i = 0; i < 8; i++)
3029 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3030 }
3031
3032 return crc;
3033}
3034
6dcbe0cd
HS		 3035/* Parse the Extended Parameter Page. */
3036static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3037 struct nand_chip *chip, struct nand_onfi_params *p)
3038{
3039 struct onfi_ext_param_page *ep;
3040 struct onfi_ext_section *s;
3041 struct onfi_ext_ecc_info *ecc;
3042 uint8_t *cursor;
3043 int ret = -EINVAL;
3044 int len;
3045 int i;
3046
3047 len = le16_to_cpu(p->ext_param_page_length) * 16;
3048 ep = kmalloc(len, GFP_KERNEL);
5cb13271
BN		 3049 if (!ep)
3050 return -ENOMEM;
6dcbe0cd
HS		 3051
3052 /* Send our own NAND_CMD_PARAM. */
3053 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3054
3055 /* Use the Change Read Column command to skip the ONFI param pages. */
3056 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3057 sizeof(*p) * p->num_of_param_pages , -1);
3058
3059 /* Read out the Extended Parameter Page. */
3060 chip->read_buf(mtd, (uint8_t *)ep, len);
3061 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3062 != le16_to_cpu(ep->crc))) {
3063 pr_debug("fail in the CRC.\n");
3064 goto ext_out;
3065 }
3066
3067 /*
3068 * Check the signature.
3069 * Do not strictly follow the ONFI spec, maybe changed in future.
3070 */
3071 if (strncmp(ep->sig, "EPPS", 4)) {
3072 pr_debug("The signature is invalid.\n");
3073 goto ext_out;
3074 }
3075
3076 /* find the ECC section. */
3077 cursor = (uint8_t *)(ep + 1);
3078 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3079 s = ep->sections + i;
3080 if (s->type == ONFI_SECTION_TYPE_2)
3081 break;
3082 cursor += s->length * 16;
3083 }
3084 if (i == ONFI_EXT_SECTION_MAX) {
3085 pr_debug("We can not find the ECC section.\n");
3086 goto ext_out;
3087 }
3088
3089 /* get the info we want. */
3090 ecc = (struct onfi_ext_ecc_info *)cursor;
3091
4ae7d228
BN		 3092 if (!ecc->codeword_size) {
3093 pr_debug("Invalid codeword size\n");
3094 goto ext_out;
6dcbe0cd
HS		 3095 }
3096
4ae7d228
BN		 3097 chip->ecc_strength_ds = ecc->ecc_bits;
3098 chip->ecc_step_ds = 1 << ecc->codeword_size;
5cb13271 3099 ret = 0;
6dcbe0cd
HS		 3100
3101ext_out:
3102 kfree(ep);
3103 return ret;
3104}
3105
8429bb39
BN		 3106static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3107{
3108 struct nand_chip *chip = mtd->priv;
3109 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3110
3111 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3112 feature);
3113}
3114
3115/*
3116 * Configure chip properties from Micron vendor-specific ONFI table
3117 */
3118static void nand_onfi_detect_micron(struct nand_chip *chip,
3119 struct nand_onfi_params *p)
3120{
3121 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3122
3123 if (le16_to_cpu(p->vendor_revision) < 1)
3124 return;
3125
3126 chip->read_retries = micron->read_retry_options;
3127 chip->setup_read_retry = nand_setup_read_retry_micron;
3128}
3129
6fb277ba 3130/*
8b6e50c9 3131 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 3132 */
3133static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 3134 int *busw)
6fb277ba
FF		 3135{
3136 struct nand_onfi_params *p = &chip->onfi_params;
bd9c6e99 3137 int i, j;
6fb277ba
FF		 3138 int val;
3139
7854d3f7 3140 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 3141 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3142 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3143 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3144 return 0;
3145
6fb277ba
FF		 3146 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3147 for (i = 0; i < 3; i++) {
bd9c6e99
BN		 3148 for (j = 0; j < sizeof(*p); j++)
3149 ((uint8_t *)p)[j] = chip->read_byte(mtd);
6fb277ba
FF		 3150 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3151 le16_to_cpu(p->crc)) {
6fb277ba
FF		 3152 break;
3153 }
3154 }
3155
c7f23a70
BN		 3156 if (i == 3) {
3157 pr_err("Could not find valid ONFI parameter page; aborting\n");
6fb277ba 3158 return 0;
c7f23a70 3159 }
6fb277ba 3160
8b6e50c9 3161 /* Check version */
6fb277ba 3162 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 3163 if (val & (1 << 5))
3164 chip->onfi_version = 23;
3165 else if (val & (1 << 4))
6fb277ba
FF		 3166 chip->onfi_version = 22;
3167 else if (val & (1 << 3))
3168 chip->onfi_version = 21;
3169 else if (val & (1 << 2))
3170 chip->onfi_version = 20;
b7b1a29d 3171 else if (val & (1 << 1))
6fb277ba 3172 chip->onfi_version = 10;
b7b1a29d
BN		 3173
3174 if (!chip->onfi_version) {
20171642 3175 pr_info("unsupported ONFI version: %d\n", val);
b7b1a29d
BN		 3176 return 0;
3177 }
6fb277ba
FF		 3178
3179 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3180 sanitize_string(p->model, sizeof(p->model));
3181 if (!mtd->name)
3182 mtd->name = p->model;
4355b70c 3183
6fb277ba 3184 mtd->writesize = le32_to_cpu(p->byte_per_page);
4355b70c
BN		 3185
3186 /*
3187 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3188 * (don't ask me who thought of this...). MTD assumes that these
3189 * dimensions will be power-of-2, so just truncate the remaining area.
3190 */
3191 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3192 mtd->erasesize *= mtd->writesize;
3193
6fb277ba 3194 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4355b70c
BN		 3195
3196 /* See erasesize comment */
3197 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3198 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
13fbd179 3199 chip->bits_per_cell = p->bits_per_cell;
e2985fc1
HS		 3200
3201 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
08c248fb 3202 *busw = NAND_BUSWIDTH_16;
e2985fc1
HS		 3203 else
3204 *busw = 0;
6fb277ba 3205
10c86bab
HS		 3206 if (p->ecc_bits != 0xff) {
3207 chip->ecc_strength_ds = p->ecc_bits;
3208 chip->ecc_step_ds = 512;
6dcbe0cd
HS		 3209 } else if (chip->onfi_version >= 21 &&
3210 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3211
3212 /*
3213 * The nand_flash_detect_ext_param_page() uses the
3214 * Change Read Column command which maybe not supported
3215 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3216 * now. We do not replace user supplied command function.
3217 */
3218 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3219 chip->cmdfunc = nand_command_lp;
3220
3221 /* The Extended Parameter Page is supported since ONFI 2.1. */
3222 if (nand_flash_detect_ext_param_page(mtd, chip, p))
c7f23a70
BN		 3223 pr_warn("Failed to detect ONFI extended param page\n");
3224 } else {
3225 pr_warn("Could not retrieve ONFI ECC requirements\n");
10c86bab
HS		 3226 }
3227
8429bb39
BN		 3228 if (p->jedec_id == NAND_MFR_MICRON)
3229 nand_onfi_detect_micron(chip, p);
3230
6fb277ba
FF		 3231 return 1;
3232}
3233
91361818
HS		 3234/*
3235 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3236 */
3237static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3238 int *busw)
3239{
3240 struct nand_jedec_params *p = &chip->jedec_params;
3241 struct jedec_ecc_info *ecc;
3242 int val;
3243 int i, j;
3244
3245 /* Try JEDEC for unknown chip or LP */
3246 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3247 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3248 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3249 chip->read_byte(mtd) != 'C')
3250 return 0;
3251
3252 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3253 for (i = 0; i < 3; i++) {
3254 for (j = 0; j < sizeof(*p); j++)
3255 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3256
3257 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3258 le16_to_cpu(p->crc))
3259 break;
3260 }
3261
3262 if (i == 3) {
3263 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3264 return 0;
3265 }
3266
3267 /* Check version */
3268 val = le16_to_cpu(p->revision);
3269 if (val & (1 << 2))
3270 chip->jedec_version = 10;
3271 else if (val & (1 << 1))
3272 chip->jedec_version = 1; /* vendor specific version */
3273
3274 if (!chip->jedec_version) {
3275 pr_info("unsupported JEDEC version: %d\n", val);
3276 return 0;
3277 }
3278
3279 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3280 sanitize_string(p->model, sizeof(p->model));
3281 if (!mtd->name)
3282 mtd->name = p->model;
3283
3284 mtd->writesize = le32_to_cpu(p->byte_per_page);
3285
3286 /* Please reference to the comment for nand_flash_detect_onfi. */
3287 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3288 mtd->erasesize *= mtd->writesize;
3289
3290 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3291
3292 /* Please reference to the comment for nand_flash_detect_onfi. */
3293 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3294 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3295 chip->bits_per_cell = p->bits_per_cell;
3296
3297 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3298 *busw = NAND_BUSWIDTH_16;
3299 else
3300 *busw = 0;
3301
3302 /* ECC info */
3303 ecc = &p->ecc_info[0];
3304
3305 if (ecc->codeword_size >= 9) {
3306 chip->ecc_strength_ds = ecc->ecc_bits;
3307 chip->ecc_step_ds = 1 << ecc->codeword_size;
3308 } else {
3309 pr_warn("Invalid codeword size\n");
3310 }
3311
3312 return 1;
3313}
3314
e3b88bd6
BN		 3315/*
3316 * nand_id_has_period - Check if an ID string has a given wraparound period
3317 * @id_data: the ID string
3318 * @arrlen: the length of the @id_data array
3319 * @period: the period of repitition
3320 *
3321 * Check if an ID string is repeated within a given sequence of bytes at
3322 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3323 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3324 * if the repetition has a period of @period; otherwise, returns zero.
3325 */
3326static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3327{
3328 int i, j;
3329 for (i = 0; i < period; i++)
3330 for (j = i + period; j < arrlen; j += period)
3331 if (id_data[i] != id_data[j])
3332 return 0;
3333 return 1;
3334}
3335
3336/*
3337 * nand_id_len - Get the length of an ID string returned by CMD_READID
3338 * @id_data: the ID string
3339 * @arrlen: the length of the @id_data array
3340
3341 * Returns the length of the ID string, according to known wraparound/trailing
3342 * zero patterns. If no pattern exists, returns the length of the array.
3343 */
3344static int nand_id_len(u8 *id_data, int arrlen)
3345{
3346 int last_nonzero, period;
3347
3348 /* Find last non-zero byte */
3349 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3350 if (id_data[last_nonzero])
3351 break;
3352
3353 /* All zeros */
3354 if (last_nonzero < 0)
3355 return 0;
3356
3357 /* Calculate wraparound period */
3358 for (period = 1; period < arrlen; period++)
3359 if (nand_id_has_period(id_data, arrlen, period))
3360 break;
3361
3362 /* There's a repeated pattern */
3363 if (period < arrlen)
3364 return period;
3365
3366 /* There are trailing zeros */
3367 if (last_nonzero < arrlen - 1)
3368 return last_nonzero + 1;
3369
3370 /* No pattern detected */
3371 return arrlen;
3372}
3373
7db906b7
HS		 3374/* Extract the bits of per cell from the 3rd byte of the extended ID */
3375static int nand_get_bits_per_cell(u8 cellinfo)
3376{
3377 int bits;
3378
3379 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3380 bits >>= NAND_CI_CELLTYPE_SHIFT;
3381 return bits + 1;
3382}
3383
fc09bbc0
BN		 3384/*
3385 * Many new NAND share similar device ID codes, which represent the size of the
3386 * chip. The rest of the parameters must be decoded according to generic or
3387 * manufacturer-specific "extended ID" decoding patterns.
3388 */
3389static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3390 u8 id_data[8], int *busw)
3391{
e3b88bd6 3392 int extid, id_len;
fc09bbc0 3393 /* The 3rd id byte holds MLC / multichip data */
7db906b7 3394 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
fc09bbc0
BN		 3395 /* The 4th id byte is the important one */
3396 extid = id_data[3];
3397
e3b88bd6
BN		 3398 id_len = nand_id_len(id_data, 8);
3399
fc09bbc0
BN		 3400 /*
3401 * Field definitions are in the following datasheets:
3402 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 3403 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 3404 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 3405 *
af451af4
BN		 3406 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3407 * ID to decide what to do.
fc09bbc0 3408 */
af451af4 3409 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
1d0ed69d 3410 !nand_is_slc(chip) && id_data[5] != 0x00) {
fc09bbc0
BN		 3411 /* Calc pagesize */
3412 mtd->writesize = 2048 << (extid & 0x03);
3413 extid >>= 2;
3414 /* Calc oobsize */
e2d3a35e 3415 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 3416 case 1:
3417 mtd->oobsize = 128;
3418 break;
3419 case 2:
3420 mtd->oobsize = 218;
3421 break;
3422 case 3:
3423 mtd->oobsize = 400;
3424 break;
e2d3a35e 3425 case 4:
fc09bbc0
BN		 3426 mtd->oobsize = 436;
3427 break;
e2d3a35e
BN		 3428 case 5:
3429 mtd->oobsize = 512;
3430 break;
3431 case 6:
e2d3a35e
BN		 3432 mtd->oobsize = 640;
3433 break;
94d04e82
HS		 3434 case 7:
3435 default: /* Other cases are "reserved" (unknown) */
3436 mtd->oobsize = 1024;
3437 break;
fc09bbc0
BN		 3438 }
3439 extid >>= 2;
3440 /* Calc blocksize */
3441 mtd->erasesize = (128 * 1024) <<
3442 (((extid >> 1) & 0x04) | (extid & 0x03));
3443 *busw = 0;
73ca392f 3444 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
1d0ed69d 3445 !nand_is_slc(chip)) {
73ca392f
BN		 3446 unsigned int tmp;
3447
3448 /* Calc pagesize */
3449 mtd->writesize = 2048 << (extid & 0x03);
3450 extid >>= 2;
3451 /* Calc oobsize */
3452 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3453 case 0:
3454 mtd->oobsize = 128;
3455 break;
3456 case 1:
3457 mtd->oobsize = 224;
3458 break;
3459 case 2:
3460 mtd->oobsize = 448;
3461 break;
3462 case 3:
3463 mtd->oobsize = 64;
3464 break;
3465 case 4:
3466 mtd->oobsize = 32;
3467 break;
3468 case 5:
3469 mtd->oobsize = 16;
3470 break;
3471 default:
3472 mtd->oobsize = 640;
3473 break;
3474 }
3475 extid >>= 2;
3476 /* Calc blocksize */
3477 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3478 if (tmp < 0x03)
3479 mtd->erasesize = (128 * 1024) << tmp;
3480 else if (tmp == 0x03)
3481 mtd->erasesize = 768 * 1024;
3482 else
3483 mtd->erasesize = (64 * 1024) << tmp;
3484 *busw = 0;
fc09bbc0
BN		 3485 } else {
3486 /* Calc pagesize */
3487 mtd->writesize = 1024 << (extid & 0x03);
3488 extid >>= 2;
3489 /* Calc oobsize */
3490 mtd->oobsize = (8 << (extid & 0x01)) *
3491 (mtd->writesize >> 9);
3492 extid >>= 2;
3493 /* Calc blocksize. Blocksize is multiples of 64KiB */
3494 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3495 extid >>= 2;
3496 /* Get buswidth information */
3497 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
60c67382
BN		 3498
3499 /*
3500 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3501 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3502 * follows:
3503 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3504 * 110b -> 24nm
3505 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3506 */
3507 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
1d0ed69d 3508 nand_is_slc(chip) &&
60c67382
BN		 3509 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3510 !(id_data[4] & 0x80) /* !BENAND */) {
3511 mtd->oobsize = 32 * mtd->writesize >> 9;
3512 }
3513
fc09bbc0
BN		 3514 }
3515}
3516
f23a481c
BN		 3517/*
3518 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3519 * decodes a matching ID table entry and assigns the MTD size parameters for
3520 * the chip.
3521 */
3522static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3523 struct nand_flash_dev *type, u8 id_data[8],
3524 int *busw)
3525{
3526 int maf_id = id_data[0];
3527
3528 mtd->erasesize = type->erasesize;
3529 mtd->writesize = type->pagesize;
3530 mtd->oobsize = mtd->writesize / 32;
3531 *busw = type->options & NAND_BUSWIDTH_16;
3532
1c195e90
HS		 3533 /* All legacy ID NAND are small-page, SLC */
3534 chip->bits_per_cell = 1;
3535
f23a481c
BN		 3536 /*
3537 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3538 * some Spansion chips have erasesize that conflicts with size
3539 * listed in nand_ids table.
3540 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3541 */
3542 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3543 && id_data[6] == 0x00 && id_data[7] == 0x00
3544 && mtd->writesize == 512) {
3545 mtd->erasesize = 128 * 1024;
3546 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3547 }
3548}
3549
7e74c2d7
BN		 3550/*
3551 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3552 * heuristic patterns using various detected parameters (e.g., manufacturer,
3553 * page size, cell-type information).
3554 */
3555static void nand_decode_bbm_options(struct mtd_info *mtd,
3556 struct nand_chip *chip, u8 id_data[8])
3557{
3558 int maf_id = id_data[0];
3559
3560 /* Set the bad block position */
3561 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3562 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3563 else
3564 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3565
3566 /*
3567 * Bad block marker is stored in the last page of each block on Samsung
3568 * and Hynix MLC devices; stored in first two pages of each block on
3569 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3570 * AMD/Spansion, and Macronix. All others scan only the first page.
3571 */
1d0ed69d 3572 if (!nand_is_slc(chip) &&
7e74c2d7
BN		 3573 (maf_id == NAND_MFR_SAMSUNG ||
3574 maf_id == NAND_MFR_HYNIX))
3575 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
1d0ed69d 3576 else if ((nand_is_slc(chip) &&
7e74c2d7
BN		 3577 (maf_id == NAND_MFR_SAMSUNG ||
3578 maf_id == NAND_MFR_HYNIX ||
3579 maf_id == NAND_MFR_TOSHIBA ||
3580 maf_id == NAND_MFR_AMD ||
3581 maf_id == NAND_MFR_MACRONIX)) ||
3582 (mtd->writesize == 2048 &&
3583 maf_id == NAND_MFR_MICRON))
3584 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3585}
3586
ec6e87e3
HS		 3587static inline bool is_full_id_nand(struct nand_flash_dev *type)
3588{
3589 return type->id_len;
3590}
3591
3592static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3593 struct nand_flash_dev *type, u8 *id_data, int *busw)
3594{
3595 if (!strncmp(type->id, id_data, type->id_len)) {
3596 mtd->writesize = type->pagesize;
3597 mtd->erasesize = type->erasesize;
3598 mtd->oobsize = type->oobsize;
3599
7db906b7 3600 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
ec6e87e3
HS		 3601 chip->chipsize = (uint64_t)type->chipsize << 20;
3602 chip->options |= type->options;
57219342
HS		 3603 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3604 chip->ecc_step_ds = NAND_ECC_STEP(type);
57a94e24
BB		 3605 chip->onfi_timing_mode_default =
3606 type->onfi_timing_mode_default;
ec6e87e3
HS		 3607
3608 *busw = type->options & NAND_BUSWIDTH_16;
3609
092b6a1d
CZ		 3610 if (!mtd->name)
3611 mtd->name = type->name;
3612
ec6e87e3
HS		 3613 return true;
3614 }
3615 return false;
3616}
3617
7aa65bfd 3618/*
8b6e50c9 3619 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3620 */
3621static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3622 struct nand_chip *chip,
7351d3a5 3623 int *maf_id, int *dev_id,
5e81e88a 3624 struct nand_flash_dev *type)
7aa65bfd 3625{
bb77082f 3626 int busw;
d1e1f4e4 3627 int i, maf_idx;
426c457a 3628 u8 id_data[8];
1da177e4
LT		 3629
3630 /* Select the device */
ace4dfee 3631 chip->select_chip(mtd, 0);
1da177e4 3632
ef89a880
KB		 3633 /*
3634 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3635 * after power-up.
ef89a880
KB		 3636 */
3637 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3638
1da177e4 3639 /* Send the command for reading device ID */
ace4dfee 3640 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3641
3642 /* Read manufacturer and device IDs */
ace4dfee 3643 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3644 *dev_id = chip->read_byte(mtd);
1da177e4 3645
8b6e50c9
BN		 3646 /*
3647 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3648 * interface concerns can cause random data which looks like a
3649 * possibly credible NAND flash to appear. If the two results do
3650 * not match, ignore the device completely.
3651 */
3652
3653 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3654
4aef9b78
BN		 3655 /* Read entire ID string */
3656 for (i = 0; i < 8; i++)
426c457a 3657 id_data[i] = chip->read_byte(mtd);
ed8165c7 3658
d1e1f4e4 3659 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
20171642 3660 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
d0370219 3661 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3662 return ERR_PTR(-ENODEV);
3663 }
3664
7aa65bfd 3665 if (!type)
5e81e88a
DW		 3666 type = nand_flash_ids;
3667
ec6e87e3
HS		 3668 for (; type->name != NULL; type++) {
3669 if (is_full_id_nand(type)) {
3670 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3671 goto ident_done;
3672 } else if (*dev_id == type->dev_id) {
3673 break;
3674 }
3675 }
5e81e88a 3676
d1e1f4e4
FF		 3677 chip->onfi_version = 0;
3678 if (!type->name || !type->pagesize) {
35fc5195 3679 /* Check if the chip is ONFI compliant */
47450b35 3680 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3681 goto ident_done;
91361818
HS		 3682
3683 /* Check if the chip is JEDEC compliant */
3684 if (nand_flash_detect_jedec(mtd, chip, &busw))
3685 goto ident_done;
d1e1f4e4
FF		 3686 }
3687
5e81e88a 3688 if (!type->name)
7aa65bfd
TG		 3689 return ERR_PTR(-ENODEV);
3690
ba0251fe
TG		 3691 if (!mtd->name)
3692 mtd->name = type->name;
3693
69423d99 3694 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3695
12a40a57 3696 if (!type->pagesize && chip->init_size) {
8b6e50c9 3697 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3698 busw = chip->init_size(mtd, chip, id_data);
3699 } else if (!type->pagesize) {
fc09bbc0
BN		 3700 /* Decode parameters from extended ID */
3701 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3702 } else {
f23a481c 3703 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3704 }
bf7a01bf
BN		 3705 /* Get chip options */
3706 chip->options |= type->options;
d1e1f4e4 3707
8b6e50c9
BN		 3708 /*
3709 * Check if chip is not a Samsung device. Do not clear the
3710 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3711 */
3712 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3713 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3714ident_done:
3715
7aa65bfd 3716 /* Try to identify manufacturer */
9a909867 3717 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3718 if (nand_manuf_ids[maf_idx].id == *maf_id)
3719 break;
3720 }
0ea4a755 3721
64b37b2a
MC		 3722 if (chip->options & NAND_BUSWIDTH_AUTO) {
3723 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3724 chip->options |= busw;
3725 nand_set_defaults(chip, busw);
3726 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3727 /*
3728 * Check, if buswidth is correct. Hardware drivers should set
3729 * chip correct!
3730 */
20171642
EG		 3731 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3732 *maf_id, *dev_id);
3733 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3734 pr_warn("bus width %d instead %d bit\n",
d0370219
BN		 3735 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3736 busw ? 16 : 8);
7aa65bfd
TG		 3737 return ERR_PTR(-EINVAL);
3738 }
61b03bd7 3739
7e74c2d7
BN		 3740 nand_decode_bbm_options(mtd, chip, id_data);
3741
7aa65bfd 3742 /* Calculate the address shift from the page size */
ace4dfee 3743 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3744 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3745 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3746
ace4dfee 3747 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3748 ffs(mtd->erasesize) - 1;
69423d99
AH		 3749 if (chip->chipsize & 0xffffffff)
3750 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3751 else {
3752 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3753 chip->chip_shift += 32 - 1;
3754 }
1da177e4 3755
26d9be11 3756 chip->badblockbits = 8;
49c50b97 3757 chip->erase = single_erase;
7aa65bfd 3758
8b6e50c9 3759 /* Do not replace user supplied command function! */
ace4dfee
TG		 3760 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3761 chip->cmdfunc = nand_command_lp;
7aa65bfd 3762
20171642
EG		 3763 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3764 *maf_id, *dev_id);
ffdac6cd
HS		 3765
3766 if (chip->onfi_version)
3767 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3768 chip->onfi_params.model);
3769 else if (chip->jedec_version)
3770 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3771 chip->jedec_params.model);
3772 else
3773 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3774 type->name);
3775
3755a991 3776 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3723e93c 3777 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3755a991 3778 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3779 return type;
3780}
3781
7aa65bfd 3782/**
3b85c321 3783 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3784 * @mtd: MTD device structure
3785 * @maxchips: number of chips to scan for
3786 * @table: alternative NAND ID table
7aa65bfd 3787 *
8b6e50c9
BN		 3788 * This is the first phase of the normal nand_scan() function. It reads the
3789 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3790 *
3b85c321 3791 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3792 */
5e81e88a
DW		 3793int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3794 struct nand_flash_dev *table)
7aa65bfd 3795{
bb77082f 3796 int i, nand_maf_id, nand_dev_id;
ace4dfee 3797 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3798 struct nand_flash_dev *type;
3799
7aa65bfd 3800 /* Set the default functions */
bb77082f 3801 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
7aa65bfd
TG		 3802
3803 /* Read the flash type */
bb77082f
CZ		 3804 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3805 &nand_dev_id, table);
7aa65bfd
TG		 3806
3807 if (IS_ERR(type)) {
b1c6e6db 3808 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3809 pr_warn("No NAND device found\n");
ace4dfee 3810 chip->select_chip(mtd, -1);
7aa65bfd 3811 return PTR_ERR(type);
1da177e4
LT		 3812 }
3813
07300164
HS		 3814 chip->select_chip(mtd, -1);
3815
7aa65bfd 3816 /* Check for a chip array */
e0c7d767 3817 for (i = 1; i < maxchips; i++) {
ace4dfee 3818 chip->select_chip(mtd, i);
ef89a880
KB		 3819 /* See comment in nand_get_flash_type for reset */
3820 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3821 /* Send the command for reading device ID */
ace4dfee 3822 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3823 /* Read manufacturer and device IDs */
ace4dfee 3824 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 3825 nand_dev_id != chip->read_byte(mtd)) {
3826 chip->select_chip(mtd, -1);
1da177e4 3827 break;
07300164
HS		 3828 }
3829 chip->select_chip(mtd, -1);
1da177e4
LT		 3830 }
3831 if (i > 1)
20171642 3832 pr_info("%d chips detected\n", i);
61b03bd7 3833
1da177e4 3834 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3835 chip->numchips = i;
3836 mtd->size = i * chip->chipsize;
7aa65bfd 3837
3b85c321
DW		 3838 return 0;
3839}
7351d3a5 3840EXPORT_SYMBOL(nand_scan_ident);
3b85c321 3841
67a9ad9b
EG		 3842/*
3843 * Check if the chip configuration meet the datasheet requirements.
3844
3845 * If our configuration corrects A bits per B bytes and the minimum
3846 * required correction level is X bits per Y bytes, then we must ensure
3847 * both of the following are true:
3848 *
3849 * (1) A / B >= X / Y
3850 * (2) A >= X
3851 *
3852 * Requirement (1) ensures we can correct for the required bitflip density.
3853 * Requirement (2) ensures we can correct even when all bitflips are clumped
3854 * in the same sector.
3855 */
3856static bool nand_ecc_strength_good(struct mtd_info *mtd)
3857{
3858 struct nand_chip *chip = mtd->priv;
3859 struct nand_ecc_ctrl *ecc = &chip->ecc;
3860 int corr, ds_corr;
3861
3862 if (ecc->size == 0 || chip->ecc_step_ds == 0)
3863 /* Not enough information */
3864 return true;
3865
3866 /*
3867 * We get the number of corrected bits per page to compare
3868 * the correction density.
3869 */
3870 corr = (mtd->writesize * ecc->strength) / ecc->size;
3871 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
3872
3873 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
3874}
3b85c321
DW		 3875
3876/**
3877 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3878 * @mtd: MTD device structure
3b85c321 3879 *
8b6e50c9
BN		 3880 * This is the second phase of the normal nand_scan() function. It fills out
3881 * all the uninitialized function pointers with the defaults and scans for a
3882 * bad block table if appropriate.
3b85c321
DW		 3883 */
3884int nand_scan_tail(struct mtd_info *mtd)
3885{
3886 int i;
3887 struct nand_chip *chip = mtd->priv;
97de79e0 3888 struct nand_ecc_ctrl *ecc = &chip->ecc;
f02ea4e6 3889 struct nand_buffers *nbuf;
3b85c321 3890
e2414f4c
BN		 3891 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3892 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3893 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3894
f02ea4e6
HS		 3895 if (!(chip->options & NAND_OWN_BUFFERS)) {
3896 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
3897 + mtd->oobsize * 3, GFP_KERNEL);
3898 if (!nbuf)
3899 return -ENOMEM;
3900 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
3901 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
3902 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
3903
3904 chip->buffers = nbuf;
3905 } else {
3906 if (!chip->buffers)
3907 return -ENOMEM;
3908 }
4bf63fcb 3909
7dcdcbef 3910 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3911 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3912
7aa65bfd 3913 /*
8b6e50c9 3914 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3915 */
97de79e0 3916 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3917 switch (mtd->oobsize) {
1da177e4 3918 case 8:
97de79e0 3919 ecc->layout = &nand_oob_8;
1da177e4
LT		 3920 break;
3921 case 16:
97de79e0 3922 ecc->layout = &nand_oob_16;
1da177e4
LT		 3923 break;
3924 case 64:
97de79e0 3925 ecc->layout = &nand_oob_64;
1da177e4 3926 break;
81ec5364 3927 case 128:
97de79e0 3928 ecc->layout = &nand_oob_128;
81ec5364 3929 break;
1da177e4 3930 default:
d0370219
BN		 3931 pr_warn("No oob scheme defined for oobsize %d\n",
3932 mtd->oobsize);
1da177e4
LT		 3933 BUG();
3934 }
3935 }
61b03bd7 3936
956e944c
DW		 3937 if (!chip->write_page)
3938 chip->write_page = nand_write_page;
3939
61b03bd7 3940 /*
8b6e50c9 3941 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3942 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3943 */
956e944c 3944
97de79e0 3945 switch (ecc->mode) {
6e0cb135
SN		 3946 case NAND_ECC_HW_OOB_FIRST:
3947 /* Similar to NAND_ECC_HW, but a separate read_page handle */
97de79e0 3948 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
2ac63d90 3949 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
6e0cb135
SN		 3950 BUG();
3951 }
97de79e0
HS		 3952 if (!ecc->read_page)
3953 ecc->read_page = nand_read_page_hwecc_oob_first;
6e0cb135 3954
6dfc6d25 3955 case NAND_ECC_HW:
8b6e50c9 3956 /* Use standard hwecc read page function? */
97de79e0
HS		 3957 if (!ecc->read_page)
3958 ecc->read_page = nand_read_page_hwecc;
3959 if (!ecc->write_page)
3960 ecc->write_page = nand_write_page_hwecc;
3961 if (!ecc->read_page_raw)
3962 ecc->read_page_raw = nand_read_page_raw;
3963 if (!ecc->write_page_raw)
3964 ecc->write_page_raw = nand_write_page_raw;
3965 if (!ecc->read_oob)
3966 ecc->read_oob = nand_read_oob_std;
3967 if (!ecc->write_oob)
3968 ecc->write_oob = nand_write_oob_std;
3969 if (!ecc->read_subpage)
3970 ecc->read_subpage = nand_read_subpage;
3971 if (!ecc->write_subpage)
3972 ecc->write_subpage = nand_write_subpage_hwecc;
f5bbdacc 3973
6dfc6d25 3974 case NAND_ECC_HW_SYNDROME:
97de79e0
HS		 3975 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
3976 (!ecc->read_page ||
3977 ecc->read_page == nand_read_page_hwecc ||
3978 !ecc->write_page ||
3979 ecc->write_page == nand_write_page_hwecc)) {
2ac63d90 3980 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
6dfc6d25
TG		 3981 BUG();
3982 }
8b6e50c9 3983 /* Use standard syndrome read/write page function? */
97de79e0
HS		 3984 if (!ecc->read_page)
3985 ecc->read_page = nand_read_page_syndrome;
3986 if (!ecc->write_page)
3987 ecc->write_page = nand_write_page_syndrome;
3988 if (!ecc->read_page_raw)
3989 ecc->read_page_raw = nand_read_page_raw_syndrome;
3990 if (!ecc->write_page_raw)
3991 ecc->write_page_raw = nand_write_page_raw_syndrome;
3992 if (!ecc->read_oob)
3993 ecc->read_oob = nand_read_oob_syndrome;
3994 if (!ecc->write_oob)
3995 ecc->write_oob = nand_write_oob_syndrome;
3996
3997 if (mtd->writesize >= ecc->size) {
3998 if (!ecc->strength) {
e2788c98
MD		 3999 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4000 BUG();
4001 }
6dfc6d25 4002 break;
e2788c98 4003 }
2ac63d90
RM		 4004 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4005 ecc->size, mtd->writesize);
97de79e0 4006 ecc->mode = NAND_ECC_SOFT;
61b03bd7 4007
6dfc6d25 4008 case NAND_ECC_SOFT:
97de79e0
HS		 4009 ecc->calculate = nand_calculate_ecc;
4010 ecc->correct = nand_correct_data;
4011 ecc->read_page = nand_read_page_swecc;
4012 ecc->read_subpage = nand_read_subpage;
4013 ecc->write_page = nand_write_page_swecc;
4014 ecc->read_page_raw = nand_read_page_raw;
4015 ecc->write_page_raw = nand_write_page_raw;
4016 ecc->read_oob = nand_read_oob_std;
4017 ecc->write_oob = nand_write_oob_std;
4018 if (!ecc->size)
4019 ecc->size = 256;
4020 ecc->bytes = 3;
4021 ecc->strength = 1;
1da177e4 4022 break;
61b03bd7 4023
193bd400
ID		 4024 case NAND_ECC_SOFT_BCH:
4025 if (!mtd_nand_has_bch()) {
148256fa 4026 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
193bd400
ID		 4027 BUG();
4028 }
97de79e0
HS		 4029 ecc->calculate = nand_bch_calculate_ecc;
4030 ecc->correct = nand_bch_correct_data;
4031 ecc->read_page = nand_read_page_swecc;
4032 ecc->read_subpage = nand_read_subpage;
4033 ecc->write_page = nand_write_page_swecc;
4034 ecc->read_page_raw = nand_read_page_raw;
4035 ecc->write_page_raw = nand_write_page_raw;
4036 ecc->read_oob = nand_read_oob_std;
4037 ecc->write_oob = nand_write_oob_std;
193bd400 4038 /*
e0377cde
AS		 4039 * Board driver should supply ecc.size and ecc.strength values
4040 * to select how many bits are correctable. Otherwise, default
4041 * to 4 bits for large page devices.
193bd400 4042 */
97de79e0
HS		 4043 if (!ecc->size && (mtd->oobsize >= 64)) {
4044 ecc->size = 512;
e0377cde 4045 ecc->strength = 4;
193bd400 4046 }
e0377cde
AS		 4047
4048 /* See nand_bch_init() for details. */
4049 ecc->bytes = DIV_ROUND_UP(
4050 ecc->strength * fls(8 * ecc->size), 8);
97de79e0
HS		 4051 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4052 &ecc->layout);
4053 if (!ecc->priv) {
9a4d4d69 4054 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 4055 BUG();
4056 }
4057 break;
4058
61b03bd7 4059 case NAND_ECC_NONE:
2ac63d90 4060 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
97de79e0
HS		 4061 ecc->read_page = nand_read_page_raw;
4062 ecc->write_page = nand_write_page_raw;
4063 ecc->read_oob = nand_read_oob_std;
4064 ecc->read_page_raw = nand_read_page_raw;
4065 ecc->write_page_raw = nand_write_page_raw;
4066 ecc->write_oob = nand_write_oob_std;
4067 ecc->size = mtd->writesize;
4068 ecc->bytes = 0;
4069 ecc->strength = 0;
1da177e4 4070 break;
956e944c 4071
1da177e4 4072 default:
97de79e0 4073 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
61b03bd7 4074 BUG();
1da177e4 4075 }
61b03bd7 4076
9ce244b3 4077 /* For many systems, the standard OOB write also works for raw */
97de79e0
HS		 4078 if (!ecc->read_oob_raw)
4079 ecc->read_oob_raw = ecc->read_oob;
4080 if (!ecc->write_oob_raw)
4081 ecc->write_oob_raw = ecc->write_oob;
9ce244b3 4082
5bd34c09
TG		 4083 /*
4084 * The number of bytes available for a client to place data into
8b6e50c9 4085 * the out of band area.
5bd34c09 4086 */
97de79e0
HS		 4087 ecc->layout->oobavail = 0;
4088 for (i = 0; ecc->layout->oobfree[i].length
4089 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4090 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4091 mtd->oobavail = ecc->layout->oobavail;
5bd34c09 4092
54c39e9b
TP		 4093 /* ECC sanity check: warn if it's too weak */
4094 if (!nand_ecc_strength_good(mtd))
4095 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4096 mtd->name);
67a9ad9b 4097
7aa65bfd
TG		 4098 /*
4099 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 4100 * mode.
7aa65bfd 4101 */
97de79e0
HS		 4102 ecc->steps = mtd->writesize / ecc->size;
4103 if (ecc->steps * ecc->size != mtd->writesize) {
9a4d4d69 4104 pr_warn("Invalid ECC parameters\n");
6dfc6d25 4105 BUG();
1da177e4 4106 }
97de79e0 4107 ecc->total = ecc->steps * ecc->bytes;
61b03bd7 4108
8b6e50c9 4109 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
1d0ed69d 4110 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
97de79e0 4111 switch (ecc->steps) {
29072b96
TG		 4112 case 2:
4113 mtd->subpage_sft = 1;
4114 break;
4115 case 4:
4116 case 8:
81ec5364 4117 case 16:
29072b96
TG		 4118 mtd->subpage_sft = 2;
4119 break;
4120 }
4121 }
4122 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4123
04bbd0ea 4124 /* Initialize state */
ace4dfee 4125 chip->state = FL_READY;
1da177e4 4126
1da177e4 4127 /* Invalidate the pagebuffer reference */
ace4dfee 4128 chip->pagebuf = -1;
1da177e4 4129
a5ff4f10 4130 /* Large page NAND with SOFT_ECC should support subpage reads */
4007e2d1
RL		 4131 switch (ecc->mode) {
4132 case NAND_ECC_SOFT:
4133 case NAND_ECC_SOFT_BCH:
4134 if (chip->page_shift > 9)
4135 chip->options |= NAND_SUBPAGE_READ;
4136 break;
4137
4138 default:
4139 break;
4140 }
a5ff4f10 4141
1da177e4 4142 /* Fill in remaining MTD driver data */
963d1c28 4143 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
93edbad6
ML		 4144 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4145 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 4146 mtd->_erase = nand_erase;
4147 mtd->_point = NULL;
4148 mtd->_unpoint = NULL;
4149 mtd->_read = nand_read;
4150 mtd->_write = nand_write;
4151 mtd->_panic_write = panic_nand_write;
4152 mtd->_read_oob = nand_read_oob;
4153 mtd->_write_oob = nand_write_oob;
4154 mtd->_sync = nand_sync;
4155 mtd->_lock = NULL;
4156 mtd->_unlock = NULL;
4157 mtd->_suspend = nand_suspend;
4158 mtd->_resume = nand_resume;
72ea4036 4159 mtd->_reboot = nand_shutdown;
8471bb73 4160 mtd->_block_isreserved = nand_block_isreserved;
3c3c10bb
AB		 4161 mtd->_block_isbad = nand_block_isbad;
4162 mtd->_block_markbad = nand_block_markbad;
cbcab65a 4163 mtd->writebufsize = mtd->writesize;
1da177e4 4164
6a918bad 4165 /* propagate ecc info to mtd_info */
97de79e0
HS		 4166 mtd->ecclayout = ecc->layout;
4167 mtd->ecc_strength = ecc->strength;
4168 mtd->ecc_step_size = ecc->size;
ea3b2ea2
SL		 4169 /*
4170 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4171 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4172 * properly set.
4173 */
4174 if (!mtd->bitflip_threshold)
240181fd 4175 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
1da177e4 4176
0040bf38 4177 /* Check, if we should skip the bad block table scan */
ace4dfee 4178 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 4179 return 0;
1da177e4
LT		 4180
4181 /* Build bad block table */
ace4dfee 4182 return chip->scan_bbt(mtd);
1da177e4 4183}
7351d3a5 4184EXPORT_SYMBOL(nand_scan_tail);
1da177e4 4185
8b6e50c9
BN		 4186/*
4187 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 4188 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 4189 * to call us from in-kernel code if the core NAND support is modular.
4190 */
3b85c321
DW		 4191#ifdef MODULE
4192#define caller_is_module() (1)
4193#else
4194#define caller_is_module() \
a6e6abd5 4195 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 4196#endif
4197
4198/**
4199 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4200 * @mtd: MTD device structure
4201 * @maxchips: number of chips to scan for
3b85c321 4202 *
8b6e50c9
BN		 4203 * This fills out all the uninitialized function pointers with the defaults.
4204 * The flash ID is read and the mtd/chip structures are filled with the
4205 * appropriate values. The mtd->owner field must be set to the module of the
4206 * caller.
3b85c321
DW		 4207 */
4208int nand_scan(struct mtd_info *mtd, int maxchips)
4209{
4210 int ret;
4211
4212 /* Many callers got this wrong, so check for it for a while... */
4213 if (!mtd->owner && caller_is_module()) {
d0370219 4214 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 4215 BUG();
4216 }
4217
5e81e88a 4218 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 4219 if (!ret)
4220 ret = nand_scan_tail(mtd);
4221 return ret;
4222}
7351d3a5 4223EXPORT_SYMBOL(nand_scan);
3b85c321 4224
1da177e4 4225/**
61b03bd7 4226 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 4227 * @mtd: MTD device structure
4228 */
e0c7d767 4229void nand_release(struct mtd_info *mtd)
1da177e4 4230{
ace4dfee 4231 struct nand_chip *chip = mtd->priv;
1da177e4 4232
193bd400
ID		 4233 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4234 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4235
5ffcaf3d 4236 mtd_device_unregister(mtd);
1da177e4 4237
fa671646 4238 /* Free bad block table memory */
ace4dfee 4239 kfree(chip->bbt);
4bf63fcb
DW		 4240 if (!(chip->options & NAND_OWN_BUFFERS))
4241 kfree(chip->buffers);
58373ff0
BN		 4242
4243 /* Free bad block descriptor memory */
4244 if (chip->badblock_pattern && chip->badblock_pattern->options
4245 & NAND_BBT_DYNAMICSTRUCT)
4246 kfree(chip->badblock_pattern);
1da177e4 4247}
e0c7d767 4248EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 4249
4250static int __init nand_base_init(void)
4251{
4252 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4253 return 0;
4254}
4255
4256static void __exit nand_base_exit(void)
4257{
4258 led_trigger_unregister_simple(nand_led_trigger);
4259}
4260
4261module_init(nand_base_init);
4262module_exit(nand_base_exit);
4263
e0c7d767 4264MODULE_LICENSE("GPL");
7351d3a5
FF		 4265MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4266MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 4267MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux kernel - Deliverables
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