Commit | Line | Data |
---|---|---|
ce4c61f1 | 1 | /* |
ce4c61f1 | 2 | * Overview: |
a808ad3b | 3 | * Platform independent driver for NDFC (NanD Flash Controller) |
ce4c61f1 TG |
4 | * integrated into EP440 cores |
5 | * | |
a808ad3b SM |
6 | * Ported to an OF platform driver by Sean MacLennan |
7 | * | |
8 | * The NDFC supports multiple chips, but this driver only supports a | |
9 | * single chip since I do not have access to any boards with | |
10 | * multiple chips. | |
11 | * | |
ce4c61f1 TG |
12 | * Author: Thomas Gleixner |
13 | * | |
14 | * Copyright 2006 IBM | |
a808ad3b SM |
15 | * Copyright 2008 PIKA Technologies |
16 | * Sean MacLennan <smaclennan@pikatech.com> | |
ce4c61f1 TG |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify it | |
19 | * under the terms of the GNU General Public License as published by the | |
20 | * Free Software Foundation; either version 2 of the License, or (at your | |
21 | * option) any later version. | |
22 | * | |
23 | */ | |
24 | #include <linux/module.h> | |
25 | #include <linux/mtd/nand.h> | |
26 | #include <linux/mtd/nand_ecc.h> | |
27 | #include <linux/mtd/partitions.h> | |
28 | #include <linux/mtd/ndfc.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
ce4c61f1 | 30 | #include <linux/mtd/mtd.h> |
5af50730 | 31 | #include <linux/of_address.h> |
a808ad3b | 32 | #include <linux/of_platform.h> |
ce4c61f1 | 33 | #include <asm/io.h> |
ce4c61f1 | 34 | |
410fe2f0 | 35 | #define NDFC_MAX_CS 4 |
ce4c61f1 TG |
36 | |
37 | struct ndfc_controller { | |
2dc11581 | 38 | struct platform_device *ofdev; |
a808ad3b SM |
39 | void __iomem *ndfcbase; |
40 | struct mtd_info mtd; | |
41 | struct nand_chip chip; | |
42 | int chip_select; | |
43 | struct nand_hw_control ndfc_control; | |
ce4c61f1 TG |
44 | }; |
45 | ||
410fe2f0 | 46 | static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS]; |
ce4c61f1 TG |
47 | |
48 | static void ndfc_select_chip(struct mtd_info *mtd, int chip) | |
49 | { | |
50 | uint32_t ccr; | |
410fe2f0 FR |
51 | struct nand_chip *nchip = mtd->priv; |
52 | struct ndfc_controller *ndfc = nchip->priv; | |
ce4c61f1 | 53 | |
a808ad3b | 54 | ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
ce4c61f1 TG |
55 | if (chip >= 0) { |
56 | ccr &= ~NDFC_CCR_BS_MASK; | |
a808ad3b | 57 | ccr |= NDFC_CCR_BS(chip + ndfc->chip_select); |
ce4c61f1 TG |
58 | } else |
59 | ccr |= NDFC_CCR_RESET_CE; | |
a808ad3b | 60 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 TG |
61 | } |
62 | ||
7abd3ef9 | 63 | static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
ce4c61f1 | 64 | { |
410fe2f0 FR |
65 | struct nand_chip *chip = mtd->priv; |
66 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 | 67 | |
7abd3ef9 TG |
68 | if (cmd == NAND_CMD_NONE) |
69 | return; | |
70 | ||
71 | if (ctrl & NAND_CLE) | |
1794c130 | 72 | writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD); |
7abd3ef9 | 73 | else |
1794c130 | 74 | writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE); |
ce4c61f1 TG |
75 | } |
76 | ||
77 | static int ndfc_ready(struct mtd_info *mtd) | |
78 | { | |
410fe2f0 FR |
79 | struct nand_chip *chip = mtd->priv; |
80 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 | 81 | |
a808ad3b | 82 | return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY; |
ce4c61f1 TG |
83 | } |
84 | ||
85 | static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode) | |
86 | { | |
87 | uint32_t ccr; | |
410fe2f0 FR |
88 | struct nand_chip *chip = mtd->priv; |
89 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 | 90 | |
a808ad3b | 91 | ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
ce4c61f1 | 92 | ccr |= NDFC_CCR_RESET_ECC; |
a808ad3b | 93 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 TG |
94 | wmb(); |
95 | } | |
96 | ||
97 | static int ndfc_calculate_ecc(struct mtd_info *mtd, | |
98 | const u_char *dat, u_char *ecc_code) | |
99 | { | |
410fe2f0 FR |
100 | struct nand_chip *chip = mtd->priv; |
101 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
102 | uint32_t ecc; |
103 | uint8_t *p = (uint8_t *)&ecc; | |
104 | ||
105 | wmb(); | |
a808ad3b SM |
106 | ecc = in_be32(ndfc->ndfcbase + NDFC_ECC); |
107 | /* The NDFC uses Smart Media (SMC) bytes order */ | |
76c23c32 FK |
108 | ecc_code[0] = p[1]; |
109 | ecc_code[1] = p[2]; | |
ce4c61f1 TG |
110 | ecc_code[2] = p[3]; |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | /* | |
116 | * Speedups for buffer read/write/verify | |
117 | * | |
118 | * NDFC allows 32bit read/write of data. So we can speed up the buffer | |
119 | * functions. No further checking, as nand_base will always read/write | |
120 | * page aligned. | |
121 | */ | |
122 | static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
123 | { | |
410fe2f0 FR |
124 | struct nand_chip *chip = mtd->priv; |
125 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
126 | uint32_t *p = (uint32_t *) buf; |
127 | ||
128 | for(;len > 0; len -= 4) | |
a808ad3b | 129 | *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA); |
ce4c61f1 TG |
130 | } |
131 | ||
132 | static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
133 | { | |
410fe2f0 FR |
134 | struct nand_chip *chip = mtd->priv; |
135 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
136 | uint32_t *p = (uint32_t *) buf; |
137 | ||
138 | for(;len > 0; len -= 4) | |
a808ad3b | 139 | out_be32(ndfc->ndfcbase + NDFC_DATA, *p++); |
ce4c61f1 TG |
140 | } |
141 | ||
ce4c61f1 TG |
142 | /* |
143 | * Initialize chip structure | |
144 | */ | |
a808ad3b SM |
145 | static int ndfc_chip_init(struct ndfc_controller *ndfc, |
146 | struct device_node *node) | |
ce4c61f1 | 147 | { |
a808ad3b SM |
148 | struct device_node *flash_np; |
149 | struct nand_chip *chip = &ndfc->chip; | |
150 | int ret; | |
ce4c61f1 TG |
151 | |
152 | chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA; | |
153 | chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA; | |
7abd3ef9 | 154 | chip->cmd_ctrl = ndfc_hwcontrol; |
ce4c61f1 TG |
155 | chip->dev_ready = ndfc_ready; |
156 | chip->select_chip = ndfc_select_chip; | |
157 | chip->chip_delay = 50; | |
ce4c61f1 TG |
158 | chip->controller = &ndfc->ndfc_control; |
159 | chip->read_buf = ndfc_read_buf; | |
160 | chip->write_buf = ndfc_write_buf; | |
6dfc6d25 TG |
161 | chip->ecc.correct = nand_correct_data; |
162 | chip->ecc.hwctl = ndfc_enable_hwecc; | |
163 | chip->ecc.calculate = ndfc_calculate_ecc; | |
164 | chip->ecc.mode = NAND_ECC_HW; | |
165 | chip->ecc.size = 256; | |
166 | chip->ecc.bytes = 3; | |
6a918bad | 167 | chip->ecc.strength = 1; |
410fe2f0 | 168 | chip->priv = ndfc; |
ce4c61f1 | 169 | |
a808ad3b | 170 | ndfc->mtd.priv = chip; |
0033cf07 | 171 | ndfc->mtd.dev.parent = &ndfc->ofdev->dev; |
ce4c61f1 | 172 | |
a808ad3b SM |
173 | flash_np = of_get_next_child(node, NULL); |
174 | if (!flash_np) | |
ce4c61f1 | 175 | return -ENODEV; |
a61ae81a | 176 | nand_set_flash_node(chip, flash_np); |
a808ad3b SM |
177 | |
178 | ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s", | |
c36f1e33 | 179 | dev_name(&ndfc->ofdev->dev), flash_np->name); |
a808ad3b SM |
180 | if (!ndfc->mtd.name) { |
181 | ret = -ENOMEM; | |
182 | goto err; | |
ce4c61f1 TG |
183 | } |
184 | ||
a808ad3b SM |
185 | ret = nand_scan(&ndfc->mtd, 1); |
186 | if (ret) | |
187 | goto err; | |
ce4c61f1 | 188 | |
a61ae81a | 189 | ret = mtd_device_register(&ndfc->mtd, NULL, 0); |
ce4c61f1 | 190 | |
a808ad3b SM |
191 | err: |
192 | of_node_put(flash_np); | |
193 | if (ret) | |
194 | kfree(ndfc->mtd.name); | |
195 | return ret; | |
ce4c61f1 TG |
196 | } |
197 | ||
06f25510 | 198 | static int ndfc_probe(struct platform_device *ofdev) |
ce4c61f1 | 199 | { |
410fe2f0 | 200 | struct ndfc_controller *ndfc; |
766f271a | 201 | const __be32 *reg; |
a808ad3b | 202 | u32 ccr; |
5828c608 DC |
203 | u32 cs; |
204 | int err, len; | |
a808ad3b SM |
205 | |
206 | /* Read the reg property to get the chip select */ | |
61c7a080 | 207 | reg = of_get_property(ofdev->dev.of_node, "reg", &len); |
a808ad3b SM |
208 | if (reg == NULL || len != 12) { |
209 | dev_err(&ofdev->dev, "unable read reg property (%d)\n", len); | |
210 | return -ENOENT; | |
211 | } | |
410fe2f0 FR |
212 | |
213 | cs = be32_to_cpu(reg[0]); | |
214 | if (cs >= NDFC_MAX_CS) { | |
215 | dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs); | |
216 | return -EINVAL; | |
217 | } | |
218 | ||
219 | ndfc = &ndfc_ctrl[cs]; | |
220 | ndfc->chip_select = cs; | |
221 | ||
222 | spin_lock_init(&ndfc->ndfc_control.lock); | |
223 | init_waitqueue_head(&ndfc->ndfc_control.wq); | |
224 | ndfc->ofdev = ofdev; | |
225 | dev_set_drvdata(&ofdev->dev, ndfc); | |
a808ad3b | 226 | |
61c7a080 | 227 | ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0); |
ce4c61f1 | 228 | if (!ndfc->ndfcbase) { |
a808ad3b | 229 | dev_err(&ofdev->dev, "failed to get memory\n"); |
ce4c61f1 TG |
230 | return -EIO; |
231 | } | |
232 | ||
a808ad3b | 233 | ccr = NDFC_CCR_BS(ndfc->chip_select); |
ce4c61f1 | 234 | |
a808ad3b | 235 | /* It is ok if ccr does not exist - just default to 0 */ |
61c7a080 | 236 | reg = of_get_property(ofdev->dev.of_node, "ccr", NULL); |
a808ad3b | 237 | if (reg) |
766f271a | 238 | ccr |= be32_to_cpup(reg); |
ce4c61f1 | 239 | |
a808ad3b | 240 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 | 241 | |
a808ad3b | 242 | /* Set the bank settings if given */ |
61c7a080 | 243 | reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL); |
a808ad3b SM |
244 | if (reg) { |
245 | int offset = NDFC_BCFG0 + (ndfc->chip_select << 2); | |
766f271a | 246 | out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg)); |
a808ad3b SM |
247 | } |
248 | ||
61c7a080 | 249 | err = ndfc_chip_init(ndfc, ofdev->dev.of_node); |
a808ad3b SM |
250 | if (err) { |
251 | iounmap(ndfc->ndfcbase); | |
252 | return err; | |
253 | } | |
ce4c61f1 TG |
254 | |
255 | return 0; | |
256 | } | |
257 | ||
810b7e06 | 258 | static int ndfc_remove(struct platform_device *ofdev) |
ce4c61f1 | 259 | { |
a808ad3b | 260 | struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev); |
ce4c61f1 | 261 | |
a808ad3b | 262 | nand_release(&ndfc->mtd); |
96166056 | 263 | kfree(ndfc->mtd.name); |
ce4c61f1 | 264 | |
ce4c61f1 TG |
265 | return 0; |
266 | } | |
267 | ||
a808ad3b SM |
268 | static const struct of_device_id ndfc_match[] = { |
269 | { .compatible = "ibm,ndfc", }, | |
270 | {} | |
ce4c61f1 | 271 | }; |
a808ad3b | 272 | MODULE_DEVICE_TABLE(of, ndfc_match); |
ce4c61f1 | 273 | |
1c48a5c9 | 274 | static struct platform_driver ndfc_driver = { |
a808ad3b | 275 | .driver = { |
4018294b | 276 | .name = "ndfc", |
4018294b | 277 | .of_match_table = ndfc_match, |
ce4c61f1 | 278 | }, |
a808ad3b | 279 | .probe = ndfc_probe, |
5153b88c | 280 | .remove = ndfc_remove, |
ce4c61f1 TG |
281 | }; |
282 | ||
f99640de | 283 | module_platform_driver(ndfc_driver); |
ce4c61f1 TG |
284 | |
285 | MODULE_LICENSE("GPL"); | |
286 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
a808ad3b | 287 | MODULE_DESCRIPTION("OF Platform driver for NDFC"); |