Commit | Line | Data |
---|---|---|
ce4c61f1 TG |
1 | /* |
2 | * drivers/mtd/ndfc.c | |
3 | * | |
4 | * Overview: | |
a808ad3b | 5 | * Platform independent driver for NDFC (NanD Flash Controller) |
ce4c61f1 TG |
6 | * integrated into EP440 cores |
7 | * | |
a808ad3b SM |
8 | * Ported to an OF platform driver by Sean MacLennan |
9 | * | |
10 | * The NDFC supports multiple chips, but this driver only supports a | |
11 | * single chip since I do not have access to any boards with | |
12 | * multiple chips. | |
13 | * | |
ce4c61f1 TG |
14 | * Author: Thomas Gleixner |
15 | * | |
16 | * Copyright 2006 IBM | |
a808ad3b SM |
17 | * Copyright 2008 PIKA Technologies |
18 | * Sean MacLennan <smaclennan@pikatech.com> | |
ce4c61f1 TG |
19 | * |
20 | * This program is free software; you can redistribute it and/or modify it | |
21 | * under the terms of the GNU General Public License as published by the | |
22 | * Free Software Foundation; either version 2 of the License, or (at your | |
23 | * option) any later version. | |
24 | * | |
25 | */ | |
26 | #include <linux/module.h> | |
27 | #include <linux/mtd/nand.h> | |
28 | #include <linux/mtd/nand_ecc.h> | |
29 | #include <linux/mtd/partitions.h> | |
30 | #include <linux/mtd/ndfc.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
ce4c61f1 | 32 | #include <linux/mtd/mtd.h> |
a808ad3b | 33 | #include <linux/of_platform.h> |
ce4c61f1 | 34 | #include <asm/io.h> |
ce4c61f1 | 35 | |
410fe2f0 | 36 | #define NDFC_MAX_CS 4 |
ce4c61f1 TG |
37 | |
38 | struct ndfc_controller { | |
2dc11581 | 39 | struct platform_device *ofdev; |
a808ad3b SM |
40 | void __iomem *ndfcbase; |
41 | struct mtd_info mtd; | |
42 | struct nand_chip chip; | |
43 | int chip_select; | |
44 | struct nand_hw_control ndfc_control; | |
a808ad3b | 45 | struct mtd_partition *parts; |
ce4c61f1 TG |
46 | }; |
47 | ||
410fe2f0 | 48 | static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS]; |
ce4c61f1 TG |
49 | |
50 | static void ndfc_select_chip(struct mtd_info *mtd, int chip) | |
51 | { | |
52 | uint32_t ccr; | |
410fe2f0 FR |
53 | struct nand_chip *nchip = mtd->priv; |
54 | struct ndfc_controller *ndfc = nchip->priv; | |
ce4c61f1 | 55 | |
a808ad3b | 56 | ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
ce4c61f1 TG |
57 | if (chip >= 0) { |
58 | ccr &= ~NDFC_CCR_BS_MASK; | |
a808ad3b | 59 | ccr |= NDFC_CCR_BS(chip + ndfc->chip_select); |
ce4c61f1 TG |
60 | } else |
61 | ccr |= NDFC_CCR_RESET_CE; | |
a808ad3b | 62 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 TG |
63 | } |
64 | ||
7abd3ef9 | 65 | static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
ce4c61f1 | 66 | { |
410fe2f0 FR |
67 | struct nand_chip *chip = mtd->priv; |
68 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 | 69 | |
7abd3ef9 TG |
70 | if (cmd == NAND_CMD_NONE) |
71 | return; | |
72 | ||
73 | if (ctrl & NAND_CLE) | |
1794c130 | 74 | writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD); |
7abd3ef9 | 75 | else |
1794c130 | 76 | writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE); |
ce4c61f1 TG |
77 | } |
78 | ||
79 | static int ndfc_ready(struct mtd_info *mtd) | |
80 | { | |
410fe2f0 FR |
81 | struct nand_chip *chip = mtd->priv; |
82 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 | 83 | |
a808ad3b | 84 | return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY; |
ce4c61f1 TG |
85 | } |
86 | ||
87 | static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode) | |
88 | { | |
89 | uint32_t ccr; | |
410fe2f0 FR |
90 | struct nand_chip *chip = mtd->priv; |
91 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 | 92 | |
a808ad3b | 93 | ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
ce4c61f1 | 94 | ccr |= NDFC_CCR_RESET_ECC; |
a808ad3b | 95 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 TG |
96 | wmb(); |
97 | } | |
98 | ||
99 | static int ndfc_calculate_ecc(struct mtd_info *mtd, | |
100 | const u_char *dat, u_char *ecc_code) | |
101 | { | |
410fe2f0 FR |
102 | struct nand_chip *chip = mtd->priv; |
103 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
104 | uint32_t ecc; |
105 | uint8_t *p = (uint8_t *)&ecc; | |
106 | ||
107 | wmb(); | |
a808ad3b SM |
108 | ecc = in_be32(ndfc->ndfcbase + NDFC_ECC); |
109 | /* The NDFC uses Smart Media (SMC) bytes order */ | |
76c23c32 FK |
110 | ecc_code[0] = p[1]; |
111 | ecc_code[1] = p[2]; | |
ce4c61f1 TG |
112 | ecc_code[2] = p[3]; |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
117 | /* | |
118 | * Speedups for buffer read/write/verify | |
119 | * | |
120 | * NDFC allows 32bit read/write of data. So we can speed up the buffer | |
121 | * functions. No further checking, as nand_base will always read/write | |
122 | * page aligned. | |
123 | */ | |
124 | static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
125 | { | |
410fe2f0 FR |
126 | struct nand_chip *chip = mtd->priv; |
127 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
128 | uint32_t *p = (uint32_t *) buf; |
129 | ||
130 | for(;len > 0; len -= 4) | |
a808ad3b | 131 | *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA); |
ce4c61f1 TG |
132 | } |
133 | ||
134 | static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
135 | { | |
410fe2f0 FR |
136 | struct nand_chip *chip = mtd->priv; |
137 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
138 | uint32_t *p = (uint32_t *) buf; |
139 | ||
140 | for(;len > 0; len -= 4) | |
a808ad3b | 141 | out_be32(ndfc->ndfcbase + NDFC_DATA, *p++); |
ce4c61f1 TG |
142 | } |
143 | ||
144 | static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
145 | { | |
410fe2f0 FR |
146 | struct nand_chip *chip = mtd->priv; |
147 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
148 | uint32_t *p = (uint32_t *) buf; |
149 | ||
150 | for(;len > 0; len -= 4) | |
a808ad3b | 151 | if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA)) |
ce4c61f1 TG |
152 | return -EFAULT; |
153 | return 0; | |
154 | } | |
155 | ||
156 | /* | |
157 | * Initialize chip structure | |
158 | */ | |
a808ad3b SM |
159 | static int ndfc_chip_init(struct ndfc_controller *ndfc, |
160 | struct device_node *node) | |
ce4c61f1 | 161 | { |
a808ad3b SM |
162 | struct device_node *flash_np; |
163 | struct nand_chip *chip = &ndfc->chip; | |
164 | int ret; | |
ce4c61f1 TG |
165 | |
166 | chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA; | |
167 | chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA; | |
7abd3ef9 | 168 | chip->cmd_ctrl = ndfc_hwcontrol; |
ce4c61f1 TG |
169 | chip->dev_ready = ndfc_ready; |
170 | chip->select_chip = ndfc_select_chip; | |
171 | chip->chip_delay = 50; | |
ce4c61f1 TG |
172 | chip->controller = &ndfc->ndfc_control; |
173 | chip->read_buf = ndfc_read_buf; | |
174 | chip->write_buf = ndfc_write_buf; | |
175 | chip->verify_buf = ndfc_verify_buf; | |
6dfc6d25 TG |
176 | chip->ecc.correct = nand_correct_data; |
177 | chip->ecc.hwctl = ndfc_enable_hwecc; | |
178 | chip->ecc.calculate = ndfc_calculate_ecc; | |
179 | chip->ecc.mode = NAND_ECC_HW; | |
180 | chip->ecc.size = 256; | |
181 | chip->ecc.bytes = 3; | |
410fe2f0 | 182 | chip->priv = ndfc; |
ce4c61f1 | 183 | |
a808ad3b SM |
184 | ndfc->mtd.priv = chip; |
185 | ndfc->mtd.owner = THIS_MODULE; | |
ce4c61f1 | 186 | |
a808ad3b SM |
187 | flash_np = of_get_next_child(node, NULL); |
188 | if (!flash_np) | |
ce4c61f1 | 189 | return -ENODEV; |
a808ad3b SM |
190 | |
191 | ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s", | |
c36f1e33 | 192 | dev_name(&ndfc->ofdev->dev), flash_np->name); |
a808ad3b SM |
193 | if (!ndfc->mtd.name) { |
194 | ret = -ENOMEM; | |
195 | goto err; | |
ce4c61f1 TG |
196 | } |
197 | ||
a808ad3b SM |
198 | ret = nand_scan(&ndfc->mtd, 1); |
199 | if (ret) | |
200 | goto err; | |
ce4c61f1 | 201 | |
2aedf3e9 | 202 | ret = parse_mtd_partitions(&ndfc->mtd, NULL, &ndfc->parts, 0); |
a808ad3b SM |
203 | if (ret < 0) |
204 | goto err; | |
205 | ||
a808ad3b SM |
206 | if (ret == 0) { |
207 | ret = of_mtd_parse_partitions(&ndfc->ofdev->dev, flash_np, | |
208 | &ndfc->parts); | |
209 | if (ret < 0) | |
210 | goto err; | |
211 | } | |
ce4c61f1 | 212 | |
1f3a7c62 | 213 | ret = mtd_device_register(&ndfc->mtd, ndfc->parts, ret); |
ce4c61f1 | 214 | |
a808ad3b SM |
215 | err: |
216 | of_node_put(flash_np); | |
217 | if (ret) | |
218 | kfree(ndfc->mtd.name); | |
219 | return ret; | |
ce4c61f1 TG |
220 | } |
221 | ||
1c48a5c9 | 222 | static int __devinit ndfc_probe(struct platform_device *ofdev) |
ce4c61f1 | 223 | { |
410fe2f0 | 224 | struct ndfc_controller *ndfc; |
766f271a | 225 | const __be32 *reg; |
a808ad3b | 226 | u32 ccr; |
410fe2f0 | 227 | int err, len, cs; |
a808ad3b SM |
228 | |
229 | /* Read the reg property to get the chip select */ | |
61c7a080 | 230 | reg = of_get_property(ofdev->dev.of_node, "reg", &len); |
a808ad3b SM |
231 | if (reg == NULL || len != 12) { |
232 | dev_err(&ofdev->dev, "unable read reg property (%d)\n", len); | |
233 | return -ENOENT; | |
234 | } | |
410fe2f0 FR |
235 | |
236 | cs = be32_to_cpu(reg[0]); | |
237 | if (cs >= NDFC_MAX_CS) { | |
238 | dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs); | |
239 | return -EINVAL; | |
240 | } | |
241 | ||
242 | ndfc = &ndfc_ctrl[cs]; | |
243 | ndfc->chip_select = cs; | |
244 | ||
245 | spin_lock_init(&ndfc->ndfc_control.lock); | |
246 | init_waitqueue_head(&ndfc->ndfc_control.wq); | |
247 | ndfc->ofdev = ofdev; | |
248 | dev_set_drvdata(&ofdev->dev, ndfc); | |
a808ad3b | 249 | |
61c7a080 | 250 | ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0); |
ce4c61f1 | 251 | if (!ndfc->ndfcbase) { |
a808ad3b | 252 | dev_err(&ofdev->dev, "failed to get memory\n"); |
ce4c61f1 TG |
253 | return -EIO; |
254 | } | |
255 | ||
a808ad3b | 256 | ccr = NDFC_CCR_BS(ndfc->chip_select); |
ce4c61f1 | 257 | |
a808ad3b | 258 | /* It is ok if ccr does not exist - just default to 0 */ |
61c7a080 | 259 | reg = of_get_property(ofdev->dev.of_node, "ccr", NULL); |
a808ad3b | 260 | if (reg) |
766f271a | 261 | ccr |= be32_to_cpup(reg); |
ce4c61f1 | 262 | |
a808ad3b | 263 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 | 264 | |
a808ad3b | 265 | /* Set the bank settings if given */ |
61c7a080 | 266 | reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL); |
a808ad3b SM |
267 | if (reg) { |
268 | int offset = NDFC_BCFG0 + (ndfc->chip_select << 2); | |
766f271a | 269 | out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg)); |
a808ad3b SM |
270 | } |
271 | ||
61c7a080 | 272 | err = ndfc_chip_init(ndfc, ofdev->dev.of_node); |
a808ad3b SM |
273 | if (err) { |
274 | iounmap(ndfc->ndfcbase); | |
275 | return err; | |
276 | } | |
ce4c61f1 TG |
277 | |
278 | return 0; | |
279 | } | |
280 | ||
2dc11581 | 281 | static int __devexit ndfc_remove(struct platform_device *ofdev) |
ce4c61f1 | 282 | { |
a808ad3b | 283 | struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev); |
ce4c61f1 | 284 | |
a808ad3b | 285 | nand_release(&ndfc->mtd); |
ce4c61f1 | 286 | |
ce4c61f1 TG |
287 | return 0; |
288 | } | |
289 | ||
a808ad3b SM |
290 | static const struct of_device_id ndfc_match[] = { |
291 | { .compatible = "ibm,ndfc", }, | |
292 | {} | |
ce4c61f1 | 293 | }; |
a808ad3b | 294 | MODULE_DEVICE_TABLE(of, ndfc_match); |
ce4c61f1 | 295 | |
1c48a5c9 | 296 | static struct platform_driver ndfc_driver = { |
a808ad3b | 297 | .driver = { |
4018294b GL |
298 | .name = "ndfc", |
299 | .owner = THIS_MODULE, | |
300 | .of_match_table = ndfc_match, | |
ce4c61f1 | 301 | }, |
a808ad3b SM |
302 | .probe = ndfc_probe, |
303 | .remove = __devexit_p(ndfc_remove), | |
ce4c61f1 TG |
304 | }; |
305 | ||
306 | static int __init ndfc_nand_init(void) | |
307 | { | |
1c48a5c9 | 308 | return platform_driver_register(&ndfc_driver); |
ce4c61f1 TG |
309 | } |
310 | ||
311 | static void __exit ndfc_nand_exit(void) | |
312 | { | |
1c48a5c9 | 313 | platform_driver_unregister(&ndfc_driver); |
ce4c61f1 TG |
314 | } |
315 | ||
316 | module_init(ndfc_nand_init); | |
317 | module_exit(ndfc_nand_exit); | |
318 | ||
319 | MODULE_LICENSE("GPL"); | |
320 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
a808ad3b | 321 | MODULE_DESCRIPTION("OF Platform driver for NDFC"); |