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67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
763e7359 | 12 | #include <linux/dmaengine.h> |
67ce04bf VS |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/delay.h> | |
a0e5cc58 | 15 | #include <linux/module.h> |
4e070376 | 16 | #include <linux/interrupt.h> |
c276aca4 | 17 | #include <linux/jiffies.h> |
18 | #include <linux/sched.h> | |
67ce04bf VS |
19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
763e7359 | 22 | #include <linux/omap-dma.h> |
67ce04bf | 23 | #include <linux/io.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
67ce04bf | 25 | |
0e618ef0 ID |
26 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
27 | #include <linux/bch.h> | |
28 | #endif | |
29 | ||
ce491cf8 TL |
30 | #include <plat/dma.h> |
31 | #include <plat/gpmc.h> | |
32 | #include <plat/nand.h> | |
67ce04bf | 33 | |
67ce04bf | 34 | #define DRIVER_NAME "omap2-nand" |
4e070376 | 35 | #define OMAP_NAND_TIMEOUT_MS 5000 |
67ce04bf | 36 | |
67ce04bf VS |
37 | #define NAND_Ecc_P1e (1 << 0) |
38 | #define NAND_Ecc_P2e (1 << 1) | |
39 | #define NAND_Ecc_P4e (1 << 2) | |
40 | #define NAND_Ecc_P8e (1 << 3) | |
41 | #define NAND_Ecc_P16e (1 << 4) | |
42 | #define NAND_Ecc_P32e (1 << 5) | |
43 | #define NAND_Ecc_P64e (1 << 6) | |
44 | #define NAND_Ecc_P128e (1 << 7) | |
45 | #define NAND_Ecc_P256e (1 << 8) | |
46 | #define NAND_Ecc_P512e (1 << 9) | |
47 | #define NAND_Ecc_P1024e (1 << 10) | |
48 | #define NAND_Ecc_P2048e (1 << 11) | |
49 | ||
50 | #define NAND_Ecc_P1o (1 << 16) | |
51 | #define NAND_Ecc_P2o (1 << 17) | |
52 | #define NAND_Ecc_P4o (1 << 18) | |
53 | #define NAND_Ecc_P8o (1 << 19) | |
54 | #define NAND_Ecc_P16o (1 << 20) | |
55 | #define NAND_Ecc_P32o (1 << 21) | |
56 | #define NAND_Ecc_P64o (1 << 22) | |
57 | #define NAND_Ecc_P128o (1 << 23) | |
58 | #define NAND_Ecc_P256o (1 << 24) | |
59 | #define NAND_Ecc_P512o (1 << 25) | |
60 | #define NAND_Ecc_P1024o (1 << 26) | |
61 | #define NAND_Ecc_P2048o (1 << 27) | |
62 | ||
63 | #define TF(value) (value ? 1 : 0) | |
64 | ||
65 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
66 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
67 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
68 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
69 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
70 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
71 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
72 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
73 | ||
74 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
75 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
76 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
77 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
78 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
79 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
80 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
81 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
82 | ||
83 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
84 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
85 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
86 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
87 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
88 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
89 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
90 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
91 | ||
92 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
93 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
94 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
95 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
96 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
97 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
98 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
99 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
100 | ||
101 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
102 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
103 | ||
65b97cf6 AM |
104 | #define PREFETCH_CONFIG1_CS_SHIFT 24 |
105 | #define ECC_CONFIG_CS_SHIFT 1 | |
106 | #define CS_MASK 0x7 | |
107 | #define ENABLE_PREFETCH (0x1 << 7) | |
108 | #define DMA_MPU_MODE_SHIFT 2 | |
109 | #define ECCSIZE1_SHIFT 22 | |
110 | #define ECC1RESULTSIZE 0x1 | |
111 | #define ECCCLEAR 0x100 | |
112 | #define ECC1 0x1 | |
113 | ||
f040d332 SG |
114 | /* oob info generated runtime depending on ecc algorithm and layout selected */ |
115 | static struct nand_ecclayout omap_oobinfo; | |
116 | /* Define some generic bad / good block scan pattern which are used | |
117 | * while scanning a device for factory marked good / bad blocks | |
118 | */ | |
119 | static uint8_t scan_ff_pattern[] = { 0xff }; | |
120 | static struct nand_bbt_descr bb_descrip_flashbased = { | |
121 | .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, | |
122 | .offs = 0, | |
123 | .len = 1, | |
124 | .pattern = scan_ff_pattern, | |
125 | }; | |
dfe32893 | 126 | |
59e9c5ae | 127 | |
67ce04bf VS |
128 | struct omap_nand_info { |
129 | struct nand_hw_control controller; | |
130 | struct omap_nand_platform_data *pdata; | |
131 | struct mtd_info mtd; | |
67ce04bf VS |
132 | struct nand_chip nand; |
133 | struct platform_device *pdev; | |
134 | ||
135 | int gpmc_cs; | |
136 | unsigned long phys_base; | |
9c4c2f8b | 137 | unsigned long mem_size; |
dfe32893 | 138 | struct completion comp; |
763e7359 | 139 | struct dma_chan *dma; |
4e070376 SG |
140 | int gpmc_irq; |
141 | enum { | |
142 | OMAP_NAND_IO_READ = 0, /* read */ | |
143 | OMAP_NAND_IO_WRITE, /* write */ | |
144 | } iomode; | |
145 | u_char *buf; | |
146 | int buf_len; | |
65b97cf6 | 147 | struct gpmc_nand_regs reg; |
0e618ef0 ID |
148 | |
149 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | |
150 | struct bch_control *bch; | |
151 | struct nand_ecclayout ecclayout; | |
152 | #endif | |
67ce04bf VS |
153 | }; |
154 | ||
65b97cf6 AM |
155 | /** |
156 | * omap_prefetch_enable - configures and starts prefetch transfer | |
157 | * @cs: cs (chip select) number | |
158 | * @fifo_th: fifo threshold to be used for read/ write | |
159 | * @dma_mode: dma mode enable (1) or disable (0) | |
160 | * @u32_count: number of bytes to be transferred | |
161 | * @is_write: prefetch read(0) or write post(1) mode | |
162 | */ | |
163 | static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, | |
164 | unsigned int u32_count, int is_write, struct omap_nand_info *info) | |
165 | { | |
166 | u32 val; | |
167 | ||
168 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) | |
169 | return -1; | |
170 | ||
171 | if (readl(info->reg.gpmc_prefetch_control)) | |
172 | return -EBUSY; | |
173 | ||
174 | /* Set the amount of bytes to be prefetched */ | |
175 | writel(u32_count, info->reg.gpmc_prefetch_config2); | |
176 | ||
177 | /* Set dma/mpu mode, the prefetch read / post write and | |
178 | * enable the engine. Set which cs is has requested for. | |
179 | */ | |
180 | val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | | |
181 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | | |
182 | (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write)); | |
183 | writel(val, info->reg.gpmc_prefetch_config1); | |
184 | ||
185 | /* Start the prefetch engine */ | |
186 | writel(0x1, info->reg.gpmc_prefetch_control); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | /** | |
192 | * omap_prefetch_reset - disables and stops the prefetch engine | |
193 | */ | |
194 | static int omap_prefetch_reset(int cs, struct omap_nand_info *info) | |
195 | { | |
196 | u32 config1; | |
197 | ||
198 | /* check if the same module/cs is trying to reset */ | |
199 | config1 = readl(info->reg.gpmc_prefetch_config1); | |
200 | if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) | |
201 | return -EINVAL; | |
202 | ||
203 | /* Stop the PFPW engine */ | |
204 | writel(0x0, info->reg.gpmc_prefetch_control); | |
205 | ||
206 | /* Reset/disable the PFPW engine */ | |
207 | writel(0x0, info->reg.gpmc_prefetch_config1); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
67ce04bf VS |
212 | /** |
213 | * omap_hwcontrol - hardware specific access to control-lines | |
214 | * @mtd: MTD device structure | |
215 | * @cmd: command to device | |
216 | * @ctrl: | |
217 | * NAND_NCE: bit 0 -> don't care | |
218 | * NAND_CLE: bit 1 -> Command Latch | |
219 | * NAND_ALE: bit 2 -> Address Latch | |
220 | * | |
221 | * NOTE: boards may use different bits for these!! | |
222 | */ | |
223 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
224 | { | |
225 | struct omap_nand_info *info = container_of(mtd, | |
226 | struct omap_nand_info, mtd); | |
67ce04bf | 227 | |
2c01946c SG |
228 | if (cmd != NAND_CMD_NONE) { |
229 | if (ctrl & NAND_CLE) | |
65b97cf6 | 230 | writeb(cmd, info->reg.gpmc_nand_command); |
2c01946c SG |
231 | |
232 | else if (ctrl & NAND_ALE) | |
65b97cf6 | 233 | writeb(cmd, info->reg.gpmc_nand_address); |
2c01946c SG |
234 | |
235 | else /* NAND_NCE */ | |
65b97cf6 | 236 | writeb(cmd, info->reg.gpmc_nand_data); |
2c01946c | 237 | } |
67ce04bf VS |
238 | } |
239 | ||
59e9c5ae | 240 | /** |
241 | * omap_read_buf8 - read data from NAND controller into buffer | |
242 | * @mtd: MTD device structure | |
243 | * @buf: buffer to store date | |
244 | * @len: number of bytes to read | |
245 | */ | |
246 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
247 | { | |
248 | struct nand_chip *nand = mtd->priv; | |
249 | ||
250 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
251 | } | |
252 | ||
253 | /** | |
254 | * omap_write_buf8 - write buffer to NAND controller | |
255 | * @mtd: MTD device structure | |
256 | * @buf: data buffer | |
257 | * @len: number of bytes to write | |
258 | */ | |
259 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
260 | { | |
261 | struct omap_nand_info *info = container_of(mtd, | |
262 | struct omap_nand_info, mtd); | |
263 | u_char *p = (u_char *)buf; | |
2c01946c | 264 | u32 status = 0; |
59e9c5ae | 265 | |
266 | while (len--) { | |
267 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
2c01946c SG |
268 | /* wait until buffer is available for write */ |
269 | do { | |
65b97cf6 AM |
270 | status = readl(info->reg.gpmc_status) & |
271 | GPMC_STATUS_BUFF_EMPTY; | |
2c01946c | 272 | } while (!status); |
59e9c5ae | 273 | } |
274 | } | |
275 | ||
67ce04bf VS |
276 | /** |
277 | * omap_read_buf16 - read data from NAND controller into buffer | |
278 | * @mtd: MTD device structure | |
279 | * @buf: buffer to store date | |
280 | * @len: number of bytes to read | |
281 | */ | |
282 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
283 | { | |
284 | struct nand_chip *nand = mtd->priv; | |
285 | ||
59e9c5ae | 286 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
287 | } |
288 | ||
289 | /** | |
290 | * omap_write_buf16 - write buffer to NAND controller | |
291 | * @mtd: MTD device structure | |
292 | * @buf: data buffer | |
293 | * @len: number of bytes to write | |
294 | */ | |
295 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
296 | { | |
297 | struct omap_nand_info *info = container_of(mtd, | |
298 | struct omap_nand_info, mtd); | |
299 | u16 *p = (u16 *) buf; | |
2c01946c | 300 | u32 status = 0; |
67ce04bf VS |
301 | /* FIXME try bursts of writesw() or DMA ... */ |
302 | len >>= 1; | |
303 | ||
304 | while (len--) { | |
59e9c5ae | 305 | iowrite16(*p++, info->nand.IO_ADDR_W); |
2c01946c SG |
306 | /* wait until buffer is available for write */ |
307 | do { | |
65b97cf6 AM |
308 | status = readl(info->reg.gpmc_status) & |
309 | GPMC_STATUS_BUFF_EMPTY; | |
2c01946c | 310 | } while (!status); |
67ce04bf VS |
311 | } |
312 | } | |
59e9c5ae | 313 | |
314 | /** | |
315 | * omap_read_buf_pref - read data from NAND controller into buffer | |
316 | * @mtd: MTD device structure | |
317 | * @buf: buffer to store date | |
318 | * @len: number of bytes to read | |
319 | */ | |
320 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
321 | { | |
322 | struct omap_nand_info *info = container_of(mtd, | |
323 | struct omap_nand_info, mtd); | |
2c01946c | 324 | uint32_t r_count = 0; |
59e9c5ae | 325 | int ret = 0; |
326 | u32 *p = (u32 *)buf; | |
327 | ||
328 | /* take care of subpage reads */ | |
c3341d0c VS |
329 | if (len % 4) { |
330 | if (info->nand.options & NAND_BUSWIDTH_16) | |
331 | omap_read_buf16(mtd, buf, len % 4); | |
332 | else | |
333 | omap_read_buf8(mtd, buf, len % 4); | |
334 | p = (u32 *) (buf + len % 4); | |
335 | len -= len % 4; | |
59e9c5ae | 336 | } |
59e9c5ae | 337 | |
338 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
339 | ret = omap_prefetch_enable(info->gpmc_cs, |
340 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); | |
59e9c5ae | 341 | if (ret) { |
342 | /* PFPW engine is busy, use cpu copy method */ | |
343 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 344 | omap_read_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 345 | else |
c5d8c0ca | 346 | omap_read_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 347 | } else { |
348 | do { | |
65b97cf6 AM |
349 | r_count = readl(info->reg.gpmc_prefetch_status); |
350 | r_count = GPMC_PREFETCH_STATUS_FIFO_CNT(r_count); | |
2c01946c SG |
351 | r_count = r_count >> 2; |
352 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); | |
59e9c5ae | 353 | p += r_count; |
354 | len -= r_count << 2; | |
355 | } while (len); | |
59e9c5ae | 356 | /* disable and stop the PFPW engine */ |
65b97cf6 | 357 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 358 | } |
359 | } | |
360 | ||
361 | /** | |
362 | * omap_write_buf_pref - write buffer to NAND controller | |
363 | * @mtd: MTD device structure | |
364 | * @buf: data buffer | |
365 | * @len: number of bytes to write | |
366 | */ | |
367 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
368 | const u_char *buf, int len) | |
369 | { | |
370 | struct omap_nand_info *info = container_of(mtd, | |
371 | struct omap_nand_info, mtd); | |
4e070376 | 372 | uint32_t w_count = 0; |
59e9c5ae | 373 | int i = 0, ret = 0; |
c5d8c0ca | 374 | u16 *p = (u16 *)buf; |
4e070376 | 375 | unsigned long tim, limit; |
65b97cf6 | 376 | u32 val; |
59e9c5ae | 377 | |
378 | /* take care of subpage writes */ | |
379 | if (len % 2 != 0) { | |
2c01946c | 380 | writeb(*buf, info->nand.IO_ADDR_W); |
59e9c5ae | 381 | p = (u16 *)(buf + 1); |
382 | len--; | |
383 | } | |
384 | ||
385 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
386 | ret = omap_prefetch_enable(info->gpmc_cs, |
387 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); | |
59e9c5ae | 388 | if (ret) { |
389 | /* PFPW engine is busy, use cpu copy method */ | |
390 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 391 | omap_write_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 392 | else |
c5d8c0ca | 393 | omap_write_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 394 | } else { |
2c01946c | 395 | while (len) { |
65b97cf6 AM |
396 | w_count = readl(info->reg.gpmc_prefetch_status); |
397 | w_count = GPMC_PREFETCH_STATUS_FIFO_CNT(w_count); | |
2c01946c | 398 | w_count = w_count >> 1; |
59e9c5ae | 399 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
2c01946c | 400 | iowrite16(*p++, info->nand.IO_ADDR_W); |
59e9c5ae | 401 | } |
2c01946c | 402 | /* wait for data to flushed-out before reset the prefetch */ |
4e070376 SG |
403 | tim = 0; |
404 | limit = (loops_per_jiffy * | |
405 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 | 406 | do { |
4e070376 | 407 | cpu_relax(); |
65b97cf6 AM |
408 | val = readl(info->reg.gpmc_prefetch_status); |
409 | val = GPMC_PREFETCH_STATUS_COUNT(val); | |
410 | } while (val && (tim++ < limit)); | |
4e070376 | 411 | |
59e9c5ae | 412 | /* disable and stop the PFPW engine */ |
65b97cf6 | 413 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 414 | } |
415 | } | |
416 | ||
dfe32893 | 417 | /* |
2df41d05 | 418 | * omap_nand_dma_callback: callback on the completion of dma transfer |
dfe32893 | 419 | * @data: pointer to completion data structure |
420 | */ | |
763e7359 RK |
421 | static void omap_nand_dma_callback(void *data) |
422 | { | |
423 | complete((struct completion *) data); | |
424 | } | |
dfe32893 | 425 | |
426 | /* | |
427 | * omap_nand_dma_transfer: configer and start dma transfer | |
428 | * @mtd: MTD device structure | |
429 | * @addr: virtual address in RAM of source/destination | |
430 | * @len: number of data bytes to be transferred | |
431 | * @is_write: flag for read/write operation | |
432 | */ | |
433 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
434 | unsigned int len, int is_write) | |
435 | { | |
436 | struct omap_nand_info *info = container_of(mtd, | |
437 | struct omap_nand_info, mtd); | |
2df41d05 | 438 | struct dma_async_tx_descriptor *tx; |
dfe32893 | 439 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
440 | DMA_FROM_DEVICE; | |
2df41d05 | 441 | struct scatterlist sg; |
4e070376 | 442 | unsigned long tim, limit; |
2df41d05 RK |
443 | unsigned n; |
444 | int ret; | |
65b97cf6 | 445 | u32 val; |
dfe32893 | 446 | |
447 | if (addr >= high_memory) { | |
448 | struct page *p1; | |
449 | ||
450 | if (((size_t)addr & PAGE_MASK) != | |
451 | ((size_t)(addr + len - 1) & PAGE_MASK)) | |
452 | goto out_copy; | |
453 | p1 = vmalloc_to_page(addr); | |
454 | if (!p1) | |
455 | goto out_copy; | |
456 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); | |
457 | } | |
458 | ||
2df41d05 RK |
459 | sg_init_one(&sg, addr, len); |
460 | n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); | |
461 | if (n == 0) { | |
dfe32893 | 462 | dev_err(&info->pdev->dev, |
463 | "Couldn't DMA map a %d byte buffer\n", len); | |
464 | goto out_copy; | |
465 | } | |
466 | ||
2df41d05 RK |
467 | tx = dmaengine_prep_slave_sg(info->dma, &sg, n, |
468 | is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
469 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
470 | if (!tx) | |
471 | goto out_copy_unmap; | |
472 | ||
473 | tx->callback = omap_nand_dma_callback; | |
474 | tx->callback_param = &info->comp; | |
475 | dmaengine_submit(tx); | |
476 | ||
65b97cf6 AM |
477 | /* configure and start prefetch transfer */ |
478 | ret = omap_prefetch_enable(info->gpmc_cs, | |
479 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); | |
dfe32893 | 480 | if (ret) |
4e070376 | 481 | /* PFPW engine is busy, use cpu copy method */ |
d7efe228 | 482 | goto out_copy_unmap; |
dfe32893 | 483 | |
484 | init_completion(&info->comp); | |
2df41d05 | 485 | dma_async_issue_pending(info->dma); |
dfe32893 | 486 | |
487 | /* setup and start DMA using dma_addr */ | |
488 | wait_for_completion(&info->comp); | |
4e070376 SG |
489 | tim = 0; |
490 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
491 | |
492 | do { | |
4e070376 | 493 | cpu_relax(); |
65b97cf6 AM |
494 | val = readl(info->reg.gpmc_prefetch_status); |
495 | val = GPMC_PREFETCH_STATUS_COUNT(val); | |
496 | } while (val && (tim++ < limit)); | |
dfe32893 | 497 | |
dfe32893 | 498 | /* disable and stop the PFPW engine */ |
65b97cf6 | 499 | omap_prefetch_reset(info->gpmc_cs, info); |
dfe32893 | 500 | |
2df41d05 | 501 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 502 | return 0; |
503 | ||
d7efe228 | 504 | out_copy_unmap: |
2df41d05 | 505 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 506 | out_copy: |
507 | if (info->nand.options & NAND_BUSWIDTH_16) | |
508 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
509 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
510 | else | |
511 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
512 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
513 | return 0; | |
514 | } | |
dfe32893 | 515 | |
516 | /** | |
517 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
518 | * @mtd: MTD device structure | |
519 | * @buf: buffer to store date | |
520 | * @len: number of bytes to read | |
521 | */ | |
522 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
523 | { | |
524 | if (len <= mtd->oobsize) | |
525 | omap_read_buf_pref(mtd, buf, len); | |
526 | else | |
527 | /* start transfer in DMA mode */ | |
528 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
529 | } | |
530 | ||
531 | /** | |
532 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
533 | * @mtd: MTD device structure | |
534 | * @buf: data buffer | |
535 | * @len: number of bytes to write | |
536 | */ | |
537 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
538 | const u_char *buf, int len) | |
539 | { | |
540 | if (len <= mtd->oobsize) | |
541 | omap_write_buf_pref(mtd, buf, len); | |
542 | else | |
543 | /* start transfer in DMA mode */ | |
bdaefc41 | 544 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
dfe32893 | 545 | } |
546 | ||
4e070376 SG |
547 | /* |
548 | * omap_nand_irq - GMPC irq handler | |
549 | * @this_irq: gpmc irq number | |
550 | * @dev: omap_nand_info structure pointer is passed here | |
551 | */ | |
552 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) | |
553 | { | |
554 | struct omap_nand_info *info = (struct omap_nand_info *) dev; | |
555 | u32 bytes; | |
556 | u32 irq_stat; | |
557 | ||
558 | irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); | |
65b97cf6 AM |
559 | bytes = readl(info->reg.gpmc_prefetch_status); |
560 | bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(bytes); | |
4e070376 SG |
561 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ |
562 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ | |
563 | if (irq_stat & 0x2) | |
564 | goto done; | |
565 | ||
566 | if (info->buf_len && (info->buf_len < bytes)) | |
567 | bytes = info->buf_len; | |
568 | else if (!info->buf_len) | |
569 | bytes = 0; | |
570 | iowrite32_rep(info->nand.IO_ADDR_W, | |
571 | (u32 *)info->buf, bytes >> 2); | |
572 | info->buf = info->buf + bytes; | |
573 | info->buf_len -= bytes; | |
574 | ||
575 | } else { | |
576 | ioread32_rep(info->nand.IO_ADDR_R, | |
577 | (u32 *)info->buf, bytes >> 2); | |
578 | info->buf = info->buf + bytes; | |
579 | ||
580 | if (irq_stat & 0x2) | |
581 | goto done; | |
582 | } | |
583 | gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); | |
584 | ||
585 | return IRQ_HANDLED; | |
586 | ||
587 | done: | |
588 | complete(&info->comp); | |
589 | /* disable irq */ | |
590 | gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0); | |
591 | ||
592 | /* clear status */ | |
593 | gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); | |
594 | ||
595 | return IRQ_HANDLED; | |
596 | } | |
597 | ||
598 | /* | |
599 | * omap_read_buf_irq_pref - read data from NAND controller into buffer | |
600 | * @mtd: MTD device structure | |
601 | * @buf: buffer to store date | |
602 | * @len: number of bytes to read | |
603 | */ | |
604 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) | |
605 | { | |
606 | struct omap_nand_info *info = container_of(mtd, | |
607 | struct omap_nand_info, mtd); | |
608 | int ret = 0; | |
609 | ||
610 | if (len <= mtd->oobsize) { | |
611 | omap_read_buf_pref(mtd, buf, len); | |
612 | return; | |
613 | } | |
614 | ||
615 | info->iomode = OMAP_NAND_IO_READ; | |
616 | info->buf = buf; | |
617 | init_completion(&info->comp); | |
618 | ||
619 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
620 | ret = omap_prefetch_enable(info->gpmc_cs, |
621 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); | |
4e070376 SG |
622 | if (ret) |
623 | /* PFPW engine is busy, use cpu copy method */ | |
624 | goto out_copy; | |
625 | ||
626 | info->buf_len = len; | |
627 | /* enable irq */ | |
628 | gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, | |
629 | (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); | |
630 | ||
631 | /* waiting for read to complete */ | |
632 | wait_for_completion(&info->comp); | |
633 | ||
634 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 635 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
636 | return; |
637 | ||
638 | out_copy: | |
639 | if (info->nand.options & NAND_BUSWIDTH_16) | |
640 | omap_read_buf16(mtd, buf, len); | |
641 | else | |
642 | omap_read_buf8(mtd, buf, len); | |
643 | } | |
644 | ||
645 | /* | |
646 | * omap_write_buf_irq_pref - write buffer to NAND controller | |
647 | * @mtd: MTD device structure | |
648 | * @buf: data buffer | |
649 | * @len: number of bytes to write | |
650 | */ | |
651 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, | |
652 | const u_char *buf, int len) | |
653 | { | |
654 | struct omap_nand_info *info = container_of(mtd, | |
655 | struct omap_nand_info, mtd); | |
656 | int ret = 0; | |
657 | unsigned long tim, limit; | |
65b97cf6 | 658 | u32 val; |
4e070376 SG |
659 | |
660 | if (len <= mtd->oobsize) { | |
661 | omap_write_buf_pref(mtd, buf, len); | |
662 | return; | |
663 | } | |
664 | ||
665 | info->iomode = OMAP_NAND_IO_WRITE; | |
666 | info->buf = (u_char *) buf; | |
667 | init_completion(&info->comp); | |
668 | ||
317379a9 | 669 | /* configure and start prefetch transfer : size=24 */ |
65b97cf6 AM |
670 | ret = omap_prefetch_enable(info->gpmc_cs, |
671 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); | |
4e070376 SG |
672 | if (ret) |
673 | /* PFPW engine is busy, use cpu copy method */ | |
674 | goto out_copy; | |
675 | ||
676 | info->buf_len = len; | |
677 | /* enable irq */ | |
678 | gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, | |
679 | (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); | |
680 | ||
681 | /* waiting for write to complete */ | |
682 | wait_for_completion(&info->comp); | |
683 | /* wait for data to flushed-out before reset the prefetch */ | |
684 | tim = 0; | |
685 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
686 | do { |
687 | val = readl(info->reg.gpmc_prefetch_status); | |
688 | val = GPMC_PREFETCH_STATUS_COUNT(val); | |
4e070376 | 689 | cpu_relax(); |
65b97cf6 | 690 | } while (val && (tim++ < limit)); |
4e070376 SG |
691 | |
692 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 693 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
694 | return; |
695 | ||
696 | out_copy: | |
697 | if (info->nand.options & NAND_BUSWIDTH_16) | |
698 | omap_write_buf16(mtd, buf, len); | |
699 | else | |
700 | omap_write_buf8(mtd, buf, len); | |
701 | } | |
702 | ||
67ce04bf VS |
703 | /** |
704 | * omap_verify_buf - Verify chip data against buffer | |
705 | * @mtd: MTD device structure | |
706 | * @buf: buffer containing the data to compare | |
707 | * @len: number of bytes to compare | |
708 | */ | |
709 | static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) | |
710 | { | |
711 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
712 | mtd); | |
713 | u16 *p = (u16 *) buf; | |
714 | ||
715 | len >>= 1; | |
716 | while (len--) { | |
717 | if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R))) | |
718 | return -EFAULT; | |
719 | } | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
67ce04bf VS |
724 | /** |
725 | * gen_true_ecc - This function will generate true ECC value | |
726 | * @ecc_buf: buffer to store ecc code | |
727 | * | |
728 | * This generated true ECC value can be used when correcting | |
729 | * data read from NAND flash memory core | |
730 | */ | |
731 | static void gen_true_ecc(u8 *ecc_buf) | |
732 | { | |
733 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
734 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
735 | ||
736 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
737 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
738 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
739 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
740 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
741 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
742 | } | |
743 | ||
744 | /** | |
745 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
746 | * @ecc_data1: ecc code from nand spare area | |
747 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
748 | * @page_data: page data | |
749 | * | |
750 | * This function compares two ECC's and indicates if there is an error. | |
751 | * If the error can be corrected it will be corrected to the buffer. | |
74f1b724 JO |
752 | * If there is no error, %0 is returned. If there is an error but it |
753 | * was corrected, %1 is returned. Otherwise, %-1 is returned. | |
67ce04bf VS |
754 | */ |
755 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
756 | u8 *ecc_data2, /* read from register */ | |
757 | u8 *page_data) | |
758 | { | |
759 | uint i; | |
760 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
761 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
762 | u8 ecc_bit[24]; | |
763 | u8 ecc_sum = 0; | |
764 | u8 find_bit = 0; | |
765 | uint find_byte = 0; | |
766 | int isEccFF; | |
767 | ||
768 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
769 | ||
770 | gen_true_ecc(ecc_data1); | |
771 | gen_true_ecc(ecc_data2); | |
772 | ||
773 | for (i = 0; i <= 2; i++) { | |
774 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
775 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
776 | } | |
777 | ||
778 | for (i = 0; i < 8; i++) { | |
779 | tmp0_bit[i] = *ecc_data1 % 2; | |
780 | *ecc_data1 = *ecc_data1 / 2; | |
781 | } | |
782 | ||
783 | for (i = 0; i < 8; i++) { | |
784 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
785 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
786 | } | |
787 | ||
788 | for (i = 0; i < 8; i++) { | |
789 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
790 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
791 | } | |
792 | ||
793 | for (i = 0; i < 8; i++) { | |
794 | comp0_bit[i] = *ecc_data2 % 2; | |
795 | *ecc_data2 = *ecc_data2 / 2; | |
796 | } | |
797 | ||
798 | for (i = 0; i < 8; i++) { | |
799 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
800 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
801 | } | |
802 | ||
803 | for (i = 0; i < 8; i++) { | |
804 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
805 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
806 | } | |
807 | ||
808 | for (i = 0; i < 6; i++) | |
809 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
810 | ||
811 | for (i = 0; i < 8; i++) | |
812 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
813 | ||
814 | for (i = 0; i < 8; i++) | |
815 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
816 | ||
817 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
818 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
819 | ||
820 | for (i = 0; i < 24; i++) | |
821 | ecc_sum += ecc_bit[i]; | |
822 | ||
823 | switch (ecc_sum) { | |
824 | case 0: | |
825 | /* Not reached because this function is not called if | |
826 | * ECC values are equal | |
827 | */ | |
828 | return 0; | |
829 | ||
830 | case 1: | |
831 | /* Uncorrectable error */ | |
289c0522 | 832 | pr_debug("ECC UNCORRECTED_ERROR 1\n"); |
67ce04bf VS |
833 | return -1; |
834 | ||
835 | case 11: | |
836 | /* UN-Correctable error */ | |
289c0522 | 837 | pr_debug("ECC UNCORRECTED_ERROR B\n"); |
67ce04bf VS |
838 | return -1; |
839 | ||
840 | case 12: | |
841 | /* Correctable error */ | |
842 | find_byte = (ecc_bit[23] << 8) + | |
843 | (ecc_bit[21] << 7) + | |
844 | (ecc_bit[19] << 6) + | |
845 | (ecc_bit[17] << 5) + | |
846 | (ecc_bit[15] << 4) + | |
847 | (ecc_bit[13] << 3) + | |
848 | (ecc_bit[11] << 2) + | |
849 | (ecc_bit[9] << 1) + | |
850 | ecc_bit[7]; | |
851 | ||
852 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
853 | ||
0a32a102 BN |
854 | pr_debug("Correcting single bit ECC error at offset: " |
855 | "%d, bit: %d\n", find_byte, find_bit); | |
67ce04bf VS |
856 | |
857 | page_data[find_byte] ^= (1 << find_bit); | |
858 | ||
74f1b724 | 859 | return 1; |
67ce04bf VS |
860 | default: |
861 | if (isEccFF) { | |
862 | if (ecc_data2[0] == 0 && | |
863 | ecc_data2[1] == 0 && | |
864 | ecc_data2[2] == 0) | |
865 | return 0; | |
866 | } | |
289c0522 | 867 | pr_debug("UNCORRECTED_ERROR default\n"); |
67ce04bf VS |
868 | return -1; |
869 | } | |
870 | } | |
871 | ||
872 | /** | |
873 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
874 | * @mtd: MTD device structure | |
875 | * @dat: page data | |
876 | * @read_ecc: ecc read from nand flash | |
877 | * @calc_ecc: ecc read from HW ECC registers | |
878 | * | |
879 | * Compares the ecc read from nand spare area with ECC registers values | |
74f1b724 JO |
880 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
881 | * detection and correction. If there are no errors, %0 is returned. If | |
882 | * there were errors and all of the errors were corrected, the number of | |
883 | * corrected errors is returned. If uncorrectable errors exist, %-1 is | |
884 | * returned. | |
67ce04bf VS |
885 | */ |
886 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
887 | u_char *read_ecc, u_char *calc_ecc) | |
888 | { | |
889 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
890 | mtd); | |
891 | int blockCnt = 0, i = 0, ret = 0; | |
74f1b724 | 892 | int stat = 0; |
67ce04bf VS |
893 | |
894 | /* Ex NAND_ECC_HW12_2048 */ | |
895 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
896 | (info->nand.ecc.size == 2048)) | |
897 | blockCnt = 4; | |
898 | else | |
899 | blockCnt = 1; | |
900 | ||
901 | for (i = 0; i < blockCnt; i++) { | |
902 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
903 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
904 | if (ret < 0) | |
905 | return ret; | |
74f1b724 JO |
906 | /* keep track of the number of corrected errors */ |
907 | stat += ret; | |
67ce04bf VS |
908 | } |
909 | read_ecc += 3; | |
910 | calc_ecc += 3; | |
911 | dat += 512; | |
912 | } | |
74f1b724 | 913 | return stat; |
67ce04bf VS |
914 | } |
915 | ||
916 | /** | |
917 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
918 | * @mtd: MTD device structure | |
919 | * @dat: The pointer to data on which ecc is computed | |
920 | * @ecc_code: The ecc_code buffer | |
921 | * | |
922 | * Using noninverted ECC can be considered ugly since writing a blank | |
923 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
924 | * nobody is trying to write data on the seemingly unused page. Reading | |
925 | * an erased page will produce an ECC mismatch between generated and read | |
926 | * ECC bytes that has to be dealt with separately. | |
927 | */ | |
928 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
929 | u_char *ecc_code) | |
930 | { | |
931 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
932 | mtd); | |
65b97cf6 AM |
933 | u32 val; |
934 | ||
935 | val = readl(info->reg.gpmc_ecc_config); | |
936 | if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) | |
937 | return -EINVAL; | |
938 | ||
939 | /* read ecc result */ | |
940 | val = readl(info->reg.gpmc_ecc1_result); | |
941 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
942 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
943 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
944 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
945 | ||
946 | return 0; | |
67ce04bf VS |
947 | } |
948 | ||
949 | /** | |
950 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
951 | * @mtd: MTD device structure | |
952 | * @mode: Read/Write mode | |
953 | */ | |
954 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
955 | { | |
956 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
957 | mtd); | |
958 | struct nand_chip *chip = mtd->priv; | |
959 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
65b97cf6 AM |
960 | u32 val; |
961 | ||
962 | /* clear ecc and enable bits */ | |
963 | val = ECCCLEAR | ECC1; | |
964 | writel(val, info->reg.gpmc_ecc_control); | |
965 | ||
966 | /* program ecc and result sizes */ | |
967 | val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | | |
968 | ECC1RESULTSIZE); | |
969 | writel(val, info->reg.gpmc_ecc_size_config); | |
970 | ||
971 | switch (mode) { | |
972 | case NAND_ECC_READ: | |
973 | case NAND_ECC_WRITE: | |
974 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); | |
975 | break; | |
976 | case NAND_ECC_READSYN: | |
977 | writel(ECCCLEAR, info->reg.gpmc_ecc_control); | |
978 | break; | |
979 | default: | |
980 | dev_info(&info->pdev->dev, | |
981 | "error: unrecognized Mode[%d]!\n", mode); | |
982 | break; | |
983 | } | |
67ce04bf | 984 | |
65b97cf6 AM |
985 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ |
986 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
987 | writel(val, info->reg.gpmc_ecc_config); | |
67ce04bf | 988 | } |
2c01946c | 989 | |
67ce04bf VS |
990 | /** |
991 | * omap_wait - wait until the command is done | |
992 | * @mtd: MTD device structure | |
993 | * @chip: NAND Chip structure | |
994 | * | |
995 | * Wait function is called during Program and erase operations and | |
996 | * the way it is called from MTD layer, we should wait till the NAND | |
997 | * chip is ready after the programming/erase operation has completed. | |
998 | * | |
999 | * Erase can take up to 400ms and program up to 20ms according to | |
1000 | * general NAND and SmartMedia specs | |
1001 | */ | |
1002 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
1003 | { | |
1004 | struct nand_chip *this = mtd->priv; | |
1005 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1006 | mtd); | |
1007 | unsigned long timeo = jiffies; | |
a9c465f0 | 1008 | int status, state = this->state; |
67ce04bf VS |
1009 | |
1010 | if (state == FL_ERASING) | |
1011 | timeo += (HZ * 400) / 1000; | |
1012 | else | |
1013 | timeo += (HZ * 20) / 1000; | |
1014 | ||
65b97cf6 | 1015 | writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); |
67ce04bf | 1016 | while (time_before(jiffies, timeo)) { |
65b97cf6 | 1017 | status = readb(info->reg.gpmc_nand_data); |
c276aca4 | 1018 | if (status & NAND_STATUS_READY) |
67ce04bf | 1019 | break; |
c276aca4 | 1020 | cond_resched(); |
67ce04bf | 1021 | } |
a9c465f0 ID |
1022 | |
1023 | status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA); | |
67ce04bf VS |
1024 | return status; |
1025 | } | |
1026 | ||
1027 | /** | |
1028 | * omap_dev_ready - calls the platform specific dev_ready function | |
1029 | * @mtd: MTD device structure | |
1030 | */ | |
1031 | static int omap_dev_ready(struct mtd_info *mtd) | |
1032 | { | |
2c01946c | 1033 | unsigned int val = 0; |
67ce04bf VS |
1034 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1035 | mtd); | |
67ce04bf | 1036 | |
65b97cf6 AM |
1037 | val = readl(info->reg.gpmc_status); |
1038 | ||
67ce04bf | 1039 | if ((val & 0x100) == 0x100) { |
65b97cf6 | 1040 | return 1; |
67ce04bf | 1041 | } else { |
65b97cf6 | 1042 | return 0; |
67ce04bf | 1043 | } |
67ce04bf VS |
1044 | } |
1045 | ||
0e618ef0 ID |
1046 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
1047 | ||
1048 | /** | |
1049 | * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction | |
1050 | * @mtd: MTD device structure | |
1051 | * @mode: Read/Write mode | |
1052 | */ | |
1053 | static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode) | |
1054 | { | |
1055 | int nerrors; | |
1056 | unsigned int dev_width; | |
1057 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1058 | mtd); | |
1059 | struct nand_chip *chip = mtd->priv; | |
1060 | ||
1061 | nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4; | |
1062 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
1063 | /* | |
1064 | * Program GPMC to perform correction on one 512-byte sector at a time. | |
1065 | * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and | |
1066 | * gives a slight (5%) performance gain (but requires additional code). | |
1067 | */ | |
1068 | (void)gpmc_enable_hwecc_bch(info->gpmc_cs, mode, dev_width, 1, nerrors); | |
1069 | } | |
1070 | ||
1071 | /** | |
1072 | * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes | |
1073 | * @mtd: MTD device structure | |
1074 | * @dat: The pointer to data on which ecc is computed | |
1075 | * @ecc_code: The ecc_code buffer | |
1076 | */ | |
1077 | static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat, | |
1078 | u_char *ecc_code) | |
1079 | { | |
1080 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1081 | mtd); | |
1082 | return gpmc_calculate_ecc_bch4(info->gpmc_cs, dat, ecc_code); | |
1083 | } | |
1084 | ||
1085 | /** | |
1086 | * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes | |
1087 | * @mtd: MTD device structure | |
1088 | * @dat: The pointer to data on which ecc is computed | |
1089 | * @ecc_code: The ecc_code buffer | |
1090 | */ | |
1091 | static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat, | |
1092 | u_char *ecc_code) | |
1093 | { | |
1094 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1095 | mtd); | |
1096 | return gpmc_calculate_ecc_bch8(info->gpmc_cs, dat, ecc_code); | |
1097 | } | |
1098 | ||
1099 | /** | |
1100 | * omap3_correct_data_bch - Decode received data and correct errors | |
1101 | * @mtd: MTD device structure | |
1102 | * @data: page data | |
1103 | * @read_ecc: ecc read from nand flash | |
1104 | * @calc_ecc: ecc read from HW ECC registers | |
1105 | */ | |
1106 | static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data, | |
1107 | u_char *read_ecc, u_char *calc_ecc) | |
1108 | { | |
1109 | int i, count; | |
1110 | /* cannot correct more than 8 errors */ | |
1111 | unsigned int errloc[8]; | |
1112 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1113 | mtd); | |
1114 | ||
1115 | count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL, | |
1116 | errloc); | |
1117 | if (count > 0) { | |
1118 | /* correct errors */ | |
1119 | for (i = 0; i < count; i++) { | |
1120 | /* correct data only, not ecc bytes */ | |
1121 | if (errloc[i] < 8*512) | |
1122 | data[errloc[i]/8] ^= 1 << (errloc[i] & 7); | |
1123 | pr_debug("corrected bitflip %u\n", errloc[i]); | |
1124 | } | |
1125 | } else if (count < 0) { | |
1126 | pr_err("ecc unrecoverable error\n"); | |
1127 | } | |
1128 | return count; | |
1129 | } | |
1130 | ||
1131 | /** | |
1132 | * omap3_free_bch - Release BCH ecc resources | |
1133 | * @mtd: MTD device structure | |
1134 | */ | |
1135 | static void omap3_free_bch(struct mtd_info *mtd) | |
1136 | { | |
1137 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1138 | mtd); | |
1139 | if (info->bch) { | |
1140 | free_bch(info->bch); | |
1141 | info->bch = NULL; | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | /** | |
1146 | * omap3_init_bch - Initialize BCH ECC | |
1147 | * @mtd: MTD device structure | |
1148 | * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW) | |
1149 | */ | |
1150 | static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt) | |
1151 | { | |
1152 | int ret, max_errors; | |
1153 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1154 | mtd); | |
1155 | #ifdef CONFIG_MTD_NAND_OMAP_BCH8 | |
1156 | const int hw_errors = 8; | |
1157 | #else | |
1158 | const int hw_errors = 4; | |
1159 | #endif | |
1160 | info->bch = NULL; | |
1161 | ||
1162 | max_errors = (ecc_opt == OMAP_ECC_BCH8_CODE_HW) ? 8 : 4; | |
1163 | if (max_errors != hw_errors) { | |
1164 | pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported", | |
1165 | max_errors, hw_errors); | |
1166 | goto fail; | |
1167 | } | |
1168 | ||
1169 | /* initialize GPMC BCH engine */ | |
1170 | ret = gpmc_init_hwecc_bch(info->gpmc_cs, 1, max_errors); | |
1171 | if (ret) | |
1172 | goto fail; | |
1173 | ||
1174 | /* software bch library is only used to detect and locate errors */ | |
1175 | info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */); | |
1176 | if (!info->bch) | |
1177 | goto fail; | |
1178 | ||
1179 | info->nand.ecc.size = 512; | |
1180 | info->nand.ecc.hwctl = omap3_enable_hwecc_bch; | |
1181 | info->nand.ecc.correct = omap3_correct_data_bch; | |
1182 | info->nand.ecc.mode = NAND_ECC_HW; | |
1183 | ||
1184 | /* | |
1185 | * The number of corrected errors in an ecc block that will trigger | |
1186 | * block scrubbing defaults to the ecc strength (4 or 8). | |
1187 | * Set mtd->bitflip_threshold here to define a custom threshold. | |
1188 | */ | |
1189 | ||
1190 | if (max_errors == 8) { | |
1191 | info->nand.ecc.strength = 8; | |
1192 | info->nand.ecc.bytes = 13; | |
1193 | info->nand.ecc.calculate = omap3_calculate_ecc_bch8; | |
1194 | } else { | |
1195 | info->nand.ecc.strength = 4; | |
1196 | info->nand.ecc.bytes = 7; | |
1197 | info->nand.ecc.calculate = omap3_calculate_ecc_bch4; | |
1198 | } | |
1199 | ||
1200 | pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors); | |
1201 | return 0; | |
1202 | fail: | |
1203 | omap3_free_bch(mtd); | |
1204 | return -1; | |
1205 | } | |
1206 | ||
1207 | /** | |
1208 | * omap3_init_bch_tail - Build an oob layout for BCH ECC correction. | |
1209 | * @mtd: MTD device structure | |
1210 | */ | |
1211 | static int omap3_init_bch_tail(struct mtd_info *mtd) | |
1212 | { | |
1213 | int i, steps; | |
1214 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1215 | mtd); | |
1216 | struct nand_ecclayout *layout = &info->ecclayout; | |
1217 | ||
1218 | /* build oob layout */ | |
1219 | steps = mtd->writesize/info->nand.ecc.size; | |
1220 | layout->eccbytes = steps*info->nand.ecc.bytes; | |
1221 | ||
1222 | /* do not bother creating special oob layouts for small page devices */ | |
1223 | if (mtd->oobsize < 64) { | |
1224 | pr_err("BCH ecc is not supported on small page devices\n"); | |
1225 | goto fail; | |
1226 | } | |
1227 | ||
1228 | /* reserve 2 bytes for bad block marker */ | |
1229 | if (layout->eccbytes+2 > mtd->oobsize) { | |
1230 | pr_err("no oob layout available for oobsize %d eccbytes %u\n", | |
1231 | mtd->oobsize, layout->eccbytes); | |
1232 | goto fail; | |
1233 | } | |
1234 | ||
1235 | /* put ecc bytes at oob tail */ | |
1236 | for (i = 0; i < layout->eccbytes; i++) | |
1237 | layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i; | |
1238 | ||
1239 | layout->oobfree[0].offset = 2; | |
1240 | layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes; | |
1241 | info->nand.ecc.layout = layout; | |
1242 | ||
1243 | if (!(info->nand.options & NAND_BUSWIDTH_16)) | |
1244 | info->nand.badblock_pattern = &bb_descrip_flashbased; | |
1245 | return 0; | |
1246 | fail: | |
1247 | omap3_free_bch(mtd); | |
1248 | return -1; | |
1249 | } | |
1250 | ||
1251 | #else | |
1252 | static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt) | |
1253 | { | |
1254 | pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n"); | |
1255 | return -1; | |
1256 | } | |
1257 | static int omap3_init_bch_tail(struct mtd_info *mtd) | |
1258 | { | |
1259 | return -1; | |
1260 | } | |
1261 | static void omap3_free_bch(struct mtd_info *mtd) | |
1262 | { | |
1263 | } | |
1264 | #endif /* CONFIG_MTD_NAND_OMAP_BCH */ | |
1265 | ||
67ce04bf VS |
1266 | static int __devinit omap_nand_probe(struct platform_device *pdev) |
1267 | { | |
1268 | struct omap_nand_info *info; | |
1269 | struct omap_nand_platform_data *pdata; | |
1270 | int err; | |
f040d332 | 1271 | int i, offset; |
763e7359 RK |
1272 | dma_cap_mask_t mask; |
1273 | unsigned sig; | |
9c4c2f8b | 1274 | struct resource *res; |
67ce04bf VS |
1275 | |
1276 | pdata = pdev->dev.platform_data; | |
1277 | if (pdata == NULL) { | |
1278 | dev_err(&pdev->dev, "platform data missing\n"); | |
1279 | return -ENODEV; | |
1280 | } | |
1281 | ||
1282 | info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); | |
1283 | if (!info) | |
1284 | return -ENOMEM; | |
1285 | ||
1286 | platform_set_drvdata(pdev, info); | |
1287 | ||
1288 | spin_lock_init(&info->controller.lock); | |
1289 | init_waitqueue_head(&info->controller.wq); | |
1290 | ||
1291 | info->pdev = pdev; | |
1292 | ||
1293 | info->gpmc_cs = pdata->cs; | |
65b97cf6 | 1294 | info->reg = pdata->reg; |
67ce04bf VS |
1295 | |
1296 | info->mtd.priv = &info->nand; | |
1297 | info->mtd.name = dev_name(&pdev->dev); | |
1298 | info->mtd.owner = THIS_MODULE; | |
1299 | ||
d5ce2b65 | 1300 | info->nand.options = pdata->devsize; |
2f70a1e9 | 1301 | info->nand.options |= NAND_SKIP_BBTSCAN; |
67ce04bf VS |
1302 | |
1303 | /* NAND write protect off */ | |
2c01946c | 1304 | gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0); |
67ce04bf | 1305 | |
9c4c2f8b AM |
1306 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1307 | if (res == NULL) { | |
1308 | err = -EINVAL; | |
1309 | dev_err(&pdev->dev, "error getting memory resource\n"); | |
1310 | goto out_free_info; | |
1311 | } | |
1312 | ||
1313 | info->phys_base = res->start; | |
1314 | info->mem_size = resource_size(res); | |
1315 | ||
1316 | if (!request_mem_region(info->phys_base, info->mem_size, | |
67ce04bf VS |
1317 | pdev->dev.driver->name)) { |
1318 | err = -EBUSY; | |
2f70a1e9 | 1319 | goto out_free_info; |
67ce04bf VS |
1320 | } |
1321 | ||
9c4c2f8b | 1322 | info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size); |
67ce04bf VS |
1323 | if (!info->nand.IO_ADDR_R) { |
1324 | err = -ENOMEM; | |
1325 | goto out_release_mem_region; | |
1326 | } | |
59e9c5ae | 1327 | |
67ce04bf VS |
1328 | info->nand.controller = &info->controller; |
1329 | ||
1330 | info->nand.IO_ADDR_W = info->nand.IO_ADDR_R; | |
1331 | info->nand.cmd_ctrl = omap_hwcontrol; | |
1332 | ||
67ce04bf VS |
1333 | /* |
1334 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
1335 | * funcrtion and the generic nand_wait function which reads the status | |
1336 | * register after monitoring the RDY/BSY line.Otherwise use a standard | |
1337 | * chip delay which is slightly more than tR (AC Timing) of the NAND | |
1338 | * device and read status register until you get a failure or success | |
1339 | */ | |
1340 | if (pdata->dev_ready) { | |
1341 | info->nand.dev_ready = omap_dev_ready; | |
1342 | info->nand.chip_delay = 0; | |
1343 | } else { | |
1344 | info->nand.waitfunc = omap_wait; | |
1345 | info->nand.chip_delay = 50; | |
1346 | } | |
1347 | ||
1b0b323c SG |
1348 | switch (pdata->xfer_type) { |
1349 | case NAND_OMAP_PREFETCH_POLLED: | |
59e9c5ae | 1350 | info->nand.read_buf = omap_read_buf_pref; |
1351 | info->nand.write_buf = omap_write_buf_pref; | |
1b0b323c SG |
1352 | break; |
1353 | ||
1354 | case NAND_OMAP_POLLED: | |
59e9c5ae | 1355 | if (info->nand.options & NAND_BUSWIDTH_16) { |
1356 | info->nand.read_buf = omap_read_buf16; | |
1357 | info->nand.write_buf = omap_write_buf16; | |
1358 | } else { | |
1359 | info->nand.read_buf = omap_read_buf8; | |
1360 | info->nand.write_buf = omap_write_buf8; | |
1361 | } | |
1b0b323c SG |
1362 | break; |
1363 | ||
1364 | case NAND_OMAP_PREFETCH_DMA: | |
763e7359 RK |
1365 | dma_cap_zero(mask); |
1366 | dma_cap_set(DMA_SLAVE, mask); | |
1367 | sig = OMAP24XX_DMA_GPMC; | |
1368 | info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
1369 | if (!info->dma) { | |
2df41d05 RK |
1370 | dev_err(&pdev->dev, "DMA engine request failed\n"); |
1371 | err = -ENXIO; | |
1372 | goto out_release_mem_region; | |
763e7359 RK |
1373 | } else { |
1374 | struct dma_slave_config cfg; | |
763e7359 RK |
1375 | |
1376 | memset(&cfg, 0, sizeof(cfg)); | |
1377 | cfg.src_addr = info->phys_base; | |
1378 | cfg.dst_addr = info->phys_base; | |
1379 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1380 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1381 | cfg.src_maxburst = 16; | |
1382 | cfg.dst_maxburst = 16; | |
d680e2c1 AB |
1383 | err = dmaengine_slave_config(info->dma, &cfg); |
1384 | if (err) { | |
763e7359 | 1385 | dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", |
d680e2c1 | 1386 | err); |
763e7359 RK |
1387 | goto out_release_mem_region; |
1388 | } | |
1389 | info->nand.read_buf = omap_read_buf_dma_pref; | |
1390 | info->nand.write_buf = omap_write_buf_dma_pref; | |
1b0b323c SG |
1391 | } |
1392 | break; | |
1393 | ||
4e070376 SG |
1394 | case NAND_OMAP_PREFETCH_IRQ: |
1395 | err = request_irq(pdata->gpmc_irq, | |
1396 | omap_nand_irq, IRQF_SHARED, "gpmc-nand", info); | |
1397 | if (err) { | |
1398 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
1399 | pdata->gpmc_irq, err); | |
1400 | goto out_release_mem_region; | |
1401 | } else { | |
1402 | info->gpmc_irq = pdata->gpmc_irq; | |
1403 | info->nand.read_buf = omap_read_buf_irq_pref; | |
1404 | info->nand.write_buf = omap_write_buf_irq_pref; | |
1405 | } | |
1406 | break; | |
1407 | ||
1b0b323c SG |
1408 | default: |
1409 | dev_err(&pdev->dev, | |
1410 | "xfer_type(%d) not supported!\n", pdata->xfer_type); | |
1411 | err = -EINVAL; | |
1412 | goto out_release_mem_region; | |
59e9c5ae | 1413 | } |
59e9c5ae | 1414 | |
59e9c5ae | 1415 | info->nand.verify_buf = omap_verify_buf; |
67ce04bf | 1416 | |
f3d73f36 SG |
1417 | /* selsect the ecc type */ |
1418 | if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) | |
1419 | info->nand.ecc.mode = NAND_ECC_SOFT; | |
f040d332 SG |
1420 | else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || |
1421 | (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { | |
f3d73f36 SG |
1422 | info->nand.ecc.bytes = 3; |
1423 | info->nand.ecc.size = 512; | |
6a918bad | 1424 | info->nand.ecc.strength = 1; |
f3d73f36 SG |
1425 | info->nand.ecc.calculate = omap_calculate_ecc; |
1426 | info->nand.ecc.hwctl = omap_enable_hwecc; | |
1427 | info->nand.ecc.correct = omap_correct_data; | |
1428 | info->nand.ecc.mode = NAND_ECC_HW; | |
0e618ef0 ID |
1429 | } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || |
1430 | (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { | |
1431 | err = omap3_init_bch(&info->mtd, pdata->ecc_opt); | |
1432 | if (err) { | |
1433 | err = -EINVAL; | |
1434 | goto out_release_mem_region; | |
1435 | } | |
f3d73f36 | 1436 | } |
67ce04bf VS |
1437 | |
1438 | /* DIP switches on some boards change between 8 and 16 bit | |
1439 | * bus widths for flash. Try the other width if the first try fails. | |
1440 | */ | |
a80f1c1f | 1441 | if (nand_scan_ident(&info->mtd, 1, NULL)) { |
67ce04bf | 1442 | info->nand.options ^= NAND_BUSWIDTH_16; |
a80f1c1f | 1443 | if (nand_scan_ident(&info->mtd, 1, NULL)) { |
67ce04bf VS |
1444 | err = -ENXIO; |
1445 | goto out_release_mem_region; | |
1446 | } | |
1447 | } | |
1448 | ||
f040d332 SG |
1449 | /* rom code layout */ |
1450 | if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) { | |
1451 | ||
1452 | if (info->nand.options & NAND_BUSWIDTH_16) | |
1453 | offset = 2; | |
1454 | else { | |
1455 | offset = 1; | |
1456 | info->nand.badblock_pattern = &bb_descrip_flashbased; | |
1457 | } | |
1458 | omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16); | |
1459 | for (i = 0; i < omap_oobinfo.eccbytes; i++) | |
1460 | omap_oobinfo.eccpos[i] = i+offset; | |
1461 | ||
1462 | omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; | |
1463 | omap_oobinfo.oobfree->length = info->mtd.oobsize - | |
1464 | (offset + omap_oobinfo.eccbytes); | |
1465 | ||
1466 | info->nand.ecc.layout = &omap_oobinfo; | |
0e618ef0 ID |
1467 | } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || |
1468 | (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { | |
1469 | /* build OOB layout for BCH ECC correction */ | |
1470 | err = omap3_init_bch_tail(&info->mtd); | |
1471 | if (err) { | |
1472 | err = -EINVAL; | |
1473 | goto out_release_mem_region; | |
1474 | } | |
f040d332 | 1475 | } |
1b0b323c | 1476 | |
a80f1c1f JW |
1477 | /* second phase scan */ |
1478 | if (nand_scan_tail(&info->mtd)) { | |
1479 | err = -ENXIO; | |
1480 | goto out_release_mem_region; | |
1481 | } | |
1482 | ||
42d7fbe2 AB |
1483 | mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts, |
1484 | pdata->nr_parts); | |
67ce04bf VS |
1485 | |
1486 | platform_set_drvdata(pdev, &info->mtd); | |
1487 | ||
1488 | return 0; | |
1489 | ||
1490 | out_release_mem_region: | |
763e7359 RK |
1491 | if (info->dma) |
1492 | dma_release_channel(info->dma); | |
9c4c2f8b | 1493 | release_mem_region(info->phys_base, info->mem_size); |
67ce04bf VS |
1494 | out_free_info: |
1495 | kfree(info); | |
1496 | ||
1497 | return err; | |
1498 | } | |
1499 | ||
1500 | static int omap_nand_remove(struct platform_device *pdev) | |
1501 | { | |
1502 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
f35b6eda VS |
1503 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1504 | mtd); | |
0e618ef0 | 1505 | omap3_free_bch(&info->mtd); |
67ce04bf VS |
1506 | |
1507 | platform_set_drvdata(pdev, NULL); | |
763e7359 RK |
1508 | if (info->dma) |
1509 | dma_release_channel(info->dma); | |
1510 | ||
4e070376 SG |
1511 | if (info->gpmc_irq) |
1512 | free_irq(info->gpmc_irq, info); | |
1513 | ||
67ce04bf VS |
1514 | /* Release NAND device, its internal structures and partitions */ |
1515 | nand_release(&info->mtd); | |
2c01946c | 1516 | iounmap(info->nand.IO_ADDR_R); |
67ce04bf VS |
1517 | kfree(&info->mtd); |
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | static struct platform_driver omap_nand_driver = { | |
1522 | .probe = omap_nand_probe, | |
1523 | .remove = omap_nand_remove, | |
1524 | .driver = { | |
1525 | .name = DRIVER_NAME, | |
1526 | .owner = THIS_MODULE, | |
1527 | }, | |
1528 | }; | |
1529 | ||
f99640de | 1530 | module_platform_driver(omap_nand_driver); |
67ce04bf | 1531 | |
c804c733 | 1532 | MODULE_ALIAS("platform:" DRIVER_NAME); |
67ce04bf VS |
1533 | MODULE_LICENSE("GPL"); |
1534 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |