[deliverable/linux.git] / drivers / mtd / nand / orion_nand.c

/*
 * drivers/mtd/nand/orion_nand.c
 *
 * NAND support for Marvell Orion SoC platforms
 *
 * Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under  the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <asm/sizes.h>
#include <linux/platform_data/mtd-orion_nand.h>

static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *nc = mtd_to_nand(mtd);
	struct orion_nand_data *board = nand_get_controller_data(nc);
	u32 offs;

	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		offs = (1 << board->cle);
	else if (ctrl & NAND_ALE)
		offs = (1 << board->ale);
	else
		return;

	if (nc->options & NAND_BUSWIDTH_16)
		offs <<= 1;

	writeb(cmd, nc->IO_ADDR_W + offs);
}

static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	void __iomem *io_base = chip->IO_ADDR_R;
	uint64_t *buf64;
	int i = 0;

	while (len && (unsigned long)buf & 7) {
		*buf++ = readb(io_base);
		len--;
	}
	buf64 = (uint64_t *)buf;
	while (i < len/8) {
		/*
		 * Since GCC has no proper constraint (PR 43518)
		 * force x variable to r2/r3 registers as ldrd instruction
		 * requires first register to be even.
		 */
		register uint64_t x asm ("r2");

		asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base));
		buf64[i++] = x;
	}
	i *= 8;
	while (i < len)
		buf[i++] = readb(io_base);
}

static int __init orion_nand_probe(struct platform_device *pdev)
{
	struct mtd_info *mtd;
	struct nand_chip *nc;
	struct orion_nand_data *board;
	struct resource *res;
	struct clk *clk;
	void __iomem *io_base;
	int ret = 0;
	u32 val = 0;

	nc = devm_kzalloc(&pdev->dev,
			sizeof(struct nand_chip),
			GFP_KERNEL);
	if (!nc)
		return -ENOMEM;
	mtd = nand_to_mtd(nc);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	io_base = devm_ioremap_resource(&pdev->dev, res);

	if (IS_ERR(io_base))
		return PTR_ERR(io_base);

	if (pdev->dev.of_node) {
		board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
					GFP_KERNEL);
		if (!board)
			return -ENOMEM;
		if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
			board->cle = (u8)val;
		else
			board->cle = 0;
		if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
			board->ale = (u8)val;
		else
			board->ale = 1;
		if (!of_property_read_u32(pdev->dev.of_node,
						"bank-width", &val))
			board->width = (u8)val * 8;
		else
			board->width = 8;
		if (!of_property_read_u32(pdev->dev.of_node,
						"chip-delay", &val))
			board->chip_delay = (u8)val;
	} else {
		board = dev_get_platdata(&pdev->dev);
	}

	mtd->dev.parent = &pdev->dev;

	nand_set_controller_data(nc, board);
	nand_set_flash_node(nc, pdev->dev.of_node);
	nc->IO_ADDR_R = nc->IO_ADDR_W = io_base;
	nc->cmd_ctrl = orion_nand_cmd_ctrl;
	nc->read_buf = orion_nand_read_buf;
	nc->ecc.mode = NAND_ECC_SOFT;
	nc->ecc.algo = NAND_ECC_HAMMING;

	if (board->chip_delay)
		nc->chip_delay = board->chip_delay;

	WARN(board->width > 16,
		"%d bit bus width out of range",
		board->width);

	if (board->width == 16)
		nc->options |= NAND_BUSWIDTH_16;

	if (board->dev_ready)
		nc->dev_ready = board->dev_ready;

	platform_set_drvdata(pdev, mtd);

	/* Not all platforms can gate the clock, so it is not
	   an error if the clock does not exists. */
	clk = clk_get(&pdev->dev, NULL);
	if (!IS_ERR(clk)) {
		clk_prepare_enable(clk);
		clk_put(clk);
	}

	if (nand_scan(mtd, 1)) {
		ret = -ENXIO;
		goto no_dev;
	}

	mtd->name = "orion_nand";
	ret = mtd_device_register(mtd, board->parts, board->nr_parts);
	if (ret) {
		nand_release(mtd);
		goto no_dev;
	}

	return 0;

no_dev:
	if (!IS_ERR(clk)) {
		clk_disable_unprepare(clk);
		clk_put(clk);
	}

	return ret;
}

static int orion_nand_remove(struct platform_device *pdev)
{
	struct mtd_info *mtd = platform_get_drvdata(pdev);
	struct clk *clk;

	nand_release(mtd);

	clk = clk_get(&pdev->dev, NULL);
	if (!IS_ERR(clk)) {
		clk_disable_unprepare(clk);
		clk_put(clk);
	}

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id orion_nand_of_match_table[] = {
	{ .compatible = "marvell,orion-nand", },
	{},
};
MODULE_DEVICE_TABLE(of, orion_nand_of_match_table);
#endif

static struct platform_driver orion_nand_driver = {
	.remove		= orion_nand_remove,
	.driver		= {
		.name	= "orion_nand",
		.of_match_table = of_match_ptr(orion_nand_of_match_table),
	},
};

module_platform_driver_probe(orion_nand_driver, orion_nand_probe);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tzachi Perelstein");
MODULE_DESCRIPTION("NAND glue for Orion platforms");
MODULE_ALIAS("platform:orion_nand");
Commit	Line	Data
2a1dba29 TP	1	/*
	2	* drivers/mtd/nand/orion_nand.c
	3	*
	4	* NAND support for Marvell Orion SoC platforms
	5	*
	6	* Tzachi Perelstein <tzachi@marvell.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/slab.h>
	14	#include <linux/module.h>
	15	#include <linux/platform_device.h>
a0fabf72	16	#include <linux/of.h>
2a1dba29 TP	17	#include <linux/mtd/mtd.h>
	18	#include <linux/mtd/nand.h>
	19	#include <linux/mtd/partitions.h>
9c2bd504 AL	20	#include <linux/clk.h>
9c2bd504 AL	21	#include <linux/err.h>
a0fa0b66	22	#include <linux/io.h>
2a1dba29	23	#include <asm/sizes.h>
c02cecb9	24	#include <linux/platform_data/mtd-orion_nand.h>
2a1dba29	25
2a1dba29 TP	26	static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
2a1dba29 TP	27	{
4bd4ebcc	28	struct nand_chip *nc = mtd_to_nand(mtd);
d699ed25	29	struct orion_nand_data *board = nand_get_controller_data(nc);
2a1dba29 TP	30	u32 offs;
	31
	32	if (cmd == NAND_CMD_NONE)
	33	return;
	34
	35	if (ctrl & NAND_CLE)
	36	offs = (1 << board->cle);
	37	else if (ctrl & NAND_ALE)
	38	offs = (1 << board->ale);
	39	else
	40	return;
	41
	42	if (nc->options & NAND_BUSWIDTH_16)
	43	offs <<= 1;
	44
	45	writeb(cmd, nc->IO_ADDR_W + offs);
	46	}
	47
bfee1a43 NP	48	static void orion_nand_read_buf(struct mtd_info mtd, uint8_t buf, int len)
bfee1a43 NP	49	{
4bd4ebcc	50	struct nand_chip *chip = mtd_to_nand(mtd);
bfee1a43 NP	51	void __iomem *io_base = chip->IO_ADDR_R;
	52	uint64_t *buf64;
	53	int i = 0;
	54
	55	while (len && (unsigned long)buf & 7) {
	56	*buf++ = readb(io_base);
	57	len--;
	58	}
	59	buf64 = (uint64_t *)buf;
	60	while (i < len/8) {
a88a2b88 PZ	61	/*
	62	* Since GCC has no proper constraint (PR 43518)
	63	* force x variable to r2/r3 registers as ldrd instruction
	64	* requires first register to be even.
	65	*/
	66	register uint64_t x asm ("r2");
	67
94da210a	68	asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base));
bfee1a43 NP	69	buf64[i++] = x;
	70	}
	71	i *= 8;
	72	while (i < len)
	73	buf[i++] = readb(io_base);
	74	}
	75
2a1dba29 TP	76	static int __init orion_nand_probe(struct platform_device *pdev)
	77	{
	78	struct mtd_info *mtd;
	79	struct nand_chip *nc;
	80	struct orion_nand_data *board;
e9903060	81	struct resource *res;
9c2bd504	82	struct clk *clk;
2a1dba29 TP	83	void __iomem *io_base;
2a1dba29 TP	84	int ret = 0;
a0fabf72	85	u32 val = 0;
2a1dba29	86
a0fa0b66	87	nc = devm_kzalloc(&pdev->dev,
53cd2681	88	sizeof(struct nand_chip),
a0fa0b66 MO	89	GFP_KERNEL);
	90	if (!nc)
	91	return -ENOMEM;
53cd2681	92	mtd = nand_to_mtd(nc);
2a1dba29	93
e9903060	94	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a0fa0b66	95	io_base = devm_ioremap_resource(&pdev->dev, res);
e9903060	96
a0fa0b66 MO	97	if (IS_ERR(io_base))
a0fa0b66 MO	98	return PTR_ERR(io_base);
2a1dba29	99
a0fabf72 JL	100	if (pdev->dev.of_node) {
	101	board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
	102	GFP_KERNEL);
a0fa0b66 MO	103	if (!board)
a0fa0b66 MO	104	return -ENOMEM;
a0fabf72 JL	105	if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
	106	board->cle = (u8)val;
	107	else
	108	board->cle = 0;
	109	if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
	110	board->ale = (u8)val;
	111	else
	112	board->ale = 1;
	113	if (!of_property_read_u32(pdev->dev.of_node,
	114	"bank-width", &val))
	115	board->width = (u8)val * 8;
	116	else
	117	board->width = 8;
	118	if (!of_property_read_u32(pdev->dev.of_node,
	119	"chip-delay", &val))
	120	board->chip_delay = (u8)val;
453810b7 JH	121	} else {
	122	board = dev_get_platdata(&pdev->dev);
	123	}
2a1dba29	124
84630994	125	mtd->dev.parent = &pdev->dev;
2a1dba29	126
d699ed25	127	nand_set_controller_data(nc, board);
a61ae81a	128	nand_set_flash_node(nc, pdev->dev.of_node);
2a1dba29 TP	129	nc->IO_ADDR_R = nc->IO_ADDR_W = io_base;
2a1dba29 TP	130	nc->cmd_ctrl = orion_nand_cmd_ctrl;
bfee1a43	131	nc->read_buf = orion_nand_read_buf;
2a1dba29	132	nc->ecc.mode = NAND_ECC_SOFT;
ac7efcbe	133	nc->ecc.algo = NAND_ECC_HAMMING;
2a1dba29	134
f4db56ff SB	135	if (board->chip_delay)
	136	nc->chip_delay = board->chip_delay;
	137
a0fabf72 JL	138	WARN(board->width > 16,
	139	"%d bit bus width out of range",
	140	board->width);
	141
2a1dba29 TP	142	if (board->width == 16)
	143	nc->options \|= NAND_BUSWIDTH_16;
	144
eedfea25 BD	145	if (board->dev_ready)
	146	nc->dev_ready = board->dev_ready;
	147
2a1dba29 TP	148	platform_set_drvdata(pdev, mtd);
2a1dba29 TP	149
9c2bd504 AL	150	/* Not all platforms can gate the clock, so it is not
	151	an error if the clock does not exists. */
	152	clk = clk_get(&pdev->dev, NULL);
	153	if (!IS_ERR(clk)) {
	154	clk_prepare_enable(clk);
	155	clk_put(clk);
	156	}
	157
2a1dba29 TP	158	if (nand_scan(mtd, 1)) {
	159	ret = -ENXIO;
	160	goto no_dev;
	161	}
	162
2a1dba29	163	mtd->name = "orion_nand";
a61ae81a	164	ret = mtd_device_register(mtd, board->parts, board->nr_parts);
2a1dba29 TP	165	if (ret) {
	166	nand_release(mtd);
	167	goto no_dev;
	168	}
	169
	170	return 0;
	171
	172	no_dev:
baffab28 SB	173	if (!IS_ERR(clk)) {
	174	clk_disable_unprepare(clk);
	175	clk_put(clk);
	176	}
2a1dba29 TP	177
	178	return ret;
	179	}
	180
810b7e06	181	static int orion_nand_remove(struct platform_device *pdev)
2a1dba29 TP	182	{
2a1dba29 TP	183	struct mtd_info *mtd = platform_get_drvdata(pdev);
9c2bd504	184	struct clk *clk;
2a1dba29 TP	185
	186	nand_release(mtd);
	187
9c2bd504 AL	188	clk = clk_get(&pdev->dev, NULL);
	189	if (!IS_ERR(clk)) {
	190	clk_disable_unprepare(clk);
	191	clk_put(clk);
	192	}
	193
2a1dba29 TP	194	return 0;
	195	}
	196
a0fabf72	197	#ifdef CONFIG_OF
cb3346ac	198	static const struct of_device_id orion_nand_of_match_table[] = {
77843504	199	{ .compatible = "marvell,orion-nand", },
a0fabf72 JL	200	{},
a0fabf72 JL	201	};
98d1a5ee	202	MODULE_DEVICE_TABLE(of, orion_nand_of_match_table);
a0fabf72 JL	203	#endif
a0fabf72 JL	204
2a1dba29	205	static struct platform_driver orion_nand_driver = {
5153b88c	206	.remove = orion_nand_remove,
2a1dba29 TP	207	.driver = {
2a1dba29 TP	208	.name = "orion_nand",
a0fabf72	209	.of_match_table = of_match_ptr(orion_nand_of_match_table),
2a1dba29 TP	210	},
	211	};
	212
d9ba3109	213	module_platform_driver_probe(orion_nand_driver, orion_nand_probe);
2a1dba29 TP	214
	215	MODULE_LICENSE("GPL");
	216	MODULE_AUTHOR("Tzachi Perelstein");
	217	MODULE_DESCRIPTION("NAND glue for Orion platforms");
1ff18422	218	MODULE_ALIAS("platform:orion_nand");