Commit | Line | Data |
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2a1dba29 TP |
1 | /* |
2 | * drivers/mtd/nand/orion_nand.c | |
3 | * | |
4 | * NAND support for Marvell Orion SoC platforms | |
5 | * | |
6 | * Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/slab.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
a0fabf72 | 16 | #include <linux/of.h> |
2a1dba29 TP |
17 | #include <linux/mtd/mtd.h> |
18 | #include <linux/mtd/nand.h> | |
19 | #include <linux/mtd/partitions.h> | |
9c2bd504 AL |
20 | #include <linux/clk.h> |
21 | #include <linux/err.h> | |
a0fa0b66 | 22 | #include <linux/io.h> |
2a1dba29 | 23 | #include <asm/sizes.h> |
c02cecb9 | 24 | #include <linux/platform_data/mtd-orion_nand.h> |
2a1dba29 | 25 | |
2a1dba29 TP |
26 | static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
27 | { | |
4bd4ebcc | 28 | struct nand_chip *nc = mtd_to_nand(mtd); |
d699ed25 | 29 | struct orion_nand_data *board = nand_get_controller_data(nc); |
2a1dba29 TP |
30 | u32 offs; |
31 | ||
32 | if (cmd == NAND_CMD_NONE) | |
33 | return; | |
34 | ||
35 | if (ctrl & NAND_CLE) | |
36 | offs = (1 << board->cle); | |
37 | else if (ctrl & NAND_ALE) | |
38 | offs = (1 << board->ale); | |
39 | else | |
40 | return; | |
41 | ||
42 | if (nc->options & NAND_BUSWIDTH_16) | |
43 | offs <<= 1; | |
44 | ||
45 | writeb(cmd, nc->IO_ADDR_W + offs); | |
46 | } | |
47 | ||
bfee1a43 NP |
48 | static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
49 | { | |
4bd4ebcc | 50 | struct nand_chip *chip = mtd_to_nand(mtd); |
bfee1a43 NP |
51 | void __iomem *io_base = chip->IO_ADDR_R; |
52 | uint64_t *buf64; | |
53 | int i = 0; | |
54 | ||
55 | while (len && (unsigned long)buf & 7) { | |
56 | *buf++ = readb(io_base); | |
57 | len--; | |
58 | } | |
59 | buf64 = (uint64_t *)buf; | |
60 | while (i < len/8) { | |
a88a2b88 PZ |
61 | /* |
62 | * Since GCC has no proper constraint (PR 43518) | |
63 | * force x variable to r2/r3 registers as ldrd instruction | |
64 | * requires first register to be even. | |
65 | */ | |
66 | register uint64_t x asm ("r2"); | |
67 | ||
94da210a | 68 | asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base)); |
bfee1a43 NP |
69 | buf64[i++] = x; |
70 | } | |
71 | i *= 8; | |
72 | while (i < len) | |
73 | buf[i++] = readb(io_base); | |
74 | } | |
75 | ||
2a1dba29 TP |
76 | static int __init orion_nand_probe(struct platform_device *pdev) |
77 | { | |
78 | struct mtd_info *mtd; | |
79 | struct nand_chip *nc; | |
80 | struct orion_nand_data *board; | |
e9903060 | 81 | struct resource *res; |
9c2bd504 | 82 | struct clk *clk; |
2a1dba29 TP |
83 | void __iomem *io_base; |
84 | int ret = 0; | |
a0fabf72 | 85 | u32 val = 0; |
2a1dba29 | 86 | |
a0fa0b66 | 87 | nc = devm_kzalloc(&pdev->dev, |
53cd2681 | 88 | sizeof(struct nand_chip), |
a0fa0b66 MO |
89 | GFP_KERNEL); |
90 | if (!nc) | |
91 | return -ENOMEM; | |
53cd2681 | 92 | mtd = nand_to_mtd(nc); |
2a1dba29 | 93 | |
e9903060 | 94 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a0fa0b66 | 95 | io_base = devm_ioremap_resource(&pdev->dev, res); |
e9903060 | 96 | |
a0fa0b66 MO |
97 | if (IS_ERR(io_base)) |
98 | return PTR_ERR(io_base); | |
2a1dba29 | 99 | |
a0fabf72 JL |
100 | if (pdev->dev.of_node) { |
101 | board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data), | |
102 | GFP_KERNEL); | |
a0fa0b66 MO |
103 | if (!board) |
104 | return -ENOMEM; | |
a0fabf72 JL |
105 | if (!of_property_read_u32(pdev->dev.of_node, "cle", &val)) |
106 | board->cle = (u8)val; | |
107 | else | |
108 | board->cle = 0; | |
109 | if (!of_property_read_u32(pdev->dev.of_node, "ale", &val)) | |
110 | board->ale = (u8)val; | |
111 | else | |
112 | board->ale = 1; | |
113 | if (!of_property_read_u32(pdev->dev.of_node, | |
114 | "bank-width", &val)) | |
115 | board->width = (u8)val * 8; | |
116 | else | |
117 | board->width = 8; | |
118 | if (!of_property_read_u32(pdev->dev.of_node, | |
119 | "chip-delay", &val)) | |
120 | board->chip_delay = (u8)val; | |
453810b7 JH |
121 | } else { |
122 | board = dev_get_platdata(&pdev->dev); | |
123 | } | |
2a1dba29 | 124 | |
84630994 | 125 | mtd->dev.parent = &pdev->dev; |
2a1dba29 | 126 | |
d699ed25 | 127 | nand_set_controller_data(nc, board); |
a61ae81a | 128 | nand_set_flash_node(nc, pdev->dev.of_node); |
2a1dba29 TP |
129 | nc->IO_ADDR_R = nc->IO_ADDR_W = io_base; |
130 | nc->cmd_ctrl = orion_nand_cmd_ctrl; | |
bfee1a43 | 131 | nc->read_buf = orion_nand_read_buf; |
2a1dba29 TP |
132 | nc->ecc.mode = NAND_ECC_SOFT; |
133 | ||
f4db56ff SB |
134 | if (board->chip_delay) |
135 | nc->chip_delay = board->chip_delay; | |
136 | ||
a0fabf72 JL |
137 | WARN(board->width > 16, |
138 | "%d bit bus width out of range", | |
139 | board->width); | |
140 | ||
2a1dba29 TP |
141 | if (board->width == 16) |
142 | nc->options |= NAND_BUSWIDTH_16; | |
143 | ||
eedfea25 BD |
144 | if (board->dev_ready) |
145 | nc->dev_ready = board->dev_ready; | |
146 | ||
2a1dba29 TP |
147 | platform_set_drvdata(pdev, mtd); |
148 | ||
9c2bd504 AL |
149 | /* Not all platforms can gate the clock, so it is not |
150 | an error if the clock does not exists. */ | |
151 | clk = clk_get(&pdev->dev, NULL); | |
152 | if (!IS_ERR(clk)) { | |
153 | clk_prepare_enable(clk); | |
154 | clk_put(clk); | |
155 | } | |
156 | ||
2a1dba29 TP |
157 | if (nand_scan(mtd, 1)) { |
158 | ret = -ENXIO; | |
159 | goto no_dev; | |
160 | } | |
161 | ||
2a1dba29 | 162 | mtd->name = "orion_nand"; |
a61ae81a | 163 | ret = mtd_device_register(mtd, board->parts, board->nr_parts); |
2a1dba29 TP |
164 | if (ret) { |
165 | nand_release(mtd); | |
166 | goto no_dev; | |
167 | } | |
168 | ||
169 | return 0; | |
170 | ||
171 | no_dev: | |
baffab28 SB |
172 | if (!IS_ERR(clk)) { |
173 | clk_disable_unprepare(clk); | |
174 | clk_put(clk); | |
175 | } | |
2a1dba29 TP |
176 | |
177 | return ret; | |
178 | } | |
179 | ||
810b7e06 | 180 | static int orion_nand_remove(struct platform_device *pdev) |
2a1dba29 TP |
181 | { |
182 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
9c2bd504 | 183 | struct clk *clk; |
2a1dba29 TP |
184 | |
185 | nand_release(mtd); | |
186 | ||
9c2bd504 AL |
187 | clk = clk_get(&pdev->dev, NULL); |
188 | if (!IS_ERR(clk)) { | |
189 | clk_disable_unprepare(clk); | |
190 | clk_put(clk); | |
191 | } | |
192 | ||
2a1dba29 TP |
193 | return 0; |
194 | } | |
195 | ||
a0fabf72 | 196 | #ifdef CONFIG_OF |
cb3346ac | 197 | static const struct of_device_id orion_nand_of_match_table[] = { |
77843504 | 198 | { .compatible = "marvell,orion-nand", }, |
a0fabf72 JL |
199 | {}, |
200 | }; | |
98d1a5ee | 201 | MODULE_DEVICE_TABLE(of, orion_nand_of_match_table); |
a0fabf72 JL |
202 | #endif |
203 | ||
2a1dba29 | 204 | static struct platform_driver orion_nand_driver = { |
5153b88c | 205 | .remove = orion_nand_remove, |
2a1dba29 TP |
206 | .driver = { |
207 | .name = "orion_nand", | |
a0fabf72 | 208 | .of_match_table = of_match_ptr(orion_nand_of_match_table), |
2a1dba29 TP |
209 | }, |
210 | }; | |
211 | ||
d9ba3109 | 212 | module_platform_driver_probe(orion_nand_driver, orion_nand_probe); |
2a1dba29 TP |
213 | |
214 | MODULE_LICENSE("GPL"); | |
215 | MODULE_AUTHOR("Tzachi Perelstein"); | |
216 | MODULE_DESCRIPTION("NAND glue for Orion platforms"); | |
1ff18422 | 217 | MODULE_ALIAS("platform:orion_nand"); |