[deliverable/linux.git] / drivers / mtd / nand / ppchameleonevb.c

/*
 *  drivers/mtd/nand/ppchameleonevb.c
 *
 *  Copyright (C) 2003 DAVE Srl (info@wawnet.biz)
 *
 *  Derived from drivers/mtd/nand/edb7312.c
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Overview:
 *   This is a device driver for the NAND flash devices found on the
 *   PPChameleon/PPChameleonEVB system.
 *   PPChameleon options (autodetected):
 *   - BA model: no NAND
 *   - ME model: 32MB (Samsung K9F5608U0B)
 *   - HI model: 128MB (Samsung K9F1G08UOM)
 *   PPChameleonEVB options:
 *   - 32MB (Samsung K9F5608U0B)
 */

#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <asm/io.h>
#include <platforms/PPChameleonEVB.h>

#undef USE_READY_BUSY_PIN
#define USE_READY_BUSY_PIN
/* see datasheets (tR) */
#define NAND_BIG_DELAY_US		25
#define NAND_SMALL_DELAY_US		10

/* handy sizes */
#define SZ_4M                           0x00400000
#define NAND_SMALL_SIZE                 0x02000000
#define NAND_MTD_NAME		"ppchameleon-nand"
#define NAND_EVB_MTD_NAME	"ppchameleonevb-nand"

/* GPIO pins used to drive NAND chip mounted on processor module */
#define NAND_nCE_GPIO_PIN 		(0x80000000 >> 1)
#define NAND_CLE_GPIO_PIN 		(0x80000000 >> 2)
#define NAND_ALE_GPIO_PIN 		(0x80000000 >> 3)
#define NAND_RB_GPIO_PIN 		(0x80000000 >> 4)
/* GPIO pins used to drive NAND chip mounted on EVB */
#define NAND_EVB_nCE_GPIO_PIN 	(0x80000000 >> 14)
#define NAND_EVB_CLE_GPIO_PIN 	(0x80000000 >> 15)
#define NAND_EVB_ALE_GPIO_PIN 	(0x80000000 >> 16)
#define NAND_EVB_RB_GPIO_PIN 	(0x80000000 >> 31)

/*
 * MTD structure for PPChameleonEVB board
 */
static struct mtd_info *ppchameleon_mtd = NULL;
static struct mtd_info *ppchameleonevb_mtd = NULL;

/*
 * Module stuff
 */
static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR;
static unsigned long ppchameleonevb_fio_pbase = CFG_NAND1_PADDR;

#ifdef MODULE
module_param(ppchameleon_fio_pbase, ulong, 0);
module_param(ppchameleonevb_fio_pbase, ulong, 0);
#else
__setup("ppchameleon_fio_pbase=", ppchameleon_fio_pbase);
__setup("ppchameleonevb_fio_pbase=", ppchameleonevb_fio_pbase);
#endif

#ifdef CONFIG_MTD_PARTITIONS
/*
 * Define static partitions for flash devices
 */
static struct mtd_partition partition_info_hi[] = {
      { .name = "PPChameleon HI Nand Flash",
	.offset = 0,
	.size = 128 * 1024 * 1024
      }
};

static struct mtd_partition partition_info_me[] = {
      { .name = "PPChameleon ME Nand Flash",
	.offset = 0,
	.size = 32 * 1024 * 1024
      }
};

static struct mtd_partition partition_info_evb[] = {
      { .name = "PPChameleonEVB Nand Flash",
	.offset = 0,
	.size = 32 * 1024 * 1024
      }
};

#define NUM_PARTITIONS 1

extern int parse_cmdline_partitions(struct mtd_info *master, struct mtd_partition **pparts, const char *mtd_id);
#endif

/*
 *	hardware specific access to control-lines
 */
static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd,
				  unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;

	if (ctrl & NAND_CTRL_CHANGE) {
#error Missing headerfiles. No way to fix this. -tglx
		switch (cmd) {
		case NAND_CTL_SETCLE:
			MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR);
			break;
		case NAND_CTL_CLRCLE:
			MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR);
			break;
		case NAND_CTL_SETALE:
			MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR);
			break;
		case NAND_CTL_CLRALE:
			MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR);
			break;
		case NAND_CTL_SETNCE:
			MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR);
			break;
		case NAND_CTL_CLRNCE:
			MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR);
			break;
		}
	}
	if (cmd != NAND_CMD_NONE)
		writeb(cmd, chip->IO_ADDR_W);
}

static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd,
				     unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;

	if (ctrl & NAND_CTRL_CHANGE) {
#error Missing headerfiles. No way to fix this. -tglx
		switch (cmd) {
		case NAND_CTL_SETCLE:
			MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR);
			break;
		case NAND_CTL_CLRCLE:
			MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR);
			break;
		case NAND_CTL_SETALE:
			MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR);
			break;
		case NAND_CTL_CLRALE:
			MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR);
			break;
		case NAND_CTL_SETNCE:
			MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR);
			break;
		case NAND_CTL_CLRNCE:
			MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR);
			break;
		}
	}
	if (cmd != NAND_CMD_NONE)
		writeb(cmd, chip->IO_ADDR_W);
}

#ifdef USE_READY_BUSY_PIN
/*
 *	read device ready pin
 */
static int ppchameleon_device_ready(struct mtd_info *minfo)
{
	if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_RB_GPIO_PIN)
		return 1;
	return 0;
}

static int ppchameleonevb_device_ready(struct mtd_info *minfo)
{
	if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN)
		return 1;
	return 0;
}
#endif

#ifdef CONFIG_MTD_PARTITIONS
const char *part_probes[] = { "cmdlinepart", NULL };
const char *part_probes_evb[] = { "cmdlinepart", NULL };
#endif

/*
 * Main initialization routine
 */
static int __init ppchameleonevb_init(void)
{
	struct nand_chip *this;
	const char *part_type = 0;
	int mtd_parts_nb = 0;
	struct mtd_partition *mtd_parts = 0;
	void __iomem *ppchameleon_fio_base;
	void __iomem *ppchameleonevb_fio_base;

	/*********************************
	* Processor module NAND (if any) *
	*********************************/
	/* Allocate memory for MTD device structure and private data */
	ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
	if (!ppchameleon_mtd) {
		printk("Unable to allocate PPChameleon NAND MTD device structure.\n");
		return -ENOMEM;
	}

	/* map physical address */
	ppchameleon_fio_base = ioremap(ppchameleon_fio_pbase, SZ_4M);
	if (!ppchameleon_fio_base) {
		printk("ioremap PPChameleon NAND flash failed\n");
		kfree(ppchameleon_mtd);
		return -EIO;
	}

	/* Get pointer to private data */
	this = (struct nand_chip *)(&ppchameleon_mtd[1]);

	/* Initialize structures */
	memset(ppchameleon_mtd, 0, sizeof(struct mtd_info));
	memset(this, 0, sizeof(struct nand_chip));

	/* Link the private data with the MTD structure */
	ppchameleon_mtd->priv = this;
	ppchameleon_mtd->owner = THIS_MODULE;

	/* Initialize GPIOs */
	/* Pin mapping for NAND chip */
	/*
	   CE   GPIO_01
	   CLE  GPIO_02
	   ALE  GPIO_03
	   R/B  GPIO_04
	 */
	/* output select */
	out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xC0FFFFFF);
	/* three-state select */
	out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xC0FFFFFF);
	/* enable output driver */
	out_be32((volatile unsigned *)GPIO0_TCR,
		 in_be32((volatile unsigned *)GPIO0_TCR) | NAND_nCE_GPIO_PIN | NAND_CLE_GPIO_PIN | NAND_ALE_GPIO_PIN);
#ifdef USE_READY_BUSY_PIN
	/* three-state select */
	out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFF3FFFFF);
	/* high-impedecence */
	out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_RB_GPIO_PIN));
	/* input select */
	out_be32((volatile unsigned *)GPIO0_ISR1H,
		 (in_be32((volatile unsigned *)GPIO0_ISR1H) & 0xFF3FFFFF) | 0x00400000);
#endif

	/* insert callbacks */
	this->IO_ADDR_R = ppchameleon_fio_base;
	this->IO_ADDR_W = ppchameleon_fio_base;
	this->cmd_ctrl = ppchameleon_hwcontrol;
#ifdef USE_READY_BUSY_PIN
	this->dev_ready = ppchameleon_device_ready;
#endif
	this->chip_delay = NAND_BIG_DELAY_US;
	/* ECC mode */
	this->ecc.mode = NAND_ECC_SOFT;

	/* Scan to find existence of the device (it could not be mounted) */
	if (nand_scan(ppchameleon_mtd, 1)) {
		iounmap((void *)ppchameleon_fio_base);
		ppchameleon_fio_base = NULL;
		kfree(ppchameleon_mtd);
		goto nand_evb_init;
	}
#ifndef USE_READY_BUSY_PIN
	/* Adjust delay if necessary */
	if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
		this->chip_delay = NAND_SMALL_DELAY_US;
#endif

#ifdef CONFIG_MTD_PARTITIONS
	ppchameleon_mtd->name = "ppchameleon-nand";
	mtd_parts_nb = parse_mtd_partitions(ppchameleon_mtd, part_probes, &mtd_parts, 0);
	if (mtd_parts_nb > 0)
		part_type = "command line";
	else
		mtd_parts_nb = 0;
#endif
	if (mtd_parts_nb == 0) {
		if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
			mtd_parts = partition_info_me;
		else
			mtd_parts = partition_info_hi;
		mtd_parts_nb = NUM_PARTITIONS;
		part_type = "static";
	}

	/* Register the partitions */
	printk(KERN_NOTICE "Using %s partition definition\n", part_type);
	add_mtd_partitions(ppchameleon_mtd, mtd_parts, mtd_parts_nb);

 nand_evb_init:
	/****************************
	* EVB NAND (always present) *
	****************************/
	/* Allocate memory for MTD device structure and private data */
	ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
	if (!ppchameleonevb_mtd) {
		printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n");
		if (ppchameleon_fio_base)
			iounmap(ppchameleon_fio_base);
		return -ENOMEM;
	}

	/* map physical address */
	ppchameleonevb_fio_base = ioremap(ppchameleonevb_fio_pbase, SZ_4M);
	if (!ppchameleonevb_fio_base) {
		printk("ioremap PPChameleonEVB NAND flash failed\n");
		kfree(ppchameleonevb_mtd);
		if (ppchameleon_fio_base)
			iounmap(ppchameleon_fio_base);
		return -EIO;
	}

	/* Get pointer to private data */
	this = (struct nand_chip *)(&ppchameleonevb_mtd[1]);

	/* Initialize structures */
	memset(ppchameleonevb_mtd, 0, sizeof(struct mtd_info));
	memset(this, 0, sizeof(struct nand_chip));

	/* Link the private data with the MTD structure */
	ppchameleonevb_mtd->priv = this;

	/* Initialize GPIOs */
	/* Pin mapping for NAND chip */
	/*
	   CE   GPIO_14
	   CLE  GPIO_15
	   ALE  GPIO_16
	   R/B  GPIO_31
	 */
	/* output select */
	out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xFFFFFFF0);
	out_be32((volatile unsigned *)GPIO0_OSRL, in_be32((volatile unsigned *)GPIO0_OSRL) & 0x3FFFFFFF);
	/* three-state select */
	out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFFFFFFF0);
	out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0x3FFFFFFF);
	/* enable output driver */
	out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) | NAND_EVB_nCE_GPIO_PIN |
		 NAND_EVB_CLE_GPIO_PIN | NAND_EVB_ALE_GPIO_PIN);
#ifdef USE_READY_BUSY_PIN
	/* three-state select */
	out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0xFFFFFFFC);
	/* high-impedecence */
	out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_EVB_RB_GPIO_PIN));
	/* input select */
	out_be32((volatile unsigned *)GPIO0_ISR1L,
		 (in_be32((volatile unsigned *)GPIO0_ISR1L) & 0xFFFFFFFC) | 0x00000001);
#endif

	/* insert callbacks */
	this->IO_ADDR_R = ppchameleonevb_fio_base;
	this->IO_ADDR_W = ppchameleonevb_fio_base;
	this->cmd_ctrl = ppchameleonevb_hwcontrol;
#ifdef USE_READY_BUSY_PIN
	this->dev_ready = ppchameleonevb_device_ready;
#endif
	this->chip_delay = NAND_SMALL_DELAY_US;

	/* ECC mode */
	this->ecc.mode = NAND_ECC_SOFT;

	/* Scan to find existence of the device */
	if (nand_scan(ppchameleonevb_mtd, 1)) {
		iounmap((void *)ppchameleonevb_fio_base);
		kfree(ppchameleonevb_mtd);
		if (ppchameleon_fio_base)
			iounmap(ppchameleon_fio_base);
		return -ENXIO;
	}
#ifdef CONFIG_MTD_PARTITIONS
	ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME;
	mtd_parts_nb = parse_mtd_partitions(ppchameleonevb_mtd, part_probes_evb, &mtd_parts, 0);
	if (mtd_parts_nb > 0)
		part_type = "command line";
	else
		mtd_parts_nb = 0;
#endif
	if (mtd_parts_nb == 0) {
		mtd_parts = partition_info_evb;
		mtd_parts_nb = NUM_PARTITIONS;
		part_type = "static";
	}

	/* Register the partitions */
	printk(KERN_NOTICE "Using %s partition definition\n", part_type);
	add_mtd_partitions(ppchameleonevb_mtd, mtd_parts, mtd_parts_nb);

	/* Return happy */
	return 0;
}

module_init(ppchameleonevb_init);

/*
 * Clean up routine
 */
static void __exit ppchameleonevb_cleanup(void)
{
	struct nand_chip *this;

	/* Release resources, unregister device(s) */
	nand_release(ppchameleon_mtd);
	nand_release(ppchameleonevb_mtd);

	/* Release iomaps */
	this = (struct nand_chip *) &ppchameleon_mtd[1];
	iounmap((void *) this->IO_ADDR_R);
	this = (struct nand_chip *) &ppchameleonevb_mtd[1];
	iounmap((void *) this->IO_ADDR_R);

	/* Free the MTD device structure */
	kfree (ppchameleon_mtd);
	kfree (ppchameleonevb_mtd);
}
module_exit(ppchameleonevb_cleanup);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>");
MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/mtd/nand/ppchameleonevb.c
	3	*
	4	* Copyright (C) 2003 DAVE Srl (info@wawnet.biz)
	5	*
	6	* Derived from drivers/mtd/nand/edb7312.c
	7	*
	8	*
1da177e4 LT	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* Overview:
	14	* This is a device driver for the NAND flash devices found on the
	15	* PPChameleon/PPChameleonEVB system.
	16	* PPChameleon options (autodetected):
	17	* - BA model: no NAND
	18	* - ME model: 32MB (Samsung K9F5608U0B)
	19	* - HI model: 128MB (Samsung K9F1G08UOM)
	20	* PPChameleonEVB options:
	21	* - 32MB (Samsung K9F5608U0B)
	22	*/
	23
	24	#include <linux/init.h>
	25	#include <linux/slab.h>
	26	#include <linux/module.h>
	27	#include <linux/mtd/mtd.h>
	28	#include <linux/mtd/nand.h>
	29	#include <linux/mtd/partitions.h>
	30	#include <asm/io.h>
	31	#include <platforms/PPChameleonEVB.h>
	32
	33	#undef USE_READY_BUSY_PIN
	34	#define USE_READY_BUSY_PIN
	35	/* see datasheets (tR) */
	36	#define NAND_BIG_DELAY_US 25
	37	#define NAND_SMALL_DELAY_US 10
	38
	39	/* handy sizes */
	40	#define SZ_4M 0x00400000
	41	#define NAND_SMALL_SIZE 0x02000000
	42	#define NAND_MTD_NAME "ppchameleon-nand"
	43	#define NAND_EVB_MTD_NAME "ppchameleonevb-nand"
	44
	45	/* GPIO pins used to drive NAND chip mounted on processor module */
	46	#define NAND_nCE_GPIO_PIN (0x80000000 >> 1)
	47	#define NAND_CLE_GPIO_PIN (0x80000000 >> 2)
	48	#define NAND_ALE_GPIO_PIN (0x80000000 >> 3)
	49	#define NAND_RB_GPIO_PIN (0x80000000 >> 4)
	50	/* GPIO pins used to drive NAND chip mounted on EVB */
	51	#define NAND_EVB_nCE_GPIO_PIN (0x80000000 >> 14)
	52	#define NAND_EVB_CLE_GPIO_PIN (0x80000000 >> 15)
	53	#define NAND_EVB_ALE_GPIO_PIN (0x80000000 >> 16)
	54	#define NAND_EVB_RB_GPIO_PIN (0x80000000 >> 31)
	55
	56	/*
	57	* MTD structure for PPChameleonEVB board
	58	*/
e0c7d767	59	static struct mtd_info *ppchameleon_mtd = NULL;
1da177e4 LT	60	static struct mtd_info *ppchameleonevb_mtd = NULL;
	61
	62	/*
	63	* Module stuff
	64	*/
e0c7d767	65	static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR;
1da177e4 LT	66	static unsigned long ppchameleonevb_fio_pbase = CFG_NAND1_PADDR;
	67
	68	#ifdef MODULE
	69	module_param(ppchameleon_fio_pbase, ulong, 0);
	70	module_param(ppchameleonevb_fio_pbase, ulong, 0);
	71	#else
e0c7d767 DW	72	__setup("ppchameleon_fio_pbase=", ppchameleon_fio_pbase);
e0c7d767 DW	73	__setup("ppchameleonevb_fio_pbase=", ppchameleonevb_fio_pbase);
1da177e4 LT	74	#endif
	75
	76	#ifdef CONFIG_MTD_PARTITIONS
	77	/*
	78	* Define static partitions for flash devices
	79	*/
	80	static struct mtd_partition partition_info_hi[] = {
e0c7d767	81	{ .name = "PPChameleon HI Nand Flash",
632155e6	82	.offset = 0,
e0c7d767 DW	83	.size = 128 * 1024 * 1024
e0c7d767 DW	84	}
1da177e4 LT	85	};
	86
	87	static struct mtd_partition partition_info_me[] = {
e0c7d767 DW	88	{ .name = "PPChameleon ME Nand Flash",
	89	.offset = 0,
	90	.size = 32 * 1024 * 1024
	91	}
1da177e4 LT	92	};
	93
	94	static struct mtd_partition partition_info_evb[] = {
e0c7d767 DW	95	{ .name = "PPChameleonEVB Nand Flash",
	96	.offset = 0,
	97	.size = 32 * 1024 * 1024
	98	}
1da177e4 LT	99	};
	100
	101	#define NUM_PARTITIONS 1
	102
e0c7d767	103	extern int parse_cmdline_partitions(struct mtd_info master, struct mtd_partition pparts, const char mtd_id);
1da177e4 LT	104	#endif
1da177e4 LT	105
1da177e4 LT	106	/*
	107	* hardware specific access to control-lines
	108	*/
7abd3ef9 TG	109	static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd,
7abd3ef9 TG	110	unsigned int ctrl)
1da177e4	111	{
7abd3ef9 TG	112	struct nand_chip *chip = mtd->priv;
	113
	114	if (ctrl & NAND_CTRL_CHANGE) {
	115	#error Missing headerfiles. No way to fix this. -tglx
	116	switch (cmd) {
	117	case NAND_CTL_SETCLE:
	118	MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR);
	119	break;
	120	case NAND_CTL_CLRCLE:
	121	MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR);
	122	break;
	123	case NAND_CTL_SETALE:
	124	MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR);
	125	break;
	126	case NAND_CTL_CLRALE:
	127	MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR);
	128	break;
	129	case NAND_CTL_SETNCE:
	130	MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR);
	131	break;
	132	case NAND_CTL_CLRNCE:
	133	MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR);
	134	break;
	135	}
1da177e4	136	}
7abd3ef9 TG	137	if (cmd != NAND_CMD_NONE)
7abd3ef9 TG	138	writeb(cmd, chip->IO_ADDR_W);
1da177e4 LT	139	}
1da177e4 LT	140
7abd3ef9 TG	141	static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd,
7abd3ef9 TG	142	unsigned int ctrl)
1da177e4	143	{
7abd3ef9 TG	144	struct nand_chip *chip = mtd->priv;
	145
	146	if (ctrl & NAND_CTRL_CHANGE) {
	147	#error Missing headerfiles. No way to fix this. -tglx
	148	switch (cmd) {
	149	case NAND_CTL_SETCLE:
	150	MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR);
	151	break;
	152	case NAND_CTL_CLRCLE:
	153	MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR);
	154	break;
	155	case NAND_CTL_SETALE:
	156	MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR);
	157	break;
	158	case NAND_CTL_CLRALE:
	159	MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR);
	160	break;
	161	case NAND_CTL_SETNCE:
	162	MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR);
	163	break;
	164	case NAND_CTL_CLRNCE:
	165	MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR);
	166	break;
	167	}
1da177e4	168	}
7abd3ef9 TG	169	if (cmd != NAND_CMD_NONE)
7abd3ef9 TG	170	writeb(cmd, chip->IO_ADDR_W);
1da177e4 LT	171	}
	172
	173	#ifdef USE_READY_BUSY_PIN
	174	/*
	175	* read device ready pin
	176	*/
	177	static int ppchameleon_device_ready(struct mtd_info *minfo)
	178	{
e0c7d767	179	if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_RB_GPIO_PIN)
1da177e4 LT	180	return 1;
	181	return 0;
	182	}
	183
	184	static int ppchameleonevb_device_ready(struct mtd_info *minfo)
	185	{
e0c7d767 DW	186	if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN)
e0c7d767 DW	187	return 1;
1da177e4 LT	188	return 0;
	189	}
	190	#endif
	191
	192	#ifdef CONFIG_MTD_PARTITIONS
	193	const char *part_probes[] = { "cmdlinepart", NULL };
	194	const char *part_probes_evb[] = { "cmdlinepart", NULL };
	195	#endif
	196
	197	/*
	198	* Main initialization routine
	199	*/
e0c7d767	200	static int __init ppchameleonevb_init(void)
1da177e4 LT	201	{
	202	struct nand_chip *this;
	203	const char *part_type = 0;
	204	int mtd_parts_nb = 0;
	205	struct mtd_partition *mtd_parts = 0;
	206	void __iomem *ppchameleon_fio_base;
	207	void __iomem *ppchameleonevb_fio_base;
	208
1da177e4 LT	209	/*********************************
	210	* Processor module NAND (if any) *
	211	*********************************/
	212	/* Allocate memory for MTD device structure and private data */
e0c7d767	213	ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
1da177e4 LT	214	if (!ppchameleon_mtd) {
	215	printk("Unable to allocate PPChameleon NAND MTD device structure.\n");
	216	return -ENOMEM;
	217	}
	218
	219	/* map physical address */
	220	ppchameleon_fio_base = ioremap(ppchameleon_fio_pbase, SZ_4M);
e0c7d767	221	if (!ppchameleon_fio_base) {
1da177e4 LT	222	printk("ioremap PPChameleon NAND flash failed\n");
	223	kfree(ppchameleon_mtd);
	224	return -EIO;
	225	}
	226
	227	/* Get pointer to private data */
e0c7d767	228	this = (struct nand_chip *)(&ppchameleon_mtd[1]);
1da177e4 LT	229
1da177e4 LT	230	/* Initialize structures */
e0c7d767 DW	231	memset(ppchameleon_mtd, 0, sizeof(struct mtd_info));
e0c7d767 DW	232	memset(this, 0, sizeof(struct nand_chip));
1da177e4 LT	233
	234	/* Link the private data with the MTD structure */
	235	ppchameleon_mtd->priv = this;
552d9205	236	ppchameleon_mtd->owner = THIS_MODULE;
1da177e4	237
e0c7d767	238	/* Initialize GPIOs */
1da177e4 LT	239	/* Pin mapping for NAND chip */
1da177e4 LT	240	/*
e0c7d767 DW	241	CE GPIO_01
	242	CLE GPIO_02
	243	ALE GPIO_03
	244	R/B GPIO_04
	245	*/
1da177e4	246	/* output select */
e0c7d767	247	out_be32((volatile unsigned )GPIO0_OSRH, in_be32((volatile unsigned )GPIO0_OSRH) & 0xC0FFFFFF);
1da177e4	248	/* three-state select */
e0c7d767	249	out_be32((volatile unsigned )GPIO0_TSRH, in_be32((volatile unsigned )GPIO0_TSRH) & 0xC0FFFFFF);
1da177e4	250	/* enable output driver */
e0c7d767 DW	251	out_be32((volatile unsigned *)GPIO0_TCR,
e0c7d767 DW	252	in_be32((volatile unsigned *)GPIO0_TCR) \| NAND_nCE_GPIO_PIN \| NAND_CLE_GPIO_PIN \| NAND_ALE_GPIO_PIN);
1da177e4 LT	253	#ifdef USE_READY_BUSY_PIN
1da177e4 LT	254	/* three-state select */
e0c7d767	255	out_be32((volatile unsigned )GPIO0_TSRH, in_be32((volatile unsigned )GPIO0_TSRH) & 0xFF3FFFFF);
1da177e4	256	/* high-impedecence */
e0c7d767	257	out_be32((volatile unsigned )GPIO0_TCR, in_be32((volatile unsigned )GPIO0_TCR) & (~NAND_RB_GPIO_PIN));
1da177e4	258	/* input select */
e0c7d767 DW	259	out_be32((volatile unsigned *)GPIO0_ISR1H,
e0c7d767 DW	260	(in_be32((volatile unsigned *)GPIO0_ISR1H) & 0xFF3FFFFF) \| 0x00400000);
1da177e4 LT	261	#endif
	262
	263	/* insert callbacks */
	264	this->IO_ADDR_R = ppchameleon_fio_base;
	265	this->IO_ADDR_W = ppchameleon_fio_base;
7abd3ef9	266	this->cmd_ctrl = ppchameleon_hwcontrol;
1da177e4 LT	267	#ifdef USE_READY_BUSY_PIN
	268	this->dev_ready = ppchameleon_device_ready;
	269	#endif
	270	this->chip_delay = NAND_BIG_DELAY_US;
	271	/* ECC mode */
6dfc6d25	272	this->ecc.mode = NAND_ECC_SOFT;
1da177e4 LT	273
1da177e4 LT	274	/* Scan to find existence of the device (it could not be mounted) */
e0c7d767	275	if (nand_scan(ppchameleon_mtd, 1)) {
1da177e4	276	iounmap((void *)ppchameleon_fio_base);
25f0c659	277	ppchameleon_fio_base = NULL;
e0c7d767	278	kfree(ppchameleon_mtd);
1da177e4 LT	279	goto nand_evb_init;
1da177e4 LT	280	}
1da177e4 LT	281	#ifndef USE_READY_BUSY_PIN
	282	/* Adjust delay if necessary */
	283	if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
	284	this->chip_delay = NAND_SMALL_DELAY_US;
	285	#endif
	286
	287	#ifdef CONFIG_MTD_PARTITIONS
	288	ppchameleon_mtd->name = "ppchameleon-nand";
	289	mtd_parts_nb = parse_mtd_partitions(ppchameleon_mtd, part_probes, &mtd_parts, 0);
	290	if (mtd_parts_nb > 0)
e0c7d767	291	part_type = "command line";
1da177e4	292	else
e0c7d767	293	mtd_parts_nb = 0;
1da177e4	294	#endif
e0c7d767	295	if (mtd_parts_nb == 0) {
1da177e4 LT	296	if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
	297	mtd_parts = partition_info_me;
	298	else
	299	mtd_parts = partition_info_hi;
	300	mtd_parts_nb = NUM_PARTITIONS;
	301	part_type = "static";
	302	}
	303
	304	/* Register the partitions */
	305	printk(KERN_NOTICE "Using %s partition definition\n", part_type);
	306	add_mtd_partitions(ppchameleon_mtd, mtd_parts, mtd_parts_nb);
	307
e0c7d767	308	nand_evb_init:
1da177e4 LT	309	/****************************
	310	* EVB NAND (always present) *
	311	****************************/
	312	/* Allocate memory for MTD device structure and private data */
e0c7d767	313	ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
1da177e4 LT	314	if (!ppchameleonevb_mtd) {
1da177e4 LT	315	printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n");
25f0c659 AL	316	if (ppchameleon_fio_base)
25f0c659 AL	317	iounmap(ppchameleon_fio_base);
1da177e4 LT	318	return -ENOMEM;
	319	}
	320
	321	/* map physical address */
	322	ppchameleonevb_fio_base = ioremap(ppchameleonevb_fio_pbase, SZ_4M);
e0c7d767	323	if (!ppchameleonevb_fio_base) {
1da177e4 LT	324	printk("ioremap PPChameleonEVB NAND flash failed\n");
1da177e4 LT	325	kfree(ppchameleonevb_mtd);
25f0c659 AL	326	if (ppchameleon_fio_base)
25f0c659 AL	327	iounmap(ppchameleon_fio_base);
1da177e4 LT	328	return -EIO;
	329	}
	330
	331	/* Get pointer to private data */
e0c7d767	332	this = (struct nand_chip *)(&ppchameleonevb_mtd[1]);
1da177e4 LT	333
1da177e4 LT	334	/* Initialize structures */
e0c7d767 DW	335	memset(ppchameleonevb_mtd, 0, sizeof(struct mtd_info));
e0c7d767 DW	336	memset(this, 0, sizeof(struct nand_chip));
1da177e4 LT	337
	338	/* Link the private data with the MTD structure */
	339	ppchameleonevb_mtd->priv = this;
	340
e0c7d767	341	/* Initialize GPIOs */
1da177e4 LT	342	/* Pin mapping for NAND chip */
1da177e4 LT	343	/*
e0c7d767 DW	344	CE GPIO_14
	345	CLE GPIO_15
	346	ALE GPIO_16
	347	R/B GPIO_31
	348	*/
1da177e4	349	/* output select */
e0c7d767 DW	350	out_be32((volatile unsigned )GPIO0_OSRH, in_be32((volatile unsigned )GPIO0_OSRH) & 0xFFFFFFF0);
e0c7d767 DW	351	out_be32((volatile unsigned )GPIO0_OSRL, in_be32((volatile unsigned )GPIO0_OSRL) & 0x3FFFFFFF);
1da177e4	352	/* three-state select */
e0c7d767 DW	353	out_be32((volatile unsigned )GPIO0_TSRH, in_be32((volatile unsigned )GPIO0_TSRH) & 0xFFFFFFF0);
e0c7d767 DW	354	out_be32((volatile unsigned )GPIO0_TSRL, in_be32((volatile unsigned )GPIO0_TSRL) & 0x3FFFFFFF);
1da177e4	355	/* enable output driver */
e0c7d767	356	out_be32((volatile unsigned )GPIO0_TCR, in_be32((volatile unsigned )GPIO0_TCR) \| NAND_EVB_nCE_GPIO_PIN \|
1da177e4 LT	357	NAND_EVB_CLE_GPIO_PIN \| NAND_EVB_ALE_GPIO_PIN);
	358	#ifdef USE_READY_BUSY_PIN
	359	/* three-state select */
e0c7d767	360	out_be32((volatile unsigned )GPIO0_TSRL, in_be32((volatile unsigned )GPIO0_TSRL) & 0xFFFFFFFC);
1da177e4	361	/* high-impedecence */
e0c7d767	362	out_be32((volatile unsigned )GPIO0_TCR, in_be32((volatile unsigned )GPIO0_TCR) & (~NAND_EVB_RB_GPIO_PIN));
1da177e4	363	/* input select */
e0c7d767 DW	364	out_be32((volatile unsigned *)GPIO0_ISR1L,
e0c7d767 DW	365	(in_be32((volatile unsigned *)GPIO0_ISR1L) & 0xFFFFFFFC) \| 0x00000001);
1da177e4 LT	366	#endif
	367
	368	/* insert callbacks */
	369	this->IO_ADDR_R = ppchameleonevb_fio_base;
	370	this->IO_ADDR_W = ppchameleonevb_fio_base;
7abd3ef9	371	this->cmd_ctrl = ppchameleonevb_hwcontrol;
1da177e4 LT	372	#ifdef USE_READY_BUSY_PIN
	373	this->dev_ready = ppchameleonevb_device_ready;
	374	#endif
	375	this->chip_delay = NAND_SMALL_DELAY_US;
	376
	377	/* ECC mode */
6dfc6d25	378	this->ecc.mode = NAND_ECC_SOFT;
1da177e4 LT	379
1da177e4 LT	380	/* Scan to find existence of the device */
e0c7d767	381	if (nand_scan(ppchameleonevb_mtd, 1)) {
1da177e4	382	iounmap((void *)ppchameleonevb_fio_base);
e0c7d767	383	kfree(ppchameleonevb_mtd);
25f0c659 AL	384	if (ppchameleon_fio_base)
25f0c659 AL	385	iounmap(ppchameleon_fio_base);
1da177e4 LT	386	return -ENXIO;
1da177e4 LT	387	}
1da177e4 LT	388	#ifdef CONFIG_MTD_PARTITIONS
	389	ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME;
	390	mtd_parts_nb = parse_mtd_partitions(ppchameleonevb_mtd, part_probes_evb, &mtd_parts, 0);
	391	if (mtd_parts_nb > 0)
e0c7d767	392	part_type = "command line";
1da177e4	393	else
e0c7d767	394	mtd_parts_nb = 0;
1da177e4	395	#endif
e0c7d767	396	if (mtd_parts_nb == 0) {
1da177e4 LT	397	mtd_parts = partition_info_evb;
	398	mtd_parts_nb = NUM_PARTITIONS;
	399	part_type = "static";
	400	}
	401
	402	/* Register the partitions */
	403	printk(KERN_NOTICE "Using %s partition definition\n", part_type);
	404	add_mtd_partitions(ppchameleonevb_mtd, mtd_parts, mtd_parts_nb);
	405
	406	/* Return happy */
	407	return 0;
	408	}
e0c7d767	409
1da177e4 LT	410	module_init(ppchameleonevb_init);
	411
	412	/*
	413	* Clean up routine
	414	*/
e0c7d767	415	static void __exit ppchameleonevb_cleanup(void)
1da177e4 LT	416	{
	417	struct nand_chip *this;
	418
	419	/* Release resources, unregister device(s) */
e0c7d767 DW	420	nand_release(ppchameleon_mtd);
e0c7d767 DW	421	nand_release(ppchameleonevb_mtd);
61b03bd7	422
1da177e4 LT	423	/* Release iomaps */
1da177e4 LT	424	this = (struct nand_chip *) &ppchameleon_mtd[1];
f8343685	425	iounmap((void *) this->IO_ADDR_R);
1da177e4	426	this = (struct nand_chip *) &ppchameleonevb_mtd[1];
f8343685	427	iounmap((void *) this->IO_ADDR_R);
1da177e4 LT	428
	429	/* Free the MTD device structure */
	430	kfree (ppchameleon_mtd);
	431	kfree (ppchameleonevb_mtd);
	432	}
	433	module_exit(ppchameleonevb_cleanup);
	434
	435	MODULE_LICENSE("GPL");
	436	MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>");
	437	MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board");