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mtd: pxa3xx_nand: remove the flash info in driver structure
[deliverable/linux.git] / drivers / mtd / nand / pxa3xx_nand.c
CommitLineData
fe69af00 1/*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
a88bdbb5 12#include <linux/kernel.h>
fe69af00 13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/delay.h>
18#include <linux/clk.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
a1c06ee1
DW		 22#include <linux/io.h>
23#include <linux/irq.h>
5a0e3ad6 24#include <linux/slab.h>
fe69af00 25
afb5b5c9 26#include <mach/dma.h>
82b95ecb 27#include <plat/pxa3xx_nand.h>
fe69af00 28
29#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
30
31/* registers and bit definitions */
32#define NDCR (0x00) /* Control register */
33#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
34#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
35#define NDSR (0x14) /* Status Register */
36#define NDPCR (0x18) /* Page Count Register */
37#define NDBDR0 (0x1C) /* Bad Block Register 0 */
38#define NDBDR1 (0x20) /* Bad Block Register 1 */
39#define NDDB (0x40) /* Data Buffer */
40#define NDCB0 (0x48) /* Command Buffer0 */
41#define NDCB1 (0x4C) /* Command Buffer1 */
42#define NDCB2 (0x50) /* Command Buffer2 */
43
44#define NDCR_SPARE_EN (0x1 << 31)
45#define NDCR_ECC_EN (0x1 << 30)
46#define NDCR_DMA_EN (0x1 << 29)
47#define NDCR_ND_RUN (0x1 << 28)
48#define NDCR_DWIDTH_C (0x1 << 27)
49#define NDCR_DWIDTH_M (0x1 << 26)
50#define NDCR_PAGE_SZ (0x1 << 24)
51#define NDCR_NCSX (0x1 << 23)
52#define NDCR_ND_MODE (0x3 << 21)
53#define NDCR_NAND_MODE (0x0)
54#define NDCR_CLR_PG_CNT (0x1 << 20)
55#define NDCR_CLR_ECC (0x1 << 19)
56#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
57#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
58
59#define NDCR_RA_START (0x1 << 15)
60#define NDCR_PG_PER_BLK (0x1 << 14)
61#define NDCR_ND_ARB_EN (0x1 << 12)
62
63#define NDSR_MASK (0xfff)
64#define NDSR_RDY (0x1 << 11)
65#define NDSR_CS0_PAGED (0x1 << 10)
66#define NDSR_CS1_PAGED (0x1 << 9)
67#define NDSR_CS0_CMDD (0x1 << 8)
68#define NDSR_CS1_CMDD (0x1 << 7)
69#define NDSR_CS0_BBD (0x1 << 6)
70#define NDSR_CS1_BBD (0x1 << 5)
71#define NDSR_DBERR (0x1 << 4)
72#define NDSR_SBERR (0x1 << 3)
73#define NDSR_WRDREQ (0x1 << 2)
74#define NDSR_RDDREQ (0x1 << 1)
75#define NDSR_WRCMDREQ (0x1)
76
77#define NDCB0_AUTO_RS (0x1 << 25)
78#define NDCB0_CSEL (0x1 << 24)
79#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
80#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
81#define NDCB0_NC (0x1 << 20)
82#define NDCB0_DBC (0x1 << 19)
83#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
84#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
85#define NDCB0_CMD2_MASK (0xff << 8)
86#define NDCB0_CMD1_MASK (0xff)
87#define NDCB0_ADDR_CYC_SHIFT (16)
88
fe69af00 89/* macros for registers read/write */
90#define nand_writel(info, off, val) \
91 __raw_writel((val), (info)->mmio_base + (off))
92
93#define nand_readl(info, off) \
94 __raw_readl((info)->mmio_base + (off))
95
96/* error code and state */
97enum {
98 ERR_NONE = 0,
99 ERR_DMABUSERR = -1,
100 ERR_SENDCMD = -2,
101 ERR_DBERR = -3,
102 ERR_BBERR = -4,
223cf6c3 103 ERR_SBERR = -5,
fe69af00 104};
105
106enum {
107 STATE_READY = 0,
108 STATE_CMD_HANDLE,
109 STATE_DMA_READING,
110 STATE_DMA_WRITING,
111 STATE_DMA_DONE,
112 STATE_PIO_READING,
113 STATE_PIO_WRITING,
114};
115
fe69af00 116struct pxa3xx_nand_info {
117 struct nand_chip nand_chip;
118
119 struct platform_device *pdev;
18c81b18 120 struct pxa3xx_nand_cmdset *cmdset;
fe69af00 121
122 struct clk *clk;
123 void __iomem *mmio_base;
8638fac8 124 unsigned long mmio_phys;
fe69af00 125
126 unsigned int buf_start;
127 unsigned int buf_count;
128
129 /* DMA information */
130 int drcmr_dat;
131 int drcmr_cmd;
132
133 unsigned char *data_buff;
18c81b18 134 unsigned char *oob_buff;
fe69af00 135 dma_addr_t data_buff_phys;
136 size_t data_buff_size;
137 int data_dma_ch;
138 struct pxa_dma_desc *data_desc;
139 dma_addr_t data_desc_addr;
140
141 uint32_t reg_ndcr;
142
143 /* saved column/page_addr during CMD_SEQIN */
144 int seqin_column;
145 int seqin_page_addr;
146
147 /* relate to the command */
148 unsigned int state;
149
150 int use_ecc; /* use HW ECC ? */
151 int use_dma; /* use DMA ? */
152
18c81b18
LW		 153 unsigned int page_size; /* page size of attached chip */
154 unsigned int data_size; /* data size in FIFO */
fe69af00 155 int retcode;
156 struct completion cmd_complete;
157
158 /* generated NDCBx register values */
159 uint32_t ndcb0;
160 uint32_t ndcb1;
161 uint32_t ndcb2;
c8c17c88 162
18c81b18
LW		 163 /* timing calcuted from setting */
164 uint32_t ndtr0cs0;
165 uint32_t ndtr1cs0;
166
c8c17c88
ES		 167 /* calculated from pxa3xx_nand_flash data */
168 size_t oob_size;
169 size_t read_id_bytes;
170
171 unsigned int col_addr_cycles;
172 unsigned int row_addr_cycles;
fe69af00 173};
174
175static int use_dma = 1;
176module_param(use_dma, bool, 0444);
177MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
178
f271049e
MR		 179/*
180 * Default NAND flash controller configuration setup by the
181 * bootloader. This configuration is used only when pdata->keep_config is set
182 */
c1f82478 183static struct pxa3xx_nand_cmdset default_cmdset = {
fe69af00 184 .read1 = 0x3000,
185 .read2 = 0x0050,
186 .program = 0x1080,
187 .read_status = 0x0070,
188 .read_id = 0x0090,
189 .erase = 0xD060,
190 .reset = 0x00FF,
191 .lock = 0x002A,
192 .unlock = 0x2423,
193 .lock_status = 0x007A,
194};
195
c1f82478 196static struct pxa3xx_nand_timing timing[] = {
227a886c
LW		 197 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
198 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
199 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
200 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
d3490dfd
HZ		 201};
202
c1f82478 203static struct pxa3xx_nand_flash builtin_flash_types[] = {
227a886c
LW		 204 { 0, 0, 2048, 8, 8, 0, &default_cmdset, &timing[0] },
205 { 0x46ec, 32, 512, 16, 16, 4096, &default_cmdset, &timing[1] },
206 { 0xdaec, 64, 2048, 8, 8, 2048, &default_cmdset, &timing[1] },
207 { 0xd7ec, 128, 4096, 8, 8, 8192, &default_cmdset, &timing[1] },
208 { 0xa12c, 64, 2048, 8, 8, 1024, &default_cmdset, &timing[2] },
209 { 0xb12c, 64, 2048, 16, 16, 1024, &default_cmdset, &timing[2] },
210 { 0xdc2c, 64, 2048, 8, 8, 4096, &default_cmdset, &timing[2] },
211 { 0xcc2c, 64, 2048, 16, 16, 4096, &default_cmdset, &timing[2] },
212 { 0xba20, 64, 2048, 16, 16, 2048, &default_cmdset, &timing[3] },
d3490dfd
HZ		 213};
214
227a886c
LW		 215/* Define a default flash type setting serve as flash detecting only */
216#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
217
fe69af00 218#define NDTR0_tCH(c) (min((c), 7) << 19)
219#define NDTR0_tCS(c) (min((c), 7) << 16)
220#define NDTR0_tWH(c) (min((c), 7) << 11)
221#define NDTR0_tWP(c) (min((c), 7) << 8)
222#define NDTR0_tRH(c) (min((c), 7) << 3)
223#define NDTR0_tRP(c) (min((c), 7) << 0)
224
225#define NDTR1_tR(c) (min((c), 65535) << 16)
226#define NDTR1_tWHR(c) (min((c), 15) << 4)
227#define NDTR1_tAR(c) (min((c), 15) << 0)
228
229/* convert nano-seconds to nand flash controller clock cycles */
93b352fc 230#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
fe69af00 231
232static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
7dad482e 233 const struct pxa3xx_nand_timing *t)
fe69af00 234{
235 unsigned long nand_clk = clk_get_rate(info->clk);
236 uint32_t ndtr0, ndtr1;
237
238 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
239 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
240 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
241 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
242 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
243 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
244
245 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
246 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
247 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
248
18c81b18
LW		 249 info->ndtr0cs0 = ndtr0;
250 info->ndtr1cs0 = ndtr1;
fe69af00 251 nand_writel(info, NDTR0CS0, ndtr0);
252 nand_writel(info, NDTR1CS0, ndtr1);
253}
254
255#define WAIT_EVENT_TIMEOUT 10
256
257static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
258{
259 int timeout = WAIT_EVENT_TIMEOUT;
260 uint32_t ndsr;
261
262 while (timeout--) {
263 ndsr = nand_readl(info, NDSR) & NDSR_MASK;
264 if (ndsr & event) {
265 nand_writel(info, NDSR, ndsr);
266 return 0;
267 }
268 udelay(10);
269 }
270
271 return -ETIMEDOUT;
272}
273
18c81b18 274static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
fe69af00 275{
fe69af00 276 /* calculate data size */
18c81b18 277 switch (info->page_size) {
fe69af00 278 case 2048:
279 info->data_size = (info->use_ecc) ? 2088 : 2112;
280 break;
281 case 512:
282 info->data_size = (info->use_ecc) ? 520 : 528;
283 break;
fe69af00 284 }
18c81b18
LW		 285}
286
287static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
288 uint16_t cmd, int column, int page_addr)
289{
290 const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
291 pxa3xx_set_datasize(info);
fe69af00 292
293 /* generate values for NDCBx registers */
294 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
295 info->ndcb1 = 0;
296 info->ndcb2 = 0;
c8c17c88 297 info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
fe69af00 298
c8c17c88 299 if (info->col_addr_cycles == 2) {
fe69af00 300 /* large block, 2 cycles for column address
301 * row address starts from 3rd cycle
302 */
7f9938d0 303 info->ndcb1 |= page_addr << 16;
c8c17c88 304 if (info->row_addr_cycles == 3)
fe69af00 305 info->ndcb2 = (page_addr >> 16) & 0xff;
306 } else
307 /* small block, 1 cycles for column address
308 * row address starts from 2nd cycle
309 */
7f9938d0 310 info->ndcb1 = page_addr << 8;
fe69af00 311
312 if (cmd == cmdset->program)
313 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
314
315 return 0;
316}
317
318static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
319 uint16_t cmd, int page_addr)
320{
321 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
322 info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
323 info->ndcb1 = page_addr;
324 info->ndcb2 = 0;
325 return 0;
326}
327
328static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
329{
18c81b18 330 const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
fe69af00 331
332 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
333 info->ndcb1 = 0;
334 info->ndcb2 = 0;
335
336 if (cmd == cmdset->read_id) {
337 info->ndcb0 |= NDCB0_CMD_TYPE(3);
338 info->data_size = 8;
339 } else if (cmd == cmdset->read_status) {
340 info->ndcb0 |= NDCB0_CMD_TYPE(4);
341 info->data_size = 8;
342 } else if (cmd == cmdset->reset || cmd == cmdset->lock ||
343 cmd == cmdset->unlock) {
344 info->ndcb0 |= NDCB0_CMD_TYPE(5);
345 } else
346 return -EINVAL;
347
348 return 0;
349}
350
351static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
352{
353 uint32_t ndcr;
354
355 ndcr = nand_readl(info, NDCR);
356 nand_writel(info, NDCR, ndcr & ~int_mask);
357}
358
359static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
360{
361 uint32_t ndcr;
362
363 ndcr = nand_readl(info, NDCR);
364 nand_writel(info, NDCR, ndcr | int_mask);
365}
366
367/* NOTE: it is a must to set ND_RUN firstly, then write command buffer
368 * otherwise, it does not work
369 */
370static int write_cmd(struct pxa3xx_nand_info *info)
371{
372 uint32_t ndcr;
373
374 /* clear status bits and run */
375 nand_writel(info, NDSR, NDSR_MASK);
376
377 ndcr = info->reg_ndcr;
378
379 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
380 ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
381 ndcr |= NDCR_ND_RUN;
382
383 nand_writel(info, NDCR, ndcr);
384
385 if (wait_for_event(info, NDSR_WRCMDREQ)) {
386 printk(KERN_ERR "timed out writing command\n");
387 return -ETIMEDOUT;
388 }
389
390 nand_writel(info, NDCB0, info->ndcb0);
391 nand_writel(info, NDCB0, info->ndcb1);
392 nand_writel(info, NDCB0, info->ndcb2);
393 return 0;
394}
395
396static int handle_data_pio(struct pxa3xx_nand_info *info)
397{
398 int ret, timeout = CHIP_DELAY_TIMEOUT;
399
400 switch (info->state) {
401 case STATE_PIO_WRITING:
402 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 403 DIV_ROUND_UP(info->data_size, 4));
fe69af00 404
405 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
406
407 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
408 if (!ret) {
409 printk(KERN_ERR "program command time out\n");
410 return -1;
411 }
412 break;
413 case STATE_PIO_READING:
414 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 415 DIV_ROUND_UP(info->data_size, 4));
fe69af00 416 break;
417 default:
a1c06ee1 418 printk(KERN_ERR "%s: invalid state %d\n", __func__,
fe69af00 419 info->state);
420 return -EINVAL;
421 }
422
423 info->state = STATE_READY;
424 return 0;
425}
426
427static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
428{
429 struct pxa_dma_desc *desc = info->data_desc;
430 int dma_len = ALIGN(info->data_size, 32);
431
432 desc->ddadr = DDADR_STOP;
433 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
434
435 if (dir_out) {
436 desc->dsadr = info->data_buff_phys;
8638fac8 437 desc->dtadr = info->mmio_phys + NDDB;
fe69af00 438 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
439 } else {
440 desc->dtadr = info->data_buff_phys;
8638fac8 441 desc->dsadr = info->mmio_phys + NDDB;
fe69af00 442 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
443 }
444
445 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
446 DDADR(info->data_dma_ch) = info->data_desc_addr;
447 DCSR(info->data_dma_ch) |= DCSR_RUN;
448}
449
450static void pxa3xx_nand_data_dma_irq(int channel, void *data)
451{
452 struct pxa3xx_nand_info *info = data;
453 uint32_t dcsr;
454
455 dcsr = DCSR(channel);
456 DCSR(channel) = dcsr;
457
458 if (dcsr & DCSR_BUSERR) {
459 info->retcode = ERR_DMABUSERR;
460 complete(&info->cmd_complete);
461 }
462
463 if (info->state == STATE_DMA_WRITING) {
464 info->state = STATE_DMA_DONE;
465 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
466 } else {
467 info->state = STATE_READY;
468 complete(&info->cmd_complete);
469 }
470}
471
472static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
473{
474 struct pxa3xx_nand_info *info = devid;
475 unsigned int status;
476
477 status = nand_readl(info, NDSR);
478
223cf6c3 479 if (status & (NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR)) {
fe69af00 480 if (status & NDSR_DBERR)
481 info->retcode = ERR_DBERR;
223cf6c3
YP		 482 else if (status & NDSR_SBERR)
483 info->retcode = ERR_SBERR;
fe69af00 484
223cf6c3 485 disable_int(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
fe69af00 486
487 if (info->use_dma) {
488 info->state = STATE_DMA_READING;
489 start_data_dma(info, 0);
490 } else {
491 info->state = STATE_PIO_READING;
492 complete(&info->cmd_complete);
493 }
494 } else if (status & NDSR_WRDREQ) {
495 disable_int(info, NDSR_WRDREQ);
496 if (info->use_dma) {
497 info->state = STATE_DMA_WRITING;
498 start_data_dma(info, 1);
499 } else {
500 info->state = STATE_PIO_WRITING;
501 complete(&info->cmd_complete);
502 }
503 } else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
504 if (status & NDSR_CS0_BBD)
505 info->retcode = ERR_BBERR;
506
507 disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
508 info->state = STATE_READY;
509 complete(&info->cmd_complete);
510 }
511 nand_writel(info, NDSR, status);
512 return IRQ_HANDLED;
513}
514
515static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
516{
517 uint32_t ndcr;
518 int ret, timeout = CHIP_DELAY_TIMEOUT;
519
520 if (write_cmd(info)) {
521 info->retcode = ERR_SENDCMD;
522 goto fail_stop;
523 }
524
525 info->state = STATE_CMD_HANDLE;
526
527 enable_int(info, event);
528
529 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
530 if (!ret) {
531 printk(KERN_ERR "command execution timed out\n");
532 info->retcode = ERR_SENDCMD;
533 goto fail_stop;
534 }
535
536 if (info->use_dma == 0 && info->data_size > 0)
537 if (handle_data_pio(info))
538 goto fail_stop;
539
540 return 0;
541
542fail_stop:
543 ndcr = nand_readl(info, NDCR);
544 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
545 udelay(10);
546 return -ETIMEDOUT;
547}
548
549static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
550{
551 struct pxa3xx_nand_info *info = mtd->priv;
552 return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
553}
554
555static inline int is_buf_blank(uint8_t *buf, size_t len)
556{
557 for (; len > 0; len--)
558 if (*buf++ != 0xff)
559 return 0;
560 return 1;
561}
562
563static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
a1c06ee1 564 int column, int page_addr)
fe69af00 565{
566 struct pxa3xx_nand_info *info = mtd->priv;
18c81b18 567 const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
fe69af00 568 int ret;
569
570 info->use_dma = (use_dma) ? 1 : 0;
571 info->use_ecc = 0;
572 info->data_size = 0;
573 info->state = STATE_READY;
574
575 init_completion(&info->cmd_complete);
576
577 switch (command) {
578 case NAND_CMD_READOOB:
579 /* disable HW ECC to get all the OOB data */
580 info->buf_count = mtd->writesize + mtd->oobsize;
581 info->buf_start = mtd->writesize + column;
7ce33aff 582 memset(info->data_buff, 0xFF, info->buf_count);
fe69af00 583
584 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
585 break;
586
223cf6c3 587 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
fe69af00 588
589 /* We only are OOB, so if the data has error, does not matter */
590 if (info->retcode == ERR_DBERR)
591 info->retcode = ERR_NONE;
592 break;
593
594 case NAND_CMD_READ0:
595 info->use_ecc = 1;
596 info->retcode = ERR_NONE;
597 info->buf_start = column;
598 info->buf_count = mtd->writesize + mtd->oobsize;
599 memset(info->data_buff, 0xFF, info->buf_count);
600
601 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
602 break;
603
223cf6c3 604 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
fe69af00 605
606 if (info->retcode == ERR_DBERR) {
607 /* for blank page (all 0xff), HW will calculate its ECC as
608 * 0, which is different from the ECC information within
609 * OOB, ignore such double bit errors
610 */
611 if (is_buf_blank(info->data_buff, mtd->writesize))
612 info->retcode = ERR_NONE;
613 }
614 break;
615 case NAND_CMD_SEQIN:
616 info->buf_start = column;
617 info->buf_count = mtd->writesize + mtd->oobsize;
618 memset(info->data_buff, 0xff, info->buf_count);
619
620 /* save column/page_addr for next CMD_PAGEPROG */
621 info->seqin_column = column;
622 info->seqin_page_addr = page_addr;
623 break;
624 case NAND_CMD_PAGEPROG:
625 info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
626
627 if (prepare_read_prog_cmd(info, cmdset->program,
628 info->seqin_column, info->seqin_page_addr))
629 break;
630
631 pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
632 break;
633 case NAND_CMD_ERASE1:
634 if (prepare_erase_cmd(info, cmdset->erase, page_addr))
635 break;
636
637 pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
638 break;
639 case NAND_CMD_ERASE2:
640 break;
641 case NAND_CMD_READID:
642 case NAND_CMD_STATUS:
643 info->use_dma = 0; /* force PIO read */
644 info->buf_start = 0;
645 info->buf_count = (command == NAND_CMD_READID) ?
c8c17c88 646 info->read_id_bytes : 1;
fe69af00 647
648 if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
649 cmdset->read_id : cmdset->read_status))
650 break;
651
652 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
653 break;
654 case NAND_CMD_RESET:
655 if (prepare_other_cmd(info, cmdset->reset))
656 break;
657
658 ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
659 if (ret == 0) {
660 int timeout = 2;
661 uint32_t ndcr;
662
663 while (timeout--) {
664 if (nand_readl(info, NDSR) & NDSR_RDY)
665 break;
666 msleep(10);
667 }
668
669 ndcr = nand_readl(info, NDCR);
670 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
671 }
672 break;
673 default:
674 printk(KERN_ERR "non-supported command.\n");
675 break;
676 }
677
678 if (info->retcode == ERR_DBERR) {
679 printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
680 info->retcode = ERR_NONE;
681 }
682}
683
684static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
685{
686 struct pxa3xx_nand_info *info = mtd->priv;
687 char retval = 0xFF;
688
689 if (info->buf_start < info->buf_count)
690 /* Has just send a new command? */
691 retval = info->data_buff[info->buf_start++];
692
693 return retval;
694}
695
696static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
697{
698 struct pxa3xx_nand_info *info = mtd->priv;
699 u16 retval = 0xFFFF;
700
701 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
702 retval = *((u16 *)(info->data_buff+info->buf_start));
703 info->buf_start += 2;
704 }
705 return retval;
706}
707
708static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
709{
710 struct pxa3xx_nand_info *info = mtd->priv;
711 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
712
713 memcpy(buf, info->data_buff + info->buf_start, real_len);
714 info->buf_start += real_len;
715}
716
717static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
718 const uint8_t *buf, int len)
719{
720 struct pxa3xx_nand_info *info = mtd->priv;
721 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
722
723 memcpy(info->data_buff + info->buf_start, buf, real_len);
724 info->buf_start += real_len;
725}
726
727static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
728 const uint8_t *buf, int len)
729{
730 return 0;
731}
732
733static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
734{
735 return;
736}
737
738static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
739{
740 struct pxa3xx_nand_info *info = mtd->priv;
741
742 /* pxa3xx_nand_send_command has waited for command complete */
743 if (this->state == FL_WRITING || this->state == FL_ERASING) {
744 if (info->retcode == ERR_NONE)
745 return 0;
746 else {
747 /*
748 * any error make it return 0x01 which will tell
749 * the caller the erase and write fail
750 */
751 return 0x01;
752 }
753 }
754
755 return 0;
756}
757
758static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
759{
760 return;
761}
762
763static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
764 const uint8_t *dat, uint8_t *ecc_code)
765{
766 return 0;
767}
768
769static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
770 uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
771{
772 struct pxa3xx_nand_info *info = mtd->priv;
773 /*
774 * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
775 * consider it as a ecc error which will tell the caller the
776 * read fail We have distinguish all the errors, but the
777 * nand_read_ecc only check this function return value
223cf6c3
YP		 778 *
779 * Corrected (single-bit) errors must also be noted.
fe69af00 780 */
223cf6c3
YP		 781 if (info->retcode == ERR_SBERR)
782 return 1;
783 else if (info->retcode != ERR_NONE)
fe69af00 784 return -1;
785
786 return 0;
787}
788
789static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
790{
18c81b18 791 const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
fe69af00 792 uint32_t ndcr;
793 uint8_t id_buff[8];
794
795 if (prepare_other_cmd(info, cmdset->read_id)) {
796 printk(KERN_ERR "failed to prepare command\n");
797 return -EINVAL;
798 }
799
800 /* Send command */
801 if (write_cmd(info))
802 goto fail_timeout;
803
804 /* Wait for CMDDM(command done successfully) */
805 if (wait_for_event(info, NDSR_RDDREQ))
806 goto fail_timeout;
807
808 __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
809 *id = id_buff[0] | (id_buff[1] << 8);
810 return 0;
811
812fail_timeout:
813 ndcr = nand_readl(info, NDCR);
814 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
815 udelay(10);
816 return -ETIMEDOUT;
817}
818
819static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
c8c17c88 820 const struct pxa3xx_nand_flash *f)
fe69af00 821{
822 struct platform_device *pdev = info->pdev;
823 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
824 uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
825
826 if (f->page_size != 2048 && f->page_size != 512)
827 return -EINVAL;
828
829 if (f->flash_width != 16 && f->flash_width != 8)
830 return -EINVAL;
831
832 /* calculate flash information */
18c81b18
LW		 833 info->cmdset = f->cmdset;
834 info->page_size = f->page_size;
835 info->oob_buff = info->data_buff + f->page_size;
c8c17c88
ES		 836 info->oob_size = (f->page_size == 2048) ? 64 : 16;
837 info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
fe69af00 838
839 /* calculate addressing information */
c8c17c88 840 info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
fe69af00 841
842 if (f->num_blocks * f->page_per_block > 65536)
c8c17c88 843 info->row_addr_cycles = 3;
fe69af00 844 else
c8c17c88 845 info->row_addr_cycles = 2;
fe69af00 846
847 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
c8c17c88 848 ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
fe69af00 849 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
850 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
851 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
852 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
853
c8c17c88 854 ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
fe69af00 855 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
856
857 info->reg_ndcr = ndcr;
858
859 pxa3xx_nand_set_timing(info, f->timing);
fe69af00 860 return 0;
861}
862
f271049e
MR		 863static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
864{
865 uint32_t ndcr = nand_readl(info, NDCR);
866 struct nand_flash_dev *type = NULL;
18c81b18 867 uint32_t id = -1, page_per_block, num_blocks;
f271049e
MR		 868 int i;
869
18c81b18
LW		 870 page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
871 info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
f271049e 872 /* set info fields needed to __readid */
18c81b18 873 info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
f271049e
MR		 874 info->reg_ndcr = ndcr;
875
876 if (__readid(info, &id))
877 return -ENODEV;
878
879 /* Lookup the flash id */
880 id = (id >> 8) & 0xff; /* device id is byte 2 */
881 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
882 if (id == nand_flash_ids[i].id) {
883 type = &nand_flash_ids[i];
884 break;
885 }
886 }
887
888 if (!type)
889 return -ENODEV;
890
891 /* fill the missing flash information */
18c81b18
LW		 892 i = __ffs(page_per_block * info->page_size);
893 num_blocks = type->chipsize << (20 - i);
f271049e 894
18c81b18 895 info->oob_size = (info->page_size == 2048) ? 64 : 16;
f271049e
MR		 896
897 /* calculate addressing information */
18c81b18 898 info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;
f271049e 899
18c81b18 900 if (num_blocks * page_per_block > 65536)
f271049e
MR		 901 info->row_addr_cycles = 3;
902 else
903 info->row_addr_cycles = 2;
904
18c81b18
LW		 905 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
906 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
907 info->cmdset = &default_cmdset;
f271049e
MR		 908
909 return 0;
910}
911
c8ac3f81
ES		 912static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
913 const struct pxa3xx_nand_platform_data *pdata)
fe69af00 914{
c8c17c88 915 const struct pxa3xx_nand_flash *f;
2675e944 916 uint32_t id = -1;
fe69af00 917 int i;
918
f271049e
MR		 919 if (pdata->keep_config)
920 if (pxa3xx_nand_detect_config(info) == 0)
921 return 0;
922
227a886c
LW		 923 /* we use default timing to detect id */
924 f = DEFAULT_FLASH_TYPE;
925 pxa3xx_nand_config_flash(info, f);
926 if (__readid(info, &id))
927 goto fail_detect;
928
929 for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
930 /* we first choose the flash definition from platfrom */
931 if (i < pdata->num_flash)
932 f = pdata->flash + i;
933 else
934 f = &builtin_flash_types[i - pdata->num_flash + 1];
935 if (f->chip_id == id) {
936 dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
937 pxa3xx_nand_config_flash(info, f);
fe69af00 938 return 0;
227a886c 939 }
fe69af00 940 }
941
2675e944
ES		 942 dev_warn(&info->pdev->dev,
943 "failed to detect configured nand flash; found %04x instead of\n",
944 id);
227a886c 945fail_detect:
fe69af00 946 return -ENODEV;
947}
948
949/* the maximum possible buffer size for large page with OOB data
950 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
951 * data buffer and the DMA descriptor
952 */
953#define MAX_BUFF_SIZE PAGE_SIZE
954
955static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
956{
957 struct platform_device *pdev = info->pdev;
958 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
959
960 if (use_dma == 0) {
961 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
962 if (info->data_buff == NULL)
963 return -ENOMEM;
964 return 0;
965 }
966
967 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
968 &info->data_buff_phys, GFP_KERNEL);
969 if (info->data_buff == NULL) {
970 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
971 return -ENOMEM;
972 }
973
974 info->data_buff_size = MAX_BUFF_SIZE;
975 info->data_desc = (void *)info->data_buff + data_desc_offset;
976 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
977
978 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
979 pxa3xx_nand_data_dma_irq, info);
980 if (info->data_dma_ch < 0) {
981 dev_err(&pdev->dev, "failed to request data dma\n");
982 dma_free_coherent(&pdev->dev, info->data_buff_size,
983 info->data_buff, info->data_buff_phys);
984 return info->data_dma_ch;
985 }
986
987 return 0;
988}
989
990static struct nand_ecclayout hw_smallpage_ecclayout = {
991 .eccbytes = 6,
992 .eccpos = {8, 9, 10, 11, 12, 13 },
993 .oobfree = { {2, 6} }
994};
995
996static struct nand_ecclayout hw_largepage_ecclayout = {
997 .eccbytes = 24,
998 .eccpos = {
999 40, 41, 42, 43, 44, 45, 46, 47,
1000 48, 49, 50, 51, 52, 53, 54, 55,
1001 56, 57, 58, 59, 60, 61, 62, 63},
1002 .oobfree = { {2, 38} }
1003};
1004
1005static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
1006 struct pxa3xx_nand_info *info)
1007{
fe69af00 1008 struct nand_chip *this = &info->nand_chip;
1009
18c81b18 1010 this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
fe69af00 1011
1012 this->waitfunc = pxa3xx_nand_waitfunc;
1013 this->select_chip = pxa3xx_nand_select_chip;
1014 this->dev_ready = pxa3xx_nand_dev_ready;
1015 this->cmdfunc = pxa3xx_nand_cmdfunc;
1016 this->read_word = pxa3xx_nand_read_word;
1017 this->read_byte = pxa3xx_nand_read_byte;
1018 this->read_buf = pxa3xx_nand_read_buf;
1019 this->write_buf = pxa3xx_nand_write_buf;
1020 this->verify_buf = pxa3xx_nand_verify_buf;
1021
1022 this->ecc.mode = NAND_ECC_HW;
1023 this->ecc.hwctl = pxa3xx_nand_ecc_hwctl;
1024 this->ecc.calculate = pxa3xx_nand_ecc_calculate;
1025 this->ecc.correct = pxa3xx_nand_ecc_correct;
18c81b18 1026 this->ecc.size = info->page_size;
fe69af00 1027
18c81b18 1028 if (info->page_size == 2048)
fe69af00 1029 this->ecc.layout = &hw_largepage_ecclayout;
1030 else
1031 this->ecc.layout = &hw_smallpage_ecclayout;
1032
a1c06ee1 1033 this->chip_delay = 25;
fe69af00 1034}
1035
1036static int pxa3xx_nand_probe(struct platform_device *pdev)
1037{
1038 struct pxa3xx_nand_platform_data *pdata;
1039 struct pxa3xx_nand_info *info;
1040 struct nand_chip *this;
1041 struct mtd_info *mtd;
1042 struct resource *r;
1043 int ret = 0, irq;
1044
1045 pdata = pdev->dev.platform_data;
1046
a1c06ee1 1047 if (!pdata) {
fe69af00 1048 dev_err(&pdev->dev, "no platform data defined\n");
1049 return -ENODEV;
1050 }
1051
1052 mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1053 GFP_KERNEL);
a1c06ee1 1054 if (!mtd) {
fe69af00 1055 dev_err(&pdev->dev, "failed to allocate memory\n");
1056 return -ENOMEM;
a1c06ee1 1057 }
fe69af00 1058
1059 info = (struct pxa3xx_nand_info *)(&mtd[1]);
1060 info->pdev = pdev;
1061
1062 this = &info->nand_chip;
1063 mtd->priv = info;
82a72d10 1064 mtd->owner = THIS_MODULE;
fe69af00 1065
e0d8b13a 1066 info->clk = clk_get(&pdev->dev, NULL);
fe69af00 1067 if (IS_ERR(info->clk)) {
1068 dev_err(&pdev->dev, "failed to get nand clock\n");
1069 ret = PTR_ERR(info->clk);
1070 goto fail_free_mtd;
1071 }
1072 clk_enable(info->clk);
1073
1074 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1075 if (r == NULL) {
1076 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1077 ret = -ENXIO;
1078 goto fail_put_clk;
1079 }
1080 info->drcmr_dat = r->start;
1081
1082 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1083 if (r == NULL) {
1084 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1085 ret = -ENXIO;
1086 goto fail_put_clk;
1087 }
1088 info->drcmr_cmd = r->start;
1089
1090 irq = platform_get_irq(pdev, 0);
1091 if (irq < 0) {
1092 dev_err(&pdev->dev, "no IRQ resource defined\n");
1093 ret = -ENXIO;
1094 goto fail_put_clk;
1095 }
1096
1097 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1098 if (r == NULL) {
1099 dev_err(&pdev->dev, "no IO memory resource defined\n");
1100 ret = -ENODEV;
1101 goto fail_put_clk;
1102 }
1103
b2ed3680 1104 r = request_mem_region(r->start, resource_size(r), pdev->name);
fe69af00 1105 if (r == NULL) {
1106 dev_err(&pdev->dev, "failed to request memory resource\n");
1107 ret = -EBUSY;
1108 goto fail_put_clk;
1109 }
1110
b2ed3680 1111 info->mmio_base = ioremap(r->start, resource_size(r));
fe69af00 1112 if (info->mmio_base == NULL) {
1113 dev_err(&pdev->dev, "ioremap() failed\n");
1114 ret = -ENODEV;
1115 goto fail_free_res;
1116 }
8638fac8 1117 info->mmio_phys = r->start;
fe69af00 1118
1119 ret = pxa3xx_nand_init_buff(info);
1120 if (ret)
1121 goto fail_free_io;
1122
346e1259
HZ		 1123 /* initialize all interrupts to be disabled */
1124 disable_int(info, NDSR_MASK);
1125
dbf5986a
HZ		 1126 ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1127 pdev->name, info);
fe69af00 1128 if (ret < 0) {
1129 dev_err(&pdev->dev, "failed to request IRQ\n");
1130 goto fail_free_buf;
1131 }
1132
c8ac3f81 1133 ret = pxa3xx_nand_detect_flash(info, pdata);
fe69af00 1134 if (ret) {
1135 dev_err(&pdev->dev, "failed to detect flash\n");
1136 ret = -ENODEV;
1137 goto fail_free_irq;
1138 }
1139
1140 pxa3xx_nand_init_mtd(mtd, info);
1141
1142 platform_set_drvdata(pdev, mtd);
1143
1144 if (nand_scan(mtd, 1)) {
1145 dev_err(&pdev->dev, "failed to scan nand\n");
1146 ret = -ENXIO;
1147 goto fail_free_irq;
1148 }
1149
99d38964 1150#ifdef CONFIG_MTD_PARTITIONS
bff3c10d
MKB		 1151 if (mtd_has_cmdlinepart()) {
1152 static const char *probes[] = { "cmdlinepart", NULL };
1153 struct mtd_partition *parts;
1154 int nr_parts;
1155
1156 nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
1157
1158 if (nr_parts)
1159 return add_mtd_partitions(mtd, parts, nr_parts);
1160 }
1161
fe69af00 1162 return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
99d38964
MB		 1163#else
1164 return 0;
1165#endif
fe69af00 1166
1167fail_free_irq:
dbf5986a 1168 free_irq(irq, info);
fe69af00 1169fail_free_buf:
1170 if (use_dma) {
1171 pxa_free_dma(info->data_dma_ch);
1172 dma_free_coherent(&pdev->dev, info->data_buff_size,
1173 info->data_buff, info->data_buff_phys);
1174 } else
1175 kfree(info->data_buff);
1176fail_free_io:
1177 iounmap(info->mmio_base);
1178fail_free_res:
b2ed3680 1179 release_mem_region(r->start, resource_size(r));
fe69af00 1180fail_put_clk:
1181 clk_disable(info->clk);
1182 clk_put(info->clk);
1183fail_free_mtd:
1184 kfree(mtd);
1185 return ret;
1186}
1187
1188static int pxa3xx_nand_remove(struct platform_device *pdev)
1189{
1190 struct mtd_info *mtd = platform_get_drvdata(pdev);
1191 struct pxa3xx_nand_info *info = mtd->priv;
82a72d10 1192 struct resource *r;
dbf5986a 1193 int irq;
fe69af00 1194
1195 platform_set_drvdata(pdev, NULL);
1196
1197 del_mtd_device(mtd);
99d38964 1198#ifdef CONFIG_MTD_PARTITIONS
fe69af00 1199 del_mtd_partitions(mtd);
99d38964 1200#endif
dbf5986a
HZ		 1201 irq = platform_get_irq(pdev, 0);
1202 if (irq >= 0)
1203 free_irq(irq, info);
fe69af00 1204 if (use_dma) {
1205 pxa_free_dma(info->data_dma_ch);
1206 dma_free_writecombine(&pdev->dev, info->data_buff_size,
1207 info->data_buff, info->data_buff_phys);
1208 } else
1209 kfree(info->data_buff);
82a72d10
MR		 1210
1211 iounmap(info->mmio_base);
1212 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1213 release_mem_region(r->start, resource_size(r));
1214
1215 clk_disable(info->clk);
1216 clk_put(info->clk);
1217
fe69af00 1218 kfree(mtd);
1219 return 0;
1220}
1221
1222#ifdef CONFIG_PM
1223static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1224{
1225 struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1226 struct pxa3xx_nand_info *info = mtd->priv;
1227
1228 if (info->state != STATE_READY) {
1229 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1230 return -EAGAIN;
1231 }
1232
1233 return 0;
1234}
1235
1236static int pxa3xx_nand_resume(struct platform_device *pdev)
1237{
1238 struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1239 struct pxa3xx_nand_info *info = mtd->priv;
1240
18c81b18
LW		 1241 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1242 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
fe69af00 1243 clk_enable(info->clk);
1244
18c81b18 1245 return 0;
fe69af00 1246}
1247#else
1248#define pxa3xx_nand_suspend NULL
1249#define pxa3xx_nand_resume NULL
1250#endif
1251
1252static struct platform_driver pxa3xx_nand_driver = {
1253 .driver = {
1254 .name = "pxa3xx-nand",
1255 },
1256 .probe = pxa3xx_nand_probe,
1257 .remove = pxa3xx_nand_remove,
1258 .suspend = pxa3xx_nand_suspend,
1259 .resume = pxa3xx_nand_resume,
1260};
1261
1262static int __init pxa3xx_nand_init(void)
1263{
1264 return platform_driver_register(&pxa3xx_nand_driver);
1265}
1266module_init(pxa3xx_nand_init);
1267
1268static void __exit pxa3xx_nand_exit(void)
1269{
1270 platform_driver_unregister(&pxa3xx_nand_driver);
1271}
1272module_exit(pxa3xx_nand_exit);
1273
1274MODULE_LICENSE("GPL");
1275MODULE_DESCRIPTION("PXA3xx NAND controller driver");
Linux kernel - Deliverables
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