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mtd: nand: use dev_get_platdata()
[deliverable/linux.git] / drivers / mtd / nand / pxa3xx_nand.c
CommitLineData
fe69af00 1/*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
a88bdbb5 12#include <linux/kernel.h>
fe69af00 13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/delay.h>
18#include <linux/clk.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
a1c06ee1
DW		 22#include <linux/io.h>
23#include <linux/irq.h>
5a0e3ad6 24#include <linux/slab.h>
1e7ba630
DM		 25#include <linux/of.h>
26#include <linux/of_device.h>
fe69af00 27
afb5b5c9 28#include <mach/dma.h>
293b2da1 29#include <linux/platform_data/mtd-nand-pxa3xx.h>
fe69af00 30
31#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
f8155a40 32#define NAND_STOP_DELAY (2 * HZ/50)
4eb2da89 33#define PAGE_CHUNK_SIZE (2048)
fe69af00 34
35/* registers and bit definitions */
36#define NDCR (0x00) /* Control register */
37#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
38#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
39#define NDSR (0x14) /* Status Register */
40#define NDPCR (0x18) /* Page Count Register */
41#define NDBDR0 (0x1C) /* Bad Block Register 0 */
42#define NDBDR1 (0x20) /* Bad Block Register 1 */
43#define NDDB (0x40) /* Data Buffer */
44#define NDCB0 (0x48) /* Command Buffer0 */
45#define NDCB1 (0x4C) /* Command Buffer1 */
46#define NDCB2 (0x50) /* Command Buffer2 */
47
48#define NDCR_SPARE_EN (0x1 << 31)
49#define NDCR_ECC_EN (0x1 << 30)
50#define NDCR_DMA_EN (0x1 << 29)
51#define NDCR_ND_RUN (0x1 << 28)
52#define NDCR_DWIDTH_C (0x1 << 27)
53#define NDCR_DWIDTH_M (0x1 << 26)
54#define NDCR_PAGE_SZ (0x1 << 24)
55#define NDCR_NCSX (0x1 << 23)
56#define NDCR_ND_MODE (0x3 << 21)
57#define NDCR_NAND_MODE (0x0)
58#define NDCR_CLR_PG_CNT (0x1 << 20)
f8155a40 59#define NDCR_STOP_ON_UNCOR (0x1 << 19)
fe69af00 60#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
61#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
62
63#define NDCR_RA_START (0x1 << 15)
64#define NDCR_PG_PER_BLK (0x1 << 14)
65#define NDCR_ND_ARB_EN (0x1 << 12)
f8155a40 66#define NDCR_INT_MASK (0xFFF)
fe69af00 67
68#define NDSR_MASK (0xfff)
f8155a40
LW		 69#define NDSR_RDY (0x1 << 12)
70#define NDSR_FLASH_RDY (0x1 << 11)
fe69af00 71#define NDSR_CS0_PAGED (0x1 << 10)
72#define NDSR_CS1_PAGED (0x1 << 9)
73#define NDSR_CS0_CMDD (0x1 << 8)
74#define NDSR_CS1_CMDD (0x1 << 7)
75#define NDSR_CS0_BBD (0x1 << 6)
76#define NDSR_CS1_BBD (0x1 << 5)
77#define NDSR_DBERR (0x1 << 4)
78#define NDSR_SBERR (0x1 << 3)
79#define NDSR_WRDREQ (0x1 << 2)
80#define NDSR_RDDREQ (0x1 << 1)
81#define NDSR_WRCMDREQ (0x1)
82
4eb2da89 83#define NDCB0_ST_ROW_EN (0x1 << 26)
fe69af00 84#define NDCB0_AUTO_RS (0x1 << 25)
85#define NDCB0_CSEL (0x1 << 24)
86#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
87#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
88#define NDCB0_NC (0x1 << 20)
89#define NDCB0_DBC (0x1 << 19)
90#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
91#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
92#define NDCB0_CMD2_MASK (0xff << 8)
93#define NDCB0_CMD1_MASK (0xff)
94#define NDCB0_ADDR_CYC_SHIFT (16)
95
fe69af00 96/* macros for registers read/write */
97#define nand_writel(info, off, val) \
98 __raw_writel((val), (info)->mmio_base + (off))
99
100#define nand_readl(info, off) \
101 __raw_readl((info)->mmio_base + (off))
102
103/* error code and state */
104enum {
105 ERR_NONE = 0,
106 ERR_DMABUSERR = -1,
107 ERR_SENDCMD = -2,
108 ERR_DBERR = -3,
109 ERR_BBERR = -4,
223cf6c3 110 ERR_SBERR = -5,
fe69af00 111};
112
113enum {
f8155a40 114 STATE_IDLE = 0,
d456882b 115 STATE_PREPARED,
fe69af00 116 STATE_CMD_HANDLE,
117 STATE_DMA_READING,
118 STATE_DMA_WRITING,
119 STATE_DMA_DONE,
120 STATE_PIO_READING,
121 STATE_PIO_WRITING,
f8155a40
LW		 122 STATE_CMD_DONE,
123 STATE_READY,
fe69af00 124};
125
d456882b
LW		 126struct pxa3xx_nand_host {
127 struct nand_chip chip;
128 struct pxa3xx_nand_cmdset *cmdset;
129 struct mtd_info *mtd;
130 void *info_data;
131
132 /* page size of attached chip */
133 unsigned int page_size;
134 int use_ecc;
f3c8cfc2 135 int cs;
fe69af00 136
d456882b
LW		 137 /* calculated from pxa3xx_nand_flash data */
138 unsigned int col_addr_cycles;
139 unsigned int row_addr_cycles;
140 size_t read_id_bytes;
141
142 /* cached register value */
143 uint32_t reg_ndcr;
144 uint32_t ndtr0cs0;
145 uint32_t ndtr1cs0;
146};
147
148struct pxa3xx_nand_info {
401e67e2 149 struct nand_hw_control controller;
fe69af00 150 struct platform_device *pdev;
fe69af00 151
152 struct clk *clk;
153 void __iomem *mmio_base;
8638fac8 154 unsigned long mmio_phys;
d456882b 155 struct completion cmd_complete;
fe69af00 156
157 unsigned int buf_start;
158 unsigned int buf_count;
159
160 /* DMA information */
161 int drcmr_dat;
162 int drcmr_cmd;
163
164 unsigned char *data_buff;
18c81b18 165 unsigned char *oob_buff;
fe69af00 166 dma_addr_t data_buff_phys;
fe69af00 167 int data_dma_ch;
168 struct pxa_dma_desc *data_desc;
169 dma_addr_t data_desc_addr;
170
f3c8cfc2 171 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
fe69af00 172 unsigned int state;
173
f3c8cfc2 174 int cs;
fe69af00 175 int use_ecc; /* use HW ECC ? */
176 int use_dma; /* use DMA ? */
401e67e2 177 int is_ready;
fe69af00 178
18c81b18
LW		 179 unsigned int page_size; /* page size of attached chip */
180 unsigned int data_size; /* data size in FIFO */
d456882b 181 unsigned int oob_size;
fe69af00 182 int retcode;
fe69af00 183
184 /* generated NDCBx register values */
185 uint32_t ndcb0;
186 uint32_t ndcb1;
187 uint32_t ndcb2;
188};
189
90ab5ee9 190static bool use_dma = 1;
fe69af00 191module_param(use_dma, bool, 0444);
25985edc 192MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
fe69af00 193
f271049e
MR		 194/*
195 * Default NAND flash controller configuration setup by the
196 * bootloader. This configuration is used only when pdata->keep_config is set
197 */
c1f82478 198static struct pxa3xx_nand_cmdset default_cmdset = {
fe69af00 199 .read1 = 0x3000,
200 .read2 = 0x0050,
201 .program = 0x1080,
202 .read_status = 0x0070,
203 .read_id = 0x0090,
204 .erase = 0xD060,
205 .reset = 0x00FF,
206 .lock = 0x002A,
207 .unlock = 0x2423,
208 .lock_status = 0x007A,
209};
210
c1f82478 211static struct pxa3xx_nand_timing timing[] = {
227a886c
LW		 212 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
213 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
214 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
215 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
d3490dfd
HZ		 216};
217
c1f82478 218static struct pxa3xx_nand_flash builtin_flash_types[] = {
4332c116
LW		 219{ "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
220{ "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
221{ "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
222{ "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
223{ "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
224{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
225{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
226{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
227{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
d3490dfd
HZ		 228};
229
227a886c
LW		 230/* Define a default flash type setting serve as flash detecting only */
231#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
232
f3c8cfc2 233const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
401e67e2 234
fe69af00 235#define NDTR0_tCH(c) (min((c), 7) << 19)
236#define NDTR0_tCS(c) (min((c), 7) << 16)
237#define NDTR0_tWH(c) (min((c), 7) << 11)
238#define NDTR0_tWP(c) (min((c), 7) << 8)
239#define NDTR0_tRH(c) (min((c), 7) << 3)
240#define NDTR0_tRP(c) (min((c), 7) << 0)
241
242#define NDTR1_tR(c) (min((c), 65535) << 16)
243#define NDTR1_tWHR(c) (min((c), 15) << 4)
244#define NDTR1_tAR(c) (min((c), 15) << 0)
245
246/* convert nano-seconds to nand flash controller clock cycles */
93b352fc 247#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
fe69af00 248
d456882b 249static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
7dad482e 250 const struct pxa3xx_nand_timing *t)
fe69af00 251{
d456882b 252 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 253 unsigned long nand_clk = clk_get_rate(info->clk);
254 uint32_t ndtr0, ndtr1;
255
256 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
257 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
258 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
259 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
260 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
261 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
262
263 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
264 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
265 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
266
d456882b
LW		 267 host->ndtr0cs0 = ndtr0;
268 host->ndtr1cs0 = ndtr1;
fe69af00 269 nand_writel(info, NDTR0CS0, ndtr0);
270 nand_writel(info, NDTR1CS0, ndtr1);
271}
272
18c81b18 273static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
fe69af00 274{
f3c8cfc2 275 struct pxa3xx_nand_host *host = info->host[info->cs];
d456882b 276 int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
9d8b1043 277
d456882b 278 info->data_size = host->page_size;
9d8b1043
LW		 279 if (!oob_enable) {
280 info->oob_size = 0;
281 return;
282 }
283
d456882b 284 switch (host->page_size) {
fe69af00 285 case 2048:
9d8b1043 286 info->oob_size = (info->use_ecc) ? 40 : 64;
fe69af00 287 break;
288 case 512:
9d8b1043 289 info->oob_size = (info->use_ecc) ? 8 : 16;
fe69af00 290 break;
fe69af00 291 }
18c81b18
LW		 292}
293
f8155a40
LW		 294/**
295 * NOTE: it is a must to set ND_RUN firstly, then write
296 * command buffer, otherwise, it does not work.
297 * We enable all the interrupt at the same time, and
298 * let pxa3xx_nand_irq to handle all logic.
299 */
300static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
301{
f3c8cfc2 302 struct pxa3xx_nand_host *host = info->host[info->cs];
f8155a40
LW		 303 uint32_t ndcr;
304
d456882b 305 ndcr = host->reg_ndcr;
f8155a40
LW		 306 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
307 ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
308 ndcr |= NDCR_ND_RUN;
309
310 /* clear status bits and run */
311 nand_writel(info, NDCR, 0);
312 nand_writel(info, NDSR, NDSR_MASK);
313 nand_writel(info, NDCR, ndcr);
314}
315
316static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
317{
318 uint32_t ndcr;
319 int timeout = NAND_STOP_DELAY;
320
321 /* wait RUN bit in NDCR become 0 */
322 ndcr = nand_readl(info, NDCR);
323 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
324 ndcr = nand_readl(info, NDCR);
325 udelay(1);
326 }
327
328 if (timeout <= 0) {
329 ndcr &= ~NDCR_ND_RUN;
330 nand_writel(info, NDCR, ndcr);
331 }
332 /* clear status bits */
333 nand_writel(info, NDSR, NDSR_MASK);
334}
335
fe69af00 336static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
337{
338 uint32_t ndcr;
339
340 ndcr = nand_readl(info, NDCR);
341 nand_writel(info, NDCR, ndcr & ~int_mask);
342}
343
344static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
345{
346 uint32_t ndcr;
347
348 ndcr = nand_readl(info, NDCR);
349 nand_writel(info, NDCR, ndcr | int_mask);
350}
351
f8155a40 352static void handle_data_pio(struct pxa3xx_nand_info *info)
fe69af00 353{
fe69af00 354 switch (info->state) {
355 case STATE_PIO_WRITING:
356 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 357 DIV_ROUND_UP(info->data_size, 4));
9d8b1043
LW		 358 if (info->oob_size > 0)
359 __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
360 DIV_ROUND_UP(info->oob_size, 4));
fe69af00 361 break;
362 case STATE_PIO_READING:
363 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 364 DIV_ROUND_UP(info->data_size, 4));
9d8b1043
LW		 365 if (info->oob_size > 0)
366 __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
367 DIV_ROUND_UP(info->oob_size, 4));
fe69af00 368 break;
369 default:
da675b4e 370 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
fe69af00 371 info->state);
f8155a40 372 BUG();
fe69af00 373 }
fe69af00 374}
375
f8155a40 376static void start_data_dma(struct pxa3xx_nand_info *info)
fe69af00 377{
378 struct pxa_dma_desc *desc = info->data_desc;
9d8b1043 379 int dma_len = ALIGN(info->data_size + info->oob_size, 32);
fe69af00 380
381 desc->ddadr = DDADR_STOP;
382 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
383
f8155a40
LW		 384 switch (info->state) {
385 case STATE_DMA_WRITING:
fe69af00 386 desc->dsadr = info->data_buff_phys;
8638fac8 387 desc->dtadr = info->mmio_phys + NDDB;
fe69af00 388 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
f8155a40
LW		 389 break;
390 case STATE_DMA_READING:
fe69af00 391 desc->dtadr = info->data_buff_phys;
8638fac8 392 desc->dsadr = info->mmio_phys + NDDB;
fe69af00 393 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
f8155a40
LW		 394 break;
395 default:
da675b4e 396 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
f8155a40
LW		 397 info->state);
398 BUG();
fe69af00 399 }
400
401 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
402 DDADR(info->data_dma_ch) = info->data_desc_addr;
403 DCSR(info->data_dma_ch) |= DCSR_RUN;
404}
405
406static void pxa3xx_nand_data_dma_irq(int channel, void *data)
407{
408 struct pxa3xx_nand_info *info = data;
409 uint32_t dcsr;
410
411 dcsr = DCSR(channel);
412 DCSR(channel) = dcsr;
413
414 if (dcsr & DCSR_BUSERR) {
415 info->retcode = ERR_DMABUSERR;
fe69af00 416 }
417
f8155a40
LW		 418 info->state = STATE_DMA_DONE;
419 enable_int(info, NDCR_INT_MASK);
420 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
fe69af00 421}
422
423static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
424{
425 struct pxa3xx_nand_info *info = devid;
f8155a40 426 unsigned int status, is_completed = 0;
f3c8cfc2
LW		 427 unsigned int ready, cmd_done;
428
429 if (info->cs == 0) {
430 ready = NDSR_FLASH_RDY;
431 cmd_done = NDSR_CS0_CMDD;
432 } else {
433 ready = NDSR_RDY;
434 cmd_done = NDSR_CS1_CMDD;
435 }
fe69af00 436
437 status = nand_readl(info, NDSR);
438
f8155a40
LW		 439 if (status & NDSR_DBERR)
440 info->retcode = ERR_DBERR;
441 if (status & NDSR_SBERR)
442 info->retcode = ERR_SBERR;
443 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
444 /* whether use dma to transfer data */
fe69af00 445 if (info->use_dma) {
f8155a40
LW		 446 disable_int(info, NDCR_INT_MASK);
447 info->state = (status & NDSR_RDDREQ) ?
448 STATE_DMA_READING : STATE_DMA_WRITING;
449 start_data_dma(info);
450 goto NORMAL_IRQ_EXIT;
fe69af00 451 } else {
f8155a40
LW		 452 info->state = (status & NDSR_RDDREQ) ?
453 STATE_PIO_READING : STATE_PIO_WRITING;
454 handle_data_pio(info);
fe69af00 455 }
fe69af00 456 }
f3c8cfc2 457 if (status & cmd_done) {
f8155a40
LW		 458 info->state = STATE_CMD_DONE;
459 is_completed = 1;
fe69af00 460 }
f3c8cfc2 461 if (status & ready) {
401e67e2 462 info->is_ready = 1;
f8155a40 463 info->state = STATE_READY;
401e67e2 464 }
fe69af00 465
f8155a40
LW		 466 if (status & NDSR_WRCMDREQ) {
467 nand_writel(info, NDSR, NDSR_WRCMDREQ);
468 status &= ~NDSR_WRCMDREQ;
469 info->state = STATE_CMD_HANDLE;
470 nand_writel(info, NDCB0, info->ndcb0);
471 nand_writel(info, NDCB0, info->ndcb1);
472 nand_writel(info, NDCB0, info->ndcb2);
fe69af00 473 }
474
f8155a40
LW		 475 /* clear NDSR to let the controller exit the IRQ */
476 nand_writel(info, NDSR, status);
477 if (is_completed)
478 complete(&info->cmd_complete);
479NORMAL_IRQ_EXIT:
480 return IRQ_HANDLED;
fe69af00 481}
482
fe69af00 483static inline int is_buf_blank(uint8_t *buf, size_t len)
484{
485 for (; len > 0; len--)
486 if (*buf++ != 0xff)
487 return 0;
488 return 1;
489}
490
4eb2da89
LW		 491static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
492 uint16_t column, int page_addr)
fe69af00 493{
4eb2da89 494 uint16_t cmd;
d456882b 495 int addr_cycle, exec_cmd;
f3c8cfc2
LW		 496 struct pxa3xx_nand_host *host;
497 struct mtd_info *mtd;
fe69af00 498
f3c8cfc2
LW		 499 host = info->host[info->cs];
500 mtd = host->mtd;
4eb2da89
LW		 501 addr_cycle = 0;
502 exec_cmd = 1;
503
504 /* reset data and oob column point to handle data */
401e67e2
LW		 505 info->buf_start = 0;
506 info->buf_count = 0;
4eb2da89
LW		 507 info->oob_size = 0;
508 info->use_ecc = 0;
0a60d049 509 info->use_dma = (use_dma) ? 1 : 0;
401e67e2 510 info->is_ready = 0;
4eb2da89 511 info->retcode = ERR_NONE;
f3c8cfc2
LW		 512 if (info->cs != 0)
513 info->ndcb0 = NDCB0_CSEL;
514 else
515 info->ndcb0 = 0;
fe69af00 516
517 switch (command) {
4eb2da89
LW		 518 case NAND_CMD_READ0:
519 case NAND_CMD_PAGEPROG:
520 info->use_ecc = 1;
fe69af00 521 case NAND_CMD_READOOB:
4eb2da89 522 pxa3xx_set_datasize(info);
fe69af00 523 break;
4eb2da89
LW		 524 case NAND_CMD_SEQIN:
525 exec_cmd = 0;
526 break;
527 default:
528 info->ndcb1 = 0;
529 info->ndcb2 = 0;
530 break;
531 }
532
d456882b
LW		 533 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
534 + host->col_addr_cycles);
fe69af00 535
4eb2da89
LW		 536 switch (command) {
537 case NAND_CMD_READOOB:
fe69af00 538 case NAND_CMD_READ0:
d456882b 539 cmd = host->cmdset->read1;
4eb2da89
LW		 540 if (command == NAND_CMD_READOOB)
541 info->buf_start = mtd->writesize + column;
542 else
543 info->buf_start = column;
544
d456882b 545 if (unlikely(host->page_size < PAGE_CHUNK_SIZE))
4eb2da89
LW		 546 info->ndcb0 |= NDCB0_CMD_TYPE(0)
547 | addr_cycle
548 | (cmd & NDCB0_CMD1_MASK);
549 else
550 info->ndcb0 |= NDCB0_CMD_TYPE(0)
551 | NDCB0_DBC
552 | addr_cycle
553 | cmd;
fe69af00 554
fe69af00 555 case NAND_CMD_SEQIN:
4eb2da89 556 /* small page addr setting */
d456882b 557 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
4eb2da89
LW		 558 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
559 | (column & 0xFF);
560
561 info->ndcb2 = 0;
562 } else {
563 info->ndcb1 = ((page_addr & 0xFFFF) << 16)
564 | (column & 0xFFFF);
565
566 if (page_addr & 0xFF0000)
567 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
568 else
569 info->ndcb2 = 0;
570 }
571
fe69af00 572 info->buf_count = mtd->writesize + mtd->oobsize;
4eb2da89 573 memset(info->data_buff, 0xFF, info->buf_count);
fe69af00 574
fe69af00 575 break;
4eb2da89 576
fe69af00 577 case NAND_CMD_PAGEPROG:
4eb2da89
LW		 578 if (is_buf_blank(info->data_buff,
579 (mtd->writesize + mtd->oobsize))) {
580 exec_cmd = 0;
581 break;
582 }
fe69af00 583
d456882b 584 cmd = host->cmdset->program;
4eb2da89
LW		 585 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
586 | NDCB0_AUTO_RS
587 | NDCB0_ST_ROW_EN
588 | NDCB0_DBC
589 | cmd
590 | addr_cycle;
fe69af00 591 break;
4eb2da89 592
ce0268f6
EG		 593 case NAND_CMD_PARAM:
594 cmd = NAND_CMD_PARAM;
595 info->buf_count = 256;
596 info->ndcb0 |= NDCB0_CMD_TYPE(0)
597 | NDCB0_ADDR_CYC(1)
598 | cmd;
599 info->ndcb1 = (column & 0xFF);
600 info->data_size = 256;
601 break;
602
fe69af00 603 case NAND_CMD_READID:
d456882b
LW		 604 cmd = host->cmdset->read_id;
605 info->buf_count = host->read_id_bytes;
4eb2da89
LW		 606 info->ndcb0 |= NDCB0_CMD_TYPE(3)
607 | NDCB0_ADDR_CYC(1)
608 | cmd;
d14231f1 609 info->ndcb1 = (column & 0xFF);
4eb2da89
LW		 610
611 info->data_size = 8;
612 break;
fe69af00 613 case NAND_CMD_STATUS:
d456882b 614 cmd = host->cmdset->read_status;
4eb2da89
LW		 615 info->buf_count = 1;
616 info->ndcb0 |= NDCB0_CMD_TYPE(4)
617 | NDCB0_ADDR_CYC(1)
618 | cmd;
619
620 info->data_size = 8;
621 break;
622
623 case NAND_CMD_ERASE1:
d456882b 624 cmd = host->cmdset->erase;
4eb2da89
LW		 625 info->ndcb0 |= NDCB0_CMD_TYPE(2)
626 | NDCB0_AUTO_RS
627 | NDCB0_ADDR_CYC(3)
628 | NDCB0_DBC
629 | cmd;
630 info->ndcb1 = page_addr;
631 info->ndcb2 = 0;
632
fe69af00 633 break;
634 case NAND_CMD_RESET:
d456882b 635 cmd = host->cmdset->reset;
4eb2da89
LW		 636 info->ndcb0 |= NDCB0_CMD_TYPE(5)
637 | cmd;
638
639 break;
640
641 case NAND_CMD_ERASE2:
642 exec_cmd = 0;
fe69af00 643 break;
4eb2da89 644
fe69af00 645 default:
4eb2da89 646 exec_cmd = 0;
da675b4e
LW		 647 dev_err(&info->pdev->dev, "non-supported command %x\n",
648 command);
fe69af00 649 break;
650 }
651
4eb2da89
LW		 652 return exec_cmd;
653}
654
655static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
656 int column, int page_addr)
657{
d456882b
LW		 658 struct pxa3xx_nand_host *host = mtd->priv;
659 struct pxa3xx_nand_info *info = host->info_data;
4eb2da89
LW		 660 int ret, exec_cmd;
661
662 /*
663 * if this is a x16 device ,then convert the input
664 * "byte" address into a "word" address appropriate
665 * for indexing a word-oriented device
666 */
d456882b 667 if (host->reg_ndcr & NDCR_DWIDTH_M)
4eb2da89
LW		 668 column /= 2;
669
f3c8cfc2
LW		 670 /*
671 * There may be different NAND chip hooked to
672 * different chip select, so check whether
673 * chip select has been changed, if yes, reset the timing
674 */
675 if (info->cs != host->cs) {
676 info->cs = host->cs;
677 nand_writel(info, NDTR0CS0, host->ndtr0cs0);
678 nand_writel(info, NDTR1CS0, host->ndtr1cs0);
679 }
680
d456882b 681 info->state = STATE_PREPARED;
4eb2da89 682 exec_cmd = prepare_command_pool(info, command, column, page_addr);
f8155a40
LW		 683 if (exec_cmd) {
684 init_completion(&info->cmd_complete);
685 pxa3xx_nand_start(info);
686
687 ret = wait_for_completion_timeout(&info->cmd_complete,
688 CHIP_DELAY_TIMEOUT);
689 if (!ret) {
da675b4e 690 dev_err(&info->pdev->dev, "Wait time out!!!\n");
f8155a40
LW		 691 /* Stop State Machine for next command cycle */
692 pxa3xx_nand_stop(info);
693 }
f8155a40 694 }
d456882b 695 info->state = STATE_IDLE;
f8155a40
LW		 696}
697
fdbad98d 698static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
1fbb938d 699 struct nand_chip *chip, const uint8_t *buf, int oob_required)
f8155a40
LW		 700{
701 chip->write_buf(mtd, buf, mtd->writesize);
702 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 703
704 return 0;
f8155a40
LW		 705}
706
707static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
1fbb938d
BN		 708 struct nand_chip *chip, uint8_t *buf, int oob_required,
709 int page)
f8155a40 710{
d456882b
LW		 711 struct pxa3xx_nand_host *host = mtd->priv;
712 struct pxa3xx_nand_info *info = host->info_data;
f8155a40
LW		 713
714 chip->read_buf(mtd, buf, mtd->writesize);
715 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
716
717 if (info->retcode == ERR_SBERR) {
718 switch (info->use_ecc) {
719 case 1:
720 mtd->ecc_stats.corrected++;
721 break;
722 case 0:
723 default:
724 break;
725 }
726 } else if (info->retcode == ERR_DBERR) {
727 /*
728 * for blank page (all 0xff), HW will calculate its ECC as
729 * 0, which is different from the ECC information within
730 * OOB, ignore such double bit errors
731 */
732 if (is_buf_blank(buf, mtd->writesize))
543e32d5
DM		 733 info->retcode = ERR_NONE;
734 else
f8155a40 735 mtd->ecc_stats.failed++;
fe69af00 736 }
f8155a40
LW		 737
738 return 0;
fe69af00 739}
740
741static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
742{
d456882b
LW		 743 struct pxa3xx_nand_host *host = mtd->priv;
744 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 745 char retval = 0xFF;
746
747 if (info->buf_start < info->buf_count)
748 /* Has just send a new command? */
749 retval = info->data_buff[info->buf_start++];
750
751 return retval;
752}
753
754static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
755{
d456882b
LW		 756 struct pxa3xx_nand_host *host = mtd->priv;
757 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 758 u16 retval = 0xFFFF;
759
760 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
761 retval = *((u16 *)(info->data_buff+info->buf_start));
762 info->buf_start += 2;
763 }
764 return retval;
765}
766
767static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
768{
d456882b
LW		 769 struct pxa3xx_nand_host *host = mtd->priv;
770 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 771 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
772
773 memcpy(buf, info->data_buff + info->buf_start, real_len);
774 info->buf_start += real_len;
775}
776
777static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
778 const uint8_t *buf, int len)
779{
d456882b
LW		 780 struct pxa3xx_nand_host *host = mtd->priv;
781 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 782 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
783
784 memcpy(info->data_buff + info->buf_start, buf, real_len);
785 info->buf_start += real_len;
786}
787
fe69af00 788static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
789{
790 return;
791}
792
793static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
794{
d456882b
LW		 795 struct pxa3xx_nand_host *host = mtd->priv;
796 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 797
798 /* pxa3xx_nand_send_command has waited for command complete */
799 if (this->state == FL_WRITING || this->state == FL_ERASING) {
800 if (info->retcode == ERR_NONE)
801 return 0;
802 else {
803 /*
804 * any error make it return 0x01 which will tell
805 * the caller the erase and write fail
806 */
807 return 0x01;
808 }
809 }
810
811 return 0;
812}
813
fe69af00 814static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
c8c17c88 815 const struct pxa3xx_nand_flash *f)
fe69af00 816{
817 struct platform_device *pdev = info->pdev;
453810b7 818 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
f3c8cfc2 819 struct pxa3xx_nand_host *host = info->host[info->cs];
f8155a40 820 uint32_t ndcr = 0x0; /* enable all interrupts */
fe69af00 821
da675b4e
LW		 822 if (f->page_size != 2048 && f->page_size != 512) {
823 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
fe69af00 824 return -EINVAL;
da675b4e 825 }
fe69af00 826
da675b4e
LW		 827 if (f->flash_width != 16 && f->flash_width != 8) {
828 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
fe69af00 829 return -EINVAL;
da675b4e 830 }
fe69af00 831
832 /* calculate flash information */
d456882b
LW		 833 host->cmdset = &default_cmdset;
834 host->page_size = f->page_size;
835 host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
fe69af00 836
837 /* calculate addressing information */
d456882b 838 host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
fe69af00 839
840 if (f->num_blocks * f->page_per_block > 65536)
d456882b 841 host->row_addr_cycles = 3;
fe69af00 842 else
d456882b 843 host->row_addr_cycles = 2;
fe69af00 844
845 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
d456882b 846 ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
fe69af00 847 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
848 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
849 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
850 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
851
d456882b 852 ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
fe69af00 853 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
854
d456882b 855 host->reg_ndcr = ndcr;
fe69af00 856
d456882b 857 pxa3xx_nand_set_timing(host, f->timing);
fe69af00 858 return 0;
859}
860
f271049e
MR		 861static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
862{
f3c8cfc2
LW		 863 /*
864 * We set 0 by hard coding here, for we don't support keep_config
865 * when there is more than one chip attached to the controller
866 */
867 struct pxa3xx_nand_host *host = info->host[0];
f271049e 868 uint32_t ndcr = nand_readl(info, NDCR);
f271049e 869
d456882b
LW		 870 if (ndcr & NDCR_PAGE_SZ) {
871 host->page_size = 2048;
872 host->read_id_bytes = 4;
873 } else {
874 host->page_size = 512;
875 host->read_id_bytes = 2;
876 }
877
878 host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
879 host->cmdset = &default_cmdset;
880
881 host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
882 host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
f271049e
MR		 883
884 return 0;
885}
886
fe69af00 887/* the maximum possible buffer size for large page with OOB data
888 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
889 * data buffer and the DMA descriptor
890 */
891#define MAX_BUFF_SIZE PAGE_SIZE
892
893static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
894{
895 struct platform_device *pdev = info->pdev;
896 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
897
898 if (use_dma == 0) {
899 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
900 if (info->data_buff == NULL)
901 return -ENOMEM;
902 return 0;
903 }
904
905 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
906 &info->data_buff_phys, GFP_KERNEL);
907 if (info->data_buff == NULL) {
908 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
909 return -ENOMEM;
910 }
911
fe69af00 912 info->data_desc = (void *)info->data_buff + data_desc_offset;
913 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
914
915 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
916 pxa3xx_nand_data_dma_irq, info);
917 if (info->data_dma_ch < 0) {
918 dev_err(&pdev->dev, "failed to request data dma\n");
d456882b 919 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
fe69af00 920 info->data_buff, info->data_buff_phys);
921 return info->data_dma_ch;
922 }
923
924 return 0;
925}
926
498b6145
EG		 927static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
928{
929 struct platform_device *pdev = info->pdev;
930 if (use_dma) {
931 pxa_free_dma(info->data_dma_ch);
932 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
933 info->data_buff, info->data_buff_phys);
934 } else {
935 kfree(info->data_buff);
936 }
937}
938
401e67e2
LW		 939static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
940{
f3c8cfc2 941 struct mtd_info *mtd;
d456882b 942 int ret;
f3c8cfc2 943 mtd = info->host[info->cs]->mtd;
401e67e2 944 /* use the common timing to make a try */
d456882b
LW		 945 ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
946 if (ret)
947 return ret;
948
949 pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
401e67e2 950 if (info->is_ready)
401e67e2 951 return 0;
d456882b
LW		 952
953 return -ENODEV;
401e67e2 954}
fe69af00 955
401e67e2 956static int pxa3xx_nand_scan(struct mtd_info *mtd)
fe69af00 957{
d456882b
LW		 958 struct pxa3xx_nand_host *host = mtd->priv;
959 struct pxa3xx_nand_info *info = host->info_data;
401e67e2 960 struct platform_device *pdev = info->pdev;
453810b7 961 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
0fab028b 962 struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
401e67e2
LW		 963 const struct pxa3xx_nand_flash *f = NULL;
964 struct nand_chip *chip = mtd->priv;
965 uint32_t id = -1;
4332c116 966 uint64_t chipsize;
401e67e2
LW		 967 int i, ret, num;
968
969 if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
4332c116 970 goto KEEP_CONFIG;
401e67e2
LW		 971
972 ret = pxa3xx_nand_sensing(info);
d456882b 973 if (ret) {
f3c8cfc2
LW		 974 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
975 info->cs);
401e67e2 976
d456882b 977 return ret;
401e67e2
LW		 978 }
979
980 chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
981 id = *((uint16_t *)(info->data_buff));
982 if (id != 0)
da675b4e 983 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
401e67e2 984 else {
da675b4e
LW		 985 dev_warn(&info->pdev->dev,
986 "Read out ID 0, potential timing set wrong!!\n");
401e67e2
LW		 987
988 return -EINVAL;
989 }
990
991 num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
992 for (i = 0; i < num; i++) {
993 if (i < pdata->num_flash)
994 f = pdata->flash + i;
995 else
996 f = &builtin_flash_types[i - pdata->num_flash + 1];
997
998 /* find the chip in default list */
4332c116 999 if (f->chip_id == id)
401e67e2 1000 break;
401e67e2
LW		 1001 }
1002
4332c116 1003 if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
da675b4e 1004 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
401e67e2
LW		 1005
1006 return -EINVAL;
1007 }
1008
d456882b
LW		 1009 ret = pxa3xx_nand_config_flash(info, f);
1010 if (ret) {
1011 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
1012 return ret;
1013 }
1014
4332c116 1015 pxa3xx_flash_ids[0].name = f->name;
68aa352d 1016 pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
4332c116
LW		 1017 pxa3xx_flash_ids[0].pagesize = f->page_size;
1018 chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
1019 pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1020 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1021 if (f->flash_width == 16)
1022 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
0fab028b
LW		 1023 pxa3xx_flash_ids[1].name = NULL;
1024 def = pxa3xx_flash_ids;
4332c116 1025KEEP_CONFIG:
d456882b
LW		 1026 chip->ecc.mode = NAND_ECC_HW;
1027 chip->ecc.size = host->page_size;
6a918bad 1028 chip->ecc.strength = 1;
d456882b 1029
d456882b
LW		 1030 if (host->reg_ndcr & NDCR_DWIDTH_M)
1031 chip->options |= NAND_BUSWIDTH_16;
1032
0fab028b 1033 if (nand_scan_ident(mtd, 1, def))
4332c116
LW		 1034 return -ENODEV;
1035 /* calculate addressing information */
d456882b
LW		 1036 if (mtd->writesize >= 2048)
1037 host->col_addr_cycles = 2;
1038 else
1039 host->col_addr_cycles = 1;
1040
4332c116
LW		 1041 info->oob_buff = info->data_buff + mtd->writesize;
1042 if ((mtd->size >> chip->page_shift) > 65536)
d456882b 1043 host->row_addr_cycles = 3;
4332c116 1044 else
d456882b 1045 host->row_addr_cycles = 2;
fe69af00 1046
d456882b 1047 mtd->name = mtd_names[0];
401e67e2 1048 return nand_scan_tail(mtd);
fe69af00 1049}
1050
d456882b 1051static int alloc_nand_resource(struct platform_device *pdev)
fe69af00 1052{
f3c8cfc2 1053 struct pxa3xx_nand_platform_data *pdata;
fe69af00 1054 struct pxa3xx_nand_info *info;
d456882b 1055 struct pxa3xx_nand_host *host;
6e308f87 1056 struct nand_chip *chip = NULL;
fe69af00 1057 struct mtd_info *mtd;
1058 struct resource *r;
f3c8cfc2 1059 int ret, irq, cs;
fe69af00 1060
453810b7 1061 pdata = dev_get_platdata(&pdev->dev);
4c073cd2
EG		 1062 info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
1063 sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1064 if (!info)
d456882b 1065 return -ENOMEM;
fe69af00 1066
fe69af00 1067 info->pdev = pdev;
f3c8cfc2
LW		 1068 for (cs = 0; cs < pdata->num_cs; cs++) {
1069 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1070 (sizeof(*mtd) + sizeof(*host)) * cs);
1071 chip = (struct nand_chip *)(&mtd[1]);
1072 host = (struct pxa3xx_nand_host *)chip;
1073 info->host[cs] = host;
1074 host->mtd = mtd;
1075 host->cs = cs;
1076 host->info_data = info;
1077 mtd->priv = host;
1078 mtd->owner = THIS_MODULE;
1079
1080 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
1081 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
1082 chip->controller = &info->controller;
1083 chip->waitfunc = pxa3xx_nand_waitfunc;
1084 chip->select_chip = pxa3xx_nand_select_chip;
1085 chip->cmdfunc = pxa3xx_nand_cmdfunc;
1086 chip->read_word = pxa3xx_nand_read_word;
1087 chip->read_byte = pxa3xx_nand_read_byte;
1088 chip->read_buf = pxa3xx_nand_read_buf;
1089 chip->write_buf = pxa3xx_nand_write_buf;
f3c8cfc2 1090 }
401e67e2
LW		 1091
1092 spin_lock_init(&chip->controller->lock);
1093 init_waitqueue_head(&chip->controller->wq);
9ca7944d 1094 info->clk = devm_clk_get(&pdev->dev, NULL);
fe69af00 1095 if (IS_ERR(info->clk)) {
1096 dev_err(&pdev->dev, "failed to get nand clock\n");
4c073cd2 1097 return PTR_ERR(info->clk);
fe69af00 1098 }
1f8eaff2
EG		 1099 ret = clk_prepare_enable(info->clk);
1100 if (ret < 0)
1101 return ret;
fe69af00 1102
1e7ba630
DM		 1103 /*
1104 * This is a dirty hack to make this driver work from devicetree
1105 * bindings. It can be removed once we have a prober DMA controller
1106 * framework for DT.
1107 */
a33e435c 1108 if (pdev->dev.of_node && of_machine_is_compatible("marvell,pxa3xx")) {
1e7ba630
DM		 1109 info->drcmr_dat = 97;
1110 info->drcmr_cmd = 99;
1111 } else {
1112 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1113 if (r == NULL) {
1114 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1115 ret = -ENXIO;
9ca7944d 1116 goto fail_disable_clk;
1e7ba630
DM		 1117 }
1118 info->drcmr_dat = r->start;
fe69af00 1119
1e7ba630
DM		 1120 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1121 if (r == NULL) {
1122 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1123 ret = -ENXIO;
9ca7944d 1124 goto fail_disable_clk;
1e7ba630
DM		 1125 }
1126 info->drcmr_cmd = r->start;
fe69af00 1127 }
fe69af00 1128
1129 irq = platform_get_irq(pdev, 0);
1130 if (irq < 0) {
1131 dev_err(&pdev->dev, "no IRQ resource defined\n");
1132 ret = -ENXIO;
9ca7944d 1133 goto fail_disable_clk;
fe69af00 1134 }
1135
1136 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0ddd846f
EG		 1137 info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
1138 if (IS_ERR(info->mmio_base)) {
1139 ret = PTR_ERR(info->mmio_base);
9ca7944d 1140 goto fail_disable_clk;
fe69af00 1141 }
8638fac8 1142 info->mmio_phys = r->start;
fe69af00 1143
1144 ret = pxa3xx_nand_init_buff(info);
1145 if (ret)
9ca7944d 1146 goto fail_disable_clk;
fe69af00 1147
346e1259
HZ		 1148 /* initialize all interrupts to be disabled */
1149 disable_int(info, NDSR_MASK);
1150
dbf5986a
HZ		 1151 ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1152 pdev->name, info);
fe69af00 1153 if (ret < 0) {
1154 dev_err(&pdev->dev, "failed to request IRQ\n");
1155 goto fail_free_buf;
1156 }
1157
e353a20a 1158 platform_set_drvdata(pdev, info);
fe69af00 1159
d456882b 1160 return 0;
fe69af00 1161
fe69af00 1162fail_free_buf:
401e67e2 1163 free_irq(irq, info);
498b6145 1164 pxa3xx_nand_free_buff(info);
9ca7944d 1165fail_disable_clk:
fb32061f 1166 clk_disable_unprepare(info->clk);
d456882b 1167 return ret;
fe69af00 1168}
1169
1170static int pxa3xx_nand_remove(struct platform_device *pdev)
1171{
e353a20a 1172 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
f3c8cfc2 1173 struct pxa3xx_nand_platform_data *pdata;
f3c8cfc2 1174 int irq, cs;
fe69af00 1175
d456882b
LW		 1176 if (!info)
1177 return 0;
1178
453810b7 1179 pdata = dev_get_platdata(&pdev->dev);
fe69af00 1180
dbf5986a
HZ		 1181 irq = platform_get_irq(pdev, 0);
1182 if (irq >= 0)
1183 free_irq(irq, info);
498b6145 1184 pxa3xx_nand_free_buff(info);
82a72d10 1185
fb32061f 1186 clk_disable_unprepare(info->clk);
82a72d10 1187
f3c8cfc2
LW		 1188 for (cs = 0; cs < pdata->num_cs; cs++)
1189 nand_release(info->host[cs]->mtd);
fe69af00 1190 return 0;
1191}
1192
1e7ba630
DM		 1193#ifdef CONFIG_OF
1194static struct of_device_id pxa3xx_nand_dt_ids[] = {
1195 { .compatible = "marvell,pxa3xx-nand" },
1196 {}
1197};
f3958984 1198MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
1e7ba630
DM		 1199
1200static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1201{
1202 struct pxa3xx_nand_platform_data *pdata;
1203 struct device_node *np = pdev->dev.of_node;
1204 const struct of_device_id *of_id =
1205 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1206
1207 if (!of_id)
1208 return 0;
1209
1210 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1211 if (!pdata)
1212 return -ENOMEM;
1213
1214 if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1215 pdata->enable_arbiter = 1;
1216 if (of_get_property(np, "marvell,nand-keep-config", NULL))
1217 pdata->keep_config = 1;
1218 of_property_read_u32(np, "num-cs", &pdata->num_cs);
1219
1220 pdev->dev.platform_data = pdata;
1221
1222 return 0;
1223}
1224#else
6e308f87 1225static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1e7ba630
DM		 1226{
1227 return 0;
1228}
1229#endif
1230
e353a20a
LW		 1231static int pxa3xx_nand_probe(struct platform_device *pdev)
1232{
1233 struct pxa3xx_nand_platform_data *pdata;
1e7ba630 1234 struct mtd_part_parser_data ppdata = {};
e353a20a 1235 struct pxa3xx_nand_info *info;
f3c8cfc2 1236 int ret, cs, probe_success;
e353a20a 1237
1e7ba630
DM		 1238 ret = pxa3xx_nand_probe_dt(pdev);
1239 if (ret)
1240 return ret;
1241
453810b7 1242 pdata = dev_get_platdata(&pdev->dev);
e353a20a
LW		 1243 if (!pdata) {
1244 dev_err(&pdev->dev, "no platform data defined\n");
1245 return -ENODEV;
1246 }
1247
d456882b
LW		 1248 ret = alloc_nand_resource(pdev);
1249 if (ret) {
1250 dev_err(&pdev->dev, "alloc nand resource failed\n");
1251 return ret;
1252 }
e353a20a 1253
d456882b 1254 info = platform_get_drvdata(pdev);
f3c8cfc2
LW		 1255 probe_success = 0;
1256 for (cs = 0; cs < pdata->num_cs; cs++) {
1257 info->cs = cs;
1258 ret = pxa3xx_nand_scan(info->host[cs]->mtd);
1259 if (ret) {
1260 dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1261 cs);
1262 continue;
1263 }
1264
1e7ba630 1265 ppdata.of_node = pdev->dev.of_node;
42d7fbe2 1266 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
1e7ba630 1267 &ppdata, pdata->parts[cs],
42d7fbe2 1268 pdata->nr_parts[cs]);
f3c8cfc2
LW		 1269 if (!ret)
1270 probe_success = 1;
1271 }
1272
1273 if (!probe_success) {
e353a20a
LW		 1274 pxa3xx_nand_remove(pdev);
1275 return -ENODEV;
1276 }
1277
f3c8cfc2 1278 return 0;
e353a20a
LW		 1279}
1280
fe69af00 1281#ifdef CONFIG_PM
1282static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1283{
e353a20a 1284 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
f3c8cfc2
LW		 1285 struct pxa3xx_nand_platform_data *pdata;
1286 struct mtd_info *mtd;
1287 int cs;
fe69af00 1288
453810b7 1289 pdata = dev_get_platdata(&pdev->dev);
f8155a40 1290 if (info->state) {
fe69af00 1291 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1292 return -EAGAIN;
1293 }
1294
f3c8cfc2
LW		 1295 for (cs = 0; cs < pdata->num_cs; cs++) {
1296 mtd = info->host[cs]->mtd;
3fe4bae8 1297 mtd_suspend(mtd);
f3c8cfc2
LW		 1298 }
1299
fe69af00 1300 return 0;
1301}
1302
1303static int pxa3xx_nand_resume(struct platform_device *pdev)
1304{
e353a20a 1305 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
f3c8cfc2
LW		 1306 struct pxa3xx_nand_platform_data *pdata;
1307 struct mtd_info *mtd;
1308 int cs;
051fc41c 1309
453810b7 1310 pdata = dev_get_platdata(&pdev->dev);
051fc41c
LW		 1311 /* We don't want to handle interrupt without calling mtd routine */
1312 disable_int(info, NDCR_INT_MASK);
fe69af00 1313
f3c8cfc2
LW		 1314 /*
1315 * Directly set the chip select to a invalid value,
1316 * then the driver would reset the timing according
1317 * to current chip select at the beginning of cmdfunc
1318 */
1319 info->cs = 0xff;
fe69af00 1320
051fc41c
LW		 1321 /*
1322 * As the spec says, the NDSR would be updated to 0x1800 when
1323 * doing the nand_clk disable/enable.
1324 * To prevent it damaging state machine of the driver, clear
1325 * all status before resume
1326 */
1327 nand_writel(info, NDSR, NDSR_MASK);
f3c8cfc2
LW		 1328 for (cs = 0; cs < pdata->num_cs; cs++) {
1329 mtd = info->host[cs]->mtd;
ead995f8 1330 mtd_resume(mtd);
f3c8cfc2
LW		 1331 }
1332
18c81b18 1333 return 0;
fe69af00 1334}
1335#else
1336#define pxa3xx_nand_suspend NULL
1337#define pxa3xx_nand_resume NULL
1338#endif
1339
1340static struct platform_driver pxa3xx_nand_driver = {
1341 .driver = {
1342 .name = "pxa3xx-nand",
1e7ba630 1343 .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
fe69af00 1344 },
1345 .probe = pxa3xx_nand_probe,
1346 .remove = pxa3xx_nand_remove,
1347 .suspend = pxa3xx_nand_suspend,
1348 .resume = pxa3xx_nand_resume,
1349};
1350
f99640de 1351module_platform_driver(pxa3xx_nand_driver);
fe69af00 1352
1353MODULE_LICENSE("GPL");
1354MODULE_DESCRIPTION("PXA3xx NAND controller driver");
Linux kernel - Deliverables
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