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mtd: nand: append missing parameter and value
[deliverable/linux.git] / drivers / mtd / nand / pxa3xx_nand.c
CommitLineData
fe69af00 1/*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
a88bdbb5 12#include <linux/kernel.h>
fe69af00 13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/delay.h>
18#include <linux/clk.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
a1c06ee1
DW		 22#include <linux/io.h>
23#include <linux/irq.h>
5a0e3ad6 24#include <linux/slab.h>
1e7ba630
DM		 25#include <linux/of.h>
26#include <linux/of_device.h>
fe69af00 27
afb5b5c9 28#include <mach/dma.h>
82b95ecb 29#include <plat/pxa3xx_nand.h>
fe69af00 30
31#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
f8155a40 32#define NAND_STOP_DELAY (2 * HZ/50)
4eb2da89 33#define PAGE_CHUNK_SIZE (2048)
fe69af00 34
35/* registers and bit definitions */
36#define NDCR (0x00) /* Control register */
37#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
38#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
39#define NDSR (0x14) /* Status Register */
40#define NDPCR (0x18) /* Page Count Register */
41#define NDBDR0 (0x1C) /* Bad Block Register 0 */
42#define NDBDR1 (0x20) /* Bad Block Register 1 */
43#define NDDB (0x40) /* Data Buffer */
44#define NDCB0 (0x48) /* Command Buffer0 */
45#define NDCB1 (0x4C) /* Command Buffer1 */
46#define NDCB2 (0x50) /* Command Buffer2 */
47
48#define NDCR_SPARE_EN (0x1 << 31)
49#define NDCR_ECC_EN (0x1 << 30)
50#define NDCR_DMA_EN (0x1 << 29)
51#define NDCR_ND_RUN (0x1 << 28)
52#define NDCR_DWIDTH_C (0x1 << 27)
53#define NDCR_DWIDTH_M (0x1 << 26)
54#define NDCR_PAGE_SZ (0x1 << 24)
55#define NDCR_NCSX (0x1 << 23)
56#define NDCR_ND_MODE (0x3 << 21)
57#define NDCR_NAND_MODE (0x0)
58#define NDCR_CLR_PG_CNT (0x1 << 20)
f8155a40 59#define NDCR_STOP_ON_UNCOR (0x1 << 19)
fe69af00 60#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
61#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
62
63#define NDCR_RA_START (0x1 << 15)
64#define NDCR_PG_PER_BLK (0x1 << 14)
65#define NDCR_ND_ARB_EN (0x1 << 12)
f8155a40 66#define NDCR_INT_MASK (0xFFF)
fe69af00 67
68#define NDSR_MASK (0xfff)
f8155a40
LW		 69#define NDSR_RDY (0x1 << 12)
70#define NDSR_FLASH_RDY (0x1 << 11)
fe69af00 71#define NDSR_CS0_PAGED (0x1 << 10)
72#define NDSR_CS1_PAGED (0x1 << 9)
73#define NDSR_CS0_CMDD (0x1 << 8)
74#define NDSR_CS1_CMDD (0x1 << 7)
75#define NDSR_CS0_BBD (0x1 << 6)
76#define NDSR_CS1_BBD (0x1 << 5)
77#define NDSR_DBERR (0x1 << 4)
78#define NDSR_SBERR (0x1 << 3)
79#define NDSR_WRDREQ (0x1 << 2)
80#define NDSR_RDDREQ (0x1 << 1)
81#define NDSR_WRCMDREQ (0x1)
82
4eb2da89 83#define NDCB0_ST_ROW_EN (0x1 << 26)
fe69af00 84#define NDCB0_AUTO_RS (0x1 << 25)
85#define NDCB0_CSEL (0x1 << 24)
86#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
87#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
88#define NDCB0_NC (0x1 << 20)
89#define NDCB0_DBC (0x1 << 19)
90#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
91#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
92#define NDCB0_CMD2_MASK (0xff << 8)
93#define NDCB0_CMD1_MASK (0xff)
94#define NDCB0_ADDR_CYC_SHIFT (16)
95
fe69af00 96/* macros for registers read/write */
97#define nand_writel(info, off, val) \
98 __raw_writel((val), (info)->mmio_base + (off))
99
100#define nand_readl(info, off) \
101 __raw_readl((info)->mmio_base + (off))
102
103/* error code and state */
104enum {
105 ERR_NONE = 0,
106 ERR_DMABUSERR = -1,
107 ERR_SENDCMD = -2,
108 ERR_DBERR = -3,
109 ERR_BBERR = -4,
223cf6c3 110 ERR_SBERR = -5,
fe69af00 111};
112
113enum {
f8155a40 114 STATE_IDLE = 0,
d456882b 115 STATE_PREPARED,
fe69af00 116 STATE_CMD_HANDLE,
117 STATE_DMA_READING,
118 STATE_DMA_WRITING,
119 STATE_DMA_DONE,
120 STATE_PIO_READING,
121 STATE_PIO_WRITING,
f8155a40
LW		 122 STATE_CMD_DONE,
123 STATE_READY,
fe69af00 124};
125
d456882b
LW		 126struct pxa3xx_nand_host {
127 struct nand_chip chip;
128 struct pxa3xx_nand_cmdset *cmdset;
129 struct mtd_info *mtd;
130 void *info_data;
131
132 /* page size of attached chip */
133 unsigned int page_size;
134 int use_ecc;
f3c8cfc2 135 int cs;
fe69af00 136
d456882b
LW		 137 /* calculated from pxa3xx_nand_flash data */
138 unsigned int col_addr_cycles;
139 unsigned int row_addr_cycles;
140 size_t read_id_bytes;
141
142 /* cached register value */
143 uint32_t reg_ndcr;
144 uint32_t ndtr0cs0;
145 uint32_t ndtr1cs0;
146};
147
148struct pxa3xx_nand_info {
401e67e2 149 struct nand_hw_control controller;
fe69af00 150 struct platform_device *pdev;
fe69af00 151
152 struct clk *clk;
153 void __iomem *mmio_base;
8638fac8 154 unsigned long mmio_phys;
d456882b 155 struct completion cmd_complete;
fe69af00 156
157 unsigned int buf_start;
158 unsigned int buf_count;
159
160 /* DMA information */
161 int drcmr_dat;
162 int drcmr_cmd;
163
164 unsigned char *data_buff;
18c81b18 165 unsigned char *oob_buff;
fe69af00 166 dma_addr_t data_buff_phys;
fe69af00 167 int data_dma_ch;
168 struct pxa_dma_desc *data_desc;
169 dma_addr_t data_desc_addr;
170
f3c8cfc2 171 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
fe69af00 172 unsigned int state;
173
f3c8cfc2 174 int cs;
fe69af00 175 int use_ecc; /* use HW ECC ? */
176 int use_dma; /* use DMA ? */
401e67e2 177 int is_ready;
fe69af00 178
18c81b18
LW		 179 unsigned int page_size; /* page size of attached chip */
180 unsigned int data_size; /* data size in FIFO */
d456882b 181 unsigned int oob_size;
fe69af00 182 int retcode;
fe69af00 183
184 /* generated NDCBx register values */
185 uint32_t ndcb0;
186 uint32_t ndcb1;
187 uint32_t ndcb2;
188};
189
90ab5ee9 190static bool use_dma = 1;
fe69af00 191module_param(use_dma, bool, 0444);
25985edc 192MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
fe69af00 193
f271049e
MR		 194/*
195 * Default NAND flash controller configuration setup by the
196 * bootloader. This configuration is used only when pdata->keep_config is set
197 */
c1f82478 198static struct pxa3xx_nand_cmdset default_cmdset = {
fe69af00 199 .read1 = 0x3000,
200 .read2 = 0x0050,
201 .program = 0x1080,
202 .read_status = 0x0070,
203 .read_id = 0x0090,
204 .erase = 0xD060,
205 .reset = 0x00FF,
206 .lock = 0x002A,
207 .unlock = 0x2423,
208 .lock_status = 0x007A,
209};
210
c1f82478 211static struct pxa3xx_nand_timing timing[] = {
227a886c
LW		 212 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
213 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
214 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
215 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
d3490dfd
HZ		 216};
217
c1f82478 218static struct pxa3xx_nand_flash builtin_flash_types[] = {
4332c116
LW		 219{ "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
220{ "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
221{ "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
222{ "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
223{ "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
224{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
225{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
226{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
227{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
d3490dfd
HZ		 228};
229
227a886c
LW		 230/* Define a default flash type setting serve as flash detecting only */
231#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
232
f3c8cfc2 233const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
401e67e2 234
fe69af00 235#define NDTR0_tCH(c) (min((c), 7) << 19)
236#define NDTR0_tCS(c) (min((c), 7) << 16)
237#define NDTR0_tWH(c) (min((c), 7) << 11)
238#define NDTR0_tWP(c) (min((c), 7) << 8)
239#define NDTR0_tRH(c) (min((c), 7) << 3)
240#define NDTR0_tRP(c) (min((c), 7) << 0)
241
242#define NDTR1_tR(c) (min((c), 65535) << 16)
243#define NDTR1_tWHR(c) (min((c), 15) << 4)
244#define NDTR1_tAR(c) (min((c), 15) << 0)
245
246/* convert nano-seconds to nand flash controller clock cycles */
93b352fc 247#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
fe69af00 248
d456882b 249static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
7dad482e 250 const struct pxa3xx_nand_timing *t)
fe69af00 251{
d456882b 252 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 253 unsigned long nand_clk = clk_get_rate(info->clk);
254 uint32_t ndtr0, ndtr1;
255
256 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
257 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
258 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
259 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
260 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
261 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
262
263 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
264 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
265 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
266
d456882b
LW		 267 host->ndtr0cs0 = ndtr0;
268 host->ndtr1cs0 = ndtr1;
fe69af00 269 nand_writel(info, NDTR0CS0, ndtr0);
270 nand_writel(info, NDTR1CS0, ndtr1);
271}
272
18c81b18 273static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
fe69af00 274{
f3c8cfc2 275 struct pxa3xx_nand_host *host = info->host[info->cs];
d456882b 276 int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
9d8b1043 277
d456882b 278 info->data_size = host->page_size;
9d8b1043
LW		 279 if (!oob_enable) {
280 info->oob_size = 0;
281 return;
282 }
283
d456882b 284 switch (host->page_size) {
fe69af00 285 case 2048:
9d8b1043 286 info->oob_size = (info->use_ecc) ? 40 : 64;
fe69af00 287 break;
288 case 512:
9d8b1043 289 info->oob_size = (info->use_ecc) ? 8 : 16;
fe69af00 290 break;
fe69af00 291 }
18c81b18
LW		 292}
293
f8155a40
LW		 294/**
295 * NOTE: it is a must to set ND_RUN firstly, then write
296 * command buffer, otherwise, it does not work.
297 * We enable all the interrupt at the same time, and
298 * let pxa3xx_nand_irq to handle all logic.
299 */
300static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
301{
f3c8cfc2 302 struct pxa3xx_nand_host *host = info->host[info->cs];
f8155a40
LW		 303 uint32_t ndcr;
304
d456882b 305 ndcr = host->reg_ndcr;
f8155a40
LW		 306 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
307 ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
308 ndcr |= NDCR_ND_RUN;
309
310 /* clear status bits and run */
311 nand_writel(info, NDCR, 0);
312 nand_writel(info, NDSR, NDSR_MASK);
313 nand_writel(info, NDCR, ndcr);
314}
315
316static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
317{
318 uint32_t ndcr;
319 int timeout = NAND_STOP_DELAY;
320
321 /* wait RUN bit in NDCR become 0 */
322 ndcr = nand_readl(info, NDCR);
323 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
324 ndcr = nand_readl(info, NDCR);
325 udelay(1);
326 }
327
328 if (timeout <= 0) {
329 ndcr &= ~NDCR_ND_RUN;
330 nand_writel(info, NDCR, ndcr);
331 }
332 /* clear status bits */
333 nand_writel(info, NDSR, NDSR_MASK);
334}
335
fe69af00 336static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
337{
338 uint32_t ndcr;
339
340 ndcr = nand_readl(info, NDCR);
341 nand_writel(info, NDCR, ndcr & ~int_mask);
342}
343
344static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
345{
346 uint32_t ndcr;
347
348 ndcr = nand_readl(info, NDCR);
349 nand_writel(info, NDCR, ndcr | int_mask);
350}
351
f8155a40 352static void handle_data_pio(struct pxa3xx_nand_info *info)
fe69af00 353{
fe69af00 354 switch (info->state) {
355 case STATE_PIO_WRITING:
356 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 357 DIV_ROUND_UP(info->data_size, 4));
9d8b1043
LW		 358 if (info->oob_size > 0)
359 __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
360 DIV_ROUND_UP(info->oob_size, 4));
fe69af00 361 break;
362 case STATE_PIO_READING:
363 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 364 DIV_ROUND_UP(info->data_size, 4));
9d8b1043
LW		 365 if (info->oob_size > 0)
366 __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
367 DIV_ROUND_UP(info->oob_size, 4));
fe69af00 368 break;
369 default:
da675b4e 370 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
fe69af00 371 info->state);
f8155a40 372 BUG();
fe69af00 373 }
fe69af00 374}
375
f8155a40 376static void start_data_dma(struct pxa3xx_nand_info *info)
fe69af00 377{
378 struct pxa_dma_desc *desc = info->data_desc;
9d8b1043 379 int dma_len = ALIGN(info->data_size + info->oob_size, 32);
fe69af00 380
381 desc->ddadr = DDADR_STOP;
382 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
383
f8155a40
LW		 384 switch (info->state) {
385 case STATE_DMA_WRITING:
fe69af00 386 desc->dsadr = info->data_buff_phys;
8638fac8 387 desc->dtadr = info->mmio_phys + NDDB;
fe69af00 388 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
f8155a40
LW		 389 break;
390 case STATE_DMA_READING:
fe69af00 391 desc->dtadr = info->data_buff_phys;
8638fac8 392 desc->dsadr = info->mmio_phys + NDDB;
fe69af00 393 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
f8155a40
LW		 394 break;
395 default:
da675b4e 396 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
f8155a40
LW		 397 info->state);
398 BUG();
fe69af00 399 }
400
401 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
402 DDADR(info->data_dma_ch) = info->data_desc_addr;
403 DCSR(info->data_dma_ch) |= DCSR_RUN;
404}
405
406static void pxa3xx_nand_data_dma_irq(int channel, void *data)
407{
408 struct pxa3xx_nand_info *info = data;
409 uint32_t dcsr;
410
411 dcsr = DCSR(channel);
412 DCSR(channel) = dcsr;
413
414 if (dcsr & DCSR_BUSERR) {
415 info->retcode = ERR_DMABUSERR;
fe69af00 416 }
417
f8155a40
LW		 418 info->state = STATE_DMA_DONE;
419 enable_int(info, NDCR_INT_MASK);
420 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
fe69af00 421}
422
423static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
424{
425 struct pxa3xx_nand_info *info = devid;
f8155a40 426 unsigned int status, is_completed = 0;
f3c8cfc2
LW		 427 unsigned int ready, cmd_done;
428
429 if (info->cs == 0) {
430 ready = NDSR_FLASH_RDY;
431 cmd_done = NDSR_CS0_CMDD;
432 } else {
433 ready = NDSR_RDY;
434 cmd_done = NDSR_CS1_CMDD;
435 }
fe69af00 436
437 status = nand_readl(info, NDSR);
438
f8155a40
LW		 439 if (status & NDSR_DBERR)
440 info->retcode = ERR_DBERR;
441 if (status & NDSR_SBERR)
442 info->retcode = ERR_SBERR;
443 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
444 /* whether use dma to transfer data */
fe69af00 445 if (info->use_dma) {
f8155a40
LW		 446 disable_int(info, NDCR_INT_MASK);
447 info->state = (status & NDSR_RDDREQ) ?
448 STATE_DMA_READING : STATE_DMA_WRITING;
449 start_data_dma(info);
450 goto NORMAL_IRQ_EXIT;
fe69af00 451 } else {
f8155a40
LW		 452 info->state = (status & NDSR_RDDREQ) ?
453 STATE_PIO_READING : STATE_PIO_WRITING;
454 handle_data_pio(info);
fe69af00 455 }
fe69af00 456 }
f3c8cfc2 457 if (status & cmd_done) {
f8155a40
LW		 458 info->state = STATE_CMD_DONE;
459 is_completed = 1;
fe69af00 460 }
f3c8cfc2 461 if (status & ready) {
401e67e2 462 info->is_ready = 1;
f8155a40 463 info->state = STATE_READY;
401e67e2 464 }
fe69af00 465
f8155a40
LW		 466 if (status & NDSR_WRCMDREQ) {
467 nand_writel(info, NDSR, NDSR_WRCMDREQ);
468 status &= ~NDSR_WRCMDREQ;
469 info->state = STATE_CMD_HANDLE;
470 nand_writel(info, NDCB0, info->ndcb0);
471 nand_writel(info, NDCB0, info->ndcb1);
472 nand_writel(info, NDCB0, info->ndcb2);
fe69af00 473 }
474
f8155a40
LW		 475 /* clear NDSR to let the controller exit the IRQ */
476 nand_writel(info, NDSR, status);
477 if (is_completed)
478 complete(&info->cmd_complete);
479NORMAL_IRQ_EXIT:
480 return IRQ_HANDLED;
fe69af00 481}
482
fe69af00 483static inline int is_buf_blank(uint8_t *buf, size_t len)
484{
485 for (; len > 0; len--)
486 if (*buf++ != 0xff)
487 return 0;
488 return 1;
489}
490
4eb2da89
LW		 491static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
492 uint16_t column, int page_addr)
fe69af00 493{
4eb2da89 494 uint16_t cmd;
d456882b 495 int addr_cycle, exec_cmd;
f3c8cfc2
LW		 496 struct pxa3xx_nand_host *host;
497 struct mtd_info *mtd;
fe69af00 498
f3c8cfc2
LW		 499 host = info->host[info->cs];
500 mtd = host->mtd;
4eb2da89
LW		 501 addr_cycle = 0;
502 exec_cmd = 1;
503
504 /* reset data and oob column point to handle data */
401e67e2
LW		 505 info->buf_start = 0;
506 info->buf_count = 0;
4eb2da89
LW		 507 info->oob_size = 0;
508 info->use_ecc = 0;
401e67e2 509 info->is_ready = 0;
4eb2da89 510 info->retcode = ERR_NONE;
f3c8cfc2
LW		 511 if (info->cs != 0)
512 info->ndcb0 = NDCB0_CSEL;
513 else
514 info->ndcb0 = 0;
fe69af00 515
516 switch (command) {
4eb2da89
LW		 517 case NAND_CMD_READ0:
518 case NAND_CMD_PAGEPROG:
519 info->use_ecc = 1;
fe69af00 520 case NAND_CMD_READOOB:
4eb2da89 521 pxa3xx_set_datasize(info);
fe69af00 522 break;
4eb2da89
LW		 523 case NAND_CMD_SEQIN:
524 exec_cmd = 0;
525 break;
526 default:
527 info->ndcb1 = 0;
528 info->ndcb2 = 0;
529 break;
530 }
531
d456882b
LW		 532 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
533 + host->col_addr_cycles);
fe69af00 534
4eb2da89
LW		 535 switch (command) {
536 case NAND_CMD_READOOB:
fe69af00 537 case NAND_CMD_READ0:
d456882b 538 cmd = host->cmdset->read1;
4eb2da89
LW		 539 if (command == NAND_CMD_READOOB)
540 info->buf_start = mtd->writesize + column;
541 else
542 info->buf_start = column;
543
d456882b 544 if (unlikely(host->page_size < PAGE_CHUNK_SIZE))
4eb2da89
LW		 545 info->ndcb0 |= NDCB0_CMD_TYPE(0)
546 | addr_cycle
547 | (cmd & NDCB0_CMD1_MASK);
548 else
549 info->ndcb0 |= NDCB0_CMD_TYPE(0)
550 | NDCB0_DBC
551 | addr_cycle
552 | cmd;
fe69af00 553
fe69af00 554 case NAND_CMD_SEQIN:
4eb2da89 555 /* small page addr setting */
d456882b 556 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
4eb2da89
LW		 557 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
558 | (column & 0xFF);
559
560 info->ndcb2 = 0;
561 } else {
562 info->ndcb1 = ((page_addr & 0xFFFF) << 16)
563 | (column & 0xFFFF);
564
565 if (page_addr & 0xFF0000)
566 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
567 else
568 info->ndcb2 = 0;
569 }
570
fe69af00 571 info->buf_count = mtd->writesize + mtd->oobsize;
4eb2da89 572 memset(info->data_buff, 0xFF, info->buf_count);
fe69af00 573
fe69af00 574 break;
4eb2da89 575
fe69af00 576 case NAND_CMD_PAGEPROG:
4eb2da89
LW		 577 if (is_buf_blank(info->data_buff,
578 (mtd->writesize + mtd->oobsize))) {
579 exec_cmd = 0;
580 break;
581 }
fe69af00 582
d456882b 583 cmd = host->cmdset->program;
4eb2da89
LW		 584 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
585 | NDCB0_AUTO_RS
586 | NDCB0_ST_ROW_EN
587 | NDCB0_DBC
588 | cmd
589 | addr_cycle;
fe69af00 590 break;
4eb2da89 591
fe69af00 592 case NAND_CMD_READID:
d456882b
LW		 593 cmd = host->cmdset->read_id;
594 info->buf_count = host->read_id_bytes;
4eb2da89
LW		 595 info->ndcb0 |= NDCB0_CMD_TYPE(3)
596 | NDCB0_ADDR_CYC(1)
597 | cmd;
598
599 info->data_size = 8;
600 break;
fe69af00 601 case NAND_CMD_STATUS:
d456882b 602 cmd = host->cmdset->read_status;
4eb2da89
LW		 603 info->buf_count = 1;
604 info->ndcb0 |= NDCB0_CMD_TYPE(4)
605 | NDCB0_ADDR_CYC(1)
606 | cmd;
607
608 info->data_size = 8;
609 break;
610
611 case NAND_CMD_ERASE1:
d456882b 612 cmd = host->cmdset->erase;
4eb2da89
LW		 613 info->ndcb0 |= NDCB0_CMD_TYPE(2)
614 | NDCB0_AUTO_RS
615 | NDCB0_ADDR_CYC(3)
616 | NDCB0_DBC
617 | cmd;
618 info->ndcb1 = page_addr;
619 info->ndcb2 = 0;
620
fe69af00 621 break;
622 case NAND_CMD_RESET:
d456882b 623 cmd = host->cmdset->reset;
4eb2da89
LW		 624 info->ndcb0 |= NDCB0_CMD_TYPE(5)
625 | cmd;
626
627 break;
628
629 case NAND_CMD_ERASE2:
630 exec_cmd = 0;
fe69af00 631 break;
4eb2da89 632
fe69af00 633 default:
4eb2da89 634 exec_cmd = 0;
da675b4e
LW		 635 dev_err(&info->pdev->dev, "non-supported command %x\n",
636 command);
fe69af00 637 break;
638 }
639
4eb2da89
LW		 640 return exec_cmd;
641}
642
643static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
644 int column, int page_addr)
645{
d456882b
LW		 646 struct pxa3xx_nand_host *host = mtd->priv;
647 struct pxa3xx_nand_info *info = host->info_data;
4eb2da89
LW		 648 int ret, exec_cmd;
649
650 /*
651 * if this is a x16 device ,then convert the input
652 * "byte" address into a "word" address appropriate
653 * for indexing a word-oriented device
654 */
d456882b 655 if (host->reg_ndcr & NDCR_DWIDTH_M)
4eb2da89
LW		 656 column /= 2;
657
f3c8cfc2
LW		 658 /*
659 * There may be different NAND chip hooked to
660 * different chip select, so check whether
661 * chip select has been changed, if yes, reset the timing
662 */
663 if (info->cs != host->cs) {
664 info->cs = host->cs;
665 nand_writel(info, NDTR0CS0, host->ndtr0cs0);
666 nand_writel(info, NDTR1CS0, host->ndtr1cs0);
667 }
668
d456882b 669 info->state = STATE_PREPARED;
4eb2da89 670 exec_cmd = prepare_command_pool(info, command, column, page_addr);
f8155a40
LW		 671 if (exec_cmd) {
672 init_completion(&info->cmd_complete);
673 pxa3xx_nand_start(info);
674
675 ret = wait_for_completion_timeout(&info->cmd_complete,
676 CHIP_DELAY_TIMEOUT);
677 if (!ret) {
da675b4e 678 dev_err(&info->pdev->dev, "Wait time out!!!\n");
f8155a40
LW		 679 /* Stop State Machine for next command cycle */
680 pxa3xx_nand_stop(info);
681 }
f8155a40 682 }
d456882b 683 info->state = STATE_IDLE;
f8155a40
LW		 684}
685
686static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
1fbb938d 687 struct nand_chip *chip, const uint8_t *buf, int oob_required)
f8155a40
LW		 688{
689 chip->write_buf(mtd, buf, mtd->writesize);
690 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
691}
692
693static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
1fbb938d
BN		 694 struct nand_chip *chip, uint8_t *buf, int oob_required,
695 int page)
f8155a40 696{
d456882b
LW		 697 struct pxa3xx_nand_host *host = mtd->priv;
698 struct pxa3xx_nand_info *info = host->info_data;
f8155a40
LW		 699
700 chip->read_buf(mtd, buf, mtd->writesize);
701 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
702
703 if (info->retcode == ERR_SBERR) {
704 switch (info->use_ecc) {
705 case 1:
706 mtd->ecc_stats.corrected++;
707 break;
708 case 0:
709 default:
710 break;
711 }
712 } else if (info->retcode == ERR_DBERR) {
713 /*
714 * for blank page (all 0xff), HW will calculate its ECC as
715 * 0, which is different from the ECC information within
716 * OOB, ignore such double bit errors
717 */
718 if (is_buf_blank(buf, mtd->writesize))
543e32d5
DM		 719 info->retcode = ERR_NONE;
720 else
f8155a40 721 mtd->ecc_stats.failed++;
fe69af00 722 }
f8155a40
LW		 723
724 return 0;
fe69af00 725}
726
727static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
728{
d456882b
LW		 729 struct pxa3xx_nand_host *host = mtd->priv;
730 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 731 char retval = 0xFF;
732
733 if (info->buf_start < info->buf_count)
734 /* Has just send a new command? */
735 retval = info->data_buff[info->buf_start++];
736
737 return retval;
738}
739
740static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
741{
d456882b
LW		 742 struct pxa3xx_nand_host *host = mtd->priv;
743 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 744 u16 retval = 0xFFFF;
745
746 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
747 retval = *((u16 *)(info->data_buff+info->buf_start));
748 info->buf_start += 2;
749 }
750 return retval;
751}
752
753static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
754{
d456882b
LW		 755 struct pxa3xx_nand_host *host = mtd->priv;
756 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 757 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
758
759 memcpy(buf, info->data_buff + info->buf_start, real_len);
760 info->buf_start += real_len;
761}
762
763static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
764 const uint8_t *buf, int len)
765{
d456882b
LW		 766 struct pxa3xx_nand_host *host = mtd->priv;
767 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 768 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
769
770 memcpy(info->data_buff + info->buf_start, buf, real_len);
771 info->buf_start += real_len;
772}
773
774static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
775 const uint8_t *buf, int len)
776{
777 return 0;
778}
779
780static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
781{
782 return;
783}
784
785static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
786{
d456882b
LW		 787 struct pxa3xx_nand_host *host = mtd->priv;
788 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 789
790 /* pxa3xx_nand_send_command has waited for command complete */
791 if (this->state == FL_WRITING || this->state == FL_ERASING) {
792 if (info->retcode == ERR_NONE)
793 return 0;
794 else {
795 /*
796 * any error make it return 0x01 which will tell
797 * the caller the erase and write fail
798 */
799 return 0x01;
800 }
801 }
802
803 return 0;
804}
805
fe69af00 806static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
c8c17c88 807 const struct pxa3xx_nand_flash *f)
fe69af00 808{
809 struct platform_device *pdev = info->pdev;
810 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
f3c8cfc2 811 struct pxa3xx_nand_host *host = info->host[info->cs];
f8155a40 812 uint32_t ndcr = 0x0; /* enable all interrupts */
fe69af00 813
da675b4e
LW		 814 if (f->page_size != 2048 && f->page_size != 512) {
815 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
fe69af00 816 return -EINVAL;
da675b4e 817 }
fe69af00 818
da675b4e
LW		 819 if (f->flash_width != 16 && f->flash_width != 8) {
820 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
fe69af00 821 return -EINVAL;
da675b4e 822 }
fe69af00 823
824 /* calculate flash information */
d456882b
LW		 825 host->cmdset = &default_cmdset;
826 host->page_size = f->page_size;
827 host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
fe69af00 828
829 /* calculate addressing information */
d456882b 830 host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
fe69af00 831
832 if (f->num_blocks * f->page_per_block > 65536)
d456882b 833 host->row_addr_cycles = 3;
fe69af00 834 else
d456882b 835 host->row_addr_cycles = 2;
fe69af00 836
837 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
d456882b 838 ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
fe69af00 839 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
840 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
841 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
842 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
843
d456882b 844 ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
fe69af00 845 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
846
d456882b 847 host->reg_ndcr = ndcr;
fe69af00 848
d456882b 849 pxa3xx_nand_set_timing(host, f->timing);
fe69af00 850 return 0;
851}
852
f271049e
MR		 853static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
854{
f3c8cfc2
LW		 855 /*
856 * We set 0 by hard coding here, for we don't support keep_config
857 * when there is more than one chip attached to the controller
858 */
859 struct pxa3xx_nand_host *host = info->host[0];
f271049e 860 uint32_t ndcr = nand_readl(info, NDCR);
f271049e 861
d456882b
LW		 862 if (ndcr & NDCR_PAGE_SZ) {
863 host->page_size = 2048;
864 host->read_id_bytes = 4;
865 } else {
866 host->page_size = 512;
867 host->read_id_bytes = 2;
868 }
869
870 host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
871 host->cmdset = &default_cmdset;
872
873 host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
874 host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
f271049e
MR		 875
876 return 0;
877}
878
fe69af00 879/* the maximum possible buffer size for large page with OOB data
880 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
881 * data buffer and the DMA descriptor
882 */
883#define MAX_BUFF_SIZE PAGE_SIZE
884
885static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
886{
887 struct platform_device *pdev = info->pdev;
888 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
889
890 if (use_dma == 0) {
891 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
892 if (info->data_buff == NULL)
893 return -ENOMEM;
894 return 0;
895 }
896
897 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
898 &info->data_buff_phys, GFP_KERNEL);
899 if (info->data_buff == NULL) {
900 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
901 return -ENOMEM;
902 }
903
fe69af00 904 info->data_desc = (void *)info->data_buff + data_desc_offset;
905 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
906
907 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
908 pxa3xx_nand_data_dma_irq, info);
909 if (info->data_dma_ch < 0) {
910 dev_err(&pdev->dev, "failed to request data dma\n");
d456882b 911 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
fe69af00 912 info->data_buff, info->data_buff_phys);
913 return info->data_dma_ch;
914 }
915
916 return 0;
917}
918
401e67e2
LW		 919static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
920{
f3c8cfc2 921 struct mtd_info *mtd;
d456882b 922 int ret;
f3c8cfc2 923 mtd = info->host[info->cs]->mtd;
401e67e2 924 /* use the common timing to make a try */
d456882b
LW		 925 ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
926 if (ret)
927 return ret;
928
929 pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
401e67e2 930 if (info->is_ready)
401e67e2 931 return 0;
d456882b
LW		 932
933 return -ENODEV;
401e67e2 934}
fe69af00 935
401e67e2 936static int pxa3xx_nand_scan(struct mtd_info *mtd)
fe69af00 937{
d456882b
LW		 938 struct pxa3xx_nand_host *host = mtd->priv;
939 struct pxa3xx_nand_info *info = host->info_data;
401e67e2
LW		 940 struct platform_device *pdev = info->pdev;
941 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
0fab028b 942 struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
401e67e2
LW		 943 const struct pxa3xx_nand_flash *f = NULL;
944 struct nand_chip *chip = mtd->priv;
945 uint32_t id = -1;
4332c116 946 uint64_t chipsize;
401e67e2
LW		 947 int i, ret, num;
948
949 if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
4332c116 950 goto KEEP_CONFIG;
401e67e2
LW		 951
952 ret = pxa3xx_nand_sensing(info);
d456882b 953 if (ret) {
f3c8cfc2
LW		 954 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
955 info->cs);
401e67e2 956
d456882b 957 return ret;
401e67e2
LW		 958 }
959
960 chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
961 id = *((uint16_t *)(info->data_buff));
962 if (id != 0)
da675b4e 963 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
401e67e2 964 else {
da675b4e
LW		 965 dev_warn(&info->pdev->dev,
966 "Read out ID 0, potential timing set wrong!!\n");
401e67e2
LW		 967
968 return -EINVAL;
969 }
970
971 num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
972 for (i = 0; i < num; i++) {
973 if (i < pdata->num_flash)
974 f = pdata->flash + i;
975 else
976 f = &builtin_flash_types[i - pdata->num_flash + 1];
977
978 /* find the chip in default list */
4332c116 979 if (f->chip_id == id)
401e67e2 980 break;
401e67e2
LW		 981 }
982
4332c116 983 if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
da675b4e 984 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
401e67e2
LW		 985
986 return -EINVAL;
987 }
988
d456882b
LW		 989 ret = pxa3xx_nand_config_flash(info, f);
990 if (ret) {
991 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
992 return ret;
993 }
994
4332c116
LW		 995 pxa3xx_flash_ids[0].name = f->name;
996 pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff;
997 pxa3xx_flash_ids[0].pagesize = f->page_size;
998 chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
999 pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1000 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1001 if (f->flash_width == 16)
1002 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
0fab028b
LW		 1003 pxa3xx_flash_ids[1].name = NULL;
1004 def = pxa3xx_flash_ids;
4332c116 1005KEEP_CONFIG:
d456882b
LW		 1006 chip->ecc.mode = NAND_ECC_HW;
1007 chip->ecc.size = host->page_size;
6a918bad 1008 chip->ecc.strength = 1;
d456882b 1009
d456882b
LW		 1010 chip->options |= NAND_NO_READRDY;
1011 if (host->reg_ndcr & NDCR_DWIDTH_M)
1012 chip->options |= NAND_BUSWIDTH_16;
1013
0fab028b 1014 if (nand_scan_ident(mtd, 1, def))
4332c116
LW		 1015 return -ENODEV;
1016 /* calculate addressing information */
d456882b
LW		 1017 if (mtd->writesize >= 2048)
1018 host->col_addr_cycles = 2;
1019 else
1020 host->col_addr_cycles = 1;
1021
4332c116
LW		 1022 info->oob_buff = info->data_buff + mtd->writesize;
1023 if ((mtd->size >> chip->page_shift) > 65536)
d456882b 1024 host->row_addr_cycles = 3;
4332c116 1025 else
d456882b 1026 host->row_addr_cycles = 2;
fe69af00 1027
d456882b 1028 mtd->name = mtd_names[0];
401e67e2 1029 return nand_scan_tail(mtd);
fe69af00 1030}
1031
d456882b 1032static int alloc_nand_resource(struct platform_device *pdev)
fe69af00 1033{
f3c8cfc2 1034 struct pxa3xx_nand_platform_data *pdata;
fe69af00 1035 struct pxa3xx_nand_info *info;
d456882b 1036 struct pxa3xx_nand_host *host;
6e308f87 1037 struct nand_chip *chip = NULL;
fe69af00 1038 struct mtd_info *mtd;
1039 struct resource *r;
f3c8cfc2 1040 int ret, irq, cs;
fe69af00 1041
f3c8cfc2
LW		 1042 pdata = pdev->dev.platform_data;
1043 info = kzalloc(sizeof(*info) + (sizeof(*mtd) +
1044 sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
d456882b 1045 if (!info) {
fe69af00 1046 dev_err(&pdev->dev, "failed to allocate memory\n");
d456882b 1047 return -ENOMEM;
a1c06ee1 1048 }
fe69af00 1049
fe69af00 1050 info->pdev = pdev;
f3c8cfc2
LW		 1051 for (cs = 0; cs < pdata->num_cs; cs++) {
1052 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1053 (sizeof(*mtd) + sizeof(*host)) * cs);
1054 chip = (struct nand_chip *)(&mtd[1]);
1055 host = (struct pxa3xx_nand_host *)chip;
1056 info->host[cs] = host;
1057 host->mtd = mtd;
1058 host->cs = cs;
1059 host->info_data = info;
1060 mtd->priv = host;
1061 mtd->owner = THIS_MODULE;
1062
1063 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
1064 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
1065 chip->controller = &info->controller;
1066 chip->waitfunc = pxa3xx_nand_waitfunc;
1067 chip->select_chip = pxa3xx_nand_select_chip;
1068 chip->cmdfunc = pxa3xx_nand_cmdfunc;
1069 chip->read_word = pxa3xx_nand_read_word;
1070 chip->read_byte = pxa3xx_nand_read_byte;
1071 chip->read_buf = pxa3xx_nand_read_buf;
1072 chip->write_buf = pxa3xx_nand_write_buf;
1073 chip->verify_buf = pxa3xx_nand_verify_buf;
1074 }
401e67e2
LW		 1075
1076 spin_lock_init(&chip->controller->lock);
1077 init_waitqueue_head(&chip->controller->wq);
e0d8b13a 1078 info->clk = clk_get(&pdev->dev, NULL);
fe69af00 1079 if (IS_ERR(info->clk)) {
1080 dev_err(&pdev->dev, "failed to get nand clock\n");
1081 ret = PTR_ERR(info->clk);
1082 goto fail_free_mtd;
1083 }
1084 clk_enable(info->clk);
1085
1e7ba630
DM		 1086 /*
1087 * This is a dirty hack to make this driver work from devicetree
1088 * bindings. It can be removed once we have a prober DMA controller
1089 * framework for DT.
1090 */
1091 if (pdev->dev.of_node && cpu_is_pxa3xx()) {
1092 info->drcmr_dat = 97;
1093 info->drcmr_cmd = 99;
1094 } else {
1095 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1096 if (r == NULL) {
1097 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1098 ret = -ENXIO;
1099 goto fail_put_clk;
1100 }
1101 info->drcmr_dat = r->start;
fe69af00 1102
1e7ba630
DM		 1103 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1104 if (r == NULL) {
1105 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1106 ret = -ENXIO;
1107 goto fail_put_clk;
1108 }
1109 info->drcmr_cmd = r->start;
fe69af00 1110 }
fe69af00 1111
1112 irq = platform_get_irq(pdev, 0);
1113 if (irq < 0) {
1114 dev_err(&pdev->dev, "no IRQ resource defined\n");
1115 ret = -ENXIO;
1116 goto fail_put_clk;
1117 }
1118
1119 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1120 if (r == NULL) {
1121 dev_err(&pdev->dev, "no IO memory resource defined\n");
1122 ret = -ENODEV;
1123 goto fail_put_clk;
1124 }
1125
b2ed3680 1126 r = request_mem_region(r->start, resource_size(r), pdev->name);
fe69af00 1127 if (r == NULL) {
1128 dev_err(&pdev->dev, "failed to request memory resource\n");
1129 ret = -EBUSY;
1130 goto fail_put_clk;
1131 }
1132
b2ed3680 1133 info->mmio_base = ioremap(r->start, resource_size(r));
fe69af00 1134 if (info->mmio_base == NULL) {
1135 dev_err(&pdev->dev, "ioremap() failed\n");
1136 ret = -ENODEV;
1137 goto fail_free_res;
1138 }
8638fac8 1139 info->mmio_phys = r->start;
fe69af00 1140
1141 ret = pxa3xx_nand_init_buff(info);
1142 if (ret)
1143 goto fail_free_io;
1144
346e1259
HZ		 1145 /* initialize all interrupts to be disabled */
1146 disable_int(info, NDSR_MASK);
1147
dbf5986a
HZ		 1148 ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1149 pdev->name, info);
fe69af00 1150 if (ret < 0) {
1151 dev_err(&pdev->dev, "failed to request IRQ\n");
1152 goto fail_free_buf;
1153 }
1154
e353a20a 1155 platform_set_drvdata(pdev, info);
fe69af00 1156
d456882b 1157 return 0;
fe69af00 1158
fe69af00 1159fail_free_buf:
401e67e2 1160 free_irq(irq, info);
fe69af00 1161 if (use_dma) {
1162 pxa_free_dma(info->data_dma_ch);
d456882b 1163 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
fe69af00 1164 info->data_buff, info->data_buff_phys);
1165 } else
1166 kfree(info->data_buff);
1167fail_free_io:
1168 iounmap(info->mmio_base);
1169fail_free_res:
b2ed3680 1170 release_mem_region(r->start, resource_size(r));
fe69af00 1171fail_put_clk:
1172 clk_disable(info->clk);
1173 clk_put(info->clk);
1174fail_free_mtd:
d456882b
LW		 1175 kfree(info);
1176 return ret;
fe69af00 1177}
1178
1179static int pxa3xx_nand_remove(struct platform_device *pdev)
1180{
e353a20a 1181 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
f3c8cfc2 1182 struct pxa3xx_nand_platform_data *pdata;
82a72d10 1183 struct resource *r;
f3c8cfc2 1184 int irq, cs;
fe69af00 1185
d456882b
LW		 1186 if (!info)
1187 return 0;
1188
f3c8cfc2 1189 pdata = pdev->dev.platform_data;
fe69af00 1190 platform_set_drvdata(pdev, NULL);
1191
dbf5986a
HZ		 1192 irq = platform_get_irq(pdev, 0);
1193 if (irq >= 0)
1194 free_irq(irq, info);
fe69af00 1195 if (use_dma) {
1196 pxa_free_dma(info->data_dma_ch);
d456882b 1197 dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE,
fe69af00 1198 info->data_buff, info->data_buff_phys);
1199 } else
1200 kfree(info->data_buff);
82a72d10
MR		 1201
1202 iounmap(info->mmio_base);
1203 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1204 release_mem_region(r->start, resource_size(r));
1205
1206 clk_disable(info->clk);
1207 clk_put(info->clk);
1208
f3c8cfc2
LW		 1209 for (cs = 0; cs < pdata->num_cs; cs++)
1210 nand_release(info->host[cs]->mtd);
d456882b 1211 kfree(info);
fe69af00 1212 return 0;
1213}
1214
1e7ba630
DM		 1215#ifdef CONFIG_OF
1216static struct of_device_id pxa3xx_nand_dt_ids[] = {
1217 { .compatible = "marvell,pxa3xx-nand" },
1218 {}
1219};
1220MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1221
1222static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1223{
1224 struct pxa3xx_nand_platform_data *pdata;
1225 struct device_node *np = pdev->dev.of_node;
1226 const struct of_device_id *of_id =
1227 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1228
1229 if (!of_id)
1230 return 0;
1231
1232 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1233 if (!pdata)
1234 return -ENOMEM;
1235
1236 if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1237 pdata->enable_arbiter = 1;
1238 if (of_get_property(np, "marvell,nand-keep-config", NULL))
1239 pdata->keep_config = 1;
1240 of_property_read_u32(np, "num-cs", &pdata->num_cs);
1241
1242 pdev->dev.platform_data = pdata;
1243
1244 return 0;
1245}
1246#else
6e308f87 1247static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1e7ba630
DM		 1248{
1249 return 0;
1250}
1251#endif
1252
e353a20a
LW		 1253static int pxa3xx_nand_probe(struct platform_device *pdev)
1254{
1255 struct pxa3xx_nand_platform_data *pdata;
1e7ba630 1256 struct mtd_part_parser_data ppdata = {};
e353a20a 1257 struct pxa3xx_nand_info *info;
f3c8cfc2 1258 int ret, cs, probe_success;
e353a20a 1259
1e7ba630
DM		 1260 ret = pxa3xx_nand_probe_dt(pdev);
1261 if (ret)
1262 return ret;
1263
e353a20a
LW		 1264 pdata = pdev->dev.platform_data;
1265 if (!pdata) {
1266 dev_err(&pdev->dev, "no platform data defined\n");
1267 return -ENODEV;
1268 }
1269
d456882b
LW		 1270 ret = alloc_nand_resource(pdev);
1271 if (ret) {
1272 dev_err(&pdev->dev, "alloc nand resource failed\n");
1273 return ret;
1274 }
e353a20a 1275
d456882b 1276 info = platform_get_drvdata(pdev);
f3c8cfc2
LW		 1277 probe_success = 0;
1278 for (cs = 0; cs < pdata->num_cs; cs++) {
1279 info->cs = cs;
1280 ret = pxa3xx_nand_scan(info->host[cs]->mtd);
1281 if (ret) {
1282 dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1283 cs);
1284 continue;
1285 }
1286
1e7ba630 1287 ppdata.of_node = pdev->dev.of_node;
42d7fbe2 1288 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
1e7ba630 1289 &ppdata, pdata->parts[cs],
42d7fbe2 1290 pdata->nr_parts[cs]);
f3c8cfc2
LW		 1291 if (!ret)
1292 probe_success = 1;
1293 }
1294
1295 if (!probe_success) {
e353a20a
LW		 1296 pxa3xx_nand_remove(pdev);
1297 return -ENODEV;
1298 }
1299
f3c8cfc2 1300 return 0;
e353a20a
LW		 1301}
1302
fe69af00 1303#ifdef CONFIG_PM
1304static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1305{
e353a20a 1306 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
f3c8cfc2
LW		 1307 struct pxa3xx_nand_platform_data *pdata;
1308 struct mtd_info *mtd;
1309 int cs;
fe69af00 1310
f3c8cfc2 1311 pdata = pdev->dev.platform_data;
f8155a40 1312 if (info->state) {
fe69af00 1313 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1314 return -EAGAIN;
1315 }
1316
f3c8cfc2
LW		 1317 for (cs = 0; cs < pdata->num_cs; cs++) {
1318 mtd = info->host[cs]->mtd;
3fe4bae8 1319 mtd_suspend(mtd);
f3c8cfc2
LW		 1320 }
1321
fe69af00 1322 return 0;
1323}
1324
1325static int pxa3xx_nand_resume(struct platform_device *pdev)
1326{
e353a20a 1327 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
f3c8cfc2
LW		 1328 struct pxa3xx_nand_platform_data *pdata;
1329 struct mtd_info *mtd;
1330 int cs;
051fc41c 1331
f3c8cfc2 1332 pdata = pdev->dev.platform_data;
051fc41c
LW		 1333 /* We don't want to handle interrupt without calling mtd routine */
1334 disable_int(info, NDCR_INT_MASK);
fe69af00 1335
f3c8cfc2
LW		 1336 /*
1337 * Directly set the chip select to a invalid value,
1338 * then the driver would reset the timing according
1339 * to current chip select at the beginning of cmdfunc
1340 */
1341 info->cs = 0xff;
fe69af00 1342
051fc41c
LW		 1343 /*
1344 * As the spec says, the NDSR would be updated to 0x1800 when
1345 * doing the nand_clk disable/enable.
1346 * To prevent it damaging state machine of the driver, clear
1347 * all status before resume
1348 */
1349 nand_writel(info, NDSR, NDSR_MASK);
f3c8cfc2
LW		 1350 for (cs = 0; cs < pdata->num_cs; cs++) {
1351 mtd = info->host[cs]->mtd;
ead995f8 1352 mtd_resume(mtd);
f3c8cfc2
LW		 1353 }
1354
18c81b18 1355 return 0;
fe69af00 1356}
1357#else
1358#define pxa3xx_nand_suspend NULL
1359#define pxa3xx_nand_resume NULL
1360#endif
1361
1362static struct platform_driver pxa3xx_nand_driver = {
1363 .driver = {
1364 .name = "pxa3xx-nand",
1e7ba630 1365 .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
fe69af00 1366 },
1367 .probe = pxa3xx_nand_probe,
1368 .remove = pxa3xx_nand_remove,
1369 .suspend = pxa3xx_nand_suspend,
1370 .resume = pxa3xx_nand_resume,
1371};
1372
f99640de 1373module_platform_driver(pxa3xx_nand_driver);
fe69af00 1374
1375MODULE_LICENSE("GPL");
1376MODULE_DESCRIPTION("PXA3xx NAND controller driver");
Linux kernel - Deliverables
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