Commit | Line | Data |
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fe69af00 | 1 | /* |
2 | * drivers/mtd/nand/pxa3xx_nand.c | |
3 | * | |
4 | * Copyright © 2005 Intel Corporation | |
5 | * Copyright © 2006 Marvell International Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
de484a38 EG |
10 | * |
11 | * See Documentation/mtd/nand/pxa3xx-nand.txt for more details. | |
fe69af00 | 12 | */ |
13 | ||
a88bdbb5 | 14 | #include <linux/kernel.h> |
fe69af00 | 15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/mtd/mtd.h> | |
22 | #include <linux/mtd/nand.h> | |
23 | #include <linux/mtd/partitions.h> | |
a1c06ee1 DW |
24 | #include <linux/io.h> |
25 | #include <linux/irq.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
1e7ba630 DM |
27 | #include <linux/of.h> |
28 | #include <linux/of_device.h> | |
fe69af00 | 29 | |
f4db2e3a EG |
30 | #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP) |
31 | #define ARCH_HAS_DMA | |
32 | #endif | |
33 | ||
34 | #ifdef ARCH_HAS_DMA | |
afb5b5c9 | 35 | #include <mach/dma.h> |
f4db2e3a EG |
36 | #endif |
37 | ||
293b2da1 | 38 | #include <linux/platform_data/mtd-nand-pxa3xx.h> |
fe69af00 | 39 | |
40 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) | |
f8155a40 | 41 | #define NAND_STOP_DELAY (2 * HZ/50) |
4eb2da89 | 42 | #define PAGE_CHUNK_SIZE (2048) |
fe69af00 | 43 | |
62e8b851 EG |
44 | /* |
45 | * Define a buffer size for the initial command that detects the flash device: | |
46 | * STATUS, READID and PARAM. The largest of these is the PARAM command, | |
47 | * needing 256 bytes. | |
48 | */ | |
49 | #define INIT_BUFFER_SIZE 256 | |
50 | ||
fe69af00 | 51 | /* registers and bit definitions */ |
52 | #define NDCR (0x00) /* Control register */ | |
53 | #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ | |
54 | #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */ | |
55 | #define NDSR (0x14) /* Status Register */ | |
56 | #define NDPCR (0x18) /* Page Count Register */ | |
57 | #define NDBDR0 (0x1C) /* Bad Block Register 0 */ | |
58 | #define NDBDR1 (0x20) /* Bad Block Register 1 */ | |
59 | #define NDDB (0x40) /* Data Buffer */ | |
60 | #define NDCB0 (0x48) /* Command Buffer0 */ | |
61 | #define NDCB1 (0x4C) /* Command Buffer1 */ | |
62 | #define NDCB2 (0x50) /* Command Buffer2 */ | |
63 | ||
64 | #define NDCR_SPARE_EN (0x1 << 31) | |
65 | #define NDCR_ECC_EN (0x1 << 30) | |
66 | #define NDCR_DMA_EN (0x1 << 29) | |
67 | #define NDCR_ND_RUN (0x1 << 28) | |
68 | #define NDCR_DWIDTH_C (0x1 << 27) | |
69 | #define NDCR_DWIDTH_M (0x1 << 26) | |
70 | #define NDCR_PAGE_SZ (0x1 << 24) | |
71 | #define NDCR_NCSX (0x1 << 23) | |
72 | #define NDCR_ND_MODE (0x3 << 21) | |
73 | #define NDCR_NAND_MODE (0x0) | |
74 | #define NDCR_CLR_PG_CNT (0x1 << 20) | |
f8155a40 | 75 | #define NDCR_STOP_ON_UNCOR (0x1 << 19) |
fe69af00 | 76 | #define NDCR_RD_ID_CNT_MASK (0x7 << 16) |
77 | #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) | |
78 | ||
79 | #define NDCR_RA_START (0x1 << 15) | |
80 | #define NDCR_PG_PER_BLK (0x1 << 14) | |
81 | #define NDCR_ND_ARB_EN (0x1 << 12) | |
f8155a40 | 82 | #define NDCR_INT_MASK (0xFFF) |
fe69af00 | 83 | |
84 | #define NDSR_MASK (0xfff) | |
f8155a40 LW |
85 | #define NDSR_RDY (0x1 << 12) |
86 | #define NDSR_FLASH_RDY (0x1 << 11) | |
fe69af00 | 87 | #define NDSR_CS0_PAGED (0x1 << 10) |
88 | #define NDSR_CS1_PAGED (0x1 << 9) | |
89 | #define NDSR_CS0_CMDD (0x1 << 8) | |
90 | #define NDSR_CS1_CMDD (0x1 << 7) | |
91 | #define NDSR_CS0_BBD (0x1 << 6) | |
92 | #define NDSR_CS1_BBD (0x1 << 5) | |
93 | #define NDSR_DBERR (0x1 << 4) | |
94 | #define NDSR_SBERR (0x1 << 3) | |
95 | #define NDSR_WRDREQ (0x1 << 2) | |
96 | #define NDSR_RDDREQ (0x1 << 1) | |
97 | #define NDSR_WRCMDREQ (0x1) | |
98 | ||
41a63430 | 99 | #define NDCB0_LEN_OVRD (0x1 << 28) |
4eb2da89 | 100 | #define NDCB0_ST_ROW_EN (0x1 << 26) |
fe69af00 | 101 | #define NDCB0_AUTO_RS (0x1 << 25) |
102 | #define NDCB0_CSEL (0x1 << 24) | |
103 | #define NDCB0_CMD_TYPE_MASK (0x7 << 21) | |
104 | #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) | |
105 | #define NDCB0_NC (0x1 << 20) | |
106 | #define NDCB0_DBC (0x1 << 19) | |
107 | #define NDCB0_ADDR_CYC_MASK (0x7 << 16) | |
108 | #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) | |
109 | #define NDCB0_CMD2_MASK (0xff << 8) | |
110 | #define NDCB0_CMD1_MASK (0xff) | |
111 | #define NDCB0_ADDR_CYC_SHIFT (16) | |
112 | ||
fe69af00 | 113 | /* macros for registers read/write */ |
114 | #define nand_writel(info, off, val) \ | |
115 | __raw_writel((val), (info)->mmio_base + (off)) | |
116 | ||
117 | #define nand_readl(info, off) \ | |
118 | __raw_readl((info)->mmio_base + (off)) | |
119 | ||
120 | /* error code and state */ | |
121 | enum { | |
122 | ERR_NONE = 0, | |
123 | ERR_DMABUSERR = -1, | |
124 | ERR_SENDCMD = -2, | |
125 | ERR_DBERR = -3, | |
126 | ERR_BBERR = -4, | |
223cf6c3 | 127 | ERR_SBERR = -5, |
fe69af00 | 128 | }; |
129 | ||
130 | enum { | |
f8155a40 | 131 | STATE_IDLE = 0, |
d456882b | 132 | STATE_PREPARED, |
fe69af00 | 133 | STATE_CMD_HANDLE, |
134 | STATE_DMA_READING, | |
135 | STATE_DMA_WRITING, | |
136 | STATE_DMA_DONE, | |
137 | STATE_PIO_READING, | |
138 | STATE_PIO_WRITING, | |
f8155a40 LW |
139 | STATE_CMD_DONE, |
140 | STATE_READY, | |
fe69af00 | 141 | }; |
142 | ||
c0f3b864 EG |
143 | enum pxa3xx_nand_variant { |
144 | PXA3XX_NAND_VARIANT_PXA, | |
145 | PXA3XX_NAND_VARIANT_ARMADA370, | |
146 | }; | |
147 | ||
d456882b LW |
148 | struct pxa3xx_nand_host { |
149 | struct nand_chip chip; | |
d456882b LW |
150 | struct mtd_info *mtd; |
151 | void *info_data; | |
152 | ||
153 | /* page size of attached chip */ | |
154 | unsigned int page_size; | |
155 | int use_ecc; | |
f3c8cfc2 | 156 | int cs; |
fe69af00 | 157 | |
d456882b LW |
158 | /* calculated from pxa3xx_nand_flash data */ |
159 | unsigned int col_addr_cycles; | |
160 | unsigned int row_addr_cycles; | |
161 | size_t read_id_bytes; | |
162 | ||
d456882b LW |
163 | }; |
164 | ||
165 | struct pxa3xx_nand_info { | |
401e67e2 | 166 | struct nand_hw_control controller; |
fe69af00 | 167 | struct platform_device *pdev; |
fe69af00 | 168 | |
169 | struct clk *clk; | |
170 | void __iomem *mmio_base; | |
8638fac8 | 171 | unsigned long mmio_phys; |
d456882b | 172 | struct completion cmd_complete; |
fe69af00 | 173 | |
174 | unsigned int buf_start; | |
175 | unsigned int buf_count; | |
62e8b851 | 176 | unsigned int buf_size; |
fe69af00 | 177 | |
178 | /* DMA information */ | |
179 | int drcmr_dat; | |
180 | int drcmr_cmd; | |
181 | ||
182 | unsigned char *data_buff; | |
18c81b18 | 183 | unsigned char *oob_buff; |
fe69af00 | 184 | dma_addr_t data_buff_phys; |
fe69af00 | 185 | int data_dma_ch; |
186 | struct pxa_dma_desc *data_desc; | |
187 | dma_addr_t data_desc_addr; | |
188 | ||
f3c8cfc2 | 189 | struct pxa3xx_nand_host *host[NUM_CHIP_SELECT]; |
fe69af00 | 190 | unsigned int state; |
191 | ||
c0f3b864 EG |
192 | /* |
193 | * This driver supports NFCv1 (as found in PXA SoC) | |
194 | * and NFCv2 (as found in Armada 370/XP SoC). | |
195 | */ | |
196 | enum pxa3xx_nand_variant variant; | |
197 | ||
f3c8cfc2 | 198 | int cs; |
fe69af00 | 199 | int use_ecc; /* use HW ECC ? */ |
200 | int use_dma; /* use DMA ? */ | |
5bb653e8 | 201 | int use_spare; /* use spare ? */ |
401e67e2 | 202 | int is_ready; |
fe69af00 | 203 | |
18c81b18 LW |
204 | unsigned int page_size; /* page size of attached chip */ |
205 | unsigned int data_size; /* data size in FIFO */ | |
d456882b | 206 | unsigned int oob_size; |
fe69af00 | 207 | int retcode; |
fe69af00 | 208 | |
48cf7efa EG |
209 | /* cached register value */ |
210 | uint32_t reg_ndcr; | |
211 | uint32_t ndtr0cs0; | |
212 | uint32_t ndtr1cs0; | |
213 | ||
fe69af00 | 214 | /* generated NDCBx register values */ |
215 | uint32_t ndcb0; | |
216 | uint32_t ndcb1; | |
217 | uint32_t ndcb2; | |
3a1a344a | 218 | uint32_t ndcb3; |
fe69af00 | 219 | }; |
220 | ||
90ab5ee9 | 221 | static bool use_dma = 1; |
fe69af00 | 222 | module_param(use_dma, bool, 0444); |
25985edc | 223 | MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW"); |
fe69af00 | 224 | |
c1f82478 | 225 | static struct pxa3xx_nand_timing timing[] = { |
227a886c LW |
226 | { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, |
227 | { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, | |
228 | { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, | |
229 | { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, | |
d3490dfd HZ |
230 | }; |
231 | ||
c1f82478 | 232 | static struct pxa3xx_nand_flash builtin_flash_types[] = { |
4332c116 LW |
233 | { "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] }, |
234 | { "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] }, | |
235 | { "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] }, | |
236 | { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] }, | |
237 | { "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] }, | |
238 | { "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] }, | |
239 | { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] }, | |
240 | { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] }, | |
241 | { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] }, | |
d3490dfd HZ |
242 | }; |
243 | ||
227a886c LW |
244 | /* Define a default flash type setting serve as flash detecting only */ |
245 | #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0]) | |
246 | ||
fe69af00 | 247 | #define NDTR0_tCH(c) (min((c), 7) << 19) |
248 | #define NDTR0_tCS(c) (min((c), 7) << 16) | |
249 | #define NDTR0_tWH(c) (min((c), 7) << 11) | |
250 | #define NDTR0_tWP(c) (min((c), 7) << 8) | |
251 | #define NDTR0_tRH(c) (min((c), 7) << 3) | |
252 | #define NDTR0_tRP(c) (min((c), 7) << 0) | |
253 | ||
254 | #define NDTR1_tR(c) (min((c), 65535) << 16) | |
255 | #define NDTR1_tWHR(c) (min((c), 15) << 4) | |
256 | #define NDTR1_tAR(c) (min((c), 15) << 0) | |
257 | ||
258 | /* convert nano-seconds to nand flash controller clock cycles */ | |
93b352fc | 259 | #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) |
fe69af00 | 260 | |
d456882b | 261 | static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, |
7dad482e | 262 | const struct pxa3xx_nand_timing *t) |
fe69af00 | 263 | { |
d456882b | 264 | struct pxa3xx_nand_info *info = host->info_data; |
fe69af00 | 265 | unsigned long nand_clk = clk_get_rate(info->clk); |
266 | uint32_t ndtr0, ndtr1; | |
267 | ||
268 | ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | | |
269 | NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | | |
270 | NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | | |
271 | NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | | |
272 | NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | | |
273 | NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); | |
274 | ||
275 | ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | | |
276 | NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | | |
277 | NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); | |
278 | ||
48cf7efa EG |
279 | info->ndtr0cs0 = ndtr0; |
280 | info->ndtr1cs0 = ndtr1; | |
fe69af00 | 281 | nand_writel(info, NDTR0CS0, ndtr0); |
282 | nand_writel(info, NDTR1CS0, ndtr1); | |
283 | } | |
284 | ||
18c81b18 | 285 | static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info) |
fe69af00 | 286 | { |
f3c8cfc2 | 287 | struct pxa3xx_nand_host *host = info->host[info->cs]; |
48cf7efa | 288 | int oob_enable = info->reg_ndcr & NDCR_SPARE_EN; |
9d8b1043 | 289 | |
d456882b | 290 | info->data_size = host->page_size; |
9d8b1043 LW |
291 | if (!oob_enable) { |
292 | info->oob_size = 0; | |
293 | return; | |
294 | } | |
295 | ||
d456882b | 296 | switch (host->page_size) { |
fe69af00 | 297 | case 2048: |
9d8b1043 | 298 | info->oob_size = (info->use_ecc) ? 40 : 64; |
fe69af00 | 299 | break; |
300 | case 512: | |
9d8b1043 | 301 | info->oob_size = (info->use_ecc) ? 8 : 16; |
fe69af00 | 302 | break; |
fe69af00 | 303 | } |
18c81b18 LW |
304 | } |
305 | ||
f8155a40 LW |
306 | /** |
307 | * NOTE: it is a must to set ND_RUN firstly, then write | |
308 | * command buffer, otherwise, it does not work. | |
309 | * We enable all the interrupt at the same time, and | |
310 | * let pxa3xx_nand_irq to handle all logic. | |
311 | */ | |
312 | static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) | |
313 | { | |
314 | uint32_t ndcr; | |
315 | ||
48cf7efa | 316 | ndcr = info->reg_ndcr; |
cd9d1182 EG |
317 | |
318 | if (info->use_ecc) | |
319 | ndcr |= NDCR_ECC_EN; | |
320 | else | |
321 | ndcr &= ~NDCR_ECC_EN; | |
322 | ||
323 | if (info->use_dma) | |
324 | ndcr |= NDCR_DMA_EN; | |
325 | else | |
326 | ndcr &= ~NDCR_DMA_EN; | |
327 | ||
5bb653e8 EG |
328 | if (info->use_spare) |
329 | ndcr |= NDCR_SPARE_EN; | |
330 | else | |
331 | ndcr &= ~NDCR_SPARE_EN; | |
332 | ||
f8155a40 LW |
333 | ndcr |= NDCR_ND_RUN; |
334 | ||
335 | /* clear status bits and run */ | |
336 | nand_writel(info, NDCR, 0); | |
337 | nand_writel(info, NDSR, NDSR_MASK); | |
338 | nand_writel(info, NDCR, ndcr); | |
339 | } | |
340 | ||
341 | static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info) | |
342 | { | |
343 | uint32_t ndcr; | |
344 | int timeout = NAND_STOP_DELAY; | |
345 | ||
346 | /* wait RUN bit in NDCR become 0 */ | |
347 | ndcr = nand_readl(info, NDCR); | |
348 | while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) { | |
349 | ndcr = nand_readl(info, NDCR); | |
350 | udelay(1); | |
351 | } | |
352 | ||
353 | if (timeout <= 0) { | |
354 | ndcr &= ~NDCR_ND_RUN; | |
355 | nand_writel(info, NDCR, ndcr); | |
356 | } | |
357 | /* clear status bits */ | |
358 | nand_writel(info, NDSR, NDSR_MASK); | |
359 | } | |
360 | ||
57ff88f0 EG |
361 | static void __maybe_unused |
362 | enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) | |
fe69af00 | 363 | { |
364 | uint32_t ndcr; | |
365 | ||
366 | ndcr = nand_readl(info, NDCR); | |
367 | nand_writel(info, NDCR, ndcr & ~int_mask); | |
368 | } | |
369 | ||
370 | static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) | |
371 | { | |
372 | uint32_t ndcr; | |
373 | ||
374 | ndcr = nand_readl(info, NDCR); | |
375 | nand_writel(info, NDCR, ndcr | int_mask); | |
376 | } | |
377 | ||
f8155a40 | 378 | static void handle_data_pio(struct pxa3xx_nand_info *info) |
fe69af00 | 379 | { |
fe69af00 | 380 | switch (info->state) { |
381 | case STATE_PIO_WRITING: | |
382 | __raw_writesl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 383 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
384 | if (info->oob_size > 0) |
385 | __raw_writesl(info->mmio_base + NDDB, info->oob_buff, | |
386 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 387 | break; |
388 | case STATE_PIO_READING: | |
389 | __raw_readsl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 390 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
391 | if (info->oob_size > 0) |
392 | __raw_readsl(info->mmio_base + NDDB, info->oob_buff, | |
393 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 394 | break; |
395 | default: | |
da675b4e | 396 | dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |
fe69af00 | 397 | info->state); |
f8155a40 | 398 | BUG(); |
fe69af00 | 399 | } |
fe69af00 | 400 | } |
401 | ||
f4db2e3a | 402 | #ifdef ARCH_HAS_DMA |
f8155a40 | 403 | static void start_data_dma(struct pxa3xx_nand_info *info) |
fe69af00 | 404 | { |
405 | struct pxa_dma_desc *desc = info->data_desc; | |
9d8b1043 | 406 | int dma_len = ALIGN(info->data_size + info->oob_size, 32); |
fe69af00 | 407 | |
408 | desc->ddadr = DDADR_STOP; | |
409 | desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len; | |
410 | ||
f8155a40 LW |
411 | switch (info->state) { |
412 | case STATE_DMA_WRITING: | |
fe69af00 | 413 | desc->dsadr = info->data_buff_phys; |
8638fac8 | 414 | desc->dtadr = info->mmio_phys + NDDB; |
fe69af00 | 415 | desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG; |
f8155a40 LW |
416 | break; |
417 | case STATE_DMA_READING: | |
fe69af00 | 418 | desc->dtadr = info->data_buff_phys; |
8638fac8 | 419 | desc->dsadr = info->mmio_phys + NDDB; |
fe69af00 | 420 | desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC; |
f8155a40 LW |
421 | break; |
422 | default: | |
da675b4e | 423 | dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |
f8155a40 LW |
424 | info->state); |
425 | BUG(); | |
fe69af00 | 426 | } |
427 | ||
428 | DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch; | |
429 | DDADR(info->data_dma_ch) = info->data_desc_addr; | |
430 | DCSR(info->data_dma_ch) |= DCSR_RUN; | |
431 | } | |
432 | ||
433 | static void pxa3xx_nand_data_dma_irq(int channel, void *data) | |
434 | { | |
435 | struct pxa3xx_nand_info *info = data; | |
436 | uint32_t dcsr; | |
437 | ||
438 | dcsr = DCSR(channel); | |
439 | DCSR(channel) = dcsr; | |
440 | ||
441 | if (dcsr & DCSR_BUSERR) { | |
442 | info->retcode = ERR_DMABUSERR; | |
fe69af00 | 443 | } |
444 | ||
f8155a40 LW |
445 | info->state = STATE_DMA_DONE; |
446 | enable_int(info, NDCR_INT_MASK); | |
447 | nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); | |
fe69af00 | 448 | } |
f4db2e3a EG |
449 | #else |
450 | static void start_data_dma(struct pxa3xx_nand_info *info) | |
451 | {} | |
452 | #endif | |
fe69af00 | 453 | |
454 | static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) | |
455 | { | |
456 | struct pxa3xx_nand_info *info = devid; | |
f8155a40 | 457 | unsigned int status, is_completed = 0; |
f3c8cfc2 LW |
458 | unsigned int ready, cmd_done; |
459 | ||
460 | if (info->cs == 0) { | |
461 | ready = NDSR_FLASH_RDY; | |
462 | cmd_done = NDSR_CS0_CMDD; | |
463 | } else { | |
464 | ready = NDSR_RDY; | |
465 | cmd_done = NDSR_CS1_CMDD; | |
466 | } | |
fe69af00 | 467 | |
468 | status = nand_readl(info, NDSR); | |
469 | ||
f8155a40 LW |
470 | if (status & NDSR_DBERR) |
471 | info->retcode = ERR_DBERR; | |
472 | if (status & NDSR_SBERR) | |
473 | info->retcode = ERR_SBERR; | |
474 | if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) { | |
475 | /* whether use dma to transfer data */ | |
fe69af00 | 476 | if (info->use_dma) { |
f8155a40 LW |
477 | disable_int(info, NDCR_INT_MASK); |
478 | info->state = (status & NDSR_RDDREQ) ? | |
479 | STATE_DMA_READING : STATE_DMA_WRITING; | |
480 | start_data_dma(info); | |
481 | goto NORMAL_IRQ_EXIT; | |
fe69af00 | 482 | } else { |
f8155a40 LW |
483 | info->state = (status & NDSR_RDDREQ) ? |
484 | STATE_PIO_READING : STATE_PIO_WRITING; | |
485 | handle_data_pio(info); | |
fe69af00 | 486 | } |
fe69af00 | 487 | } |
f3c8cfc2 | 488 | if (status & cmd_done) { |
f8155a40 LW |
489 | info->state = STATE_CMD_DONE; |
490 | is_completed = 1; | |
fe69af00 | 491 | } |
f3c8cfc2 | 492 | if (status & ready) { |
401e67e2 | 493 | info->is_ready = 1; |
f8155a40 | 494 | info->state = STATE_READY; |
401e67e2 | 495 | } |
fe69af00 | 496 | |
f8155a40 LW |
497 | if (status & NDSR_WRCMDREQ) { |
498 | nand_writel(info, NDSR, NDSR_WRCMDREQ); | |
499 | status &= ~NDSR_WRCMDREQ; | |
500 | info->state = STATE_CMD_HANDLE; | |
3a1a344a EG |
501 | |
502 | /* | |
503 | * Command buffer registers NDCB{0-2} (and optionally NDCB3) | |
504 | * must be loaded by writing directly either 12 or 16 | |
505 | * bytes directly to NDCB0, four bytes at a time. | |
506 | * | |
507 | * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored | |
508 | * but each NDCBx register can be read. | |
509 | */ | |
f8155a40 LW |
510 | nand_writel(info, NDCB0, info->ndcb0); |
511 | nand_writel(info, NDCB0, info->ndcb1); | |
512 | nand_writel(info, NDCB0, info->ndcb2); | |
3a1a344a EG |
513 | |
514 | /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */ | |
515 | if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) | |
516 | nand_writel(info, NDCB0, info->ndcb3); | |
fe69af00 | 517 | } |
518 | ||
f8155a40 LW |
519 | /* clear NDSR to let the controller exit the IRQ */ |
520 | nand_writel(info, NDSR, status); | |
521 | if (is_completed) | |
522 | complete(&info->cmd_complete); | |
523 | NORMAL_IRQ_EXIT: | |
524 | return IRQ_HANDLED; | |
fe69af00 | 525 | } |
526 | ||
fe69af00 | 527 | static inline int is_buf_blank(uint8_t *buf, size_t len) |
528 | { | |
529 | for (; len > 0; len--) | |
530 | if (*buf++ != 0xff) | |
531 | return 0; | |
532 | return 1; | |
533 | } | |
534 | ||
4eb2da89 LW |
535 | static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, |
536 | uint16_t column, int page_addr) | |
fe69af00 | 537 | { |
d456882b | 538 | int addr_cycle, exec_cmd; |
f3c8cfc2 LW |
539 | struct pxa3xx_nand_host *host; |
540 | struct mtd_info *mtd; | |
fe69af00 | 541 | |
f3c8cfc2 LW |
542 | host = info->host[info->cs]; |
543 | mtd = host->mtd; | |
4eb2da89 LW |
544 | addr_cycle = 0; |
545 | exec_cmd = 1; | |
546 | ||
547 | /* reset data and oob column point to handle data */ | |
401e67e2 LW |
548 | info->buf_start = 0; |
549 | info->buf_count = 0; | |
4eb2da89 LW |
550 | info->oob_size = 0; |
551 | info->use_ecc = 0; | |
5bb653e8 | 552 | info->use_spare = 1; |
401e67e2 | 553 | info->is_ready = 0; |
4eb2da89 | 554 | info->retcode = ERR_NONE; |
f3c8cfc2 LW |
555 | if (info->cs != 0) |
556 | info->ndcb0 = NDCB0_CSEL; | |
557 | else | |
558 | info->ndcb0 = 0; | |
fe69af00 | 559 | |
560 | switch (command) { | |
4eb2da89 LW |
561 | case NAND_CMD_READ0: |
562 | case NAND_CMD_PAGEPROG: | |
563 | info->use_ecc = 1; | |
fe69af00 | 564 | case NAND_CMD_READOOB: |
4eb2da89 | 565 | pxa3xx_set_datasize(info); |
fe69af00 | 566 | break; |
41a63430 EG |
567 | case NAND_CMD_PARAM: |
568 | info->use_spare = 0; | |
569 | break; | |
4eb2da89 LW |
570 | case NAND_CMD_SEQIN: |
571 | exec_cmd = 0; | |
572 | break; | |
573 | default: | |
574 | info->ndcb1 = 0; | |
575 | info->ndcb2 = 0; | |
3a1a344a | 576 | info->ndcb3 = 0; |
4eb2da89 LW |
577 | break; |
578 | } | |
579 | ||
d456882b LW |
580 | addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles |
581 | + host->col_addr_cycles); | |
fe69af00 | 582 | |
4eb2da89 LW |
583 | switch (command) { |
584 | case NAND_CMD_READOOB: | |
fe69af00 | 585 | case NAND_CMD_READ0: |
ec82135a EG |
586 | info->buf_start = column; |
587 | info->ndcb0 |= NDCB0_CMD_TYPE(0) | |
588 | | addr_cycle | |
589 | | NAND_CMD_READ0; | |
590 | ||
4eb2da89 | 591 | if (command == NAND_CMD_READOOB) |
ec82135a | 592 | info->buf_start += mtd->writesize; |
4eb2da89 | 593 | |
ec82135a EG |
594 | /* Second command setting for large pages */ |
595 | if (host->page_size >= PAGE_CHUNK_SIZE) | |
596 | info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); | |
fe69af00 | 597 | |
fe69af00 | 598 | case NAND_CMD_SEQIN: |
4eb2da89 | 599 | /* small page addr setting */ |
d456882b | 600 | if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) { |
4eb2da89 LW |
601 | info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) |
602 | | (column & 0xFF); | |
603 | ||
604 | info->ndcb2 = 0; | |
605 | } else { | |
606 | info->ndcb1 = ((page_addr & 0xFFFF) << 16) | |
607 | | (column & 0xFFFF); | |
608 | ||
609 | if (page_addr & 0xFF0000) | |
610 | info->ndcb2 = (page_addr & 0xFF0000) >> 16; | |
611 | else | |
612 | info->ndcb2 = 0; | |
613 | } | |
614 | ||
fe69af00 | 615 | info->buf_count = mtd->writesize + mtd->oobsize; |
4eb2da89 | 616 | memset(info->data_buff, 0xFF, info->buf_count); |
fe69af00 | 617 | |
fe69af00 | 618 | break; |
4eb2da89 | 619 | |
fe69af00 | 620 | case NAND_CMD_PAGEPROG: |
4eb2da89 LW |
621 | if (is_buf_blank(info->data_buff, |
622 | (mtd->writesize + mtd->oobsize))) { | |
623 | exec_cmd = 0; | |
624 | break; | |
625 | } | |
fe69af00 | 626 | |
4eb2da89 LW |
627 | info->ndcb0 |= NDCB0_CMD_TYPE(0x1) |
628 | | NDCB0_AUTO_RS | |
629 | | NDCB0_ST_ROW_EN | |
630 | | NDCB0_DBC | |
ec82135a EG |
631 | | (NAND_CMD_PAGEPROG << 8) |
632 | | NAND_CMD_SEQIN | |
4eb2da89 | 633 | | addr_cycle; |
fe69af00 | 634 | break; |
4eb2da89 | 635 | |
ce0268f6 | 636 | case NAND_CMD_PARAM: |
ce0268f6 EG |
637 | info->buf_count = 256; |
638 | info->ndcb0 |= NDCB0_CMD_TYPE(0) | |
639 | | NDCB0_ADDR_CYC(1) | |
41a63430 | 640 | | NDCB0_LEN_OVRD |
ec82135a | 641 | | command; |
ce0268f6 | 642 | info->ndcb1 = (column & 0xFF); |
41a63430 | 643 | info->ndcb3 = 256; |
ce0268f6 EG |
644 | info->data_size = 256; |
645 | break; | |
646 | ||
fe69af00 | 647 | case NAND_CMD_READID: |
d456882b | 648 | info->buf_count = host->read_id_bytes; |
4eb2da89 LW |
649 | info->ndcb0 |= NDCB0_CMD_TYPE(3) |
650 | | NDCB0_ADDR_CYC(1) | |
ec82135a | 651 | | command; |
d14231f1 | 652 | info->ndcb1 = (column & 0xFF); |
4eb2da89 LW |
653 | |
654 | info->data_size = 8; | |
655 | break; | |
fe69af00 | 656 | case NAND_CMD_STATUS: |
4eb2da89 LW |
657 | info->buf_count = 1; |
658 | info->ndcb0 |= NDCB0_CMD_TYPE(4) | |
659 | | NDCB0_ADDR_CYC(1) | |
ec82135a | 660 | | command; |
4eb2da89 LW |
661 | |
662 | info->data_size = 8; | |
663 | break; | |
664 | ||
665 | case NAND_CMD_ERASE1: | |
4eb2da89 LW |
666 | info->ndcb0 |= NDCB0_CMD_TYPE(2) |
667 | | NDCB0_AUTO_RS | |
668 | | NDCB0_ADDR_CYC(3) | |
669 | | NDCB0_DBC | |
ec82135a EG |
670 | | (NAND_CMD_ERASE2 << 8) |
671 | | NAND_CMD_ERASE1; | |
4eb2da89 LW |
672 | info->ndcb1 = page_addr; |
673 | info->ndcb2 = 0; | |
674 | ||
fe69af00 | 675 | break; |
676 | case NAND_CMD_RESET: | |
4eb2da89 | 677 | info->ndcb0 |= NDCB0_CMD_TYPE(5) |
ec82135a | 678 | | command; |
4eb2da89 LW |
679 | |
680 | break; | |
681 | ||
682 | case NAND_CMD_ERASE2: | |
683 | exec_cmd = 0; | |
fe69af00 | 684 | break; |
4eb2da89 | 685 | |
fe69af00 | 686 | default: |
4eb2da89 | 687 | exec_cmd = 0; |
da675b4e LW |
688 | dev_err(&info->pdev->dev, "non-supported command %x\n", |
689 | command); | |
fe69af00 | 690 | break; |
691 | } | |
692 | ||
4eb2da89 LW |
693 | return exec_cmd; |
694 | } | |
695 | ||
696 | static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |
697 | int column, int page_addr) | |
698 | { | |
d456882b LW |
699 | struct pxa3xx_nand_host *host = mtd->priv; |
700 | struct pxa3xx_nand_info *info = host->info_data; | |
4eb2da89 LW |
701 | int ret, exec_cmd; |
702 | ||
703 | /* | |
704 | * if this is a x16 device ,then convert the input | |
705 | * "byte" address into a "word" address appropriate | |
706 | * for indexing a word-oriented device | |
707 | */ | |
48cf7efa | 708 | if (info->reg_ndcr & NDCR_DWIDTH_M) |
4eb2da89 LW |
709 | column /= 2; |
710 | ||
f3c8cfc2 LW |
711 | /* |
712 | * There may be different NAND chip hooked to | |
713 | * different chip select, so check whether | |
714 | * chip select has been changed, if yes, reset the timing | |
715 | */ | |
716 | if (info->cs != host->cs) { | |
717 | info->cs = host->cs; | |
48cf7efa EG |
718 | nand_writel(info, NDTR0CS0, info->ndtr0cs0); |
719 | nand_writel(info, NDTR1CS0, info->ndtr1cs0); | |
f3c8cfc2 LW |
720 | } |
721 | ||
d456882b | 722 | info->state = STATE_PREPARED; |
4eb2da89 | 723 | exec_cmd = prepare_command_pool(info, command, column, page_addr); |
f8155a40 LW |
724 | if (exec_cmd) { |
725 | init_completion(&info->cmd_complete); | |
726 | pxa3xx_nand_start(info); | |
727 | ||
728 | ret = wait_for_completion_timeout(&info->cmd_complete, | |
729 | CHIP_DELAY_TIMEOUT); | |
730 | if (!ret) { | |
da675b4e | 731 | dev_err(&info->pdev->dev, "Wait time out!!!\n"); |
f8155a40 LW |
732 | /* Stop State Machine for next command cycle */ |
733 | pxa3xx_nand_stop(info); | |
734 | } | |
f8155a40 | 735 | } |
d456882b | 736 | info->state = STATE_IDLE; |
f8155a40 LW |
737 | } |
738 | ||
fdbad98d | 739 | static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, |
1fbb938d | 740 | struct nand_chip *chip, const uint8_t *buf, int oob_required) |
f8155a40 LW |
741 | { |
742 | chip->write_buf(mtd, buf, mtd->writesize); | |
743 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
744 | |
745 | return 0; | |
f8155a40 LW |
746 | } |
747 | ||
748 | static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, | |
1fbb938d BN |
749 | struct nand_chip *chip, uint8_t *buf, int oob_required, |
750 | int page) | |
f8155a40 | 751 | { |
d456882b LW |
752 | struct pxa3xx_nand_host *host = mtd->priv; |
753 | struct pxa3xx_nand_info *info = host->info_data; | |
f8155a40 LW |
754 | |
755 | chip->read_buf(mtd, buf, mtd->writesize); | |
756 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
757 | ||
758 | if (info->retcode == ERR_SBERR) { | |
759 | switch (info->use_ecc) { | |
760 | case 1: | |
761 | mtd->ecc_stats.corrected++; | |
762 | break; | |
763 | case 0: | |
764 | default: | |
765 | break; | |
766 | } | |
767 | } else if (info->retcode == ERR_DBERR) { | |
768 | /* | |
769 | * for blank page (all 0xff), HW will calculate its ECC as | |
770 | * 0, which is different from the ECC information within | |
771 | * OOB, ignore such double bit errors | |
772 | */ | |
773 | if (is_buf_blank(buf, mtd->writesize)) | |
543e32d5 DM |
774 | info->retcode = ERR_NONE; |
775 | else | |
f8155a40 | 776 | mtd->ecc_stats.failed++; |
fe69af00 | 777 | } |
f8155a40 LW |
778 | |
779 | return 0; | |
fe69af00 | 780 | } |
781 | ||
782 | static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) | |
783 | { | |
d456882b LW |
784 | struct pxa3xx_nand_host *host = mtd->priv; |
785 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 786 | char retval = 0xFF; |
787 | ||
788 | if (info->buf_start < info->buf_count) | |
789 | /* Has just send a new command? */ | |
790 | retval = info->data_buff[info->buf_start++]; | |
791 | ||
792 | return retval; | |
793 | } | |
794 | ||
795 | static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) | |
796 | { | |
d456882b LW |
797 | struct pxa3xx_nand_host *host = mtd->priv; |
798 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 799 | u16 retval = 0xFFFF; |
800 | ||
801 | if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { | |
802 | retval = *((u16 *)(info->data_buff+info->buf_start)); | |
803 | info->buf_start += 2; | |
804 | } | |
805 | return retval; | |
806 | } | |
807 | ||
808 | static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
809 | { | |
d456882b LW |
810 | struct pxa3xx_nand_host *host = mtd->priv; |
811 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 812 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); |
813 | ||
814 | memcpy(buf, info->data_buff + info->buf_start, real_len); | |
815 | info->buf_start += real_len; | |
816 | } | |
817 | ||
818 | static void pxa3xx_nand_write_buf(struct mtd_info *mtd, | |
819 | const uint8_t *buf, int len) | |
820 | { | |
d456882b LW |
821 | struct pxa3xx_nand_host *host = mtd->priv; |
822 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 823 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); |
824 | ||
825 | memcpy(info->data_buff + info->buf_start, buf, real_len); | |
826 | info->buf_start += real_len; | |
827 | } | |
828 | ||
fe69af00 | 829 | static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) |
830 | { | |
831 | return; | |
832 | } | |
833 | ||
834 | static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) | |
835 | { | |
d456882b LW |
836 | struct pxa3xx_nand_host *host = mtd->priv; |
837 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 838 | |
839 | /* pxa3xx_nand_send_command has waited for command complete */ | |
840 | if (this->state == FL_WRITING || this->state == FL_ERASING) { | |
841 | if (info->retcode == ERR_NONE) | |
842 | return 0; | |
843 | else { | |
844 | /* | |
845 | * any error make it return 0x01 which will tell | |
846 | * the caller the erase and write fail | |
847 | */ | |
848 | return 0x01; | |
849 | } | |
850 | } | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
fe69af00 | 855 | static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, |
c8c17c88 | 856 | const struct pxa3xx_nand_flash *f) |
fe69af00 | 857 | { |
858 | struct platform_device *pdev = info->pdev; | |
453810b7 | 859 | struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); |
f3c8cfc2 | 860 | struct pxa3xx_nand_host *host = info->host[info->cs]; |
f8155a40 | 861 | uint32_t ndcr = 0x0; /* enable all interrupts */ |
fe69af00 | 862 | |
da675b4e LW |
863 | if (f->page_size != 2048 && f->page_size != 512) { |
864 | dev_err(&pdev->dev, "Current only support 2048 and 512 size\n"); | |
fe69af00 | 865 | return -EINVAL; |
da675b4e | 866 | } |
fe69af00 | 867 | |
da675b4e LW |
868 | if (f->flash_width != 16 && f->flash_width != 8) { |
869 | dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n"); | |
fe69af00 | 870 | return -EINVAL; |
da675b4e | 871 | } |
fe69af00 | 872 | |
873 | /* calculate flash information */ | |
d456882b LW |
874 | host->page_size = f->page_size; |
875 | host->read_id_bytes = (f->page_size == 2048) ? 4 : 2; | |
fe69af00 | 876 | |
877 | /* calculate addressing information */ | |
d456882b | 878 | host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1; |
fe69af00 | 879 | |
880 | if (f->num_blocks * f->page_per_block > 65536) | |
d456882b | 881 | host->row_addr_cycles = 3; |
fe69af00 | 882 | else |
d456882b | 883 | host->row_addr_cycles = 2; |
fe69af00 | 884 | |
885 | ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; | |
d456882b | 886 | ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; |
fe69af00 | 887 | ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0; |
888 | ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0; | |
889 | ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0; | |
890 | ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; | |
891 | ||
d456882b | 892 | ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); |
fe69af00 | 893 | ndcr |= NDCR_SPARE_EN; /* enable spare by default */ |
894 | ||
48cf7efa | 895 | info->reg_ndcr = ndcr; |
fe69af00 | 896 | |
d456882b | 897 | pxa3xx_nand_set_timing(host, f->timing); |
fe69af00 | 898 | return 0; |
899 | } | |
900 | ||
f271049e MR |
901 | static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) |
902 | { | |
f3c8cfc2 LW |
903 | /* |
904 | * We set 0 by hard coding here, for we don't support keep_config | |
905 | * when there is more than one chip attached to the controller | |
906 | */ | |
907 | struct pxa3xx_nand_host *host = info->host[0]; | |
f271049e | 908 | uint32_t ndcr = nand_readl(info, NDCR); |
f271049e | 909 | |
d456882b LW |
910 | if (ndcr & NDCR_PAGE_SZ) { |
911 | host->page_size = 2048; | |
912 | host->read_id_bytes = 4; | |
913 | } else { | |
914 | host->page_size = 512; | |
915 | host->read_id_bytes = 2; | |
916 | } | |
917 | ||
48cf7efa EG |
918 | info->reg_ndcr = ndcr & ~NDCR_INT_MASK; |
919 | info->ndtr0cs0 = nand_readl(info, NDTR0CS0); | |
920 | info->ndtr1cs0 = nand_readl(info, NDTR1CS0); | |
f271049e MR |
921 | return 0; |
922 | } | |
923 | ||
f4db2e3a | 924 | #ifdef ARCH_HAS_DMA |
fe69af00 | 925 | static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) |
926 | { | |
927 | struct platform_device *pdev = info->pdev; | |
62e8b851 | 928 | int data_desc_offset = info->buf_size - sizeof(struct pxa_dma_desc); |
fe69af00 | 929 | |
930 | if (use_dma == 0) { | |
62e8b851 | 931 | info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); |
fe69af00 | 932 | if (info->data_buff == NULL) |
933 | return -ENOMEM; | |
934 | return 0; | |
935 | } | |
936 | ||
62e8b851 | 937 | info->data_buff = dma_alloc_coherent(&pdev->dev, info->buf_size, |
fe69af00 | 938 | &info->data_buff_phys, GFP_KERNEL); |
939 | if (info->data_buff == NULL) { | |
940 | dev_err(&pdev->dev, "failed to allocate dma buffer\n"); | |
941 | return -ENOMEM; | |
942 | } | |
943 | ||
fe69af00 | 944 | info->data_desc = (void *)info->data_buff + data_desc_offset; |
945 | info->data_desc_addr = info->data_buff_phys + data_desc_offset; | |
946 | ||
947 | info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW, | |
948 | pxa3xx_nand_data_dma_irq, info); | |
949 | if (info->data_dma_ch < 0) { | |
950 | dev_err(&pdev->dev, "failed to request data dma\n"); | |
62e8b851 | 951 | dma_free_coherent(&pdev->dev, info->buf_size, |
fe69af00 | 952 | info->data_buff, info->data_buff_phys); |
953 | return info->data_dma_ch; | |
954 | } | |
955 | ||
95b26563 EG |
956 | /* |
957 | * Now that DMA buffers are allocated we turn on | |
958 | * DMA proper for I/O operations. | |
959 | */ | |
960 | info->use_dma = 1; | |
fe69af00 | 961 | return 0; |
962 | } | |
963 | ||
498b6145 EG |
964 | static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) |
965 | { | |
966 | struct platform_device *pdev = info->pdev; | |
15b540c7 | 967 | if (info->use_dma) { |
498b6145 | 968 | pxa_free_dma(info->data_dma_ch); |
62e8b851 | 969 | dma_free_coherent(&pdev->dev, info->buf_size, |
498b6145 EG |
970 | info->data_buff, info->data_buff_phys); |
971 | } else { | |
972 | kfree(info->data_buff); | |
973 | } | |
974 | } | |
f4db2e3a EG |
975 | #else |
976 | static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) | |
977 | { | |
62e8b851 | 978 | info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); |
f4db2e3a EG |
979 | if (info->data_buff == NULL) |
980 | return -ENOMEM; | |
981 | return 0; | |
982 | } | |
983 | ||
984 | static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) | |
985 | { | |
986 | kfree(info->data_buff); | |
987 | } | |
988 | #endif | |
498b6145 | 989 | |
401e67e2 LW |
990 | static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info) |
991 | { | |
f3c8cfc2 | 992 | struct mtd_info *mtd; |
d456882b | 993 | int ret; |
f3c8cfc2 | 994 | mtd = info->host[info->cs]->mtd; |
401e67e2 | 995 | /* use the common timing to make a try */ |
d456882b LW |
996 | ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]); |
997 | if (ret) | |
998 | return ret; | |
999 | ||
1000 | pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0); | |
401e67e2 | 1001 | if (info->is_ready) |
401e67e2 | 1002 | return 0; |
d456882b LW |
1003 | |
1004 | return -ENODEV; | |
401e67e2 | 1005 | } |
fe69af00 | 1006 | |
401e67e2 | 1007 | static int pxa3xx_nand_scan(struct mtd_info *mtd) |
fe69af00 | 1008 | { |
d456882b LW |
1009 | struct pxa3xx_nand_host *host = mtd->priv; |
1010 | struct pxa3xx_nand_info *info = host->info_data; | |
401e67e2 | 1011 | struct platform_device *pdev = info->pdev; |
453810b7 | 1012 | struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0fab028b | 1013 | struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL; |
401e67e2 LW |
1014 | const struct pxa3xx_nand_flash *f = NULL; |
1015 | struct nand_chip *chip = mtd->priv; | |
1016 | uint32_t id = -1; | |
4332c116 | 1017 | uint64_t chipsize; |
401e67e2 LW |
1018 | int i, ret, num; |
1019 | ||
1020 | if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) | |
4332c116 | 1021 | goto KEEP_CONFIG; |
401e67e2 LW |
1022 | |
1023 | ret = pxa3xx_nand_sensing(info); | |
d456882b | 1024 | if (ret) { |
f3c8cfc2 LW |
1025 | dev_info(&info->pdev->dev, "There is no chip on cs %d!\n", |
1026 | info->cs); | |
401e67e2 | 1027 | |
d456882b | 1028 | return ret; |
401e67e2 LW |
1029 | } |
1030 | ||
1031 | chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0); | |
1032 | id = *((uint16_t *)(info->data_buff)); | |
1033 | if (id != 0) | |
da675b4e | 1034 | dev_info(&info->pdev->dev, "Detect a flash id %x\n", id); |
401e67e2 | 1035 | else { |
da675b4e LW |
1036 | dev_warn(&info->pdev->dev, |
1037 | "Read out ID 0, potential timing set wrong!!\n"); | |
401e67e2 LW |
1038 | |
1039 | return -EINVAL; | |
1040 | } | |
1041 | ||
1042 | num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; | |
1043 | for (i = 0; i < num; i++) { | |
1044 | if (i < pdata->num_flash) | |
1045 | f = pdata->flash + i; | |
1046 | else | |
1047 | f = &builtin_flash_types[i - pdata->num_flash + 1]; | |
1048 | ||
1049 | /* find the chip in default list */ | |
4332c116 | 1050 | if (f->chip_id == id) |
401e67e2 | 1051 | break; |
401e67e2 LW |
1052 | } |
1053 | ||
4332c116 | 1054 | if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) { |
da675b4e | 1055 | dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n"); |
401e67e2 LW |
1056 | |
1057 | return -EINVAL; | |
1058 | } | |
1059 | ||
d456882b LW |
1060 | ret = pxa3xx_nand_config_flash(info, f); |
1061 | if (ret) { | |
1062 | dev_err(&info->pdev->dev, "ERROR! Configure failed\n"); | |
1063 | return ret; | |
1064 | } | |
1065 | ||
4332c116 | 1066 | pxa3xx_flash_ids[0].name = f->name; |
68aa352d | 1067 | pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff; |
4332c116 LW |
1068 | pxa3xx_flash_ids[0].pagesize = f->page_size; |
1069 | chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size; | |
1070 | pxa3xx_flash_ids[0].chipsize = chipsize >> 20; | |
1071 | pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block; | |
1072 | if (f->flash_width == 16) | |
1073 | pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16; | |
0fab028b LW |
1074 | pxa3xx_flash_ids[1].name = NULL; |
1075 | def = pxa3xx_flash_ids; | |
4332c116 | 1076 | KEEP_CONFIG: |
d456882b LW |
1077 | chip->ecc.mode = NAND_ECC_HW; |
1078 | chip->ecc.size = host->page_size; | |
6a918bad | 1079 | chip->ecc.strength = 1; |
d456882b | 1080 | |
48cf7efa | 1081 | if (info->reg_ndcr & NDCR_DWIDTH_M) |
d456882b LW |
1082 | chip->options |= NAND_BUSWIDTH_16; |
1083 | ||
0fab028b | 1084 | if (nand_scan_ident(mtd, 1, def)) |
4332c116 LW |
1085 | return -ENODEV; |
1086 | /* calculate addressing information */ | |
d456882b LW |
1087 | if (mtd->writesize >= 2048) |
1088 | host->col_addr_cycles = 2; | |
1089 | else | |
1090 | host->col_addr_cycles = 1; | |
1091 | ||
62e8b851 EG |
1092 | /* release the initial buffer */ |
1093 | kfree(info->data_buff); | |
1094 | ||
1095 | /* allocate the real data + oob buffer */ | |
1096 | info->buf_size = mtd->writesize + mtd->oobsize; | |
1097 | ret = pxa3xx_nand_init_buff(info); | |
1098 | if (ret) | |
1099 | return ret; | |
4332c116 | 1100 | info->oob_buff = info->data_buff + mtd->writesize; |
62e8b851 | 1101 | |
4332c116 | 1102 | if ((mtd->size >> chip->page_shift) > 65536) |
d456882b | 1103 | host->row_addr_cycles = 3; |
4332c116 | 1104 | else |
d456882b | 1105 | host->row_addr_cycles = 2; |
401e67e2 | 1106 | return nand_scan_tail(mtd); |
fe69af00 | 1107 | } |
1108 | ||
d456882b | 1109 | static int alloc_nand_resource(struct platform_device *pdev) |
fe69af00 | 1110 | { |
f3c8cfc2 | 1111 | struct pxa3xx_nand_platform_data *pdata; |
fe69af00 | 1112 | struct pxa3xx_nand_info *info; |
d456882b | 1113 | struct pxa3xx_nand_host *host; |
6e308f87 | 1114 | struct nand_chip *chip = NULL; |
fe69af00 | 1115 | struct mtd_info *mtd; |
1116 | struct resource *r; | |
f3c8cfc2 | 1117 | int ret, irq, cs; |
fe69af00 | 1118 | |
453810b7 | 1119 | pdata = dev_get_platdata(&pdev->dev); |
4c073cd2 EG |
1120 | info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) + |
1121 | sizeof(*host)) * pdata->num_cs, GFP_KERNEL); | |
1122 | if (!info) | |
d456882b | 1123 | return -ENOMEM; |
fe69af00 | 1124 | |
fe69af00 | 1125 | info->pdev = pdev; |
f3c8cfc2 LW |
1126 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1127 | mtd = (struct mtd_info *)((unsigned int)&info[1] + | |
1128 | (sizeof(*mtd) + sizeof(*host)) * cs); | |
1129 | chip = (struct nand_chip *)(&mtd[1]); | |
1130 | host = (struct pxa3xx_nand_host *)chip; | |
1131 | info->host[cs] = host; | |
1132 | host->mtd = mtd; | |
1133 | host->cs = cs; | |
1134 | host->info_data = info; | |
1135 | mtd->priv = host; | |
1136 | mtd->owner = THIS_MODULE; | |
1137 | ||
1138 | chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; | |
1139 | chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; | |
1140 | chip->controller = &info->controller; | |
1141 | chip->waitfunc = pxa3xx_nand_waitfunc; | |
1142 | chip->select_chip = pxa3xx_nand_select_chip; | |
1143 | chip->cmdfunc = pxa3xx_nand_cmdfunc; | |
1144 | chip->read_word = pxa3xx_nand_read_word; | |
1145 | chip->read_byte = pxa3xx_nand_read_byte; | |
1146 | chip->read_buf = pxa3xx_nand_read_buf; | |
1147 | chip->write_buf = pxa3xx_nand_write_buf; | |
f3c8cfc2 | 1148 | } |
401e67e2 LW |
1149 | |
1150 | spin_lock_init(&chip->controller->lock); | |
1151 | init_waitqueue_head(&chip->controller->wq); | |
9ca7944d | 1152 | info->clk = devm_clk_get(&pdev->dev, NULL); |
fe69af00 | 1153 | if (IS_ERR(info->clk)) { |
1154 | dev_err(&pdev->dev, "failed to get nand clock\n"); | |
4c073cd2 | 1155 | return PTR_ERR(info->clk); |
fe69af00 | 1156 | } |
1f8eaff2 EG |
1157 | ret = clk_prepare_enable(info->clk); |
1158 | if (ret < 0) | |
1159 | return ret; | |
fe69af00 | 1160 | |
6b45c1ee EG |
1161 | if (use_dma) { |
1162 | /* | |
1163 | * This is a dirty hack to make this driver work from | |
1164 | * devicetree bindings. It can be removed once we have | |
1165 | * a prober DMA controller framework for DT. | |
1166 | */ | |
1167 | if (pdev->dev.of_node && | |
1168 | of_machine_is_compatible("marvell,pxa3xx")) { | |
1169 | info->drcmr_dat = 97; | |
1170 | info->drcmr_cmd = 99; | |
1171 | } else { | |
1172 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1173 | if (r == NULL) { | |
1174 | dev_err(&pdev->dev, | |
1175 | "no resource defined for data DMA\n"); | |
1176 | ret = -ENXIO; | |
1177 | goto fail_disable_clk; | |
1178 | } | |
1179 | info->drcmr_dat = r->start; | |
1180 | ||
1181 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1182 | if (r == NULL) { | |
1183 | dev_err(&pdev->dev, | |
1184 | "no resource defined for cmd DMA\n"); | |
1185 | ret = -ENXIO; | |
1186 | goto fail_disable_clk; | |
1187 | } | |
1188 | info->drcmr_cmd = r->start; | |
1e7ba630 | 1189 | } |
fe69af00 | 1190 | } |
fe69af00 | 1191 | |
1192 | irq = platform_get_irq(pdev, 0); | |
1193 | if (irq < 0) { | |
1194 | dev_err(&pdev->dev, "no IRQ resource defined\n"); | |
1195 | ret = -ENXIO; | |
9ca7944d | 1196 | goto fail_disable_clk; |
fe69af00 | 1197 | } |
1198 | ||
1199 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
0ddd846f EG |
1200 | info->mmio_base = devm_ioremap_resource(&pdev->dev, r); |
1201 | if (IS_ERR(info->mmio_base)) { | |
1202 | ret = PTR_ERR(info->mmio_base); | |
9ca7944d | 1203 | goto fail_disable_clk; |
fe69af00 | 1204 | } |
8638fac8 | 1205 | info->mmio_phys = r->start; |
fe69af00 | 1206 | |
62e8b851 EG |
1207 | /* Allocate a buffer to allow flash detection */ |
1208 | info->buf_size = INIT_BUFFER_SIZE; | |
1209 | info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); | |
1210 | if (info->data_buff == NULL) { | |
1211 | ret = -ENOMEM; | |
9ca7944d | 1212 | goto fail_disable_clk; |
62e8b851 | 1213 | } |
fe69af00 | 1214 | |
346e1259 HZ |
1215 | /* initialize all interrupts to be disabled */ |
1216 | disable_int(info, NDSR_MASK); | |
1217 | ||
b1eb234f | 1218 | ret = request_irq(irq, pxa3xx_nand_irq, 0, pdev->name, info); |
fe69af00 | 1219 | if (ret < 0) { |
1220 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
1221 | goto fail_free_buf; | |
1222 | } | |
1223 | ||
e353a20a | 1224 | platform_set_drvdata(pdev, info); |
fe69af00 | 1225 | |
d456882b | 1226 | return 0; |
fe69af00 | 1227 | |
fe69af00 | 1228 | fail_free_buf: |
401e67e2 | 1229 | free_irq(irq, info); |
62e8b851 | 1230 | kfree(info->data_buff); |
9ca7944d | 1231 | fail_disable_clk: |
fb32061f | 1232 | clk_disable_unprepare(info->clk); |
d456882b | 1233 | return ret; |
fe69af00 | 1234 | } |
1235 | ||
1236 | static int pxa3xx_nand_remove(struct platform_device *pdev) | |
1237 | { | |
e353a20a | 1238 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 | 1239 | struct pxa3xx_nand_platform_data *pdata; |
f3c8cfc2 | 1240 | int irq, cs; |
fe69af00 | 1241 | |
d456882b LW |
1242 | if (!info) |
1243 | return 0; | |
1244 | ||
453810b7 | 1245 | pdata = dev_get_platdata(&pdev->dev); |
fe69af00 | 1246 | |
dbf5986a HZ |
1247 | irq = platform_get_irq(pdev, 0); |
1248 | if (irq >= 0) | |
1249 | free_irq(irq, info); | |
498b6145 | 1250 | pxa3xx_nand_free_buff(info); |
82a72d10 | 1251 | |
fb32061f | 1252 | clk_disable_unprepare(info->clk); |
82a72d10 | 1253 | |
f3c8cfc2 LW |
1254 | for (cs = 0; cs < pdata->num_cs; cs++) |
1255 | nand_release(info->host[cs]->mtd); | |
fe69af00 | 1256 | return 0; |
1257 | } | |
1258 | ||
1e7ba630 | 1259 | static struct of_device_id pxa3xx_nand_dt_ids[] = { |
c0f3b864 EG |
1260 | { |
1261 | .compatible = "marvell,pxa3xx-nand", | |
1262 | .data = (void *)PXA3XX_NAND_VARIANT_PXA, | |
1263 | }, | |
1e7ba630 DM |
1264 | {} |
1265 | }; | |
f3958984 | 1266 | MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids); |
1e7ba630 | 1267 | |
c0f3b864 EG |
1268 | static enum pxa3xx_nand_variant |
1269 | pxa3xx_nand_get_variant(struct platform_device *pdev) | |
1270 | { | |
1271 | const struct of_device_id *of_id = | |
1272 | of_match_device(pxa3xx_nand_dt_ids, &pdev->dev); | |
1273 | if (!of_id) | |
1274 | return PXA3XX_NAND_VARIANT_PXA; | |
1275 | return (enum pxa3xx_nand_variant)of_id->data; | |
1276 | } | |
1277 | ||
1e7ba630 DM |
1278 | static int pxa3xx_nand_probe_dt(struct platform_device *pdev) |
1279 | { | |
1280 | struct pxa3xx_nand_platform_data *pdata; | |
1281 | struct device_node *np = pdev->dev.of_node; | |
1282 | const struct of_device_id *of_id = | |
1283 | of_match_device(pxa3xx_nand_dt_ids, &pdev->dev); | |
1284 | ||
1285 | if (!of_id) | |
1286 | return 0; | |
1287 | ||
1288 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1289 | if (!pdata) | |
1290 | return -ENOMEM; | |
1291 | ||
1292 | if (of_get_property(np, "marvell,nand-enable-arbiter", NULL)) | |
1293 | pdata->enable_arbiter = 1; | |
1294 | if (of_get_property(np, "marvell,nand-keep-config", NULL)) | |
1295 | pdata->keep_config = 1; | |
1296 | of_property_read_u32(np, "num-cs", &pdata->num_cs); | |
1297 | ||
1298 | pdev->dev.platform_data = pdata; | |
1299 | ||
1300 | return 0; | |
1301 | } | |
1e7ba630 | 1302 | |
e353a20a LW |
1303 | static int pxa3xx_nand_probe(struct platform_device *pdev) |
1304 | { | |
1305 | struct pxa3xx_nand_platform_data *pdata; | |
1e7ba630 | 1306 | struct mtd_part_parser_data ppdata = {}; |
e353a20a | 1307 | struct pxa3xx_nand_info *info; |
f3c8cfc2 | 1308 | int ret, cs, probe_success; |
e353a20a | 1309 | |
f4db2e3a EG |
1310 | #ifndef ARCH_HAS_DMA |
1311 | if (use_dma) { | |
1312 | use_dma = 0; | |
1313 | dev_warn(&pdev->dev, | |
1314 | "This platform can't do DMA on this device\n"); | |
1315 | } | |
1316 | #endif | |
1e7ba630 DM |
1317 | ret = pxa3xx_nand_probe_dt(pdev); |
1318 | if (ret) | |
1319 | return ret; | |
1320 | ||
453810b7 | 1321 | pdata = dev_get_platdata(&pdev->dev); |
e353a20a LW |
1322 | if (!pdata) { |
1323 | dev_err(&pdev->dev, "no platform data defined\n"); | |
1324 | return -ENODEV; | |
1325 | } | |
1326 | ||
d456882b LW |
1327 | ret = alloc_nand_resource(pdev); |
1328 | if (ret) { | |
1329 | dev_err(&pdev->dev, "alloc nand resource failed\n"); | |
1330 | return ret; | |
1331 | } | |
e353a20a | 1332 | |
d456882b | 1333 | info = platform_get_drvdata(pdev); |
c0f3b864 | 1334 | info->variant = pxa3xx_nand_get_variant(pdev); |
f3c8cfc2 LW |
1335 | probe_success = 0; |
1336 | for (cs = 0; cs < pdata->num_cs; cs++) { | |
b7655bcb | 1337 | struct mtd_info *mtd = info->host[cs]->mtd; |
f455578d | 1338 | |
18a84e93 EG |
1339 | /* |
1340 | * The mtd name matches the one used in 'mtdparts' kernel | |
1341 | * parameter. This name cannot be changed or otherwise | |
1342 | * user's mtd partitions configuration would get broken. | |
1343 | */ | |
1344 | mtd->name = "pxa3xx_nand-0"; | |
f3c8cfc2 | 1345 | info->cs = cs; |
b7655bcb | 1346 | ret = pxa3xx_nand_scan(mtd); |
f3c8cfc2 LW |
1347 | if (ret) { |
1348 | dev_warn(&pdev->dev, "failed to scan nand at cs %d\n", | |
1349 | cs); | |
1350 | continue; | |
1351 | } | |
1352 | ||
1e7ba630 | 1353 | ppdata.of_node = pdev->dev.of_node; |
b7655bcb | 1354 | ret = mtd_device_parse_register(mtd, NULL, |
1e7ba630 | 1355 | &ppdata, pdata->parts[cs], |
42d7fbe2 | 1356 | pdata->nr_parts[cs]); |
f3c8cfc2 LW |
1357 | if (!ret) |
1358 | probe_success = 1; | |
1359 | } | |
1360 | ||
1361 | if (!probe_success) { | |
e353a20a LW |
1362 | pxa3xx_nand_remove(pdev); |
1363 | return -ENODEV; | |
1364 | } | |
1365 | ||
f3c8cfc2 | 1366 | return 0; |
e353a20a LW |
1367 | } |
1368 | ||
fe69af00 | 1369 | #ifdef CONFIG_PM |
1370 | static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state) | |
1371 | { | |
e353a20a | 1372 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 LW |
1373 | struct pxa3xx_nand_platform_data *pdata; |
1374 | struct mtd_info *mtd; | |
1375 | int cs; | |
fe69af00 | 1376 | |
453810b7 | 1377 | pdata = dev_get_platdata(&pdev->dev); |
f8155a40 | 1378 | if (info->state) { |
fe69af00 | 1379 | dev_err(&pdev->dev, "driver busy, state = %d\n", info->state); |
1380 | return -EAGAIN; | |
1381 | } | |
1382 | ||
f3c8cfc2 LW |
1383 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1384 | mtd = info->host[cs]->mtd; | |
3fe4bae8 | 1385 | mtd_suspend(mtd); |
f3c8cfc2 LW |
1386 | } |
1387 | ||
fe69af00 | 1388 | return 0; |
1389 | } | |
1390 | ||
1391 | static int pxa3xx_nand_resume(struct platform_device *pdev) | |
1392 | { | |
e353a20a | 1393 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 LW |
1394 | struct pxa3xx_nand_platform_data *pdata; |
1395 | struct mtd_info *mtd; | |
1396 | int cs; | |
051fc41c | 1397 | |
453810b7 | 1398 | pdata = dev_get_platdata(&pdev->dev); |
051fc41c LW |
1399 | /* We don't want to handle interrupt without calling mtd routine */ |
1400 | disable_int(info, NDCR_INT_MASK); | |
fe69af00 | 1401 | |
f3c8cfc2 LW |
1402 | /* |
1403 | * Directly set the chip select to a invalid value, | |
1404 | * then the driver would reset the timing according | |
1405 | * to current chip select at the beginning of cmdfunc | |
1406 | */ | |
1407 | info->cs = 0xff; | |
fe69af00 | 1408 | |
051fc41c LW |
1409 | /* |
1410 | * As the spec says, the NDSR would be updated to 0x1800 when | |
1411 | * doing the nand_clk disable/enable. | |
1412 | * To prevent it damaging state machine of the driver, clear | |
1413 | * all status before resume | |
1414 | */ | |
1415 | nand_writel(info, NDSR, NDSR_MASK); | |
f3c8cfc2 LW |
1416 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1417 | mtd = info->host[cs]->mtd; | |
ead995f8 | 1418 | mtd_resume(mtd); |
f3c8cfc2 LW |
1419 | } |
1420 | ||
18c81b18 | 1421 | return 0; |
fe69af00 | 1422 | } |
1423 | #else | |
1424 | #define pxa3xx_nand_suspend NULL | |
1425 | #define pxa3xx_nand_resume NULL | |
1426 | #endif | |
1427 | ||
1428 | static struct platform_driver pxa3xx_nand_driver = { | |
1429 | .driver = { | |
1430 | .name = "pxa3xx-nand", | |
5576bc7b | 1431 | .of_match_table = pxa3xx_nand_dt_ids, |
fe69af00 | 1432 | }, |
1433 | .probe = pxa3xx_nand_probe, | |
1434 | .remove = pxa3xx_nand_remove, | |
1435 | .suspend = pxa3xx_nand_suspend, | |
1436 | .resume = pxa3xx_nand_resume, | |
1437 | }; | |
1438 | ||
f99640de | 1439 | module_platform_driver(pxa3xx_nand_driver); |
fe69af00 | 1440 | |
1441 | MODULE_LICENSE("GPL"); | |
1442 | MODULE_DESCRIPTION("PXA3xx NAND controller driver"); |