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mtd: pxa3xx_nand: rework irq logic
[deliverable/linux.git] / drivers / mtd / nand / pxa3xx_nand.c
CommitLineData
fe69af00 1/*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
a88bdbb5 12#include <linux/kernel.h>
fe69af00 13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/delay.h>
18#include <linux/clk.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
a1c06ee1
DW		 22#include <linux/io.h>
23#include <linux/irq.h>
5a0e3ad6 24#include <linux/slab.h>
fe69af00 25
afb5b5c9 26#include <mach/dma.h>
82b95ecb 27#include <plat/pxa3xx_nand.h>
fe69af00 28
29#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
f8155a40 30#define NAND_STOP_DELAY (2 * HZ/50)
fe69af00 31
32/* registers and bit definitions */
33#define NDCR (0x00) /* Control register */
34#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
35#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
36#define NDSR (0x14) /* Status Register */
37#define NDPCR (0x18) /* Page Count Register */
38#define NDBDR0 (0x1C) /* Bad Block Register 0 */
39#define NDBDR1 (0x20) /* Bad Block Register 1 */
40#define NDDB (0x40) /* Data Buffer */
41#define NDCB0 (0x48) /* Command Buffer0 */
42#define NDCB1 (0x4C) /* Command Buffer1 */
43#define NDCB2 (0x50) /* Command Buffer2 */
44
45#define NDCR_SPARE_EN (0x1 << 31)
46#define NDCR_ECC_EN (0x1 << 30)
47#define NDCR_DMA_EN (0x1 << 29)
48#define NDCR_ND_RUN (0x1 << 28)
49#define NDCR_DWIDTH_C (0x1 << 27)
50#define NDCR_DWIDTH_M (0x1 << 26)
51#define NDCR_PAGE_SZ (0x1 << 24)
52#define NDCR_NCSX (0x1 << 23)
53#define NDCR_ND_MODE (0x3 << 21)
54#define NDCR_NAND_MODE (0x0)
55#define NDCR_CLR_PG_CNT (0x1 << 20)
f8155a40 56#define NDCR_STOP_ON_UNCOR (0x1 << 19)
fe69af00 57#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
58#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
59
60#define NDCR_RA_START (0x1 << 15)
61#define NDCR_PG_PER_BLK (0x1 << 14)
62#define NDCR_ND_ARB_EN (0x1 << 12)
f8155a40 63#define NDCR_INT_MASK (0xFFF)
fe69af00 64
65#define NDSR_MASK (0xfff)
f8155a40
LW		 66#define NDSR_RDY (0x1 << 12)
67#define NDSR_FLASH_RDY (0x1 << 11)
fe69af00 68#define NDSR_CS0_PAGED (0x1 << 10)
69#define NDSR_CS1_PAGED (0x1 << 9)
70#define NDSR_CS0_CMDD (0x1 << 8)
71#define NDSR_CS1_CMDD (0x1 << 7)
72#define NDSR_CS0_BBD (0x1 << 6)
73#define NDSR_CS1_BBD (0x1 << 5)
74#define NDSR_DBERR (0x1 << 4)
75#define NDSR_SBERR (0x1 << 3)
76#define NDSR_WRDREQ (0x1 << 2)
77#define NDSR_RDDREQ (0x1 << 1)
78#define NDSR_WRCMDREQ (0x1)
79
80#define NDCB0_AUTO_RS (0x1 << 25)
81#define NDCB0_CSEL (0x1 << 24)
82#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
83#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
84#define NDCB0_NC (0x1 << 20)
85#define NDCB0_DBC (0x1 << 19)
86#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
87#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
88#define NDCB0_CMD2_MASK (0xff << 8)
89#define NDCB0_CMD1_MASK (0xff)
90#define NDCB0_ADDR_CYC_SHIFT (16)
91
fe69af00 92/* macros for registers read/write */
93#define nand_writel(info, off, val) \
94 __raw_writel((val), (info)->mmio_base + (off))
95
96#define nand_readl(info, off) \
97 __raw_readl((info)->mmio_base + (off))
98
99/* error code and state */
100enum {
101 ERR_NONE = 0,
102 ERR_DMABUSERR = -1,
103 ERR_SENDCMD = -2,
104 ERR_DBERR = -3,
105 ERR_BBERR = -4,
223cf6c3 106 ERR_SBERR = -5,
fe69af00 107};
108
109enum {
f8155a40 110 STATE_IDLE = 0,
fe69af00 111 STATE_CMD_HANDLE,
112 STATE_DMA_READING,
113 STATE_DMA_WRITING,
114 STATE_DMA_DONE,
115 STATE_PIO_READING,
116 STATE_PIO_WRITING,
f8155a40
LW		 117 STATE_CMD_DONE,
118 STATE_READY,
fe69af00 119};
120
fe69af00 121struct pxa3xx_nand_info {
122 struct nand_chip nand_chip;
123
124 struct platform_device *pdev;
18c81b18 125 struct pxa3xx_nand_cmdset *cmdset;
fe69af00 126
127 struct clk *clk;
128 void __iomem *mmio_base;
8638fac8 129 unsigned long mmio_phys;
fe69af00 130
131 unsigned int buf_start;
132 unsigned int buf_count;
133
e353a20a 134 struct mtd_info *mtd;
fe69af00 135 /* DMA information */
136 int drcmr_dat;
137 int drcmr_cmd;
138
139 unsigned char *data_buff;
18c81b18 140 unsigned char *oob_buff;
fe69af00 141 dma_addr_t data_buff_phys;
142 size_t data_buff_size;
143 int data_dma_ch;
144 struct pxa_dma_desc *data_desc;
145 dma_addr_t data_desc_addr;
146
147 uint32_t reg_ndcr;
148
149 /* saved column/page_addr during CMD_SEQIN */
150 int seqin_column;
151 int seqin_page_addr;
152
153 /* relate to the command */
154 unsigned int state;
155
156 int use_ecc; /* use HW ECC ? */
157 int use_dma; /* use DMA ? */
158
18c81b18
LW		 159 unsigned int page_size; /* page size of attached chip */
160 unsigned int data_size; /* data size in FIFO */
fe69af00 161 int retcode;
162 struct completion cmd_complete;
163
164 /* generated NDCBx register values */
165 uint32_t ndcb0;
166 uint32_t ndcb1;
167 uint32_t ndcb2;
c8c17c88 168
18c81b18
LW		 169 /* timing calcuted from setting */
170 uint32_t ndtr0cs0;
171 uint32_t ndtr1cs0;
172
c8c17c88
ES		 173 /* calculated from pxa3xx_nand_flash data */
174 size_t oob_size;
175 size_t read_id_bytes;
176
177 unsigned int col_addr_cycles;
178 unsigned int row_addr_cycles;
fe69af00 179};
180
181static int use_dma = 1;
182module_param(use_dma, bool, 0444);
183MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
184
f271049e
MR		 185/*
186 * Default NAND flash controller configuration setup by the
187 * bootloader. This configuration is used only when pdata->keep_config is set
188 */
c1f82478 189static struct pxa3xx_nand_cmdset default_cmdset = {
fe69af00 190 .read1 = 0x3000,
191 .read2 = 0x0050,
192 .program = 0x1080,
193 .read_status = 0x0070,
194 .read_id = 0x0090,
195 .erase = 0xD060,
196 .reset = 0x00FF,
197 .lock = 0x002A,
198 .unlock = 0x2423,
199 .lock_status = 0x007A,
200};
201
c1f82478 202static struct pxa3xx_nand_timing timing[] = {
227a886c
LW		 203 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
204 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
205 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
206 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
d3490dfd
HZ		 207};
208
c1f82478 209static struct pxa3xx_nand_flash builtin_flash_types[] = {
227a886c
LW		 210 { 0, 0, 2048, 8, 8, 0, &default_cmdset, &timing[0] },
211 { 0x46ec, 32, 512, 16, 16, 4096, &default_cmdset, &timing[1] },
212 { 0xdaec, 64, 2048, 8, 8, 2048, &default_cmdset, &timing[1] },
213 { 0xd7ec, 128, 4096, 8, 8, 8192, &default_cmdset, &timing[1] },
214 { 0xa12c, 64, 2048, 8, 8, 1024, &default_cmdset, &timing[2] },
215 { 0xb12c, 64, 2048, 16, 16, 1024, &default_cmdset, &timing[2] },
216 { 0xdc2c, 64, 2048, 8, 8, 4096, &default_cmdset, &timing[2] },
217 { 0xcc2c, 64, 2048, 16, 16, 4096, &default_cmdset, &timing[2] },
218 { 0xba20, 64, 2048, 16, 16, 2048, &default_cmdset, &timing[3] },
d3490dfd
HZ		 219};
220
227a886c
LW		 221/* Define a default flash type setting serve as flash detecting only */
222#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
223
fe69af00 224#define NDTR0_tCH(c) (min((c), 7) << 19)
225#define NDTR0_tCS(c) (min((c), 7) << 16)
226#define NDTR0_tWH(c) (min((c), 7) << 11)
227#define NDTR0_tWP(c) (min((c), 7) << 8)
228#define NDTR0_tRH(c) (min((c), 7) << 3)
229#define NDTR0_tRP(c) (min((c), 7) << 0)
230
231#define NDTR1_tR(c) (min((c), 65535) << 16)
232#define NDTR1_tWHR(c) (min((c), 15) << 4)
233#define NDTR1_tAR(c) (min((c), 15) << 0)
234
235/* convert nano-seconds to nand flash controller clock cycles */
93b352fc 236#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
fe69af00 237
238static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
7dad482e 239 const struct pxa3xx_nand_timing *t)
fe69af00 240{
241 unsigned long nand_clk = clk_get_rate(info->clk);
242 uint32_t ndtr0, ndtr1;
243
244 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
245 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
246 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
247 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
248 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
249 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
250
251 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
252 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
253 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
254
18c81b18
LW		 255 info->ndtr0cs0 = ndtr0;
256 info->ndtr1cs0 = ndtr1;
fe69af00 257 nand_writel(info, NDTR0CS0, ndtr0);
258 nand_writel(info, NDTR1CS0, ndtr1);
259}
260
261#define WAIT_EVENT_TIMEOUT 10
262
263static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
264{
265 int timeout = WAIT_EVENT_TIMEOUT;
266 uint32_t ndsr;
267
268 while (timeout--) {
269 ndsr = nand_readl(info, NDSR) & NDSR_MASK;
270 if (ndsr & event) {
271 nand_writel(info, NDSR, ndsr);
272 return 0;
273 }
274 udelay(10);
275 }
276
277 return -ETIMEDOUT;
278}
279
18c81b18 280static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
fe69af00 281{
9d8b1043
LW		 282 int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
283
284 info->data_size = info->page_size;
285 if (!oob_enable) {
286 info->oob_size = 0;
287 return;
288 }
289
18c81b18 290 switch (info->page_size) {
fe69af00 291 case 2048:
9d8b1043 292 info->oob_size = (info->use_ecc) ? 40 : 64;
fe69af00 293 break;
294 case 512:
9d8b1043 295 info->oob_size = (info->use_ecc) ? 8 : 16;
fe69af00 296 break;
fe69af00 297 }
18c81b18
LW		 298}
299
f8155a40
LW		 300/**
301 * NOTE: it is a must to set ND_RUN firstly, then write
302 * command buffer, otherwise, it does not work.
303 * We enable all the interrupt at the same time, and
304 * let pxa3xx_nand_irq to handle all logic.
305 */
306static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
307{
308 uint32_t ndcr;
309
310 ndcr = info->reg_ndcr;
311 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
312 ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
313 ndcr |= NDCR_ND_RUN;
314
315 /* clear status bits and run */
316 nand_writel(info, NDCR, 0);
317 nand_writel(info, NDSR, NDSR_MASK);
318 nand_writel(info, NDCR, ndcr);
319}
320
321static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
322{
323 uint32_t ndcr;
324 int timeout = NAND_STOP_DELAY;
325
326 /* wait RUN bit in NDCR become 0 */
327 ndcr = nand_readl(info, NDCR);
328 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
329 ndcr = nand_readl(info, NDCR);
330 udelay(1);
331 }
332
333 if (timeout <= 0) {
334 ndcr &= ~NDCR_ND_RUN;
335 nand_writel(info, NDCR, ndcr);
336 }
337 /* clear status bits */
338 nand_writel(info, NDSR, NDSR_MASK);
339}
340
341static void prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
18c81b18
LW		 342 uint16_t cmd, int column, int page_addr)
343{
344 const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
345 pxa3xx_set_datasize(info);
fe69af00 346
347 /* generate values for NDCBx registers */
348 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
349 info->ndcb1 = 0;
350 info->ndcb2 = 0;
c8c17c88 351 info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
fe69af00 352
c8c17c88 353 if (info->col_addr_cycles == 2) {
fe69af00 354 /* large block, 2 cycles for column address
355 * row address starts from 3rd cycle
356 */
7f9938d0 357 info->ndcb1 |= page_addr << 16;
c8c17c88 358 if (info->row_addr_cycles == 3)
fe69af00 359 info->ndcb2 = (page_addr >> 16) & 0xff;
360 } else
361 /* small block, 1 cycles for column address
362 * row address starts from 2nd cycle
363 */
7f9938d0 364 info->ndcb1 = page_addr << 8;
fe69af00 365
366 if (cmd == cmdset->program)
367 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
fe69af00 368}
369
f8155a40 370static void prepare_erase_cmd(struct pxa3xx_nand_info *info,
fe69af00 371 uint16_t cmd, int page_addr)
372{
373 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
374 info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
375 info->ndcb1 = page_addr;
376 info->ndcb2 = 0;
fe69af00 377}
378
f8155a40 379static void prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
fe69af00 380{
18c81b18 381 const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
fe69af00 382
383 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
384 info->ndcb1 = 0;
385 info->ndcb2 = 0;
386
9d8b1043 387 info->oob_size = 0;
fe69af00 388 if (cmd == cmdset->read_id) {
f8155a40 389 info->ndcb0 |= NDCB0_CMD_TYPE(3) | NDCB0_ADDR_CYC(1);
fe69af00 390 info->data_size = 8;
391 } else if (cmd == cmdset->read_status) {
392 info->ndcb0 |= NDCB0_CMD_TYPE(4);
393 info->data_size = 8;
394 } else if (cmd == cmdset->reset || cmd == cmdset->lock ||
395 cmd == cmdset->unlock) {
396 info->ndcb0 |= NDCB0_CMD_TYPE(5);
397 } else
f8155a40 398 BUG();
fe69af00 399}
400
401static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
402{
403 uint32_t ndcr;
404
405 ndcr = nand_readl(info, NDCR);
406 nand_writel(info, NDCR, ndcr & ~int_mask);
407}
408
409static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
410{
411 uint32_t ndcr;
412
413 ndcr = nand_readl(info, NDCR);
414 nand_writel(info, NDCR, ndcr | int_mask);
415}
416
417/* NOTE: it is a must to set ND_RUN firstly, then write command buffer
418 * otherwise, it does not work
419 */
420static int write_cmd(struct pxa3xx_nand_info *info)
421{
422 uint32_t ndcr;
423
424 /* clear status bits and run */
425 nand_writel(info, NDSR, NDSR_MASK);
426
427 ndcr = info->reg_ndcr;
428
429 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
430 ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
431 ndcr |= NDCR_ND_RUN;
432
433 nand_writel(info, NDCR, ndcr);
434
435 if (wait_for_event(info, NDSR_WRCMDREQ)) {
436 printk(KERN_ERR "timed out writing command\n");
437 return -ETIMEDOUT;
438 }
439
440 nand_writel(info, NDCB0, info->ndcb0);
441 nand_writel(info, NDCB0, info->ndcb1);
442 nand_writel(info, NDCB0, info->ndcb2);
443 return 0;
444}
445
f8155a40 446static void handle_data_pio(struct pxa3xx_nand_info *info)
fe69af00 447{
fe69af00 448 switch (info->state) {
449 case STATE_PIO_WRITING:
450 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 451 DIV_ROUND_UP(info->data_size, 4));
9d8b1043
LW		 452 if (info->oob_size > 0)
453 __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
454 DIV_ROUND_UP(info->oob_size, 4));
fe69af00 455 break;
456 case STATE_PIO_READING:
457 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 458 DIV_ROUND_UP(info->data_size, 4));
9d8b1043
LW		 459 if (info->oob_size > 0)
460 __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
461 DIV_ROUND_UP(info->oob_size, 4));
fe69af00 462 break;
463 default:
a1c06ee1 464 printk(KERN_ERR "%s: invalid state %d\n", __func__,
fe69af00 465 info->state);
f8155a40 466 BUG();
fe69af00 467 }
fe69af00 468}
469
f8155a40 470static void start_data_dma(struct pxa3xx_nand_info *info)
fe69af00 471{
472 struct pxa_dma_desc *desc = info->data_desc;
9d8b1043 473 int dma_len = ALIGN(info->data_size + info->oob_size, 32);
fe69af00 474
475 desc->ddadr = DDADR_STOP;
476 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
477
f8155a40
LW		 478 switch (info->state) {
479 case STATE_DMA_WRITING:
fe69af00 480 desc->dsadr = info->data_buff_phys;
8638fac8 481 desc->dtadr = info->mmio_phys + NDDB;
fe69af00 482 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
f8155a40
LW		 483 break;
484 case STATE_DMA_READING:
fe69af00 485 desc->dtadr = info->data_buff_phys;
8638fac8 486 desc->dsadr = info->mmio_phys + NDDB;
fe69af00 487 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
f8155a40
LW		 488 break;
489 default:
490 printk(KERN_ERR "%s: invalid state %d\n", __func__,
491 info->state);
492 BUG();
fe69af00 493 }
494
495 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
496 DDADR(info->data_dma_ch) = info->data_desc_addr;
497 DCSR(info->data_dma_ch) |= DCSR_RUN;
498}
499
500static void pxa3xx_nand_data_dma_irq(int channel, void *data)
501{
502 struct pxa3xx_nand_info *info = data;
503 uint32_t dcsr;
504
505 dcsr = DCSR(channel);
506 DCSR(channel) = dcsr;
507
508 if (dcsr & DCSR_BUSERR) {
509 info->retcode = ERR_DMABUSERR;
fe69af00 510 }
511
f8155a40
LW		 512 info->state = STATE_DMA_DONE;
513 enable_int(info, NDCR_INT_MASK);
514 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
fe69af00 515}
516
517static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
518{
519 struct pxa3xx_nand_info *info = devid;
f8155a40 520 unsigned int status, is_completed = 0;
fe69af00 521
522 status = nand_readl(info, NDSR);
523
f8155a40
LW		 524 if (status & NDSR_DBERR)
525 info->retcode = ERR_DBERR;
526 if (status & NDSR_SBERR)
527 info->retcode = ERR_SBERR;
528 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
529 /* whether use dma to transfer data */
fe69af00 530 if (info->use_dma) {
f8155a40
LW		 531 disable_int(info, NDCR_INT_MASK);
532 info->state = (status & NDSR_RDDREQ) ?
533 STATE_DMA_READING : STATE_DMA_WRITING;
534 start_data_dma(info);
535 goto NORMAL_IRQ_EXIT;
fe69af00 536 } else {
f8155a40
LW		 537 info->state = (status & NDSR_RDDREQ) ?
538 STATE_PIO_READING : STATE_PIO_WRITING;
539 handle_data_pio(info);
fe69af00 540 }
fe69af00 541 }
f8155a40
LW		 542 if (status & NDSR_CS0_CMDD) {
543 info->state = STATE_CMD_DONE;
544 is_completed = 1;
fe69af00 545 }
f8155a40
LW		 546 if (status & NDSR_FLASH_RDY)
547 info->state = STATE_READY;
fe69af00 548
f8155a40
LW		 549 if (status & NDSR_WRCMDREQ) {
550 nand_writel(info, NDSR, NDSR_WRCMDREQ);
551 status &= ~NDSR_WRCMDREQ;
552 info->state = STATE_CMD_HANDLE;
553 nand_writel(info, NDCB0, info->ndcb0);
554 nand_writel(info, NDCB0, info->ndcb1);
555 nand_writel(info, NDCB0, info->ndcb2);
fe69af00 556 }
557
f8155a40
LW		 558 /* clear NDSR to let the controller exit the IRQ */
559 nand_writel(info, NDSR, status);
560 if (is_completed)
561 complete(&info->cmd_complete);
562NORMAL_IRQ_EXIT:
563 return IRQ_HANDLED;
fe69af00 564}
565
566static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
567{
568 struct pxa3xx_nand_info *info = mtd->priv;
569 return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
570}
571
572static inline int is_buf_blank(uint8_t *buf, size_t len)
573{
574 for (; len > 0; len--)
575 if (*buf++ != 0xff)
576 return 0;
577 return 1;
578}
579
580static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
a1c06ee1 581 int column, int page_addr)
fe69af00 582{
583 struct pxa3xx_nand_info *info = mtd->priv;
18c81b18 584 const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
f8155a40 585 int ret, exec_cmd = 0;
fe69af00 586
587 info->use_dma = (use_dma) ? 1 : 0;
588 info->use_ecc = 0;
589 info->data_size = 0;
f8155a40
LW		 590 info->state = 0;
591 info->retcode = ERR_NONE;
fe69af00 592
593 switch (command) {
594 case NAND_CMD_READOOB:
595 /* disable HW ECC to get all the OOB data */
596 info->buf_count = mtd->writesize + mtd->oobsize;
597 info->buf_start = mtd->writesize + column;
7ce33aff 598 memset(info->data_buff, 0xFF, info->buf_count);
fe69af00 599
f8155a40
LW		 600 prepare_read_prog_cmd(info, cmdset->read1, column, page_addr);
601 exec_cmd = 1;
fe69af00 602 break;
603
604 case NAND_CMD_READ0:
605 info->use_ecc = 1;
fe69af00 606 info->buf_start = column;
607 info->buf_count = mtd->writesize + mtd->oobsize;
608 memset(info->data_buff, 0xFF, info->buf_count);
609
f8155a40
LW		 610 prepare_read_prog_cmd(info, cmdset->read1, column, page_addr);
611 exec_cmd = 1;
fe69af00 612 break;
613 case NAND_CMD_SEQIN:
614 info->buf_start = column;
615 info->buf_count = mtd->writesize + mtd->oobsize;
616 memset(info->data_buff, 0xff, info->buf_count);
617
618 /* save column/page_addr for next CMD_PAGEPROG */
619 info->seqin_column = column;
620 info->seqin_page_addr = page_addr;
621 break;
622 case NAND_CMD_PAGEPROG:
623 info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
624
f8155a40
LW		 625 prepare_read_prog_cmd(info, cmdset->program,
626 info->seqin_column, info->seqin_page_addr);
627 exec_cmd = 1;
fe69af00 628 break;
629 case NAND_CMD_ERASE1:
f8155a40
LW		 630 prepare_erase_cmd(info, cmdset->erase, page_addr);
631 exec_cmd = 1;
fe69af00 632 break;
633 case NAND_CMD_ERASE2:
634 break;
635 case NAND_CMD_READID:
636 case NAND_CMD_STATUS:
637 info->use_dma = 0; /* force PIO read */
638 info->buf_start = 0;
639 info->buf_count = (command == NAND_CMD_READID) ?
c8c17c88 640 info->read_id_bytes : 1;
fe69af00 641
f8155a40
LW		 642 prepare_other_cmd(info, (command == NAND_CMD_READID) ?
643 cmdset->read_id : cmdset->read_status);
644 exec_cmd = 1;
fe69af00 645 break;
646 case NAND_CMD_RESET:
f8155a40
LW		 647 prepare_other_cmd(info, cmdset->reset);
648 exec_cmd = 1;
fe69af00 649 break;
650 default:
651 printk(KERN_ERR "non-supported command.\n");
652 break;
653 }
654
f8155a40
LW		 655 if (exec_cmd) {
656 init_completion(&info->cmd_complete);
657 pxa3xx_nand_start(info);
658
659 ret = wait_for_completion_timeout(&info->cmd_complete,
660 CHIP_DELAY_TIMEOUT);
661 if (!ret) {
662 printk(KERN_ERR "Wait time out!!!\n");
663 /* Stop State Machine for next command cycle */
664 pxa3xx_nand_stop(info);
665 }
666 info->state = STATE_IDLE;
667 }
668}
669
670static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
671 struct nand_chip *chip, const uint8_t *buf)
672{
673 chip->write_buf(mtd, buf, mtd->writesize);
674 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
675}
676
677static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
678 struct nand_chip *chip, uint8_t *buf, int page)
679{
680 struct pxa3xx_nand_info *info = mtd->priv;
681
682 chip->read_buf(mtd, buf, mtd->writesize);
683 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
684
685 if (info->retcode == ERR_SBERR) {
686 switch (info->use_ecc) {
687 case 1:
688 mtd->ecc_stats.corrected++;
689 break;
690 case 0:
691 default:
692 break;
693 }
694 } else if (info->retcode == ERR_DBERR) {
695 /*
696 * for blank page (all 0xff), HW will calculate its ECC as
697 * 0, which is different from the ECC information within
698 * OOB, ignore such double bit errors
699 */
700 if (is_buf_blank(buf, mtd->writesize))
701 mtd->ecc_stats.failed++;
fe69af00 702 }
f8155a40
LW		 703
704 return 0;
fe69af00 705}
706
707static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
708{
709 struct pxa3xx_nand_info *info = mtd->priv;
710 char retval = 0xFF;
711
712 if (info->buf_start < info->buf_count)
713 /* Has just send a new command? */
714 retval = info->data_buff[info->buf_start++];
715
716 return retval;
717}
718
719static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
720{
721 struct pxa3xx_nand_info *info = mtd->priv;
722 u16 retval = 0xFFFF;
723
724 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
725 retval = *((u16 *)(info->data_buff+info->buf_start));
726 info->buf_start += 2;
727 }
728 return retval;
729}
730
731static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
732{
733 struct pxa3xx_nand_info *info = mtd->priv;
734 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
735
736 memcpy(buf, info->data_buff + info->buf_start, real_len);
737 info->buf_start += real_len;
738}
739
740static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
741 const uint8_t *buf, int len)
742{
743 struct pxa3xx_nand_info *info = mtd->priv;
744 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
745
746 memcpy(info->data_buff + info->buf_start, buf, real_len);
747 info->buf_start += real_len;
748}
749
750static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
751 const uint8_t *buf, int len)
752{
753 return 0;
754}
755
756static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
757{
758 return;
759}
760
761static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
762{
763 struct pxa3xx_nand_info *info = mtd->priv;
764
765 /* pxa3xx_nand_send_command has waited for command complete */
766 if (this->state == FL_WRITING || this->state == FL_ERASING) {
767 if (info->retcode == ERR_NONE)
768 return 0;
769 else {
770 /*
771 * any error make it return 0x01 which will tell
772 * the caller the erase and write fail
773 */
774 return 0x01;
775 }
776 }
777
778 return 0;
779}
780
fe69af00 781static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
782{
18c81b18 783 const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
fe69af00 784 uint32_t ndcr;
785 uint8_t id_buff[8];
786
f8155a40 787 prepare_other_cmd(info, cmdset->read_id);
fe69af00 788
789 /* Send command */
790 if (write_cmd(info))
791 goto fail_timeout;
792
793 /* Wait for CMDDM(command done successfully) */
794 if (wait_for_event(info, NDSR_RDDREQ))
795 goto fail_timeout;
796
797 __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
798 *id = id_buff[0] | (id_buff[1] << 8);
799 return 0;
800
801fail_timeout:
802 ndcr = nand_readl(info, NDCR);
803 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
804 udelay(10);
805 return -ETIMEDOUT;
806}
807
808static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
c8c17c88 809 const struct pxa3xx_nand_flash *f)
fe69af00 810{
811 struct platform_device *pdev = info->pdev;
812 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
f8155a40 813 uint32_t ndcr = 0x0; /* enable all interrupts */
fe69af00 814
815 if (f->page_size != 2048 && f->page_size != 512)
816 return -EINVAL;
817
818 if (f->flash_width != 16 && f->flash_width != 8)
819 return -EINVAL;
820
821 /* calculate flash information */
18c81b18
LW		 822 info->cmdset = f->cmdset;
823 info->page_size = f->page_size;
824 info->oob_buff = info->data_buff + f->page_size;
c8c17c88 825 info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
fe69af00 826
827 /* calculate addressing information */
c8c17c88 828 info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
fe69af00 829
830 if (f->num_blocks * f->page_per_block > 65536)
c8c17c88 831 info->row_addr_cycles = 3;
fe69af00 832 else
c8c17c88 833 info->row_addr_cycles = 2;
fe69af00 834
835 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
c8c17c88 836 ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
fe69af00 837 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
838 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
839 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
840 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
841
c8c17c88 842 ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
fe69af00 843 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
844
845 info->reg_ndcr = ndcr;
846
847 pxa3xx_nand_set_timing(info, f->timing);
fe69af00 848 return 0;
849}
850
f271049e
MR		 851static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
852{
853 uint32_t ndcr = nand_readl(info, NDCR);
854 struct nand_flash_dev *type = NULL;
18c81b18 855 uint32_t id = -1, page_per_block, num_blocks;
f271049e
MR		 856 int i;
857
18c81b18
LW		 858 page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
859 info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
f271049e 860 /* set info fields needed to __readid */
18c81b18 861 info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
f271049e 862 info->reg_ndcr = ndcr;
52d039fd 863 info->cmdset = &default_cmdset;
f271049e 864
f8155a40
LW		 865 pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
866 id = *((uint16_t *)(info->data_buff));
867 if (id == 0)
f271049e
MR		 868 return -ENODEV;
869
870 /* Lookup the flash id */
f271049e
MR		 871 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
872 if (id == nand_flash_ids[i].id) {
873 type = &nand_flash_ids[i];
874 break;
875 }
876 }
877
878 if (!type)
879 return -ENODEV;
880
881 /* fill the missing flash information */
18c81b18
LW		 882 i = __ffs(page_per_block * info->page_size);
883 num_blocks = type->chipsize << (20 - i);
f271049e 884
f271049e 885 /* calculate addressing information */
18c81b18 886 info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;
f271049e 887
18c81b18 888 if (num_blocks * page_per_block > 65536)
f271049e
MR		 889 info->row_addr_cycles = 3;
890 else
891 info->row_addr_cycles = 2;
892
18c81b18
LW		 893 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
894 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
f271049e
MR		 895
896 return 0;
897}
898
c8ac3f81
ES		 899static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
900 const struct pxa3xx_nand_platform_data *pdata)
fe69af00 901{
c8c17c88 902 const struct pxa3xx_nand_flash *f;
2675e944 903 uint32_t id = -1;
fe69af00 904 int i;
905
f271049e
MR		 906 if (pdata->keep_config)
907 if (pxa3xx_nand_detect_config(info) == 0)
908 return 0;
909
227a886c
LW		 910 /* we use default timing to detect id */
911 f = DEFAULT_FLASH_TYPE;
912 pxa3xx_nand_config_flash(info, f);
f8155a40
LW		 913 pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
914 id = *((uint16_t *)(info->data_buff));
227a886c
LW		 915
916 for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
917 /* we first choose the flash definition from platfrom */
918 if (i < pdata->num_flash)
919 f = pdata->flash + i;
920 else
921 f = &builtin_flash_types[i - pdata->num_flash + 1];
922 if (f->chip_id == id) {
923 dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
924 pxa3xx_nand_config_flash(info, f);
fe69af00 925 return 0;
227a886c 926 }
fe69af00 927 }
928
2675e944
ES		 929 dev_warn(&info->pdev->dev,
930 "failed to detect configured nand flash; found %04x instead of\n",
931 id);
fe69af00 932 return -ENODEV;
933}
934
935/* the maximum possible buffer size for large page with OOB data
936 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
937 * data buffer and the DMA descriptor
938 */
939#define MAX_BUFF_SIZE PAGE_SIZE
940
941static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
942{
943 struct platform_device *pdev = info->pdev;
944 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
945
946 if (use_dma == 0) {
947 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
948 if (info->data_buff == NULL)
949 return -ENOMEM;
950 return 0;
951 }
952
953 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
954 &info->data_buff_phys, GFP_KERNEL);
955 if (info->data_buff == NULL) {
956 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
957 return -ENOMEM;
958 }
959
960 info->data_buff_size = MAX_BUFF_SIZE;
961 info->data_desc = (void *)info->data_buff + data_desc_offset;
962 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
963
964 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
965 pxa3xx_nand_data_dma_irq, info);
966 if (info->data_dma_ch < 0) {
967 dev_err(&pdev->dev, "failed to request data dma\n");
968 dma_free_coherent(&pdev->dev, info->data_buff_size,
969 info->data_buff, info->data_buff_phys);
970 return info->data_dma_ch;
971 }
972
973 return 0;
974}
975
976static struct nand_ecclayout hw_smallpage_ecclayout = {
977 .eccbytes = 6,
978 .eccpos = {8, 9, 10, 11, 12, 13 },
979 .oobfree = { {2, 6} }
980};
981
982static struct nand_ecclayout hw_largepage_ecclayout = {
983 .eccbytes = 24,
984 .eccpos = {
985 40, 41, 42, 43, 44, 45, 46, 47,
986 48, 49, 50, 51, 52, 53, 54, 55,
987 56, 57, 58, 59, 60, 61, 62, 63},
988 .oobfree = { {2, 38} }
989};
990
991static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
992 struct pxa3xx_nand_info *info)
993{
fe69af00 994 struct nand_chip *this = &info->nand_chip;
995
18c81b18 996 this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
fe69af00 997
998 this->waitfunc = pxa3xx_nand_waitfunc;
999 this->select_chip = pxa3xx_nand_select_chip;
1000 this->dev_ready = pxa3xx_nand_dev_ready;
1001 this->cmdfunc = pxa3xx_nand_cmdfunc;
f8155a40
LW		 1002 this->ecc.read_page = pxa3xx_nand_read_page_hwecc;
1003 this->ecc.write_page = pxa3xx_nand_write_page_hwecc;
fe69af00 1004 this->read_word = pxa3xx_nand_read_word;
1005 this->read_byte = pxa3xx_nand_read_byte;
1006 this->read_buf = pxa3xx_nand_read_buf;
1007 this->write_buf = pxa3xx_nand_write_buf;
1008 this->verify_buf = pxa3xx_nand_verify_buf;
1009
1010 this->ecc.mode = NAND_ECC_HW;
18c81b18 1011 this->ecc.size = info->page_size;
fe69af00 1012
18c81b18 1013 if (info->page_size == 2048)
fe69af00 1014 this->ecc.layout = &hw_largepage_ecclayout;
1015 else
1016 this->ecc.layout = &hw_smallpage_ecclayout;
1017
a1c06ee1 1018 this->chip_delay = 25;
fe69af00 1019}
1020
e353a20a
LW		 1021static
1022struct pxa3xx_nand_info *alloc_nand_resource(struct platform_device *pdev)
fe69af00 1023{
e353a20a 1024 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
fe69af00 1025 struct pxa3xx_nand_info *info;
fe69af00 1026 struct mtd_info *mtd;
1027 struct resource *r;
e353a20a 1028 int ret, irq;
fe69af00 1029
1030 mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1031 GFP_KERNEL);
a1c06ee1 1032 if (!mtd) {
fe69af00 1033 dev_err(&pdev->dev, "failed to allocate memory\n");
e353a20a 1034 return NULL;
a1c06ee1 1035 }
fe69af00 1036
1037 info = (struct pxa3xx_nand_info *)(&mtd[1]);
1038 info->pdev = pdev;
1039
fe69af00 1040 mtd->priv = info;
e353a20a 1041 info->mtd = mtd;
82a72d10 1042 mtd->owner = THIS_MODULE;
fe69af00 1043
e0d8b13a 1044 info->clk = clk_get(&pdev->dev, NULL);
fe69af00 1045 if (IS_ERR(info->clk)) {
1046 dev_err(&pdev->dev, "failed to get nand clock\n");
1047 ret = PTR_ERR(info->clk);
1048 goto fail_free_mtd;
1049 }
1050 clk_enable(info->clk);
1051
1052 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1053 if (r == NULL) {
1054 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1055 ret = -ENXIO;
1056 goto fail_put_clk;
1057 }
1058 info->drcmr_dat = r->start;
1059
1060 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1061 if (r == NULL) {
1062 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1063 ret = -ENXIO;
1064 goto fail_put_clk;
1065 }
1066 info->drcmr_cmd = r->start;
1067
1068 irq = platform_get_irq(pdev, 0);
1069 if (irq < 0) {
1070 dev_err(&pdev->dev, "no IRQ resource defined\n");
1071 ret = -ENXIO;
1072 goto fail_put_clk;
1073 }
1074
1075 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1076 if (r == NULL) {
1077 dev_err(&pdev->dev, "no IO memory resource defined\n");
1078 ret = -ENODEV;
1079 goto fail_put_clk;
1080 }
1081
b2ed3680 1082 r = request_mem_region(r->start, resource_size(r), pdev->name);
fe69af00 1083 if (r == NULL) {
1084 dev_err(&pdev->dev, "failed to request memory resource\n");
1085 ret = -EBUSY;
1086 goto fail_put_clk;
1087 }
1088
b2ed3680 1089 info->mmio_base = ioremap(r->start, resource_size(r));
fe69af00 1090 if (info->mmio_base == NULL) {
1091 dev_err(&pdev->dev, "ioremap() failed\n");
1092 ret = -ENODEV;
1093 goto fail_free_res;
1094 }
8638fac8 1095 info->mmio_phys = r->start;
fe69af00 1096
1097 ret = pxa3xx_nand_init_buff(info);
1098 if (ret)
1099 goto fail_free_io;
1100
346e1259
HZ		 1101 /* initialize all interrupts to be disabled */
1102 disable_int(info, NDSR_MASK);
1103
dbf5986a
HZ		 1104 ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1105 pdev->name, info);
fe69af00 1106 if (ret < 0) {
1107 dev_err(&pdev->dev, "failed to request IRQ\n");
1108 goto fail_free_buf;
1109 }
1110
c8ac3f81 1111 ret = pxa3xx_nand_detect_flash(info, pdata);
fe69af00 1112 if (ret) {
1113 dev_err(&pdev->dev, "failed to detect flash\n");
1114 ret = -ENODEV;
1115 goto fail_free_irq;
1116 }
1117
1118 pxa3xx_nand_init_mtd(mtd, info);
e353a20a 1119 platform_set_drvdata(pdev, info);
fe69af00 1120
e353a20a 1121 return info;
fe69af00 1122
1123fail_free_irq:
dbf5986a 1124 free_irq(irq, info);
fe69af00 1125fail_free_buf:
1126 if (use_dma) {
1127 pxa_free_dma(info->data_dma_ch);
1128 dma_free_coherent(&pdev->dev, info->data_buff_size,
1129 info->data_buff, info->data_buff_phys);
1130 } else
1131 kfree(info->data_buff);
1132fail_free_io:
1133 iounmap(info->mmio_base);
1134fail_free_res:
b2ed3680 1135 release_mem_region(r->start, resource_size(r));
fe69af00 1136fail_put_clk:
1137 clk_disable(info->clk);
1138 clk_put(info->clk);
1139fail_free_mtd:
1140 kfree(mtd);
e353a20a 1141 return NULL;
fe69af00 1142}
1143
1144static int pxa3xx_nand_remove(struct platform_device *pdev)
1145{
e353a20a
LW		 1146 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1147 struct mtd_info *mtd = info->mtd;
82a72d10 1148 struct resource *r;
dbf5986a 1149 int irq;
fe69af00 1150
1151 platform_set_drvdata(pdev, NULL);
1152
dbf5986a
HZ		 1153 irq = platform_get_irq(pdev, 0);
1154 if (irq >= 0)
1155 free_irq(irq, info);
fe69af00 1156 if (use_dma) {
1157 pxa_free_dma(info->data_dma_ch);
1158 dma_free_writecombine(&pdev->dev, info->data_buff_size,
1159 info->data_buff, info->data_buff_phys);
1160 } else
1161 kfree(info->data_buff);
82a72d10
MR		 1162
1163 iounmap(info->mmio_base);
1164 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1165 release_mem_region(r->start, resource_size(r));
1166
1167 clk_disable(info->clk);
1168 clk_put(info->clk);
1169
f8155a40
LW		 1170 if (mtd) {
1171 del_mtd_device(mtd);
1172#ifdef CONFIG_MTD_PARTITIONS
1173 del_mtd_partitions(mtd);
1174#endif
1175 kfree(mtd);
1176 }
fe69af00 1177 return 0;
1178}
1179
e353a20a
LW		 1180static int pxa3xx_nand_probe(struct platform_device *pdev)
1181{
1182 struct pxa3xx_nand_platform_data *pdata;
1183 struct pxa3xx_nand_info *info;
1184
1185 pdata = pdev->dev.platform_data;
1186 if (!pdata) {
1187 dev_err(&pdev->dev, "no platform data defined\n");
1188 return -ENODEV;
1189 }
1190
1191 info = alloc_nand_resource(pdev);
1192 if (info == NULL)
1193 return -ENOMEM;
1194
1195 if (nand_scan(info->mtd, 1)) {
1196 dev_err(&pdev->dev, "failed to scan nand\n");
1197 pxa3xx_nand_remove(pdev);
1198 return -ENODEV;
1199 }
1200
1201#ifdef CONFIG_MTD_PARTITIONS
1202 if (mtd_has_cmdlinepart()) {
1203 const char *probes[] = { "cmdlinepart", NULL };
1204 struct mtd_partition *parts;
1205 int nr_parts;
1206
1207 nr_parts = parse_mtd_partitions(info->mtd, probes, &parts, 0);
1208
1209 if (nr_parts)
f8155a40 1210 return add_mtd_partitions(info->mtd, parts, nr_parts);
e353a20a
LW		 1211 }
1212
f8155a40 1213 return add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts);
e353a20a
LW		 1214#else
1215 return 0;
1216#endif
1217}
1218
fe69af00 1219#ifdef CONFIG_PM
1220static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1221{
e353a20a
LW		 1222 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1223 struct mtd_info *mtd = info->mtd;
fe69af00 1224
f8155a40 1225 if (info->state) {
fe69af00 1226 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1227 return -EAGAIN;
1228 }
1229
1230 return 0;
1231}
1232
1233static int pxa3xx_nand_resume(struct platform_device *pdev)
1234{
e353a20a
LW		 1235 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1236 struct mtd_info *mtd = info->mtd;
fe69af00 1237
18c81b18
LW		 1238 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1239 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
fe69af00 1240 clk_enable(info->clk);
1241
18c81b18 1242 return 0;
fe69af00 1243}
1244#else
1245#define pxa3xx_nand_suspend NULL
1246#define pxa3xx_nand_resume NULL
1247#endif
1248
1249static struct platform_driver pxa3xx_nand_driver = {
1250 .driver = {
1251 .name = "pxa3xx-nand",
1252 },
1253 .probe = pxa3xx_nand_probe,
1254 .remove = pxa3xx_nand_remove,
1255 .suspend = pxa3xx_nand_suspend,
1256 .resume = pxa3xx_nand_resume,
1257};
1258
1259static int __init pxa3xx_nand_init(void)
1260{
1261 return platform_driver_register(&pxa3xx_nand_driver);
1262}
1263module_init(pxa3xx_nand_init);
1264
1265static void __exit pxa3xx_nand_exit(void)
1266{
1267 platform_driver_unregister(&pxa3xx_nand_driver);
1268}
1269module_exit(pxa3xx_nand_exit);
1270
1271MODULE_LICENSE("GPL");
1272MODULE_DESCRIPTION("PXA3xx NAND controller driver");
Linux kernel - Deliverables
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