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mtd: mxc_nand: support i.MX21
[deliverable/linux.git] / drivers / mtd / nand / r852.c
CommitLineData
67e054e9
ML		 1/*
2 * Copyright © 2009 - Maxim Levitsky
3 * driver for Ricoh xD readers
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/jiffies.h>
13#include <linux/workqueue.h>
14#include <linux/interrupt.h>
f696aa43 15#include <linux/pci.h>
67e054e9 16#include <linux/pci_ids.h>
ada49657 17#include <linux/delay.h>
67e054e9
ML		 18#include <asm/byteorder.h>
19#include <linux/sched.h>
20#include "sm_common.h"
21#include "r852.h"
22
23
ada49657
SR		 24static int r852_enable_dma = 1;
25module_param(r852_enable_dma, bool, S_IRUGO);
26MODULE_PARM_DESC(r852_enable_dma, "Enable usage of the DMA (default)");
67e054e9
ML		 27
28static int debug;
29module_param(debug, int, S_IRUGO | S_IWUSR);
30MODULE_PARM_DESC(debug, "Debug level (0-2)");
31
32/* read register */
33static inline uint8_t r852_read_reg(struct r852_device *dev, int address)
34{
35 uint8_t reg = readb(dev->mmio + address);
36 return reg;
37}
38
39/* write register */
40static inline void r852_write_reg(struct r852_device *dev,
41 int address, uint8_t value)
42{
43 writeb(value, dev->mmio + address);
44 mmiowb();
45}
46
47
48/* read dword sized register */
49static inline uint32_t r852_read_reg_dword(struct r852_device *dev, int address)
50{
51 uint32_t reg = le32_to_cpu(readl(dev->mmio + address));
52 return reg;
53}
54
55/* write dword sized register */
56static inline void r852_write_reg_dword(struct r852_device *dev,
57 int address, uint32_t value)
58{
59 writel(cpu_to_le32(value), dev->mmio + address);
60 mmiowb();
61}
62
63/* returns pointer to our private structure */
64static inline struct r852_device *r852_get_dev(struct mtd_info *mtd)
65{
66 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
67 return (struct r852_device *)chip->priv;
68}
69
70
71/* check if controller supports dma */
72static void r852_dma_test(struct r852_device *dev)
73{
74 dev->dma_usable = (r852_read_reg(dev, R852_DMA_CAP) &
75 (R852_DMA1 | R852_DMA2)) == (R852_DMA1 | R852_DMA2);
76
77 if (!dev->dma_usable)
78 message("Non dma capable device detected, dma disabled");
79
ada49657 80 if (!r852_enable_dma) {
67e054e9
ML		 81 message("disabling dma on user request");
82 dev->dma_usable = 0;
83 }
84}
85
86/*
87 * Enable dma. Enables ether first or second stage of the DMA,
88 * Expects dev->dma_dir and dev->dma_state be set
89 */
90static void r852_dma_enable(struct r852_device *dev)
91{
92 uint8_t dma_reg, dma_irq_reg;
93
94 /* Set up dma settings */
95 dma_reg = r852_read_reg_dword(dev, R852_DMA_SETTINGS);
96 dma_reg &= ~(R852_DMA_READ | R852_DMA_INTERNAL | R852_DMA_MEMORY);
97
98 if (dev->dma_dir)
99 dma_reg |= R852_DMA_READ;
100
fb45d323 101 if (dev->dma_state == DMA_INTERNAL) {
67e054e9 102 dma_reg |= R852_DMA_INTERNAL;
fb45d323
ML		 103 /* Precaution to make sure HW doesn't write */
104 /* to random kernel memory */
105 r852_write_reg_dword(dev, R852_DMA_ADDR,
106 cpu_to_le32(dev->phys_bounce_buffer));
107 } else {
67e054e9
ML		 108 dma_reg |= R852_DMA_MEMORY;
109 r852_write_reg_dword(dev, R852_DMA_ADDR,
110 cpu_to_le32(dev->phys_dma_addr));
111 }
112
fb45d323
ML		 113 /* Precaution: make sure write reached the device */
114 r852_read_reg_dword(dev, R852_DMA_ADDR);
115
67e054e9
ML		 116 r852_write_reg_dword(dev, R852_DMA_SETTINGS, dma_reg);
117
118 /* Set dma irq */
119 dma_irq_reg = r852_read_reg_dword(dev, R852_DMA_IRQ_ENABLE);
120 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE,
121 dma_irq_reg |
122 R852_DMA_IRQ_INTERNAL |
123 R852_DMA_IRQ_ERROR |
124 R852_DMA_IRQ_MEMORY);
125}
126
127/*
128 * Disable dma, called from the interrupt handler, which specifies
129 * success of the operation via 'error' argument
130 */
131static void r852_dma_done(struct r852_device *dev, int error)
132{
133 WARN_ON(dev->dma_stage == 0);
134
135 r852_write_reg_dword(dev, R852_DMA_IRQ_STA,
136 r852_read_reg_dword(dev, R852_DMA_IRQ_STA));
137
138 r852_write_reg_dword(dev, R852_DMA_SETTINGS, 0);
139 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE, 0);
140
fb45d323
ML		 141 /* Precaution to make sure HW doesn't write to random kernel memory */
142 r852_write_reg_dword(dev, R852_DMA_ADDR,
143 cpu_to_le32(dev->phys_bounce_buffer));
144 r852_read_reg_dword(dev, R852_DMA_ADDR);
145
67e054e9
ML		 146 dev->dma_error = error;
147 dev->dma_stage = 0;
148
149 if (dev->phys_dma_addr && dev->phys_dma_addr != dev->phys_bounce_buffer)
150 pci_unmap_single(dev->pci_dev, dev->phys_dma_addr, R852_DMA_LEN,
151 dev->dma_dir ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
152 complete(&dev->dma_done);
153}
154
155/*
156 * Wait, till dma is done, which includes both phases of it
157 */
158static int r852_dma_wait(struct r852_device *dev)
159{
160 long timeout = wait_for_completion_timeout(&dev->dma_done,
161 msecs_to_jiffies(1000));
162 if (!timeout) {
163 dbg("timeout waiting for DMA interrupt");
164 return -ETIMEDOUT;
165 }
166
167 return 0;
168}
169
170/*
171 * Read/Write one page using dma. Only pages can be read (512 bytes)
172*/
173static void r852_do_dma(struct r852_device *dev, uint8_t *buf, int do_read)
174{
175 int bounce = 0;
176 unsigned long flags;
177 int error;
178
179 dev->dma_error = 0;
180
181 /* Set dma direction */
182 dev->dma_dir = do_read;
183 dev->dma_stage = 1;
184
185 dbg_verbose("doing dma %s ", do_read ? "read" : "write");
186
187 /* Set intial dma state: for reading first fill on board buffer,
188 from device, for writes first fill the buffer from memory*/
189 dev->dma_state = do_read ? DMA_INTERNAL : DMA_MEMORY;
190
191 /* if incoming buffer is not page aligned, we should do bounce */
192 if ((unsigned long)buf & (R852_DMA_LEN-1))
193 bounce = 1;
194
195 if (!bounce) {
196 dev->phys_dma_addr = pci_map_single(dev->pci_dev, (void *)buf,
197 R852_DMA_LEN,
198 (do_read ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
199
0c82d3ce 200 if (pci_dma_mapping_error(dev->pci_dev, dev->phys_dma_addr))
67e054e9
ML		 201 bounce = 1;
202 }
203
204 if (bounce) {
205 dbg_verbose("dma: using bounce buffer");
206 dev->phys_dma_addr = dev->phys_bounce_buffer;
207 if (!do_read)
208 memcpy(dev->bounce_buffer, buf, R852_DMA_LEN);
209 }
210
211 /* Enable DMA */
212 spin_lock_irqsave(&dev->irqlock, flags);
213 r852_dma_enable(dev);
214 spin_unlock_irqrestore(&dev->irqlock, flags);
215
216 /* Wait till complete */
217 error = r852_dma_wait(dev);
218
219 if (error) {
220 r852_dma_done(dev, error);
221 return;
222 }
223
224 if (do_read && bounce)
225 memcpy((void *)buf, dev->bounce_buffer, R852_DMA_LEN);
226}
227
228/*
229 * Program data lines of the nand chip to send data to it
230 */
231void r852_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
232{
233 struct r852_device *dev = r852_get_dev(mtd);
234 uint32_t reg;
235
236 /* Don't allow any access to hardware if we suspect card removal */
237 if (dev->card_unstable)
238 return;
239
240 /* Special case for whole sector read */
241 if (len == R852_DMA_LEN && dev->dma_usable) {
242 r852_do_dma(dev, (uint8_t *)buf, 0);
243 return;
244 }
245
246 /* write DWORD chinks - faster */
247 while (len) {
248 reg = buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24;
249 r852_write_reg_dword(dev, R852_DATALINE, reg);
250 buf += 4;
251 len -= 4;
252
253 }
254
255 /* write rest */
256 while (len)
257 r852_write_reg(dev, R852_DATALINE, *buf++);
258}
259
260/*
261 * Read data lines of the nand chip to retrieve data
262 */
263void r852_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
264{
265 struct r852_device *dev = r852_get_dev(mtd);
266 uint32_t reg;
267
268 if (dev->card_unstable) {
269 /* since we can't signal error here, at least, return
270 predictable buffer */
271 memset(buf, 0, len);
272 return;
273 }
274
275 /* special case for whole sector read */
276 if (len == R852_DMA_LEN && dev->dma_usable) {
277 r852_do_dma(dev, buf, 1);
278 return;
279 }
280
281 /* read in dword sized chunks */
282 while (len >= 4) {
283
284 reg = r852_read_reg_dword(dev, R852_DATALINE);
285 *buf++ = reg & 0xFF;
286 *buf++ = (reg >> 8) & 0xFF;
287 *buf++ = (reg >> 16) & 0xFF;
288 *buf++ = (reg >> 24) & 0xFF;
289 len -= 4;
290 }
291
292 /* read the reset by bytes */
293 while (len--)
294 *buf++ = r852_read_reg(dev, R852_DATALINE);
295}
296
297/*
298 * Read one byte from nand chip
299 */
300static uint8_t r852_read_byte(struct mtd_info *mtd)
301{
302 struct r852_device *dev = r852_get_dev(mtd);
303
304 /* Same problem as in r852_read_buf.... */
305 if (dev->card_unstable)
306 return 0;
307
308 return r852_read_reg(dev, R852_DATALINE);
309}
310
311
312/*
313 * Readback the buffer to verify it
314 */
315int r852_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
316{
317 struct r852_device *dev = r852_get_dev(mtd);
318
319 /* We can't be sure about anything here... */
320 if (dev->card_unstable)
321 return -1;
322
323 /* This will never happen, unless you wired up a nand chip
324 with > 512 bytes page size to the reader */
325 if (len > SM_SECTOR_SIZE)
326 return 0;
327
328 r852_read_buf(mtd, dev->tmp_buffer, len);
329 return memcmp(buf, dev->tmp_buffer, len);
330}
331
332/*
333 * Control several chip lines & send commands
334 */
335void r852_cmdctl(struct mtd_info *mtd, int dat, unsigned int ctrl)
336{
337 struct r852_device *dev = r852_get_dev(mtd);
338
339 if (dev->card_unstable)
340 return;
341
342 if (ctrl & NAND_CTRL_CHANGE) {
343
344 dev->ctlreg &= ~(R852_CTL_DATA | R852_CTL_COMMAND |
345 R852_CTL_ON | R852_CTL_CARDENABLE);
346
347 if (ctrl & NAND_ALE)
348 dev->ctlreg |= R852_CTL_DATA;
349
350 if (ctrl & NAND_CLE)
351 dev->ctlreg |= R852_CTL_COMMAND;
352
353 if (ctrl & NAND_NCE)
354 dev->ctlreg |= (R852_CTL_CARDENABLE | R852_CTL_ON);
355 else
356 dev->ctlreg &= ~R852_CTL_WRITE;
357
358 /* when write is stareted, enable write access */
359 if (dat == NAND_CMD_ERASE1)
360 dev->ctlreg |= R852_CTL_WRITE;
361
362 r852_write_reg(dev, R852_CTL, dev->ctlreg);
363 }
364
365 /* HACK: NAND_CMD_SEQIN is called without NAND_CTRL_CHANGE, but we need
366 to set write mode */
367 if (dat == NAND_CMD_SEQIN && (dev->ctlreg & R852_CTL_COMMAND)) {
368 dev->ctlreg |= R852_CTL_WRITE;
369 r852_write_reg(dev, R852_CTL, dev->ctlreg);
370 }
371
372 if (dat != NAND_CMD_NONE)
373 r852_write_reg(dev, R852_DATALINE, dat);
374}
375
376/*
377 * Wait till card is ready.
378 * based on nand_wait, but returns errors on DMA error
379 */
380int r852_wait(struct mtd_info *mtd, struct nand_chip *chip)
381{
382 struct r852_device *dev = (struct r852_device *)chip->priv;
383
384 unsigned long timeout;
385 int status;
386
387 timeout = jiffies + (chip->state == FL_ERASING ?
388 msecs_to_jiffies(400) : msecs_to_jiffies(20));
389
390 while (time_before(jiffies, timeout))
391 if (chip->dev_ready(mtd))
392 break;
393
394 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
395 status = (int)chip->read_byte(mtd);
396
397 /* Unfortunelly, no way to send detailed error status... */
398 if (dev->dma_error) {
399 status |= NAND_STATUS_FAIL;
400 dev->dma_error = 0;
401 }
402 return status;
403}
404
405/*
406 * Check if card is ready
407 */
408
409int r852_ready(struct mtd_info *mtd)
410{
411 struct r852_device *dev = r852_get_dev(mtd);
412 return !(r852_read_reg(dev, R852_CARD_STA) & R852_CARD_STA_BUSY);
413}
414
415
416/*
417 * Set ECC engine mode
418*/
419
420void r852_ecc_hwctl(struct mtd_info *mtd, int mode)
421{
422 struct r852_device *dev = r852_get_dev(mtd);
423
424 if (dev->card_unstable)
425 return;
426
427 switch (mode) {
428 case NAND_ECC_READ:
429 case NAND_ECC_WRITE:
430 /* enable ecc generation/check*/
431 dev->ctlreg |= R852_CTL_ECC_ENABLE;
432
433 /* flush ecc buffer */
434 r852_write_reg(dev, R852_CTL,
435 dev->ctlreg | R852_CTL_ECC_ACCESS);
436
437 r852_read_reg_dword(dev, R852_DATALINE);
438 r852_write_reg(dev, R852_CTL, dev->ctlreg);
439 return;
440
441 case NAND_ECC_READSYN:
442 /* disable ecc generation */
443 dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
444 r852_write_reg(dev, R852_CTL, dev->ctlreg);
445 }
446}
447
448/*
449 * Calculate ECC, only used for writes
450 */
451
452int r852_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
453 uint8_t *ecc_code)
454{
455 struct r852_device *dev = r852_get_dev(mtd);
456 struct sm_oob *oob = (struct sm_oob *)ecc_code;
457 uint32_t ecc1, ecc2;
458
459 if (dev->card_unstable)
460 return 0;
461
462 dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
463 r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
464
465 ecc1 = r852_read_reg_dword(dev, R852_DATALINE);
466 ecc2 = r852_read_reg_dword(dev, R852_DATALINE);
467
468 oob->ecc1[0] = (ecc1) & 0xFF;
469 oob->ecc1[1] = (ecc1 >> 8) & 0xFF;
470 oob->ecc1[2] = (ecc1 >> 16) & 0xFF;
471
472 oob->ecc2[0] = (ecc2) & 0xFF;
473 oob->ecc2[1] = (ecc2 >> 8) & 0xFF;
474 oob->ecc2[2] = (ecc2 >> 16) & 0xFF;
475
476 r852_write_reg(dev, R852_CTL, dev->ctlreg);
477 return 0;
478}
479
480/*
481 * Correct the data using ECC, hw did almost everything for us
482 */
483
484int r852_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
485 uint8_t *read_ecc, uint8_t *calc_ecc)
486{
487 uint16_t ecc_reg;
488 uint8_t ecc_status, err_byte;
489 int i, error = 0;
490
491 struct r852_device *dev = r852_get_dev(mtd);
492
493 if (dev->card_unstable)
494 return 0;
495
496 r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
497 ecc_reg = r852_read_reg_dword(dev, R852_DATALINE);
498 r852_write_reg(dev, R852_CTL, dev->ctlreg);
499
500 for (i = 0 ; i <= 1 ; i++) {
501
502 ecc_status = (ecc_reg >> 8) & 0xFF;
503
504 /* ecc uncorrectable error */
505 if (ecc_status & R852_ECC_FAIL) {
506 dbg("ecc: unrecoverable error, in half %d", i);
507 error = -1;
508 goto exit;
509 }
510
511 /* correctable error */
512 if (ecc_status & R852_ECC_CORRECTABLE) {
513
514 err_byte = ecc_reg & 0xFF;
515 dbg("ecc: recoverable error, "
516 "in half %d, byte %d, bit %d", i,
517 err_byte, ecc_status & R852_ECC_ERR_BIT_MSK);
518
519 dat[err_byte] ^=
520 1 << (ecc_status & R852_ECC_ERR_BIT_MSK);
521 error++;
522 }
523
524 dat += 256;
525 ecc_reg >>= 16;
526 }
527exit:
528 return error;
529}
530
531/*
532 * This is copy of nand_read_oob_std
533 * nand_read_oob_syndrome assumes we can send column address - we can't
534 */
535static int r852_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
536 int page, int sndcmd)
537{
538 if (sndcmd) {
539 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
540 sndcmd = 0;
541 }
542 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
543 return sndcmd;
544}
545
546/*
547 * Start the nand engine
548 */
549
550void r852_engine_enable(struct r852_device *dev)
551{
552 if (r852_read_reg_dword(dev, R852_HW) & R852_HW_UNKNOWN) {
553 r852_write_reg(dev, R852_CTL, R852_CTL_RESET | R852_CTL_ON);
554 r852_write_reg_dword(dev, R852_HW, R852_HW_ENABLED);
555 } else {
556 r852_write_reg_dword(dev, R852_HW, R852_HW_ENABLED);
557 r852_write_reg(dev, R852_CTL, R852_CTL_RESET | R852_CTL_ON);
558 }
559 msleep(300);
560 r852_write_reg(dev, R852_CTL, 0);
561}
562
563
564/*
565 * Stop the nand engine
566 */
567
568void r852_engine_disable(struct r852_device *dev)
569{
570 r852_write_reg_dword(dev, R852_HW, 0);
571 r852_write_reg(dev, R852_CTL, R852_CTL_RESET);
572}
573
574/*
575 * Test if card is present
576 */
577
578void r852_card_update_present(struct r852_device *dev)
579{
580 unsigned long flags;
581 uint8_t reg;
582
583 spin_lock_irqsave(&dev->irqlock, flags);
584 reg = r852_read_reg(dev, R852_CARD_STA);
585 dev->card_detected = !!(reg & R852_CARD_STA_PRESENT);
586 spin_unlock_irqrestore(&dev->irqlock, flags);
587}
588
589/*
590 * Update card detection IRQ state according to current card state
591 * which is read in r852_card_update_present
592 */
593void r852_update_card_detect(struct r852_device *dev)
594{
595 int card_detect_reg = r852_read_reg(dev, R852_CARD_IRQ_ENABLE);
fb45d323 596 dev->card_unstable = 0;
67e054e9
ML		 597
598 card_detect_reg &= ~(R852_CARD_IRQ_REMOVE | R852_CARD_IRQ_INSERT);
599 card_detect_reg |= R852_CARD_IRQ_GENABLE;
600
601 card_detect_reg |= dev->card_detected ?
602 R852_CARD_IRQ_REMOVE : R852_CARD_IRQ_INSERT;
603
604 r852_write_reg(dev, R852_CARD_IRQ_ENABLE, card_detect_reg);
605}
606
607ssize_t r852_media_type_show(struct device *sys_dev,
608 struct device_attribute *attr, char *buf)
609{
610 struct mtd_info *mtd = container_of(sys_dev, struct mtd_info, dev);
611 struct r852_device *dev = r852_get_dev(mtd);
612 char *data = dev->sm ? "smartmedia" : "xd";
613
614 strcpy(buf, data);
615 return strlen(data);
616}
617
618DEVICE_ATTR(media_type, S_IRUGO, r852_media_type_show, NULL);
619
620
621/* Detect properties of card in slot */
622void r852_update_media_status(struct r852_device *dev)
623{
624 uint8_t reg;
625 unsigned long flags;
626 int readonly;
627
628 spin_lock_irqsave(&dev->irqlock, flags);
629 if (!dev->card_detected) {
630 message("card removed");
631 spin_unlock_irqrestore(&dev->irqlock, flags);
632 return ;
633 }
634
635 readonly = r852_read_reg(dev, R852_CARD_STA) & R852_CARD_STA_RO;
636 reg = r852_read_reg(dev, R852_DMA_CAP);
637 dev->sm = (reg & (R852_DMA1 | R852_DMA2)) && (reg & R852_SMBIT);
638
639 message("detected %s %s card in slot",
640 dev->sm ? "SmartMedia" : "xD",
641 readonly ? "readonly" : "writeable");
642
643 dev->readonly = readonly;
644 spin_unlock_irqrestore(&dev->irqlock, flags);
645}
646
647/*
648 * Register the nand device
649 * Called when the card is detected
650 */
651int r852_register_nand_device(struct r852_device *dev)
652{
653 dev->mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
654
655 if (!dev->mtd)
656 goto error1;
657
658 WARN_ON(dev->card_registred);
659
660 dev->mtd->owner = THIS_MODULE;
661 dev->mtd->priv = dev->chip;
662 dev->mtd->dev.parent = &dev->pci_dev->dev;
663
664 if (dev->readonly)
665 dev->chip->options |= NAND_ROM;
666
667 r852_engine_enable(dev);
668
669 if (sm_register_device(dev->mtd))
670 goto error2;
671
133fa8c7
ML		 672 if (device_create_file(&dev->mtd->dev, &dev_attr_media_type))
673 message("can't create media type sysfs attribute");
674
67e054e9
ML		 675 dev->card_registred = 1;
676 return 0;
677error2:
678 kfree(dev->mtd);
679error1:
680 /* Force card redetect */
681 dev->card_detected = 0;
682 return -1;
683}
684
685/*
686 * Unregister the card
687 */
688
689void r852_unregister_nand_device(struct r852_device *dev)
690{
691 if (!dev->card_registred)
692 return;
693
694 device_remove_file(&dev->mtd->dev, &dev_attr_media_type);
695 nand_release(dev->mtd);
696 r852_engine_disable(dev);
697 dev->card_registred = 0;
698 kfree(dev->mtd);
699 dev->mtd = NULL;
700}
701
702/* Card state updater */
703void r852_card_detect_work(struct work_struct *work)
704{
705 struct r852_device *dev =
706 container_of(work, struct r852_device, card_detect_work.work);
707
fb45d323 708 r852_card_update_present(dev);
67e054e9
ML		 709 dev->card_unstable = 0;
710
fb45d323 711 /* False alarm */
67e054e9
ML		 712 if (dev->card_detected == dev->card_registred)
713 goto exit;
714
715 /* Read media properties */
716 r852_update_media_status(dev);
717
718 /* Register the card */
719 if (dev->card_detected)
720 r852_register_nand_device(dev);
721 else
722 r852_unregister_nand_device(dev);
723exit:
724 /* Update detection logic */
725 r852_update_card_detect(dev);
726}
727
728/* Ack + disable IRQ generation */
729static void r852_disable_irqs(struct r852_device *dev)
730{
731 uint8_t reg;
732 reg = r852_read_reg(dev, R852_CARD_IRQ_ENABLE);
733 r852_write_reg(dev, R852_CARD_IRQ_ENABLE, reg & ~R852_CARD_IRQ_MASK);
734
735 reg = r852_read_reg_dword(dev, R852_DMA_IRQ_ENABLE);
736 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE,
737 reg & ~R852_DMA_IRQ_MASK);
738
739 r852_write_reg(dev, R852_CARD_IRQ_STA, R852_CARD_IRQ_MASK);
740 r852_write_reg_dword(dev, R852_DMA_IRQ_STA, R852_DMA_IRQ_MASK);
741}
742
743/* Interrupt handler */
744static irqreturn_t r852_irq(int irq, void *data)
745{
746 struct r852_device *dev = (struct r852_device *)data;
747
748 uint8_t card_status, dma_status;
749 unsigned long flags;
750 irqreturn_t ret = IRQ_NONE;
751
752 spin_lock_irqsave(&dev->irqlock, flags);
753
754 /* We can recieve shared interrupt while pci is suspended
755 in that case reads will return 0xFFFFFFFF.... */
756 if (dev->insuspend)
757 goto out;
758
759 /* handle card detection interrupts first */
760 card_status = r852_read_reg(dev, R852_CARD_IRQ_STA);
761 r852_write_reg(dev, R852_CARD_IRQ_STA, card_status);
762
763 if (card_status & (R852_CARD_IRQ_INSERT|R852_CARD_IRQ_REMOVE)) {
764
765 ret = IRQ_HANDLED;
766 dev->card_detected = !!(card_status & R852_CARD_IRQ_INSERT);
767
768 /* we shouldn't recieve any interrupts if we wait for card
769 to settle */
770 WARN_ON(dev->card_unstable);
771
772 /* disable irqs while card is unstable */
773 /* this will timeout DMA if active, but better that garbage */
774 r852_disable_irqs(dev);
775
776 if (dev->card_unstable)
777 goto out;
778
779 /* let, card state to settle a bit, and then do the work */
780 dev->card_unstable = 1;
781 queue_delayed_work(dev->card_workqueue,
782 &dev->card_detect_work, msecs_to_jiffies(100));
783 goto out;
784 }
785
786
787 /* Handle dma interrupts */
788 dma_status = r852_read_reg_dword(dev, R852_DMA_IRQ_STA);
789 r852_write_reg_dword(dev, R852_DMA_IRQ_STA, dma_status);
790
791 if (dma_status & R852_DMA_IRQ_MASK) {
792
793 ret = IRQ_HANDLED;
794
795 if (dma_status & R852_DMA_IRQ_ERROR) {
796 dbg("recieved dma error IRQ");
797 r852_dma_done(dev, -EIO);
798 goto out;
799 }
800
801 /* recieved DMA interrupt out of nowhere? */
802 WARN_ON_ONCE(dev->dma_stage == 0);
803
804 if (dev->dma_stage == 0)
805 goto out;
806
807 /* done device access */
808 if (dev->dma_state == DMA_INTERNAL &&
809 (dma_status & R852_DMA_IRQ_INTERNAL)) {
810
811 dev->dma_state = DMA_MEMORY;
812 dev->dma_stage++;
813 }
814
815 /* done memory DMA */
816 if (dev->dma_state == DMA_MEMORY &&
817 (dma_status & R852_DMA_IRQ_MEMORY)) {
818 dev->dma_state = DMA_INTERNAL;
819 dev->dma_stage++;
820 }
821
822 /* Enable 2nd half of dma dance */
823 if (dev->dma_stage == 2)
824 r852_dma_enable(dev);
825
826 /* Operation done */
827 if (dev->dma_stage == 3)
828 r852_dma_done(dev, 0);
829 goto out;
830 }
831
832 /* Handle unknown interrupts */
833 if (dma_status)
834 dbg("bad dma IRQ status = %x", dma_status);
835
836 if (card_status & ~R852_CARD_STA_CD)
837 dbg("strange card status = %x", card_status);
838
839out:
840 spin_unlock_irqrestore(&dev->irqlock, flags);
841 return ret;
842}
843
844int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
845{
846 int error;
847 struct nand_chip *chip;
848 struct r852_device *dev;
849
850 /* pci initialization */
851 error = pci_enable_device(pci_dev);
852
853 if (error)
854 goto error1;
855
856 pci_set_master(pci_dev);
857
133fa8c7 858 error = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
67e054e9
ML		 859 if (error)
860 goto error2;
861
862 error = pci_request_regions(pci_dev, DRV_NAME);
863
864 if (error)
865 goto error3;
866
867 error = -ENOMEM;
868
869 /* init nand chip, but register it only on card insert */
870 chip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
871
872 if (!chip)
873 goto error4;
874
875 /* commands */
876 chip->cmd_ctrl = r852_cmdctl;
877 chip->waitfunc = r852_wait;
878 chip->dev_ready = r852_ready;
879
880 /* I/O */
881 chip->read_byte = r852_read_byte;
882 chip->read_buf = r852_read_buf;
883 chip->write_buf = r852_write_buf;
884 chip->verify_buf = r852_verify_buf;
885
886 /* ecc */
887 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
888 chip->ecc.size = R852_DMA_LEN;
889 chip->ecc.bytes = SM_OOB_SIZE;
890 chip->ecc.hwctl = r852_ecc_hwctl;
891 chip->ecc.calculate = r852_ecc_calculate;
892 chip->ecc.correct = r852_ecc_correct;
893
894 /* TODO: hack */
895 chip->ecc.read_oob = r852_read_oob;
896
897 /* init our device structure */
898 dev = kzalloc(sizeof(struct r852_device), GFP_KERNEL);
899
900 if (!dev)
901 goto error5;
902
903 chip->priv = dev;
904 dev->chip = chip;
905 dev->pci_dev = pci_dev;
906 pci_set_drvdata(pci_dev, dev);
907
908 dev->bounce_buffer = pci_alloc_consistent(pci_dev, R852_DMA_LEN,
909 &dev->phys_bounce_buffer);
910
911 if (!dev->bounce_buffer)
912 goto error6;
913
914
915 error = -ENODEV;
916 dev->mmio = pci_ioremap_bar(pci_dev, 0);
917
918 if (!dev->mmio)
919 goto error7;
920
921 error = -ENOMEM;
922 dev->tmp_buffer = kzalloc(SM_SECTOR_SIZE, GFP_KERNEL);
923
924 if (!dev->tmp_buffer)
925 goto error8;
926
927 init_completion(&dev->dma_done);
928
929 dev->card_workqueue = create_freezeable_workqueue(DRV_NAME);
930
931 if (!dev->card_workqueue)
932 goto error9;
933
934 INIT_DELAYED_WORK(&dev->card_detect_work, r852_card_detect_work);
935
936 /* shutdown everything - precation */
937 r852_engine_disable(dev);
938 r852_disable_irqs(dev);
939
940 r852_dma_test(dev);
941
942 /*register irq handler*/
943 error = -ENODEV;
944 if (request_irq(pci_dev->irq, &r852_irq, IRQF_SHARED,
945 DRV_NAME, dev))
946 goto error10;
947
948 dev->irq = pci_dev->irq;
949 spin_lock_init(&dev->irqlock);
950
951 /* kick initial present test */
952 dev->card_detected = 0;
953 r852_card_update_present(dev);
954 queue_delayed_work(dev->card_workqueue,
955 &dev->card_detect_work, 0);
956
957
958 printk(KERN_NOTICE DRV_NAME ": driver loaded succesfully\n");
959 return 0;
960
961error10:
962 destroy_workqueue(dev->card_workqueue);
963error9:
964 kfree(dev->tmp_buffer);
965error8:
966 pci_iounmap(pci_dev, dev->mmio);
967error7:
968 pci_free_consistent(pci_dev, R852_DMA_LEN,
969 dev->bounce_buffer, dev->phys_bounce_buffer);
970error6:
971 kfree(dev);
972error5:
973 kfree(chip);
974error4:
975 pci_release_regions(pci_dev);
976error3:
977error2:
978 pci_disable_device(pci_dev);
979error1:
980 return error;
981}
982
983void r852_remove(struct pci_dev *pci_dev)
984{
985 struct r852_device *dev = pci_get_drvdata(pci_dev);
986
987 /* Stop detect workqueue -
988 we are going to unregister the device anyway*/
989 cancel_delayed_work_sync(&dev->card_detect_work);
990 destroy_workqueue(dev->card_workqueue);
991
992 /* Unregister the device, this might make more IO */
993 r852_unregister_nand_device(dev);
994
995 /* Stop interrupts */
996 r852_disable_irqs(dev);
997 synchronize_irq(dev->irq);
998 free_irq(dev->irq, dev);
999
1000 /* Cleanup */
1001 kfree(dev->tmp_buffer);
1002 pci_iounmap(pci_dev, dev->mmio);
1003 pci_free_consistent(pci_dev, R852_DMA_LEN,
1004 dev->bounce_buffer, dev->phys_bounce_buffer);
1005
1006 kfree(dev->chip);
1007 kfree(dev);
1008
1009 /* Shutdown the PCI device */
1010 pci_release_regions(pci_dev);
1011 pci_disable_device(pci_dev);
1012}
1013
1014void r852_shutdown(struct pci_dev *pci_dev)
1015{
1016 struct r852_device *dev = pci_get_drvdata(pci_dev);
1017
1018 cancel_delayed_work_sync(&dev->card_detect_work);
1019 r852_disable_irqs(dev);
1020 synchronize_irq(dev->irq);
1021 pci_disable_device(pci_dev);
1022}
1023
b2aaf7a2 1024#ifdef CONFIG_PM
67e054e9
ML		 1025int r852_suspend(struct device *device)
1026{
1027 struct r852_device *dev = pci_get_drvdata(to_pci_dev(device));
1028 unsigned long flags;
1029
1030 if (dev->ctlreg & R852_CTL_CARDENABLE)
1031 return -EBUSY;
1032
1033 /* First make sure the detect work is gone */
1034 cancel_delayed_work_sync(&dev->card_detect_work);
1035
1036 /* Turn off the interrupts and stop the device */
1037 r852_disable_irqs(dev);
1038 r852_engine_disable(dev);
1039
1040 spin_lock_irqsave(&dev->irqlock, flags);
1041 dev->insuspend = 1;
1042 spin_unlock_irqrestore(&dev->irqlock, flags);
1043
1044 /* At that point, even if interrupt handler is running, it will quit */
1045 /* So wait for this to happen explictly */
1046 synchronize_irq(dev->irq);
1047
1048 /* If card was pulled off just during the suspend, which is very
1049 unlikely, we will remove it on resume, it too late now
1050 anyway... */
1051 dev->card_unstable = 0;
1052
1053 pci_save_state(to_pci_dev(device));
1054 return pci_prepare_to_sleep(to_pci_dev(device));
1055}
1056
1057int r852_resume(struct device *device)
1058{
1059 struct r852_device *dev = pci_get_drvdata(to_pci_dev(device));
1060 unsigned long flags;
1061
1062 /* Turn on the hardware */
1063 pci_back_from_sleep(to_pci_dev(device));
1064 pci_restore_state(to_pci_dev(device));
1065
1066 r852_disable_irqs(dev);
1067 r852_card_update_present(dev);
1068 r852_engine_disable(dev);
1069
1070
1071 /* Now its safe for IRQ to run */
1072 spin_lock_irqsave(&dev->irqlock, flags);
1073 dev->insuspend = 0;
1074 spin_unlock_irqrestore(&dev->irqlock, flags);
1075
1076
1077 /* If card status changed, just do the work */
1078 if (dev->card_detected != dev->card_registred) {
1079 dbg("card was %s during low power state",
1080 dev->card_detected ? "added" : "removed");
1081
1082 queue_delayed_work(dev->card_workqueue,
1083 &dev->card_detect_work, 1000);
1084 return 0;
1085 }
1086
1087 /* Otherwise, initialize the card */
1088 if (dev->card_registred) {
1089 r852_engine_enable(dev);
1090 dev->chip->select_chip(dev->mtd, 0);
1091 dev->chip->cmdfunc(dev->mtd, NAND_CMD_RESET, -1, -1);
1092 dev->chip->select_chip(dev->mtd, -1);
1093 }
1094
1095 /* Program card detection IRQ */
1096 r852_update_card_detect(dev);
1097 return 0;
1098}
b2aaf7a2
RD		 1099#else
1100#define r852_suspend NULL
1101#define r852_resume NULL
1102#endif
67e054e9
ML		 1103
1104static const struct pci_device_id r852_pci_id_tbl[] = {
1105
d4080cb3 1106 { PCI_VDEVICE(RICOH, 0x0852), },
67e054e9
ML		 1107 { },
1108};
1109
1110MODULE_DEVICE_TABLE(pci, r852_pci_id_tbl);
1111
1112SIMPLE_DEV_PM_OPS(r852_pm_ops, r852_suspend, r852_resume);
1113
1114
1115static struct pci_driver r852_pci_driver = {
1116 .name = DRV_NAME,
1117 .id_table = r852_pci_id_tbl,
1118 .probe = r852_probe,
1119 .remove = r852_remove,
1120 .shutdown = r852_shutdown,
1121 .driver.pm = &r852_pm_ops,
1122};
1123
1124static __init int r852_module_init(void)
1125{
1126 return pci_register_driver(&r852_pci_driver);
1127}
1128
1129static void __exit r852_module_exit(void)
1130{
1131 pci_unregister_driver(&r852_pci_driver);
1132}
1133
1134module_init(r852_module_init);
1135module_exit(r852_module_exit);
1136
1137MODULE_LICENSE("GPL");
1138MODULE_AUTHOR("Maxim Levitsky <maximlevitsky@gmail.com>");
1139MODULE_DESCRIPTION("Ricoh 85xx xD/smartmedia card reader driver");
Linux kernel - Deliverables
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