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mtd: nand: r852: fix name space clash
[deliverable/linux.git] / drivers / mtd / nand / r852.c
CommitLineData
67e054e9
ML		 1/*
2 * Copyright © 2009 - Maxim Levitsky
3 * driver for Ricoh xD readers
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/jiffies.h>
13#include <linux/workqueue.h>
14#include <linux/interrupt.h>
15#include <linux/pci_ids.h>
ada49657 16#include <linux/delay.h>
67e054e9
ML		 17#include <asm/byteorder.h>
18#include <linux/sched.h>
19#include "sm_common.h"
20#include "r852.h"
21
22
ada49657
SR		 23static int r852_enable_dma = 1;
24module_param(r852_enable_dma, bool, S_IRUGO);
25MODULE_PARM_DESC(r852_enable_dma, "Enable usage of the DMA (default)");
67e054e9
ML		 26
27static int debug;
28module_param(debug, int, S_IRUGO | S_IWUSR);
29MODULE_PARM_DESC(debug, "Debug level (0-2)");
30
31/* read register */
32static inline uint8_t r852_read_reg(struct r852_device *dev, int address)
33{
34 uint8_t reg = readb(dev->mmio + address);
35 return reg;
36}
37
38/* write register */
39static inline void r852_write_reg(struct r852_device *dev,
40 int address, uint8_t value)
41{
42 writeb(value, dev->mmio + address);
43 mmiowb();
44}
45
46
47/* read dword sized register */
48static inline uint32_t r852_read_reg_dword(struct r852_device *dev, int address)
49{
50 uint32_t reg = le32_to_cpu(readl(dev->mmio + address));
51 return reg;
52}
53
54/* write dword sized register */
55static inline void r852_write_reg_dword(struct r852_device *dev,
56 int address, uint32_t value)
57{
58 writel(cpu_to_le32(value), dev->mmio + address);
59 mmiowb();
60}
61
62/* returns pointer to our private structure */
63static inline struct r852_device *r852_get_dev(struct mtd_info *mtd)
64{
65 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
66 return (struct r852_device *)chip->priv;
67}
68
69
70/* check if controller supports dma */
71static void r852_dma_test(struct r852_device *dev)
72{
73 dev->dma_usable = (r852_read_reg(dev, R852_DMA_CAP) &
74 (R852_DMA1 | R852_DMA2)) == (R852_DMA1 | R852_DMA2);
75
76 if (!dev->dma_usable)
77 message("Non dma capable device detected, dma disabled");
78
ada49657 79 if (!r852_enable_dma) {
67e054e9
ML		 80 message("disabling dma on user request");
81 dev->dma_usable = 0;
82 }
83}
84
85/*
86 * Enable dma. Enables ether first or second stage of the DMA,
87 * Expects dev->dma_dir and dev->dma_state be set
88 */
89static void r852_dma_enable(struct r852_device *dev)
90{
91 uint8_t dma_reg, dma_irq_reg;
92
93 /* Set up dma settings */
94 dma_reg = r852_read_reg_dword(dev, R852_DMA_SETTINGS);
95 dma_reg &= ~(R852_DMA_READ | R852_DMA_INTERNAL | R852_DMA_MEMORY);
96
97 if (dev->dma_dir)
98 dma_reg |= R852_DMA_READ;
99
fb45d323 100 if (dev->dma_state == DMA_INTERNAL) {
67e054e9 101 dma_reg |= R852_DMA_INTERNAL;
fb45d323
ML		 102 /* Precaution to make sure HW doesn't write */
103 /* to random kernel memory */
104 r852_write_reg_dword(dev, R852_DMA_ADDR,
105 cpu_to_le32(dev->phys_bounce_buffer));
106 } else {
67e054e9
ML		 107 dma_reg |= R852_DMA_MEMORY;
108 r852_write_reg_dword(dev, R852_DMA_ADDR,
109 cpu_to_le32(dev->phys_dma_addr));
110 }
111
fb45d323
ML		 112 /* Precaution: make sure write reached the device */
113 r852_read_reg_dword(dev, R852_DMA_ADDR);
114
67e054e9
ML		 115 r852_write_reg_dword(dev, R852_DMA_SETTINGS, dma_reg);
116
117 /* Set dma irq */
118 dma_irq_reg = r852_read_reg_dword(dev, R852_DMA_IRQ_ENABLE);
119 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE,
120 dma_irq_reg |
121 R852_DMA_IRQ_INTERNAL |
122 R852_DMA_IRQ_ERROR |
123 R852_DMA_IRQ_MEMORY);
124}
125
126/*
127 * Disable dma, called from the interrupt handler, which specifies
128 * success of the operation via 'error' argument
129 */
130static void r852_dma_done(struct r852_device *dev, int error)
131{
132 WARN_ON(dev->dma_stage == 0);
133
134 r852_write_reg_dword(dev, R852_DMA_IRQ_STA,
135 r852_read_reg_dword(dev, R852_DMA_IRQ_STA));
136
137 r852_write_reg_dword(dev, R852_DMA_SETTINGS, 0);
138 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE, 0);
139
fb45d323
ML		 140 /* Precaution to make sure HW doesn't write to random kernel memory */
141 r852_write_reg_dword(dev, R852_DMA_ADDR,
142 cpu_to_le32(dev->phys_bounce_buffer));
143 r852_read_reg_dword(dev, R852_DMA_ADDR);
144
67e054e9
ML		 145 dev->dma_error = error;
146 dev->dma_stage = 0;
147
148 if (dev->phys_dma_addr && dev->phys_dma_addr != dev->phys_bounce_buffer)
149 pci_unmap_single(dev->pci_dev, dev->phys_dma_addr, R852_DMA_LEN,
150 dev->dma_dir ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
151 complete(&dev->dma_done);
152}
153
154/*
155 * Wait, till dma is done, which includes both phases of it
156 */
157static int r852_dma_wait(struct r852_device *dev)
158{
159 long timeout = wait_for_completion_timeout(&dev->dma_done,
160 msecs_to_jiffies(1000));
161 if (!timeout) {
162 dbg("timeout waiting for DMA interrupt");
163 return -ETIMEDOUT;
164 }
165
166 return 0;
167}
168
169/*
170 * Read/Write one page using dma. Only pages can be read (512 bytes)
171*/
172static void r852_do_dma(struct r852_device *dev, uint8_t *buf, int do_read)
173{
174 int bounce = 0;
175 unsigned long flags;
176 int error;
177
178 dev->dma_error = 0;
179
180 /* Set dma direction */
181 dev->dma_dir = do_read;
182 dev->dma_stage = 1;
183
184 dbg_verbose("doing dma %s ", do_read ? "read" : "write");
185
186 /* Set intial dma state: for reading first fill on board buffer,
187 from device, for writes first fill the buffer from memory*/
188 dev->dma_state = do_read ? DMA_INTERNAL : DMA_MEMORY;
189
190 /* if incoming buffer is not page aligned, we should do bounce */
191 if ((unsigned long)buf & (R852_DMA_LEN-1))
192 bounce = 1;
193
194 if (!bounce) {
195 dev->phys_dma_addr = pci_map_single(dev->pci_dev, (void *)buf,
196 R852_DMA_LEN,
197 (do_read ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
198
199 if (dev->phys_dma_addr == DMA_ERROR_CODE)
200 bounce = 1;
201 }
202
203 if (bounce) {
204 dbg_verbose("dma: using bounce buffer");
205 dev->phys_dma_addr = dev->phys_bounce_buffer;
206 if (!do_read)
207 memcpy(dev->bounce_buffer, buf, R852_DMA_LEN);
208 }
209
210 /* Enable DMA */
211 spin_lock_irqsave(&dev->irqlock, flags);
212 r852_dma_enable(dev);
213 spin_unlock_irqrestore(&dev->irqlock, flags);
214
215 /* Wait till complete */
216 error = r852_dma_wait(dev);
217
218 if (error) {
219 r852_dma_done(dev, error);
220 return;
221 }
222
223 if (do_read && bounce)
224 memcpy((void *)buf, dev->bounce_buffer, R852_DMA_LEN);
225}
226
227/*
228 * Program data lines of the nand chip to send data to it
229 */
230void r852_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
231{
232 struct r852_device *dev = r852_get_dev(mtd);
233 uint32_t reg;
234
235 /* Don't allow any access to hardware if we suspect card removal */
236 if (dev->card_unstable)
237 return;
238
239 /* Special case for whole sector read */
240 if (len == R852_DMA_LEN && dev->dma_usable) {
241 r852_do_dma(dev, (uint8_t *)buf, 0);
242 return;
243 }
244
245 /* write DWORD chinks - faster */
246 while (len) {
247 reg = buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24;
248 r852_write_reg_dword(dev, R852_DATALINE, reg);
249 buf += 4;
250 len -= 4;
251
252 }
253
254 /* write rest */
255 while (len)
256 r852_write_reg(dev, R852_DATALINE, *buf++);
257}
258
259/*
260 * Read data lines of the nand chip to retrieve data
261 */
262void r852_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
263{
264 struct r852_device *dev = r852_get_dev(mtd);
265 uint32_t reg;
266
267 if (dev->card_unstable) {
268 /* since we can't signal error here, at least, return
269 predictable buffer */
270 memset(buf, 0, len);
271 return;
272 }
273
274 /* special case for whole sector read */
275 if (len == R852_DMA_LEN && dev->dma_usable) {
276 r852_do_dma(dev, buf, 1);
277 return;
278 }
279
280 /* read in dword sized chunks */
281 while (len >= 4) {
282
283 reg = r852_read_reg_dword(dev, R852_DATALINE);
284 *buf++ = reg & 0xFF;
285 *buf++ = (reg >> 8) & 0xFF;
286 *buf++ = (reg >> 16) & 0xFF;
287 *buf++ = (reg >> 24) & 0xFF;
288 len -= 4;
289 }
290
291 /* read the reset by bytes */
292 while (len--)
293 *buf++ = r852_read_reg(dev, R852_DATALINE);
294}
295
296/*
297 * Read one byte from nand chip
298 */
299static uint8_t r852_read_byte(struct mtd_info *mtd)
300{
301 struct r852_device *dev = r852_get_dev(mtd);
302
303 /* Same problem as in r852_read_buf.... */
304 if (dev->card_unstable)
305 return 0;
306
307 return r852_read_reg(dev, R852_DATALINE);
308}
309
310
311/*
312 * Readback the buffer to verify it
313 */
314int r852_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
315{
316 struct r852_device *dev = r852_get_dev(mtd);
317
318 /* We can't be sure about anything here... */
319 if (dev->card_unstable)
320 return -1;
321
322 /* This will never happen, unless you wired up a nand chip
323 with > 512 bytes page size to the reader */
324 if (len > SM_SECTOR_SIZE)
325 return 0;
326
327 r852_read_buf(mtd, dev->tmp_buffer, len);
328 return memcmp(buf, dev->tmp_buffer, len);
329}
330
331/*
332 * Control several chip lines & send commands
333 */
334void r852_cmdctl(struct mtd_info *mtd, int dat, unsigned int ctrl)
335{
336 struct r852_device *dev = r852_get_dev(mtd);
337
338 if (dev->card_unstable)
339 return;
340
341 if (ctrl & NAND_CTRL_CHANGE) {
342
343 dev->ctlreg &= ~(R852_CTL_DATA | R852_CTL_COMMAND |
344 R852_CTL_ON | R852_CTL_CARDENABLE);
345
346 if (ctrl & NAND_ALE)
347 dev->ctlreg |= R852_CTL_DATA;
348
349 if (ctrl & NAND_CLE)
350 dev->ctlreg |= R852_CTL_COMMAND;
351
352 if (ctrl & NAND_NCE)
353 dev->ctlreg |= (R852_CTL_CARDENABLE | R852_CTL_ON);
354 else
355 dev->ctlreg &= ~R852_CTL_WRITE;
356
357 /* when write is stareted, enable write access */
358 if (dat == NAND_CMD_ERASE1)
359 dev->ctlreg |= R852_CTL_WRITE;
360
361 r852_write_reg(dev, R852_CTL, dev->ctlreg);
362 }
363
364 /* HACK: NAND_CMD_SEQIN is called without NAND_CTRL_CHANGE, but we need
365 to set write mode */
366 if (dat == NAND_CMD_SEQIN && (dev->ctlreg & R852_CTL_COMMAND)) {
367 dev->ctlreg |= R852_CTL_WRITE;
368 r852_write_reg(dev, R852_CTL, dev->ctlreg);
369 }
370
371 if (dat != NAND_CMD_NONE)
372 r852_write_reg(dev, R852_DATALINE, dat);
373}
374
375/*
376 * Wait till card is ready.
377 * based on nand_wait, but returns errors on DMA error
378 */
379int r852_wait(struct mtd_info *mtd, struct nand_chip *chip)
380{
381 struct r852_device *dev = (struct r852_device *)chip->priv;
382
383 unsigned long timeout;
384 int status;
385
386 timeout = jiffies + (chip->state == FL_ERASING ?
387 msecs_to_jiffies(400) : msecs_to_jiffies(20));
388
389 while (time_before(jiffies, timeout))
390 if (chip->dev_ready(mtd))
391 break;
392
393 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
394 status = (int)chip->read_byte(mtd);
395
396 /* Unfortunelly, no way to send detailed error status... */
397 if (dev->dma_error) {
398 status |= NAND_STATUS_FAIL;
399 dev->dma_error = 0;
400 }
401 return status;
402}
403
404/*
405 * Check if card is ready
406 */
407
408int r852_ready(struct mtd_info *mtd)
409{
410 struct r852_device *dev = r852_get_dev(mtd);
411 return !(r852_read_reg(dev, R852_CARD_STA) & R852_CARD_STA_BUSY);
412}
413
414
415/*
416 * Set ECC engine mode
417*/
418
419void r852_ecc_hwctl(struct mtd_info *mtd, int mode)
420{
421 struct r852_device *dev = r852_get_dev(mtd);
422
423 if (dev->card_unstable)
424 return;
425
426 switch (mode) {
427 case NAND_ECC_READ:
428 case NAND_ECC_WRITE:
429 /* enable ecc generation/check*/
430 dev->ctlreg |= R852_CTL_ECC_ENABLE;
431
432 /* flush ecc buffer */
433 r852_write_reg(dev, R852_CTL,
434 dev->ctlreg | R852_CTL_ECC_ACCESS);
435
436 r852_read_reg_dword(dev, R852_DATALINE);
437 r852_write_reg(dev, R852_CTL, dev->ctlreg);
438 return;
439
440 case NAND_ECC_READSYN:
441 /* disable ecc generation */
442 dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
443 r852_write_reg(dev, R852_CTL, dev->ctlreg);
444 }
445}
446
447/*
448 * Calculate ECC, only used for writes
449 */
450
451int r852_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
452 uint8_t *ecc_code)
453{
454 struct r852_device *dev = r852_get_dev(mtd);
455 struct sm_oob *oob = (struct sm_oob *)ecc_code;
456 uint32_t ecc1, ecc2;
457
458 if (dev->card_unstable)
459 return 0;
460
461 dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
462 r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
463
464 ecc1 = r852_read_reg_dword(dev, R852_DATALINE);
465 ecc2 = r852_read_reg_dword(dev, R852_DATALINE);
466
467 oob->ecc1[0] = (ecc1) & 0xFF;
468 oob->ecc1[1] = (ecc1 >> 8) & 0xFF;
469 oob->ecc1[2] = (ecc1 >> 16) & 0xFF;
470
471 oob->ecc2[0] = (ecc2) & 0xFF;
472 oob->ecc2[1] = (ecc2 >> 8) & 0xFF;
473 oob->ecc2[2] = (ecc2 >> 16) & 0xFF;
474
475 r852_write_reg(dev, R852_CTL, dev->ctlreg);
476 return 0;
477}
478
479/*
480 * Correct the data using ECC, hw did almost everything for us
481 */
482
483int r852_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
484 uint8_t *read_ecc, uint8_t *calc_ecc)
485{
486 uint16_t ecc_reg;
487 uint8_t ecc_status, err_byte;
488 int i, error = 0;
489
490 struct r852_device *dev = r852_get_dev(mtd);
491
492 if (dev->card_unstable)
493 return 0;
494
495 r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
496 ecc_reg = r852_read_reg_dword(dev, R852_DATALINE);
497 r852_write_reg(dev, R852_CTL, dev->ctlreg);
498
499 for (i = 0 ; i <= 1 ; i++) {
500
501 ecc_status = (ecc_reg >> 8) & 0xFF;
502
503 /* ecc uncorrectable error */
504 if (ecc_status & R852_ECC_FAIL) {
505 dbg("ecc: unrecoverable error, in half %d", i);
506 error = -1;
507 goto exit;
508 }
509
510 /* correctable error */
511 if (ecc_status & R852_ECC_CORRECTABLE) {
512
513 err_byte = ecc_reg & 0xFF;
514 dbg("ecc: recoverable error, "
515 "in half %d, byte %d, bit %d", i,
516 err_byte, ecc_status & R852_ECC_ERR_BIT_MSK);
517
518 dat[err_byte] ^=
519 1 << (ecc_status & R852_ECC_ERR_BIT_MSK);
520 error++;
521 }
522
523 dat += 256;
524 ecc_reg >>= 16;
525 }
526exit:
527 return error;
528}
529
530/*
531 * This is copy of nand_read_oob_std
532 * nand_read_oob_syndrome assumes we can send column address - we can't
533 */
534static int r852_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
535 int page, int sndcmd)
536{
537 if (sndcmd) {
538 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
539 sndcmd = 0;
540 }
541 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
542 return sndcmd;
543}
544
545/*
546 * Start the nand engine
547 */
548
549void r852_engine_enable(struct r852_device *dev)
550{
551 if (r852_read_reg_dword(dev, R852_HW) & R852_HW_UNKNOWN) {
552 r852_write_reg(dev, R852_CTL, R852_CTL_RESET | R852_CTL_ON);
553 r852_write_reg_dword(dev, R852_HW, R852_HW_ENABLED);
554 } else {
555 r852_write_reg_dword(dev, R852_HW, R852_HW_ENABLED);
556 r852_write_reg(dev, R852_CTL, R852_CTL_RESET | R852_CTL_ON);
557 }
558 msleep(300);
559 r852_write_reg(dev, R852_CTL, 0);
560}
561
562
563/*
564 * Stop the nand engine
565 */
566
567void r852_engine_disable(struct r852_device *dev)
568{
569 r852_write_reg_dword(dev, R852_HW, 0);
570 r852_write_reg(dev, R852_CTL, R852_CTL_RESET);
571}
572
573/*
574 * Test if card is present
575 */
576
577void r852_card_update_present(struct r852_device *dev)
578{
579 unsigned long flags;
580 uint8_t reg;
581
582 spin_lock_irqsave(&dev->irqlock, flags);
583 reg = r852_read_reg(dev, R852_CARD_STA);
584 dev->card_detected = !!(reg & R852_CARD_STA_PRESENT);
585 spin_unlock_irqrestore(&dev->irqlock, flags);
586}
587
588/*
589 * Update card detection IRQ state according to current card state
590 * which is read in r852_card_update_present
591 */
592void r852_update_card_detect(struct r852_device *dev)
593{
594 int card_detect_reg = r852_read_reg(dev, R852_CARD_IRQ_ENABLE);
fb45d323 595 dev->card_unstable = 0;
67e054e9
ML		 596
597 card_detect_reg &= ~(R852_CARD_IRQ_REMOVE | R852_CARD_IRQ_INSERT);
598 card_detect_reg |= R852_CARD_IRQ_GENABLE;
599
600 card_detect_reg |= dev->card_detected ?
601 R852_CARD_IRQ_REMOVE : R852_CARD_IRQ_INSERT;
602
603 r852_write_reg(dev, R852_CARD_IRQ_ENABLE, card_detect_reg);
604}
605
606ssize_t r852_media_type_show(struct device *sys_dev,
607 struct device_attribute *attr, char *buf)
608{
609 struct mtd_info *mtd = container_of(sys_dev, struct mtd_info, dev);
610 struct r852_device *dev = r852_get_dev(mtd);
611 char *data = dev->sm ? "smartmedia" : "xd";
612
613 strcpy(buf, data);
614 return strlen(data);
615}
616
617DEVICE_ATTR(media_type, S_IRUGO, r852_media_type_show, NULL);
618
619
620/* Detect properties of card in slot */
621void r852_update_media_status(struct r852_device *dev)
622{
623 uint8_t reg;
624 unsigned long flags;
625 int readonly;
626
627 spin_lock_irqsave(&dev->irqlock, flags);
628 if (!dev->card_detected) {
629 message("card removed");
630 spin_unlock_irqrestore(&dev->irqlock, flags);
631 return ;
632 }
633
634 readonly = r852_read_reg(dev, R852_CARD_STA) & R852_CARD_STA_RO;
635 reg = r852_read_reg(dev, R852_DMA_CAP);
636 dev->sm = (reg & (R852_DMA1 | R852_DMA2)) && (reg & R852_SMBIT);
637
638 message("detected %s %s card in slot",
639 dev->sm ? "SmartMedia" : "xD",
640 readonly ? "readonly" : "writeable");
641
642 dev->readonly = readonly;
643 spin_unlock_irqrestore(&dev->irqlock, flags);
644}
645
646/*
647 * Register the nand device
648 * Called when the card is detected
649 */
650int r852_register_nand_device(struct r852_device *dev)
651{
652 dev->mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
653
654 if (!dev->mtd)
655 goto error1;
656
657 WARN_ON(dev->card_registred);
658
659 dev->mtd->owner = THIS_MODULE;
660 dev->mtd->priv = dev->chip;
661 dev->mtd->dev.parent = &dev->pci_dev->dev;
662
663 if (dev->readonly)
664 dev->chip->options |= NAND_ROM;
665
666 r852_engine_enable(dev);
667
668 if (sm_register_device(dev->mtd))
669 goto error2;
670
133fa8c7
ML		 671 if (device_create_file(&dev->mtd->dev, &dev_attr_media_type))
672 message("can't create media type sysfs attribute");
673
67e054e9
ML		 674 dev->card_registred = 1;
675 return 0;
676error2:
677 kfree(dev->mtd);
678error1:
679 /* Force card redetect */
680 dev->card_detected = 0;
681 return -1;
682}
683
684/*
685 * Unregister the card
686 */
687
688void r852_unregister_nand_device(struct r852_device *dev)
689{
690 if (!dev->card_registred)
691 return;
692
693 device_remove_file(&dev->mtd->dev, &dev_attr_media_type);
694 nand_release(dev->mtd);
695 r852_engine_disable(dev);
696 dev->card_registred = 0;
697 kfree(dev->mtd);
698 dev->mtd = NULL;
699}
700
701/* Card state updater */
702void r852_card_detect_work(struct work_struct *work)
703{
704 struct r852_device *dev =
705 container_of(work, struct r852_device, card_detect_work.work);
706
fb45d323 707 r852_card_update_present(dev);
67e054e9
ML		 708 dev->card_unstable = 0;
709
fb45d323 710 /* False alarm */
67e054e9
ML		 711 if (dev->card_detected == dev->card_registred)
712 goto exit;
713
714 /* Read media properties */
715 r852_update_media_status(dev);
716
717 /* Register the card */
718 if (dev->card_detected)
719 r852_register_nand_device(dev);
720 else
721 r852_unregister_nand_device(dev);
722exit:
723 /* Update detection logic */
724 r852_update_card_detect(dev);
725}
726
727/* Ack + disable IRQ generation */
728static void r852_disable_irqs(struct r852_device *dev)
729{
730 uint8_t reg;
731 reg = r852_read_reg(dev, R852_CARD_IRQ_ENABLE);
732 r852_write_reg(dev, R852_CARD_IRQ_ENABLE, reg & ~R852_CARD_IRQ_MASK);
733
734 reg = r852_read_reg_dword(dev, R852_DMA_IRQ_ENABLE);
735 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE,
736 reg & ~R852_DMA_IRQ_MASK);
737
738 r852_write_reg(dev, R852_CARD_IRQ_STA, R852_CARD_IRQ_MASK);
739 r852_write_reg_dword(dev, R852_DMA_IRQ_STA, R852_DMA_IRQ_MASK);
740}
741
742/* Interrupt handler */
743static irqreturn_t r852_irq(int irq, void *data)
744{
745 struct r852_device *dev = (struct r852_device *)data;
746
747 uint8_t card_status, dma_status;
748 unsigned long flags;
749 irqreturn_t ret = IRQ_NONE;
750
751 spin_lock_irqsave(&dev->irqlock, flags);
752
753 /* We can recieve shared interrupt while pci is suspended
754 in that case reads will return 0xFFFFFFFF.... */
755 if (dev->insuspend)
756 goto out;
757
758 /* handle card detection interrupts first */
759 card_status = r852_read_reg(dev, R852_CARD_IRQ_STA);
760 r852_write_reg(dev, R852_CARD_IRQ_STA, card_status);
761
762 if (card_status & (R852_CARD_IRQ_INSERT|R852_CARD_IRQ_REMOVE)) {
763
764 ret = IRQ_HANDLED;
765 dev->card_detected = !!(card_status & R852_CARD_IRQ_INSERT);
766
767 /* we shouldn't recieve any interrupts if we wait for card
768 to settle */
769 WARN_ON(dev->card_unstable);
770
771 /* disable irqs while card is unstable */
772 /* this will timeout DMA if active, but better that garbage */
773 r852_disable_irqs(dev);
774
775 if (dev->card_unstable)
776 goto out;
777
778 /* let, card state to settle a bit, and then do the work */
779 dev->card_unstable = 1;
780 queue_delayed_work(dev->card_workqueue,
781 &dev->card_detect_work, msecs_to_jiffies(100));
782 goto out;
783 }
784
785
786 /* Handle dma interrupts */
787 dma_status = r852_read_reg_dword(dev, R852_DMA_IRQ_STA);
788 r852_write_reg_dword(dev, R852_DMA_IRQ_STA, dma_status);
789
790 if (dma_status & R852_DMA_IRQ_MASK) {
791
792 ret = IRQ_HANDLED;
793
794 if (dma_status & R852_DMA_IRQ_ERROR) {
795 dbg("recieved dma error IRQ");
796 r852_dma_done(dev, -EIO);
797 goto out;
798 }
799
800 /* recieved DMA interrupt out of nowhere? */
801 WARN_ON_ONCE(dev->dma_stage == 0);
802
803 if (dev->dma_stage == 0)
804 goto out;
805
806 /* done device access */
807 if (dev->dma_state == DMA_INTERNAL &&
808 (dma_status & R852_DMA_IRQ_INTERNAL)) {
809
810 dev->dma_state = DMA_MEMORY;
811 dev->dma_stage++;
812 }
813
814 /* done memory DMA */
815 if (dev->dma_state == DMA_MEMORY &&
816 (dma_status & R852_DMA_IRQ_MEMORY)) {
817 dev->dma_state = DMA_INTERNAL;
818 dev->dma_stage++;
819 }
820
821 /* Enable 2nd half of dma dance */
822 if (dev->dma_stage == 2)
823 r852_dma_enable(dev);
824
825 /* Operation done */
826 if (dev->dma_stage == 3)
827 r852_dma_done(dev, 0);
828 goto out;
829 }
830
831 /* Handle unknown interrupts */
832 if (dma_status)
833 dbg("bad dma IRQ status = %x", dma_status);
834
835 if (card_status & ~R852_CARD_STA_CD)
836 dbg("strange card status = %x", card_status);
837
838out:
839 spin_unlock_irqrestore(&dev->irqlock, flags);
840 return ret;
841}
842
843int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
844{
845 int error;
846 struct nand_chip *chip;
847 struct r852_device *dev;
848
849 /* pci initialization */
850 error = pci_enable_device(pci_dev);
851
852 if (error)
853 goto error1;
854
855 pci_set_master(pci_dev);
856
133fa8c7 857 error = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
67e054e9
ML		 858 if (error)
859 goto error2;
860
861 error = pci_request_regions(pci_dev, DRV_NAME);
862
863 if (error)
864 goto error3;
865
866 error = -ENOMEM;
867
868 /* init nand chip, but register it only on card insert */
869 chip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
870
871 if (!chip)
872 goto error4;
873
874 /* commands */
875 chip->cmd_ctrl = r852_cmdctl;
876 chip->waitfunc = r852_wait;
877 chip->dev_ready = r852_ready;
878
879 /* I/O */
880 chip->read_byte = r852_read_byte;
881 chip->read_buf = r852_read_buf;
882 chip->write_buf = r852_write_buf;
883 chip->verify_buf = r852_verify_buf;
884
885 /* ecc */
886 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
887 chip->ecc.size = R852_DMA_LEN;
888 chip->ecc.bytes = SM_OOB_SIZE;
889 chip->ecc.hwctl = r852_ecc_hwctl;
890 chip->ecc.calculate = r852_ecc_calculate;
891 chip->ecc.correct = r852_ecc_correct;
892
893 /* TODO: hack */
894 chip->ecc.read_oob = r852_read_oob;
895
896 /* init our device structure */
897 dev = kzalloc(sizeof(struct r852_device), GFP_KERNEL);
898
899 if (!dev)
900 goto error5;
901
902 chip->priv = dev;
903 dev->chip = chip;
904 dev->pci_dev = pci_dev;
905 pci_set_drvdata(pci_dev, dev);
906
907 dev->bounce_buffer = pci_alloc_consistent(pci_dev, R852_DMA_LEN,
908 &dev->phys_bounce_buffer);
909
910 if (!dev->bounce_buffer)
911 goto error6;
912
913
914 error = -ENODEV;
915 dev->mmio = pci_ioremap_bar(pci_dev, 0);
916
917 if (!dev->mmio)
918 goto error7;
919
920 error = -ENOMEM;
921 dev->tmp_buffer = kzalloc(SM_SECTOR_SIZE, GFP_KERNEL);
922
923 if (!dev->tmp_buffer)
924 goto error8;
925
926 init_completion(&dev->dma_done);
927
928 dev->card_workqueue = create_freezeable_workqueue(DRV_NAME);
929
930 if (!dev->card_workqueue)
931 goto error9;
932
933 INIT_DELAYED_WORK(&dev->card_detect_work, r852_card_detect_work);
934
935 /* shutdown everything - precation */
936 r852_engine_disable(dev);
937 r852_disable_irqs(dev);
938
939 r852_dma_test(dev);
940
941 /*register irq handler*/
942 error = -ENODEV;
943 if (request_irq(pci_dev->irq, &r852_irq, IRQF_SHARED,
944 DRV_NAME, dev))
945 goto error10;
946
947 dev->irq = pci_dev->irq;
948 spin_lock_init(&dev->irqlock);
949
950 /* kick initial present test */
951 dev->card_detected = 0;
952 r852_card_update_present(dev);
953 queue_delayed_work(dev->card_workqueue,
954 &dev->card_detect_work, 0);
955
956
957 printk(KERN_NOTICE DRV_NAME ": driver loaded succesfully\n");
958 return 0;
959
960error10:
961 destroy_workqueue(dev->card_workqueue);
962error9:
963 kfree(dev->tmp_buffer);
964error8:
965 pci_iounmap(pci_dev, dev->mmio);
966error7:
967 pci_free_consistent(pci_dev, R852_DMA_LEN,
968 dev->bounce_buffer, dev->phys_bounce_buffer);
969error6:
970 kfree(dev);
971error5:
972 kfree(chip);
973error4:
974 pci_release_regions(pci_dev);
975error3:
976error2:
977 pci_disable_device(pci_dev);
978error1:
979 return error;
980}
981
982void r852_remove(struct pci_dev *pci_dev)
983{
984 struct r852_device *dev = pci_get_drvdata(pci_dev);
985
986 /* Stop detect workqueue -
987 we are going to unregister the device anyway*/
988 cancel_delayed_work_sync(&dev->card_detect_work);
989 destroy_workqueue(dev->card_workqueue);
990
991 /* Unregister the device, this might make more IO */
992 r852_unregister_nand_device(dev);
993
994 /* Stop interrupts */
995 r852_disable_irqs(dev);
996 synchronize_irq(dev->irq);
997 free_irq(dev->irq, dev);
998
999 /* Cleanup */
1000 kfree(dev->tmp_buffer);
1001 pci_iounmap(pci_dev, dev->mmio);
1002 pci_free_consistent(pci_dev, R852_DMA_LEN,
1003 dev->bounce_buffer, dev->phys_bounce_buffer);
1004
1005 kfree(dev->chip);
1006 kfree(dev);
1007
1008 /* Shutdown the PCI device */
1009 pci_release_regions(pci_dev);
1010 pci_disable_device(pci_dev);
1011}
1012
1013void r852_shutdown(struct pci_dev *pci_dev)
1014{
1015 struct r852_device *dev = pci_get_drvdata(pci_dev);
1016
1017 cancel_delayed_work_sync(&dev->card_detect_work);
1018 r852_disable_irqs(dev);
1019 synchronize_irq(dev->irq);
1020 pci_disable_device(pci_dev);
1021}
1022
b2aaf7a2 1023#ifdef CONFIG_PM
67e054e9
ML		 1024int r852_suspend(struct device *device)
1025{
1026 struct r852_device *dev = pci_get_drvdata(to_pci_dev(device));
1027 unsigned long flags;
1028
1029 if (dev->ctlreg & R852_CTL_CARDENABLE)
1030 return -EBUSY;
1031
1032 /* First make sure the detect work is gone */
1033 cancel_delayed_work_sync(&dev->card_detect_work);
1034
1035 /* Turn off the interrupts and stop the device */
1036 r852_disable_irqs(dev);
1037 r852_engine_disable(dev);
1038
1039 spin_lock_irqsave(&dev->irqlock, flags);
1040 dev->insuspend = 1;
1041 spin_unlock_irqrestore(&dev->irqlock, flags);
1042
1043 /* At that point, even if interrupt handler is running, it will quit */
1044 /* So wait for this to happen explictly */
1045 synchronize_irq(dev->irq);
1046
1047 /* If card was pulled off just during the suspend, which is very
1048 unlikely, we will remove it on resume, it too late now
1049 anyway... */
1050 dev->card_unstable = 0;
1051
1052 pci_save_state(to_pci_dev(device));
1053 return pci_prepare_to_sleep(to_pci_dev(device));
1054}
1055
1056int r852_resume(struct device *device)
1057{
1058 struct r852_device *dev = pci_get_drvdata(to_pci_dev(device));
1059 unsigned long flags;
1060
1061 /* Turn on the hardware */
1062 pci_back_from_sleep(to_pci_dev(device));
1063 pci_restore_state(to_pci_dev(device));
1064
1065 r852_disable_irqs(dev);
1066 r852_card_update_present(dev);
1067 r852_engine_disable(dev);
1068
1069
1070 /* Now its safe for IRQ to run */
1071 spin_lock_irqsave(&dev->irqlock, flags);
1072 dev->insuspend = 0;
1073 spin_unlock_irqrestore(&dev->irqlock, flags);
1074
1075
1076 /* If card status changed, just do the work */
1077 if (dev->card_detected != dev->card_registred) {
1078 dbg("card was %s during low power state",
1079 dev->card_detected ? "added" : "removed");
1080
1081 queue_delayed_work(dev->card_workqueue,
1082 &dev->card_detect_work, 1000);
1083 return 0;
1084 }
1085
1086 /* Otherwise, initialize the card */
1087 if (dev->card_registred) {
1088 r852_engine_enable(dev);
1089 dev->chip->select_chip(dev->mtd, 0);
1090 dev->chip->cmdfunc(dev->mtd, NAND_CMD_RESET, -1, -1);
1091 dev->chip->select_chip(dev->mtd, -1);
1092 }
1093
1094 /* Program card detection IRQ */
1095 r852_update_card_detect(dev);
1096 return 0;
1097}
b2aaf7a2
RD		 1098#else
1099#define r852_suspend NULL
1100#define r852_resume NULL
1101#endif
67e054e9
ML		 1102
1103static const struct pci_device_id r852_pci_id_tbl[] = {
1104
d4080cb3 1105 { PCI_VDEVICE(RICOH, 0x0852), },
67e054e9
ML		 1106 { },
1107};
1108
1109MODULE_DEVICE_TABLE(pci, r852_pci_id_tbl);
1110
1111SIMPLE_DEV_PM_OPS(r852_pm_ops, r852_suspend, r852_resume);
1112
1113
1114static struct pci_driver r852_pci_driver = {
1115 .name = DRV_NAME,
1116 .id_table = r852_pci_id_tbl,
1117 .probe = r852_probe,
1118 .remove = r852_remove,
1119 .shutdown = r852_shutdown,
1120 .driver.pm = &r852_pm_ops,
1121};
1122
1123static __init int r852_module_init(void)
1124{
1125 return pci_register_driver(&r852_pci_driver);
1126}
1127
1128static void __exit r852_module_exit(void)
1129{
1130 pci_unregister_driver(&r852_pci_driver);
1131}
1132
1133module_init(r852_module_init);
1134module_exit(r852_module_exit);
1135
1136MODULE_LICENSE("GPL");
1137MODULE_AUTHOR("Maxim Levitsky <maximlevitsky@gmail.com>");
1138MODULE_DESCRIPTION("Ricoh 85xx xD/smartmedia card reader driver");
Linux kernel - Deliverables
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