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1da177e4 LT |
1 | /* linux/drivers/mtd/nand/s3c2410.c |
2 | * | |
7e74a507 BD |
3 | * Copyright © 2004-2008 Simtec Electronics |
4 | * http://armlinux.simtec.co.uk/ | |
fdf2fd52 | 5 | * Ben Dooks <ben@simtec.co.uk> |
1da177e4 | 6 | * |
7e74a507 | 7 | * Samsung S3C2410/S3C2440/S3C2412 NAND driver |
1da177e4 | 8 | * |
1da177e4 LT |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
1da177e4 LT |
24 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG |
25 | #define DEBUG | |
26 | #endif | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/ioport.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
1da177e4 LT |
35 | #include <linux/delay.h> |
36 | #include <linux/err.h> | |
4e57b681 | 37 | #include <linux/slab.h> |
f8ce2547 | 38 | #include <linux/clk.h> |
30821fee | 39 | #include <linux/cpufreq.h> |
1da177e4 LT |
40 | |
41 | #include <linux/mtd/mtd.h> | |
42 | #include <linux/mtd/nand.h> | |
43 | #include <linux/mtd/nand_ecc.h> | |
44 | #include <linux/mtd/partitions.h> | |
45 | ||
46 | #include <asm/io.h> | |
1da177e4 | 47 | |
7926b5a3 | 48 | #include <plat/regs-nand.h> |
436d42c6 | 49 | #include <linux/platform_data/mtd-nand-s3c2410.h> |
1da177e4 | 50 | |
1da177e4 LT |
51 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
52 | static int hardware_ecc = 1; | |
53 | #else | |
54 | static int hardware_ecc = 0; | |
55 | #endif | |
56 | ||
d1fef3c5 | 57 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP |
ac497c16 | 58 | static const int clock_stop = 1; |
d1fef3c5 BD |
59 | #else |
60 | static const int clock_stop = 0; | |
61 | #endif | |
62 | ||
63 | ||
1da177e4 LT |
64 | /* new oob placement block for use with hardware ecc generation |
65 | */ | |
66 | ||
5bd34c09 | 67 | static struct nand_ecclayout nand_hw_eccoob = { |
e0c7d767 DW |
68 | .eccbytes = 3, |
69 | .eccpos = {0, 1, 2}, | |
70 | .oobfree = {{8, 8}} | |
1da177e4 LT |
71 | }; |
72 | ||
73 | /* controller and mtd information */ | |
74 | ||
75 | struct s3c2410_nand_info; | |
76 | ||
3db72151 BD |
77 | /** |
78 | * struct s3c2410_nand_mtd - driver MTD structure | |
79 | * @mtd: The MTD instance to pass to the MTD layer. | |
80 | * @chip: The NAND chip information. | |
81 | * @set: The platform information supplied for this set of NAND chips. | |
82 | * @info: Link back to the hardware information. | |
83 | * @scan_res: The result from calling nand_scan_ident(). | |
84 | */ | |
1da177e4 LT |
85 | struct s3c2410_nand_mtd { |
86 | struct mtd_info mtd; | |
87 | struct nand_chip chip; | |
88 | struct s3c2410_nand_set *set; | |
89 | struct s3c2410_nand_info *info; | |
90 | int scan_res; | |
91 | }; | |
92 | ||
2c06a082 BD |
93 | enum s3c_cpu_type { |
94 | TYPE_S3C2410, | |
95 | TYPE_S3C2412, | |
96 | TYPE_S3C2440, | |
97 | }; | |
98 | ||
ac497c16 JP |
99 | enum s3c_nand_clk_state { |
100 | CLOCK_DISABLE = 0, | |
101 | CLOCK_ENABLE, | |
102 | CLOCK_SUSPEND, | |
103 | }; | |
104 | ||
1da177e4 LT |
105 | /* overview of the s3c2410 nand state */ |
106 | ||
3db72151 BD |
107 | /** |
108 | * struct s3c2410_nand_info - NAND controller state. | |
109 | * @mtds: An array of MTD instances on this controoler. | |
110 | * @platform: The platform data for this board. | |
111 | * @device: The platform device we bound to. | |
112 | * @area: The IO area resource that came from request_mem_region(). | |
113 | * @clk: The clock resource for this controller. | |
114 | * @regs: The area mapped for the hardware registers described by @area. | |
115 | * @sel_reg: Pointer to the register controlling the NAND selection. | |
116 | * @sel_bit: The bit in @sel_reg to select the NAND chip. | |
117 | * @mtd_count: The number of MTDs created from this controller. | |
118 | * @save_sel: The contents of @sel_reg to be saved over suspend. | |
119 | * @clk_rate: The clock rate from @clk. | |
ac497c16 | 120 | * @clk_state: The current clock state. |
3db72151 BD |
121 | * @cpu_type: The exact type of this controller. |
122 | */ | |
1da177e4 LT |
123 | struct s3c2410_nand_info { |
124 | /* mtd info */ | |
125 | struct nand_hw_control controller; | |
126 | struct s3c2410_nand_mtd *mtds; | |
127 | struct s3c2410_platform_nand *platform; | |
128 | ||
129 | /* device info */ | |
130 | struct device *device; | |
131 | struct resource *area; | |
132 | struct clk *clk; | |
fdf2fd52 | 133 | void __iomem *regs; |
2c06a082 BD |
134 | void __iomem *sel_reg; |
135 | int sel_bit; | |
1da177e4 | 136 | int mtd_count; |
09160832 | 137 | unsigned long save_sel; |
30821fee | 138 | unsigned long clk_rate; |
ac497c16 | 139 | enum s3c_nand_clk_state clk_state; |
03680b1e | 140 | |
2c06a082 | 141 | enum s3c_cpu_type cpu_type; |
30821fee BD |
142 | |
143 | #ifdef CONFIG_CPU_FREQ | |
144 | struct notifier_block freq_transition; | |
145 | #endif | |
1da177e4 LT |
146 | }; |
147 | ||
148 | /* conversion functions */ | |
149 | ||
150 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) | |
151 | { | |
152 | return container_of(mtd, struct s3c2410_nand_mtd, mtd); | |
153 | } | |
154 | ||
155 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) | |
156 | { | |
157 | return s3c2410_nand_mtd_toours(mtd)->info; | |
158 | } | |
159 | ||
3ae5eaec | 160 | static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) |
1da177e4 | 161 | { |
3ae5eaec | 162 | return platform_get_drvdata(dev); |
1da177e4 LT |
163 | } |
164 | ||
3ae5eaec | 165 | static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) |
1da177e4 | 166 | { |
3ae5eaec | 167 | return dev->dev.platform_data; |
1da177e4 LT |
168 | } |
169 | ||
ac497c16 | 170 | static inline int allow_clk_suspend(struct s3c2410_nand_info *info) |
d1fef3c5 BD |
171 | { |
172 | return clock_stop; | |
173 | } | |
174 | ||
ac497c16 JP |
175 | /** |
176 | * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. | |
177 | * @info: The controller instance. | |
178 | * @new_state: State to which clock should be set. | |
179 | */ | |
180 | static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, | |
181 | enum s3c_nand_clk_state new_state) | |
182 | { | |
183 | if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) | |
184 | return; | |
185 | ||
186 | if (info->clk_state == CLOCK_ENABLE) { | |
187 | if (new_state != CLOCK_ENABLE) | |
188 | clk_disable(info->clk); | |
189 | } else { | |
190 | if (new_state == CLOCK_ENABLE) | |
191 | clk_enable(info->clk); | |
192 | } | |
193 | ||
194 | info->clk_state = new_state; | |
195 | } | |
196 | ||
1da177e4 LT |
197 | /* timing calculations */ |
198 | ||
cfd320fb | 199 | #define NS_IN_KHZ 1000000 |
1da177e4 | 200 | |
3db72151 BD |
201 | /** |
202 | * s3c_nand_calc_rate - calculate timing data. | |
203 | * @wanted: The cycle time in nanoseconds. | |
204 | * @clk: The clock rate in kHz. | |
205 | * @max: The maximum divider value. | |
206 | * | |
207 | * Calculate the timing value from the given parameters. | |
208 | */ | |
2c06a082 | 209 | static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) |
1da177e4 LT |
210 | { |
211 | int result; | |
212 | ||
947391cf | 213 | result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); |
1da177e4 LT |
214 | |
215 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); | |
216 | ||
217 | if (result > max) { | |
e0c7d767 | 218 | printk("%d ns is too big for current clock rate %ld\n", wanted, clk); |
1da177e4 LT |
219 | return -1; |
220 | } | |
221 | ||
222 | if (result < 1) | |
223 | result = 1; | |
224 | ||
225 | return result; | |
226 | } | |
227 | ||
cfd320fb | 228 | #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
1da177e4 LT |
229 | |
230 | /* controller setup */ | |
231 | ||
3db72151 BD |
232 | /** |
233 | * s3c2410_nand_setrate - setup controller timing information. | |
234 | * @info: The controller instance. | |
235 | * | |
236 | * Given the information supplied by the platform, calculate and set | |
237 | * the necessary timing registers in the hardware to generate the | |
238 | * necessary timing cycles to the hardware. | |
239 | */ | |
30821fee | 240 | static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) |
1da177e4 | 241 | { |
30821fee | 242 | struct s3c2410_platform_nand *plat = info->platform; |
2c06a082 | 243 | int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; |
cfd320fb | 244 | int tacls, twrph0, twrph1; |
30821fee | 245 | unsigned long clkrate = clk_get_rate(info->clk); |
2612e523 | 246 | unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); |
30821fee | 247 | unsigned long flags; |
1da177e4 LT |
248 | |
249 | /* calculate the timing information for the controller */ | |
250 | ||
30821fee | 251 | info->clk_rate = clkrate; |
cfd320fb BD |
252 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
253 | ||
1da177e4 | 254 | if (plat != NULL) { |
2c06a082 BD |
255 | tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); |
256 | twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); | |
257 | twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); | |
1da177e4 LT |
258 | } else { |
259 | /* default timings */ | |
2c06a082 | 260 | tacls = tacls_max; |
1da177e4 LT |
261 | twrph0 = 8; |
262 | twrph1 = 8; | |
263 | } | |
61b03bd7 | 264 | |
1da177e4 | 265 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
99974c62 | 266 | dev_err(info->device, "cannot get suitable timings\n"); |
1da177e4 LT |
267 | return -EINVAL; |
268 | } | |
269 | ||
99974c62 | 270 | dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
e0c7d767 | 271 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate)); |
1da177e4 | 272 | |
30821fee BD |
273 | switch (info->cpu_type) { |
274 | case TYPE_S3C2410: | |
275 | mask = (S3C2410_NFCONF_TACLS(3) | | |
276 | S3C2410_NFCONF_TWRPH0(7) | | |
277 | S3C2410_NFCONF_TWRPH1(7)); | |
278 | set = S3C2410_NFCONF_EN; | |
279 | set |= S3C2410_NFCONF_TACLS(tacls - 1); | |
280 | set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); | |
281 | set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); | |
282 | break; | |
283 | ||
284 | case TYPE_S3C2440: | |
285 | case TYPE_S3C2412: | |
a755a385 PK |
286 | mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | |
287 | S3C2440_NFCONF_TWRPH0(7) | | |
288 | S3C2440_NFCONF_TWRPH1(7)); | |
30821fee BD |
289 | |
290 | set = S3C2440_NFCONF_TACLS(tacls - 1); | |
291 | set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); | |
292 | set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); | |
293 | break; | |
294 | ||
295 | default: | |
30821fee BD |
296 | BUG(); |
297 | } | |
298 | ||
30821fee BD |
299 | local_irq_save(flags); |
300 | ||
301 | cfg = readl(info->regs + S3C2410_NFCONF); | |
302 | cfg &= ~mask; | |
303 | cfg |= set; | |
304 | writel(cfg, info->regs + S3C2410_NFCONF); | |
305 | ||
306 | local_irq_restore(flags); | |
307 | ||
ae7304e5 AG |
308 | dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); |
309 | ||
30821fee BD |
310 | return 0; |
311 | } | |
312 | ||
3db72151 BD |
313 | /** |
314 | * s3c2410_nand_inithw - basic hardware initialisation | |
315 | * @info: The hardware state. | |
316 | * | |
317 | * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() | |
318 | * to setup the hardware access speeds and set the controller to be enabled. | |
319 | */ | |
30821fee BD |
320 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) |
321 | { | |
322 | int ret; | |
323 | ||
324 | ret = s3c2410_nand_setrate(info); | |
325 | if (ret < 0) | |
326 | return ret; | |
327 | ||
2c06a082 BD |
328 | switch (info->cpu_type) { |
329 | case TYPE_S3C2410: | |
30821fee | 330 | default: |
2c06a082 BD |
331 | break; |
332 | ||
333 | case TYPE_S3C2440: | |
334 | case TYPE_S3C2412: | |
d1fef3c5 BD |
335 | /* enable the controller and de-assert nFCE */ |
336 | ||
2c06a082 | 337 | writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); |
a4f957f1 | 338 | } |
1da177e4 | 339 | |
1da177e4 LT |
340 | return 0; |
341 | } | |
342 | ||
3db72151 BD |
343 | /** |
344 | * s3c2410_nand_select_chip - select the given nand chip | |
345 | * @mtd: The MTD instance for this chip. | |
346 | * @chip: The chip number. | |
347 | * | |
348 | * This is called by the MTD layer to either select a given chip for the | |
349 | * @mtd instance, or to indicate that the access has finished and the | |
350 | * chip can be de-selected. | |
351 | * | |
352 | * The routine ensures that the nFCE line is correctly setup, and any | |
353 | * platform specific selection code is called to route nFCE to the specific | |
354 | * chip. | |
355 | */ | |
1da177e4 LT |
356 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) |
357 | { | |
358 | struct s3c2410_nand_info *info; | |
61b03bd7 | 359 | struct s3c2410_nand_mtd *nmtd; |
1da177e4 LT |
360 | struct nand_chip *this = mtd->priv; |
361 | unsigned long cur; | |
362 | ||
363 | nmtd = this->priv; | |
364 | info = nmtd->info; | |
365 | ||
ac497c16 JP |
366 | if (chip != -1) |
367 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); | |
d1fef3c5 | 368 | |
2c06a082 | 369 | cur = readl(info->sel_reg); |
1da177e4 LT |
370 | |
371 | if (chip == -1) { | |
2c06a082 | 372 | cur |= info->sel_bit; |
1da177e4 | 373 | } else { |
fb8d82a8 | 374 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
99974c62 | 375 | dev_err(info->device, "invalid chip %d\n", chip); |
1da177e4 LT |
376 | return; |
377 | } | |
378 | ||
379 | if (info->platform != NULL) { | |
380 | if (info->platform->select_chip != NULL) | |
e0c7d767 | 381 | (info->platform->select_chip) (nmtd->set, chip); |
1da177e4 LT |
382 | } |
383 | ||
2c06a082 | 384 | cur &= ~info->sel_bit; |
1da177e4 LT |
385 | } |
386 | ||
2c06a082 | 387 | writel(cur, info->sel_reg); |
d1fef3c5 | 388 | |
ac497c16 JP |
389 | if (chip == -1) |
390 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); | |
1da177e4 LT |
391 | } |
392 | ||
ad3b5fb7 | 393 | /* s3c2410_nand_hwcontrol |
a4f957f1 | 394 | * |
ad3b5fb7 | 395 | * Issue command and address cycles to the chip |
a4f957f1 | 396 | */ |
1da177e4 | 397 | |
7abd3ef9 | 398 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
f9068876 | 399 | unsigned int ctrl) |
1da177e4 LT |
400 | { |
401 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
c9ac5977 | 402 | |
7abd3ef9 TG |
403 | if (cmd == NAND_CMD_NONE) |
404 | return; | |
405 | ||
f9068876 | 406 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
407 | writeb(cmd, info->regs + S3C2410_NFCMD); |
408 | else | |
409 | writeb(cmd, info->regs + S3C2410_NFADDR); | |
a4f957f1 BD |
410 | } |
411 | ||
412 | /* command and control functions */ | |
413 | ||
f9068876 DW |
414 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
415 | unsigned int ctrl) | |
a4f957f1 BD |
416 | { |
417 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 | 418 | |
7abd3ef9 TG |
419 | if (cmd == NAND_CMD_NONE) |
420 | return; | |
421 | ||
f9068876 | 422 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
423 | writeb(cmd, info->regs + S3C2440_NFCMD); |
424 | else | |
425 | writeb(cmd, info->regs + S3C2440_NFADDR); | |
1da177e4 LT |
426 | } |
427 | ||
1da177e4 LT |
428 | /* s3c2410_nand_devready() |
429 | * | |
430 | * returns 0 if the nand is busy, 1 if it is ready | |
431 | */ | |
432 | ||
433 | static int s3c2410_nand_devready(struct mtd_info *mtd) | |
434 | { | |
435 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 LT |
436 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
437 | } | |
438 | ||
2c06a082 BD |
439 | static int s3c2440_nand_devready(struct mtd_info *mtd) |
440 | { | |
441 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
442 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; | |
443 | } | |
444 | ||
445 | static int s3c2412_nand_devready(struct mtd_info *mtd) | |
446 | { | |
447 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
448 | return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; | |
449 | } | |
450 | ||
1da177e4 LT |
451 | /* ECC handling functions */ |
452 | ||
2c06a082 BD |
453 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
454 | u_char *read_ecc, u_char *calc_ecc) | |
1da177e4 | 455 | { |
a2593247 BD |
456 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
457 | unsigned int diff0, diff1, diff2; | |
458 | unsigned int bit, byte; | |
459 | ||
460 | pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); | |
461 | ||
462 | diff0 = read_ecc[0] ^ calc_ecc[0]; | |
463 | diff1 = read_ecc[1] ^ calc_ecc[1]; | |
464 | diff2 = read_ecc[2] ^ calc_ecc[2]; | |
465 | ||
466 | pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n", | |
467 | __func__, | |
468 | read_ecc[0], read_ecc[1], read_ecc[2], | |
469 | calc_ecc[0], calc_ecc[1], calc_ecc[2], | |
470 | diff0, diff1, diff2); | |
471 | ||
472 | if (diff0 == 0 && diff1 == 0 && diff2 == 0) | |
473 | return 0; /* ECC is ok */ | |
474 | ||
c45c6c68 BD |
475 | /* sometimes people do not think about using the ECC, so check |
476 | * to see if we have an 0xff,0xff,0xff read ECC and then ignore | |
477 | * the error, on the assumption that this is an un-eccd page. | |
478 | */ | |
479 | if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff | |
480 | && info->platform->ignore_unset_ecc) | |
481 | return 0; | |
482 | ||
a2593247 BD |
483 | /* Can we correct this ECC (ie, one row and column change). |
484 | * Note, this is similar to the 256 error code on smartmedia */ | |
485 | ||
486 | if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && | |
487 | ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && | |
488 | ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { | |
489 | /* calculate the bit position of the error */ | |
490 | ||
d0bf3793 MR |
491 | bit = ((diff2 >> 3) & 1) | |
492 | ((diff2 >> 4) & 2) | | |
493 | ((diff2 >> 5) & 4); | |
1da177e4 | 494 | |
a2593247 | 495 | /* calculate the byte position of the error */ |
1da177e4 | 496 | |
d0bf3793 MR |
497 | byte = ((diff2 << 7) & 0x100) | |
498 | ((diff1 << 0) & 0x80) | | |
499 | ((diff1 << 1) & 0x40) | | |
500 | ((diff1 << 2) & 0x20) | | |
501 | ((diff1 << 3) & 0x10) | | |
502 | ((diff0 >> 4) & 0x08) | | |
503 | ((diff0 >> 3) & 0x04) | | |
504 | ((diff0 >> 2) & 0x02) | | |
505 | ((diff0 >> 1) & 0x01); | |
a2593247 BD |
506 | |
507 | dev_dbg(info->device, "correcting error bit %d, byte %d\n", | |
508 | bit, byte); | |
509 | ||
510 | dat[byte] ^= (1 << bit); | |
511 | return 1; | |
512 | } | |
513 | ||
514 | /* if there is only one bit difference in the ECC, then | |
515 | * one of only a row or column parity has changed, which | |
516 | * means the error is most probably in the ECC itself */ | |
517 | ||
518 | diff0 |= (diff1 << 8); | |
519 | diff0 |= (diff2 << 16); | |
520 | ||
521 | if ((diff0 & ~(1<<fls(diff0))) == 0) | |
522 | return 1; | |
523 | ||
4fac9f69 | 524 | return -1; |
1da177e4 LT |
525 | } |
526 | ||
a4f957f1 BD |
527 | /* ECC functions |
528 | * | |
529 | * These allow the s3c2410 and s3c2440 to use the controller's ECC | |
530 | * generator block to ECC the data as it passes through] | |
531 | */ | |
532 | ||
1da177e4 LT |
533 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
534 | { | |
535 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
536 | unsigned long ctrl; | |
537 | ||
538 | ctrl = readl(info->regs + S3C2410_NFCONF); | |
539 | ctrl |= S3C2410_NFCONF_INITECC; | |
540 | writel(ctrl, info->regs + S3C2410_NFCONF); | |
541 | } | |
542 | ||
4f659923 MC |
543 | static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
544 | { | |
545 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
546 | unsigned long ctrl; | |
547 | ||
548 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
549 | writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT); | |
550 | } | |
551 | ||
a4f957f1 BD |
552 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
553 | { | |
554 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
555 | unsigned long ctrl; | |
556 | ||
557 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
558 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); | |
559 | } | |
560 | ||
e0c7d767 | 561 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
1da177e4 LT |
562 | { |
563 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
564 | ||
565 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); | |
566 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); | |
567 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); | |
568 | ||
a2593247 BD |
569 | pr_debug("%s: returning ecc %02x%02x%02x\n", __func__, |
570 | ecc_code[0], ecc_code[1], ecc_code[2]); | |
1da177e4 LT |
571 | |
572 | return 0; | |
573 | } | |
574 | ||
4f659923 MC |
575 | static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
576 | { | |
577 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
578 | unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); | |
579 | ||
580 | ecc_code[0] = ecc; | |
581 | ecc_code[1] = ecc >> 8; | |
582 | ecc_code[2] = ecc >> 16; | |
583 | ||
584 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
e0c7d767 | 589 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
a4f957f1 BD |
590 | { |
591 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
592 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); | |
593 | ||
594 | ecc_code[0] = ecc; | |
595 | ecc_code[1] = ecc >> 8; | |
596 | ecc_code[2] = ecc >> 16; | |
597 | ||
71d54f38 | 598 | pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); |
a4f957f1 BD |
599 | |
600 | return 0; | |
601 | } | |
602 | ||
a4f957f1 BD |
603 | /* over-ride the standard functions for a little more speed. We can |
604 | * use read/write block to move the data buffers to/from the controller | |
605 | */ | |
1da177e4 LT |
606 | |
607 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
608 | { | |
609 | struct nand_chip *this = mtd->priv; | |
610 | readsb(this->IO_ADDR_R, buf, len); | |
611 | } | |
612 | ||
b773bb2e MR |
613 | static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
614 | { | |
615 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
616 | |
617 | readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
618 | ||
619 | /* cleanup if we've got less than a word to do */ | |
620 | if (len & 3) { | |
621 | buf += len & ~3; | |
622 | ||
623 | for (; len & 3; len--) | |
624 | *buf++ = readb(info->regs + S3C2440_NFDATA); | |
625 | } | |
b773bb2e MR |
626 | } |
627 | ||
e0c7d767 | 628 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
1da177e4 LT |
629 | { |
630 | struct nand_chip *this = mtd->priv; | |
631 | writesb(this->IO_ADDR_W, buf, len); | |
632 | } | |
633 | ||
b773bb2e MR |
634 | static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
635 | { | |
636 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
637 | |
638 | writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
639 | ||
640 | /* cleanup any fractional write */ | |
641 | if (len & 3) { | |
642 | buf += len & ~3; | |
643 | ||
644 | for (; len & 3; len--, buf++) | |
645 | writeb(*buf, info->regs + S3C2440_NFDATA); | |
646 | } | |
b773bb2e MR |
647 | } |
648 | ||
30821fee BD |
649 | /* cpufreq driver support */ |
650 | ||
651 | #ifdef CONFIG_CPU_FREQ | |
652 | ||
653 | static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, | |
654 | unsigned long val, void *data) | |
655 | { | |
656 | struct s3c2410_nand_info *info; | |
657 | unsigned long newclk; | |
658 | ||
659 | info = container_of(nb, struct s3c2410_nand_info, freq_transition); | |
660 | newclk = clk_get_rate(info->clk); | |
661 | ||
662 | if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || | |
663 | (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { | |
664 | s3c2410_nand_setrate(info); | |
665 | } | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
670 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
671 | { | |
672 | info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; | |
673 | ||
674 | return cpufreq_register_notifier(&info->freq_transition, | |
675 | CPUFREQ_TRANSITION_NOTIFIER); | |
676 | } | |
677 | ||
678 | static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
679 | { | |
680 | cpufreq_unregister_notifier(&info->freq_transition, | |
681 | CPUFREQ_TRANSITION_NOTIFIER); | |
682 | } | |
683 | ||
684 | #else | |
685 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
686 | { | |
687 | return 0; | |
688 | } | |
689 | ||
690 | static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
691 | { | |
692 | } | |
693 | #endif | |
694 | ||
1da177e4 LT |
695 | /* device management functions */ |
696 | ||
ec0482e6 | 697 | static int s3c24xx_nand_remove(struct platform_device *pdev) |
1da177e4 | 698 | { |
3ae5eaec | 699 | struct s3c2410_nand_info *info = to_nand_info(pdev); |
1da177e4 | 700 | |
3ae5eaec | 701 | platform_set_drvdata(pdev, NULL); |
1da177e4 | 702 | |
61b03bd7 | 703 | if (info == NULL) |
1da177e4 LT |
704 | return 0; |
705 | ||
30821fee BD |
706 | s3c2410_nand_cpufreq_deregister(info); |
707 | ||
708 | /* Release all our mtds and their partitions, then go through | |
709 | * freeing the resources used | |
1da177e4 | 710 | */ |
61b03bd7 | 711 | |
1da177e4 LT |
712 | if (info->mtds != NULL) { |
713 | struct s3c2410_nand_mtd *ptr = info->mtds; | |
714 | int mtdno; | |
715 | ||
716 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { | |
717 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); | |
718 | nand_release(&ptr->mtd); | |
719 | } | |
720 | ||
721 | kfree(info->mtds); | |
722 | } | |
723 | ||
724 | /* free the common resources */ | |
725 | ||
4aa10626 | 726 | if (!IS_ERR(info->clk)) { |
ac497c16 | 727 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
1da177e4 LT |
728 | clk_put(info->clk); |
729 | } | |
730 | ||
731 | if (info->regs != NULL) { | |
732 | iounmap(info->regs); | |
733 | info->regs = NULL; | |
734 | } | |
735 | ||
736 | if (info->area != NULL) { | |
737 | release_resource(info->area); | |
738 | kfree(info->area); | |
739 | info->area = NULL; | |
740 | } | |
741 | ||
742 | kfree(info); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
1da177e4 LT |
747 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, |
748 | struct s3c2410_nand_mtd *mtd, | |
749 | struct s3c2410_nand_set *set) | |
750 | { | |
599501a7 DES |
751 | if (set) |
752 | mtd->mtd.name = set->name; | |
ed27f028 | 753 | |
42d7fbe2 AB |
754 | return mtd_device_parse_register(&mtd->mtd, NULL, NULL, |
755 | set->partitions, set->nr_partitions); | |
1da177e4 | 756 | } |
1da177e4 | 757 | |
3db72151 BD |
758 | /** |
759 | * s3c2410_nand_init_chip - initialise a single instance of an chip | |
760 | * @info: The base NAND controller the chip is on. | |
761 | * @nmtd: The new controller MTD instance to fill in. | |
762 | * @set: The information passed from the board specific platform data. | |
1da177e4 | 763 | * |
3db72151 BD |
764 | * Initialise the given @nmtd from the information in @info and @set. This |
765 | * readies the structure for use with the MTD layer functions by ensuring | |
766 | * all pointers are setup and the necessary control routines selected. | |
767 | */ | |
1da177e4 LT |
768 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, |
769 | struct s3c2410_nand_mtd *nmtd, | |
770 | struct s3c2410_nand_set *set) | |
771 | { | |
772 | struct nand_chip *chip = &nmtd->chip; | |
2c06a082 | 773 | void __iomem *regs = info->regs; |
1da177e4 | 774 | |
1da177e4 LT |
775 | chip->write_buf = s3c2410_nand_write_buf; |
776 | chip->read_buf = s3c2410_nand_read_buf; | |
777 | chip->select_chip = s3c2410_nand_select_chip; | |
778 | chip->chip_delay = 50; | |
779 | chip->priv = nmtd; | |
74218fed | 780 | chip->options = set->options; |
1da177e4 LT |
781 | chip->controller = &info->controller; |
782 | ||
2c06a082 BD |
783 | switch (info->cpu_type) { |
784 | case TYPE_S3C2410: | |
785 | chip->IO_ADDR_W = regs + S3C2410_NFDATA; | |
786 | info->sel_reg = regs + S3C2410_NFCONF; | |
787 | info->sel_bit = S3C2410_NFCONF_nFCE; | |
788 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; | |
789 | chip->dev_ready = s3c2410_nand_devready; | |
790 | break; | |
791 | ||
792 | case TYPE_S3C2440: | |
793 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
794 | info->sel_reg = regs + S3C2440_NFCONT; | |
795 | info->sel_bit = S3C2440_NFCONT_nFCE; | |
796 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
797 | chip->dev_ready = s3c2440_nand_devready; | |
b773bb2e MR |
798 | chip->read_buf = s3c2440_nand_read_buf; |
799 | chip->write_buf = s3c2440_nand_write_buf; | |
2c06a082 BD |
800 | break; |
801 | ||
802 | case TYPE_S3C2412: | |
803 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
804 | info->sel_reg = regs + S3C2440_NFCONT; | |
805 | info->sel_bit = S3C2412_NFCONT_nFCE0; | |
806 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
807 | chip->dev_ready = s3c2412_nand_devready; | |
808 | ||
809 | if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) | |
810 | dev_info(info->device, "System booted from NAND\n"); | |
811 | ||
812 | break; | |
813 | } | |
814 | ||
815 | chip->IO_ADDR_R = chip->IO_ADDR_W; | |
a4f957f1 | 816 | |
1da177e4 LT |
817 | nmtd->info = info; |
818 | nmtd->mtd.priv = chip; | |
552d9205 | 819 | nmtd->mtd.owner = THIS_MODULE; |
1da177e4 LT |
820 | nmtd->set = set; |
821 | ||
822 | if (hardware_ecc) { | |
6dfc6d25 | 823 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
2c06a082 | 824 | chip->ecc.correct = s3c2410_nand_correct_data; |
6dfc6d25 | 825 | chip->ecc.mode = NAND_ECC_HW; |
6a918bad | 826 | chip->ecc.strength = 1; |
a4f957f1 | 827 | |
2c06a082 BD |
828 | switch (info->cpu_type) { |
829 | case TYPE_S3C2410: | |
830 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; | |
831 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | |
832 | break; | |
833 | ||
834 | case TYPE_S3C2412: | |
4f659923 MC |
835 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; |
836 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; | |
837 | break; | |
838 | ||
2c06a082 BD |
839 | case TYPE_S3C2440: |
840 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; | |
841 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; | |
842 | break; | |
843 | ||
a4f957f1 | 844 | } |
1da177e4 | 845 | } else { |
6dfc6d25 | 846 | chip->ecc.mode = NAND_ECC_SOFT; |
1da177e4 | 847 | } |
1c21ab67 BD |
848 | |
849 | if (set->ecc_layout != NULL) | |
850 | chip->ecc.layout = set->ecc_layout; | |
37e5ffa3 BD |
851 | |
852 | if (set->disable_ecc) | |
853 | chip->ecc.mode = NAND_ECC_NONE; | |
8c3e843d AG |
854 | |
855 | switch (chip->ecc.mode) { | |
856 | case NAND_ECC_NONE: | |
857 | dev_info(info->device, "NAND ECC disabled\n"); | |
858 | break; | |
859 | case NAND_ECC_SOFT: | |
860 | dev_info(info->device, "NAND soft ECC\n"); | |
861 | break; | |
862 | case NAND_ECC_HW: | |
863 | dev_info(info->device, "NAND hardware ECC\n"); | |
864 | break; | |
865 | default: | |
866 | dev_info(info->device, "NAND ECC UNKNOWN\n"); | |
867 | break; | |
868 | } | |
9db41f9e MP |
869 | |
870 | /* If you use u-boot BBT creation code, specifying this flag will | |
871 | * let the kernel fish out the BBT from the NAND, and also skip the | |
872 | * full NAND scan that can take 1/2s or so. Little things... */ | |
a40f7341 | 873 | if (set->flash_bbt) { |
bb9ebd4e | 874 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 BN |
875 | chip->options |= NAND_SKIP_BBTSCAN; |
876 | } | |
1da177e4 LT |
877 | } |
878 | ||
3db72151 BD |
879 | /** |
880 | * s3c2410_nand_update_chip - post probe update | |
881 | * @info: The controller instance. | |
882 | * @nmtd: The driver version of the MTD instance. | |
71d54f38 | 883 | * |
af901ca1 | 884 | * This routine is called after the chip probe has successfully completed |
3db72151 BD |
885 | * and the relevant per-chip information updated. This call ensure that |
886 | * we update the internal state accordingly. | |
887 | * | |
888 | * The internal state is currently limited to the ECC state information. | |
889 | */ | |
71d54f38 BD |
890 | static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info, |
891 | struct s3c2410_nand_mtd *nmtd) | |
892 | { | |
893 | struct nand_chip *chip = &nmtd->chip; | |
894 | ||
451d3399 BD |
895 | dev_dbg(info->device, "chip %p => page shift %d\n", |
896 | chip, chip->page_shift); | |
71d54f38 | 897 | |
8c3e843d AG |
898 | if (chip->ecc.mode != NAND_ECC_HW) |
899 | return; | |
900 | ||
71d54f38 BD |
901 | /* change the behaviour depending on wether we are using |
902 | * the large or small page nand device */ | |
903 | ||
8c3e843d AG |
904 | if (chip->page_shift > 10) { |
905 | chip->ecc.size = 256; | |
906 | chip->ecc.bytes = 3; | |
907 | } else { | |
908 | chip->ecc.size = 512; | |
909 | chip->ecc.bytes = 3; | |
910 | chip->ecc.layout = &nand_hw_eccoob; | |
71d54f38 BD |
911 | } |
912 | } | |
913 | ||
ec0482e6 | 914 | /* s3c24xx_nand_probe |
1da177e4 LT |
915 | * |
916 | * called by device layer when it finds a device matching | |
917 | * one our driver can handled. This code checks to see if | |
918 | * it can allocate all necessary resources then calls the | |
919 | * nand layer to look for devices | |
920 | */ | |
ec0482e6 | 921 | static int s3c24xx_nand_probe(struct platform_device *pdev) |
1da177e4 | 922 | { |
3ae5eaec | 923 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
ec0482e6 | 924 | enum s3c_cpu_type cpu_type; |
1da177e4 LT |
925 | struct s3c2410_nand_info *info; |
926 | struct s3c2410_nand_mtd *nmtd; | |
927 | struct s3c2410_nand_set *sets; | |
928 | struct resource *res; | |
929 | int err = 0; | |
930 | int size; | |
931 | int nr_sets; | |
932 | int setno; | |
933 | ||
ec0482e6 BD |
934 | cpu_type = platform_get_device_id(pdev)->driver_data; |
935 | ||
3ae5eaec | 936 | pr_debug("s3c2410_nand_probe(%p)\n", pdev); |
1da177e4 | 937 | |
ecce2a6f | 938 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
1da177e4 | 939 | if (info == NULL) { |
3ae5eaec | 940 | dev_err(&pdev->dev, "no memory for flash info\n"); |
1da177e4 LT |
941 | err = -ENOMEM; |
942 | goto exit_error; | |
943 | } | |
944 | ||
3ae5eaec | 945 | platform_set_drvdata(pdev, info); |
1da177e4 LT |
946 | |
947 | spin_lock_init(&info->controller.lock); | |
a4f957f1 | 948 | init_waitqueue_head(&info->controller.wq); |
1da177e4 LT |
949 | |
950 | /* get the clock source and enable it */ | |
951 | ||
3ae5eaec | 952 | info->clk = clk_get(&pdev->dev, "nand"); |
1da177e4 | 953 | if (IS_ERR(info->clk)) { |
898eb71c | 954 | dev_err(&pdev->dev, "failed to get clock\n"); |
1da177e4 LT |
955 | err = -ENOENT; |
956 | goto exit_error; | |
957 | } | |
958 | ||
ac497c16 | 959 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
1da177e4 LT |
960 | |
961 | /* allocate and map the resource */ | |
962 | ||
a4f957f1 BD |
963 | /* currently we assume we have the one resource */ |
964 | res = pdev->resource; | |
fc161c4e | 965 | size = resource_size(res); |
1da177e4 LT |
966 | |
967 | info->area = request_mem_region(res->start, size, pdev->name); | |
968 | ||
969 | if (info->area == NULL) { | |
3ae5eaec | 970 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
1da177e4 LT |
971 | err = -ENOENT; |
972 | goto exit_error; | |
973 | } | |
974 | ||
3ae5eaec | 975 | info->device = &pdev->dev; |
a4f957f1 BD |
976 | info->platform = plat; |
977 | info->regs = ioremap(res->start, size); | |
2c06a082 | 978 | info->cpu_type = cpu_type; |
1da177e4 LT |
979 | |
980 | if (info->regs == NULL) { | |
3ae5eaec | 981 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
1da177e4 LT |
982 | err = -EIO; |
983 | goto exit_error; | |
61b03bd7 | 984 | } |
1da177e4 | 985 | |
3ae5eaec | 986 | dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); |
1da177e4 LT |
987 | |
988 | /* initialise the hardware */ | |
989 | ||
30821fee | 990 | err = s3c2410_nand_inithw(info); |
1da177e4 LT |
991 | if (err != 0) |
992 | goto exit_error; | |
993 | ||
994 | sets = (plat != NULL) ? plat->sets : NULL; | |
995 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; | |
996 | ||
997 | info->mtd_count = nr_sets; | |
998 | ||
999 | /* allocate our information */ | |
1000 | ||
1001 | size = nr_sets * sizeof(*info->mtds); | |
ecce2a6f | 1002 | info->mtds = kzalloc(size, GFP_KERNEL); |
1da177e4 | 1003 | if (info->mtds == NULL) { |
3ae5eaec | 1004 | dev_err(&pdev->dev, "failed to allocate mtd storage\n"); |
1da177e4 LT |
1005 | err = -ENOMEM; |
1006 | goto exit_error; | |
1007 | } | |
1008 | ||
1da177e4 LT |
1009 | /* initialise all possible chips */ |
1010 | ||
1011 | nmtd = info->mtds; | |
1012 | ||
1013 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { | |
e0c7d767 | 1014 | pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info); |
61b03bd7 | 1015 | |
1da177e4 LT |
1016 | s3c2410_nand_init_chip(info, nmtd, sets); |
1017 | ||
71d54f38 | 1018 | nmtd->scan_res = nand_scan_ident(&nmtd->mtd, |
5e81e88a DW |
1019 | (sets) ? sets->nr_chips : 1, |
1020 | NULL); | |
1da177e4 LT |
1021 | |
1022 | if (nmtd->scan_res == 0) { | |
71d54f38 BD |
1023 | s3c2410_nand_update_chip(info, nmtd); |
1024 | nand_scan_tail(&nmtd->mtd); | |
1da177e4 LT |
1025 | s3c2410_nand_add_partition(info, nmtd, sets); |
1026 | } | |
1027 | ||
1028 | if (sets != NULL) | |
1029 | sets++; | |
1030 | } | |
61b03bd7 | 1031 | |
30821fee BD |
1032 | err = s3c2410_nand_cpufreq_register(info); |
1033 | if (err < 0) { | |
1034 | dev_err(&pdev->dev, "failed to init cpufreq support\n"); | |
1035 | goto exit_error; | |
1036 | } | |
1037 | ||
ac497c16 | 1038 | if (allow_clk_suspend(info)) { |
d1fef3c5 | 1039 | dev_info(&pdev->dev, "clock idle support enabled\n"); |
ac497c16 | 1040 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1041 | } |
1042 | ||
1da177e4 LT |
1043 | pr_debug("initialised ok\n"); |
1044 | return 0; | |
1045 | ||
1046 | exit_error: | |
ec0482e6 | 1047 | s3c24xx_nand_remove(pdev); |
1da177e4 LT |
1048 | |
1049 | if (err == 0) | |
1050 | err = -EINVAL; | |
1051 | return err; | |
1052 | } | |
1053 | ||
d1fef3c5 BD |
1054 | /* PM Support */ |
1055 | #ifdef CONFIG_PM | |
1056 | ||
1057 | static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) | |
1058 | { | |
1059 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
1060 | ||
1061 | if (info) { | |
09160832 | 1062 | info->save_sel = readl(info->sel_reg); |
03680b1e BD |
1063 | |
1064 | /* For the moment, we must ensure nFCE is high during | |
1065 | * the time we are suspended. This really should be | |
1066 | * handled by suspending the MTDs we are using, but | |
1067 | * that is currently not the case. */ | |
1068 | ||
09160832 | 1069 | writel(info->save_sel | info->sel_bit, info->sel_reg); |
03680b1e | 1070 | |
ac497c16 | 1071 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
d1fef3c5 BD |
1072 | } |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
1077 | static int s3c24xx_nand_resume(struct platform_device *dev) | |
1078 | { | |
1079 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
09160832 | 1080 | unsigned long sel; |
d1fef3c5 BD |
1081 | |
1082 | if (info) { | |
ac497c16 | 1083 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
30821fee | 1084 | s3c2410_nand_inithw(info); |
d1fef3c5 | 1085 | |
03680b1e BD |
1086 | /* Restore the state of the nFCE line. */ |
1087 | ||
09160832 BD |
1088 | sel = readl(info->sel_reg); |
1089 | sel &= ~info->sel_bit; | |
1090 | sel |= info->save_sel & info->sel_bit; | |
1091 | writel(sel, info->sel_reg); | |
03680b1e | 1092 | |
ac497c16 | 1093 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1094 | } |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | #else | |
1100 | #define s3c24xx_nand_suspend NULL | |
1101 | #define s3c24xx_nand_resume NULL | |
1102 | #endif | |
1103 | ||
a4f957f1 BD |
1104 | /* driver device registration */ |
1105 | ||
ec0482e6 BD |
1106 | static struct platform_device_id s3c24xx_driver_ids[] = { |
1107 | { | |
1108 | .name = "s3c2410-nand", | |
1109 | .driver_data = TYPE_S3C2410, | |
1110 | }, { | |
1111 | .name = "s3c2440-nand", | |
1112 | .driver_data = TYPE_S3C2440, | |
1113 | }, { | |
1114 | .name = "s3c2412-nand", | |
1115 | .driver_data = TYPE_S3C2412, | |
9dbc0902 PK |
1116 | }, { |
1117 | .name = "s3c6400-nand", | |
1118 | .driver_data = TYPE_S3C2412, /* compatible with 2412 */ | |
3ae5eaec | 1119 | }, |
ec0482e6 | 1120 | { } |
1da177e4 LT |
1121 | }; |
1122 | ||
ec0482e6 | 1123 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
a4f957f1 | 1124 | |
ec0482e6 BD |
1125 | static struct platform_driver s3c24xx_nand_driver = { |
1126 | .probe = s3c24xx_nand_probe, | |
1127 | .remove = s3c24xx_nand_remove, | |
2c06a082 BD |
1128 | .suspend = s3c24xx_nand_suspend, |
1129 | .resume = s3c24xx_nand_resume, | |
ec0482e6 | 1130 | .id_table = s3c24xx_driver_ids, |
2c06a082 | 1131 | .driver = { |
ec0482e6 | 1132 | .name = "s3c24xx-nand", |
2c06a082 BD |
1133 | .owner = THIS_MODULE, |
1134 | }, | |
1135 | }; | |
1136 | ||
1da177e4 LT |
1137 | static int __init s3c2410_nand_init(void) |
1138 | { | |
a4f957f1 BD |
1139 | printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n"); |
1140 | ||
ec0482e6 | 1141 | return platform_driver_register(&s3c24xx_nand_driver); |
1da177e4 LT |
1142 | } |
1143 | ||
1144 | static void __exit s3c2410_nand_exit(void) | |
1145 | { | |
ec0482e6 | 1146 | platform_driver_unregister(&s3c24xx_nand_driver); |
1da177e4 LT |
1147 | } |
1148 | ||
1149 | module_init(s3c2410_nand_init); | |
1150 | module_exit(s3c2410_nand_exit); | |
1151 | ||
1152 | MODULE_LICENSE("GPL"); | |
1153 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
a4f957f1 | 1154 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |