Commit | Line | Data |
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1da177e4 LT |
1 | /* linux/drivers/mtd/nand/s3c2410.c |
2 | * | |
7e74a507 BD |
3 | * Copyright © 2004-2008 Simtec Electronics |
4 | * http://armlinux.simtec.co.uk/ | |
fdf2fd52 | 5 | * Ben Dooks <ben@simtec.co.uk> |
1da177e4 | 6 | * |
7e74a507 | 7 | * Samsung S3C2410/S3C2440/S3C2412 NAND driver |
1da177e4 | 8 | * |
1da177e4 LT |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
92aeb5d2 SK |
24 | #define pr_fmt(fmt) "nand-s3c2410: " fmt |
25 | ||
1da177e4 LT |
26 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG |
27 | #define DEBUG | |
28 | #endif | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/types.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/string.h> | |
d2a89be8 | 35 | #include <linux/io.h> |
1da177e4 | 36 | #include <linux/ioport.h> |
d052d1be | 37 | #include <linux/platform_device.h> |
1da177e4 LT |
38 | #include <linux/delay.h> |
39 | #include <linux/err.h> | |
4e57b681 | 40 | #include <linux/slab.h> |
f8ce2547 | 41 | #include <linux/clk.h> |
30821fee | 42 | #include <linux/cpufreq.h> |
1da177e4 LT |
43 | |
44 | #include <linux/mtd/mtd.h> | |
45 | #include <linux/mtd/nand.h> | |
46 | #include <linux/mtd/nand_ecc.h> | |
47 | #include <linux/mtd/partitions.h> | |
48 | ||
7926b5a3 BD |
49 | #include <plat/regs-nand.h> |
50 | #include <plat/nand.h> | |
1da177e4 | 51 | |
1da177e4 LT |
52 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
53 | static int hardware_ecc = 1; | |
54 | #else | |
55 | static int hardware_ecc = 0; | |
56 | #endif | |
57 | ||
d1fef3c5 | 58 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP |
ac497c16 | 59 | static const int clock_stop = 1; |
d1fef3c5 BD |
60 | #else |
61 | static const int clock_stop = 0; | |
62 | #endif | |
63 | ||
64 | ||
1da177e4 LT |
65 | /* new oob placement block for use with hardware ecc generation |
66 | */ | |
67 | ||
5bd34c09 | 68 | static struct nand_ecclayout nand_hw_eccoob = { |
e0c7d767 DW |
69 | .eccbytes = 3, |
70 | .eccpos = {0, 1, 2}, | |
71 | .oobfree = {{8, 8}} | |
1da177e4 LT |
72 | }; |
73 | ||
74 | /* controller and mtd information */ | |
75 | ||
76 | struct s3c2410_nand_info; | |
77 | ||
3db72151 BD |
78 | /** |
79 | * struct s3c2410_nand_mtd - driver MTD structure | |
80 | * @mtd: The MTD instance to pass to the MTD layer. | |
81 | * @chip: The NAND chip information. | |
82 | * @set: The platform information supplied for this set of NAND chips. | |
83 | * @info: Link back to the hardware information. | |
84 | * @scan_res: The result from calling nand_scan_ident(). | |
85 | */ | |
1da177e4 LT |
86 | struct s3c2410_nand_mtd { |
87 | struct mtd_info mtd; | |
88 | struct nand_chip chip; | |
89 | struct s3c2410_nand_set *set; | |
90 | struct s3c2410_nand_info *info; | |
91 | int scan_res; | |
92 | }; | |
93 | ||
2c06a082 BD |
94 | enum s3c_cpu_type { |
95 | TYPE_S3C2410, | |
96 | TYPE_S3C2412, | |
97 | TYPE_S3C2440, | |
98 | }; | |
99 | ||
ac497c16 JP |
100 | enum s3c_nand_clk_state { |
101 | CLOCK_DISABLE = 0, | |
102 | CLOCK_ENABLE, | |
103 | CLOCK_SUSPEND, | |
104 | }; | |
105 | ||
1da177e4 LT |
106 | /* overview of the s3c2410 nand state */ |
107 | ||
3db72151 BD |
108 | /** |
109 | * struct s3c2410_nand_info - NAND controller state. | |
110 | * @mtds: An array of MTD instances on this controoler. | |
111 | * @platform: The platform data for this board. | |
112 | * @device: The platform device we bound to. | |
113 | * @area: The IO area resource that came from request_mem_region(). | |
114 | * @clk: The clock resource for this controller. | |
115 | * @regs: The area mapped for the hardware registers described by @area. | |
116 | * @sel_reg: Pointer to the register controlling the NAND selection. | |
117 | * @sel_bit: The bit in @sel_reg to select the NAND chip. | |
118 | * @mtd_count: The number of MTDs created from this controller. | |
119 | * @save_sel: The contents of @sel_reg to be saved over suspend. | |
120 | * @clk_rate: The clock rate from @clk. | |
ac497c16 | 121 | * @clk_state: The current clock state. |
3db72151 BD |
122 | * @cpu_type: The exact type of this controller. |
123 | */ | |
1da177e4 LT |
124 | struct s3c2410_nand_info { |
125 | /* mtd info */ | |
126 | struct nand_hw_control controller; | |
127 | struct s3c2410_nand_mtd *mtds; | |
128 | struct s3c2410_platform_nand *platform; | |
129 | ||
130 | /* device info */ | |
131 | struct device *device; | |
132 | struct resource *area; | |
133 | struct clk *clk; | |
fdf2fd52 | 134 | void __iomem *regs; |
2c06a082 BD |
135 | void __iomem *sel_reg; |
136 | int sel_bit; | |
1da177e4 | 137 | int mtd_count; |
09160832 | 138 | unsigned long save_sel; |
30821fee | 139 | unsigned long clk_rate; |
ac497c16 | 140 | enum s3c_nand_clk_state clk_state; |
03680b1e | 141 | |
2c06a082 | 142 | enum s3c_cpu_type cpu_type; |
30821fee BD |
143 | |
144 | #ifdef CONFIG_CPU_FREQ | |
145 | struct notifier_block freq_transition; | |
146 | #endif | |
1da177e4 LT |
147 | }; |
148 | ||
149 | /* conversion functions */ | |
150 | ||
151 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) | |
152 | { | |
153 | return container_of(mtd, struct s3c2410_nand_mtd, mtd); | |
154 | } | |
155 | ||
156 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) | |
157 | { | |
158 | return s3c2410_nand_mtd_toours(mtd)->info; | |
159 | } | |
160 | ||
3ae5eaec | 161 | static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) |
1da177e4 | 162 | { |
3ae5eaec | 163 | return platform_get_drvdata(dev); |
1da177e4 LT |
164 | } |
165 | ||
3ae5eaec | 166 | static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) |
1da177e4 | 167 | { |
3ae5eaec | 168 | return dev->dev.platform_data; |
1da177e4 LT |
169 | } |
170 | ||
ac497c16 | 171 | static inline int allow_clk_suspend(struct s3c2410_nand_info *info) |
d1fef3c5 BD |
172 | { |
173 | return clock_stop; | |
174 | } | |
175 | ||
ac497c16 JP |
176 | /** |
177 | * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. | |
178 | * @info: The controller instance. | |
179 | * @new_state: State to which clock should be set. | |
180 | */ | |
181 | static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, | |
182 | enum s3c_nand_clk_state new_state) | |
183 | { | |
184 | if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) | |
185 | return; | |
186 | ||
187 | if (info->clk_state == CLOCK_ENABLE) { | |
188 | if (new_state != CLOCK_ENABLE) | |
189 | clk_disable(info->clk); | |
190 | } else { | |
191 | if (new_state == CLOCK_ENABLE) | |
192 | clk_enable(info->clk); | |
193 | } | |
194 | ||
195 | info->clk_state = new_state; | |
196 | } | |
197 | ||
1da177e4 LT |
198 | /* timing calculations */ |
199 | ||
cfd320fb | 200 | #define NS_IN_KHZ 1000000 |
1da177e4 | 201 | |
3db72151 BD |
202 | /** |
203 | * s3c_nand_calc_rate - calculate timing data. | |
204 | * @wanted: The cycle time in nanoseconds. | |
205 | * @clk: The clock rate in kHz. | |
206 | * @max: The maximum divider value. | |
207 | * | |
208 | * Calculate the timing value from the given parameters. | |
209 | */ | |
2c06a082 | 210 | static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) |
1da177e4 LT |
211 | { |
212 | int result; | |
213 | ||
947391cf | 214 | result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); |
1da177e4 LT |
215 | |
216 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); | |
217 | ||
218 | if (result > max) { | |
92aeb5d2 SK |
219 | pr_err("%d ns is too big for current clock rate %ld\n", |
220 | wanted, clk); | |
1da177e4 LT |
221 | return -1; |
222 | } | |
223 | ||
224 | if (result < 1) | |
225 | result = 1; | |
226 | ||
227 | return result; | |
228 | } | |
229 | ||
cfd320fb | 230 | #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
1da177e4 LT |
231 | |
232 | /* controller setup */ | |
233 | ||
3db72151 BD |
234 | /** |
235 | * s3c2410_nand_setrate - setup controller timing information. | |
236 | * @info: The controller instance. | |
237 | * | |
238 | * Given the information supplied by the platform, calculate and set | |
239 | * the necessary timing registers in the hardware to generate the | |
240 | * necessary timing cycles to the hardware. | |
241 | */ | |
30821fee | 242 | static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) |
1da177e4 | 243 | { |
30821fee | 244 | struct s3c2410_platform_nand *plat = info->platform; |
2c06a082 | 245 | int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; |
cfd320fb | 246 | int tacls, twrph0, twrph1; |
30821fee | 247 | unsigned long clkrate = clk_get_rate(info->clk); |
2612e523 | 248 | unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); |
30821fee | 249 | unsigned long flags; |
1da177e4 LT |
250 | |
251 | /* calculate the timing information for the controller */ | |
252 | ||
30821fee | 253 | info->clk_rate = clkrate; |
cfd320fb BD |
254 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
255 | ||
1da177e4 | 256 | if (plat != NULL) { |
2c06a082 BD |
257 | tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); |
258 | twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); | |
259 | twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); | |
1da177e4 LT |
260 | } else { |
261 | /* default timings */ | |
2c06a082 | 262 | tacls = tacls_max; |
1da177e4 LT |
263 | twrph0 = 8; |
264 | twrph1 = 8; | |
265 | } | |
61b03bd7 | 266 | |
1da177e4 | 267 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
99974c62 | 268 | dev_err(info->device, "cannot get suitable timings\n"); |
1da177e4 LT |
269 | return -EINVAL; |
270 | } | |
271 | ||
99974c62 | 272 | dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
e0c7d767 | 273 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate)); |
1da177e4 | 274 | |
30821fee BD |
275 | switch (info->cpu_type) { |
276 | case TYPE_S3C2410: | |
277 | mask = (S3C2410_NFCONF_TACLS(3) | | |
278 | S3C2410_NFCONF_TWRPH0(7) | | |
279 | S3C2410_NFCONF_TWRPH1(7)); | |
280 | set = S3C2410_NFCONF_EN; | |
281 | set |= S3C2410_NFCONF_TACLS(tacls - 1); | |
282 | set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); | |
283 | set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); | |
284 | break; | |
285 | ||
286 | case TYPE_S3C2440: | |
287 | case TYPE_S3C2412: | |
a755a385 PK |
288 | mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | |
289 | S3C2440_NFCONF_TWRPH0(7) | | |
290 | S3C2440_NFCONF_TWRPH1(7)); | |
30821fee BD |
291 | |
292 | set = S3C2440_NFCONF_TACLS(tacls - 1); | |
293 | set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); | |
294 | set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); | |
295 | break; | |
296 | ||
297 | default: | |
30821fee BD |
298 | BUG(); |
299 | } | |
300 | ||
30821fee BD |
301 | local_irq_save(flags); |
302 | ||
303 | cfg = readl(info->regs + S3C2410_NFCONF); | |
304 | cfg &= ~mask; | |
305 | cfg |= set; | |
306 | writel(cfg, info->regs + S3C2410_NFCONF); | |
307 | ||
308 | local_irq_restore(flags); | |
309 | ||
ae7304e5 AG |
310 | dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); |
311 | ||
30821fee BD |
312 | return 0; |
313 | } | |
314 | ||
3db72151 BD |
315 | /** |
316 | * s3c2410_nand_inithw - basic hardware initialisation | |
317 | * @info: The hardware state. | |
318 | * | |
319 | * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() | |
320 | * to setup the hardware access speeds and set the controller to be enabled. | |
321 | */ | |
30821fee BD |
322 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) |
323 | { | |
324 | int ret; | |
325 | ||
326 | ret = s3c2410_nand_setrate(info); | |
327 | if (ret < 0) | |
328 | return ret; | |
329 | ||
2c06a082 BD |
330 | switch (info->cpu_type) { |
331 | case TYPE_S3C2410: | |
30821fee | 332 | default: |
2c06a082 BD |
333 | break; |
334 | ||
335 | case TYPE_S3C2440: | |
336 | case TYPE_S3C2412: | |
d1fef3c5 BD |
337 | /* enable the controller and de-assert nFCE */ |
338 | ||
2c06a082 | 339 | writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); |
a4f957f1 | 340 | } |
1da177e4 | 341 | |
1da177e4 LT |
342 | return 0; |
343 | } | |
344 | ||
3db72151 BD |
345 | /** |
346 | * s3c2410_nand_select_chip - select the given nand chip | |
347 | * @mtd: The MTD instance for this chip. | |
348 | * @chip: The chip number. | |
349 | * | |
350 | * This is called by the MTD layer to either select a given chip for the | |
351 | * @mtd instance, or to indicate that the access has finished and the | |
352 | * chip can be de-selected. | |
353 | * | |
354 | * The routine ensures that the nFCE line is correctly setup, and any | |
355 | * platform specific selection code is called to route nFCE to the specific | |
356 | * chip. | |
357 | */ | |
1da177e4 LT |
358 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) |
359 | { | |
360 | struct s3c2410_nand_info *info; | |
61b03bd7 | 361 | struct s3c2410_nand_mtd *nmtd; |
1da177e4 LT |
362 | struct nand_chip *this = mtd->priv; |
363 | unsigned long cur; | |
364 | ||
365 | nmtd = this->priv; | |
366 | info = nmtd->info; | |
367 | ||
ac497c16 JP |
368 | if (chip != -1) |
369 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); | |
d1fef3c5 | 370 | |
2c06a082 | 371 | cur = readl(info->sel_reg); |
1da177e4 LT |
372 | |
373 | if (chip == -1) { | |
2c06a082 | 374 | cur |= info->sel_bit; |
1da177e4 | 375 | } else { |
fb8d82a8 | 376 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
99974c62 | 377 | dev_err(info->device, "invalid chip %d\n", chip); |
1da177e4 LT |
378 | return; |
379 | } | |
380 | ||
381 | if (info->platform != NULL) { | |
382 | if (info->platform->select_chip != NULL) | |
e0c7d767 | 383 | (info->platform->select_chip) (nmtd->set, chip); |
1da177e4 LT |
384 | } |
385 | ||
2c06a082 | 386 | cur &= ~info->sel_bit; |
1da177e4 LT |
387 | } |
388 | ||
2c06a082 | 389 | writel(cur, info->sel_reg); |
d1fef3c5 | 390 | |
ac497c16 JP |
391 | if (chip == -1) |
392 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); | |
1da177e4 LT |
393 | } |
394 | ||
ad3b5fb7 | 395 | /* s3c2410_nand_hwcontrol |
a4f957f1 | 396 | * |
ad3b5fb7 | 397 | * Issue command and address cycles to the chip |
a4f957f1 | 398 | */ |
1da177e4 | 399 | |
7abd3ef9 | 400 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
f9068876 | 401 | unsigned int ctrl) |
1da177e4 LT |
402 | { |
403 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
c9ac5977 | 404 | |
7abd3ef9 TG |
405 | if (cmd == NAND_CMD_NONE) |
406 | return; | |
407 | ||
f9068876 | 408 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
409 | writeb(cmd, info->regs + S3C2410_NFCMD); |
410 | else | |
411 | writeb(cmd, info->regs + S3C2410_NFADDR); | |
a4f957f1 BD |
412 | } |
413 | ||
414 | /* command and control functions */ | |
415 | ||
f9068876 DW |
416 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
417 | unsigned int ctrl) | |
a4f957f1 BD |
418 | { |
419 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 | 420 | |
7abd3ef9 TG |
421 | if (cmd == NAND_CMD_NONE) |
422 | return; | |
423 | ||
f9068876 | 424 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
425 | writeb(cmd, info->regs + S3C2440_NFCMD); |
426 | else | |
427 | writeb(cmd, info->regs + S3C2440_NFADDR); | |
1da177e4 LT |
428 | } |
429 | ||
1da177e4 LT |
430 | /* s3c2410_nand_devready() |
431 | * | |
432 | * returns 0 if the nand is busy, 1 if it is ready | |
433 | */ | |
434 | ||
435 | static int s3c2410_nand_devready(struct mtd_info *mtd) | |
436 | { | |
437 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 LT |
438 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
439 | } | |
440 | ||
2c06a082 BD |
441 | static int s3c2440_nand_devready(struct mtd_info *mtd) |
442 | { | |
443 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
444 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; | |
445 | } | |
446 | ||
447 | static int s3c2412_nand_devready(struct mtd_info *mtd) | |
448 | { | |
449 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
450 | return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; | |
451 | } | |
452 | ||
1da177e4 LT |
453 | /* ECC handling functions */ |
454 | ||
2c06a082 BD |
455 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
456 | u_char *read_ecc, u_char *calc_ecc) | |
1da177e4 | 457 | { |
a2593247 BD |
458 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
459 | unsigned int diff0, diff1, diff2; | |
460 | unsigned int bit, byte; | |
461 | ||
462 | pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); | |
463 | ||
464 | diff0 = read_ecc[0] ^ calc_ecc[0]; | |
465 | diff1 = read_ecc[1] ^ calc_ecc[1]; | |
466 | diff2 = read_ecc[2] ^ calc_ecc[2]; | |
467 | ||
468 | pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n", | |
469 | __func__, | |
470 | read_ecc[0], read_ecc[1], read_ecc[2], | |
471 | calc_ecc[0], calc_ecc[1], calc_ecc[2], | |
472 | diff0, diff1, diff2); | |
473 | ||
474 | if (diff0 == 0 && diff1 == 0 && diff2 == 0) | |
475 | return 0; /* ECC is ok */ | |
476 | ||
c45c6c68 BD |
477 | /* sometimes people do not think about using the ECC, so check |
478 | * to see if we have an 0xff,0xff,0xff read ECC and then ignore | |
479 | * the error, on the assumption that this is an un-eccd page. | |
480 | */ | |
481 | if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff | |
482 | && info->platform->ignore_unset_ecc) | |
483 | return 0; | |
484 | ||
a2593247 BD |
485 | /* Can we correct this ECC (ie, one row and column change). |
486 | * Note, this is similar to the 256 error code on smartmedia */ | |
487 | ||
488 | if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && | |
489 | ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && | |
490 | ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { | |
491 | /* calculate the bit position of the error */ | |
492 | ||
d0bf3793 MR |
493 | bit = ((diff2 >> 3) & 1) | |
494 | ((diff2 >> 4) & 2) | | |
495 | ((diff2 >> 5) & 4); | |
1da177e4 | 496 | |
a2593247 | 497 | /* calculate the byte position of the error */ |
1da177e4 | 498 | |
d0bf3793 MR |
499 | byte = ((diff2 << 7) & 0x100) | |
500 | ((diff1 << 0) & 0x80) | | |
501 | ((diff1 << 1) & 0x40) | | |
502 | ((diff1 << 2) & 0x20) | | |
503 | ((diff1 << 3) & 0x10) | | |
504 | ((diff0 >> 4) & 0x08) | | |
505 | ((diff0 >> 3) & 0x04) | | |
506 | ((diff0 >> 2) & 0x02) | | |
507 | ((diff0 >> 1) & 0x01); | |
a2593247 BD |
508 | |
509 | dev_dbg(info->device, "correcting error bit %d, byte %d\n", | |
510 | bit, byte); | |
511 | ||
512 | dat[byte] ^= (1 << bit); | |
513 | return 1; | |
514 | } | |
515 | ||
516 | /* if there is only one bit difference in the ECC, then | |
517 | * one of only a row or column parity has changed, which | |
518 | * means the error is most probably in the ECC itself */ | |
519 | ||
520 | diff0 |= (diff1 << 8); | |
521 | diff0 |= (diff2 << 16); | |
522 | ||
523 | if ((diff0 & ~(1<<fls(diff0))) == 0) | |
524 | return 1; | |
525 | ||
4fac9f69 | 526 | return -1; |
1da177e4 LT |
527 | } |
528 | ||
a4f957f1 BD |
529 | /* ECC functions |
530 | * | |
531 | * These allow the s3c2410 and s3c2440 to use the controller's ECC | |
532 | * generator block to ECC the data as it passes through] | |
533 | */ | |
534 | ||
1da177e4 LT |
535 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
536 | { | |
537 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
538 | unsigned long ctrl; | |
539 | ||
540 | ctrl = readl(info->regs + S3C2410_NFCONF); | |
541 | ctrl |= S3C2410_NFCONF_INITECC; | |
542 | writel(ctrl, info->regs + S3C2410_NFCONF); | |
543 | } | |
544 | ||
4f659923 MC |
545 | static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
546 | { | |
547 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
548 | unsigned long ctrl; | |
549 | ||
550 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
551 | writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT); | |
552 | } | |
553 | ||
a4f957f1 BD |
554 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
555 | { | |
556 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
557 | unsigned long ctrl; | |
558 | ||
559 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
560 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); | |
561 | } | |
562 | ||
e0c7d767 | 563 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
1da177e4 LT |
564 | { |
565 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
566 | ||
567 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); | |
568 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); | |
569 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); | |
570 | ||
a2593247 BD |
571 | pr_debug("%s: returning ecc %02x%02x%02x\n", __func__, |
572 | ecc_code[0], ecc_code[1], ecc_code[2]); | |
1da177e4 LT |
573 | |
574 | return 0; | |
575 | } | |
576 | ||
4f659923 MC |
577 | static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
578 | { | |
579 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
580 | unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); | |
581 | ||
582 | ecc_code[0] = ecc; | |
583 | ecc_code[1] = ecc >> 8; | |
584 | ecc_code[2] = ecc >> 16; | |
585 | ||
586 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
e0c7d767 | 591 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
a4f957f1 BD |
592 | { |
593 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
594 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); | |
595 | ||
596 | ecc_code[0] = ecc; | |
597 | ecc_code[1] = ecc >> 8; | |
598 | ecc_code[2] = ecc >> 16; | |
599 | ||
71d54f38 | 600 | pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); |
a4f957f1 BD |
601 | |
602 | return 0; | |
603 | } | |
604 | ||
a4f957f1 BD |
605 | /* over-ride the standard functions for a little more speed. We can |
606 | * use read/write block to move the data buffers to/from the controller | |
607 | */ | |
1da177e4 LT |
608 | |
609 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
610 | { | |
611 | struct nand_chip *this = mtd->priv; | |
612 | readsb(this->IO_ADDR_R, buf, len); | |
613 | } | |
614 | ||
b773bb2e MR |
615 | static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
616 | { | |
617 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
618 | |
619 | readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
620 | ||
621 | /* cleanup if we've got less than a word to do */ | |
622 | if (len & 3) { | |
623 | buf += len & ~3; | |
624 | ||
625 | for (; len & 3; len--) | |
626 | *buf++ = readb(info->regs + S3C2440_NFDATA); | |
627 | } | |
b773bb2e MR |
628 | } |
629 | ||
e0c7d767 | 630 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
1da177e4 LT |
631 | { |
632 | struct nand_chip *this = mtd->priv; | |
633 | writesb(this->IO_ADDR_W, buf, len); | |
634 | } | |
635 | ||
b773bb2e MR |
636 | static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
637 | { | |
638 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
639 | |
640 | writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
641 | ||
642 | /* cleanup any fractional write */ | |
643 | if (len & 3) { | |
644 | buf += len & ~3; | |
645 | ||
646 | for (; len & 3; len--, buf++) | |
647 | writeb(*buf, info->regs + S3C2440_NFDATA); | |
648 | } | |
b773bb2e MR |
649 | } |
650 | ||
30821fee BD |
651 | /* cpufreq driver support */ |
652 | ||
653 | #ifdef CONFIG_CPU_FREQ | |
654 | ||
655 | static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, | |
656 | unsigned long val, void *data) | |
657 | { | |
658 | struct s3c2410_nand_info *info; | |
659 | unsigned long newclk; | |
660 | ||
661 | info = container_of(nb, struct s3c2410_nand_info, freq_transition); | |
662 | newclk = clk_get_rate(info->clk); | |
663 | ||
664 | if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || | |
665 | (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { | |
666 | s3c2410_nand_setrate(info); | |
667 | } | |
668 | ||
669 | return 0; | |
670 | } | |
671 | ||
672 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
673 | { | |
674 | info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; | |
675 | ||
676 | return cpufreq_register_notifier(&info->freq_transition, | |
677 | CPUFREQ_TRANSITION_NOTIFIER); | |
678 | } | |
679 | ||
680 | static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
681 | { | |
682 | cpufreq_unregister_notifier(&info->freq_transition, | |
683 | CPUFREQ_TRANSITION_NOTIFIER); | |
684 | } | |
685 | ||
686 | #else | |
687 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
688 | { | |
689 | return 0; | |
690 | } | |
691 | ||
692 | static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
693 | { | |
694 | } | |
695 | #endif | |
696 | ||
1da177e4 LT |
697 | /* device management functions */ |
698 | ||
ec0482e6 | 699 | static int s3c24xx_nand_remove(struct platform_device *pdev) |
1da177e4 | 700 | { |
3ae5eaec | 701 | struct s3c2410_nand_info *info = to_nand_info(pdev); |
1da177e4 | 702 | |
3ae5eaec | 703 | platform_set_drvdata(pdev, NULL); |
1da177e4 | 704 | |
61b03bd7 | 705 | if (info == NULL) |
1da177e4 LT |
706 | return 0; |
707 | ||
30821fee BD |
708 | s3c2410_nand_cpufreq_deregister(info); |
709 | ||
710 | /* Release all our mtds and their partitions, then go through | |
711 | * freeing the resources used | |
1da177e4 | 712 | */ |
61b03bd7 | 713 | |
1da177e4 LT |
714 | if (info->mtds != NULL) { |
715 | struct s3c2410_nand_mtd *ptr = info->mtds; | |
716 | int mtdno; | |
717 | ||
718 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { | |
719 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); | |
720 | nand_release(&ptr->mtd); | |
721 | } | |
722 | ||
723 | kfree(info->mtds); | |
724 | } | |
725 | ||
726 | /* free the common resources */ | |
727 | ||
4aa10626 | 728 | if (!IS_ERR(info->clk)) { |
ac497c16 | 729 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
1da177e4 LT |
730 | clk_put(info->clk); |
731 | } | |
732 | ||
733 | if (info->regs != NULL) { | |
734 | iounmap(info->regs); | |
735 | info->regs = NULL; | |
736 | } | |
737 | ||
738 | if (info->area != NULL) { | |
739 | release_resource(info->area); | |
740 | kfree(info->area); | |
741 | info->area = NULL; | |
742 | } | |
743 | ||
744 | kfree(info); | |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
1da177e4 LT |
749 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, |
750 | struct s3c2410_nand_mtd *mtd, | |
751 | struct s3c2410_nand_set *set) | |
752 | { | |
599501a7 DES |
753 | if (set) |
754 | mtd->mtd.name = set->name; | |
ed27f028 | 755 | |
42d7fbe2 AB |
756 | return mtd_device_parse_register(&mtd->mtd, NULL, NULL, |
757 | set->partitions, set->nr_partitions); | |
1da177e4 | 758 | } |
1da177e4 | 759 | |
3db72151 BD |
760 | /** |
761 | * s3c2410_nand_init_chip - initialise a single instance of an chip | |
762 | * @info: The base NAND controller the chip is on. | |
763 | * @nmtd: The new controller MTD instance to fill in. | |
764 | * @set: The information passed from the board specific platform data. | |
1da177e4 | 765 | * |
3db72151 BD |
766 | * Initialise the given @nmtd from the information in @info and @set. This |
767 | * readies the structure for use with the MTD layer functions by ensuring | |
768 | * all pointers are setup and the necessary control routines selected. | |
769 | */ | |
1da177e4 LT |
770 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, |
771 | struct s3c2410_nand_mtd *nmtd, | |
772 | struct s3c2410_nand_set *set) | |
773 | { | |
774 | struct nand_chip *chip = &nmtd->chip; | |
2c06a082 | 775 | void __iomem *regs = info->regs; |
1da177e4 | 776 | |
1da177e4 LT |
777 | chip->write_buf = s3c2410_nand_write_buf; |
778 | chip->read_buf = s3c2410_nand_read_buf; | |
779 | chip->select_chip = s3c2410_nand_select_chip; | |
780 | chip->chip_delay = 50; | |
781 | chip->priv = nmtd; | |
74218fed | 782 | chip->options = set->options; |
1da177e4 LT |
783 | chip->controller = &info->controller; |
784 | ||
2c06a082 BD |
785 | switch (info->cpu_type) { |
786 | case TYPE_S3C2410: | |
787 | chip->IO_ADDR_W = regs + S3C2410_NFDATA; | |
788 | info->sel_reg = regs + S3C2410_NFCONF; | |
789 | info->sel_bit = S3C2410_NFCONF_nFCE; | |
790 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; | |
791 | chip->dev_ready = s3c2410_nand_devready; | |
792 | break; | |
793 | ||
794 | case TYPE_S3C2440: | |
795 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
796 | info->sel_reg = regs + S3C2440_NFCONT; | |
797 | info->sel_bit = S3C2440_NFCONT_nFCE; | |
798 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
799 | chip->dev_ready = s3c2440_nand_devready; | |
b773bb2e MR |
800 | chip->read_buf = s3c2440_nand_read_buf; |
801 | chip->write_buf = s3c2440_nand_write_buf; | |
2c06a082 BD |
802 | break; |
803 | ||
804 | case TYPE_S3C2412: | |
805 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
806 | info->sel_reg = regs + S3C2440_NFCONT; | |
807 | info->sel_bit = S3C2412_NFCONT_nFCE0; | |
808 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
809 | chip->dev_ready = s3c2412_nand_devready; | |
810 | ||
811 | if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) | |
812 | dev_info(info->device, "System booted from NAND\n"); | |
813 | ||
814 | break; | |
815 | } | |
816 | ||
817 | chip->IO_ADDR_R = chip->IO_ADDR_W; | |
a4f957f1 | 818 | |
1da177e4 LT |
819 | nmtd->info = info; |
820 | nmtd->mtd.priv = chip; | |
552d9205 | 821 | nmtd->mtd.owner = THIS_MODULE; |
1da177e4 LT |
822 | nmtd->set = set; |
823 | ||
824 | if (hardware_ecc) { | |
6dfc6d25 | 825 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
2c06a082 | 826 | chip->ecc.correct = s3c2410_nand_correct_data; |
6dfc6d25 | 827 | chip->ecc.mode = NAND_ECC_HW; |
6a918bad | 828 | chip->ecc.strength = 1; |
a4f957f1 | 829 | |
2c06a082 BD |
830 | switch (info->cpu_type) { |
831 | case TYPE_S3C2410: | |
832 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; | |
833 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | |
834 | break; | |
835 | ||
836 | case TYPE_S3C2412: | |
4f659923 MC |
837 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; |
838 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; | |
839 | break; | |
840 | ||
2c06a082 BD |
841 | case TYPE_S3C2440: |
842 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; | |
843 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; | |
844 | break; | |
845 | ||
a4f957f1 | 846 | } |
1da177e4 | 847 | } else { |
6dfc6d25 | 848 | chip->ecc.mode = NAND_ECC_SOFT; |
1da177e4 | 849 | } |
1c21ab67 BD |
850 | |
851 | if (set->ecc_layout != NULL) | |
852 | chip->ecc.layout = set->ecc_layout; | |
37e5ffa3 BD |
853 | |
854 | if (set->disable_ecc) | |
855 | chip->ecc.mode = NAND_ECC_NONE; | |
8c3e843d AG |
856 | |
857 | switch (chip->ecc.mode) { | |
858 | case NAND_ECC_NONE: | |
859 | dev_info(info->device, "NAND ECC disabled\n"); | |
860 | break; | |
861 | case NAND_ECC_SOFT: | |
862 | dev_info(info->device, "NAND soft ECC\n"); | |
863 | break; | |
864 | case NAND_ECC_HW: | |
865 | dev_info(info->device, "NAND hardware ECC\n"); | |
866 | break; | |
867 | default: | |
868 | dev_info(info->device, "NAND ECC UNKNOWN\n"); | |
869 | break; | |
870 | } | |
9db41f9e MP |
871 | |
872 | /* If you use u-boot BBT creation code, specifying this flag will | |
873 | * let the kernel fish out the BBT from the NAND, and also skip the | |
874 | * full NAND scan that can take 1/2s or so. Little things... */ | |
a40f7341 | 875 | if (set->flash_bbt) { |
bb9ebd4e | 876 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 BN |
877 | chip->options |= NAND_SKIP_BBTSCAN; |
878 | } | |
1da177e4 LT |
879 | } |
880 | ||
3db72151 BD |
881 | /** |
882 | * s3c2410_nand_update_chip - post probe update | |
883 | * @info: The controller instance. | |
884 | * @nmtd: The driver version of the MTD instance. | |
71d54f38 | 885 | * |
af901ca1 | 886 | * This routine is called after the chip probe has successfully completed |
3db72151 BD |
887 | * and the relevant per-chip information updated. This call ensure that |
888 | * we update the internal state accordingly. | |
889 | * | |
890 | * The internal state is currently limited to the ECC state information. | |
891 | */ | |
71d54f38 BD |
892 | static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info, |
893 | struct s3c2410_nand_mtd *nmtd) | |
894 | { | |
895 | struct nand_chip *chip = &nmtd->chip; | |
896 | ||
451d3399 BD |
897 | dev_dbg(info->device, "chip %p => page shift %d\n", |
898 | chip, chip->page_shift); | |
71d54f38 | 899 | |
8c3e843d AG |
900 | if (chip->ecc.mode != NAND_ECC_HW) |
901 | return; | |
902 | ||
71d54f38 BD |
903 | /* change the behaviour depending on wether we are using |
904 | * the large or small page nand device */ | |
905 | ||
8c3e843d AG |
906 | if (chip->page_shift > 10) { |
907 | chip->ecc.size = 256; | |
908 | chip->ecc.bytes = 3; | |
909 | } else { | |
910 | chip->ecc.size = 512; | |
911 | chip->ecc.bytes = 3; | |
912 | chip->ecc.layout = &nand_hw_eccoob; | |
71d54f38 BD |
913 | } |
914 | } | |
915 | ||
ec0482e6 | 916 | /* s3c24xx_nand_probe |
1da177e4 LT |
917 | * |
918 | * called by device layer when it finds a device matching | |
919 | * one our driver can handled. This code checks to see if | |
920 | * it can allocate all necessary resources then calls the | |
921 | * nand layer to look for devices | |
922 | */ | |
ec0482e6 | 923 | static int s3c24xx_nand_probe(struct platform_device *pdev) |
1da177e4 | 924 | { |
3ae5eaec | 925 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
ec0482e6 | 926 | enum s3c_cpu_type cpu_type; |
1da177e4 LT |
927 | struct s3c2410_nand_info *info; |
928 | struct s3c2410_nand_mtd *nmtd; | |
929 | struct s3c2410_nand_set *sets; | |
930 | struct resource *res; | |
931 | int err = 0; | |
932 | int size; | |
933 | int nr_sets; | |
934 | int setno; | |
935 | ||
ec0482e6 BD |
936 | cpu_type = platform_get_device_id(pdev)->driver_data; |
937 | ||
3ae5eaec | 938 | pr_debug("s3c2410_nand_probe(%p)\n", pdev); |
1da177e4 | 939 | |
ecce2a6f | 940 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
1da177e4 | 941 | if (info == NULL) { |
3ae5eaec | 942 | dev_err(&pdev->dev, "no memory for flash info\n"); |
1da177e4 LT |
943 | err = -ENOMEM; |
944 | goto exit_error; | |
945 | } | |
946 | ||
3ae5eaec | 947 | platform_set_drvdata(pdev, info); |
1da177e4 LT |
948 | |
949 | spin_lock_init(&info->controller.lock); | |
a4f957f1 | 950 | init_waitqueue_head(&info->controller.wq); |
1da177e4 LT |
951 | |
952 | /* get the clock source and enable it */ | |
953 | ||
3ae5eaec | 954 | info->clk = clk_get(&pdev->dev, "nand"); |
1da177e4 | 955 | if (IS_ERR(info->clk)) { |
898eb71c | 956 | dev_err(&pdev->dev, "failed to get clock\n"); |
1da177e4 LT |
957 | err = -ENOENT; |
958 | goto exit_error; | |
959 | } | |
960 | ||
ac497c16 | 961 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
1da177e4 LT |
962 | |
963 | /* allocate and map the resource */ | |
964 | ||
a4f957f1 BD |
965 | /* currently we assume we have the one resource */ |
966 | res = pdev->resource; | |
fc161c4e | 967 | size = resource_size(res); |
1da177e4 LT |
968 | |
969 | info->area = request_mem_region(res->start, size, pdev->name); | |
970 | ||
971 | if (info->area == NULL) { | |
3ae5eaec | 972 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
1da177e4 LT |
973 | err = -ENOENT; |
974 | goto exit_error; | |
975 | } | |
976 | ||
3ae5eaec | 977 | info->device = &pdev->dev; |
a4f957f1 BD |
978 | info->platform = plat; |
979 | info->regs = ioremap(res->start, size); | |
2c06a082 | 980 | info->cpu_type = cpu_type; |
1da177e4 LT |
981 | |
982 | if (info->regs == NULL) { | |
3ae5eaec | 983 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
1da177e4 LT |
984 | err = -EIO; |
985 | goto exit_error; | |
61b03bd7 | 986 | } |
1da177e4 | 987 | |
3ae5eaec | 988 | dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); |
1da177e4 LT |
989 | |
990 | /* initialise the hardware */ | |
991 | ||
30821fee | 992 | err = s3c2410_nand_inithw(info); |
1da177e4 LT |
993 | if (err != 0) |
994 | goto exit_error; | |
995 | ||
996 | sets = (plat != NULL) ? plat->sets : NULL; | |
997 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; | |
998 | ||
999 | info->mtd_count = nr_sets; | |
1000 | ||
1001 | /* allocate our information */ | |
1002 | ||
1003 | size = nr_sets * sizeof(*info->mtds); | |
ecce2a6f | 1004 | info->mtds = kzalloc(size, GFP_KERNEL); |
1da177e4 | 1005 | if (info->mtds == NULL) { |
3ae5eaec | 1006 | dev_err(&pdev->dev, "failed to allocate mtd storage\n"); |
1da177e4 LT |
1007 | err = -ENOMEM; |
1008 | goto exit_error; | |
1009 | } | |
1010 | ||
1da177e4 LT |
1011 | /* initialise all possible chips */ |
1012 | ||
1013 | nmtd = info->mtds; | |
1014 | ||
1015 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { | |
e0c7d767 | 1016 | pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info); |
61b03bd7 | 1017 | |
1da177e4 LT |
1018 | s3c2410_nand_init_chip(info, nmtd, sets); |
1019 | ||
71d54f38 | 1020 | nmtd->scan_res = nand_scan_ident(&nmtd->mtd, |
5e81e88a DW |
1021 | (sets) ? sets->nr_chips : 1, |
1022 | NULL); | |
1da177e4 LT |
1023 | |
1024 | if (nmtd->scan_res == 0) { | |
71d54f38 BD |
1025 | s3c2410_nand_update_chip(info, nmtd); |
1026 | nand_scan_tail(&nmtd->mtd); | |
1da177e4 LT |
1027 | s3c2410_nand_add_partition(info, nmtd, sets); |
1028 | } | |
1029 | ||
1030 | if (sets != NULL) | |
1031 | sets++; | |
1032 | } | |
61b03bd7 | 1033 | |
30821fee BD |
1034 | err = s3c2410_nand_cpufreq_register(info); |
1035 | if (err < 0) { | |
1036 | dev_err(&pdev->dev, "failed to init cpufreq support\n"); | |
1037 | goto exit_error; | |
1038 | } | |
1039 | ||
ac497c16 | 1040 | if (allow_clk_suspend(info)) { |
d1fef3c5 | 1041 | dev_info(&pdev->dev, "clock idle support enabled\n"); |
ac497c16 | 1042 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1043 | } |
1044 | ||
1da177e4 LT |
1045 | pr_debug("initialised ok\n"); |
1046 | return 0; | |
1047 | ||
1048 | exit_error: | |
ec0482e6 | 1049 | s3c24xx_nand_remove(pdev); |
1da177e4 LT |
1050 | |
1051 | if (err == 0) | |
1052 | err = -EINVAL; | |
1053 | return err; | |
1054 | } | |
1055 | ||
d1fef3c5 BD |
1056 | /* PM Support */ |
1057 | #ifdef CONFIG_PM | |
1058 | ||
1059 | static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) | |
1060 | { | |
1061 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
1062 | ||
1063 | if (info) { | |
09160832 | 1064 | info->save_sel = readl(info->sel_reg); |
03680b1e BD |
1065 | |
1066 | /* For the moment, we must ensure nFCE is high during | |
1067 | * the time we are suspended. This really should be | |
1068 | * handled by suspending the MTDs we are using, but | |
1069 | * that is currently not the case. */ | |
1070 | ||
09160832 | 1071 | writel(info->save_sel | info->sel_bit, info->sel_reg); |
03680b1e | 1072 | |
ac497c16 | 1073 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
d1fef3c5 BD |
1074 | } |
1075 | ||
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | static int s3c24xx_nand_resume(struct platform_device *dev) | |
1080 | { | |
1081 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
09160832 | 1082 | unsigned long sel; |
d1fef3c5 BD |
1083 | |
1084 | if (info) { | |
ac497c16 | 1085 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
30821fee | 1086 | s3c2410_nand_inithw(info); |
d1fef3c5 | 1087 | |
03680b1e BD |
1088 | /* Restore the state of the nFCE line. */ |
1089 | ||
09160832 BD |
1090 | sel = readl(info->sel_reg); |
1091 | sel &= ~info->sel_bit; | |
1092 | sel |= info->save_sel & info->sel_bit; | |
1093 | writel(sel, info->sel_reg); | |
03680b1e | 1094 | |
ac497c16 | 1095 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1096 | } |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | #else | |
1102 | #define s3c24xx_nand_suspend NULL | |
1103 | #define s3c24xx_nand_resume NULL | |
1104 | #endif | |
1105 | ||
a4f957f1 BD |
1106 | /* driver device registration */ |
1107 | ||
ec0482e6 BD |
1108 | static struct platform_device_id s3c24xx_driver_ids[] = { |
1109 | { | |
1110 | .name = "s3c2410-nand", | |
1111 | .driver_data = TYPE_S3C2410, | |
1112 | }, { | |
1113 | .name = "s3c2440-nand", | |
1114 | .driver_data = TYPE_S3C2440, | |
1115 | }, { | |
1116 | .name = "s3c2412-nand", | |
1117 | .driver_data = TYPE_S3C2412, | |
9dbc0902 PK |
1118 | }, { |
1119 | .name = "s3c6400-nand", | |
1120 | .driver_data = TYPE_S3C2412, /* compatible with 2412 */ | |
3ae5eaec | 1121 | }, |
ec0482e6 | 1122 | { } |
1da177e4 LT |
1123 | }; |
1124 | ||
ec0482e6 | 1125 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
a4f957f1 | 1126 | |
ec0482e6 BD |
1127 | static struct platform_driver s3c24xx_nand_driver = { |
1128 | .probe = s3c24xx_nand_probe, | |
1129 | .remove = s3c24xx_nand_remove, | |
2c06a082 BD |
1130 | .suspend = s3c24xx_nand_suspend, |
1131 | .resume = s3c24xx_nand_resume, | |
ec0482e6 | 1132 | .id_table = s3c24xx_driver_ids, |
2c06a082 | 1133 | .driver = { |
ec0482e6 | 1134 | .name = "s3c24xx-nand", |
2c06a082 BD |
1135 | .owner = THIS_MODULE, |
1136 | }, | |
1137 | }; | |
1138 | ||
056fcab5 | 1139 | module_platform_driver(s3c24xx_nand_driver); |
1da177e4 LT |
1140 | |
1141 | MODULE_LICENSE("GPL"); | |
1142 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
a4f957f1 | 1143 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |