Commit | Line | Data |
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1da177e4 LT |
1 | /* linux/drivers/mtd/nand/s3c2410.c |
2 | * | |
7e74a507 BD |
3 | * Copyright © 2004-2008 Simtec Electronics |
4 | * http://armlinux.simtec.co.uk/ | |
fdf2fd52 | 5 | * Ben Dooks <ben@simtec.co.uk> |
1da177e4 | 6 | * |
7e74a507 | 7 | * Samsung S3C2410/S3C2440/S3C2412 NAND driver |
1da177e4 | 8 | * |
1da177e4 LT |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
92aeb5d2 SK |
24 | #define pr_fmt(fmt) "nand-s3c2410: " fmt |
25 | ||
1da177e4 LT |
26 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG |
27 | #define DEBUG | |
28 | #endif | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/types.h> | |
1da177e4 LT |
32 | #include <linux/kernel.h> |
33 | #include <linux/string.h> | |
d2a89be8 | 34 | #include <linux/io.h> |
1da177e4 | 35 | #include <linux/ioport.h> |
d052d1be | 36 | #include <linux/platform_device.h> |
1da177e4 LT |
37 | #include <linux/delay.h> |
38 | #include <linux/err.h> | |
4e57b681 | 39 | #include <linux/slab.h> |
f8ce2547 | 40 | #include <linux/clk.h> |
30821fee | 41 | #include <linux/cpufreq.h> |
1da177e4 LT |
42 | |
43 | #include <linux/mtd/mtd.h> | |
44 | #include <linux/mtd/nand.h> | |
45 | #include <linux/mtd/nand_ecc.h> | |
46 | #include <linux/mtd/partitions.h> | |
47 | ||
436d42c6 | 48 | #include <linux/platform_data/mtd-nand-s3c2410.h> |
1da177e4 | 49 | |
02d01862 SK |
50 | #define S3C2410_NFREG(x) (x) |
51 | ||
52 | #define S3C2410_NFCONF S3C2410_NFREG(0x00) | |
53 | #define S3C2410_NFCMD S3C2410_NFREG(0x04) | |
54 | #define S3C2410_NFADDR S3C2410_NFREG(0x08) | |
55 | #define S3C2410_NFDATA S3C2410_NFREG(0x0C) | |
56 | #define S3C2410_NFSTAT S3C2410_NFREG(0x10) | |
57 | #define S3C2410_NFECC S3C2410_NFREG(0x14) | |
58 | #define S3C2440_NFCONT S3C2410_NFREG(0x04) | |
59 | #define S3C2440_NFCMD S3C2410_NFREG(0x08) | |
60 | #define S3C2440_NFADDR S3C2410_NFREG(0x0C) | |
61 | #define S3C2440_NFDATA S3C2410_NFREG(0x10) | |
62 | #define S3C2440_NFSTAT S3C2410_NFREG(0x20) | |
63 | #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) | |
64 | #define S3C2412_NFSTAT S3C2410_NFREG(0x28) | |
65 | #define S3C2412_NFMECC0 S3C2410_NFREG(0x34) | |
66 | #define S3C2410_NFCONF_EN (1<<15) | |
67 | #define S3C2410_NFCONF_INITECC (1<<12) | |
68 | #define S3C2410_NFCONF_nFCE (1<<11) | |
69 | #define S3C2410_NFCONF_TACLS(x) ((x)<<8) | |
70 | #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) | |
71 | #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) | |
72 | #define S3C2410_NFSTAT_BUSY (1<<0) | |
73 | #define S3C2440_NFCONF_TACLS(x) ((x)<<12) | |
74 | #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) | |
75 | #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) | |
76 | #define S3C2440_NFCONT_INITECC (1<<4) | |
77 | #define S3C2440_NFCONT_nFCE (1<<1) | |
78 | #define S3C2440_NFCONT_ENABLE (1<<0) | |
79 | #define S3C2440_NFSTAT_READY (1<<0) | |
80 | #define S3C2412_NFCONF_NANDBOOT (1<<31) | |
81 | #define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5) | |
82 | #define S3C2412_NFCONT_nFCE0 (1<<1) | |
83 | #define S3C2412_NFSTAT_READY (1<<0) | |
84 | ||
1da177e4 LT |
85 | /* new oob placement block for use with hardware ecc generation |
86 | */ | |
bf01e06b BB |
87 | static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section, |
88 | struct mtd_oob_region *oobregion) | |
89 | { | |
90 | if (section) | |
91 | return -ERANGE; | |
92 | ||
93 | oobregion->offset = 0; | |
94 | oobregion->length = 3; | |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
99 | static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section, | |
100 | struct mtd_oob_region *oobregion) | |
101 | { | |
102 | if (section) | |
103 | return -ERANGE; | |
104 | ||
105 | oobregion->offset = 8; | |
106 | oobregion->length = 8; | |
107 | ||
108 | return 0; | |
109 | } | |
1da177e4 | 110 | |
bf01e06b BB |
111 | static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = { |
112 | .ecc = s3c2410_ooblayout_ecc, | |
113 | .free = s3c2410_ooblayout_free, | |
1da177e4 LT |
114 | }; |
115 | ||
116 | /* controller and mtd information */ | |
117 | ||
118 | struct s3c2410_nand_info; | |
119 | ||
3db72151 BD |
120 | /** |
121 | * struct s3c2410_nand_mtd - driver MTD structure | |
122 | * @mtd: The MTD instance to pass to the MTD layer. | |
123 | * @chip: The NAND chip information. | |
124 | * @set: The platform information supplied for this set of NAND chips. | |
125 | * @info: Link back to the hardware information. | |
126 | * @scan_res: The result from calling nand_scan_ident(). | |
127 | */ | |
1da177e4 | 128 | struct s3c2410_nand_mtd { |
1da177e4 LT |
129 | struct nand_chip chip; |
130 | struct s3c2410_nand_set *set; | |
131 | struct s3c2410_nand_info *info; | |
132 | int scan_res; | |
133 | }; | |
134 | ||
2c06a082 BD |
135 | enum s3c_cpu_type { |
136 | TYPE_S3C2410, | |
137 | TYPE_S3C2412, | |
138 | TYPE_S3C2440, | |
139 | }; | |
140 | ||
ac497c16 JP |
141 | enum s3c_nand_clk_state { |
142 | CLOCK_DISABLE = 0, | |
143 | CLOCK_ENABLE, | |
144 | CLOCK_SUSPEND, | |
145 | }; | |
146 | ||
1da177e4 LT |
147 | /* overview of the s3c2410 nand state */ |
148 | ||
3db72151 BD |
149 | /** |
150 | * struct s3c2410_nand_info - NAND controller state. | |
151 | * @mtds: An array of MTD instances on this controoler. | |
152 | * @platform: The platform data for this board. | |
153 | * @device: The platform device we bound to. | |
3db72151 | 154 | * @clk: The clock resource for this controller. |
6f32a3e2 | 155 | * @regs: The area mapped for the hardware registers. |
3db72151 BD |
156 | * @sel_reg: Pointer to the register controlling the NAND selection. |
157 | * @sel_bit: The bit in @sel_reg to select the NAND chip. | |
158 | * @mtd_count: The number of MTDs created from this controller. | |
159 | * @save_sel: The contents of @sel_reg to be saved over suspend. | |
160 | * @clk_rate: The clock rate from @clk. | |
ac497c16 | 161 | * @clk_state: The current clock state. |
3db72151 BD |
162 | * @cpu_type: The exact type of this controller. |
163 | */ | |
1da177e4 LT |
164 | struct s3c2410_nand_info { |
165 | /* mtd info */ | |
166 | struct nand_hw_control controller; | |
167 | struct s3c2410_nand_mtd *mtds; | |
168 | struct s3c2410_platform_nand *platform; | |
169 | ||
170 | /* device info */ | |
171 | struct device *device; | |
1da177e4 | 172 | struct clk *clk; |
fdf2fd52 | 173 | void __iomem *regs; |
2c06a082 BD |
174 | void __iomem *sel_reg; |
175 | int sel_bit; | |
1da177e4 | 176 | int mtd_count; |
09160832 | 177 | unsigned long save_sel; |
30821fee | 178 | unsigned long clk_rate; |
ac497c16 | 179 | enum s3c_nand_clk_state clk_state; |
03680b1e | 180 | |
2c06a082 | 181 | enum s3c_cpu_type cpu_type; |
30821fee BD |
182 | |
183 | #ifdef CONFIG_CPU_FREQ | |
184 | struct notifier_block freq_transition; | |
185 | #endif | |
1da177e4 LT |
186 | }; |
187 | ||
188 | /* conversion functions */ | |
189 | ||
190 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) | |
191 | { | |
7208b997 BB |
192 | return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd, |
193 | chip); | |
1da177e4 LT |
194 | } |
195 | ||
196 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) | |
197 | { | |
198 | return s3c2410_nand_mtd_toours(mtd)->info; | |
199 | } | |
200 | ||
3ae5eaec | 201 | static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) |
1da177e4 | 202 | { |
3ae5eaec | 203 | return platform_get_drvdata(dev); |
1da177e4 LT |
204 | } |
205 | ||
3ae5eaec | 206 | static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) |
1da177e4 | 207 | { |
453810b7 | 208 | return dev_get_platdata(&dev->dev); |
1da177e4 LT |
209 | } |
210 | ||
ac497c16 | 211 | static inline int allow_clk_suspend(struct s3c2410_nand_info *info) |
d1fef3c5 | 212 | { |
a68c5ec8 SK |
213 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP |
214 | return 1; | |
215 | #else | |
216 | return 0; | |
217 | #endif | |
d1fef3c5 BD |
218 | } |
219 | ||
ac497c16 JP |
220 | /** |
221 | * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. | |
222 | * @info: The controller instance. | |
223 | * @new_state: State to which clock should be set. | |
224 | */ | |
225 | static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, | |
226 | enum s3c_nand_clk_state new_state) | |
227 | { | |
228 | if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) | |
229 | return; | |
230 | ||
231 | if (info->clk_state == CLOCK_ENABLE) { | |
232 | if (new_state != CLOCK_ENABLE) | |
887957b4 | 233 | clk_disable_unprepare(info->clk); |
ac497c16 JP |
234 | } else { |
235 | if (new_state == CLOCK_ENABLE) | |
887957b4 | 236 | clk_prepare_enable(info->clk); |
ac497c16 JP |
237 | } |
238 | ||
239 | info->clk_state = new_state; | |
240 | } | |
241 | ||
1da177e4 LT |
242 | /* timing calculations */ |
243 | ||
cfd320fb | 244 | #define NS_IN_KHZ 1000000 |
1da177e4 | 245 | |
3db72151 BD |
246 | /** |
247 | * s3c_nand_calc_rate - calculate timing data. | |
248 | * @wanted: The cycle time in nanoseconds. | |
249 | * @clk: The clock rate in kHz. | |
250 | * @max: The maximum divider value. | |
251 | * | |
252 | * Calculate the timing value from the given parameters. | |
253 | */ | |
2c06a082 | 254 | static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) |
1da177e4 LT |
255 | { |
256 | int result; | |
257 | ||
947391cf | 258 | result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); |
1da177e4 LT |
259 | |
260 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); | |
261 | ||
262 | if (result > max) { | |
92aeb5d2 SK |
263 | pr_err("%d ns is too big for current clock rate %ld\n", |
264 | wanted, clk); | |
1da177e4 LT |
265 | return -1; |
266 | } | |
267 | ||
268 | if (result < 1) | |
269 | result = 1; | |
270 | ||
271 | return result; | |
272 | } | |
273 | ||
54cd0208 | 274 | #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
1da177e4 LT |
275 | |
276 | /* controller setup */ | |
277 | ||
3db72151 BD |
278 | /** |
279 | * s3c2410_nand_setrate - setup controller timing information. | |
280 | * @info: The controller instance. | |
281 | * | |
282 | * Given the information supplied by the platform, calculate and set | |
283 | * the necessary timing registers in the hardware to generate the | |
284 | * necessary timing cycles to the hardware. | |
285 | */ | |
30821fee | 286 | static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) |
1da177e4 | 287 | { |
30821fee | 288 | struct s3c2410_platform_nand *plat = info->platform; |
2c06a082 | 289 | int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; |
cfd320fb | 290 | int tacls, twrph0, twrph1; |
30821fee | 291 | unsigned long clkrate = clk_get_rate(info->clk); |
2612e523 | 292 | unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); |
30821fee | 293 | unsigned long flags; |
1da177e4 LT |
294 | |
295 | /* calculate the timing information for the controller */ | |
296 | ||
30821fee | 297 | info->clk_rate = clkrate; |
cfd320fb BD |
298 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
299 | ||
1da177e4 | 300 | if (plat != NULL) { |
2c06a082 BD |
301 | tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); |
302 | twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); | |
303 | twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); | |
1da177e4 LT |
304 | } else { |
305 | /* default timings */ | |
2c06a082 | 306 | tacls = tacls_max; |
1da177e4 LT |
307 | twrph0 = 8; |
308 | twrph1 = 8; | |
309 | } | |
61b03bd7 | 310 | |
1da177e4 | 311 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
99974c62 | 312 | dev_err(info->device, "cannot get suitable timings\n"); |
1da177e4 LT |
313 | return -EINVAL; |
314 | } | |
315 | ||
99974c62 | 316 | dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
54cd0208 SK |
317 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), |
318 | twrph1, to_ns(twrph1, clkrate)); | |
1da177e4 | 319 | |
30821fee BD |
320 | switch (info->cpu_type) { |
321 | case TYPE_S3C2410: | |
322 | mask = (S3C2410_NFCONF_TACLS(3) | | |
323 | S3C2410_NFCONF_TWRPH0(7) | | |
324 | S3C2410_NFCONF_TWRPH1(7)); | |
325 | set = S3C2410_NFCONF_EN; | |
326 | set |= S3C2410_NFCONF_TACLS(tacls - 1); | |
327 | set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); | |
328 | set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); | |
329 | break; | |
330 | ||
331 | case TYPE_S3C2440: | |
332 | case TYPE_S3C2412: | |
a755a385 PK |
333 | mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | |
334 | S3C2440_NFCONF_TWRPH0(7) | | |
335 | S3C2440_NFCONF_TWRPH1(7)); | |
30821fee BD |
336 | |
337 | set = S3C2440_NFCONF_TACLS(tacls - 1); | |
338 | set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); | |
339 | set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); | |
340 | break; | |
341 | ||
342 | default: | |
30821fee BD |
343 | BUG(); |
344 | } | |
345 | ||
30821fee BD |
346 | local_irq_save(flags); |
347 | ||
348 | cfg = readl(info->regs + S3C2410_NFCONF); | |
349 | cfg &= ~mask; | |
350 | cfg |= set; | |
351 | writel(cfg, info->regs + S3C2410_NFCONF); | |
352 | ||
353 | local_irq_restore(flags); | |
354 | ||
ae7304e5 AG |
355 | dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); |
356 | ||
30821fee BD |
357 | return 0; |
358 | } | |
359 | ||
3db72151 BD |
360 | /** |
361 | * s3c2410_nand_inithw - basic hardware initialisation | |
362 | * @info: The hardware state. | |
363 | * | |
364 | * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() | |
365 | * to setup the hardware access speeds and set the controller to be enabled. | |
366 | */ | |
30821fee BD |
367 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) |
368 | { | |
369 | int ret; | |
370 | ||
371 | ret = s3c2410_nand_setrate(info); | |
372 | if (ret < 0) | |
373 | return ret; | |
374 | ||
54cd0208 SK |
375 | switch (info->cpu_type) { |
376 | case TYPE_S3C2410: | |
30821fee | 377 | default: |
2c06a082 BD |
378 | break; |
379 | ||
54cd0208 SK |
380 | case TYPE_S3C2440: |
381 | case TYPE_S3C2412: | |
d1fef3c5 BD |
382 | /* enable the controller and de-assert nFCE */ |
383 | ||
2c06a082 | 384 | writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); |
a4f957f1 | 385 | } |
1da177e4 | 386 | |
1da177e4 LT |
387 | return 0; |
388 | } | |
389 | ||
3db72151 BD |
390 | /** |
391 | * s3c2410_nand_select_chip - select the given nand chip | |
392 | * @mtd: The MTD instance for this chip. | |
393 | * @chip: The chip number. | |
394 | * | |
395 | * This is called by the MTD layer to either select a given chip for the | |
396 | * @mtd instance, or to indicate that the access has finished and the | |
397 | * chip can be de-selected. | |
398 | * | |
399 | * The routine ensures that the nFCE line is correctly setup, and any | |
400 | * platform specific selection code is called to route nFCE to the specific | |
401 | * chip. | |
402 | */ | |
1da177e4 LT |
403 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) |
404 | { | |
405 | struct s3c2410_nand_info *info; | |
61b03bd7 | 406 | struct s3c2410_nand_mtd *nmtd; |
4bd4ebcc | 407 | struct nand_chip *this = mtd_to_nand(mtd); |
1da177e4 LT |
408 | unsigned long cur; |
409 | ||
d699ed25 | 410 | nmtd = nand_get_controller_data(this); |
1da177e4 LT |
411 | info = nmtd->info; |
412 | ||
ac497c16 JP |
413 | if (chip != -1) |
414 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); | |
d1fef3c5 | 415 | |
2c06a082 | 416 | cur = readl(info->sel_reg); |
1da177e4 LT |
417 | |
418 | if (chip == -1) { | |
2c06a082 | 419 | cur |= info->sel_bit; |
1da177e4 | 420 | } else { |
fb8d82a8 | 421 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
99974c62 | 422 | dev_err(info->device, "invalid chip %d\n", chip); |
1da177e4 LT |
423 | return; |
424 | } | |
425 | ||
426 | if (info->platform != NULL) { | |
427 | if (info->platform->select_chip != NULL) | |
e0c7d767 | 428 | (info->platform->select_chip) (nmtd->set, chip); |
1da177e4 LT |
429 | } |
430 | ||
2c06a082 | 431 | cur &= ~info->sel_bit; |
1da177e4 LT |
432 | } |
433 | ||
2c06a082 | 434 | writel(cur, info->sel_reg); |
d1fef3c5 | 435 | |
ac497c16 JP |
436 | if (chip == -1) |
437 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); | |
1da177e4 LT |
438 | } |
439 | ||
ad3b5fb7 | 440 | /* s3c2410_nand_hwcontrol |
a4f957f1 | 441 | * |
ad3b5fb7 | 442 | * Issue command and address cycles to the chip |
a4f957f1 | 443 | */ |
1da177e4 | 444 | |
7abd3ef9 | 445 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
f9068876 | 446 | unsigned int ctrl) |
1da177e4 LT |
447 | { |
448 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
c9ac5977 | 449 | |
7abd3ef9 TG |
450 | if (cmd == NAND_CMD_NONE) |
451 | return; | |
452 | ||
f9068876 | 453 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
454 | writeb(cmd, info->regs + S3C2410_NFCMD); |
455 | else | |
456 | writeb(cmd, info->regs + S3C2410_NFADDR); | |
a4f957f1 BD |
457 | } |
458 | ||
459 | /* command and control functions */ | |
460 | ||
f9068876 DW |
461 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
462 | unsigned int ctrl) | |
a4f957f1 BD |
463 | { |
464 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 | 465 | |
7abd3ef9 TG |
466 | if (cmd == NAND_CMD_NONE) |
467 | return; | |
468 | ||
f9068876 | 469 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
470 | writeb(cmd, info->regs + S3C2440_NFCMD); |
471 | else | |
472 | writeb(cmd, info->regs + S3C2440_NFADDR); | |
1da177e4 LT |
473 | } |
474 | ||
1da177e4 LT |
475 | /* s3c2410_nand_devready() |
476 | * | |
477 | * returns 0 if the nand is busy, 1 if it is ready | |
478 | */ | |
479 | ||
480 | static int s3c2410_nand_devready(struct mtd_info *mtd) | |
481 | { | |
482 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 LT |
483 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
484 | } | |
485 | ||
2c06a082 BD |
486 | static int s3c2440_nand_devready(struct mtd_info *mtd) |
487 | { | |
488 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
489 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; | |
490 | } | |
491 | ||
492 | static int s3c2412_nand_devready(struct mtd_info *mtd) | |
493 | { | |
494 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
495 | return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; | |
496 | } | |
497 | ||
1da177e4 LT |
498 | /* ECC handling functions */ |
499 | ||
19da4158 | 500 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
2c06a082 BD |
501 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
502 | u_char *read_ecc, u_char *calc_ecc) | |
1da177e4 | 503 | { |
a2593247 BD |
504 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
505 | unsigned int diff0, diff1, diff2; | |
506 | unsigned int bit, byte; | |
507 | ||
508 | pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); | |
509 | ||
510 | diff0 = read_ecc[0] ^ calc_ecc[0]; | |
511 | diff1 = read_ecc[1] ^ calc_ecc[1]; | |
512 | diff2 = read_ecc[2] ^ calc_ecc[2]; | |
513 | ||
13e85974 AS |
514 | pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n", |
515 | __func__, 3, read_ecc, 3, calc_ecc, | |
a2593247 BD |
516 | diff0, diff1, diff2); |
517 | ||
518 | if (diff0 == 0 && diff1 == 0 && diff2 == 0) | |
519 | return 0; /* ECC is ok */ | |
520 | ||
c45c6c68 BD |
521 | /* sometimes people do not think about using the ECC, so check |
522 | * to see if we have an 0xff,0xff,0xff read ECC and then ignore | |
523 | * the error, on the assumption that this is an un-eccd page. | |
524 | */ | |
525 | if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff | |
526 | && info->platform->ignore_unset_ecc) | |
527 | return 0; | |
528 | ||
a2593247 BD |
529 | /* Can we correct this ECC (ie, one row and column change). |
530 | * Note, this is similar to the 256 error code on smartmedia */ | |
531 | ||
532 | if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && | |
533 | ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && | |
534 | ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { | |
535 | /* calculate the bit position of the error */ | |
536 | ||
d0bf3793 MR |
537 | bit = ((diff2 >> 3) & 1) | |
538 | ((diff2 >> 4) & 2) | | |
539 | ((diff2 >> 5) & 4); | |
1da177e4 | 540 | |
a2593247 | 541 | /* calculate the byte position of the error */ |
1da177e4 | 542 | |
d0bf3793 MR |
543 | byte = ((diff2 << 7) & 0x100) | |
544 | ((diff1 << 0) & 0x80) | | |
545 | ((diff1 << 1) & 0x40) | | |
546 | ((diff1 << 2) & 0x20) | | |
547 | ((diff1 << 3) & 0x10) | | |
548 | ((diff0 >> 4) & 0x08) | | |
549 | ((diff0 >> 3) & 0x04) | | |
550 | ((diff0 >> 2) & 0x02) | | |
551 | ((diff0 >> 1) & 0x01); | |
a2593247 BD |
552 | |
553 | dev_dbg(info->device, "correcting error bit %d, byte %d\n", | |
554 | bit, byte); | |
555 | ||
556 | dat[byte] ^= (1 << bit); | |
557 | return 1; | |
558 | } | |
559 | ||
560 | /* if there is only one bit difference in the ECC, then | |
561 | * one of only a row or column parity has changed, which | |
562 | * means the error is most probably in the ECC itself */ | |
563 | ||
564 | diff0 |= (diff1 << 8); | |
565 | diff0 |= (diff2 << 16); | |
566 | ||
03a97550 ZZ |
567 | /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */ |
568 | if ((diff0 & (diff0 - 1)) == 0) | |
a2593247 BD |
569 | return 1; |
570 | ||
4fac9f69 | 571 | return -1; |
1da177e4 LT |
572 | } |
573 | ||
a4f957f1 BD |
574 | /* ECC functions |
575 | * | |
576 | * These allow the s3c2410 and s3c2440 to use the controller's ECC | |
577 | * generator block to ECC the data as it passes through] | |
578 | */ | |
579 | ||
1da177e4 LT |
580 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
581 | { | |
582 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
583 | unsigned long ctrl; | |
584 | ||
585 | ctrl = readl(info->regs + S3C2410_NFCONF); | |
586 | ctrl |= S3C2410_NFCONF_INITECC; | |
587 | writel(ctrl, info->regs + S3C2410_NFCONF); | |
588 | } | |
589 | ||
4f659923 MC |
590 | static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
591 | { | |
592 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
593 | unsigned long ctrl; | |
594 | ||
595 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
f938bc56 SK |
596 | writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, |
597 | info->regs + S3C2440_NFCONT); | |
4f659923 MC |
598 | } |
599 | ||
a4f957f1 BD |
600 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
601 | { | |
602 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
603 | unsigned long ctrl; | |
604 | ||
605 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
606 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); | |
607 | } | |
608 | ||
f938bc56 SK |
609 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
610 | u_char *ecc_code) | |
1da177e4 LT |
611 | { |
612 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
613 | ||
614 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); | |
615 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); | |
616 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); | |
617 | ||
13e85974 | 618 | pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); |
1da177e4 LT |
619 | |
620 | return 0; | |
621 | } | |
622 | ||
f938bc56 SK |
623 | static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
624 | u_char *ecc_code) | |
4f659923 MC |
625 | { |
626 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
627 | unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); | |
628 | ||
629 | ecc_code[0] = ecc; | |
630 | ecc_code[1] = ecc >> 8; | |
631 | ecc_code[2] = ecc >> 16; | |
632 | ||
13e85974 | 633 | pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); |
4f659923 MC |
634 | |
635 | return 0; | |
636 | } | |
637 | ||
f938bc56 SK |
638 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
639 | u_char *ecc_code) | |
a4f957f1 BD |
640 | { |
641 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
642 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); | |
643 | ||
644 | ecc_code[0] = ecc; | |
645 | ecc_code[1] = ecc >> 8; | |
646 | ecc_code[2] = ecc >> 16; | |
647 | ||
71d54f38 | 648 | pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); |
a4f957f1 BD |
649 | |
650 | return 0; | |
651 | } | |
19da4158 | 652 | #endif |
a4f957f1 | 653 | |
a4f957f1 BD |
654 | /* over-ride the standard functions for a little more speed. We can |
655 | * use read/write block to move the data buffers to/from the controller | |
656 | */ | |
1da177e4 LT |
657 | |
658 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
659 | { | |
4bd4ebcc | 660 | struct nand_chip *this = mtd_to_nand(mtd); |
1da177e4 LT |
661 | readsb(this->IO_ADDR_R, buf, len); |
662 | } | |
663 | ||
b773bb2e MR |
664 | static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
665 | { | |
666 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
667 | |
668 | readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
669 | ||
670 | /* cleanup if we've got less than a word to do */ | |
671 | if (len & 3) { | |
672 | buf += len & ~3; | |
673 | ||
674 | for (; len & 3; len--) | |
675 | *buf++ = readb(info->regs + S3C2440_NFDATA); | |
676 | } | |
b773bb2e MR |
677 | } |
678 | ||
f938bc56 SK |
679 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, |
680 | int len) | |
1da177e4 | 681 | { |
4bd4ebcc | 682 | struct nand_chip *this = mtd_to_nand(mtd); |
1da177e4 LT |
683 | writesb(this->IO_ADDR_W, buf, len); |
684 | } | |
685 | ||
f938bc56 SK |
686 | static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, |
687 | int len) | |
b773bb2e MR |
688 | { |
689 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
690 | |
691 | writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
692 | ||
693 | /* cleanup any fractional write */ | |
694 | if (len & 3) { | |
695 | buf += len & ~3; | |
696 | ||
697 | for (; len & 3; len--, buf++) | |
698 | writeb(*buf, info->regs + S3C2440_NFDATA); | |
699 | } | |
b773bb2e MR |
700 | } |
701 | ||
30821fee BD |
702 | /* cpufreq driver support */ |
703 | ||
704 | #ifdef CONFIG_CPU_FREQ | |
705 | ||
706 | static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, | |
707 | unsigned long val, void *data) | |
708 | { | |
709 | struct s3c2410_nand_info *info; | |
710 | unsigned long newclk; | |
711 | ||
712 | info = container_of(nb, struct s3c2410_nand_info, freq_transition); | |
713 | newclk = clk_get_rate(info->clk); | |
714 | ||
715 | if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || | |
716 | (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { | |
717 | s3c2410_nand_setrate(info); | |
718 | } | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
724 | { | |
725 | info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; | |
726 | ||
727 | return cpufreq_register_notifier(&info->freq_transition, | |
728 | CPUFREQ_TRANSITION_NOTIFIER); | |
729 | } | |
730 | ||
f938bc56 SK |
731 | static inline void |
732 | s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
30821fee BD |
733 | { |
734 | cpufreq_unregister_notifier(&info->freq_transition, | |
735 | CPUFREQ_TRANSITION_NOTIFIER); | |
736 | } | |
737 | ||
738 | #else | |
739 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
740 | { | |
741 | return 0; | |
742 | } | |
743 | ||
f938bc56 SK |
744 | static inline void |
745 | s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
30821fee BD |
746 | { |
747 | } | |
748 | #endif | |
749 | ||
1da177e4 LT |
750 | /* device management functions */ |
751 | ||
ec0482e6 | 752 | static int s3c24xx_nand_remove(struct platform_device *pdev) |
1da177e4 | 753 | { |
3ae5eaec | 754 | struct s3c2410_nand_info *info = to_nand_info(pdev); |
1da177e4 | 755 | |
61b03bd7 | 756 | if (info == NULL) |
1da177e4 LT |
757 | return 0; |
758 | ||
30821fee BD |
759 | s3c2410_nand_cpufreq_deregister(info); |
760 | ||
761 | /* Release all our mtds and their partitions, then go through | |
762 | * freeing the resources used | |
1da177e4 | 763 | */ |
61b03bd7 | 764 | |
1da177e4 LT |
765 | if (info->mtds != NULL) { |
766 | struct s3c2410_nand_mtd *ptr = info->mtds; | |
767 | int mtdno; | |
768 | ||
769 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { | |
770 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); | |
7208b997 | 771 | nand_release(nand_to_mtd(&ptr->chip)); |
1da177e4 | 772 | } |
1da177e4 LT |
773 | } |
774 | ||
775 | /* free the common resources */ | |
776 | ||
6f32a3e2 | 777 | if (!IS_ERR(info->clk)) |
ac497c16 | 778 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
1da177e4 LT |
779 | |
780 | return 0; | |
781 | } | |
782 | ||
1da177e4 LT |
783 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, |
784 | struct s3c2410_nand_mtd *mtd, | |
785 | struct s3c2410_nand_set *set) | |
786 | { | |
ded4c55d | 787 | if (set) { |
7208b997 | 788 | struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip); |
ed27f028 | 789 | |
7208b997 BB |
790 | mtdinfo->name = set->name; |
791 | ||
792 | return mtd_device_parse_register(mtdinfo, NULL, NULL, | |
42d7fbe2 | 793 | set->partitions, set->nr_partitions); |
ded4c55d SK |
794 | } |
795 | ||
796 | return -ENODEV; | |
1da177e4 | 797 | } |
1da177e4 | 798 | |
3db72151 BD |
799 | /** |
800 | * s3c2410_nand_init_chip - initialise a single instance of an chip | |
801 | * @info: The base NAND controller the chip is on. | |
802 | * @nmtd: The new controller MTD instance to fill in. | |
803 | * @set: The information passed from the board specific platform data. | |
1da177e4 | 804 | * |
3db72151 BD |
805 | * Initialise the given @nmtd from the information in @info and @set. This |
806 | * readies the structure for use with the MTD layer functions by ensuring | |
807 | * all pointers are setup and the necessary control routines selected. | |
808 | */ | |
1da177e4 LT |
809 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, |
810 | struct s3c2410_nand_mtd *nmtd, | |
811 | struct s3c2410_nand_set *set) | |
812 | { | |
813 | struct nand_chip *chip = &nmtd->chip; | |
2c06a082 | 814 | void __iomem *regs = info->regs; |
1da177e4 | 815 | |
1da177e4 LT |
816 | chip->write_buf = s3c2410_nand_write_buf; |
817 | chip->read_buf = s3c2410_nand_read_buf; | |
818 | chip->select_chip = s3c2410_nand_select_chip; | |
819 | chip->chip_delay = 50; | |
d699ed25 | 820 | nand_set_controller_data(chip, nmtd); |
74218fed | 821 | chip->options = set->options; |
1da177e4 LT |
822 | chip->controller = &info->controller; |
823 | ||
2c06a082 BD |
824 | switch (info->cpu_type) { |
825 | case TYPE_S3C2410: | |
826 | chip->IO_ADDR_W = regs + S3C2410_NFDATA; | |
827 | info->sel_reg = regs + S3C2410_NFCONF; | |
828 | info->sel_bit = S3C2410_NFCONF_nFCE; | |
829 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; | |
830 | chip->dev_ready = s3c2410_nand_devready; | |
831 | break; | |
832 | ||
833 | case TYPE_S3C2440: | |
834 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
835 | info->sel_reg = regs + S3C2440_NFCONT; | |
836 | info->sel_bit = S3C2440_NFCONT_nFCE; | |
837 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
838 | chip->dev_ready = s3c2440_nand_devready; | |
b773bb2e MR |
839 | chip->read_buf = s3c2440_nand_read_buf; |
840 | chip->write_buf = s3c2440_nand_write_buf; | |
2c06a082 BD |
841 | break; |
842 | ||
843 | case TYPE_S3C2412: | |
844 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
845 | info->sel_reg = regs + S3C2440_NFCONT; | |
846 | info->sel_bit = S3C2412_NFCONT_nFCE0; | |
847 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
848 | chip->dev_ready = s3c2412_nand_devready; | |
849 | ||
850 | if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) | |
851 | dev_info(info->device, "System booted from NAND\n"); | |
852 | ||
853 | break; | |
54cd0208 | 854 | } |
2c06a082 BD |
855 | |
856 | chip->IO_ADDR_R = chip->IO_ADDR_W; | |
a4f957f1 | 857 | |
1da177e4 | 858 | nmtd->info = info; |
1da177e4 LT |
859 | nmtd->set = set; |
860 | ||
a68c5ec8 SK |
861 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
862 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | |
863 | chip->ecc.correct = s3c2410_nand_correct_data; | |
864 | chip->ecc.mode = NAND_ECC_HW; | |
865 | chip->ecc.strength = 1; | |
866 | ||
867 | switch (info->cpu_type) { | |
868 | case TYPE_S3C2410: | |
869 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; | |
6dfc6d25 | 870 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
a68c5ec8 | 871 | break; |
2c06a082 | 872 | |
a68c5ec8 SK |
873 | case TYPE_S3C2412: |
874 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; | |
875 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; | |
876 | break; | |
877 | ||
878 | case TYPE_S3C2440: | |
879 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; | |
880 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; | |
881 | break; | |
1da177e4 | 882 | } |
a68c5ec8 SK |
883 | #else |
884 | chip->ecc.mode = NAND_ECC_SOFT; | |
c4fe72a7 | 885 | chip->ecc.algo = NAND_ECC_HAMMING; |
a68c5ec8 | 886 | #endif |
1c21ab67 | 887 | |
37e5ffa3 BD |
888 | if (set->disable_ecc) |
889 | chip->ecc.mode = NAND_ECC_NONE; | |
8c3e843d AG |
890 | |
891 | switch (chip->ecc.mode) { | |
892 | case NAND_ECC_NONE: | |
893 | dev_info(info->device, "NAND ECC disabled\n"); | |
894 | break; | |
895 | case NAND_ECC_SOFT: | |
896 | dev_info(info->device, "NAND soft ECC\n"); | |
897 | break; | |
898 | case NAND_ECC_HW: | |
899 | dev_info(info->device, "NAND hardware ECC\n"); | |
900 | break; | |
901 | default: | |
902 | dev_info(info->device, "NAND ECC UNKNOWN\n"); | |
903 | break; | |
904 | } | |
9db41f9e MP |
905 | |
906 | /* If you use u-boot BBT creation code, specifying this flag will | |
907 | * let the kernel fish out the BBT from the NAND, and also skip the | |
908 | * full NAND scan that can take 1/2s or so. Little things... */ | |
a40f7341 | 909 | if (set->flash_bbt) { |
bb9ebd4e | 910 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 BN |
911 | chip->options |= NAND_SKIP_BBTSCAN; |
912 | } | |
1da177e4 LT |
913 | } |
914 | ||
3db72151 BD |
915 | /** |
916 | * s3c2410_nand_update_chip - post probe update | |
917 | * @info: The controller instance. | |
918 | * @nmtd: The driver version of the MTD instance. | |
71d54f38 | 919 | * |
af901ca1 | 920 | * This routine is called after the chip probe has successfully completed |
3db72151 BD |
921 | * and the relevant per-chip information updated. This call ensure that |
922 | * we update the internal state accordingly. | |
923 | * | |
924 | * The internal state is currently limited to the ECC state information. | |
925 | */ | |
71d54f38 BD |
926 | static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info, |
927 | struct s3c2410_nand_mtd *nmtd) | |
928 | { | |
929 | struct nand_chip *chip = &nmtd->chip; | |
930 | ||
451d3399 BD |
931 | dev_dbg(info->device, "chip %p => page shift %d\n", |
932 | chip, chip->page_shift); | |
71d54f38 | 933 | |
8c3e843d AG |
934 | if (chip->ecc.mode != NAND_ECC_HW) |
935 | return; | |
936 | ||
48fc7f7e | 937 | /* change the behaviour depending on whether we are using |
71d54f38 BD |
938 | * the large or small page nand device */ |
939 | ||
8c3e843d AG |
940 | if (chip->page_shift > 10) { |
941 | chip->ecc.size = 256; | |
942 | chip->ecc.bytes = 3; | |
943 | } else { | |
944 | chip->ecc.size = 512; | |
945 | chip->ecc.bytes = 3; | |
bf01e06b | 946 | mtd_set_ooblayout(nand_to_mtd(chip), &s3c2410_ooblayout_ops); |
71d54f38 BD |
947 | } |
948 | } | |
949 | ||
ec0482e6 | 950 | /* s3c24xx_nand_probe |
1da177e4 LT |
951 | * |
952 | * called by device layer when it finds a device matching | |
953 | * one our driver can handled. This code checks to see if | |
954 | * it can allocate all necessary resources then calls the | |
955 | * nand layer to look for devices | |
956 | */ | |
ec0482e6 | 957 | static int s3c24xx_nand_probe(struct platform_device *pdev) |
1da177e4 | 958 | { |
3ae5eaec | 959 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
54cd0208 | 960 | enum s3c_cpu_type cpu_type; |
1da177e4 LT |
961 | struct s3c2410_nand_info *info; |
962 | struct s3c2410_nand_mtd *nmtd; | |
963 | struct s3c2410_nand_set *sets; | |
964 | struct resource *res; | |
965 | int err = 0; | |
966 | int size; | |
967 | int nr_sets; | |
968 | int setno; | |
969 | ||
ec0482e6 BD |
970 | cpu_type = platform_get_device_id(pdev)->driver_data; |
971 | ||
6f32a3e2 | 972 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
1da177e4 | 973 | if (info == NULL) { |
1da177e4 LT |
974 | err = -ENOMEM; |
975 | goto exit_error; | |
976 | } | |
977 | ||
3ae5eaec | 978 | platform_set_drvdata(pdev, info); |
1da177e4 | 979 | |
fe18266a | 980 | nand_hw_control_init(&info->controller); |
1da177e4 LT |
981 | |
982 | /* get the clock source and enable it */ | |
983 | ||
6f32a3e2 | 984 | info->clk = devm_clk_get(&pdev->dev, "nand"); |
1da177e4 | 985 | if (IS_ERR(info->clk)) { |
898eb71c | 986 | dev_err(&pdev->dev, "failed to get clock\n"); |
1da177e4 LT |
987 | err = -ENOENT; |
988 | goto exit_error; | |
989 | } | |
990 | ||
ac497c16 | 991 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
1da177e4 LT |
992 | |
993 | /* allocate and map the resource */ | |
994 | ||
a4f957f1 | 995 | /* currently we assume we have the one resource */ |
6f32a3e2 | 996 | res = pdev->resource; |
fc161c4e | 997 | size = resource_size(res); |
1da177e4 | 998 | |
6f32a3e2 SK |
999 | info->device = &pdev->dev; |
1000 | info->platform = plat; | |
1001 | info->cpu_type = cpu_type; | |
1da177e4 | 1002 | |
b0de774c TR |
1003 | info->regs = devm_ioremap_resource(&pdev->dev, res); |
1004 | if (IS_ERR(info->regs)) { | |
1005 | err = PTR_ERR(info->regs); | |
1da177e4 | 1006 | goto exit_error; |
61b03bd7 | 1007 | } |
1da177e4 | 1008 | |
3ae5eaec | 1009 | dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); |
1da177e4 LT |
1010 | |
1011 | /* initialise the hardware */ | |
1012 | ||
30821fee | 1013 | err = s3c2410_nand_inithw(info); |
1da177e4 LT |
1014 | if (err != 0) |
1015 | goto exit_error; | |
1016 | ||
1017 | sets = (plat != NULL) ? plat->sets : NULL; | |
1018 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; | |
1019 | ||
1020 | info->mtd_count = nr_sets; | |
1021 | ||
1022 | /* allocate our information */ | |
1023 | ||
1024 | size = nr_sets * sizeof(*info->mtds); | |
6f32a3e2 | 1025 | info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
1da177e4 | 1026 | if (info->mtds == NULL) { |
1da177e4 LT |
1027 | err = -ENOMEM; |
1028 | goto exit_error; | |
1029 | } | |
1030 | ||
1da177e4 LT |
1031 | /* initialise all possible chips */ |
1032 | ||
1033 | nmtd = info->mtds; | |
1034 | ||
1035 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { | |
7208b997 BB |
1036 | struct mtd_info *mtd = nand_to_mtd(&nmtd->chip); |
1037 | ||
f938bc56 SK |
1038 | pr_debug("initialising set %d (%p, info %p)\n", |
1039 | setno, nmtd, info); | |
61b03bd7 | 1040 | |
7208b997 | 1041 | mtd->dev.parent = &pdev->dev; |
1da177e4 LT |
1042 | s3c2410_nand_init_chip(info, nmtd, sets); |
1043 | ||
7208b997 | 1044 | nmtd->scan_res = nand_scan_ident(mtd, |
5e81e88a DW |
1045 | (sets) ? sets->nr_chips : 1, |
1046 | NULL); | |
1da177e4 LT |
1047 | |
1048 | if (nmtd->scan_res == 0) { | |
71d54f38 | 1049 | s3c2410_nand_update_chip(info, nmtd); |
7208b997 | 1050 | nand_scan_tail(mtd); |
1da177e4 LT |
1051 | s3c2410_nand_add_partition(info, nmtd, sets); |
1052 | } | |
1053 | ||
1054 | if (sets != NULL) | |
1055 | sets++; | |
1056 | } | |
61b03bd7 | 1057 | |
30821fee BD |
1058 | err = s3c2410_nand_cpufreq_register(info); |
1059 | if (err < 0) { | |
1060 | dev_err(&pdev->dev, "failed to init cpufreq support\n"); | |
1061 | goto exit_error; | |
1062 | } | |
1063 | ||
ac497c16 | 1064 | if (allow_clk_suspend(info)) { |
d1fef3c5 | 1065 | dev_info(&pdev->dev, "clock idle support enabled\n"); |
ac497c16 | 1066 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1067 | } |
1068 | ||
1da177e4 LT |
1069 | return 0; |
1070 | ||
1071 | exit_error: | |
ec0482e6 | 1072 | s3c24xx_nand_remove(pdev); |
1da177e4 LT |
1073 | |
1074 | if (err == 0) | |
1075 | err = -EINVAL; | |
1076 | return err; | |
1077 | } | |
1078 | ||
d1fef3c5 BD |
1079 | /* PM Support */ |
1080 | #ifdef CONFIG_PM | |
1081 | ||
1082 | static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) | |
1083 | { | |
1084 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
1085 | ||
1086 | if (info) { | |
09160832 | 1087 | info->save_sel = readl(info->sel_reg); |
03680b1e BD |
1088 | |
1089 | /* For the moment, we must ensure nFCE is high during | |
1090 | * the time we are suspended. This really should be | |
1091 | * handled by suspending the MTDs we are using, but | |
1092 | * that is currently not the case. */ | |
1093 | ||
09160832 | 1094 | writel(info->save_sel | info->sel_bit, info->sel_reg); |
03680b1e | 1095 | |
ac497c16 | 1096 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
d1fef3c5 BD |
1097 | } |
1098 | ||
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static int s3c24xx_nand_resume(struct platform_device *dev) | |
1103 | { | |
1104 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
09160832 | 1105 | unsigned long sel; |
d1fef3c5 BD |
1106 | |
1107 | if (info) { | |
ac497c16 | 1108 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
30821fee | 1109 | s3c2410_nand_inithw(info); |
d1fef3c5 | 1110 | |
03680b1e BD |
1111 | /* Restore the state of the nFCE line. */ |
1112 | ||
09160832 BD |
1113 | sel = readl(info->sel_reg); |
1114 | sel &= ~info->sel_bit; | |
1115 | sel |= info->save_sel & info->sel_bit; | |
1116 | writel(sel, info->sel_reg); | |
03680b1e | 1117 | |
ac497c16 | 1118 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1119 | } |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | #else | |
1125 | #define s3c24xx_nand_suspend NULL | |
1126 | #define s3c24xx_nand_resume NULL | |
1127 | #endif | |
1128 | ||
a4f957f1 BD |
1129 | /* driver device registration */ |
1130 | ||
0abe75d2 | 1131 | static const struct platform_device_id s3c24xx_driver_ids[] = { |
ec0482e6 BD |
1132 | { |
1133 | .name = "s3c2410-nand", | |
1134 | .driver_data = TYPE_S3C2410, | |
1135 | }, { | |
1136 | .name = "s3c2440-nand", | |
1137 | .driver_data = TYPE_S3C2440, | |
1138 | }, { | |
1139 | .name = "s3c2412-nand", | |
1140 | .driver_data = TYPE_S3C2412, | |
9dbc0902 PK |
1141 | }, { |
1142 | .name = "s3c6400-nand", | |
1143 | .driver_data = TYPE_S3C2412, /* compatible with 2412 */ | |
3ae5eaec | 1144 | }, |
ec0482e6 | 1145 | { } |
1da177e4 LT |
1146 | }; |
1147 | ||
ec0482e6 | 1148 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
a4f957f1 | 1149 | |
ec0482e6 BD |
1150 | static struct platform_driver s3c24xx_nand_driver = { |
1151 | .probe = s3c24xx_nand_probe, | |
1152 | .remove = s3c24xx_nand_remove, | |
2c06a082 BD |
1153 | .suspend = s3c24xx_nand_suspend, |
1154 | .resume = s3c24xx_nand_resume, | |
ec0482e6 | 1155 | .id_table = s3c24xx_driver_ids, |
2c06a082 | 1156 | .driver = { |
ec0482e6 | 1157 | .name = "s3c24xx-nand", |
2c06a082 BD |
1158 | }, |
1159 | }; | |
1160 | ||
056fcab5 | 1161 | module_platform_driver(s3c24xx_nand_driver); |
1da177e4 LT |
1162 | |
1163 | MODULE_LICENSE("GPL"); | |
1164 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
a4f957f1 | 1165 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |