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1da177e4 LT |
1 | /* linux/drivers/mtd/nand/s3c2410.c |
2 | * | |
a4f957f1 | 3 | * Copyright (c) 2004,2005 Simtec Electronics |
fdf2fd52 BD |
4 | * http://www.simtec.co.uk/products/SWLINUX/ |
5 | * Ben Dooks <ben@simtec.co.uk> | |
1da177e4 | 6 | * |
a4f957f1 | 7 | * Samsung S3C2410/S3C240 NAND driver |
1da177e4 LT |
8 | * |
9 | * Changelog: | |
10 | * 21-Sep-2004 BJD Initial version | |
11 | * 23-Sep-2004 BJD Mulitple device support | |
12 | * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode | |
13 | * 12-Oct-2004 BJD Fixed errors in use of platform data | |
3e4ef3bb BD |
14 | * 18-Feb-2005 BJD Fix sparse errors |
15 | * 14-Mar-2005 BJD Applied tglx's code reduction patch | |
a4f957f1 BD |
16 | * 02-May-2005 BJD Fixed s3c2440 support |
17 | * 02-May-2005 BJD Reduced hwcontrol decode | |
18 | * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug | |
fb8d82a8 | 19 | * 08-Jul-2005 BJD Fix OOPS when no platform data supplied |
cfd320fb | 20 | * 20-Oct-2005 BJD Fix timing calculation bug |
1da177e4 | 21 | * |
61b03bd7 | 22 | * $Id: s3c2410.c,v 1.20 2005/11/07 11:14:31 gleixner Exp $ |
1da177e4 LT |
23 | * |
24 | * This program is free software; you can redistribute it and/or modify | |
25 | * it under the terms of the GNU General Public License as published by | |
26 | * the Free Software Foundation; either version 2 of the License, or | |
27 | * (at your option) any later version. | |
28 | * | |
29 | * This program is distributed in the hope that it will be useful, | |
30 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
31 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
32 | * GNU General Public License for more details. | |
33 | * | |
34 | * You should have received a copy of the GNU General Public License | |
35 | * along with this program; if not, write to the Free Software | |
36 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
37 | */ | |
38 | ||
39 | #include <config/mtd/nand/s3c2410/hwecc.h> | |
40 | #include <config/mtd/nand/s3c2410/debug.h> | |
41 | ||
42 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG | |
43 | #define DEBUG | |
44 | #endif | |
45 | ||
46 | #include <linux/module.h> | |
47 | #include <linux/types.h> | |
48 | #include <linux/init.h> | |
49 | #include <linux/kernel.h> | |
50 | #include <linux/string.h> | |
51 | #include <linux/ioport.h> | |
d052d1be | 52 | #include <linux/platform_device.h> |
1da177e4 LT |
53 | #include <linux/delay.h> |
54 | #include <linux/err.h> | |
4e57b681 | 55 | #include <linux/slab.h> |
f8ce2547 | 56 | #include <linux/clk.h> |
1da177e4 LT |
57 | |
58 | #include <linux/mtd/mtd.h> | |
59 | #include <linux/mtd/nand.h> | |
60 | #include <linux/mtd/nand_ecc.h> | |
61 | #include <linux/mtd/partitions.h> | |
62 | ||
63 | #include <asm/io.h> | |
1da177e4 LT |
64 | |
65 | #include <asm/arch/regs-nand.h> | |
66 | #include <asm/arch/nand.h> | |
67 | ||
68 | #define PFX "s3c2410-nand: " | |
69 | ||
70 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC | |
71 | static int hardware_ecc = 1; | |
72 | #else | |
73 | static int hardware_ecc = 0; | |
74 | #endif | |
75 | ||
76 | /* new oob placement block for use with hardware ecc generation | |
77 | */ | |
78 | ||
79 | static struct nand_oobinfo nand_hw_eccoob = { | |
e0c7d767 DW |
80 | .useecc = MTD_NANDECC_AUTOPLACE, |
81 | .eccbytes = 3, | |
82 | .eccpos = {0, 1, 2}, | |
83 | .oobfree = {{8, 8}} | |
1da177e4 LT |
84 | }; |
85 | ||
86 | /* controller and mtd information */ | |
87 | ||
88 | struct s3c2410_nand_info; | |
89 | ||
90 | struct s3c2410_nand_mtd { | |
91 | struct mtd_info mtd; | |
92 | struct nand_chip chip; | |
93 | struct s3c2410_nand_set *set; | |
94 | struct s3c2410_nand_info *info; | |
95 | int scan_res; | |
96 | }; | |
97 | ||
98 | /* overview of the s3c2410 nand state */ | |
99 | ||
100 | struct s3c2410_nand_info { | |
101 | /* mtd info */ | |
102 | struct nand_hw_control controller; | |
103 | struct s3c2410_nand_mtd *mtds; | |
104 | struct s3c2410_platform_nand *platform; | |
105 | ||
106 | /* device info */ | |
107 | struct device *device; | |
108 | struct resource *area; | |
109 | struct clk *clk; | |
fdf2fd52 | 110 | void __iomem *regs; |
1da177e4 | 111 | int mtd_count; |
a4f957f1 BD |
112 | |
113 | unsigned char is_s3c2440; | |
1da177e4 LT |
114 | }; |
115 | ||
116 | /* conversion functions */ | |
117 | ||
118 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) | |
119 | { | |
120 | return container_of(mtd, struct s3c2410_nand_mtd, mtd); | |
121 | } | |
122 | ||
123 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) | |
124 | { | |
125 | return s3c2410_nand_mtd_toours(mtd)->info; | |
126 | } | |
127 | ||
3ae5eaec | 128 | static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) |
1da177e4 | 129 | { |
3ae5eaec | 130 | return platform_get_drvdata(dev); |
1da177e4 LT |
131 | } |
132 | ||
3ae5eaec | 133 | static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) |
1da177e4 | 134 | { |
3ae5eaec | 135 | return dev->dev.platform_data; |
1da177e4 LT |
136 | } |
137 | ||
138 | /* timing calculations */ | |
139 | ||
cfd320fb | 140 | #define NS_IN_KHZ 1000000 |
1da177e4 LT |
141 | |
142 | static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max) | |
143 | { | |
144 | int result; | |
145 | ||
cfd320fb | 146 | result = (wanted * clk) / NS_IN_KHZ; |
1da177e4 LT |
147 | result++; |
148 | ||
149 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); | |
150 | ||
151 | if (result > max) { | |
e0c7d767 | 152 | printk("%d ns is too big for current clock rate %ld\n", wanted, clk); |
1da177e4 LT |
153 | return -1; |
154 | } | |
155 | ||
156 | if (result < 1) | |
157 | result = 1; | |
158 | ||
159 | return result; | |
160 | } | |
161 | ||
cfd320fb | 162 | #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
1da177e4 LT |
163 | |
164 | /* controller setup */ | |
165 | ||
e0c7d767 | 166 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, struct platform_device *pdev) |
1da177e4 | 167 | { |
3ae5eaec | 168 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
1da177e4 | 169 | unsigned long clkrate = clk_get_rate(info->clk); |
cfd320fb | 170 | int tacls, twrph0, twrph1; |
1da177e4 LT |
171 | unsigned long cfg; |
172 | ||
173 | /* calculate the timing information for the controller */ | |
174 | ||
cfd320fb BD |
175 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
176 | ||
1da177e4 | 177 | if (plat != NULL) { |
e0c7d767 | 178 | tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4); |
1da177e4 LT |
179 | twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8); |
180 | twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8); | |
181 | } else { | |
182 | /* default timings */ | |
a4f957f1 | 183 | tacls = 4; |
1da177e4 LT |
184 | twrph0 = 8; |
185 | twrph1 = 8; | |
186 | } | |
61b03bd7 | 187 | |
1da177e4 LT |
188 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
189 | printk(KERN_ERR PFX "cannot get timings suitable for board\n"); | |
190 | return -EINVAL; | |
191 | } | |
192 | ||
cfd320fb | 193 | printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
e0c7d767 | 194 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate)); |
1da177e4 | 195 | |
a4f957f1 | 196 | if (!info->is_s3c2440) { |
e0c7d767 DW |
197 | cfg = S3C2410_NFCONF_EN; |
198 | cfg |= S3C2410_NFCONF_TACLS(tacls - 1); | |
199 | cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); | |
200 | cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); | |
a4f957f1 | 201 | } else { |
e0c7d767 DW |
202 | cfg = S3C2440_NFCONF_TACLS(tacls - 1); |
203 | cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); | |
204 | cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); | |
a4f957f1 | 205 | } |
1da177e4 LT |
206 | |
207 | pr_debug(PFX "NF_CONF is 0x%lx\n", cfg); | |
208 | ||
209 | writel(cfg, info->regs + S3C2410_NFCONF); | |
210 | return 0; | |
211 | } | |
212 | ||
213 | /* select chip */ | |
214 | ||
215 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) | |
216 | { | |
217 | struct s3c2410_nand_info *info; | |
61b03bd7 | 218 | struct s3c2410_nand_mtd *nmtd; |
1da177e4 | 219 | struct nand_chip *this = mtd->priv; |
a4f957f1 | 220 | void __iomem *reg; |
1da177e4 | 221 | unsigned long cur; |
a4f957f1 | 222 | unsigned long bit; |
1da177e4 LT |
223 | |
224 | nmtd = this->priv; | |
225 | info = nmtd->info; | |
226 | ||
a4f957f1 | 227 | bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE; |
e0c7d767 | 228 | reg = info->regs + ((info->is_s3c2440) ? S3C2440_NFCONT : S3C2410_NFCONF); |
a4f957f1 BD |
229 | |
230 | cur = readl(reg); | |
1da177e4 LT |
231 | |
232 | if (chip == -1) { | |
a4f957f1 | 233 | cur |= bit; |
1da177e4 | 234 | } else { |
fb8d82a8 | 235 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
1da177e4 LT |
236 | printk(KERN_ERR PFX "chip %d out of range\n", chip); |
237 | return; | |
238 | } | |
239 | ||
240 | if (info->platform != NULL) { | |
241 | if (info->platform->select_chip != NULL) | |
e0c7d767 | 242 | (info->platform->select_chip) (nmtd->set, chip); |
1da177e4 LT |
243 | } |
244 | ||
a4f957f1 | 245 | cur &= ~bit; |
1da177e4 LT |
246 | } |
247 | ||
a4f957f1 | 248 | writel(cur, reg); |
1da177e4 LT |
249 | } |
250 | ||
61b03bd7 | 251 | /* command and control functions |
a4f957f1 BD |
252 | * |
253 | * Note, these all use tglx's method of changing the IO_ADDR_W field | |
254 | * to make the code simpler, and use the nand layer's code to issue the | |
255 | * command and address sequences via the proper IO ports. | |
256 | * | |
257 | */ | |
1da177e4 | 258 | |
7abd3ef9 TG |
259 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
260 | unsigend int ctrl) | |
1da177e4 LT |
261 | { |
262 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
3e4ef3bb | 263 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 264 | |
7abd3ef9 TG |
265 | if (cmd == NAND_CMD_NONE) |
266 | return; | |
267 | ||
268 | if (cmd & NAND_CLE) | |
269 | writeb(cmd, info->regs + S3C2410_NFCMD); | |
270 | else | |
271 | writeb(cmd, info->regs + S3C2410_NFADDR); | |
a4f957f1 BD |
272 | } |
273 | ||
274 | /* command and control functions */ | |
275 | ||
7abd3ef9 TG |
276 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
277 | unsigend int ctrl) | |
a4f957f1 BD |
278 | { |
279 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
280 | struct nand_chip *chip = mtd->priv; | |
1da177e4 | 281 | |
7abd3ef9 TG |
282 | if (cmd == NAND_CMD_NONE) |
283 | return; | |
284 | ||
285 | if (cmd & NAND_CLE) | |
286 | writeb(cmd, info->regs + S3C2440_NFCMD); | |
287 | else | |
288 | writeb(cmd, info->regs + S3C2440_NFADDR); | |
1da177e4 LT |
289 | } |
290 | ||
1da177e4 LT |
291 | /* s3c2410_nand_devready() |
292 | * | |
293 | * returns 0 if the nand is busy, 1 if it is ready | |
294 | */ | |
295 | ||
296 | static int s3c2410_nand_devready(struct mtd_info *mtd) | |
297 | { | |
298 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
61b03bd7 | 299 | |
a4f957f1 BD |
300 | if (info->is_s3c2440) |
301 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; | |
1da177e4 LT |
302 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
303 | } | |
304 | ||
305 | /* ECC handling functions */ | |
306 | ||
e0c7d767 | 307 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) |
1da177e4 | 308 | { |
e0c7d767 | 309 | pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc); |
1da177e4 LT |
310 | |
311 | pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n", | |
e0c7d767 | 312 | read_ecc[0], read_ecc[1], read_ecc[2], calc_ecc[0], calc_ecc[1], calc_ecc[2]); |
1da177e4 | 313 | |
e0c7d767 | 314 | if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2]) |
1da177e4 LT |
315 | return 0; |
316 | ||
317 | /* we curently have no method for correcting the error */ | |
318 | ||
319 | return -1; | |
320 | } | |
321 | ||
a4f957f1 BD |
322 | /* ECC functions |
323 | * | |
324 | * These allow the s3c2410 and s3c2440 to use the controller's ECC | |
325 | * generator block to ECC the data as it passes through] | |
326 | */ | |
327 | ||
1da177e4 LT |
328 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
329 | { | |
330 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
331 | unsigned long ctrl; | |
332 | ||
333 | ctrl = readl(info->regs + S3C2410_NFCONF); | |
334 | ctrl |= S3C2410_NFCONF_INITECC; | |
335 | writel(ctrl, info->regs + S3C2410_NFCONF); | |
336 | } | |
337 | ||
a4f957f1 BD |
338 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
339 | { | |
340 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
341 | unsigned long ctrl; | |
342 | ||
343 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
344 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); | |
345 | } | |
346 | ||
e0c7d767 | 347 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
1da177e4 LT |
348 | { |
349 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
350 | ||
351 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); | |
352 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); | |
353 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); | |
354 | ||
e0c7d767 | 355 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); |
1da177e4 LT |
356 | |
357 | return 0; | |
358 | } | |
359 | ||
e0c7d767 | 360 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
a4f957f1 BD |
361 | { |
362 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
363 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); | |
364 | ||
365 | ecc_code[0] = ecc; | |
366 | ecc_code[1] = ecc >> 8; | |
367 | ecc_code[2] = ecc >> 16; | |
368 | ||
e0c7d767 | 369 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]); |
a4f957f1 BD |
370 | |
371 | return 0; | |
372 | } | |
373 | ||
a4f957f1 BD |
374 | /* over-ride the standard functions for a little more speed. We can |
375 | * use read/write block to move the data buffers to/from the controller | |
376 | */ | |
1da177e4 LT |
377 | |
378 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
379 | { | |
380 | struct nand_chip *this = mtd->priv; | |
381 | readsb(this->IO_ADDR_R, buf, len); | |
382 | } | |
383 | ||
e0c7d767 | 384 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
1da177e4 LT |
385 | { |
386 | struct nand_chip *this = mtd->priv; | |
387 | writesb(this->IO_ADDR_W, buf, len); | |
388 | } | |
389 | ||
390 | /* device management functions */ | |
391 | ||
3ae5eaec | 392 | static int s3c2410_nand_remove(struct platform_device *pdev) |
1da177e4 | 393 | { |
3ae5eaec | 394 | struct s3c2410_nand_info *info = to_nand_info(pdev); |
1da177e4 | 395 | |
3ae5eaec | 396 | platform_set_drvdata(pdev, NULL); |
1da177e4 | 397 | |
61b03bd7 | 398 | if (info == NULL) |
1da177e4 LT |
399 | return 0; |
400 | ||
401 | /* first thing we need to do is release all our mtds | |
402 | * and their partitions, then go through freeing the | |
61b03bd7 | 403 | * resources used |
1da177e4 | 404 | */ |
61b03bd7 | 405 | |
1da177e4 LT |
406 | if (info->mtds != NULL) { |
407 | struct s3c2410_nand_mtd *ptr = info->mtds; | |
408 | int mtdno; | |
409 | ||
410 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { | |
411 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); | |
412 | nand_release(&ptr->mtd); | |
413 | } | |
414 | ||
415 | kfree(info->mtds); | |
416 | } | |
417 | ||
418 | /* free the common resources */ | |
419 | ||
420 | if (info->clk != NULL && !IS_ERR(info->clk)) { | |
421 | clk_disable(info->clk); | |
1da177e4 LT |
422 | clk_put(info->clk); |
423 | } | |
424 | ||
425 | if (info->regs != NULL) { | |
426 | iounmap(info->regs); | |
427 | info->regs = NULL; | |
428 | } | |
429 | ||
430 | if (info->area != NULL) { | |
431 | release_resource(info->area); | |
432 | kfree(info->area); | |
433 | info->area = NULL; | |
434 | } | |
435 | ||
436 | kfree(info); | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | #ifdef CONFIG_MTD_PARTITIONS | |
442 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, | |
443 | struct s3c2410_nand_mtd *mtd, | |
444 | struct s3c2410_nand_set *set) | |
445 | { | |
446 | if (set == NULL) | |
447 | return add_mtd_device(&mtd->mtd); | |
448 | ||
449 | if (set->nr_partitions > 0 && set->partitions != NULL) { | |
e0c7d767 | 450 | return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions); |
1da177e4 LT |
451 | } |
452 | ||
453 | return add_mtd_device(&mtd->mtd); | |
454 | } | |
455 | #else | |
456 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, | |
457 | struct s3c2410_nand_mtd *mtd, | |
458 | struct s3c2410_nand_set *set) | |
459 | { | |
460 | return add_mtd_device(&mtd->mtd); | |
461 | } | |
462 | #endif | |
463 | ||
464 | /* s3c2410_nand_init_chip | |
465 | * | |
61b03bd7 | 466 | * init a single instance of an chip |
1da177e4 LT |
467 | */ |
468 | ||
469 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, | |
470 | struct s3c2410_nand_mtd *nmtd, | |
471 | struct s3c2410_nand_set *set) | |
472 | { | |
473 | struct nand_chip *chip = &nmtd->chip; | |
474 | ||
fdf2fd52 BD |
475 | chip->IO_ADDR_R = info->regs + S3C2410_NFDATA; |
476 | chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; | |
7abd3ef9 | 477 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; |
1da177e4 | 478 | chip->dev_ready = s3c2410_nand_devready; |
1da177e4 LT |
479 | chip->write_buf = s3c2410_nand_write_buf; |
480 | chip->read_buf = s3c2410_nand_read_buf; | |
481 | chip->select_chip = s3c2410_nand_select_chip; | |
482 | chip->chip_delay = 50; | |
483 | chip->priv = nmtd; | |
484 | chip->options = 0; | |
485 | chip->controller = &info->controller; | |
486 | ||
a4f957f1 BD |
487 | if (info->is_s3c2440) { |
488 | chip->IO_ADDR_R = info->regs + S3C2440_NFDATA; | |
489 | chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; | |
7abd3ef9 | 490 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; |
a4f957f1 BD |
491 | } |
492 | ||
1da177e4 LT |
493 | nmtd->info = info; |
494 | nmtd->mtd.priv = chip; | |
552d9205 | 495 | nmtd->mtd.owner = THIS_MODULE; |
1da177e4 LT |
496 | nmtd->set = set; |
497 | ||
498 | if (hardware_ecc) { | |
6dfc6d25 TG |
499 | chip->ecc.correct = s3c2410_nand_correct_data; |
500 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; | |
501 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | |
502 | chip->ecc.mode = NAND_ECC_HW; | |
503 | chip->ecc.size = 512; | |
504 | chip->ecc.bytes = 3; | |
1da177e4 | 505 | chip->autooob = &nand_hw_eccoob; |
a4f957f1 BD |
506 | |
507 | if (info->is_s3c2440) { | |
6dfc6d25 TG |
508 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; |
509 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; | |
a4f957f1 | 510 | } |
1da177e4 | 511 | } else { |
6dfc6d25 | 512 | chip->ecc.mode = NAND_ECC_SOFT; |
1da177e4 LT |
513 | } |
514 | } | |
515 | ||
516 | /* s3c2410_nand_probe | |
517 | * | |
518 | * called by device layer when it finds a device matching | |
519 | * one our driver can handled. This code checks to see if | |
520 | * it can allocate all necessary resources then calls the | |
521 | * nand layer to look for devices | |
522 | */ | |
523 | ||
3ae5eaec | 524 | static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440) |
1da177e4 | 525 | { |
3ae5eaec | 526 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
1da177e4 LT |
527 | struct s3c2410_nand_info *info; |
528 | struct s3c2410_nand_mtd *nmtd; | |
529 | struct s3c2410_nand_set *sets; | |
530 | struct resource *res; | |
531 | int err = 0; | |
532 | int size; | |
533 | int nr_sets; | |
534 | int setno; | |
535 | ||
3ae5eaec | 536 | pr_debug("s3c2410_nand_probe(%p)\n", pdev); |
1da177e4 LT |
537 | |
538 | info = kmalloc(sizeof(*info), GFP_KERNEL); | |
539 | if (info == NULL) { | |
3ae5eaec | 540 | dev_err(&pdev->dev, "no memory for flash info\n"); |
1da177e4 LT |
541 | err = -ENOMEM; |
542 | goto exit_error; | |
543 | } | |
544 | ||
545 | memzero(info, sizeof(*info)); | |
3ae5eaec | 546 | platform_set_drvdata(pdev, info); |
1da177e4 LT |
547 | |
548 | spin_lock_init(&info->controller.lock); | |
a4f957f1 | 549 | init_waitqueue_head(&info->controller.wq); |
1da177e4 LT |
550 | |
551 | /* get the clock source and enable it */ | |
552 | ||
3ae5eaec | 553 | info->clk = clk_get(&pdev->dev, "nand"); |
1da177e4 | 554 | if (IS_ERR(info->clk)) { |
3ae5eaec | 555 | dev_err(&pdev->dev, "failed to get clock"); |
1da177e4 LT |
556 | err = -ENOENT; |
557 | goto exit_error; | |
558 | } | |
559 | ||
1da177e4 LT |
560 | clk_enable(info->clk); |
561 | ||
562 | /* allocate and map the resource */ | |
563 | ||
a4f957f1 BD |
564 | /* currently we assume we have the one resource */ |
565 | res = pdev->resource; | |
1da177e4 LT |
566 | size = res->end - res->start + 1; |
567 | ||
568 | info->area = request_mem_region(res->start, size, pdev->name); | |
569 | ||
570 | if (info->area == NULL) { | |
3ae5eaec | 571 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
1da177e4 LT |
572 | err = -ENOENT; |
573 | goto exit_error; | |
574 | } | |
575 | ||
3ae5eaec | 576 | info->device = &pdev->dev; |
a4f957f1 BD |
577 | info->platform = plat; |
578 | info->regs = ioremap(res->start, size); | |
579 | info->is_s3c2440 = is_s3c2440; | |
1da177e4 LT |
580 | |
581 | if (info->regs == NULL) { | |
3ae5eaec | 582 | dev_err(&pdev->dev, "cannot reserve register region\n"); |
1da177e4 LT |
583 | err = -EIO; |
584 | goto exit_error; | |
61b03bd7 | 585 | } |
1da177e4 | 586 | |
3ae5eaec | 587 | dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); |
1da177e4 LT |
588 | |
589 | /* initialise the hardware */ | |
590 | ||
3ae5eaec | 591 | err = s3c2410_nand_inithw(info, pdev); |
1da177e4 LT |
592 | if (err != 0) |
593 | goto exit_error; | |
594 | ||
595 | sets = (plat != NULL) ? plat->sets : NULL; | |
596 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; | |
597 | ||
598 | info->mtd_count = nr_sets; | |
599 | ||
600 | /* allocate our information */ | |
601 | ||
602 | size = nr_sets * sizeof(*info->mtds); | |
603 | info->mtds = kmalloc(size, GFP_KERNEL); | |
604 | if (info->mtds == NULL) { | |
3ae5eaec | 605 | dev_err(&pdev->dev, "failed to allocate mtd storage\n"); |
1da177e4 LT |
606 | err = -ENOMEM; |
607 | goto exit_error; | |
608 | } | |
609 | ||
610 | memzero(info->mtds, size); | |
611 | ||
612 | /* initialise all possible chips */ | |
613 | ||
614 | nmtd = info->mtds; | |
615 | ||
616 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { | |
e0c7d767 | 617 | pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info); |
61b03bd7 | 618 | |
1da177e4 LT |
619 | s3c2410_nand_init_chip(info, nmtd, sets); |
620 | ||
e0c7d767 | 621 | nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1); |
1da177e4 LT |
622 | |
623 | if (nmtd->scan_res == 0) { | |
624 | s3c2410_nand_add_partition(info, nmtd, sets); | |
625 | } | |
626 | ||
627 | if (sets != NULL) | |
628 | sets++; | |
629 | } | |
61b03bd7 | 630 | |
1da177e4 LT |
631 | pr_debug("initialised ok\n"); |
632 | return 0; | |
633 | ||
634 | exit_error: | |
3ae5eaec | 635 | s3c2410_nand_remove(pdev); |
1da177e4 LT |
636 | |
637 | if (err == 0) | |
638 | err = -EINVAL; | |
639 | return err; | |
640 | } | |
641 | ||
a4f957f1 BD |
642 | /* driver device registration */ |
643 | ||
3ae5eaec | 644 | static int s3c2410_nand_probe(struct platform_device *dev) |
a4f957f1 BD |
645 | { |
646 | return s3c24xx_nand_probe(dev, 0); | |
647 | } | |
648 | ||
3ae5eaec | 649 | static int s3c2440_nand_probe(struct platform_device *dev) |
a4f957f1 BD |
650 | { |
651 | return s3c24xx_nand_probe(dev, 1); | |
652 | } | |
653 | ||
3ae5eaec | 654 | static struct platform_driver s3c2410_nand_driver = { |
1da177e4 LT |
655 | .probe = s3c2410_nand_probe, |
656 | .remove = s3c2410_nand_remove, | |
3ae5eaec RK |
657 | .driver = { |
658 | .name = "s3c2410-nand", | |
659 | .owner = THIS_MODULE, | |
660 | }, | |
1da177e4 LT |
661 | }; |
662 | ||
3ae5eaec | 663 | static struct platform_driver s3c2440_nand_driver = { |
a4f957f1 BD |
664 | .probe = s3c2440_nand_probe, |
665 | .remove = s3c2410_nand_remove, | |
3ae5eaec RK |
666 | .driver = { |
667 | .name = "s3c2440-nand", | |
668 | .owner = THIS_MODULE, | |
669 | }, | |
a4f957f1 BD |
670 | }; |
671 | ||
1da177e4 LT |
672 | static int __init s3c2410_nand_init(void) |
673 | { | |
a4f957f1 BD |
674 | printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n"); |
675 | ||
3ae5eaec RK |
676 | platform_driver_register(&s3c2440_nand_driver); |
677 | return platform_driver_register(&s3c2410_nand_driver); | |
1da177e4 LT |
678 | } |
679 | ||
680 | static void __exit s3c2410_nand_exit(void) | |
681 | { | |
3ae5eaec RK |
682 | platform_driver_unregister(&s3c2440_nand_driver); |
683 | platform_driver_unregister(&s3c2410_nand_driver); | |
1da177e4 LT |
684 | } |
685 | ||
686 | module_init(s3c2410_nand_init); | |
687 | module_exit(s3c2410_nand_exit); | |
688 | ||
689 | MODULE_LICENSE("GPL"); | |
690 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
a4f957f1 | 691 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |