[deliverable/linux.git] / drivers / mtd / nand / sharpsl.c

/*
 * drivers/mtd/nand/sharpsl.c
 *
 *  Copyright (C) 2004 Richard Purdie
 *
 *  $Id: sharpsl.c,v 1.7 2005/11/07 11:14:31 gleixner Exp $
 *
 *  Based on Sharp's NAND driver sharp_sl.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/genhd.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>

static void __iomem *sharpsl_io_base;
static int sharpsl_phys_base = 0x0C000000;

/* register offset */
#define ECCLPLB	 	sharpsl_io_base+0x00	/* line parity 7 - 0 bit */
#define ECCLPUB	 	sharpsl_io_base+0x04	/* line parity 15 - 8 bit */
#define ECCCP	   	sharpsl_io_base+0x08	/* column parity 5 - 0 bit */
#define ECCCNTR	 	sharpsl_io_base+0x0C	/* ECC byte counter */
#define ECCCLRR	 	sharpsl_io_base+0x10	/* cleare ECC */
#define FLASHIO	 	sharpsl_io_base+0x14	/* Flash I/O */
#define FLASHCTL	sharpsl_io_base+0x18	/* Flash Control */

/* Flash control bit */
#define FLRYBY		(1 << 5)
#define FLCE1		(1 << 4)
#define FLWP		(1 << 3)
#define FLALE		(1 << 2)
#define FLCLE		(1 << 1)
#define FLCE0		(1 << 0)

/*
 * MTD structure for SharpSL
 */
static struct mtd_info *sharpsl_mtd = NULL;

/*
 * Define partitions for flash device
 */
#define DEFAULT_NUM_PARTITIONS 3

static int nr_partitions;
static struct mtd_partition sharpsl_nand_default_partition_info[] = {
	{
	 .name = "System Area",
	 .offset = 0,
	 .size = 7 * 1024 * 1024,
	 },
	{
	 .name = "Root Filesystem",
	 .offset = 7 * 1024 * 1024,
	 .size = 30 * 1024 * 1024,
	 },
	{
	 .name = "Home Filesystem",
	 .offset = MTDPART_OFS_APPEND,
	 .size = MTDPART_SIZ_FULL,
	 },
};

/*
 *	hardware specific access to control-lines
 */
static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
	switch (cmd) {
	case NAND_CTL_SETCLE:
		writeb(readb(FLASHCTL) | FLCLE, FLASHCTL);
		break;
	case NAND_CTL_CLRCLE:
		writeb(readb(FLASHCTL) & ~FLCLE, FLASHCTL);
		break;

	case NAND_CTL_SETALE:
		writeb(readb(FLASHCTL) | FLALE, FLASHCTL);
		break;
	case NAND_CTL_CLRALE:
		writeb(readb(FLASHCTL) & ~FLALE, FLASHCTL);
		break;

	case NAND_CTL_SETNCE:
		writeb(readb(FLASHCTL) & ~(FLCE0 | FLCE1), FLASHCTL);
		break;
	case NAND_CTL_CLRNCE:
		writeb(readb(FLASHCTL) | (FLCE0 | FLCE1), FLASHCTL);
		break;
	}
}

static uint8_t scan_ff_pattern[] = { 0xff, 0xff };

static struct nand_bbt_descr sharpsl_bbt = {
	.options = 0,
	.offs = 4,
	.len = 2,
	.pattern = scan_ff_pattern
};

static struct nand_bbt_descr sharpsl_akita_bbt = {
	.options = 0,
	.offs = 4,
	.len = 1,
	.pattern = scan_ff_pattern
};

static struct nand_oobinfo akita_oobinfo = {
	.useecc = MTD_NANDECC_AUTOPLACE,
	.eccbytes = 24,
	.eccpos = {
		   0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
		   0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
		   0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
	.oobfree = {{0x08, 0x09}}
};

static int sharpsl_nand_dev_ready(struct mtd_info *mtd)
{
	return !((readb(FLASHCTL) & FLRYBY) == 0);
}

static void sharpsl_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
	writeb(0, ECCCLRR);
}

static int sharpsl_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code)
{
	ecc_code[0] = ~readb(ECCLPUB);
	ecc_code[1] = ~readb(ECCLPLB);
	ecc_code[2] = (~readb(ECCCP) << 2) | 0x03;
	return readb(ECCCNTR) != 0;
}

#ifdef CONFIG_MTD_PARTITIONS
const char *part_probes[] = { "cmdlinepart", NULL };
#endif

/*
 * Main initialization routine
 */
int __init sharpsl_nand_init(void)
{
	struct nand_chip *this;
	struct mtd_partition *sharpsl_partition_info;
	int err = 0;

	/* Allocate memory for MTD device structure and private data */
	sharpsl_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
	if (!sharpsl_mtd) {
		printk("Unable to allocate SharpSL NAND MTD device structure.\n");
		return -ENOMEM;
	}

	/* map physical adress */
	sharpsl_io_base = ioremap(sharpsl_phys_base, 0x1000);
	if (!sharpsl_io_base) {
		printk("ioremap to access Sharp SL NAND chip failed\n");
		kfree(sharpsl_mtd);
		return -EIO;
	}

	/* Get pointer to private data */
	this = (struct nand_chip *)(&sharpsl_mtd[1]);

	/* Initialize structures */
	memset(sharpsl_mtd, 0, sizeof(struct mtd_info));
	memset(this, 0, sizeof(struct nand_chip));

	/* Link the private data with the MTD structure */
	sharpsl_mtd->priv = this;
	sharpsl_mtd->owner = THIS_MODULE;

	/*
	 * PXA initialize
	 */
	writeb(readb(FLASHCTL) | FLWP, FLASHCTL);

	/* Set address of NAND IO lines */
	this->IO_ADDR_R = FLASHIO;
	this->IO_ADDR_W = FLASHIO;
	/* Set address of hardware control function */
	this->hwcontrol = sharpsl_nand_hwcontrol;
	this->dev_ready = sharpsl_nand_dev_ready;
	/* 15 us command delay time */
	this->chip_delay = 15;
	/* set eccmode using hardware ECC */
	this->eccmode = NAND_ECC_HW3_256;
	this->badblock_pattern = &sharpsl_bbt;
	if (machine_is_akita() || machine_is_borzoi()) {
		this->badblock_pattern = &sharpsl_akita_bbt;
		this->autooob = &akita_oobinfo;
	}
	this->enable_hwecc = sharpsl_nand_enable_hwecc;
	this->calculate_ecc = sharpsl_nand_calculate_ecc;
	this->correct_data = nand_correct_data;

	/* Scan to find existence of the device */
	err = nand_scan(sharpsl_mtd, 1);
	if (err) {
		iounmap(sharpsl_io_base);
		kfree(sharpsl_mtd);
		return err;
	}

	/* Register the partitions */
	sharpsl_mtd->name = "sharpsl-nand";
	nr_partitions = parse_mtd_partitions(sharpsl_mtd, part_probes, &sharpsl_partition_info, 0);

	if (nr_partitions <= 0) {
		nr_partitions = DEFAULT_NUM_PARTITIONS;
		sharpsl_partition_info = sharpsl_nand_default_partition_info;
		if (machine_is_poodle()) {
			sharpsl_partition_info[1].size = 22 * 1024 * 1024;
		} else if (machine_is_corgi() || machine_is_shepherd()) {
			sharpsl_partition_info[1].size = 25 * 1024 * 1024;
		} else if (machine_is_husky()) {
			sharpsl_partition_info[1].size = 53 * 1024 * 1024;
		} else if (machine_is_spitz()) {
			sharpsl_partition_info[1].size = 5 * 1024 * 1024;
		} else if (machine_is_akita()) {
			sharpsl_partition_info[1].size = 58 * 1024 * 1024;
		} else if (machine_is_borzoi()) {
			sharpsl_partition_info[1].size = 32 * 1024 * 1024;
		}
	}

	if (machine_is_husky() || machine_is_borzoi() || machine_is_akita()) {
		/* Need to use small eraseblock size for backward compatibility */
		sharpsl_mtd->flags |= MTD_NO_VIRTBLOCKS;
	}

	add_mtd_partitions(sharpsl_mtd, sharpsl_partition_info, nr_partitions);

	/* Return happy */
	return 0;
}

module_init(sharpsl_nand_init);

/*
 * Clean up routine
 */
#ifdef MODULE
static void __exit sharpsl_nand_cleanup(void)
{
	struct nand_chip *this = (struct nand_chip *)&sharpsl_mtd[1];

	/* Release resources, unregister device */
	nand_release(sharpsl_mtd);

	iounmap(sharpsl_io_base);

	/* Free the MTD device structure */
	kfree(sharpsl_mtd);
}

module_exit(sharpsl_nand_cleanup);
#endif

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/mtd/nand/sharpsl.c
	3	*
	4	* Copyright (C) 2004 Richard Purdie
	5	*
61b03bd7	6	* $Id: sharpsl.c,v 1.7 2005/11/07 11:14:31 gleixner Exp $
1da177e4 LT	7	*
	8	* Based on Sharp's NAND driver sharp_sl.c
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	*/
	15
	16	#include <linux/genhd.h>
	17	#include <linux/slab.h>
	18	#include <linux/module.h>
	19	#include <linux/delay.h>
	20	#include <linux/mtd/mtd.h>
	21	#include <linux/mtd/nand.h>
	22	#include <linux/mtd/nand_ecc.h>
	23	#include <linux/mtd/partitions.h>
	24	#include <linux/interrupt.h>
	25	#include <asm/io.h>
	26	#include <asm/hardware.h>
	27	#include <asm/mach-types.h>
	28
	29	static void __iomem *sharpsl_io_base;
	30	static int sharpsl_phys_base = 0x0C000000;
	31
	32	/* register offset */
	33	#define ECCLPLB sharpsl_io_base+0x00 /* line parity 7 - 0 bit */
	34	#define ECCLPUB sharpsl_io_base+0x04 /* line parity 15 - 8 bit */
	35	#define ECCCP sharpsl_io_base+0x08 /* column parity 5 - 0 bit */
	36	#define ECCCNTR sharpsl_io_base+0x0C /* ECC byte counter */
	37	#define ECCCLRR sharpsl_io_base+0x10 /* cleare ECC */
	38	#define FLASHIO sharpsl_io_base+0x14 /* Flash I/O */
	39	#define FLASHCTL sharpsl_io_base+0x18 /* Flash Control */
	40
	41	/* Flash control bit */
	42	#define FLRYBY (1 << 5)
	43	#define FLCE1 (1 << 4)
	44	#define FLWP (1 << 3)
	45	#define FLALE (1 << 2)
	46	#define FLCLE (1 << 1)
	47	#define FLCE0 (1 << 0)
	48
1da177e4 LT	49	/*
	50	* MTD structure for SharpSL
	51	*/
	52	static struct mtd_info *sharpsl_mtd = NULL;
	53
	54	/*
	55	* Define partitions for flash device
	56	*/
	57	#define DEFAULT_NUM_PARTITIONS 3
	58
	59	static int nr_partitions;
	60	static struct mtd_partition sharpsl_nand_default_partition_info[] = {
	61	{
e0c7d767 DW	62	.name = "System Area",
	63	.offset = 0,
	64	.size = 7 * 1024 * 1024,
	65	},
1da177e4	66	{
e0c7d767 DW	67	.name = "Root Filesystem",
	68	.offset = 7 * 1024 * 1024,
	69	.size = 30 * 1024 * 1024,
	70	},
1da177e4	71	{
e0c7d767 DW	72	.name = "Home Filesystem",
	73	.offset = MTDPART_OFS_APPEND,
	74	.size = MTDPART_SIZ_FULL,
	75	},
1da177e4 LT	76	};
1da177e4 LT	77
61b03bd7	78	/*
1da177e4 LT	79	* hardware specific access to control-lines
1da177e4 LT	80	*/
e0c7d767	81	static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd)
1da177e4 LT	82	{
1da177e4 LT	83	switch (cmd) {
61b03bd7	84	case NAND_CTL_SETCLE:
1da177e4 LT	85	writeb(readb(FLASHCTL) \| FLCLE, FLASHCTL);
	86	break;
	87	case NAND_CTL_CLRCLE:
	88	writeb(readb(FLASHCTL) & ~FLCLE, FLASHCTL);
	89	break;
	90
	91	case NAND_CTL_SETALE:
	92	writeb(readb(FLASHCTL) \| FLALE, FLASHCTL);
	93	break;
	94	case NAND_CTL_CLRALE:
	95	writeb(readb(FLASHCTL) & ~FLALE, FLASHCTL);
	96	break;
	97
61b03bd7	98	case NAND_CTL_SETNCE:
e0c7d767	99	writeb(readb(FLASHCTL) & ~(FLCE0 \| FLCE1), FLASHCTL);
1da177e4	100	break;
61b03bd7	101	case NAND_CTL_CLRNCE:
e0c7d767	102	writeb(readb(FLASHCTL) \| (FLCE0 \| FLCE1), FLASHCTL);
1da177e4 LT	103	break;
	104	}
	105	}
	106
	107	static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
	108
	109	static struct nand_bbt_descr sharpsl_bbt = {
	110	.options = 0,
	111	.offs = 4,
	112	.len = 2,
	113	.pattern = scan_ff_pattern
	114	};
	115
87c146dc RP	116	static struct nand_bbt_descr sharpsl_akita_bbt = {
	117	.options = 0,
	118	.offs = 4,
	119	.len = 1,
	120	.pattern = scan_ff_pattern
	121	};
	122
	123	static struct nand_oobinfo akita_oobinfo = {
	124	.useecc = MTD_NANDECC_AUTOPLACE,
	125	.eccbytes = 24,
	126	.eccpos = {
e0c7d767 DW	127	0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
	128	0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
	129	0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
	130	.oobfree = {{0x08, 0x09}}
87c146dc RP	131	};
87c146dc RP	132
e0c7d767	133	static int sharpsl_nand_dev_ready(struct mtd_info *mtd)
1da177e4 LT	134	{
	135	return !((readb(FLASHCTL) & FLRYBY) == 0);
	136	}
	137
e0c7d767	138	static void sharpsl_nand_enable_hwecc(struct mtd_info *mtd, int mode)
1da177e4	139	{
e0c7d767	140	writeb(0, ECCCLRR);
1da177e4 LT	141	}
1da177e4 LT	142
e0c7d767	143	static int sharpsl_nand_calculate_ecc(struct mtd_info mtd, const u_char dat, u_char * ecc_code)
1da177e4 LT	144	{
	145	ecc_code[0] = ~readb(ECCLPUB);
	146	ecc_code[1] = ~readb(ECCLPLB);
	147	ecc_code[2] = (~readb(ECCCP) << 2) \| 0x03;
	148	return readb(ECCCNTR) != 0;
	149	}
	150
1da177e4 LT	151	#ifdef CONFIG_MTD_PARTITIONS
	152	const char *part_probes[] = { "cmdlinepart", NULL };
	153	#endif
	154
1da177e4 LT	155	/*
	156	* Main initialization routine
	157	*/
e0c7d767	158	int __init sharpsl_nand_init(void)
1da177e4 LT	159	{
1da177e4 LT	160	struct nand_chip *this;
e0c7d767	161	struct mtd_partition *sharpsl_partition_info;
1da177e4 LT	162	int err = 0;
	163
	164	/* Allocate memory for MTD device structure and private data */
e0c7d767	165	sharpsl_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
1da177e4	166	if (!sharpsl_mtd) {
e0c7d767	167	printk("Unable to allocate SharpSL NAND MTD device structure.\n");
1da177e4 LT	168	return -ENOMEM;
1da177e4 LT	169	}
61b03bd7	170
1da177e4 LT	171	/* map physical adress */
1da177e4 LT	172	sharpsl_io_base = ioremap(sharpsl_phys_base, 0x1000);
e0c7d767	173	if (!sharpsl_io_base) {
1da177e4 LT	174	printk("ioremap to access Sharp SL NAND chip failed\n");
	175	kfree(sharpsl_mtd);
	176	return -EIO;
	177	}
61b03bd7	178
1da177e4	179	/* Get pointer to private data */
e0c7d767	180	this = (struct nand_chip *)(&sharpsl_mtd[1]);
1da177e4 LT	181
1da177e4 LT	182	/* Initialize structures */
e0c7d767 DW	183	memset(sharpsl_mtd, 0, sizeof(struct mtd_info));
e0c7d767 DW	184	memset(this, 0, sizeof(struct nand_chip));
1da177e4 LT	185
	186	/* Link the private data with the MTD structure */
	187	sharpsl_mtd->priv = this;
552d9205	188	sharpsl_mtd->owner = THIS_MODULE;
1da177e4 LT	189
	190	/*
	191	* PXA initialize
	192	*/
	193	writeb(readb(FLASHCTL) \| FLWP, FLASHCTL);
	194
	195	/* Set address of NAND IO lines */
	196	this->IO_ADDR_R = FLASHIO;
	197	this->IO_ADDR_W = FLASHIO;
	198	/* Set address of hardware control function */
	199	this->hwcontrol = sharpsl_nand_hwcontrol;
	200	this->dev_ready = sharpsl_nand_dev_ready;
	201	/* 15 us command delay time */
	202	this->chip_delay = 15;
	203	/* set eccmode using hardware ECC */
	204	this->eccmode = NAND_ECC_HW3_256;
61b03bd7	205	this->badblock_pattern = &sharpsl_bbt;
87c146dc RP	206	if (machine_is_akita() \|\| machine_is_borzoi()) {
	207	this->badblock_pattern = &sharpsl_akita_bbt;
	208	this->autooob = &akita_oobinfo;
	209	}
1da177e4 LT	210	this->enable_hwecc = sharpsl_nand_enable_hwecc;
	211	this->calculate_ecc = sharpsl_nand_calculate_ecc;
	212	this->correct_data = nand_correct_data;
1da177e4 LT	213
1da177e4 LT	214	/* Scan to find existence of the device */
e0c7d767	215	err = nand_scan(sharpsl_mtd, 1);
1da177e4 LT	216	if (err) {
	217	iounmap(sharpsl_io_base);
	218	kfree(sharpsl_mtd);
	219	return err;
	220	}
	221
	222	/* Register the partitions */
	223	sharpsl_mtd->name = "sharpsl-nand";
e0c7d767	224	nr_partitions = parse_mtd_partitions(sharpsl_mtd, part_probes, &sharpsl_partition_info, 0);
61b03bd7	225
1da177e4 LT	226	if (nr_partitions <= 0) {
	227	nr_partitions = DEFAULT_NUM_PARTITIONS;
	228	sharpsl_partition_info = sharpsl_nand_default_partition_info;
	229	if (machine_is_poodle()) {
e0c7d767	230	sharpsl_partition_info[1].size = 22 * 1024 * 1024;
1da177e4	231	} else if (machine_is_corgi() \|\| machine_is_shepherd()) {
e0c7d767	232	sharpsl_partition_info[1].size = 25 * 1024 * 1024;
1da177e4	233	} else if (machine_is_husky()) {
e0c7d767	234	sharpsl_partition_info[1].size = 53 * 1024 * 1024;
62052d42	235	} else if (machine_is_spitz()) {
e0c7d767	236	sharpsl_partition_info[1].size = 5 * 1024 * 1024;
62052d42	237	} else if (machine_is_akita()) {
e0c7d767	238	sharpsl_partition_info[1].size = 58 * 1024 * 1024;
62052d42	239	} else if (machine_is_borzoi()) {
e0c7d767	240	sharpsl_partition_info[1].size = 32 * 1024 * 1024;
62052d42	241	}
1da177e4 LT	242	}
1da177e4 LT	243
87c146dc	244	if (machine_is_husky() \|\| machine_is_borzoi() \|\| machine_is_akita()) {
1da177e4 LT	245	/* Need to use small eraseblock size for backward compatibility */
	246	sharpsl_mtd->flags \|= MTD_NO_VIRTBLOCKS;
	247	}
	248
	249	add_mtd_partitions(sharpsl_mtd, sharpsl_partition_info, nr_partitions);
	250
	251	/* Return happy */
	252	return 0;
	253	}
e0c7d767	254
1da177e4 LT	255	module_init(sharpsl_nand_init);
	256
	257	/*
	258	* Clean up routine
	259	*/
	260	#ifdef MODULE
	261	static void __exit sharpsl_nand_cleanup(void)
	262	{
e0c7d767	263	struct nand_chip this = (struct nand_chip )&sharpsl_mtd[1];
1da177e4 LT	264
	265	/* Release resources, unregister device */
	266	nand_release(sharpsl_mtd);
	267
	268	iounmap(sharpsl_io_base);
	269
	270	/* Free the MTD device structure */
	271	kfree(sharpsl_mtd);
	272	}
e0c7d767	273
1da177e4 LT	274	module_exit(sharpsl_nand_cleanup);
	275	#endif
	276
	277	MODULE_LICENSE("GPL");
	278	MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
	279	MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series");