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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand/sharpsl.c | |
3 | * | |
4 | * Copyright (C) 2004 Richard Purdie | |
5 | * | |
87c146dc | 6 | * $Id: sharpsl.c,v 1.6 2005/11/03 11:36:42 rpurdie Exp $ |
1da177e4 LT |
7 | * |
8 | * Based on Sharp's NAND driver sharp_sl.c | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/genhd.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/mtd/mtd.h> | |
21 | #include <linux/mtd/nand.h> | |
22 | #include <linux/mtd/nand_ecc.h> | |
23 | #include <linux/mtd/partitions.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <asm/io.h> | |
26 | #include <asm/hardware.h> | |
27 | #include <asm/mach-types.h> | |
28 | ||
29 | static void __iomem *sharpsl_io_base; | |
30 | static int sharpsl_phys_base = 0x0C000000; | |
31 | ||
32 | /* register offset */ | |
33 | #define ECCLPLB sharpsl_io_base+0x00 /* line parity 7 - 0 bit */ | |
34 | #define ECCLPUB sharpsl_io_base+0x04 /* line parity 15 - 8 bit */ | |
35 | #define ECCCP sharpsl_io_base+0x08 /* column parity 5 - 0 bit */ | |
36 | #define ECCCNTR sharpsl_io_base+0x0C /* ECC byte counter */ | |
37 | #define ECCCLRR sharpsl_io_base+0x10 /* cleare ECC */ | |
38 | #define FLASHIO sharpsl_io_base+0x14 /* Flash I/O */ | |
39 | #define FLASHCTL sharpsl_io_base+0x18 /* Flash Control */ | |
40 | ||
41 | /* Flash control bit */ | |
42 | #define FLRYBY (1 << 5) | |
43 | #define FLCE1 (1 << 4) | |
44 | #define FLWP (1 << 3) | |
45 | #define FLALE (1 << 2) | |
46 | #define FLCLE (1 << 1) | |
47 | #define FLCE0 (1 << 0) | |
48 | ||
49 | ||
50 | /* | |
51 | * MTD structure for SharpSL | |
52 | */ | |
53 | static struct mtd_info *sharpsl_mtd = NULL; | |
54 | ||
55 | /* | |
56 | * Define partitions for flash device | |
57 | */ | |
58 | #define DEFAULT_NUM_PARTITIONS 3 | |
59 | ||
60 | static int nr_partitions; | |
61 | static struct mtd_partition sharpsl_nand_default_partition_info[] = { | |
62 | { | |
63 | .name = "System Area", | |
64 | .offset = 0, | |
65 | .size = 7 * 1024 * 1024, | |
66 | }, | |
67 | { | |
68 | .name = "Root Filesystem", | |
69 | .offset = 7 * 1024 * 1024, | |
70 | .size = 30 * 1024 * 1024, | |
71 | }, | |
72 | { | |
73 | .name = "Home Filesystem", | |
74 | .offset = MTDPART_OFS_APPEND , | |
75 | .size = MTDPART_SIZ_FULL , | |
76 | }, | |
77 | }; | |
78 | ||
79 | /* | |
80 | * hardware specific access to control-lines | |
81 | */ | |
82 | static void | |
83 | sharpsl_nand_hwcontrol(struct mtd_info* mtd, int cmd) | |
84 | { | |
85 | switch (cmd) { | |
86 | case NAND_CTL_SETCLE: | |
87 | writeb(readb(FLASHCTL) | FLCLE, FLASHCTL); | |
88 | break; | |
89 | case NAND_CTL_CLRCLE: | |
90 | writeb(readb(FLASHCTL) & ~FLCLE, FLASHCTL); | |
91 | break; | |
92 | ||
93 | case NAND_CTL_SETALE: | |
94 | writeb(readb(FLASHCTL) | FLALE, FLASHCTL); | |
95 | break; | |
96 | case NAND_CTL_CLRALE: | |
97 | writeb(readb(FLASHCTL) & ~FLALE, FLASHCTL); | |
98 | break; | |
99 | ||
100 | case NAND_CTL_SETNCE: | |
101 | writeb(readb(FLASHCTL) & ~(FLCE0|FLCE1), FLASHCTL); | |
102 | break; | |
103 | case NAND_CTL_CLRNCE: | |
104 | writeb(readb(FLASHCTL) | (FLCE0|FLCE1), FLASHCTL); | |
105 | break; | |
106 | } | |
107 | } | |
108 | ||
109 | static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; | |
110 | ||
111 | static struct nand_bbt_descr sharpsl_bbt = { | |
112 | .options = 0, | |
113 | .offs = 4, | |
114 | .len = 2, | |
115 | .pattern = scan_ff_pattern | |
116 | }; | |
117 | ||
87c146dc RP |
118 | static struct nand_bbt_descr sharpsl_akita_bbt = { |
119 | .options = 0, | |
120 | .offs = 4, | |
121 | .len = 1, | |
122 | .pattern = scan_ff_pattern | |
123 | }; | |
124 | ||
125 | static struct nand_oobinfo akita_oobinfo = { | |
126 | .useecc = MTD_NANDECC_AUTOPLACE, | |
127 | .eccbytes = 24, | |
128 | .eccpos = { | |
129 | 0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11, | |
130 | 0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23, | |
131 | 0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37}, | |
132 | .oobfree = { {0x08, 0x09} } | |
133 | }; | |
134 | ||
1da177e4 LT |
135 | static int |
136 | sharpsl_nand_dev_ready(struct mtd_info* mtd) | |
137 | { | |
138 | return !((readb(FLASHCTL) & FLRYBY) == 0); | |
139 | } | |
140 | ||
141 | static void | |
142 | sharpsl_nand_enable_hwecc(struct mtd_info* mtd, int mode) | |
143 | { | |
144 | writeb(0 ,ECCCLRR); | |
145 | } | |
146 | ||
147 | static int | |
148 | sharpsl_nand_calculate_ecc(struct mtd_info* mtd, const u_char* dat, | |
149 | u_char* ecc_code) | |
150 | { | |
151 | ecc_code[0] = ~readb(ECCLPUB); | |
152 | ecc_code[1] = ~readb(ECCLPLB); | |
153 | ecc_code[2] = (~readb(ECCCP) << 2) | 0x03; | |
154 | return readb(ECCCNTR) != 0; | |
155 | } | |
156 | ||
157 | ||
158 | #ifdef CONFIG_MTD_PARTITIONS | |
159 | const char *part_probes[] = { "cmdlinepart", NULL }; | |
160 | #endif | |
161 | ||
162 | ||
163 | /* | |
164 | * Main initialization routine | |
165 | */ | |
166 | int __init | |
167 | sharpsl_nand_init(void) | |
168 | { | |
169 | struct nand_chip *this; | |
170 | struct mtd_partition* sharpsl_partition_info; | |
171 | int err = 0; | |
172 | ||
173 | /* Allocate memory for MTD device structure and private data */ | |
174 | sharpsl_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), | |
175 | GFP_KERNEL); | |
176 | if (!sharpsl_mtd) { | |
177 | printk ("Unable to allocate SharpSL NAND MTD device structure.\n"); | |
178 | return -ENOMEM; | |
179 | } | |
180 | ||
181 | /* map physical adress */ | |
182 | sharpsl_io_base = ioremap(sharpsl_phys_base, 0x1000); | |
183 | if(!sharpsl_io_base){ | |
184 | printk("ioremap to access Sharp SL NAND chip failed\n"); | |
185 | kfree(sharpsl_mtd); | |
186 | return -EIO; | |
187 | } | |
188 | ||
189 | /* Get pointer to private data */ | |
190 | this = (struct nand_chip *) (&sharpsl_mtd[1]); | |
191 | ||
192 | /* Initialize structures */ | |
193 | memset((char *) sharpsl_mtd, 0, sizeof(struct mtd_info)); | |
194 | memset((char *) this, 0, sizeof(struct nand_chip)); | |
195 | ||
196 | /* Link the private data with the MTD structure */ | |
197 | sharpsl_mtd->priv = this; | |
198 | ||
199 | /* | |
200 | * PXA initialize | |
201 | */ | |
202 | writeb(readb(FLASHCTL) | FLWP, FLASHCTL); | |
203 | ||
204 | /* Set address of NAND IO lines */ | |
205 | this->IO_ADDR_R = FLASHIO; | |
206 | this->IO_ADDR_W = FLASHIO; | |
207 | /* Set address of hardware control function */ | |
208 | this->hwcontrol = sharpsl_nand_hwcontrol; | |
209 | this->dev_ready = sharpsl_nand_dev_ready; | |
210 | /* 15 us command delay time */ | |
211 | this->chip_delay = 15; | |
212 | /* set eccmode using hardware ECC */ | |
213 | this->eccmode = NAND_ECC_HW3_256; | |
87c146dc RP |
214 | this->badblock_pattern = &sharpsl_bbt; |
215 | if (machine_is_akita() || machine_is_borzoi()) { | |
216 | this->badblock_pattern = &sharpsl_akita_bbt; | |
217 | this->autooob = &akita_oobinfo; | |
218 | } | |
1da177e4 LT |
219 | this->enable_hwecc = sharpsl_nand_enable_hwecc; |
220 | this->calculate_ecc = sharpsl_nand_calculate_ecc; | |
221 | this->correct_data = nand_correct_data; | |
1da177e4 LT |
222 | |
223 | /* Scan to find existence of the device */ | |
224 | err=nand_scan(sharpsl_mtd,1); | |
225 | if (err) { | |
226 | iounmap(sharpsl_io_base); | |
227 | kfree(sharpsl_mtd); | |
228 | return err; | |
229 | } | |
230 | ||
231 | /* Register the partitions */ | |
232 | sharpsl_mtd->name = "sharpsl-nand"; | |
233 | nr_partitions = parse_mtd_partitions(sharpsl_mtd, part_probes, | |
234 | &sharpsl_partition_info, 0); | |
235 | ||
236 | if (nr_partitions <= 0) { | |
237 | nr_partitions = DEFAULT_NUM_PARTITIONS; | |
238 | sharpsl_partition_info = sharpsl_nand_default_partition_info; | |
239 | if (machine_is_poodle()) { | |
7ba48c45 | 240 | sharpsl_partition_info[1].size=30 * 1024 * 1024; |
1da177e4 LT |
241 | } else if (machine_is_corgi() || machine_is_shepherd()) { |
242 | sharpsl_partition_info[1].size=25 * 1024 * 1024; | |
243 | } else if (machine_is_husky()) { | |
244 | sharpsl_partition_info[1].size=53 * 1024 * 1024; | |
62052d42 RP |
245 | } else if (machine_is_spitz()) { |
246 | sharpsl_partition_info[1].size=5 * 1024 * 1024; | |
247 | } else if (machine_is_akita()) { | |
248 | sharpsl_partition_info[1].size=58 * 1024 * 1024; | |
249 | } else if (machine_is_borzoi()) { | |
250 | sharpsl_partition_info[1].size=32 * 1024 * 1024; | |
251 | } | |
1da177e4 LT |
252 | } |
253 | ||
87c146dc | 254 | if (machine_is_husky() || machine_is_borzoi() || machine_is_akita()) { |
1da177e4 LT |
255 | /* Need to use small eraseblock size for backward compatibility */ |
256 | sharpsl_mtd->flags |= MTD_NO_VIRTBLOCKS; | |
257 | } | |
258 | ||
259 | add_mtd_partitions(sharpsl_mtd, sharpsl_partition_info, nr_partitions); | |
260 | ||
261 | /* Return happy */ | |
262 | return 0; | |
263 | } | |
264 | module_init(sharpsl_nand_init); | |
265 | ||
266 | /* | |
267 | * Clean up routine | |
268 | */ | |
269 | #ifdef MODULE | |
270 | static void __exit sharpsl_nand_cleanup(void) | |
271 | { | |
272 | struct nand_chip *this = (struct nand_chip *) &sharpsl_mtd[1]; | |
273 | ||
274 | /* Release resources, unregister device */ | |
275 | nand_release(sharpsl_mtd); | |
276 | ||
277 | iounmap(sharpsl_io_base); | |
278 | ||
279 | /* Free the MTD device structure */ | |
280 | kfree(sharpsl_mtd); | |
281 | } | |
282 | module_exit(sharpsl_nand_cleanup); | |
283 | #endif | |
284 | ||
285 | MODULE_LICENSE("GPL"); | |
286 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
287 | MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series"); |