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ec43b816 IM |
1 | /* |
2 | * Toshiba TMIO NAND flash controller driver | |
3 | * | |
4 | * Slightly murky pre-git history of the driver: | |
5 | * | |
6 | * Copyright (c) Ian Molton 2004, 2005, 2008 | |
25985edc | 7 | * Original work, independent of sharps code. Included hardware ECC support. |
ec43b816 IM |
8 | * Hard ECC did not work for writes in the early revisions. |
9 | * Copyright (c) Dirk Opfer 2005. | |
10 | * Modifications developed from sharps code but | |
11 | * NOT containing any, ported onto Ians base. | |
12 | * Copyright (c) Chris Humbert 2005 | |
13 | * Copyright (c) Dmitry Baryshkov 2008 | |
14 | * Minor fixes | |
15 | * | |
16 | * Parts copyright Sebastian Carlier | |
17 | * | |
18 | * This file is licensed under | |
19 | * the terms of the GNU General Public License version 2. This program | |
20 | * is licensed "as is" without any warranty of any kind, whether express | |
21 | * or implied. | |
22 | * | |
23 | */ | |
24 | ||
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/mfd/core.h> | |
30 | #include <linux/mfd/tmio.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/irq.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/mtd/mtd.h> | |
37 | #include <linux/mtd/nand.h> | |
38 | #include <linux/mtd/nand_ecc.h> | |
39 | #include <linux/mtd/partitions.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
ec43b816 IM |
41 | |
42 | /*--------------------------------------------------------------------------*/ | |
43 | ||
44 | /* | |
45 | * NAND Flash Host Controller Configuration Register | |
46 | */ | |
47 | #define CCR_COMMAND 0x04 /* w Command */ | |
48 | #define CCR_BASE 0x10 /* l NAND Flash Control Reg Base Addr */ | |
49 | #define CCR_INTP 0x3d /* b Interrupt Pin */ | |
50 | #define CCR_INTE 0x48 /* b Interrupt Enable */ | |
51 | #define CCR_EC 0x4a /* b Event Control */ | |
52 | #define CCR_ICC 0x4c /* b Internal Clock Control */ | |
53 | #define CCR_ECCC 0x5b /* b ECC Control */ | |
54 | #define CCR_NFTC 0x60 /* b NAND Flash Transaction Control */ | |
55 | #define CCR_NFM 0x61 /* b NAND Flash Monitor */ | |
56 | #define CCR_NFPSC 0x62 /* b NAND Flash Power Supply Control */ | |
57 | #define CCR_NFDC 0x63 /* b NAND Flash Detect Control */ | |
58 | ||
59 | /* | |
60 | * NAND Flash Control Register | |
61 | */ | |
62 | #define FCR_DATA 0x00 /* bwl Data Register */ | |
63 | #define FCR_MODE 0x04 /* b Mode Register */ | |
64 | #define FCR_STATUS 0x05 /* b Status Register */ | |
65 | #define FCR_ISR 0x06 /* b Interrupt Status Register */ | |
66 | #define FCR_IMR 0x07 /* b Interrupt Mask Register */ | |
67 | ||
68 | /* FCR_MODE Register Command List */ | |
69 | #define FCR_MODE_DATA 0x94 /* Data Data_Mode */ | |
70 | #define FCR_MODE_COMMAND 0x95 /* Data Command_Mode */ | |
71 | #define FCR_MODE_ADDRESS 0x96 /* Data Address_Mode */ | |
72 | ||
73 | #define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */ | |
74 | #define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */ | |
75 | #define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */ | |
76 | ||
77 | #define FCR_MODE_POWER_ON 0x0C /* Power Supply ON to SSFDC card */ | |
78 | #define FCR_MODE_POWER_OFF 0x08 /* Power Supply OFF to SSFDC card */ | |
79 | ||
80 | #define FCR_MODE_LED_OFF 0x00 /* LED OFF */ | |
81 | #define FCR_MODE_LED_ON 0x04 /* LED ON */ | |
82 | ||
83 | #define FCR_MODE_EJECT_ON 0x68 /* Ejection events active */ | |
84 | #define FCR_MODE_EJECT_OFF 0x08 /* Ejection events ignored */ | |
85 | ||
86 | #define FCR_MODE_LOCK 0x6C /* Lock_Mode. Eject Switch Invalid */ | |
87 | #define FCR_MODE_UNLOCK 0x0C /* UnLock_Mode. Eject Switch is valid */ | |
88 | ||
89 | #define FCR_MODE_CONTROLLER_ID 0x40 /* Controller ID Read */ | |
90 | #define FCR_MODE_STANDBY 0x00 /* SSFDC card Changes Standby State */ | |
91 | ||
92 | #define FCR_MODE_WE 0x80 | |
93 | #define FCR_MODE_ECC1 0x40 | |
94 | #define FCR_MODE_ECC0 0x20 | |
95 | #define FCR_MODE_CE 0x10 | |
96 | #define FCR_MODE_PCNT1 0x08 | |
97 | #define FCR_MODE_PCNT0 0x04 | |
98 | #define FCR_MODE_ALE 0x02 | |
99 | #define FCR_MODE_CLE 0x01 | |
100 | ||
101 | #define FCR_STATUS_BUSY 0x80 | |
102 | ||
103 | /*--------------------------------------------------------------------------*/ | |
104 | ||
105 | struct tmio_nand { | |
106 | struct mtd_info mtd; | |
107 | struct nand_chip chip; | |
108 | ||
109 | struct platform_device *dev; | |
110 | ||
111 | void __iomem *ccr; | |
112 | void __iomem *fcr; | |
076c7f4c | 113 | unsigned long fcr_base; |
ec43b816 IM |
114 | |
115 | unsigned int irq; | |
116 | ||
117 | /* for tmio_nand_read_byte */ | |
118 | u8 read; | |
119 | unsigned read_good:1; | |
120 | }; | |
121 | ||
122 | #define mtd_to_tmio(m) container_of(m, struct tmio_nand, mtd) | |
123 | ||
ec43b816 IM |
124 | |
125 | /*--------------------------------------------------------------------------*/ | |
126 | ||
127 | static void tmio_nand_hwcontrol(struct mtd_info *mtd, int cmd, | |
128 | unsigned int ctrl) | |
129 | { | |
130 | struct tmio_nand *tmio = mtd_to_tmio(mtd); | |
131 | struct nand_chip *chip = mtd->priv; | |
132 | ||
133 | if (ctrl & NAND_CTRL_CHANGE) { | |
134 | u8 mode; | |
135 | ||
136 | if (ctrl & NAND_NCE) { | |
137 | mode = FCR_MODE_DATA; | |
138 | ||
139 | if (ctrl & NAND_CLE) | |
140 | mode |= FCR_MODE_CLE; | |
141 | else | |
142 | mode &= ~FCR_MODE_CLE; | |
143 | ||
144 | if (ctrl & NAND_ALE) | |
145 | mode |= FCR_MODE_ALE; | |
146 | else | |
147 | mode &= ~FCR_MODE_ALE; | |
148 | } else { | |
149 | mode = FCR_MODE_STANDBY; | |
150 | } | |
151 | ||
152 | tmio_iowrite8(mode, tmio->fcr + FCR_MODE); | |
153 | tmio->read_good = 0; | |
154 | } | |
155 | ||
156 | if (cmd != NAND_CMD_NONE) | |
157 | tmio_iowrite8(cmd, chip->IO_ADDR_W); | |
158 | } | |
159 | ||
160 | static int tmio_nand_dev_ready(struct mtd_info *mtd) | |
161 | { | |
162 | struct tmio_nand *tmio = mtd_to_tmio(mtd); | |
163 | ||
164 | return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY); | |
165 | } | |
166 | ||
167 | static irqreturn_t tmio_irq(int irq, void *__tmio) | |
168 | { | |
169 | struct tmio_nand *tmio = __tmio; | |
170 | struct nand_chip *nand_chip = &tmio->chip; | |
171 | ||
172 | /* disable RDYREQ interrupt */ | |
173 | tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); | |
174 | ||
175 | if (unlikely(!waitqueue_active(&nand_chip->controller->wq))) | |
176 | dev_warn(&tmio->dev->dev, "spurious interrupt\n"); | |
177 | ||
178 | wake_up(&nand_chip->controller->wq); | |
179 | return IRQ_HANDLED; | |
180 | } | |
181 | ||
182 | /* | |
183 | *The TMIO core has a RDYREQ interrupt on the posedge of #SMRB. | |
184 | *This interrupt is normally disabled, but for long operations like | |
185 | *erase and write, we enable it to wake us up. The irq handler | |
186 | *disables the interrupt. | |
187 | */ | |
188 | static int | |
189 | tmio_nand_wait(struct mtd_info *mtd, struct nand_chip *nand_chip) | |
190 | { | |
191 | struct tmio_nand *tmio = mtd_to_tmio(mtd); | |
192 | long timeout; | |
193 | ||
194 | /* enable RDYREQ interrupt */ | |
195 | tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); | |
196 | tmio_iowrite8(0x81, tmio->fcr + FCR_IMR); | |
197 | ||
198 | timeout = wait_event_timeout(nand_chip->controller->wq, | |
199 | tmio_nand_dev_ready(mtd), | |
200 | msecs_to_jiffies(nand_chip->state == FL_ERASING ? 400 : 20)); | |
201 | ||
202 | if (unlikely(!tmio_nand_dev_ready(mtd))) { | |
203 | tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); | |
204 | dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n", | |
205 | nand_chip->state == FL_ERASING ? "erase" : "program", | |
206 | nand_chip->state == FL_ERASING ? 400 : 20); | |
207 | ||
208 | } else if (unlikely(!timeout)) { | |
209 | tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); | |
210 | dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n"); | |
211 | } | |
212 | ||
213 | nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); | |
214 | return nand_chip->read_byte(mtd); | |
215 | } | |
216 | ||
217 | /* | |
218 | *The TMIO controller combines two 8-bit data bytes into one 16-bit | |
219 | *word. This function separates them so nand_base.c works as expected, | |
220 | *especially its NAND_CMD_READID routines. | |
221 | * | |
222 | *To prevent stale data from being read, tmio_nand_hwcontrol() clears | |
223 | *tmio->read_good. | |
224 | */ | |
225 | static u_char tmio_nand_read_byte(struct mtd_info *mtd) | |
226 | { | |
227 | struct tmio_nand *tmio = mtd_to_tmio(mtd); | |
228 | unsigned int data; | |
229 | ||
230 | if (tmio->read_good--) | |
231 | return tmio->read; | |
232 | ||
233 | data = tmio_ioread16(tmio->fcr + FCR_DATA); | |
234 | tmio->read = data >> 8; | |
235 | return data; | |
236 | } | |
237 | ||
238 | /* | |
239 | *The TMIO controller converts an 8-bit NAND interface to a 16-bit | |
240 | *bus interface, so all data reads and writes must be 16-bit wide. | |
241 | *Thus, we implement 16-bit versions of the read, write, and verify | |
242 | *buffer functions. | |
243 | */ | |
244 | static void | |
245 | tmio_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
246 | { | |
247 | struct tmio_nand *tmio = mtd_to_tmio(mtd); | |
248 | ||
249 | tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); | |
250 | } | |
251 | ||
252 | static void tmio_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
253 | { | |
254 | struct tmio_nand *tmio = mtd_to_tmio(mtd); | |
255 | ||
256 | tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); | |
257 | } | |
258 | ||
259 | static int | |
260 | tmio_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
261 | { | |
262 | struct tmio_nand *tmio = mtd_to_tmio(mtd); | |
263 | u16 *p = (u16 *) buf; | |
264 | ||
265 | for (len >>= 1; len; len--) | |
266 | if (*(p++) != tmio_ioread16(tmio->fcr + FCR_DATA)) | |
267 | return -EFAULT; | |
268 | return 0; | |
269 | } | |
270 | ||
271 | static void tmio_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
272 | { | |
273 | struct tmio_nand *tmio = mtd_to_tmio(mtd); | |
274 | ||
275 | tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE); | |
276 | tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */ | |
277 | tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE); | |
278 | } | |
279 | ||
280 | static int tmio_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
281 | u_char *ecc_code) | |
282 | { | |
283 | struct tmio_nand *tmio = mtd_to_tmio(mtd); | |
284 | unsigned int ecc; | |
285 | ||
286 | tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE); | |
287 | ||
288 | ecc = tmio_ioread16(tmio->fcr + FCR_DATA); | |
289 | ecc_code[1] = ecc; /* 000-255 LP7-0 */ | |
290 | ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */ | |
291 | ecc = tmio_ioread16(tmio->fcr + FCR_DATA); | |
292 | ecc_code[2] = ecc; /* 000-255 CP5-0,11b */ | |
293 | ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */ | |
294 | ecc = tmio_ioread16(tmio->fcr + FCR_DATA); | |
295 | ecc_code[3] = ecc; /* 256-511 LP15-8 */ | |
296 | ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */ | |
297 | ||
298 | tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE); | |
299 | return 0; | |
300 | } | |
301 | ||
0f777fb9 AN |
302 | static int tmio_nand_correct_data(struct mtd_info *mtd, unsigned char *buf, |
303 | unsigned char *read_ecc, unsigned char *calc_ecc) | |
304 | { | |
305 | int r0, r1; | |
306 | ||
307 | /* assume ecc.size = 512 and ecc.bytes = 6 */ | |
308 | r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256); | |
309 | if (r0 < 0) | |
310 | return r0; | |
311 | r1 = __nand_correct_data(buf + 256, read_ecc + 3, calc_ecc + 3, 256); | |
312 | if (r1 < 0) | |
313 | return r1; | |
314 | return r0 + r1; | |
315 | } | |
316 | ||
ec43b816 IM |
317 | static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio) |
318 | { | |
944dc035 | 319 | const struct mfd_cell *cell = mfd_get_cell(dev); |
ec43b816 IM |
320 | int ret; |
321 | ||
322 | if (cell->enable) { | |
323 | ret = cell->enable(dev); | |
324 | if (ret) | |
325 | return ret; | |
326 | } | |
327 | ||
328 | /* (4Ch) CLKRUN Enable 1st spcrunc */ | |
329 | tmio_iowrite8(0x81, tmio->ccr + CCR_ICC); | |
330 | ||
331 | /* (10h)BaseAddress 0x1000 spba.spba2 */ | |
076c7f4c DB |
332 | tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE); |
333 | tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2); | |
ec43b816 IM |
334 | |
335 | /* (04h)Command Register I/O spcmd */ | |
336 | tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND); | |
337 | ||
338 | /* (62h) Power Supply Control ssmpwc */ | |
339 | /* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */ | |
340 | tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC); | |
341 | ||
342 | /* (63h) Detect Control ssmdtc */ | |
343 | tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC); | |
344 | ||
345 | /* Interrupt status register clear sintst */ | |
346 | tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); | |
347 | ||
348 | /* After power supply, Media are reset smode */ | |
349 | tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE); | |
350 | tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE); | |
351 | tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA); | |
352 | ||
353 | /* Standby Mode smode */ | |
354 | tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE); | |
355 | ||
356 | mdelay(5); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio) | |
362 | { | |
944dc035 | 363 | const struct mfd_cell *cell = mfd_get_cell(dev); |
ec43b816 IM |
364 | |
365 | tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE); | |
366 | if (cell->disable) | |
367 | cell->disable(dev); | |
368 | } | |
369 | ||
370 | static int tmio_probe(struct platform_device *dev) | |
371 | { | |
7dc00a0d | 372 | struct tmio_nand_data *data = dev->dev.platform_data; |
ec43b816 IM |
373 | struct resource *fcr = platform_get_resource(dev, |
374 | IORESOURCE_MEM, 0); | |
375 | struct resource *ccr = platform_get_resource(dev, | |
376 | IORESOURCE_MEM, 1); | |
377 | int irq = platform_get_irq(dev, 0); | |
378 | struct tmio_nand *tmio; | |
379 | struct mtd_info *mtd; | |
380 | struct nand_chip *nand_chip; | |
ec43b816 IM |
381 | int retval; |
382 | ||
383 | if (data == NULL) | |
384 | dev_warn(&dev->dev, "NULL platform data!\n"); | |
385 | ||
386 | tmio = kzalloc(sizeof *tmio, GFP_KERNEL); | |
387 | if (!tmio) { | |
388 | retval = -ENOMEM; | |
389 | goto err_kzalloc; | |
390 | } | |
391 | ||
392 | tmio->dev = dev; | |
393 | ||
394 | platform_set_drvdata(dev, tmio); | |
395 | mtd = &tmio->mtd; | |
396 | nand_chip = &tmio->chip; | |
397 | mtd->priv = nand_chip; | |
398 | mtd->name = "tmio-nand"; | |
399 | ||
448791ab | 400 | tmio->ccr = ioremap(ccr->start, resource_size(ccr)); |
ec43b816 IM |
401 | if (!tmio->ccr) { |
402 | retval = -EIO; | |
403 | goto err_iomap_ccr; | |
404 | } | |
405 | ||
076c7f4c | 406 | tmio->fcr_base = fcr->start & 0xfffff; |
448791ab | 407 | tmio->fcr = ioremap(fcr->start, resource_size(fcr)); |
ec43b816 IM |
408 | if (!tmio->fcr) { |
409 | retval = -EIO; | |
410 | goto err_iomap_fcr; | |
411 | } | |
412 | ||
413 | retval = tmio_hw_init(dev, tmio); | |
414 | if (retval) | |
415 | goto err_hwinit; | |
416 | ||
417 | /* Set address of NAND IO lines */ | |
418 | nand_chip->IO_ADDR_R = tmio->fcr; | |
419 | nand_chip->IO_ADDR_W = tmio->fcr; | |
420 | ||
421 | /* Set address of hardware control function */ | |
422 | nand_chip->cmd_ctrl = tmio_nand_hwcontrol; | |
423 | nand_chip->dev_ready = tmio_nand_dev_ready; | |
424 | nand_chip->read_byte = tmio_nand_read_byte; | |
425 | nand_chip->write_buf = tmio_nand_write_buf; | |
426 | nand_chip->read_buf = tmio_nand_read_buf; | |
427 | nand_chip->verify_buf = tmio_nand_verify_buf; | |
428 | ||
429 | /* set eccmode using hardware ECC */ | |
430 | nand_chip->ecc.mode = NAND_ECC_HW; | |
431 | nand_chip->ecc.size = 512; | |
432 | nand_chip->ecc.bytes = 6; | |
433 | nand_chip->ecc.hwctl = tmio_nand_enable_hwecc; | |
434 | nand_chip->ecc.calculate = tmio_nand_calculate_ecc; | |
0f777fb9 | 435 | nand_chip->ecc.correct = tmio_nand_correct_data; |
ec43b816 IM |
436 | |
437 | if (data) | |
438 | nand_chip->badblock_pattern = data->badblock_pattern; | |
439 | ||
440 | /* 15 us command delay time */ | |
441 | nand_chip->chip_delay = 15; | |
442 | ||
443 | retval = request_irq(irq, &tmio_irq, | |
475b44c1 | 444 | IRQF_DISABLED, dev_name(&dev->dev), tmio); |
ec43b816 IM |
445 | if (retval) { |
446 | dev_err(&dev->dev, "request_irq error %d\n", retval); | |
447 | goto err_irq; | |
448 | } | |
449 | ||
450 | tmio->irq = irq; | |
451 | nand_chip->waitfunc = tmio_nand_wait; | |
452 | ||
453 | /* Scan to find existence of the device */ | |
454 | if (nand_scan(mtd, 1)) { | |
455 | retval = -ENODEV; | |
456 | goto err_scan; | |
457 | } | |
458 | /* Register the partitions */ | |
68adef5d DES |
459 | retval = mtd_device_parse_register(mtd, NULL, 0, |
460 | data ? data->partition : NULL, | |
461 | data ? data->num_partitions : 0); | |
ec43b816 IM |
462 | if (!retval) |
463 | return retval; | |
464 | ||
465 | nand_release(mtd); | |
466 | ||
467 | err_scan: | |
468 | if (tmio->irq) | |
469 | free_irq(tmio->irq, tmio); | |
470 | err_irq: | |
471 | tmio_hw_stop(dev, tmio); | |
472 | err_hwinit: | |
473 | iounmap(tmio->fcr); | |
474 | err_iomap_fcr: | |
475 | iounmap(tmio->ccr); | |
476 | err_iomap_ccr: | |
477 | kfree(tmio); | |
478 | err_kzalloc: | |
479 | return retval; | |
480 | } | |
481 | ||
482 | static int tmio_remove(struct platform_device *dev) | |
483 | { | |
484 | struct tmio_nand *tmio = platform_get_drvdata(dev); | |
485 | ||
486 | nand_release(&tmio->mtd); | |
487 | if (tmio->irq) | |
488 | free_irq(tmio->irq, tmio); | |
489 | tmio_hw_stop(dev, tmio); | |
490 | iounmap(tmio->fcr); | |
491 | iounmap(tmio->ccr); | |
492 | kfree(tmio); | |
493 | return 0; | |
494 | } | |
495 | ||
496 | #ifdef CONFIG_PM | |
497 | static int tmio_suspend(struct platform_device *dev, pm_message_t state) | |
498 | { | |
944dc035 | 499 | const struct mfd_cell *cell = mfd_get_cell(dev); |
ec43b816 IM |
500 | |
501 | if (cell->suspend) | |
502 | cell->suspend(dev); | |
503 | ||
504 | tmio_hw_stop(dev, platform_get_drvdata(dev)); | |
505 | return 0; | |
506 | } | |
507 | ||
508 | static int tmio_resume(struct platform_device *dev) | |
509 | { | |
944dc035 | 510 | const struct mfd_cell *cell = mfd_get_cell(dev); |
ec43b816 IM |
511 | |
512 | /* FIXME - is this required or merely another attack of the broken | |
513 | * SHARP platform? Looks suspicious. | |
514 | */ | |
515 | tmio_hw_init(dev, platform_get_drvdata(dev)); | |
516 | ||
517 | if (cell->resume) | |
518 | cell->resume(dev); | |
519 | ||
520 | return 0; | |
521 | } | |
522 | #else | |
523 | #define tmio_suspend NULL | |
524 | #define tmio_resume NULL | |
525 | #endif | |
526 | ||
527 | static struct platform_driver tmio_driver = { | |
528 | .driver.name = "tmio-nand", | |
529 | .driver.owner = THIS_MODULE, | |
530 | .probe = tmio_probe, | |
531 | .remove = tmio_remove, | |
532 | .suspend = tmio_suspend, | |
533 | .resume = tmio_resume, | |
534 | }; | |
535 | ||
f99640de | 536 | module_platform_driver(tmio_driver); |
ec43b816 IM |
537 | |
538 | MODULE_LICENSE("GPL v2"); | |
539 | MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov"); | |
540 | MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller"); | |
541 | MODULE_ALIAS("platform:tmio-nand"); |