[deliverable/linux.git] / drivers / mtd / nand / txx9ndfmc.c

/*
 * TXx9 NAND flash memory controller driver
 * Based on RBTX49xx patch from CELF patch archive.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * (C) Copyright TOSHIBA CORPORATION 2004-2007
 * All Rights Reserved.
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
#include <asm/txx9/ndfmc.h>

/* TXX9 NDFMC Registers */
#define TXX9_NDFDTR	0x00
#define TXX9_NDFMCR	0x04
#define TXX9_NDFSR	0x08
#define TXX9_NDFISR	0x0c
#define TXX9_NDFIMR	0x10
#define TXX9_NDFSPR	0x14
#define TXX9_NDFRSTR	0x18	/* not TX4939 */

/* NDFMCR : NDFMC Mode Control */
#define TXX9_NDFMCR_WE	0x80
#define TXX9_NDFMCR_ECC_ALL	0x60
#define TXX9_NDFMCR_ECC_RESET	0x60
#define TXX9_NDFMCR_ECC_READ	0x40
#define TXX9_NDFMCR_ECC_ON	0x20
#define TXX9_NDFMCR_ECC_OFF	0x00
#define TXX9_NDFMCR_CE	0x10
#define TXX9_NDFMCR_BSPRT	0x04	/* TX4925/TX4926 only */
#define TXX9_NDFMCR_ALE	0x02
#define TXX9_NDFMCR_CLE	0x01
/* TX4939 only */
#define TXX9_NDFMCR_X16	0x0400
#define TXX9_NDFMCR_DMAREQ_MASK	0x0300
#define TXX9_NDFMCR_DMAREQ_NODMA	0x0000
#define TXX9_NDFMCR_DMAREQ_128	0x0100
#define TXX9_NDFMCR_DMAREQ_256	0x0200
#define TXX9_NDFMCR_DMAREQ_512	0x0300
#define TXX9_NDFMCR_CS_MASK	0x0c
#define TXX9_NDFMCR_CS(ch)	((ch) << 2)

/* NDFMCR : NDFMC Status */
#define TXX9_NDFSR_BUSY	0x80
/* TX4939 only */
#define TXX9_NDFSR_DMARUN	0x40

/* NDFMCR : NDFMC Reset */
#define TXX9_NDFRSTR_RST	0x01

struct txx9ndfmc_priv {
	struct platform_device *dev;
	struct nand_chip chip;
	int cs;
	const char *mtdname;
};

#define MAX_TXX9NDFMC_DEV	4
struct txx9ndfmc_drvdata {
	struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
	void __iomem *base;
	unsigned char hold;	/* in gbusclock */
	unsigned char spw;	/* in gbusclock */
	struct nand_hw_control hw_control;
};

static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip);
	return txx9_priv->dev;
}

static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
{
	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);

	return drvdata->base + (reg << plat->shift);
}

static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
{
	return __raw_readl(ndregaddr(dev, reg));
}

static void txx9ndfmc_write(struct platform_device *dev,
			    u32 val, unsigned int reg)
{
	__raw_writel(val, ndregaddr(dev, reg));
}

static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
{
	struct platform_device *dev = mtd_to_platdev(mtd);

	return txx9ndfmc_read(dev, TXX9_NDFDTR);
}

static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
				int len)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
	while (len--)
		__raw_writel(*buf++, ndfdtr);
	txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
}

static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);

	while (len--)
		*buf++ = __raw_readl(ndfdtr);
}

static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
			       unsigned int ctrl)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip);
	struct platform_device *dev = txx9_priv->dev;
	struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);

	if (ctrl & NAND_CTRL_CHANGE) {
		u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

		mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
		mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
		mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
		/* TXX9_NDFMCR_CE bit is 0:high 1:low */
		mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
		if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
			mcr &= ~TXX9_NDFMCR_CS_MASK;
			mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
		}
		txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
	}
	if (cmd != NAND_CMD_NONE)
		txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
	if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
		/* dummy write to update external latch */
		if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
			txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
	}
	mmiowb();
}

static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
{
	struct platform_device *dev = mtd_to_platdev(mtd);

	return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
}

static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
				   uint8_t *ecc_code)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	struct nand_chip *chip = mtd_to_nand(mtd);
	int eccbytes;
	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
	for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
		ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
		ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
		ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
		ecc_code += 3;
	}
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	return 0;
}

static int txx9ndfmc_correct_data(struct mtd_info *mtd, unsigned char *buf,
		unsigned char *read_ecc, unsigned char *calc_ecc)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	int eccsize;
	int corrected = 0;
	int stat;

	for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
		stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
		if (stat < 0)
			return stat;
		corrected += stat;
		buf += 256;
		read_ecc += 3;
		calc_ecc += 3;
	}
	return corrected;
}

static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
}

static void txx9ndfmc_initialize(struct platform_device *dev)
{
	struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	int tmout = 100;

	if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
		; /* no NDFRSTR.  Write to NDFSPR resets the NDFMC. */
	else {
		/* reset NDFMC */
		txx9ndfmc_write(dev,
				txx9ndfmc_read(dev, TXX9_NDFRSTR) |
				TXX9_NDFRSTR_RST,
				TXX9_NDFRSTR);
		while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
			if (--tmout == 0) {
				dev_err(&dev->dev, "reset failed.\n");
				break;
			}
			udelay(1);
		}
	}
	/* setup Hold Time, Strobe Pulse Width */
	txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
	txx9ndfmc_write(dev,
			(plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
			TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
}

#define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
	DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)

static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	int ret;

	ret = nand_scan_ident(mtd, 1, NULL);
	if (!ret) {
		if (mtd->writesize >= 512) {
			/* Hardware ECC 6 byte ECC per 512 Byte data */
			chip->ecc.size = 512;
			chip->ecc.bytes = 6;
		}
		ret = nand_scan_tail(mtd);
	}
	return ret;
}

static int __init txx9ndfmc_probe(struct platform_device *dev)
{
	struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
	int hold, spw;
	int i;
	struct txx9ndfmc_drvdata *drvdata;
	unsigned long gbusclk = plat->gbus_clock;
	struct resource *res;

	drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
	if (!drvdata)
		return -ENOMEM;
	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	drvdata->base = devm_ioremap_resource(&dev->dev, res);
	if (IS_ERR(drvdata->base))
		return PTR_ERR(drvdata->base);

	hold = plat->hold ?: 20; /* tDH */
	spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */

	hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
	spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
	if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
		hold -= 2;	/* actual hold time : (HOLD + 2) BUSCLK */
	spw -= 1;	/* actual wait time : (SPW + 1) BUSCLK */
	hold = clamp(hold, 1, 15);
	drvdata->hold = hold;
	spw = clamp(spw, 1, 15);
	drvdata->spw = spw;
	dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
		 (gbusclk + 500000) / 1000000, hold, spw);

	spin_lock_init(&drvdata->hw_control.lock);
	init_waitqueue_head(&drvdata->hw_control.wq);

	platform_set_drvdata(dev, drvdata);
	txx9ndfmc_initialize(dev);

	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
		struct txx9ndfmc_priv *txx9_priv;
		struct nand_chip *chip;
		struct mtd_info *mtd;

		if (!(plat->ch_mask & (1 << i)))
			continue;
		txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
				    GFP_KERNEL);
		if (!txx9_priv)
			continue;
		chip = &txx9_priv->chip;
		mtd = nand_to_mtd(chip);
		mtd->dev.parent = &dev->dev;

		chip->read_byte = txx9ndfmc_read_byte;
		chip->read_buf = txx9ndfmc_read_buf;
		chip->write_buf = txx9ndfmc_write_buf;
		chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
		chip->dev_ready = txx9ndfmc_dev_ready;
		chip->ecc.calculate = txx9ndfmc_calculate_ecc;
		chip->ecc.correct = txx9ndfmc_correct_data;
		chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
		chip->ecc.mode = NAND_ECC_HW;
		/* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
		chip->ecc.size = 256;
		chip->ecc.bytes = 3;
		chip->ecc.strength = 1;
		chip->chip_delay = 100;
		chip->controller = &drvdata->hw_control;

		nand_set_controller_data(chip, txx9_priv);
		txx9_priv->dev = dev;

		if (plat->ch_mask != 1) {
			txx9_priv->cs = i;
			txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
						       dev_name(&dev->dev), i);
		} else {
			txx9_priv->cs = -1;
			txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
						     GFP_KERNEL);
		}
		if (!txx9_priv->mtdname) {
			kfree(txx9_priv);
			dev_err(&dev->dev, "Unable to allocate MTD name.\n");
			continue;
		}
		if (plat->wide_mask & (1 << i))
			chip->options |= NAND_BUSWIDTH_16;

		if (txx9ndfmc_nand_scan(mtd)) {
			kfree(txx9_priv->mtdname);
			kfree(txx9_priv);
			continue;
		}
		mtd->name = txx9_priv->mtdname;

		mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
		drvdata->mtds[i] = mtd;
	}

	return 0;
}

static int __exit txx9ndfmc_remove(struct platform_device *dev)
{
	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	int i;

	if (!drvdata)
		return 0;
	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
		struct mtd_info *mtd = drvdata->mtds[i];
		struct nand_chip *chip;
		struct txx9ndfmc_priv *txx9_priv;

		if (!mtd)
			continue;
		chip = mtd_to_nand(mtd);
		txx9_priv = nand_get_controller_data(chip);

		nand_release(mtd);
		kfree(txx9_priv->mtdname);
		kfree(txx9_priv);
	}
	return 0;
}

#ifdef CONFIG_PM
static int txx9ndfmc_resume(struct platform_device *dev)
{
	if (platform_get_drvdata(dev))
		txx9ndfmc_initialize(dev);
	return 0;
}
#else
#define txx9ndfmc_resume NULL
#endif

static struct platform_driver txx9ndfmc_driver = {
	.remove		= __exit_p(txx9ndfmc_remove),
	.resume		= txx9ndfmc_resume,
	.driver		= {
		.name	= "txx9ndfmc",
	},
};

module_platform_driver_probe(txx9ndfmc_driver, txx9ndfmc_probe);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
MODULE_ALIAS("platform:txx9ndfmc");
Commit	Line	Data
64fb65ba AN	1	/*
	2	* TXx9 NAND flash memory controller driver
	3	* Based on RBTX49xx patch from CELF patch archive.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* (C) Copyright TOSHIBA CORPORATION 2004-2007
	10	* All Rights Reserved.
	11	*/
b0de774c	12	#include <linux/err.h>
64fb65ba AN	13	#include <linux/init.h>
	14	#include <linux/slab.h>
	15	#include <linux/module.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/delay.h>
	18	#include <linux/mtd/mtd.h>
	19	#include <linux/mtd/nand.h>
	20	#include <linux/mtd/nand_ecc.h>
	21	#include <linux/mtd/partitions.h>
	22	#include <linux/io.h>
	23	#include <asm/txx9/ndfmc.h>
	24
	25	/* TXX9 NDFMC Registers */
	26	#define TXX9_NDFDTR 0x00
	27	#define TXX9_NDFMCR 0x04
	28	#define TXX9_NDFSR 0x08
	29	#define TXX9_NDFISR 0x0c
	30	#define TXX9_NDFIMR 0x10
	31	#define TXX9_NDFSPR 0x14
	32	#define TXX9_NDFRSTR 0x18 /* not TX4939 */
	33
	34	/* NDFMCR : NDFMC Mode Control */
	35	#define TXX9_NDFMCR_WE 0x80
	36	#define TXX9_NDFMCR_ECC_ALL 0x60
	37	#define TXX9_NDFMCR_ECC_RESET 0x60
	38	#define TXX9_NDFMCR_ECC_READ 0x40
	39	#define TXX9_NDFMCR_ECC_ON 0x20
	40	#define TXX9_NDFMCR_ECC_OFF 0x00
	41	#define TXX9_NDFMCR_CE 0x10
	42	#define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */
	43	#define TXX9_NDFMCR_ALE 0x02
	44	#define TXX9_NDFMCR_CLE 0x01
	45	/* TX4939 only */
	46	#define TXX9_NDFMCR_X16 0x0400
	47	#define TXX9_NDFMCR_DMAREQ_MASK 0x0300
	48	#define TXX9_NDFMCR_DMAREQ_NODMA 0x0000
	49	#define TXX9_NDFMCR_DMAREQ_128 0x0100
	50	#define TXX9_NDFMCR_DMAREQ_256 0x0200
	51	#define TXX9_NDFMCR_DMAREQ_512 0x0300
	52	#define TXX9_NDFMCR_CS_MASK 0x0c
	53	#define TXX9_NDFMCR_CS(ch) ((ch) << 2)
	54
	55	/* NDFMCR : NDFMC Status */
	56	#define TXX9_NDFSR_BUSY 0x80
	57	/* TX4939 only */
	58	#define TXX9_NDFSR_DMARUN 0x40
	59
	60	/* NDFMCR : NDFMC Reset */
	61	#define TXX9_NDFRSTR_RST 0x01
	62
	63	struct txx9ndfmc_priv {
	64	struct platform_device *dev;
	65	struct nand_chip chip;
64fb65ba	66	int cs;
81933046	67	const char *mtdname;
64fb65ba AN	68	};
	69
	70	#define MAX_TXX9NDFMC_DEV 4
	71	struct txx9ndfmc_drvdata {
	72	struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
	73	void __iomem *base;
	74	unsigned char hold; /* in gbusclock */
	75	unsigned char spw; /* in gbusclock */
	76	struct nand_hw_control hw_control;
64fb65ba AN	77	};
	78
	79	static struct platform_device mtd_to_platdev(struct mtd_info mtd)
	80	{
4bd4ebcc	81	struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25	82	struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip);
64fb65ba AN	83	return txx9_priv->dev;
	84	}
	85
	86	static void __iomem ndregaddr(struct platform_device dev, unsigned int reg)
	87	{
	88	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
453810b7	89	struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
64fb65ba AN	90
	91	return drvdata->base + (reg << plat->shift);
	92	}
	93
	94	static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
	95	{
	96	return __raw_readl(ndregaddr(dev, reg));
	97	}
	98
	99	static void txx9ndfmc_write(struct platform_device *dev,
	100	u32 val, unsigned int reg)
	101	{
	102	__raw_writel(val, ndregaddr(dev, reg));
	103	}
	104
	105	static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
	106	{
	107	struct platform_device *dev = mtd_to_platdev(mtd);
	108
	109	return txx9ndfmc_read(dev, TXX9_NDFDTR);
	110	}
	111
	112	static void txx9ndfmc_write_buf(struct mtd_info mtd, const uint8_t buf,
	113	int len)
	114	{
	115	struct platform_device *dev = mtd_to_platdev(mtd);
	116	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
	117	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	118
	119	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_WE, TXX9_NDFMCR);
	120	while (len--)
	121	__raw_writel(*buf++, ndfdtr);
	122	txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
	123	}
	124
	125	static void txx9ndfmc_read_buf(struct mtd_info mtd, uint8_t buf, int len)
	126	{
	127	struct platform_device *dev = mtd_to_platdev(mtd);
	128	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
	129
	130	while (len--)
	131	*buf++ = __raw_readl(ndfdtr);
	132	}
	133
64fb65ba AN	134	static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
	135	unsigned int ctrl)
	136	{
4bd4ebcc	137	struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25	138	struct txx9ndfmc_priv *txx9_priv = nand_get_controller_data(chip);
64fb65ba	139	struct platform_device *dev = txx9_priv->dev;
453810b7	140	struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
64fb65ba AN	141
	142	if (ctrl & NAND_CTRL_CHANGE) {
	143	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	144
	145	mcr &= ~(TXX9_NDFMCR_CLE \| TXX9_NDFMCR_ALE \| TXX9_NDFMCR_CE);
	146	mcr \|= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
	147	mcr \|= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
	148	/* TXX9_NDFMCR_CE bit is 0:high 1:low */
	149	mcr \|= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
	150	if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
	151	mcr &= ~TXX9_NDFMCR_CS_MASK;
	152	mcr \|= TXX9_NDFMCR_CS(txx9_priv->cs);
	153	}
	154	txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
	155	}
	156	if (cmd != NAND_CMD_NONE)
	157	txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
	158	if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
	159	/* dummy write to update external latch */
	160	if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
	161	txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
	162	}
	163	mmiowb();
	164	}
	165
	166	static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
	167	{
	168	struct platform_device *dev = mtd_to_platdev(mtd);
	169
	170	return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
	171	}
	172
	173	static int txx9ndfmc_calculate_ecc(struct mtd_info mtd, const uint8_t dat,
	174	uint8_t *ecc_code)
	175	{
	176	struct platform_device *dev = mtd_to_platdev(mtd);
4bd4ebcc	177	struct nand_chip *chip = mtd_to_nand(mtd);
c0cbfd0e	178	int eccbytes;
64fb65ba AN	179	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	180
	181	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	182	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	183	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
c0cbfd0e AN	184	for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
	185	ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
	186	ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
	187	ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
	188	ecc_code += 3;
	189	}
64fb65ba AN	190	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	191	return 0;
	192	}
	193
c0cbfd0e AN	194	static int txx9ndfmc_correct_data(struct mtd_info mtd, unsigned char buf,
	195	unsigned char read_ecc, unsigned char calc_ecc)
	196	{
4bd4ebcc	197	struct nand_chip *chip = mtd_to_nand(mtd);
c0cbfd0e AN	198	int eccsize;
	199	int corrected = 0;
	200	int stat;
	201
	202	for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
	203	stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
	204	if (stat < 0)
	205	return stat;
	206	corrected += stat;
	207	buf += 256;
	208	read_ecc += 3;
	209	calc_ecc += 3;
	210	}
	211	return corrected;
	212	}
	213
64fb65ba AN	214	static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
	215	{
	216	struct platform_device *dev = mtd_to_platdev(mtd);
	217	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	218
	219	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	220	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
	221	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	222	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
	223	}
	224
	225	static void txx9ndfmc_initialize(struct platform_device *dev)
	226	{
453810b7	227	struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
64fb65ba AN	228	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	229	int tmout = 100;
	230
	231	if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
	232	; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */
	233	else {
	234	/* reset NDFMC */
	235	txx9ndfmc_write(dev,
	236	txx9ndfmc_read(dev, TXX9_NDFRSTR) \|
	237	TXX9_NDFRSTR_RST,
	238	TXX9_NDFRSTR);
	239	while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
	240	if (--tmout == 0) {
	241	dev_err(&dev->dev, "reset failed.\n");
	242	break;
	243	}
	244	udelay(1);
	245	}
	246	}
	247	/* setup Hold Time, Strobe Pulse Width */
	248	txx9ndfmc_write(dev, (drvdata->hold << 4) \| drvdata->spw, TXX9_NDFSPR);
	249	txx9ndfmc_write(dev,
	250	(plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
	251	TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
	252	}
	253
	254	#define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
	255	DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
	256
c0cbfd0e AN	257	static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
c0cbfd0e AN	258	{
4bd4ebcc	259	struct nand_chip *chip = mtd_to_nand(mtd);
c0cbfd0e AN	260	int ret;
c0cbfd0e AN	261
5e81e88a	262	ret = nand_scan_ident(mtd, 1, NULL);
c0cbfd0e AN	263	if (!ret) {
c0cbfd0e AN	264	if (mtd->writesize >= 512) {
24ac9a94 RR	265	/* Hardware ECC 6 byte ECC per 512 Byte data */
	266	chip->ecc.size = 512;
	267	chip->ecc.bytes = 6;
c0cbfd0e AN	268	}
	269	ret = nand_scan_tail(mtd);
	270	}
	271	return ret;
	272	}
	273
64fb65ba AN	274	static int __init txx9ndfmc_probe(struct platform_device *dev)
64fb65ba AN	275	{
453810b7	276	struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
64fb65ba AN	277	int hold, spw;
	278	int i;
	279	struct txx9ndfmc_drvdata *drvdata;
	280	unsigned long gbusclk = plat->gbus_clock;
	281	struct resource *res;
	282
64fb65ba AN	283	drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
	284	if (!drvdata)
	285	return -ENOMEM;
7a96541a	286	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
b0de774c TR	287	drvdata->base = devm_ioremap_resource(&dev->dev, res);
	288	if (IS_ERR(drvdata->base))
	289	return PTR_ERR(drvdata->base);
64fb65ba AN	290
	291	hold = plat->hold ?: 20; /* tDH */
	292	spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */
	293
	294	hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
	295	spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
	296	if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
	297	hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */
	298	spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */
	299	hold = clamp(hold, 1, 15);
	300	drvdata->hold = hold;
	301	spw = clamp(spw, 1, 15);
	302	drvdata->spw = spw;
	303	dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
	304	(gbusclk + 500000) / 1000000, hold, spw);
	305
	306	spin_lock_init(&drvdata->hw_control.lock);
	307	init_waitqueue_head(&drvdata->hw_control.wq);
	308
	309	platform_set_drvdata(dev, drvdata);
	310	txx9ndfmc_initialize(dev);
	311
	312	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
	313	struct txx9ndfmc_priv *txx9_priv;
	314	struct nand_chip *chip;
	315	struct mtd_info *mtd;
64fb65ba AN	316
	317	if (!(plat->ch_mask & (1 << i)))
	318	continue;
	319	txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
	320	GFP_KERNEL);
844a72c5	321	if (!txx9_priv)
64fb65ba	322	continue;
64fb65ba	323	chip = &txx9_priv->chip;
a3f54377	324	mtd = nand_to_mtd(chip);
693ad872	325	mtd->dev.parent = &dev->dev;
64fb65ba	326
64fb65ba AN	327	chip->read_byte = txx9ndfmc_read_byte;
	328	chip->read_buf = txx9ndfmc_read_buf;
	329	chip->write_buf = txx9ndfmc_write_buf;
64fb65ba AN	330	chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
	331	chip->dev_ready = txx9ndfmc_dev_ready;
	332	chip->ecc.calculate = txx9ndfmc_calculate_ecc;
c0cbfd0e	333	chip->ecc.correct = txx9ndfmc_correct_data;
64fb65ba AN	334	chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
64fb65ba AN	335	chip->ecc.mode = NAND_ECC_HW;
c0cbfd0e	336	/* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
64fb65ba AN	337	chip->ecc.size = 256;
64fb65ba AN	338	chip->ecc.bytes = 3;
6a918bad	339	chip->ecc.strength = 1;
64fb65ba AN	340	chip->chip_delay = 100;
	341	chip->controller = &drvdata->hw_control;
	342
d699ed25	343	nand_set_controller_data(chip, txx9_priv);
64fb65ba AN	344	txx9_priv->dev = dev;
	345
	346	if (plat->ch_mask != 1) {
	347	txx9_priv->cs = i;
81933046 DW	348	txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
81933046 DW	349	dev_name(&dev->dev), i);
64fb65ba AN	350	} else {
64fb65ba AN	351	txx9_priv->cs = -1;
272023df AN	352	txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
	353	GFP_KERNEL);
	354	}
	355	if (!txx9_priv->mtdname) {
	356	kfree(txx9_priv);
	357	dev_err(&dev->dev, "Unable to allocate MTD name.\n");
	358	continue;
64fb65ba AN	359	}
	360	if (plat->wide_mask & (1 << i))
	361	chip->options \|= NAND_BUSWIDTH_16;
	362
c0cbfd0e	363	if (txx9ndfmc_nand_scan(mtd)) {
272023df	364	kfree(txx9_priv->mtdname);
64fb65ba AN	365	kfree(txx9_priv);
	366	continue;
	367	}
	368	mtd->name = txx9_priv->mtdname;
	369
42d7fbe2	370	mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
64fb65ba AN	371	drvdata->mtds[i] = mtd;
	372	}
	373
	374	return 0;
	375	}
	376
	377	static int __exit txx9ndfmc_remove(struct platform_device *dev)
	378	{
	379	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	380	int i;
	381
64fb65ba AN	382	if (!drvdata)
	383	return 0;
	384	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
	385	struct mtd_info *mtd = drvdata->mtds[i];
	386	struct nand_chip *chip;
	387	struct txx9ndfmc_priv *txx9_priv;
	388
	389	if (!mtd)
	390	continue;
4bd4ebcc	391	chip = mtd_to_nand(mtd);
d699ed25	392	txx9_priv = nand_get_controller_data(chip);
64fb65ba	393
6eb4feff	394	nand_release(mtd);
272023df	395	kfree(txx9_priv->mtdname);
64fb65ba AN	396	kfree(txx9_priv);
	397	}
	398	return 0;
	399	}
	400
	401	#ifdef CONFIG_PM
	402	static int txx9ndfmc_resume(struct platform_device *dev)
	403	{
	404	if (platform_get_drvdata(dev))
	405	txx9ndfmc_initialize(dev);
	406	return 0;
	407	}
	408	#else
	409	#define txx9ndfmc_resume NULL
	410	#endif
	411
	412	static struct platform_driver txx9ndfmc_driver = {
	413	.remove = __exit_p(txx9ndfmc_remove),
	414	.resume = txx9ndfmc_resume,
	415	.driver = {
	416	.name = "txx9ndfmc",
64fb65ba AN	417	},
	418	};
	419
3a2a13fa	420	module_platform_driver_probe(txx9ndfmc_driver, txx9ndfmc_probe);
64fb65ba AN	421
	422	MODULE_LICENSE("GPL");
	423	MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
	424	MODULE_ALIAS("platform:txx9ndfmc");