[deliverable/linux.git] / drivers / mtd / nand / txx9ndfmc.c

/*
 * TXx9 NAND flash memory controller driver
 * Based on RBTX49xx patch from CELF patch archive.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * (C) Copyright TOSHIBA CORPORATION 2004-2007
 * All Rights Reserved.
 */
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
#include <asm/txx9/ndfmc.h>

/* TXX9 NDFMC Registers */
#define TXX9_NDFDTR	0x00
#define TXX9_NDFMCR	0x04
#define TXX9_NDFSR	0x08
#define TXX9_NDFISR	0x0c
#define TXX9_NDFIMR	0x10
#define TXX9_NDFSPR	0x14
#define TXX9_NDFRSTR	0x18	/* not TX4939 */

/* NDFMCR : NDFMC Mode Control */
#define TXX9_NDFMCR_WE	0x80
#define TXX9_NDFMCR_ECC_ALL	0x60
#define TXX9_NDFMCR_ECC_RESET	0x60
#define TXX9_NDFMCR_ECC_READ	0x40
#define TXX9_NDFMCR_ECC_ON	0x20
#define TXX9_NDFMCR_ECC_OFF	0x00
#define TXX9_NDFMCR_CE	0x10
#define TXX9_NDFMCR_BSPRT	0x04	/* TX4925/TX4926 only */
#define TXX9_NDFMCR_ALE	0x02
#define TXX9_NDFMCR_CLE	0x01
/* TX4939 only */
#define TXX9_NDFMCR_X16	0x0400
#define TXX9_NDFMCR_DMAREQ_MASK	0x0300
#define TXX9_NDFMCR_DMAREQ_NODMA	0x0000
#define TXX9_NDFMCR_DMAREQ_128	0x0100
#define TXX9_NDFMCR_DMAREQ_256	0x0200
#define TXX9_NDFMCR_DMAREQ_512	0x0300
#define TXX9_NDFMCR_CS_MASK	0x0c
#define TXX9_NDFMCR_CS(ch)	((ch) << 2)

/* NDFMCR : NDFMC Status */
#define TXX9_NDFSR_BUSY	0x80
/* TX4939 only */
#define TXX9_NDFSR_DMARUN	0x40

/* NDFMCR : NDFMC Reset */
#define TXX9_NDFRSTR_RST	0x01

struct txx9ndfmc_priv {
	struct platform_device *dev;
	struct nand_chip chip;
	struct mtd_info mtd;
	int cs;
	const char *mtdname;
};

#define MAX_TXX9NDFMC_DEV	4
struct txx9ndfmc_drvdata {
	struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
	void __iomem *base;
	unsigned char hold;	/* in gbusclock */
	unsigned char spw;	/* in gbusclock */
	struct nand_hw_control hw_control;
};

static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
{
	struct nand_chip *chip = mtd->priv;
	struct txx9ndfmc_priv *txx9_priv = chip->priv;
	return txx9_priv->dev;
}

static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
{
	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;

	return drvdata->base + (reg << plat->shift);
}

static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
{
	return __raw_readl(ndregaddr(dev, reg));
}

static void txx9ndfmc_write(struct platform_device *dev,
			    u32 val, unsigned int reg)
{
	__raw_writel(val, ndregaddr(dev, reg));
}

static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
{
	struct platform_device *dev = mtd_to_platdev(mtd);

	return txx9ndfmc_read(dev, TXX9_NDFDTR);
}

static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
				int len)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
	while (len--)
		__raw_writel(*buf++, ndfdtr);
	txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
}

static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);

	while (len--)
		*buf++ = __raw_readl(ndfdtr);
}

static int txx9ndfmc_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
				int len)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);

	while (len--)
		if (*buf++ != (uint8_t)__raw_readl(ndfdtr))
			return -EFAULT;
	return 0;
}

static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
			       unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;
	struct txx9ndfmc_priv *txx9_priv = chip->priv;
	struct platform_device *dev = txx9_priv->dev;
	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;

	if (ctrl & NAND_CTRL_CHANGE) {
		u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

		mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
		mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
		mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
		/* TXX9_NDFMCR_CE bit is 0:high 1:low */
		mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
		if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
			mcr &= ~TXX9_NDFMCR_CS_MASK;
			mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
		}
		txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
	}
	if (cmd != NAND_CMD_NONE)
		txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
	if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
		/* dummy write to update external latch */
		if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
			txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
	}
	mmiowb();
}

static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
{
	struct platform_device *dev = mtd_to_platdev(mtd);

	return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
}

static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
				   uint8_t *ecc_code)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	struct nand_chip *chip = mtd->priv;
	int eccbytes;
	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
	for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
		ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
		ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
		ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
		ecc_code += 3;
	}
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	return 0;
}

static int txx9ndfmc_correct_data(struct mtd_info *mtd, unsigned char *buf,
		unsigned char *read_ecc, unsigned char *calc_ecc)
{
	struct nand_chip *chip = mtd->priv;
	int eccsize;
	int corrected = 0;
	int stat;

	for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
		stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
		if (stat < 0)
			return stat;
		corrected += stat;
		buf += 256;
		read_ecc += 3;
		calc_ecc += 3;
	}
	return corrected;
}

static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
}

static void txx9ndfmc_initialize(struct platform_device *dev)
{
	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	int tmout = 100;

	if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
		; /* no NDFRSTR.  Write to NDFSPR resets the NDFMC. */
	else {
		/* reset NDFMC */
		txx9ndfmc_write(dev,
				txx9ndfmc_read(dev, TXX9_NDFRSTR) |
				TXX9_NDFRSTR_RST,
				TXX9_NDFRSTR);
		while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
			if (--tmout == 0) {
				dev_err(&dev->dev, "reset failed.\n");
				break;
			}
			udelay(1);
		}
	}
	/* setup Hold Time, Strobe Pulse Width */
	txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
	txx9ndfmc_write(dev,
			(plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
			TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
}

#define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
	DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)

static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
{
	struct nand_chip *chip = mtd->priv;
	int ret;

	ret = nand_scan_ident(mtd, 1, NULL);
	if (!ret) {
		if (mtd->writesize >= 512) {
			/* Hardware ECC 6 byte ECC per 512 Byte data */
			chip->ecc.size = 512;
			chip->ecc.bytes = 6;
		}
		ret = nand_scan_tail(mtd);
	}
	return ret;
}

static int __init txx9ndfmc_probe(struct platform_device *dev)
{
	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
	int hold, spw;
	int i;
	struct txx9ndfmc_drvdata *drvdata;
	unsigned long gbusclk = plat->gbus_clock;
	struct resource *res;

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;
	drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
	if (!drvdata)
		return -ENOMEM;
	if (!devm_request_mem_region(&dev->dev, res->start,
				     resource_size(res), dev_name(&dev->dev)))
		return -EBUSY;
	drvdata->base = devm_ioremap(&dev->dev, res->start,
				     resource_size(res));
	if (!drvdata->base)
		return -EBUSY;

	hold = plat->hold ?: 20; /* tDH */
	spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */

	hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
	spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
	if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
		hold -= 2;	/* actual hold time : (HOLD + 2) BUSCLK */
	spw -= 1;	/* actual wait time : (SPW + 1) BUSCLK */
	hold = clamp(hold, 1, 15);
	drvdata->hold = hold;
	spw = clamp(spw, 1, 15);
	drvdata->spw = spw;
	dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
		 (gbusclk + 500000) / 1000000, hold, spw);

	spin_lock_init(&drvdata->hw_control.lock);
	init_waitqueue_head(&drvdata->hw_control.wq);

	platform_set_drvdata(dev, drvdata);
	txx9ndfmc_initialize(dev);

	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
		struct txx9ndfmc_priv *txx9_priv;
		struct nand_chip *chip;
		struct mtd_info *mtd;

		if (!(plat->ch_mask & (1 << i)))
			continue;
		txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
				    GFP_KERNEL);
		if (!txx9_priv) {
			dev_err(&dev->dev, "Unable to allocate "
				"TXx9 NDFMC MTD device structure.\n");
			continue;
		}
		chip = &txx9_priv->chip;
		mtd = &txx9_priv->mtd;
		mtd->owner = THIS_MODULE;

		mtd->priv = chip;

		chip->read_byte = txx9ndfmc_read_byte;
		chip->read_buf = txx9ndfmc_read_buf;
		chip->write_buf = txx9ndfmc_write_buf;
		chip->verify_buf = txx9ndfmc_verify_buf;
		chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
		chip->dev_ready = txx9ndfmc_dev_ready;
		chip->ecc.calculate = txx9ndfmc_calculate_ecc;
		chip->ecc.correct = txx9ndfmc_correct_data;
		chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
		chip->ecc.mode = NAND_ECC_HW;
		/* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
		chip->ecc.size = 256;
		chip->ecc.bytes = 3;
		chip->chip_delay = 100;
		chip->controller = &drvdata->hw_control;

		chip->priv = txx9_priv;
		txx9_priv->dev = dev;

		if (plat->ch_mask != 1) {
			txx9_priv->cs = i;
			txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
						       dev_name(&dev->dev), i);
		} else {
			txx9_priv->cs = -1;
			txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
						     GFP_KERNEL);
		}
		if (!txx9_priv->mtdname) {
			kfree(txx9_priv);
			dev_err(&dev->dev, "Unable to allocate MTD name.\n");
			continue;
		}
		if (plat->wide_mask & (1 << i))
			chip->options |= NAND_BUSWIDTH_16;

		if (txx9ndfmc_nand_scan(mtd)) {
			kfree(txx9_priv->mtdname);
			kfree(txx9_priv);
			continue;
		}
		mtd->name = txx9_priv->mtdname;

		mtd_device_parse_register(mtd, NULL, 0, NULL, 0);
		drvdata->mtds[i] = mtd;
	}

	return 0;
}

static int __exit txx9ndfmc_remove(struct platform_device *dev)
{
	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	int i;

	platform_set_drvdata(dev, NULL);
	if (!drvdata)
		return 0;
	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
		struct mtd_info *mtd = drvdata->mtds[i];
		struct nand_chip *chip;
		struct txx9ndfmc_priv *txx9_priv;

		if (!mtd)
			continue;
		chip = mtd->priv;
		txx9_priv = chip->priv;

		nand_release(mtd);
		kfree(txx9_priv->mtdname);
		kfree(txx9_priv);
	}
	return 0;
}

#ifdef CONFIG_PM
static int txx9ndfmc_resume(struct platform_device *dev)
{
	if (platform_get_drvdata(dev))
		txx9ndfmc_initialize(dev);
	return 0;
}
#else
#define txx9ndfmc_resume NULL
#endif

static struct platform_driver txx9ndfmc_driver = {
	.remove		= __exit_p(txx9ndfmc_remove),
	.resume		= txx9ndfmc_resume,
	.driver		= {
		.name	= "txx9ndfmc",
		.owner	= THIS_MODULE,
	},
};

static int __init txx9ndfmc_init(void)
{
	return platform_driver_probe(&txx9ndfmc_driver, txx9ndfmc_probe);
}

static void __exit txx9ndfmc_exit(void)
{
	platform_driver_unregister(&txx9ndfmc_driver);
}

module_init(txx9ndfmc_init);
module_exit(txx9ndfmc_exit);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
MODULE_ALIAS("platform:txx9ndfmc");
Commit	Line	Data
64fb65ba AN	1	/*
	2	* TXx9 NAND flash memory controller driver
	3	* Based on RBTX49xx patch from CELF patch archive.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* (C) Copyright TOSHIBA CORPORATION 2004-2007
	10	* All Rights Reserved.
	11	*/
	12	#include <linux/init.h>
	13	#include <linux/slab.h>
	14	#include <linux/module.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/delay.h>
	17	#include <linux/mtd/mtd.h>
	18	#include <linux/mtd/nand.h>
	19	#include <linux/mtd/nand_ecc.h>
	20	#include <linux/mtd/partitions.h>
	21	#include <linux/io.h>
	22	#include <asm/txx9/ndfmc.h>
	23
	24	/* TXX9 NDFMC Registers */
	25	#define TXX9_NDFDTR 0x00
	26	#define TXX9_NDFMCR 0x04
	27	#define TXX9_NDFSR 0x08
	28	#define TXX9_NDFISR 0x0c
	29	#define TXX9_NDFIMR 0x10
	30	#define TXX9_NDFSPR 0x14
	31	#define TXX9_NDFRSTR 0x18 /* not TX4939 */
	32
	33	/* NDFMCR : NDFMC Mode Control */
	34	#define TXX9_NDFMCR_WE 0x80
	35	#define TXX9_NDFMCR_ECC_ALL 0x60
	36	#define TXX9_NDFMCR_ECC_RESET 0x60
	37	#define TXX9_NDFMCR_ECC_READ 0x40
	38	#define TXX9_NDFMCR_ECC_ON 0x20
	39	#define TXX9_NDFMCR_ECC_OFF 0x00
	40	#define TXX9_NDFMCR_CE 0x10
	41	#define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */
	42	#define TXX9_NDFMCR_ALE 0x02
	43	#define TXX9_NDFMCR_CLE 0x01
	44	/* TX4939 only */
	45	#define TXX9_NDFMCR_X16 0x0400
	46	#define TXX9_NDFMCR_DMAREQ_MASK 0x0300
	47	#define TXX9_NDFMCR_DMAREQ_NODMA 0x0000
	48	#define TXX9_NDFMCR_DMAREQ_128 0x0100
	49	#define TXX9_NDFMCR_DMAREQ_256 0x0200
	50	#define TXX9_NDFMCR_DMAREQ_512 0x0300
	51	#define TXX9_NDFMCR_CS_MASK 0x0c
	52	#define TXX9_NDFMCR_CS(ch) ((ch) << 2)
	53
	54	/* NDFMCR : NDFMC Status */
	55	#define TXX9_NDFSR_BUSY 0x80
	56	/* TX4939 only */
	57	#define TXX9_NDFSR_DMARUN 0x40
	58
	59	/* NDFMCR : NDFMC Reset */
	60	#define TXX9_NDFRSTR_RST 0x01
	61
	62	struct txx9ndfmc_priv {
	63	struct platform_device *dev;
	64	struct nand_chip chip;
65	struct mtd_info mtd;
66	int cs;
81933046	67	const char *mtdname;
64fb65ba AN	68	};
	69
	70	#define MAX_TXX9NDFMC_DEV 4
	71	struct txx9ndfmc_drvdata {
	72	struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
	73	void __iomem *base;
	74	unsigned char hold; /* in gbusclock */
	75	unsigned char spw; /* in gbusclock */
	76	struct nand_hw_control hw_control;
64fb65ba AN	77	};
	78
	79	static struct platform_device mtd_to_platdev(struct mtd_info mtd)
	80	{
	81	struct nand_chip *chip = mtd->priv;
	82	struct txx9ndfmc_priv *txx9_priv = chip->priv;
	83	return txx9_priv->dev;
	84	}
	85
	86	static void __iomem ndregaddr(struct platform_device dev, unsigned int reg)
	87	{
	88	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	89	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
	90
	91	return drvdata->base + (reg << plat->shift);
	92	}
	93
	94	static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
	95	{
	96	return __raw_readl(ndregaddr(dev, reg));
	97	}
	98
	99	static void txx9ndfmc_write(struct platform_device *dev,
	100	u32 val, unsigned int reg)
	101	{
	102	__raw_writel(val, ndregaddr(dev, reg));
	103	}
	104
	105	static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
	106	{
	107	struct platform_device *dev = mtd_to_platdev(mtd);
	108
	109	return txx9ndfmc_read(dev, TXX9_NDFDTR);
	110	}
	111
	112	static void txx9ndfmc_write_buf(struct mtd_info mtd, const uint8_t buf,
	113	int len)
	114	{
	115	struct platform_device *dev = mtd_to_platdev(mtd);
	116	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
	117	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	118
	119	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_WE, TXX9_NDFMCR);
	120	while (len--)
	121	__raw_writel(*buf++, ndfdtr);
	122	txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
	123	}
	124
	125	static void txx9ndfmc_read_buf(struct mtd_info mtd, uint8_t buf, int len)
	126	{
	127	struct platform_device *dev = mtd_to_platdev(mtd);
	128	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
	129
	130	while (len--)
	131	*buf++ = __raw_readl(ndfdtr);
	132	}
	133
	134	static int txx9ndfmc_verify_buf(struct mtd_info mtd, const uint8_t buf,
	135	int len)
	136	{
	137	struct platform_device *dev = mtd_to_platdev(mtd);
	138	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
	139
	140	while (len--)
141	if (*buf++ != (uint8_t)__raw_readl(ndfdtr))
142	return -EFAULT;
143	return 0;
144	}
145
146	static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
147	unsigned int ctrl)
148	{
149	struct nand_chip *chip = mtd->priv;
150	struct txx9ndfmc_priv *txx9_priv = chip->priv;
151	struct platform_device *dev = txx9_priv->dev;
152	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
153
154	if (ctrl & NAND_CTRL_CHANGE) {
155	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
156
157	mcr &= ~(TXX9_NDFMCR_CLE \| TXX9_NDFMCR_ALE \| TXX9_NDFMCR_CE);
158	mcr \|= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
159	mcr \|= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
160	/* TXX9_NDFMCR_CE bit is 0:high 1:low */
161	mcr \|= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
162	if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
163	mcr &= ~TXX9_NDFMCR_CS_MASK;
164	mcr \|= TXX9_NDFMCR_CS(txx9_priv->cs);
165	}
166	txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
167	}
168	if (cmd != NAND_CMD_NONE)
169	txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
170	if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
171	/* dummy write to update external latch */
172	if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
173	txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
174	}
175	mmiowb();
176	}
177
178	static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
179	{
180	struct platform_device *dev = mtd_to_platdev(mtd);
181
182	return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
183	}
184
185	static int txx9ndfmc_calculate_ecc(struct mtd_info mtd, const uint8_t dat,
186	uint8_t *ecc_code)
187	{
188	struct platform_device *dev = mtd_to_platdev(mtd);
c0cbfd0e AN	189	struct nand_chip *chip = mtd->priv;
c0cbfd0e AN	190	int eccbytes;
64fb65ba AN	191	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	192
	193	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	194	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	195	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
c0cbfd0e AN	196	for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
	197	ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
	198	ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
	199	ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
	200	ecc_code += 3;
	201	}
64fb65ba AN	202	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	203	return 0;
	204	}
	205
c0cbfd0e AN	206	static int txx9ndfmc_correct_data(struct mtd_info mtd, unsigned char buf,
	207	unsigned char read_ecc, unsigned char calc_ecc)
	208	{
	209	struct nand_chip *chip = mtd->priv;
	210	int eccsize;
	211	int corrected = 0;
	212	int stat;
	213
	214	for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
	215	stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
	216	if (stat < 0)
	217	return stat;
	218	corrected += stat;
	219	buf += 256;
	220	read_ecc += 3;
	221	calc_ecc += 3;
	222	}
	223	return corrected;
	224	}
	225
64fb65ba AN	226	static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
	227	{
	228	struct platform_device *dev = mtd_to_platdev(mtd);
	229	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	230
	231	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	232	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
	233	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	234	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
	235	}
	236
	237	static void txx9ndfmc_initialize(struct platform_device *dev)
	238	{
	239	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
	240	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	241	int tmout = 100;
	242
	243	if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
	244	; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */
	245	else {
	246	/* reset NDFMC */
	247	txx9ndfmc_write(dev,
	248	txx9ndfmc_read(dev, TXX9_NDFRSTR) \|
	249	TXX9_NDFRSTR_RST,
	250	TXX9_NDFRSTR);
	251	while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
	252	if (--tmout == 0) {
	253	dev_err(&dev->dev, "reset failed.\n");
	254	break;
	255	}
	256	udelay(1);
	257	}
	258	}
	259	/* setup Hold Time, Strobe Pulse Width */
	260	txx9ndfmc_write(dev, (drvdata->hold << 4) \| drvdata->spw, TXX9_NDFSPR);
	261	txx9ndfmc_write(dev,
	262	(plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
	263	TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
	264	}
	265
	266	#define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
	267	DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
	268
c0cbfd0e AN	269	static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
	270	{
	271	struct nand_chip *chip = mtd->priv;
	272	int ret;
	273
5e81e88a	274	ret = nand_scan_ident(mtd, 1, NULL);
c0cbfd0e AN	275	if (!ret) {
c0cbfd0e AN	276	if (mtd->writesize >= 512) {
24ac9a94 RR	277	/* Hardware ECC 6 byte ECC per 512 Byte data */
	278	chip->ecc.size = 512;
	279	chip->ecc.bytes = 6;
c0cbfd0e AN	280	}
	281	ret = nand_scan_tail(mtd);
	282	}
	283	return ret;
	284	}
	285
64fb65ba AN	286	static int __init txx9ndfmc_probe(struct platform_device *dev)
	287	{
	288	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
64fb65ba AN	289	int hold, spw;
	290	int i;
	291	struct txx9ndfmc_drvdata *drvdata;
	292	unsigned long gbusclk = plat->gbus_clock;
	293	struct resource *res;
	294
	295	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	296	if (!res)
	297	return -ENODEV;
	298	drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
	299	if (!drvdata)
	300	return -ENOMEM;
	301	if (!devm_request_mem_region(&dev->dev, res->start,
	302	resource_size(res), dev_name(&dev->dev)))
	303	return -EBUSY;
	304	drvdata->base = devm_ioremap(&dev->dev, res->start,
	305	resource_size(res));
	306	if (!drvdata->base)
	307	return -EBUSY;
	308
	309	hold = plat->hold ?: 20; /* tDH */
	310	spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */
	311
	312	hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
	313	spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
	314	if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
	315	hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */
	316	spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */
	317	hold = clamp(hold, 1, 15);
	318	drvdata->hold = hold;
	319	spw = clamp(spw, 1, 15);
	320	drvdata->spw = spw;
	321	dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
	322	(gbusclk + 500000) / 1000000, hold, spw);
	323
	324	spin_lock_init(&drvdata->hw_control.lock);
	325	init_waitqueue_head(&drvdata->hw_control.wq);
	326
	327	platform_set_drvdata(dev, drvdata);
	328	txx9ndfmc_initialize(dev);
	329
	330	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
	331	struct txx9ndfmc_priv *txx9_priv;
	332	struct nand_chip *chip;
	333	struct mtd_info *mtd;
64fb65ba AN	334
	335	if (!(plat->ch_mask & (1 << i)))
	336	continue;
	337	txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
	338	GFP_KERNEL);
	339	if (!txx9_priv) {
	340	dev_err(&dev->dev, "Unable to allocate "
	341	"TXx9 NDFMC MTD device structure.\n");
	342	continue;
	343	}
	344	chip = &txx9_priv->chip;
	345	mtd = &txx9_priv->mtd;
	346	mtd->owner = THIS_MODULE;
	347
	348	mtd->priv = chip;
	349
	350	chip->read_byte = txx9ndfmc_read_byte;
	351	chip->read_buf = txx9ndfmc_read_buf;
	352	chip->write_buf = txx9ndfmc_write_buf;
	353	chip->verify_buf = txx9ndfmc_verify_buf;
	354	chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
	355	chip->dev_ready = txx9ndfmc_dev_ready;
	356	chip->ecc.calculate = txx9ndfmc_calculate_ecc;
c0cbfd0e	357	chip->ecc.correct = txx9ndfmc_correct_data;
64fb65ba AN	358	chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
64fb65ba AN	359	chip->ecc.mode = NAND_ECC_HW;
c0cbfd0e	360	/* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
64fb65ba AN	361	chip->ecc.size = 256;
	362	chip->ecc.bytes = 3;
	363	chip->chip_delay = 100;
	364	chip->controller = &drvdata->hw_control;
	365
	366	chip->priv = txx9_priv;
	367	txx9_priv->dev = dev;
	368
	369	if (plat->ch_mask != 1) {
	370	txx9_priv->cs = i;
81933046 DW	371	txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
81933046 DW	372	dev_name(&dev->dev), i);
64fb65ba AN	373	} else {
64fb65ba AN	374	txx9_priv->cs = -1;
272023df AN	375	txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
	376	GFP_KERNEL);
	377	}
	378	if (!txx9_priv->mtdname) {
	379	kfree(txx9_priv);
	380	dev_err(&dev->dev, "Unable to allocate MTD name.\n");
	381	continue;
64fb65ba AN	382	}
	383	if (plat->wide_mask & (1 << i))
	384	chip->options \|= NAND_BUSWIDTH_16;
	385
c0cbfd0e	386	if (txx9ndfmc_nand_scan(mtd)) {
272023df	387	kfree(txx9_priv->mtdname);
64fb65ba AN	388	kfree(txx9_priv);
	389	continue;
	390	}
	391	mtd->name = txx9_priv->mtdname;
	392
9e58c5d4	393	mtd_device_parse_register(mtd, NULL, 0, NULL, 0);
64fb65ba AN	394	drvdata->mtds[i] = mtd;
	395	}
	396
	397	return 0;
	398	}
	399
	400	static int __exit txx9ndfmc_remove(struct platform_device *dev)
	401	{
	402	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	403	int i;
	404
	405	platform_set_drvdata(dev, NULL);
	406	if (!drvdata)
	407	return 0;
	408	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
	409	struct mtd_info *mtd = drvdata->mtds[i];
	410	struct nand_chip *chip;
	411	struct txx9ndfmc_priv *txx9_priv;
	412
	413	if (!mtd)
	414	continue;
	415	chip = mtd->priv;
	416	txx9_priv = chip->priv;
	417
6eb4feff	418	nand_release(mtd);
272023df	419	kfree(txx9_priv->mtdname);
64fb65ba AN	420	kfree(txx9_priv);
	421	}
	422	return 0;
	423	}
	424
	425	#ifdef CONFIG_PM
	426	static int txx9ndfmc_resume(struct platform_device *dev)
	427	{
	428	if (platform_get_drvdata(dev))
	429	txx9ndfmc_initialize(dev);
	430	return 0;
	431	}
	432	#else
	433	#define txx9ndfmc_resume NULL
	434	#endif
	435
	436	static struct platform_driver txx9ndfmc_driver = {
	437	.remove = __exit_p(txx9ndfmc_remove),
	438	.resume = txx9ndfmc_resume,
	439	.driver = {
	440	.name = "txx9ndfmc",
	441	.owner = THIS_MODULE,
	442	},
	443	};
	444
	445	static int __init txx9ndfmc_init(void)
	446	{
	447	return platform_driver_probe(&txx9ndfmc_driver, txx9ndfmc_probe);
	448	}
	449
	450	static void __exit txx9ndfmc_exit(void)
	451	{
	452	platform_driver_unregister(&txx9ndfmc_driver);
	453	}
	454
	455	module_init(txx9ndfmc_init);
	456	module_exit(txx9ndfmc_exit);
	457
	458	MODULE_LICENSE("GPL");
	459	MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
	460	MODULE_ALIAS("platform:txx9ndfmc");