[deliverable/linux.git] / drivers / mtd / nand / xway_nand.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 *  Copyright © 2012 John Crispin <blogic@openwrt.org>
 */

#include <linux/mtd/nand.h>
#include <linux/of_gpio.h>
#include <linux/of_platform.h>

#include <lantiq_soc.h>

/* nand registers */
#define EBU_ADDSEL1		0x24
#define EBU_NAND_CON		0xB0
#define EBU_NAND_WAIT		0xB4
#define  NAND_WAIT_RD		BIT(0) /* NAND flash status output */
#define  NAND_WAIT_WR_C		BIT(3) /* NAND Write/Read complete */
#define EBU_NAND_ECC0		0xB8
#define EBU_NAND_ECC_AC		0xBC

/*
 * nand commands
 * The pins of the NAND chip are selected based on the address bits of the
 * "register" read and write. There are no special registers, but an
 * address range and the lower address bits are used to activate the
 * correct line. For example when the bit (1 << 2) is set in the address
 * the ALE pin will be activated.
 */
#define NAND_CMD_ALE		BIT(2) /* address latch enable */
#define NAND_CMD_CLE		BIT(3) /* command latch enable */
#define NAND_CMD_CS		BIT(4) /* chip select */
#define NAND_CMD_SE		BIT(5) /* spare area access latch */
#define NAND_CMD_WP		BIT(6) /* write protect */
#define NAND_WRITE_CMD_RESET	0xff
#define NAND_WRITE_CMD		(NAND_CMD_CS | NAND_CMD_CLE)
#define NAND_WRITE_ADDR		(NAND_CMD_CS | NAND_CMD_ALE)
#define NAND_WRITE_DATA		(NAND_CMD_CS)
#define NAND_READ_DATA		(NAND_CMD_CS)

/* we need to tel the ebu which addr we mapped the nand to */
#define ADDSEL1_MASK(x)		(x << 4)
#define ADDSEL1_REGEN		1

/* we need to tell the EBU that we have nand attached and set it up properly */
#define BUSCON1_SETUP		(1 << 22)
#define BUSCON1_BCGEN_RES	(0x3 << 12)
#define BUSCON1_WAITWRC2	(2 << 8)
#define BUSCON1_WAITRDC2	(2 << 6)
#define BUSCON1_HOLDC1		(1 << 4)
#define BUSCON1_RECOVC1		(1 << 2)
#define BUSCON1_CMULT4		1

#define NAND_CON_CE		(1 << 20)
#define NAND_CON_OUT_CS1	(1 << 10)
#define NAND_CON_IN_CS1		(1 << 8)
#define NAND_CON_PRE_P		(1 << 7)
#define NAND_CON_WP_P		(1 << 6)
#define NAND_CON_SE_P		(1 << 5)
#define NAND_CON_CS_P		(1 << 4)
#define NAND_CON_CSMUX		(1 << 1)
#define NAND_CON_NANDM		1

static void xway_reset_chip(struct nand_chip *chip)
{
	unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
	unsigned long flags;

	nandaddr &= ~NAND_WRITE_ADDR;
	nandaddr |= NAND_WRITE_CMD;

	/* finish with a reset */
	spin_lock_irqsave(&ebu_lock, flags);
	writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
		;
	spin_unlock_irqrestore(&ebu_lock, flags);
}

static void xway_select_chip(struct mtd_info *mtd, int chip)
{

	switch (chip) {
	case -1:
		ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
		ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
		break;
	case 0:
		ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
		ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
		break;
	default:
		BUG();
	}
}

static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *this = mtd_to_nand(mtd);
	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
	unsigned long flags;

	if (ctrl & NAND_CTRL_CHANGE) {
		nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
		if (ctrl & NAND_CLE)
			nandaddr |= NAND_WRITE_CMD;
		else
			nandaddr |= NAND_WRITE_ADDR;
		this->IO_ADDR_W = (void __iomem *) nandaddr;
	}

	if (cmd != NAND_CMD_NONE) {
		spin_lock_irqsave(&ebu_lock, flags);
		writeb(cmd, this->IO_ADDR_W);
		while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
			;
		spin_unlock_irqrestore(&ebu_lock, flags);
	}
}

static int xway_dev_ready(struct mtd_info *mtd)
{
	return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
}

static unsigned char xway_read_byte(struct mtd_info *mtd)
{
	struct nand_chip *this = mtd_to_nand(mtd);
	unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&ebu_lock, flags);
	ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA));
	spin_unlock_irqrestore(&ebu_lock, flags);

	return ret;
}

static int xway_nand_probe(struct platform_device *pdev)
{
	struct nand_chip *this = platform_get_drvdata(pdev);
	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
	const __be32 *cs = of_get_property(pdev->dev.of_node,
					"lantiq,cs", NULL);
	u32 cs_flag = 0;

	/* load our CS from the DT. Either we find a valid 1 or default to 0 */
	if (cs && (*cs == 1))
		cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;

	/* setup the EBU to run in NAND mode on our base addr */
	ltq_ebu_w32(CPHYSADDR(nandaddr)
		| ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);

	ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
		| BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
		| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);

	ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
		| NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
		| cs_flag, EBU_NAND_CON);

	/* finish with a reset */
	xway_reset_chip(this);

	return 0;
}

static struct platform_nand_data xway_nand_data = {
	.chip = {
		.nr_chips		= 1,
		.chip_delay		= 30,
	},
	.ctrl = {
		.probe		= xway_nand_probe,
		.cmd_ctrl	= xway_cmd_ctrl,
		.dev_ready	= xway_dev_ready,
		.select_chip	= xway_select_chip,
		.read_byte	= xway_read_byte,
	}
};

/*
 * Try to find the node inside the DT. If it is available attach out
 * platform_nand_data
 */
static int __init xway_register_nand(void)
{
	struct device_node *node;
	struct platform_device *pdev;

	node = of_find_compatible_node(NULL, NULL, "lantiq,nand-xway");
	if (!node)
		return -ENOENT;
	pdev = of_find_device_by_node(node);
	if (!pdev)
		return -EINVAL;
	pdev->dev.platform_data = &xway_nand_data;
	of_node_put(node);
	return 0;
}

subsys_initcall(xway_register_nand);
Commit	Line	Data
99f2b107 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Copyright © 2012 John Crispin <blogic@openwrt.org>
	7	*/
	8
	9	#include <linux/mtd/nand.h>
	10	#include <linux/of_gpio.h>
	11	#include <linux/of_platform.h>
	12
	13	#include <lantiq_soc.h>
	14
	15	/* nand registers */
	16	#define EBU_ADDSEL1 0x24
	17	#define EBU_NAND_CON 0xB0
	18	#define EBU_NAND_WAIT 0xB4
3d8cec22 HM	19	#define NAND_WAIT_RD BIT(0) /* NAND flash status output */
3d8cec22 HM	20	#define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
99f2b107 JC	21	#define EBU_NAND_ECC0 0xB8
	22	#define EBU_NAND_ECC_AC 0xBC
	23
3d8cec22 HM	24	/*
	25	* nand commands
	26	* The pins of the NAND chip are selected based on the address bits of the
	27	* "register" read and write. There are no special registers, but an
	28	* address range and the lower address bits are used to activate the
	29	* correct line. For example when the bit (1 << 2) is set in the address
	30	* the ALE pin will be activated.
	31	*/
	32	#define NAND_CMD_ALE BIT(2) /* address latch enable */
	33	#define NAND_CMD_CLE BIT(3) /* command latch enable */
	34	#define NAND_CMD_CS BIT(4) /* chip select */
	35	#define NAND_CMD_SE BIT(5) /* spare area access latch */
	36	#define NAND_CMD_WP BIT(6) /* write protect */
99f2b107 JC	37	#define NAND_WRITE_CMD_RESET 0xff
	38	#define NAND_WRITE_CMD (NAND_CMD_CS \| NAND_CMD_CLE)
	39	#define NAND_WRITE_ADDR (NAND_CMD_CS \| NAND_CMD_ALE)
	40	#define NAND_WRITE_DATA (NAND_CMD_CS)
	41	#define NAND_READ_DATA (NAND_CMD_CS)
99f2b107 JC	42
	43	/* we need to tel the ebu which addr we mapped the nand to */
	44	#define ADDSEL1_MASK(x) (x << 4)
	45	#define ADDSEL1_REGEN 1
	46
	47	/* we need to tell the EBU that we have nand attached and set it up properly */
	48	#define BUSCON1_SETUP (1 << 22)
	49	#define BUSCON1_BCGEN_RES (0x3 << 12)
	50	#define BUSCON1_WAITWRC2 (2 << 8)
	51	#define BUSCON1_WAITRDC2 (2 << 6)
	52	#define BUSCON1_HOLDC1 (1 << 4)
	53	#define BUSCON1_RECOVC1 (1 << 2)
	54	#define BUSCON1_CMULT4 1
	55
	56	#define NAND_CON_CE (1 << 20)
	57	#define NAND_CON_OUT_CS1 (1 << 10)
	58	#define NAND_CON_IN_CS1 (1 << 8)
	59	#define NAND_CON_PRE_P (1 << 7)
	60	#define NAND_CON_WP_P (1 << 6)
	61	#define NAND_CON_SE_P (1 << 5)
	62	#define NAND_CON_CS_P (1 << 4)
	63	#define NAND_CON_CSMUX (1 << 1)
	64	#define NAND_CON_NANDM 1
	65
	66	static void xway_reset_chip(struct nand_chip *chip)
	67	{
	68	unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
	69	unsigned long flags;
	70
	71	nandaddr &= ~NAND_WRITE_ADDR;
	72	nandaddr \|= NAND_WRITE_CMD;
	73
	74	/* finish with a reset */
	75	spin_lock_irqsave(&ebu_lock, flags);
	76	writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
	77	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
	78	;
	79	spin_unlock_irqrestore(&ebu_lock, flags);
	80	}
	81
	82	static void xway_select_chip(struct mtd_info *mtd, int chip)
	83	{
	84
	85	switch (chip) {
	86	case -1:
	87	ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
	88	ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
	89	break;
	90	case 0:
	91	ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
	92	ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
	93	break;
	94	default:
	95	BUG();
	96	}
	97	}
	98
	99	static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	100	{
4bd4ebcc	101	struct nand_chip *this = mtd_to_nand(mtd);
99f2b107 JC	102	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
	103	unsigned long flags;
	104
	105	if (ctrl & NAND_CTRL_CHANGE) {
	106	nandaddr &= ~(NAND_WRITE_CMD \| NAND_WRITE_ADDR);
	107	if (ctrl & NAND_CLE)
	108	nandaddr \|= NAND_WRITE_CMD;
	109	else
	110	nandaddr \|= NAND_WRITE_ADDR;
	111	this->IO_ADDR_W = (void __iomem *) nandaddr;
	112	}
	113
	114	if (cmd != NAND_CMD_NONE) {
	115	spin_lock_irqsave(&ebu_lock, flags);
	116	writeb(cmd, this->IO_ADDR_W);
	117	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
	118	;
	119	spin_unlock_irqrestore(&ebu_lock, flags);
	120	}
	121	}
	122
	123	static int xway_dev_ready(struct mtd_info *mtd)
	124	{
	125	return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
	126	}
	127
	128	static unsigned char xway_read_byte(struct mtd_info *mtd)
	129	{
4bd4ebcc	130	struct nand_chip *this = mtd_to_nand(mtd);
99f2b107 JC	131	unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
	132	unsigned long flags;
	133	int ret;
	134
	135	spin_lock_irqsave(&ebu_lock, flags);
	136	ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA));
	137	spin_unlock_irqrestore(&ebu_lock, flags);
	138
	139	return ret;
	140	}
	141
	142	static int xway_nand_probe(struct platform_device *pdev)
	143	{
	144	struct nand_chip *this = platform_get_drvdata(pdev);
	145	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
	146	const __be32 *cs = of_get_property(pdev->dev.of_node,
	147	"lantiq,cs", NULL);
	148	u32 cs_flag = 0;
	149
	150	/* load our CS from the DT. Either we find a valid 1 or default to 0 */
	151	if (cs && (*cs == 1))
	152	cs_flag = NAND_CON_IN_CS1 \| NAND_CON_OUT_CS1;
	153
	154	/* setup the EBU to run in NAND mode on our base addr */
	155	ltq_ebu_w32(CPHYSADDR(nandaddr)
	156	\| ADDSEL1_MASK(3) \| ADDSEL1_REGEN, EBU_ADDSEL1);
	157
	158	ltq_ebu_w32(BUSCON1_SETUP \| BUSCON1_BCGEN_RES \| BUSCON1_WAITWRC2
	159	\| BUSCON1_WAITRDC2 \| BUSCON1_HOLDC1 \| BUSCON1_RECOVC1
	160	\| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
	161
	162	ltq_ebu_w32(NAND_CON_NANDM \| NAND_CON_CSMUX \| NAND_CON_CS_P
	163	\| NAND_CON_SE_P \| NAND_CON_WP_P \| NAND_CON_PRE_P
	164	\| cs_flag, EBU_NAND_CON);
	165
	166	/* finish with a reset */
	167	xway_reset_chip(this);
	168
	169	return 0;
	170	}
	171
99f2b107 JC	172	static struct platform_nand_data xway_nand_data = {
	173	.chip = {
	174	.nr_chips = 1,
	175	.chip_delay = 30,
99f2b107 JC	176	},
	177	.ctrl = {
	178	.probe = xway_nand_probe,
	179	.cmd_ctrl = xway_cmd_ctrl,
	180	.dev_ready = xway_dev_ready,
	181	.select_chip = xway_select_chip,
	182	.read_byte = xway_read_byte,
	183	}
	184	};
	185
	186	/*
	187	* Try to find the node inside the DT. If it is available attach out
	188	* platform_nand_data
	189	*/
	190	static int __init xway_register_nand(void)
	191	{
	192	struct device_node *node;
	193	struct platform_device *pdev;
	194
	195	node = of_find_compatible_node(NULL, NULL, "lantiq,nand-xway");
	196	if (!node)
	197	return -ENOENT;
	198	pdev = of_find_device_by_node(node);
	199	if (!pdev)
	200	return -EINVAL;
	201	pdev->dev.platform_data = &xway_nand_data;
	202	of_node_put(node);
	203	return 0;
	204	}
	205
	206	subsys_initcall(xway_register_nand);