[deliverable/linux.git] / drivers / mtd / nand / xway_nand.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 *  Copyright © 2012 John Crispin <blogic@openwrt.org>
 *  Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
 */

#include <linux/mtd/nand.h>
#include <linux/of_gpio.h>
#include <linux/of_platform.h>

#include <lantiq_soc.h>

/* nand registers */
#define EBU_ADDSEL1		0x24
#define EBU_NAND_CON		0xB0
#define EBU_NAND_WAIT		0xB4
#define  NAND_WAIT_RD		BIT(0) /* NAND flash status output */
#define  NAND_WAIT_WR_C		BIT(3) /* NAND Write/Read complete */
#define EBU_NAND_ECC0		0xB8
#define EBU_NAND_ECC_AC		0xBC

/*
 * nand commands
 * The pins of the NAND chip are selected based on the address bits of the
 * "register" read and write. There are no special registers, but an
 * address range and the lower address bits are used to activate the
 * correct line. For example when the bit (1 << 2) is set in the address
 * the ALE pin will be activated.
 */
#define NAND_CMD_ALE		BIT(2) /* address latch enable */
#define NAND_CMD_CLE		BIT(3) /* command latch enable */
#define NAND_CMD_CS		BIT(4) /* chip select */
#define NAND_CMD_SE		BIT(5) /* spare area access latch */
#define NAND_CMD_WP		BIT(6) /* write protect */
#define NAND_WRITE_CMD		(NAND_CMD_CS | NAND_CMD_CLE)
#define NAND_WRITE_ADDR		(NAND_CMD_CS | NAND_CMD_ALE)
#define NAND_WRITE_DATA		(NAND_CMD_CS)
#define NAND_READ_DATA		(NAND_CMD_CS)

/* we need to tel the ebu which addr we mapped the nand to */
#define ADDSEL1_MASK(x)		(x << 4)
#define ADDSEL1_REGEN		1

/* we need to tell the EBU that we have nand attached and set it up properly */
#define BUSCON1_SETUP		(1 << 22)
#define BUSCON1_BCGEN_RES	(0x3 << 12)
#define BUSCON1_WAITWRC2	(2 << 8)
#define BUSCON1_WAITRDC2	(2 << 6)
#define BUSCON1_HOLDC1		(1 << 4)
#define BUSCON1_RECOVC1		(1 << 2)
#define BUSCON1_CMULT4		1

#define NAND_CON_CE		(1 << 20)
#define NAND_CON_OUT_CS1	(1 << 10)
#define NAND_CON_IN_CS1		(1 << 8)
#define NAND_CON_PRE_P		(1 << 7)
#define NAND_CON_WP_P		(1 << 6)
#define NAND_CON_SE_P		(1 << 5)
#define NAND_CON_CS_P		(1 << 4)
#define NAND_CON_CSMUX		(1 << 1)
#define NAND_CON_NANDM		1

struct xway_nand_data {
	struct nand_chip	chip;
	unsigned long		csflags;
};

static u8 xway_readb(struct mtd_info *mtd, int op)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	void __iomem *nandaddr = chip->IO_ADDR_R;

	return readb(nandaddr + op);
}

static void xway_writeb(struct mtd_info *mtd, int op, u8 value)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	void __iomem *nandaddr = chip->IO_ADDR_W;

	writeb(value, nandaddr + op);
}

static void xway_select_chip(struct mtd_info *mtd, int select)
{
	struct nand_chip *chip = mtd_to_nand(mtd);
	struct xway_nand_data *data = nand_get_controller_data(chip);

	switch (select) {
	case -1:
		ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
		ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
		spin_unlock_irqrestore(&ebu_lock, data->csflags);
		break;
	case 0:
		spin_lock_irqsave(&ebu_lock, data->csflags);
		ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
		ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
		break;
	default:
		BUG();
	}
}

static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		xway_writeb(mtd, NAND_WRITE_CMD, cmd);
	else if (ctrl & NAND_ALE)
		xway_writeb(mtd, NAND_WRITE_ADDR, cmd);

	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
		;
}

static int xway_dev_ready(struct mtd_info *mtd)
{
	return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
}

static unsigned char xway_read_byte(struct mtd_info *mtd)
{
	return xway_readb(mtd, NAND_READ_DATA);
}

/*
 * Probe for the NAND device.
 */
static int xway_nand_probe(struct platform_device *pdev)
{
	struct xway_nand_data *data;
	struct mtd_info *mtd;
	struct resource *res;
	int err;
	void __iomem *nandaddr;
	u32 cs;
	u32 cs_flag = 0;

	/* Allocate memory for the device structure (and zero it) */
	data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
			    GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	nandaddr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(nandaddr))
		return PTR_ERR(nandaddr);

	nand_set_flash_node(&data->chip, pdev->dev.of_node);
	mtd = nand_to_mtd(&data->chip);
	mtd->dev.parent = &pdev->dev;

	data->chip.IO_ADDR_R = nandaddr;
	data->chip.IO_ADDR_W = nandaddr;
	data->chip.cmd_ctrl = xway_cmd_ctrl;
	data->chip.dev_ready = xway_dev_ready;
	data->chip.select_chip = xway_select_chip;
	data->chip.read_byte = xway_read_byte;
	data->chip.chip_delay = 30;

	data->chip.ecc.mode = NAND_ECC_SOFT;
	data->chip.ecc.algo = NAND_ECC_HAMMING;

	platform_set_drvdata(pdev, data);
	nand_set_controller_data(&data->chip, data);

	/* load our CS from the DT. Either we find a valid 1 or default to 0 */
	err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs);
	if (!err && cs == 1)
		cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;

	/* setup the EBU to run in NAND mode on our base addr */
	ltq_ebu_w32(CPHYSADDR(nandaddr)
		| ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);

	ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
		| BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
		| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);

	ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
		| NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
		| cs_flag, EBU_NAND_CON);

	/* Scan to find existence of the device */
	err = nand_scan(mtd, 1);
	if (err)
		return err;

	err = mtd_device_register(mtd, NULL, 0);
	if (err)
		nand_release(mtd);

	return err;
}

/*
 * Remove a NAND device.
 */
static int xway_nand_remove(struct platform_device *pdev)
{
	struct xway_nand_data *data = platform_get_drvdata(pdev);

	nand_release(nand_to_mtd(&data->chip));

	return 0;
}

static const struct of_device_id xway_nand_match[] = {
	{ .compatible = "lantiq,nand-xway" },
	{},
};
MODULE_DEVICE_TABLE(of, xway_nand_match);

static struct platform_driver xway_nand_driver = {
	.probe	= xway_nand_probe,
	.remove	= xway_nand_remove,
	.driver	= {
		.name		= "lantiq,nand-xway",
		.of_match_table = xway_nand_match,
	},
};

module_platform_driver(xway_nand_driver);

MODULE_LICENSE("GPL");
Commit	Line	Data
99f2b107 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Copyright © 2012 John Crispin <blogic@openwrt.org>
02436675	7	* Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
99f2b107 JC	8	*/
	9
	10	#include <linux/mtd/nand.h>
	11	#include <linux/of_gpio.h>
	12	#include <linux/of_platform.h>
	13
	14	#include <lantiq_soc.h>
	15
	16	/* nand registers */
	17	#define EBU_ADDSEL1 0x24
	18	#define EBU_NAND_CON 0xB0
	19	#define EBU_NAND_WAIT 0xB4
3d8cec22 HM	20	#define NAND_WAIT_RD BIT(0) /* NAND flash status output */
3d8cec22 HM	21	#define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
99f2b107 JC	22	#define EBU_NAND_ECC0 0xB8
	23	#define EBU_NAND_ECC_AC 0xBC
	24
3d8cec22 HM	25	/*
	26	* nand commands
	27	* The pins of the NAND chip are selected based on the address bits of the
	28	* "register" read and write. There are no special registers, but an
	29	* address range and the lower address bits are used to activate the
	30	* correct line. For example when the bit (1 << 2) is set in the address
	31	* the ALE pin will be activated.
	32	*/
	33	#define NAND_CMD_ALE BIT(2) /* address latch enable */
	34	#define NAND_CMD_CLE BIT(3) /* command latch enable */
	35	#define NAND_CMD_CS BIT(4) /* chip select */
	36	#define NAND_CMD_SE BIT(5) /* spare area access latch */
	37	#define NAND_CMD_WP BIT(6) /* write protect */
99f2b107 JC	38	#define NAND_WRITE_CMD (NAND_CMD_CS \| NAND_CMD_CLE)
	39	#define NAND_WRITE_ADDR (NAND_CMD_CS \| NAND_CMD_ALE)
	40	#define NAND_WRITE_DATA (NAND_CMD_CS)
	41	#define NAND_READ_DATA (NAND_CMD_CS)
99f2b107 JC	42
	43	/* we need to tel the ebu which addr we mapped the nand to */
	44	#define ADDSEL1_MASK(x) (x << 4)
	45	#define ADDSEL1_REGEN 1
	46
	47	/* we need to tell the EBU that we have nand attached and set it up properly */
	48	#define BUSCON1_SETUP (1 << 22)
	49	#define BUSCON1_BCGEN_RES (0x3 << 12)
	50	#define BUSCON1_WAITWRC2 (2 << 8)
	51	#define BUSCON1_WAITRDC2 (2 << 6)
	52	#define BUSCON1_HOLDC1 (1 << 4)
	53	#define BUSCON1_RECOVC1 (1 << 2)
	54	#define BUSCON1_CMULT4 1
	55
	56	#define NAND_CON_CE (1 << 20)
	57	#define NAND_CON_OUT_CS1 (1 << 10)
	58	#define NAND_CON_IN_CS1 (1 << 8)
	59	#define NAND_CON_PRE_P (1 << 7)
	60	#define NAND_CON_WP_P (1 << 6)
	61	#define NAND_CON_SE_P (1 << 5)
	62	#define NAND_CON_CS_P (1 << 4)
	63	#define NAND_CON_CSMUX (1 << 1)
	64	#define NAND_CON_NANDM 1
	65
02436675 HM	66	struct xway_nand_data {
02436675 HM	67	struct nand_chip chip;
e7e1f7be	68	unsigned long csflags;
02436675 HM	69	};
02436675 HM	70
ddbed9c2 HM	71	static u8 xway_readb(struct mtd_info *mtd, int op)
	72	{
	73	struct nand_chip *chip = mtd_to_nand(mtd);
	74	void __iomem *nandaddr = chip->IO_ADDR_R;
	75
	76	return readb(nandaddr + op);
	77	}
	78
	79	static void xway_writeb(struct mtd_info *mtd, int op, u8 value)
	80	{
	81	struct nand_chip *chip = mtd_to_nand(mtd);
	82	void __iomem *nandaddr = chip->IO_ADDR_W;
	83
	84	writeb(value, nandaddr + op);
	85	}
	86
e7e1f7be	87	static void xway_select_chip(struct mtd_info *mtd, int select)
99f2b107	88	{
e7e1f7be JC	89	struct nand_chip *chip = mtd_to_nand(mtd);
e7e1f7be JC	90	struct xway_nand_data *data = nand_get_controller_data(chip);
99f2b107	91
e7e1f7be	92	switch (select) {
99f2b107 JC	93	case -1:
	94	ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
	95	ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
e7e1f7be	96	spin_unlock_irqrestore(&ebu_lock, data->csflags);
99f2b107 JC	97	break;
99f2b107 JC	98	case 0:
e7e1f7be	99	spin_lock_irqsave(&ebu_lock, data->csflags);
99f2b107 JC	100	ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
	101	ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
	102	break;
	103	default:
	104	BUG();
	105	}
	106	}
	107
	108	static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	109	{
f45eb7b5 JC	110	if (cmd == NAND_CMD_NONE)
f45eb7b5 JC	111	return;
99f2b107	112
f45eb7b5	113	if (ctrl & NAND_CLE)
ddbed9c2	114	xway_writeb(mtd, NAND_WRITE_CMD, cmd);
f45eb7b5	115	else if (ctrl & NAND_ALE)
ddbed9c2	116	xway_writeb(mtd, NAND_WRITE_ADDR, cmd);
f45eb7b5 JC	117
	118	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
	119	;
99f2b107 JC	120	}
	121
	122	static int xway_dev_ready(struct mtd_info *mtd)
	123	{
	124	return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
	125	}
	126
	127	static unsigned char xway_read_byte(struct mtd_info *mtd)
	128	{
ddbed9c2	129	return xway_readb(mtd, NAND_READ_DATA);
99f2b107 JC	130	}
99f2b107 JC	131
02436675 HM	132	/*
	133	* Probe for the NAND device.
	134	*/
99f2b107 JC	135	static int xway_nand_probe(struct platform_device *pdev)
99f2b107 JC	136	{
02436675 HM	137	struct xway_nand_data *data;
	138	struct mtd_info *mtd;
	139	struct resource *res;
	140	int err;
	141	void __iomem *nandaddr;
	142	u32 cs;
99f2b107 JC	143	u32 cs_flag = 0;
99f2b107 JC	144
02436675 HM	145	/* Allocate memory for the device structure (and zero it) */
	146	data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
	147	GFP_KERNEL);
	148	if (!data)
	149	return -ENOMEM;
	150
	151	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	152	nandaddr = devm_ioremap_resource(&pdev->dev, res);
	153	if (IS_ERR(nandaddr))
	154	return PTR_ERR(nandaddr);
	155
	156	nand_set_flash_node(&data->chip, pdev->dev.of_node);
	157	mtd = nand_to_mtd(&data->chip);
	158	mtd->dev.parent = &pdev->dev;
	159
	160	data->chip.IO_ADDR_R = nandaddr;
	161	data->chip.IO_ADDR_W = nandaddr;
	162	data->chip.cmd_ctrl = xway_cmd_ctrl;
	163	data->chip.dev_ready = xway_dev_ready;
	164	data->chip.select_chip = xway_select_chip;
	165	data->chip.read_byte = xway_read_byte;
	166	data->chip.chip_delay = 30;
	167
	168	data->chip.ecc.mode = NAND_ECC_SOFT;
	169	data->chip.ecc.algo = NAND_ECC_HAMMING;
	170
	171	platform_set_drvdata(pdev, data);
	172	nand_set_controller_data(&data->chip, data);
	173
99f2b107	174	/* load our CS from the DT. Either we find a valid 1 or default to 0 */
02436675 HM	175	err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs);
02436675 HM	176	if (!err && cs == 1)
99f2b107 JC	177	cs_flag = NAND_CON_IN_CS1 \| NAND_CON_OUT_CS1;
	178
	179	/* setup the EBU to run in NAND mode on our base addr */
	180	ltq_ebu_w32(CPHYSADDR(nandaddr)
	181	\| ADDSEL1_MASK(3) \| ADDSEL1_REGEN, EBU_ADDSEL1);
	182
	183	ltq_ebu_w32(BUSCON1_SETUP \| BUSCON1_BCGEN_RES \| BUSCON1_WAITWRC2
	184	\| BUSCON1_WAITRDC2 \| BUSCON1_HOLDC1 \| BUSCON1_RECOVC1
	185	\| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
	186
	187	ltq_ebu_w32(NAND_CON_NANDM \| NAND_CON_CSMUX \| NAND_CON_CS_P
	188	\| NAND_CON_SE_P \| NAND_CON_WP_P \| NAND_CON_PRE_P
	189	\| cs_flag, EBU_NAND_CON);
	190
02436675 HM	191	/* Scan to find existence of the device */
	192	err = nand_scan(mtd, 1);
	193	if (err)
	194	return err;
99f2b107	195
02436675 HM	196	err = mtd_device_register(mtd, NULL, 0);
	197	if (err)
	198	nand_release(mtd);
	199
	200	return err;
	201	}
99f2b107 JC	202
99f2b107 JC	203	/*
02436675	204	* Remove a NAND device.
99f2b107	205	*/
02436675	206	static int xway_nand_remove(struct platform_device *pdev)
99f2b107	207	{
02436675 HM	208	struct xway_nand_data *data = platform_get_drvdata(pdev);
	209
	210	nand_release(nand_to_mtd(&data->chip));
	211
99f2b107 JC	212	return 0;
	213	}
	214
02436675 HM	215	static const struct of_device_id xway_nand_match[] = {
	216	{ .compatible = "lantiq,nand-xway" },
	217	{},
	218	};
	219	MODULE_DEVICE_TABLE(of, xway_nand_match);
	220
	221	static struct platform_driver xway_nand_driver = {
	222	.probe = xway_nand_probe,
	223	.remove = xway_nand_remove,
	224	.driver = {
	225	.name = "lantiq,nand-xway",
	226	.of_match_table = xway_nand_match,
	227	},
	228	};
	229
	230	module_platform_driver(xway_nand_driver);
	231
	232	MODULE_LICENSE("GPL");